PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 8 -- 26 November 2014 Product data sheet 1. General description The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity inversion register. All registers can be read by the system master. The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and a different address range. The PCA9539; PCA9539R open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. In the PCA9539, the RESET pin causes the same reset/default I/O input configuration to occur without de-powering the device, holding the registers and I2C-bus state machine in their default state until the RESET input is once again HIGH. This input requires a pull-up to VDD. In the PCA9539R however, only the device state machine is initialized by the RESET pin and the internal general-purpose registers remain unchanged. Using the PCA9539R RESET pin will only reset the I2C-bus interface should it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I2C-bus is being restored. Two hardware pins (A0, A1) vary the fixed I2C-bus address and allow up to four devices to share the same I2C-bus/SMBus. 2. Features and benefits 16-bit I2C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9539PW/Q900) 5 V tolerant I/Os PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Polarity inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in three different packages: SO24, TSSOP24, and HVQFN24 3. Ordering information Table 1. Ordering information Type number Topside marking Package PCA9539BS 9539 539R HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm SOT616-1 PCA9539RBS PCA9539D PCA9539D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 PCA9539PW PCA9539PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 PCA9539PW/Q900[1] PCA9539PW PCA9539RPW PA9539RPW [1] Name Description Version PCA9539PW/Q900 is AEC-Q100 compliant. Contact I2C.support@nxp.com for PPAP. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum Temperature order quantity PCA9539BS PCA9539BS,115 HVQFN24 Reel 7" Q1/T1 *standard mark SMD[1] 1500 Tamb = 40 C to +85 C PCA9539BS,118 HVQFN24 Reel 13" Q1/T1 *standard mark SMD[1] 6000 Tamb = 40 C to +85 C PCA9539BSHP HVQFN24 Reel 13" Q2/T3 *standard mark SMD[2] 6000 Tamb = 40 C to +85 C PCA9539RBS,118 HVQFN24 Reel 13" Q1/T1 *standard mark SMD[1] 6000 Tamb = 40 C to +85 C PCA9539RBS PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 2 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 2. Ordering options ...continued Type number Orderable part number Package Packing method Minimum Temperature order quantity PCA9539D PCA9539D,112 SO24 Standard marking * IC's tube DSC bulk pack 1200 Tamb = 40 C to +85 C PCA9539D,118 SO24 Reel 13" Q1/T1 *standard mark SMD[1] 1000 Tamb = 40 C to +85 C PCA9539PW,112 TSSOP24 Standard marking * IC's tube DSC bulk pack 1575 Tamb = 40 C to +85 C PCA9539PW,118 TSSOP24 Reel 13" Q1/T1 *standard mark SMD[1] 2500 Tamb = 40 C to +85 C PCA9539PW/Q900 PCA9539PW/Q900,118 TSSOP24 Reel 13" Q1/T1 *standard mark SMD[1] 2500 Tamb = 40 C to +125 C PCA9539RPW Reel 13" Q1/T1 *standard mark SMD[1] 2500 Tamb = 40 C to +85 C PCA9539PW PCA9539RPW,118 [1] Pin 1 in Quadrant 1; see Figure 2. [2] Pin 1 in Quadrant 2; see Figure 3. TSSOP24 3.1.1 Pin 1 quadrant indication way into the reel Q1 Q2 Q3 Q4 Quadrant designations Q1 = upper left Q2 = upper right Q3 = lower left Q4 = lower right round sprocket holes aaa-010180 Fig 1. Fig 2. PCA9539_PCA9539R Product data sheet Carrier tape pin 1 quadrant designations SLQ SLQ DDD DDD Pin 1 in Q1 Fig 3. All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 Pin 1 in Q2 (c) NXP Semiconductors N.V. 2014. All rights reserved. 3 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 4. Block diagram PCA9539 PCA9539R IO1_0 IO1_1 8-bit A0 A1 write pulse IO1_2 INPUT/ OUTPUT PORTS IO1_3 IO1_4 IO1_5 IO1_6 read pulse IO1_7 I2C-BUS/SMBus CONTROL SCL SDA IO0_0 INPUT FILTER IO0_1 8-bit write pulse VDD RESET IO0_2 INPUT/ OUTPUT PORTS IO0_4 IO0_5 IO0_6 read pulse IO0_7 POWER-ON RESET VSS IO0_3 VDD LP FILTER INT 002aad722 Remark: All I/Os are set to inputs at reset. Fig 4. PCA9539_PCA9539R Product data sheet Block diagram of PCA9539; PCA9539R All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 4 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5. Pinning information 5.1 Pinning INT 1 24 VDD INT 1 A1 2 23 SDA A1 2 24 VDD 23 SDA RESET 3 22 SCL RESET 3 22 SCL IO0_0 4 21 A0 IO0_0 4 21 A0 IO0_1 5 20 IO1_7 IO0_1 5 IO0_2 6 19 IO1_6 IO0_2 6 IO0_3 7 18 IO1_5 IO0_3 7 IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4 IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3 IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2 IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1 VSS 12 13 IO1_0 VSS 12 13 IO1_0 PCA9539D 20 IO1_7 PCA9539PW PCA9539PW/Q900 PCA9539RPW 002aad719 Fig 5. 19 IO1_6 18 IO1_5 002aad720 Pin configuration for SO24 Fig 6. Pin configuration for TSSOP24 19 SCL 20 SDA 21 VDD 22 INT terminal 1 index area 23 A1 24 RESET PCA9539BS PCA9539RBS 14 IO1_4 IO0_5 6 13 IO1_3 IO1_2 12 5 IO1_1 11 15 IO1_5 IO0_4 IO1_0 10 4 9 16 IO1_6 IO0_3 VSS 3 8 17 IO1_7 IO0_2 7 18 A0 2 IO0_7 1 IO0_1 IO0_6 IO0_0 002aad721 Transparent top view Fig 7. PCA9539_PCA9539R Product data sheet Pin configuration for HVQFN24 All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 5 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5.2 Pin description Table 3. Symbol Product data sheet Pin Description SO24, TSSOP24 HVQFN24 INT 1 22 A1 2 23 address input 1 RESET 3 24 active LOW reset input. Driving this pin LOW causes: interrupt output (open-drain) * PCA9539 to reset its state machine and registers * PCA9539R to reset its state machine, but has no effect on its registers IO0_0 4 1 port 0 input/output 0 IO0_1 5 2 port 0 input/output 1 IO0_2 6 3 port 0 input/output 2 IO0_3 7 4 port 0 input/output 3 IO0_4 8 5 port 0 input/output 4 IO0_5 9 6 port 0 input/output 5 IO0_6 10 7 port 0 input/output 6 IO0_7 11 8 port 0 input/output 7 VSS 12 9[1] supply ground IO1_0 13 10 port 1 input/output 0 IO1_1 14 11 port 1 input/output 1 IO1_2 15 12 port 1 input/output 2 IO1_3 16 13 port 1 input/output 3 IO1_4 17 14 port 1 input/output 4 IO1_5 18 15 port 1 input/output 5 IO1_6 19 16 port 1 input/output 6 IO1_7 20 17 port 1 input/output 7 A0 21 18 address input 0 SCL 22 19 serial clock line input SDA 23 20 serial data line open-drain input/output VDD 24 21 supply voltage [1] PCA9539_PCA9539R Pin description HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 6 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6. Functional description Refer to Figure 4 "Block diagram of PCA9539; PCA9539R". 6.1 Device address slave address 1 1 1 0 fixed 1 A1 A0 R/W programmable 002aad724 Fig 8. PCA9539; PCA9539R device address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Table 4. PCA9539_PCA9539R Product data sheet Command byte Command Register 0 Input port 0 1 Input port 1 2 Output port 0 3 Output port 1 4 Polarity inversion port 0 5 Polarity inversion port 1 6 Configuration port 0 7 Configuration port 1 All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 7 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value `X' is determined by the externally applied logic level. Table 5. Bit Input port 0 register 7 6 5 4 3 2 1 0 Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0 Default X X X X X X X X Table 6. Bit Input port 1 register 7 6 5 4 3 2 1 0 Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 Default X X X X X X X X 6.2.3 Registers 2 and 3: Output port registers This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7. Bit Output port 0 register 7 6 5 4 3 2 1 0 Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 Default 1 1 1 1 1 1 1 1 Table 8. Bit Output port 1 register 7 6 5 4 3 2 1 0 Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 Default 1 1 1 1 1 1 1 1 6.2.4 Registers 4 and 5: Polarity inversion registers This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with `1'), the Input port data polarity is inverted. If a bit in this register is cleared (written with a `0'), the Input port data polarity is retained. Table 9. Bit 7 6 5 4 3 2 1 0 Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0 Default 0 0 0 0 0 0 0 0 Table 10. Bit PCA9539_PCA9539R Product data sheet Polarity inversion port 0 register Polarity inversion port 1 register 7 6 5 4 3 2 1 0 Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 Default 0 0 0 0 0 0 0 0 All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 8 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins. If a bit in this register is set (written with `1'), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with `0'), the corresponding port pin is enabled as an output. At reset, the device's ports are inputs. Table 11. Bit Configuration port 0 register 7 6 5 4 3 2 1 0 Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 Default 1 1 1 1 1 1 1 1 Table 12. Bit Configuration port 1 register 7 6 5 4 3 2 1 0 Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 Default 1 1 1 1 1 1 1 1 6.3 Power-on reset When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9539; PCA9539R registers and SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.4 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In the PCA9539 the registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input typically requires a pull-up to VDD. In the PCA9539R, only the device state machine is initialized. The internal general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin will only reset the I2C-bus interface should it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I2C-bus is being restored. 6.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS. PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 9 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset data from shift register output port register data configuration register data from shift register D VDD Q1 Q FF write configuration pulse CK Q D Q FF write pulse I/O pin Q2 CK output port register input port register D Q FF read pulse VSS input port register data CK to INT polarity inversion register data from shift register D Q FF write polarity pulse polarity inversion register data CK 002aad723 At power-on reset, all registers return to default values. Fig 9. Simplified schematic of I/Os 6.6 Bus transactions 6.6.1 Writing to the port registers Data is transmitted to the PCA9539; PCA9539R by sending the device address and setting the least significant bit to a logic 0 (see Figure 8 "PCA9539; PCA9539R device address"). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9539; PCA9539R are configured to operate as four register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and Configuration ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 10 and Figure 11). For example, if the first byte is sent to Output port 1 (register 3), then the next byte will be stored in Output port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 10 of 38 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 2 3 4 5 6 7 8 9 slave address SDA S 1 1 1 NXP Semiconductors PCA9539_PCA9539R Product data sheet 1 SCL data to port 0 command byte 0 1 A1 A0 0 START condition R/W A 0 0 0 0 0 0 1 0 acknowledge from slave A 0.7 DATA 0 data to port 1 0.0 A 1.7 acknowledge from slave DATA 1 1.0 A P STOP condition acknowledge from slave write to port tv(Q) data out from port 1 DATA VALID 002aad725 Fig 10. Write to output port registers 1 2 3 4 5 6 7 8 9 data to register 11 of 38 (c) NXP Semiconductors N.V. 2014. All rights reserved. slave address SDA S 1 1 1 command byte 0 1 A1 A0 0 START condition R/W A 0 0 0 acknowledge from slave 0 0 1 MSB 1 0 A acknowledge from slave data to register MSB LSB DATA 0 A acknowledge from slave LSB DATA 1 A P STOP condition 002aad726 Fig 11. Write to configuration registers PCA9539; PCA9539R SCL 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 8 -- 26 November 2014 All information provided in this document is subject to legal disclaimers. tv(Q) data out from port 0 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6.2 Reading the port registers In order to read data from the PCA9539; PCA9539R, the bus master must first send the PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 8 "PCA9539; PCA9539R device address"). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9539; PCA9539R (see Figure 12, Figure 13 and Figure 14). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input port 1, then the next byte read would be Input port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. slave address SDA S 1 1 1 0 1 A1 A0 0 START condition A R/W data from lower or upper byte of register slave address 1 1 1 0 (repeated) START condition MSB 1 A1 A0 1 (cont.) acknowledge from slave acknowledge from slave (cont.) S A COMMAND BYTE A data from upper or lower byte of register LSB DATA (first byte) R/W acknowledge from slave MSB A acknowledge from master LSB DATA (last byte) NA P no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter STOP condition 002aad727 Remark: Transfer can be stopped at any time by a STOP condition. Fig 12. Read from register PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 12 of 38 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA9539_PCA9539R Product data sheet data into port 0 data into port 1 tv(INT_N) SCL 1 2 3 4 trst(INT_N) 5 6 slave address SDA S 1 1 1 0 START condition 7 8 9 R/W 1 A1 A0 1 I0.x A 7 6 5 acknowledge from slave 4 3 I1.x 2 1 0 A acknowledge from master 7 6 5 4 3 I0.x 2 1 0 A acknowledge from master 7 6 5 4 3 STOP condition I1.x 2 1 0 A acknowledge from master 7 6 5 4 3 2 1 0 1 P non acknowledge from master read from port 1 002aad728 13 of 38 (c) NXP Semiconductors N.V. 2014. All rights reserved. Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to `00' (read input port register). Fig 13. Read input port register, scenario 1 PCA9539; PCA9539R read from port 0 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 8 -- 26 November 2014 All information provided in this document is subject to legal disclaimers. INT xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DATA 00 DATA 01 DATA 02 DATA 03 tsu(D) th(D) data into port 1 NXP Semiconductors PCA9539_PCA9539R Product data sheet data into port 0 DATA 10 DATA 11 DATA 12 tsu(D) th(D) tv(INT_N) SCL 1 2 3 4 trst(INT_N) 5 6 slave address SDA S 1 1 1 0 START condition 7 8 9 R/W 1 A1 A0 1 I0.x A acknowledge from slave DATA 00 I1.x A acknowledge from master DATA 10 I0.x A acknowledge from master DATA 03 I1.x A acknowledge from master DATA 12 STOP condition 1 P non acknowledge from master read from port 1 002aad729 14 of 38 (c) NXP Semiconductors N.V. 2014. All rights reserved. Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to `00' (read input port register). Fig 14. Read input port register, scenario 2 PCA9539; PCA9539R read from port 0 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 8 -- 26 November 2014 All information provided in this document is subject to legal disclaimers. INT PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input port register is read (see Figure 13). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input port register. 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15). SDA SCL data line stable; data valid change of data allowed mba607 Fig 15. Bit transfer 7.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16). SDA SCL S P START condition STOP condition mba608 Fig 16. Definition of START and STOP conditions PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 15 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7.2 System configuration A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 17). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 17. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S START condition 8 9 clock pulse for acknowledgement 002aaa987 Fig 18. Acknowledgement on the I2C-bus PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 16 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8. Application design-in information VDD (5 V) 10 k 10 k 10 k 10 k 2 k VDD VDD MASTER CONTROLLER PCA9539 INT SCL SCL IO0_0 SDA SDA IO0_1 INT INT RESET RESET SUB-SYSTEM 1 (e.g., temp sensor) 100 k (x3) SUB-SYSTEM 2 (e.g., counter) IO0_2 RESET IO0_3 VSS A IO0_4 controlled switch (e.g., CBT device) enable IO0_5 B IO0_6 IO0_7 IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A1 A0 SUB-SYSTEM 3 (e.g., alarm system) 10 DIGIT NUMERIC KEYPAD ALARM VDD VSS 002aad730 Device address configured as 1110 100X for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs. Fig 19. Typical application PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 17 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 19. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 20 shows a high value resistor in parallel with the LED. Figure 21 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. 3.3 V VDD VDD LED 5V VDD 100 k LED LEDn LEDn 002aac190 002aac189 Fig 20. High value resistor in parallel with the LED Fig 21. Device supplied by a lower voltage 9. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max +6.0 VDD supply voltage 0.5 VI/O voltage on an input/output pin VSS 0.5 6 IO output current II Unit V V - 50 mA input current - 20 mA IDD supply current - 160 mA ISS ground supply current - 200 mA Ptot total power dissipation - 200 mW Tstg storage temperature 65 +150 C Tamb ambient temperature all devices except PCA9539PW/Q900 40 +85 C PCA9539PW/Q900 40 +125 C - 125 C Tj(max) on an I/O pin operating maximum junction temperature PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 18 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 10. Static characteristics Table 14. Static characteristics for all devices except PCA9539PW/Q900 VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz; I/O = inputs - 135 200 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 0.25 1 A Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 A no load; VI = VDD or VSS - 1.5 1.65 V VPOR power-on reset voltage[1] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V 3 - - mA IL leakage current VI = VDD = VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF 0.5 - +0.3VDD V I/Os VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current VOH HIGH-level output voltage 0.7VDD - 5.5 V VDD = 2.3 V to 5.5 V; VOL = 0.5 V [2] 8 9 - mA VDD = 2.3 V to 5.5 V; VOL = 0.7 V [2] 10 11 - mA IOH = 8 mA; VDD = 2.3 V [3] 1.8 - - V IOH = 10 mA; VDD = 2.3 V [3] 1.7 - - V IOH = 8 mA; VDD = 3.0 V [3] 2.6 - - V IOH = 10 mA; VDD = 3.0 V [3] 2.5 - - V IOH = 8 mA; VDD = 4.75 V [3] 4.1 - - V IOH = 10 mA; VDD = 4.75 V [3] 4.0 - - V ILIH HIGH-level input leakage current VDD = 5.5 V; VI = VDD - - 1 A ILIL LOW-level input leakage current VDD = 5.5 V; VI = VSS - - 1 A Ci input capacitance - 3.7 5 pF Co output capacitance - 3.7 5 pF 3 - - mA Interrupt INT IOL LOW-level output current VOL = 0.4 V Select inputs A0, A1 and RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current 1 - +1 A [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 19 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). Table 15. Static characteristics for PCA9539PW/Q900 VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3.0 - 5.5 V Supplies VDD supply voltage IDD supply current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz; I/O = inputs - 135 200 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 0.25 1 A Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 A no load; VI = VDD or VSS - 1.5 1.65 V VPOR power-on reset voltage[1] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current, SDA VDD = 5.5 V 3 - - mA VDD = 3.0 V VOL = 0.4 V 2.5 - - mA IL leakage current VI = VDD = VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF I/Os VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.5 V VDD = 4.5 V [2] 8 9 - mA VDD = 3.0 V [2] 7.5 - - mA VDD = 4.5 V [2] 10 11 - mA VDD = 3.0 V [2] 9.5 - - mA VDD = 4.5 V [3] 4.1 - - V VDD = 3.0 V [3] 2.5 - - V VDD = 4.5 V [3] 4.0 - - V VDD = 3.0 V [3] 2.4 - - V VOL = 0.7 V VOH IOH = 8 mA HIGH-level output voltage IOH = 10 mA ILIH HIGH-level input leakage current VDD = 5.5 V; VI = VDD - - 1 A ILIL LOW-level input leakage current VDD = 5.5 V; VI = VSS - - 1 A Ci input capacitance - 3.7 5 pF Co output capacitance - 3.7 5 pF 3 - - mA Interrupt INT IOL LOW-level output current PCA9539_PCA9539R Product data sheet VOL = 0.4 V All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 20 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 15. Static characteristics for PCA9539PW/Q900 ...continued VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit +0.3VDD V Select inputs A0, A1 and RESET VIL LOW-level input voltage 0.5 - VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current 1 - +1 A [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). 11. Dynamic characteristics Table 16. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Min Max Min Max 0 100 0 400 Unit fSCL SCL clock frequency tBUF bus free time between a STOP and START condition 4.7 - 1.3 - s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition tVD;ACK data valid acknowledge time tHD;DAT data hold time tVD;DAT data valid time [1] [2] kHz 4.0 - 0.6 - s 0.3 3.45 0.1 0.9 s 0 - 0 - ns 300 - 50 - ns tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s fall time of both SDA and SCL signals [3] - 300 20 + 0.1Cb 300 ns tr rise time of both SDA and SCL signals [3] - 1000 20 + 0.1Cb 300 ns tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tf Port timing tv(Q) data output valid time tsu(D) data input set-up time th(D) data input hold time [4] - 200 - 200 ns 150 - 150 - ns 1 - 1 - s Interrupt timing tv(INT_N) valid time on pin INT - 4 - 4 s trst(INT_N) reset time on pin INT - 4 - 4 s PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 21 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 16. Dynamic characteristics ...continued Symbol Parameter Conditions Standard-mode I2C-bus Min Fast-mode I2C-bus Max Min Unit Max RESET timing tw(rst) reset pulse width 4 - 4 - ns trec(rst) reset recovery time 0 - 0 - ns trst reset time 400 - 400 - ns [5][6] [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. [4] tv(Q) measured from 0.7VDD on SCL to 50 % I/O output. [5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. [6] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus. 0.7 x VDD SDA 0.3 x VDD tr tBUF tf tHD;STA tSP tLOW 0.7 x VDD SCL 0.3 x VDD tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 22. Definition of timing on the I2C-bus ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os reconfigured as inputs 002aad732 Fig 23. Definition of RESET timing in PCA9539 PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 22 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os unchanged; device state machine reset 002aad733 Fig 24. Definition of RESET timing in PCA9539R SCL 2 1 0 A 70 % 30 % P SDA tsu(D) th(Q) input 50 % tv(INT_N) trst(INT_N) INT 002aad734 Fig 25. Expanded view of read input port register SCL 2 1 0 A 70 % P SDA tv(Q) output 50 % 002aad735 Fig 26. Expanded view of write to output port register PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 23 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 1 (D1) bit 0 (D0) acknowledge (A) STOP condition (P) 1 / fSCL 0.7 x VDD SCL 0.3 x VDD tBUF tr tf 0.7 x VDD SDA 0.3 x VDD tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab285 Rise and fall times refer to VIL and VIH. Fig 27. I2C-bus timing diagram PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 24 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 12. Test information VDD PULSE GENERATOR VI RL 500 VO VDD open GND DUT CL 50 pF RT 002aab284 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance of Zo of the pulse generators. Fig 28. Test circuitry for switching times RL from output under test 500 CL 50 pF S1 2VDD open GND RL 500 002aac226 Fig 29. Load circuit Table 17. Test tv(Q) PCA9539_PCA9539R Product data sheet Test data Load Switch CL RL 50 pF 500 All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 2 VDD (c) NXP Semiconductors N.V. 2014. All rights reserved. 25 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F +( \ Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H ES GHWDLO; Z 0 PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ PP LQFKHV = R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 30. Package outline SOT137-1 (SO24) PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 26 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F +( \ Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / ES H GHWDLO; Z 0 PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Fig 31. Package outline SOT355-1 (TSSOP24) PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 27 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset +94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ WHUPLQDO LQGH[DUHD $ $ ( F GHWDLO; H & H H \ & Y 0 & $ % Z 0 & E \ / H H (K H WHUPLQDO LQGH[DUHD ; 'K PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV $ 81,7 $ F E 'K ' PD[ PP ( (K H H H / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627 02 (8523($1 352-(&7,21 ,668('$7( Fig 32. Package outline SOT616-1 (HVQFN24) PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 28 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 29 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 33) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 Table 18. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 19. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 33. PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 30 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 31 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 16. Soldering: PCB footprints )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI62SDFNDJH 627 +[ *[ 3 +\ *\ %\ $\ & ' [ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\ VRWBIU Fig 34. PCB footprint for SOT137-1 (SO24); reflow soldering PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 32 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH 627 +[ *[ 3 +\ *\ %\ $\ & ' [ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\ VRWBIU Fig 35. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 33 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH 627 +[ *[ ' 3 & 63[ Q63[ +\ 63\WRW 63\ *\ 6/\ Q63\ %\ $\ 63[WRW 6/[ %[ $[ *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG VROGHUSDVWHGHSRVLW VROGHUODQGSOXVVROGHUSDVWH RFFXSLHGDUHD Q63[ Q63\ 'LPHQVLRQVLQPP 3 $[ $\ %[ %\ & ' 6/[ 6/\ 63[WRW 63\WRW 63[ 63\ *[ *\ +[ +\ ,VVXHGDWH VRWBIU Fig 36. PCB footprint for SOT616-1 (HVQFN24); reflow soldering PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 34 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 17. Abbreviations Table 20. Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CBT Cross-Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge FET Field-Effect Transistor FF Flip-Flop GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light Emitting Diode SMBus System Management Bus 18. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9539_PCA9539R v.8 20141126 Product data sheet - PCA9539_PCA9539R v.7 Modifications: * Table 15 "Static characteristics for PCA9539PW/Q900": updated IOL and VOH; changed operating power supply voltage range from "5.0 V 10 %" to "3.0 V to 5.5 V" for PCA9539PW/Q900 PCA9539_PCA9539R v.7 20140415 Product data sheet - PCA9539_PCA9539R v.6 PCA9539_PCA9539R v.6 20130206 Product data sheet - PCA9539_PCA9539R v.5 PCA9539_PCA9539R v.5 20080728 Product data sheet - PCA9539_PCA9539R v.4 PCA9539_PCA9539R v.4 20080519 Product data sheet - PCA9539 v.3 PCA9539 v.3 20060921 Product data sheet - PCA9539 v.2 PCA9539 v.2 (9397 750 14048) 20040930 Product data sheet - PCA9539 v.1 PCA9539 v.1 (9397 750 12898) 20040827 Product data sheet - - PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 35 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9539_PCA9539R Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 36 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP Semiconductors N.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 -- 26 November 2014 (c) NXP Semiconductors N.V. 2014. All rights reserved. 37 of 38 PCA9539; PCA9539R NXP Semiconductors 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 21. Contents 1 2 3 3.1 3.1.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 7 7.1 7.1.1 7.2 7.3 8 8.1 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin 1 quadrant indication . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 7 Registers 0 and 1: Input port registers . . . . . . . 8 Registers 2 and 3: Output port registers. . . . . . 8 Registers 4 and 5: Polarity inversion registers . 8 Registers 6 and 7: Configuration registers . . . . 9 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Writing to the port registers. . . . . . . . . . . . . . . 10 Reading the port registers . . . . . . . . . . . . . . . 12 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics of the I2C-bus . . . . . . . . . . . . 15 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 START and STOP conditions . . . . . . . . . . . . . 15 System configuration . . . . . . . . . . . . . . . . . . . 16 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application design-in information . . . . . . . . . 17 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Test information . . . . . . . . . . . . . . . . . . . . . . . . 25 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Handling information. . . . . . . . . . . . . . . . . . . . 29 Soldering of SMD packages . . . . . . . . . . . . . . 29 Introduction to soldering . . . . . . . . . . . . . . . . . 29 Wave and reflow soldering . . . . . . . . . . . . . . . 29 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 29 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 30 Soldering: PCB footprints. . . . . . . . . . . . . . . . 32 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18 19 19.1 19.2 19.3 19.4 20 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 36 36 36 37 37 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 November 2014 Document identifier: PCA9539_PCA9539R Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: PCA9539D,112 PCA9539D,118 PCA9539PW,112 PCA9539PW,118 PCA9539RPW,112 PCA9539RPW,118 PCA9539PW/Q900,118