LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 Common Anode Capable High Brightness LED Driver with High Frequency Dimming Check for Samples: LM3434 FEATURES DESCRIPTION * The LM3434 is an adaptive constant on-time DC/DC buck (step-down) constant current controller (a true current source). The LM3434 provides a constant current for illuminating high power LEDs. The output configuration allows the anodes of multiple LEDs to be tied directly to the ground referenced chassis for maximum heat sink efficacy. The high frequency capable architecture allows the use of small external passive components and no output capacitor while maintaining low LED ripple current. Two control inputs are used to modulate LED brightness. An analog current control input is provided so the LM3434 can be adjusted to compensate for LED manufacturing variations and/or color temperature correction. The other input is a logic level PWM control of LED current. The PWM functions by shorting out the LED with a parallel switch allowing high PWM dimming frequencies. High frequency PWM dimming allows digital color temperature control, interference blanking, field sequential illumination, and brightness control. Additional features include thermal shutdown, VCC under-voltage lockout, and logic level shutdown mode. The LM3434 is available in a low profile 24-pin WQFN package. 1 2 * * * * * * * * * * Operating Input Voltage Range of -9V to -30V w.r.t. LED Anode Control Inputs are Referenced to the LED Anode Output Current Greater than 6A Greater than 30kHz PWM Frequency Capable Negative Output Voltage Capability Allows LED Anode to be Tied Directly to Chassis for Maximum Heat Sink Efficiency No Output Capacitor Required Up to 1MHz Switching Frequency Low IQ, 1mA Typical Soft Start Adaptive Programmable ON Time Allows for Constant Ripple Current 24-Pin WQFN Package APPLICATIONS * * * Projection Systems Solid State Lighting Automotive Lighting TYPICAL APPLICATION CIRCUIT ADJ ADJ EN EN DIM DIM DMO TON DIMR -12V LED ANODE BST2 CSP 270 pF CSN 0.1 PF 44.2k 0.47 PF LM3434 BST 6 PH 0.01 LED CATHODE Q2 LS LO SS COMP VEE 4.7 PF CGND VIN LED HS VCC +3.3V Q3 Q1 HO 22 PF 2.2 PF GND 0.01 PF -12V 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2013, Texas Instruments Incorporated LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com NC BST2 DIMO DIMR 21 20 19 CSN 23 22 CSP 24 CONNECTION DIAGRAM TON 1 18 HS ADJ 2 17 HO EN 3 16 BST DIM 4 15 VCC VIN 5 14 LO CGND 6 13 LS 9 10 11 NC SS NC 12 8 NC 7 VEE COMP LM3434 Figure 1. 24-Lead WQFN (Top View) See RTW0024A Package PIN DESCRIPTIONS 2 Pin Name Function 1 TON On-time programming pin. Tie an external resistor (RON) from TON to CSN, and a capacitor (CON) from TON to VEE. This sets the nominal operating frequency when the LED is fully illuminated. 2 ADJ Analog LED current adjust. Tie to VIN for fixed 60mV average current sense resistor voltage. Tie to an external reference to adjust the average current sense resistor voltage (programmed output current). Refer to the "VSENSE vs. ADJ Voltage" graphs in the Typical Performance Characteristics section and the Design Procedure section of the datasheet. 3 EN Enable pin. Connect this pin to logic level HI or VIN for normal operation. Connect this pin to CGND for low current shutdown. EN is internally tied to VIN through a 100k resistor. 4 DIM Logic level input for LED PWM dimming. DIM is internally tied to CGND through a 100k resistor. 5 VIN Logic power input: Connect to positive voltage between +3.0V and +5.8V w.r.t. CGND. 6 CGND Chassis ground connection. 7 VEE 8 COMP Negative voltage power input: Connect to voltage between -30V to -9V w.r.t. CGND. 9 NC No internal connection. Tie to VEE or leave open. 10 SS Soft Start pin. Tie a capacitor from SS to VEE to reduce input current ramp rate. Leave pin open if function is not used. The SS pin is pulled to VEE when the device is not enabled. 11 NC No internal connection. Tie to VEE or leave open. 12 NC No internal connection. Tie to VEE or leave open. 13 LS Low side FET gate drive return pin. 14 LO Low side FET gate drive output. Low in shutdown. 15 VCC Low side FET gate drive power bypass connection and boost diode anode connection. Tie a 2.2F capacitor between VCC and VEE. 16 BST High side "synchronous" FET drive bootstrap rail. 17 HO High side "synchronous" FET gate drive output. Pulled to HS in shutdown. 18 HS Switching node and high side "synchronous" FET gate drive return. Compensation pin. Connect a capacitor between this pin and VEE. 19 DIMR LED dimming FET gate drive return. Tie to LED cathode. If PWM dimming is not used this pin may be left open. 20 DIMO LED dimming FET gate drive output. DIMO is a driver that switches between DIMR and BST2. If PWM dimming is not used this pin may be left open. 21 BST2 DIMO high side drive supply pin. Tie a 0.1F between BST2 and CGND. 22 NC No internal connection. Tie to VEE or leave open. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 PIN DESCRIPTIONS (continued) Pin Name 23 CSN Current sense amplifier inverting input. Connect to current sense resistor negative terminal. Function 24 CSP Current sense amplifier non-inverting input. Connect to current sense resistor positive terminal. EP VEE Exposed Pad on the underside of the device. Connect this pad to a PC board plane connected to VEE. BLOCK DIAGRAM VIN CGND Linear Regulator BST2 Level Shift DIM PWM Driver DIMO Level Shift EN DIMR ADJ VCC UVLO BST Thermal Shutdown + Gm CSP + CSN - Bootstrap Driver Programmable ON Time Gm HO HS Off-Time Comp Low Side Gate Driver 10 PA LO LS SS COMP VEE TON Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 3 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/ Distributors for availability and specifications. VALUE / UNIT VIN, EN, DIM, ADJ to CGND -0.3V to +7V COMP, SS to VEE -0.3V to +7V BST to HS -0.3V to +7V VCC to VEE -0.3V to +7.5V CGND, DIMR, CSP, CSN, TON to VEE -0.3V to +33V HS to VEE (2) -0.3V to +33V LS to VEE -0.3V to +0.3V HO output HS-0.3V to BST+0.3V DIMO to DIMR -0.3V to +7V LO output LS-0.3V to VCC +0.3V BST2 to VEE -0.3V to 40V Maximum Junction Temperature 150C Power Dissipation (3) Internally Limited ESD Susceptibility Human Body Model (4) (1) (2) (3) (4) 2kV Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test conditions, see the Electrical Characteristics. The HS pin can go to -6V with respect to VEE for 30ns and +22V with respect to VEE for 50ns without sustaining damage. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) - TA)/JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=175C (typ.) and disengages at TJ=155C (typ). Human Body Model, applicable std. JESD22-A114-C. RECOMMENDED OPERATING CONDITIONS VALUE / UNIT Operating Junction Temperature Range (1) -40C to +125C -65C to +150C Storage Temperature Input Voltage VIN w.r.t. CGND 3.0V to 5.8V Input Voltage VEE w.r.t. CGND -9V to -30V ADJ Input Voltage Range to CGND (1) 4 0V to VIN All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 ELECTRICAL CHARACTERISTICS Specifications in standard type face are for TJ = 25C and those with boldface type apply over the full Operating Temperature Range ( TJ = -40C to +125C). Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VEE = -12.0V and VIN = +3.3V with respect to CGND. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units SUPPLY CURRENT IINVEE IINVIN VEE Quiescent Current VIN Quiescent Current EN = CGND 142 EN = VIN, Not Switching 1.0 250 EN = VIN, Not Switching 450 EN = CGND 35 71 A mA A OUTPUT CURRENT CONTROL VCS Current sense target voltage; VCS = VCSP - VCSN VADJ = VIN 57 60 63 mV GADJ IADJ Gain = (VADJ-CGND)/(VCNP-VCSN) VIN = 3.3V, VADJ = 0.5V or 1.5V w.r.t. CGND 15 16.67 18 V/V ICSN Isense Input Current VADJ = 1V w.r.t. CGND -50 VADJ = VIN 10 VADJ = VIN 60 VADJ = 1V w.r.t. CGND 1 ICSP Isense Input Current Gm CS to COMP Transconductance; Gm = ICOMP / (VCSP - VCSN - VADJ/16.67) A A 0.6 1.3 2.2 mS VTON - VEE at terminate ON time event 230 287 334 mV 6.3 6.75 7.1 ON TIME CONTROL TONTH On time threshold GATE DRIVE AND INTERNAL REGULATOR VCCOUT VCC output regulation w.r.t. VEE ICC = 0mA to 20mA VCCILIM VCC current limit VCC = VEE ROLH HO output low resistance I = 50mA source 2 ROHH HO output high resistance I = 50mA sink 3 ROLL LO output low resistance I = 50mA source 2 ROHL LO output high resistance I = 50mA sink 3 ROLP DIMO output low resistance I = 5mA source 20 ROHP DIMO output high resistance I = 5mA sink 30 -110 V mA FUNCTIONAL CONTROL VINUVLO VIN undervoltage lockout With respect to CGND VCCUVLO VCC - VEE undervoltage lockout thresholds On Threshold 6.0 6.6 7.0 Off threshold 4.9 5.4 5.8 VEN Enable threshold, with respect to CGND Device on w.r.t. CGND Device off w.r.t. CGND REN Enable pin pullup resistor VDIM DIM logic input threshold DIM pin pulldown resistor IADJ ADJ pin current ISS SS pin source current RSS SS pin pulldown resistance (1) (2) V 1.6 0.6 100 DIM rising threshold w.r.t. CGND DIM falling threshold w.r.t. CGND RDIM 1.4 0.6 100 EN = CGND V k 1.6 -1.0 V V k 1.0 A 10 A 1.0 k All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely norm. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 5 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Specifications in standard type face are for TJ = 25C and those with boldface type apply over the full Operating Temperature Range ( TJ = -40C to +125C). Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VEE = -12.0V and VIN = +3.3V with respect to CGND. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units AC SPECIFICATIONS TDTD LO and HO dead time TPDIM DIM to DIMO propagation delay LO falling to HO rising dead time 26 HO falling to LO rising dead time 28 DIM rising to DIMO rising delay 96 175 DIM falling to DIMO falling delay 40 160 ns ns THERMAL SPECIFICATIONS TJLIM Junction temperature thermal limit 175 TJLIM(hyst) Thermal limit hysteresis 20 C JA WQFN package thermal resistance 39 C/W 6 JEDEC 4 layer board Submit Documentation Feedback C Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs. LED Forward Voltage (VCGND-VEE = 9V) Efficiency vs. LED Forward Voltage (VCGND-VEE = 12V) 97 96 2A 4A 6A 8A 96 94 94 EFFICIENCY (%) EFFICIENCY (%) 95 93 92 91 90 2A 4A 6A 8A 89 88 87 1 2 3 4 5 92 90 88 86 6 84 7 1 2 3 VLED (V) 5 6 7 VLED (V) Figure 2. Figure 3. Efficiency vs. LED Forward Voltage (VCGND-VEE = 14V) VSENSE vs. VADJ (VIN = 3.3V) 100 96 2A 4A 6A 8A 94 90 80 70 VSENSE (mV) 92 EFFICIENCY (%) 4 90 88 86 60 50 40 30 84 20 82 10 0 0.2 80 1 2 3 4 5 6 7 0.4 0.6 0.8 1 1.2 1.4 1.6 60 80 ADJ VOLTAGE (V) VLED (V) Figure 4. Figure 5. VSENSE vs. VADJ (VIN = 5.0V) VSENSE vs. Temperature (ADJ = VIN) 61 250 60.8 60.6 200 VSENSE (mV) VSENSE (mV) 60.4 150 100 60.2 60 59.8 59.6 59.4 50 59.2 0 0.2 0.7 1.2 1.7 2.2 2.7 3.2 59 -40 -20 0 20 40 AMBIENT TEMPERATURE (C) ADJ VOLTAGE (V) Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 7 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) VSENSE vs. Temperature (ADJ = 1.0V) Average LED Current vs. DIM Duty Cycle (30kHz dimming, ILED = 6A nominal) 61 7 AVERAGE LED CURRENT (A) 60.8 60.6 VSENSE (mV) 60.4 60.2 60 59.8 59.6 59.4 59.2 59 -40 -20 0 20 40 60 6 5 4 3 2 1 0 80 0 AMBIENT TEMPERATURE (C) 10 20 30 40 50 60 70 80 90 100 DIM DUTY CYCLE (%) Figure 8. Figure 9. Startup Waveform Shutdown Waveform ILED = 6A nominal, VIN = 3.3V, VEE = -12V, VLED = 3V, SS = open Top trace: EN input, 2V/div, DC Middle trace: VEE input current, 2A/div, DC Bottom trace: ILED, 2A/div, DC T = 100s/div Figure 10. ILED = 6A nominal, VIN = 3.3V, VEE = -12V, VLED = 3V, SS = open Top trace: EN input, 2V/div, DC Middle trace: VEE input current, 2A/div, DC Bottom trace: ILED, 2A/div, DC T = 100s/div Figure 11. 30kHz PWM Dimming Waveform Showing Inductor Ripple Current ILED = 6A nominal, VIN = 3.3V, VEE = -12V Top trace: DIM input, 2V/div, DC Bottom trace: ILED, 2A/div, DC T = 10s/div Figure 12. 8 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 OPERATION CURRENT REGULATOR OPERATION The LM3434 is a controller for a Continuous Conduction Buck Converter. Because of its buck topology and operation in the continuous mode, the output current is very well controlled. It only varies within a switching frequency cycle by the inductor ripple current. This ripple current is normally set at 10% of the DC current. Setting the ripple current lower than 10% is a useful tradeoff of inductor size for less LED light output ripple. Additional circuitry can be added to achieve any LED light ripple desired. The LED current is set by the voltage across a sense resistor. This sense voltage is nominally 60mV but can be programmed higher or lower by an external control voltage. The running frequency of the converter is programmed by an external RC network in conjunction with the LED's forward voltage. The frequency is nominally set around 200kHz to 500khz. Fast PWM control is available by shorting the output of the current source by a MOSFET in parallel with the LED. During the LED OFF time the running frequency is determined by the RC network and the parasitic resistance of the output circuit including the DIM FET RDSON. The LM3434 system has been evaluated to be a very accurate, high compliance current source. This is manifest in its high output impedance and accurate current control. The current is measured to vary less than 6mA out of 6A when transitioning from LED OFF (output shorted) to LED ON (output ~6V). PROTECTION The LM3434 has dedicated protection circuitry running during normal operation. The thermal shutdown circuitry turns off all power devices when the die temperature reaches excessive levels. The VCC undervoltage lockout (UVLO) comparator protects the power devices during power supply startup and shutdown to prevent operation at voltages less than the minimum operating input voltage. The VCC pin is short circuit protected to VEE. The LM3434 also features a shutdown mode which decreases the supply current to approximately 35A. The ADJ, EN, and DIM pins are capable of sustaining up to +/-2mA. If the voltages on these pins will exceed either VIN or CGND by necessity or by a potential fault, an external resistor is recommended for protection. Size this resistor to limit pin current to under 2mA. A 10k resistor should be sufficient. This resistor may be used in any application for added protection without any impact on function or performance. Output Open Circuit The LM3434 can be powered up with an open circuit without sustaining any damage to the circuit. During normal operation the circuit will also tolerate an open circuit condition without sustaining damage provided a schottky diode is placed within the circuit to provide a current path to disharge the energy stored in the inductor. The anode of the schottky should be connected to the negative supply voltage while the cathode should be connected to the point where the inductor and sense resistor intersect. This diode should have a surge current rating equal to that of the maximum LED current driven. DESIGN PROCEDURE This section presents guidelines for selecting external components. SETTING LED CURRENT CONTROL LM3434 uses average current mode control to regulate the current delivered to the LED (ILED). An external current sense resistor (RSENSE) in series with the LED is used to convert ILED into a voltage that is sensed by the LM3434 at the CSP and CSN pins. CSP and CSN are the inputs to an error amplifier with a programmed input offset voltage (VSENSE). VSENSE is used to regulate ILED based on the following equation: ILED = VSENSE/RSENSE (1) Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 9 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com FIXED LED CURRENT The ADJ pin sets VSENSE. Tie ADJ to VIN to use a fixed 60mV internal reference for VSENSE. Select RSENSE to fix the LED current based on the following equation: RSENSE = 60mV/ILED (2) ADJUSTABLE LED CURRENT When tied to an external voltage the ADJ pin sets VSENSE based on the following equation: VSENSE = (VADJ - VCGND)/16.66 (3) When the reference on ADJ is adjustable, VSENSE and ILED can be adjusted within the linear range of the ADJ pin. This range has the following limitations: 0.3V < VADJ < (The greater of 1.5V or (VIN - 1.9V)) (4) When VADJ is less than this linear range the VSENSE is specified by design to be less than or equal to 0.3V/16.667. When VADJ is greater than this linear range and less than VIN - 1V, VSENSE is specified by design to be less than or equal to VADJ/16.667. If VADJ is greater than VIN - 1V, VSENSE switches to 60mV. INPUT CAPACITOR SELECTION A low ESR ceramic capacitor is needed to bypass the MOSFETs. This capacitor is connected between the drain of the synchronous FET (CGND) and the source of the main switch (VEE). This capacitor prevents large voltage transients from appearing at the VEE pin of the LM3434. Use a 22F value minimum with X5R or X7R dielectric. In addition to the FET bypass capacitors, additional bypass capacitors should be placed near the VEE and VIN pins and should be returned to CGND. The input capacitor must also be sized to handle the dimming frequency input ripple when the DIM function is used. This ripple may be as high as 85% of the nominal DC input current (at 50% duty cycle). When dimming this input capacitor should be selected to handle the input ripple current. RECOMMENDED OPERATING FREQUENCY AND ON TIME "TIMEON" CALCULATION Although the switching frequency can be set over a wide range, the following equation describes the recommended frequency selection given inexpensive magnetic materials available today: A (MHz) f= ILED (5) In the above equation A=1.2 for powdered iron core inductors and A=0.9 or less for ferrite core inductors. This difference takes into account the fact that ferrite cores generally become more lossy at higher frequencies. Given the switching frequency f calculated above, TIMEON can be calculated. If VLED is the forward voltage drop of the LED that is being driven, TIMEON can be calculated with the following equation: VLED TIMEON = f|VEE| (6) TIMING COMPONENTS (RON and CON) Using the calculated value for TIMEON, the timing components RON and CON can be selected. CON should be large enough to dominate the parasitic capacitance of the TON pin. A good CON value for most applications is 1nF. Based on calculated TIMEON, CON, and the nominal VEE and VLED voltages, RON can be calculated based on the following equation: RON = 10 TIMEON CON(0.3/(|VEE|-VLED)) (7) Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 INDUCTOR SELECTION The most critical inductor parameters are inductance, current rating, and DC resistance. To calculate the inductance, use the desired peak to peak LED ripple current (IRIPPLE), RON, and CON. A reasonable value for IRIPPLE is 10% of ILED. The inductor value is calculated using the following equation: L= 0.3 x RON x CON IRIPPLE (8) For all VLED and VEE voltages, IRIPPLE remains constant and is only dependent on the passive external components RON, CON, and L. The I2R loss caused by the DC resistance of the inductor is an important parameter affecting the efficiency. Lower DC resistance inductors are larger. A good tradeoff point between the efficiency and the core size is letting the inductor I2R loss equal 1% to 2% of the output power. The inductor should have a current rating greater than the peak current for the application. The peak current is ILED plus 1/2 IRIPPLE. POWER FET SELECTION FETs should be chosen so that the I2RDSON loss is less than 1% of the total output power. Analysis shows best efficiency with around 8m of RDSON and 15nC of gate charge for a 6A application. All of the switching loss is in the main switch FET. An additional important parameter for the synchronous FET is reverse recovery charge (QRR). High QRR adversely affects the transient voltages seen by the IC. A low QRR FET should be used. DIM FET SELECTION Choose a DIM FET with the lowest RDSON for maximum efficieny and low input current draw during the DIM cycle. The output voltage during DIM will determine the switching frequency. A lower output voltage results in a lower switching frequency. If the lower frequency during DIM must be bound, choose a FET with a higher RDSON to force the switching frequency higher during the DIM cycle. Placement of the Parallel Dimming FET When using a FET in parallel with the LED for PWM dimming special consideration must be used for the location of the FET. The ideal placement of the FET is directly next to the LED. Any distance between this FET and the LED results in line inductance. Fast current changes through this inductance can induce large voltage spikes due to v = Ldi/dt. These can be mitigated by either reducing the distance between the FET and the LED and/or slowing the PWM edges, and therefore the dt, by using some gate resistance on the FET. In cases where the dimming FET is not placed close to the LED and/or very fast switching edges are desired the induced voltages can become great enough to damage the dimming FET and/or the LM3434 HS pin. This can also result in a large spike of current into the LED when the FET is turned off. In these cases a snubber should be placed across the dimming FET to protect the device(s). BOOTSTRAP CAPACITORS The LM3434 uses two bootstrap capacitors and a bypass capacitor on VCC to generate the voltages needed to drive the external FETs. A 2.2F ceramic capacitor or larger is recommended between the VCC and LS pins. A 0.47F is recommended between the HS and BST pins. A 0.1F is recommended between BST2 and CGND. SOFT-START CAPACITOR The LM3434 integrates circuitry that, when used in conjunction with the SS pin, will slow the current ramp on start-up. The SS pin is used to tailor the soft-start for a specific application. A capacitor value of 0.1F on the SS pin will yield a 12mS soft start time. For most applications soft start is not needed. ENABLE OPERATION The EN pin of the LM3434 is designed so that it may be controlled using a 1.6V or higher logic signal. If the enable function is not used, the EN pin may be tied to VIN or left open. This pin is pulled to VIN internally through a 100k pull up resistor. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 11 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com PWM DIM OPERATION The DIM pin of the LM3434 is designed so that it may be controlled using a 1.6V or higher logic signal. The PWM frequency easily accomodates more than 40kHz dimming and can be much faster if needed. If the PWM DIM pin is not used, tie it to CGND or leave it open. The DIM pin is tied to CGND internally through a 100k pull down resistor. LAYOUT CONSIDERATIONS The LM3434 is a high performance current driver so attention to layout details is critical to obtain maximum performance. The most important PCB board design consideration is minimizing the loop comprised by the main FET, synchronous FET, and their associated decoupling capacitor(s). Place the VCC bypass capacitor as near as possible to the LM3434. Place the PWM dimming/shunt FET as close to the LED as possible. A ground plane should be used for power distribution to the power FETs. Use a star ground between the LM3434 circuitry, the synchronous FET, and the decoupling capacitor(s). The EP contact on the underside of the package must be connected to VEE. The two lines connecting the sense resistor to CSN and CSP must be routed as a differential pair directly from the resistor. A Kelvin connection is recommended. It is good practice to route the DIMO/DIMR, HS/HO, and LO/LS lines as differential pairs. The most important PCB board design consideration is minimizing the loop comprised by the main FET, synchronous FET, and their associated decoupling capacitor(s). Optimally this loop should be orthogonal to the ground plane. 12 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 APPLICATION INFORMATION 0.1 PF 44.2k LED ANODE ADJ ADJ EN EN DIM DIM DMO DIMR TON BST2 CSP 270 pF -12V CSN Q3* Q1 HO LED HS 0.47 PF LM3434 BST LED CATHODE Q2 LO 22 PF LS SS 4.7 PF COMP 100 VEE CGND VIN +3.3V 0.01 15 PH VCC 2.2 PF * Only required if PWM dimming is used. GND + 68 PF* 0.01 PF 0.1 PF -12V Figure 13. Up to 10A Output Application Circuit 0.1 PF 39k Q1 LED ANODE Q2 ADJ ADJ EN EN DIM DIM DIMR DMO TON BST2 CSP 330 pF -12V CSN Q5* Q6* HO LED HS 0.47 PF LM3434 BST Q3 Q4 0.005 10 PH LED CATHODE LO 22 PF X 2 LS SS 4.7 PF COMP 100 VEE VIN +5V CGND VCC GND + 150 PF* 0.1 PF * Only required if PWM dimming is used. 0.01 PF 2.2 PF -12V Figure 14. Up to 20A Output Application Circuit Table 1. Some Recommended Inductors (Others May Be Used) Manufacturer Inductor Contact Information Coilcraft GA3252-AL series, SER1360 series, and SER2900 series www.coilcraft.com 800-322-2645 Coiltronics HCLP2 series www.coiltronics.com Pulse PB2020 series www.pulseeng.com Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 13 LM3434 SNVS619B - MARCH 2010 - REVISED MAY 2013 www.ti.com Table 2. Some Recommended Input/Bypass Capacitors (Others May Be Used) Manufacturer Capacitor Contact Information Vishay Sprague 293D, 592D, and 595D series tantalum www.vishay.com 407-324-4140 Taiyo Yuden High capacitance MLCC ceramic www.t-yuden.com 408-573-4150 Cornell Dubilier ESRD seriec Polymer Aluminum Electrolytic SPV and AFK series V-chip series www.cde.com MuRata High capacitance MLCC ceramic www.murata.com Table 3. Some Recommended MOSFETs (Others May Be Used) 14 Manufacturer MOSFET Contact Information Siliconix Si7386DP (Main FET, DIM FET) Si7668ADP (Synchronous FET) Si7790DP (Main FET, Synchronous FET, DIM FET) www.vishay.com/company/bra nds/siliconix/ ON Semiconductor NTMFS4841NHT1G (Main FET, Synchronous FET, DIM FET) www.onsemi.com Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 LM3434 www.ti.com SNVS619B - MARCH 2010 - REVISED MAY 2013 REVISION HISTORY Changes from Revision A (May 2013) to Revision B * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LM3434 15 PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM3434SQ/NOPB LIFEBUY WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L3434 LM3434SQX/NOPB LIFEBUY WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L3434 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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