© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 6 1Publication Order Number:
NB4N316M/D
NB4N316M
3.3 V AnyLevel] Receiver
to CML Driver/Translator
with Input Hysteresis
2.0 GHz Clock / 2.5 Gb/s Data
The NB4N316M is a differential Clock or Data receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to CML, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications. The CML outputs are 16 mA open collector
(see Figure 18) which requires resistor (RL) load path to VTT
termination voltage (see Figure 19). The open collector CML outputs
must be terminated to VTT at power up. The differential outputs
produce Current–Mode Logic (CML) compatible levels when the
receiver is loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V
or 3.3 V supplies. This simplifies device interface by eliminating a
need for coupling capacitors.
The NB4N316M features an input threshold hysteresis of
approximately 25 mV, providing increased noise immunity and stability.
The device is offered in a small 8−pin TSSOP package (MSOP−8
compatible). Application notes, models, and support documentation
are available at www.onsemi.com.
Features
•Maximum Input Clock Frequency > 2.0 GHz
•Maximum Input Data Rate > 2.5 Gb/s
•Typically 1 ps of RMS Clock Jitter
•Typically 10 ps of Data Dependent Jitter
•550 ps Typical Propagation Delay
•150 ps Typical Rise and Fall Times
•Differential CML Outputs
•25 mV of Receiver Input Threshold Hysteresis
•Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and
VTT = 1.8 V to 3.6 V
•Functionally Compatible with Existing 2.5 V / 3.3 V LVEL,
LVEP, EP, and SG Devices
•−40°C to +85°C Ambient Operating Temperature
•These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM*
www.onsemi.com
TSSOP−8
DT SUFFIX
CASE 948R
1
8
E316
ALYWG
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Functional Block Diagram
Q
Q
D
D
(Note: Microdot may be in either location)
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2
Figure 2. Pinout (Top View) and Logic Diagram
1
2
3
45
6
7
8
Q
VEE
VCC
D
Q
D
VBB
NC
Table 1. Pin Description
Pin Name I/O Description
1 NC − No Connect.
2 D ECL, CML, LVCMOS, LVDS,
LVTTL Input Noninverted Differential Input. (Note 1)
3 D ECL, CML, LVCMOS, LVDS,
LVTTL Input Inverted Differential Input. (Note 1)
4 VBB −Internally Generated Reference Voltage Supply.
5 VEE −Negative Supply Voltage.
6 Q CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT.
7 Q CML Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT.
8 VCC −Positive Supply Voltage.
1. In the differential configuration if no signal is applied on D/D input, then the device will be susceptible to self−oscillation.
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Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model > 1000 V
> 70 V
Moisture Sensitivity (Note 1) 8−TSSOP Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 225
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply VEE = −0.5 V 4 V
VEE Negative Power Supply VCC = +0.5 V −4 V
VIPositive Input
Negative Input VEE = 0 V
VCC = 0 V VI = VCC +0.4 V
VI = VEE –0.4 V 4
−4 V
V
VOOutput Voltage Minimum
Maximum VEE + 600
VCC + 400 mV
mV
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient)
(Note 2) 0 lfpm
500 lfpm TSSOP−8
TSSOP−8 190
130 °C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 2) TSSOP−8 41 to 44 °C/W
Tsol Wave Solder < 3 Sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs VCC = 3.0 V to 3.6 V, VEE = 0 V, TA = −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current (Inputs and Outputs Open) 20 30 mA
RL = 50 W, VTT = 3.6 V to 2.5 V
VOH Output HIGH Voltage (Note 3) VTT − 60 VTT − 10 VTT mV
VOL Output LOW Voltage (Note 3) VTT − 1100 VTT − 800 VTT − 640 mV
|VOD|Differential Output Voltage Magnitude 640 780 1000 mV
RL = 25 W, VTT = 3.6 V to 2.5 V $5%
VOH Output HIGH Voltage (Note 3) VTT − 60 VTT − 10 VTT mV
VOL Output LOW Voltage (Note 3) VTT − 550 VTT − 400 VTT − 320 mV
|VOD|Differential Output Voltage Magnitude 320 390 500 mV
RL = 50 W, VTT = 1.8 V $5%
VOH Output HIGH Voltage (Note 3) VTT − 170 VTT − 10 VTT mV
VOL Output LOW Voltage (Note 3) VTT − 1100 VTT − 800 VTT − 640 mV
|VOD|Differential Output Voltage Magnitude 570 780 1000 mV
RL = 25 W, VTT = 1.8 V $5%
VOH Output HIGH Voltage (Note 3) VTT − 85 VTT − 10 VTT mV
VOL Output LOW Voltage (Note 3) VTT − 500 VTT − 400 VTT − 320 mV
|VOD|Differential Output Voltage Magnitude 285 390 500 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14 and 16)
Vth Input Threshold Reference Voltage Range (Note 5) VEE VCC mV
VIH Single−ended Input HIGH Voltage Vth + 100 VCC + 400 mV
VIL Single−ended Input LOW Voltage VEE − 400 Vth − 100 mV
VBB Internally Generated Reference Voltage Supply (Loaded with −100 mA) VCC − 1500 VCC − 1400 VCC − 1300 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)
VIHD Differential Input HIGH Voltage VEE VCC + 400 mV
VILD Differential Input LOW Voltage VEE − 400 VCC − 100 mV
VCMR Input Common Mode Range (Differential Configuration) VEE VCC mV
VID(HYST) Dif ferential Input Voltage Hysteresis (VIHD − VILD) 25 mV
|VID|Differential Input Voltage Magnitude (|VIHD − VILD|) (Note 7) 100 VCC − VEE mV
CIN Input Capacitance (Note 7) 1.5 pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. CML outputs require RL receiver termination resistors to VTT for proper operation. Outputs must be connected through RL to VTT at power
up. The output parameters vary 1:1 with VTT. VTT = 1.71 V to 3.6 V.
4. Input parameters vary 1:1 with VCC.
5. Vth is applied to the complementary input when operating in single−ended mode.
6. VCMR (MIN) varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
7. Parameter guaranteed by design and evaluation but not tested in production.
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Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VOUTPP Output Voltage Amplitude (RL = 50 W)
fin ≤ 1 GHz
(See Figure 12) fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
550
400
200
660
640
400
550
400
200
660
640
400
550
400
200
660
640
400
mV
VOUTPP Output Voltage Amplitude (RL = 25 W)
fin ≤ 1 GHz
(See Figure 12) fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
280
280
200
370
360
300
280
280
200
370
360
400
280
280
200
370
360
400
mV
fDATA Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s
tPLH,
tPHL Propagation Delay to Output Differential
@ 0.25 GHz 350 550 750 350 550 750 350 550 750 ps
tSKEW Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13) 2
20 20
100 2
20 20
100 2
20 20
100 ps
tJITTER RMS Random Clock Jitter RL = 50 W and
RL = 25 W (Note 11) fin = 750 MHz
fin = 1.5 GHz
fin = 2.0 GHz
Peak−to−Peak Data Dependent Jitter RL = 50 W
fDATA = 1.5 Gb/s
(Note 12) fDATA = 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter RL = 25 W
fDATA = 1.5 Gb/s
(Note 12) fDATA = 2.5 Gb/s
1
1
1
15
20
5
10
3
3
3
55
85
35
35
1
1
1
15
20
5
10
3
3
3
55
85
35
35
1
1
1
15
20
5
10
3
3
3
55
85
35
35
ps
VINPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10) 200 200 200 mV
tr
tfOutput Rise/Fall Times @ 0.25 GHz Q, Q
(20% − 80%) 150 300 150 300 150 300 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT.
Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.25 GHz.
10.VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11.Additive RMS jitter with 50% duty cycle clock signal.
12.Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 223−1).
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
0
100
200
300
400
500
600
700
800
0.75 1 1.25 1.5 1.75 2
RL = 50 W
RL = 25 W
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
(VCC − VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.75 1 1.25 1.5 1.75 2
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
(VCC − VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
RL = 50 W
RL = 25 W
0.5 0.5
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6
NB4N316M
0
10
20
30
40
50
60
70
80
0.5 0.75 1 1.25 1.5 1.75 2
−40°C
25°C
85°C
INPUT CLOCK FREQUENCY (GHz)
TIME (ps)
Figure 4. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 50 W)
0
5
10
15
20
25
30
35
0.5 0.75 1 1.25 1.5 1.75
2
25°C
−40°C
85°C
INPUT CLOCK FREQUENCY (GHz)
TIME (ps)
Figure 5. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 25 W)
300
350
400
450
500
550
600
−40 25 85
Figure 6. Typical Propagation Delay vs.
Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; V
in
= 100 mV; R
L
= 50 W)
TEMPERATURE (°C)
TIME (ps)
tPD
Figure 7. Typical Propagation Delay vs. Input
Offset Voltage (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; V
in
= 100 mV R
L
= 50 W)
300
350
400
450
500
550
600
tPD
INPUT OFFSET VOLTAGE (V)
TIME (ps)
VEE − 0.5 V VCC + 0.5
V
VCC *VEE
2
0.25 0.25
Figure 8. Supply Current vs. Temperature
0
5
10
15
20
25
30
35
−40 25 85
ICC
TEMPERATURE (°C)
CURRENT (mA)
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Figure 9. Typical Differential Output Waveform at 750 Mb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
Figure 10. Typical Differential Output Waveform 1.5 Gb/s
(R
L
= 50 W Left Plot, R
L
= 25 W Right Plot, V
in
= 100 mV, System DDJ = 25 ps)
DDJ = 5 ps
TIME (266.8 ps/div)
VOLTAGE (200 mV/div)
TIME (133.2 ps/div)
VOLTAGE (200 mV/div)
TIME (266.8 ps/div)
VOLTAGE (100 mV/div)
TIME (133.2 ps/div)
VOLTAGE (100 mV/div)
DDJ = 3 ps
DDJ = 5 ps
DDJ = 12 ps
Figure 11. Typical Differential Output Waveform 2.5 Gb/s
(R
L
= 50 W Left Plot, R
L
= 25 W Right Plot, V
in
= 100 mV, System DDJ = 24 ps)
TIME (80 ps/div)
VOLTAGE (200 mV/div)
TIME (80 ps/div)
VOLTAGE (100 mV/div)
DDJ = 20 ps DDJ = 7 ps
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8
Figure 12. AC Reference Measurement
D
D
Q
Q
tPHL
tPLH
VINPP = VIH(D) − VIL(D)
VOUTPP = VOH(Q) − VOL(Q)
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VCC
Figure 14. Differential Input Driven
Single−Ended Figure 15. Differential Inputs Driven
Differentially
Figure 16. Vth Diagram Figure 17. VCMR Diagram
D
VCC
GND
VIH
VIHmin
VIHmax
Vthmax
Vth
Vth
Vthmin VCMmax
VCMmax
D
VCMR
VCC
GND
D
D
Vth
Vth
D
D
VILmax
VIL
VILmin
D
VILCLKmax
VIHCLKmax
VID = VIHD − VILD
VILDtyp
VIHDtyp
VILDmin
VIHDmin
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Figure 19. Typical Examples of the Application Interface
Receiver
A
Receiver
B
VCCB = 1.8 V 2.5 V or 3.3 V
VCCA = 1.8 V 2.5 V or 3.3 V
50 W50 W
50 W50 W
50 W50 W
VTT = VCCB
VTT = VCCB
VTT = VCCA
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
NB4N316M
Receiver
C
Receiver
D
VCCD = 1.8 V 2.5 V or 3.3 V
VCCC = 1.8 V 2.5 V or 3.3 V
VCC = 3.3 V
VEE = 0 V
100 W100 W
75 W75 W
VTT = VCCD
VTT = VCCC
Z = 75 W
Z = 75 W
Z = 100 W
Z = 100 W
NB4N316M
NB4N316M
NB4N316M
VEE = 0 V
VCC = 3.3 V
VEE = 0 V
VCC = 3.3 V
VCC = 3.3 V
VEE = 0 V
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ORDERING INFORMATION
Device Package Shipping†
NB4N316MDTG TSSOP−8
(Pb−Free) 100 Units / Rail
NB4N316MDTR2G TSSOP−8
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1 14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
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NB4N316M/D
AnyLevel and ECLinPS are trademarks of Semiconductor Components INdustries, LLC (SCILLC).
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