SST39SF040-70-4C-PHE - MICROCHIP

Data Sheet

www.microchip.com

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Features

• Org anized as 128K x8 / 256K x8 / 512K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 10 mA (typical)

– Standby Current: 30 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 55 ns

– 70 ns

• Latched Address and Data

• Automatic Write Timing

– Internal VPP Gener ation

• Fast Erase and Byte-Pr ogram

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

2 seconds (typical) for SST39SF010A

4 seconds (typical) for SST39SF020A

8 seconds (typical) for SST39SF040

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP

• All devices are RoHS compliant

The SST39SF010A / SST39SF020A / SST39SF040 are CMOS Multi-Purpose

Flash (MPF) devices manufactured with SST proprietary, high performance

CMOS SuperFlash technology. The split-gate cell design and thick oxide tunnel-

ing injector attain better reliability and manufacturability compared with alternate

approaches. The SST39SF010A / SST39SF0 20A / SST39SF040 write (Program

or Erase) with a 4.5-5.5V power supply, and conforms to JEDEC st andard pinouts

for x8 memories

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Product Description

The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s propri-

etary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tun-

neling injector attain better reliability and manufacturability compared with alter nate approaches. The

SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply. The

SST39SF010A/020A/ 040 devices conform to JEDEC standard pinouts for x8 memories.

Featur ing high performance Byte-Program, the SST39SF010A/0 20A/040 devices provide a maximum

Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the comple-

tion of Program operation. To protect against inadver tent write, they have on-chip hardware and Soft-

ware Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of

applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data

retention is rated at greater than 100 years.

The SST39SF010A/020A/040 devices are suited for applications that require convenient and econom-

ical updating of program, configuration, or data memory. For all system applications, they significantly

improve performance and reliability, while lowering power consumption. They inherently use less

energy during erase and program than alternative flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and has a shorter erase time, the total energy

consumed during any Erase or Program operation is less than alternative flash technologies. These

devices also improve flexibility while lowering the cost for program, data, and configuration storage

applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have

to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Pro gram cycles.

To meet high density, surf a ce mount requir ements, the SST39SF010A/020A/040 are o ffered in 32-lead

PLCC and 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 2, 3, and 4

for pin assignments.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Block Diagram

Figure 1: Functional Block Diagram

Y-Decoder

I/O Buffers and Data Latches

1147 B1.2

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Pin Assignment

Figure 2: Pin Assignments for 32-lead PLCC

SST39SF010A

DQ0

SST39SF020ASST39SF040

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

SST39SF020A SST39SF040

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

A16

VDD

WE#

SST39SF020A SST39SF040

A12

A15

A16

VDD

WE#

A17

A12

A15

A16

A18

VDD

WE#

A17

32-lead PLCC

Top View

1147 32-plcc P2.4

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

SST39SF020ASST39SF040

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)

Figure 4: Pin Assignments for 32-pin PDIP

A11

A13

A14

WE#

VDD

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1147 32-tsop P1.1

Standard Pinout

Top View

Die Up

SST39SF010A

A11

A13

A14

A17

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

SST39SF020ASST39SF040 SST39SF010A

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

SST39SF020A SST39SF040

32-pin

PDIP

Top View

1147 32-pdip P3.2

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF010A

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF020A

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF040

SST39SF010A

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

SST39SF020A SST39SF040

VDD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Table 1: Pin Descr iption

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Erase AMS-A12 address lines will sele ct the sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate th e data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide 5.0V supply (4 .5-5.5V)

VSS Ground

NC No Connection Unconnected pins.

T1.2 25022

1. AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Device Operation

Commands are used to initiate the memor y operation functions of the device. Commands are written

to the de vice using standard micro processor write sequences. A command is written b y asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be

low f or the system to obtain data from the outputs . CE# is used f or device selection. When CE# is high,

the chip is deselected and only standby power is consumed. OE# is the output control and is used to

gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is

high. Refer to the Read cycle timing diagram (Figure 5) for further details.

Byte-Program Operation

The SST39SF010A/020A/040 are progr ammed on a byte-by-byte basis. Before programming, the sec-

tor where the byte exists must be fully erased. The Program operation is accom plished in three ste ps.

The first step is the three-byte load sequence for Software Data Protection. The second step is to load

byte address and byte data. During the Byte-Program operation, the addresses are latched on the fall-

ing edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either

CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated

after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once

initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and CE# controlled Program

operation timing diagrams and Figure 16 for flowcharts. Dur ing the Program operation, the only valid

reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to per-

form additional tasks. Any commands written during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The

sector architecture is based on unifor m sector size of 4 KByte. The Sector-Erase operation is initiated

by executing a six-byte comma nd lo ad se qu e nc e for Software Data Prot ect ion wit h Se cto r -Erase c om -

mand (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling

edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE#

pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be deter-

mined using either Data# Polling or Toggle Bit methods. See Figure 10 for timing w aveforms. An y com-

mands written during the Sector-Erase operation will be ignored.

Chip-Erase Operation

The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire

memory array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

sequence with Chip-Er ase command (10H) wit h address 5555H in t he last b yte sequence . The int ernal

Erase oper ation begins with the rising edge of the sixt h WE# or CE#, whiche v e r occurs first. During the

internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the com-

mand sequence, Figure 11 for timing diagram, and Figure 19 for the flowchar t. Any commands written

during the Chip-Erase operation will be ignored.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Write Operation Status Detection

The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Pro-

gram or Er ase) cycle, in order to optimize the system Write cycle time. The softw are detection includes

two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The En d-of -Write detectio n mode is en ab led

after the rising edge of WE# which initiate s the internal Progr am or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39SF010 A/020A/04 0 are in the internal Progr am oper ation, any att empt to read DQ7 will

produce the complement of the true data. Once the Program operation is completed, DQ7 will produce

true data. Note that even though DQ7 may have valid dat a immediately following the completion of an

internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after an interval of 1 µs. During inter nal Erase

operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,

DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for

Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth

WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce

alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is

completed, the toggling will stop. The de vice is then ready f or the ne xt oper ation. The Toggle Bit is valid

after the rising edge of four th WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase,

the Toggle Bit is valid after the rising edge of sixth WE# (o r CE#) pulse. See Figure 9 for Toggle Bit tim-

ing diagram and Figure 17 for a flowchart.

Data Protection

The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data

from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down .

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Software Data Protection (SDP)

The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all

data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a

series of three-byte sequence. The th ree- byte load sequence is used to in itiat e the Pr ogram ope r at ion ,

providing optimal protection from inadvertent Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of six-byte load sequence. The

SST39SF010A/020A/040 devices are shipped with the Software Data Protection permanently

enabled. See Table 4 for the specific software command codes. During SDP command sequence,

invalid commands will abort the device to read mode, within TRC.

Product Identification

The Product Identification mode identifies the device as the SST39SF040, SST39SF010A, or

SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users

may wish to use the software Product Identification operation to identify the part (i.e., using the device

ID) when using multiple manufacturers in the same socket. For details, Table 4 for software operation,

Figure 12 for the software ID entry and read timing diagram and Figure 18 for the ID entry command

sequence flowchart.

Product Identification Mode Exit/Reset

In order to retu rn to the standard Read mode, t he Softwa re Product Identi fication mode m ust be e xited.

Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read

operation. Please note that the software reset command is ignored during an internal Program or

Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure

18 for a flowchart.

Table 2: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39SF010A 0001H B5H

SST39SF020A 0001H B6H

SST39SF040 0001H B7H

T2.2 25022

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Operations

Table 3: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address, XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.3 25022

Table 4: Software Command Sequence

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr

1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

Data Addr

Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA

2. BA = Program Byte address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

3. SAX for Sector-Erase; uses AMS-A12 address lines

30H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softwa re ID Entry

4,5

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST39SF010A Device ID = B5H, is read with A0 = 1

SST39SF020A Device ID = B6H, is read with A0 = 1

SST39SF040 Device ID = B7H, is read with A0 = 1

5555H AAH 2AAAH 55H 5555H 90H

Softwa re ID Exit

6. Both Software ID Exit operations are equivalent

XXH F0H

Softwa re ID Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.2 25022

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Rat ings” ma y cause permanent damage to the de vice . This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sectio ns of this data sheet is not implied. Exposu re to absolute maxim um stress rat ing con-

ditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 5: Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

T5.1 25022

Table 6: AC Conditions of Test1

1. See Figures 14 and 15

Input Rise/Fall Time Output Load

5ns CL = 30 pF for 55 ns

CL = 100 pF for 70 ns

T6.1 25022

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Table 7: DC Operating Characteristics VDD = 4.5-5.5V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min

VDD=VDD Max

Read225 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH

ISB1 Standby VDD Current

(TTL input) 3mACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 100 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

T7.10 25022

1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 5V for SF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

Table 8: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Er ase Operation 100 µs

T8.1 25022

Table 9: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T9.0 25022

Table 10: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum f or the whole de vice. A se ctor- or block-le v el rating would

result in a higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.2 25022

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

AC Characteristics

Table 11: Read Cycle Timing Parameters VDD = 4.5-5.5V

Symbol Parameter

SST39SF010A/020A/040-55 SST39SF010A/020A/040-70

UnitsMin Max Min Max

TRC Read Cycle Time 55 70 ns

TCE Chip Enable Access Time 55 70 ns

TAA Address Access Time 55 70 ns

TOE Output Enable Access Time 35 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 25 ns

TOHZ1OE# High to High-Z Output 2 0 25 ns

TOH1Output Hold from Address Change 0 0 ns

T11.4 25022

Table 12: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 40 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TSCE Chip-Erase 100 ms

T12.1 25022

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 5: Read Cycle Timing Diagram

Figure 6: WE# Controlled Program Cycle Timing Diagram

1147 F03.1

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1147 F04.1

ADDRESS AMS-0

DQ7-0

TDH

TWPH TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 7: CE# Controlled Program Cycle Timing Diagram

Figure 8: Data# Polling Timing Diagram

1147 F05.1

ADDRESS AMS-0

DQ7-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1147 F06.1

ADDRESS A

MS-0

DD# D# D

WE#

OE#

CE#

OEH

OES

Note: AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 9: Toggle Bit Timing Diagram

Figure 10: WE# Controlled Sector-Erase Timing Diagram

1147 F07.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggled bit output is always high first.

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1147 F08.1

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. (See Table 10)

SAXX = Sector Address

Toggled bit output is always high first.

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 11: WE# Controlled Chip-Erase Timing Diagram

Figure 12: Software ID Entry and Read

1147 F17.1

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. (See Table 10)

SAXX = Sector Address

Toggled bit output is always high first.

AMS = Most significant address

1147 F09.2

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte Sequence for

Software ID Entry

TWP

TWPH TAA

BF De vice ID55AA 90

Note: Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 13: Software ID Exit and Reset

Figure 14: AC Input/Output Reference Waveforms

Figure 15: A Test Load Example

1147 F10.0

ADDRESS A

14-0

7-0

IDA

WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

1147 F11.1

REFERENCE POINTS OUTPUTINPUT

IHT

ILT

A C test in puts a re d riven at VIHT (3.0V) for a logic “1” and VILT (0V) fo r a logic “ 0”.

Measurement reference points f or inputs and outpu ts are VIT (1 .5V) an d V OT (1.5V). Input rise

and fall times (10% ↔ 90%) are <5 ns . Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1147 F12.0

T O TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 16: Byte-Program Algorithm

1147 F13.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 17: Wait Options

1147 F14.0

W ait TBP,

TSCE, or TSE

Byte

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte

Program/Erase

Initiated

Byte

Program/Erase

Initiated

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 18: Software Product Command Flowchar ts

1147 F15.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 19: Erase Command Sequence

1147 F16.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

W ait TSCE

Chip erased

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

W ait TSE

Sector erased

to FFH

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Product Ordering Information

SST 39 SF 010A - 70 - 4C - NHE

XX XX XXXX -XX-XX-XXX

Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC

P = PDIP

W = TSOP (type 1, die up , 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns

70 = 70 ns

Version

A = Special Feature Version

Device Density

040 = 4 Mbit

020 = 2 Mbit

010 = 1 Mbit

Voltage

S = 4.5-5.5V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compli-

ant”.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Note:Valid combinations are thos e products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of v alid combinations and to determine av ailability of new combi-

nations.

Valid combinations for SST39SF010A

SST39SF010A-55-4C-NHE SST39SF010A-55-4C-WHE

SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-70-4C-PHE

SST39SF010A-55-4I-NHE SST39SF010A-55-4I-WHE

SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE

Valid combinations for SST39SF020A

SST39SF020A-55-4C-NHE SST39SF020A-55-4C-WHE

SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-70-4C-PHE

SST39SF020A-55-4I-NHE SST39SF020A-55-5I-WHE

SST39SF020A-70-4I-NHE SST39SF020A-70-4I-WHE

Valid combinations for SST39SF040

SST39SF040-55-4C-NHE SST39SF040-55-4C-WHE

SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-70-4C-PHE

SST39SF040-55-4I-NHE SST39SF040-55-4I-WHE

SST39SF040-70-4I-NHE SST39SF040-70-4I-WHE

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Packaging Diagrams

Figure 20: 32-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30°

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 21: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

SST Package Code: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0°- 5°

DETAIL

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 22: 32-pin Plastic Dual In-line Pins (PDIP)

SST Package Code: PH

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7°

4 PLCS.

.600 BSC

.100 BSC .150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065 1.655

1.645

.012

.008

0°

15°

.625

.600

.550

.530

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Table 13: Revision History

Revision Description Date

02 •2002 Data Book Ma y 2002

03 •Changes to Table 7 on page 12

•Added footnote for MPF power usage and Typical conditions

•Clarified the Test Conditions for Power Supply Current and Read

parameters

•Clarified IDD Write to be Program and Erase

Mar 2003

04 •Document status changed from “Preliminary Specification” to “Data

Sheet”

•Changed IDD Program and Erase max values from 25 to 35 in Table 7

on page 12

Oct 2003

05 •2004 Data Book

•Added non-Pb MPNs and removed footnote (See page 24) Nov 2003

06 •Corrected Revision History for Version 04:

IDD max value was incorrectly stated as 30 mA instead of 35 mA A ug 2004

07 •Removed leaded parts from valid combinations. See PSN-D0PB0001 Mar 2009

08 •Changed endurance from 10,000 to 100,000 in Product Description,

page 1 Sep 2009

09 •End of Life for all 45 ns v alid combinations. See S71147(02).

•Added replacement 55 ns va lid combinations Ja n 2010

A•All 45 ns parts reinstated.

•Applied new document format

•Released document under letter revision system

•Updated spec number from S71147 to DS25022

Jul 2011

B•End of Lif e for all 45 ns valid combinations.

•Updated Table 6 and Table 11 Apr 2013

SST, Silicon Stor age Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered tr ademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Te chnology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Ref er to www .microchip .com for the most recent documentation. F or the most current

package dra wings, please see the Pac kaging Specification located at http://www . microchip .com/pac kaging.

Memory sizes denote raw storage capacity; actual usable capacity ma y be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-62077-167-9