a
ICE-Port is a trademark of Analog Devices, Inc.
DSP Microcomputer
ADSP-218xN Series
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.
PERFORMANCE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus-
tained performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
pation with 200 CLKIN cycle recovery from power-down
condition
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 256K byte of on-chip RAM, configured
Up to 48K words program memory RAM
Up to 56K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
Two independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
SYSTEM INTERFACE FEATURES
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
All inputs tolerate up to 3.6 V regardless of mode
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and pro-
gram overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Programmable wait state generation
Two double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from byte-
wide external memory, for example, EPROM, or through
internal DMA Port
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final
systems
Figure 1. Functional Block Diagram
ARITHMETIC UNITS
SHIFTERMAC
ALU
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
UP TO
48K ⴛ24-BIT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
SPORT0
SERIAL PORTS
SPORT1
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
HOST MODE
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
DAG1
DATA ADDRESS
GENERATORS
DAG2
PROGRAM
SEQUENCER
ADSP-2100 BASE
ARCHITECTURE
DATA
MEMORY
UP TO
56K ⴛ16-BIT
FULL MEMORY MODE
Rev. A | Page 2 of 48 | August 2006
ADSP-218xN
TABLE OF CONTENTS
General Description ................................................. 3
Architecture Overview ........................................... 3
Modes Of Operation .............................................. 5
Interrupts ........................................................... 5
Low-power Operation ............................................ 6
System Interface ................................................... 7
Reset .................................................................. 8
Power Supplies ..................................................... 8
Memory Architecture ............................................ 9
Bus Request and Bus Grant ................................... 14
Flag I/O Pins ..................................................... 15
Instruction Set Description ................................... 15
Development System ........................................... 15
Additional Information ........................................ 17
Pin Descriptions .................................................... 18
Memory Interface Pins ......................................... 19
Terminating Unused Pins ..................................... 19
Specifications ........................................................ 22
Recommended Operating Conditions ...................... 22
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings .................................. 23
ESD Sensitivity ................................................... 23
ESD Diode Protection .......................................... 24
Power Dissipation ............................................... 24
Environmental Conditions .................................... 25
Test Conditions .................................................. 25
Timing Specifications .......................................... 26
LQFP Package Pinout .......................................... 40
BGA Package Pinout ........................................... 42
Outline Dimensions ............................................... 45
Surface Mount Design .......................................... 46
Ordering Guide ..................................................... 47
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Miscellaneous Format Updates.......................... Universal
Applied Corrections or Additional Information to:
Clock Signals ....................................................... 8
External Crystal Connections .................................. 8
ADSP-2185 Memory Architecture ............................ 9
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings ................................... 23
ESD Diode Protection .......................................... 24
Memory Read ..................................................... 31
Memory Write .................................................... 32
Serial Ports ........................................................ 33
Outline Dimensions ............................................. 45
Ordering Guide .................................................. 47
ADSP-218xN
Rev. A | Page 3 of 48 | August 2006
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip microcom-
puters optimized for digital signal processing applications. The
high-level block diagram for the ADSP-218xN series members
appears on the previous page. All series members are pin-com-
patible and are differentiated solely by the amount of on-chip
SRAM. This feature, combined with ADSP-21xx code compati-
bility, provides a great deal of flexibility in the design decision.
Specific family members are shown in Table 1.
ADSP-218xN series members combine the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
ADSP-218xN series members integrate up to 256K bytes of on-
chip memory configured as up to 48K words (24-bit) of pro-
gram RAM, and up to 56K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery-operated portable equipment. The ADSP-218xN is
available in a 100-lead LQFP package and 144-ball BGA.
Fabricated in a high-speed, low-power, 0.18 μm CMOS process,
ADSP-218xN series members operate with a 12.5 ns instruction
cycle time. Every instruction can execute in a single pro-
cessor cycle.
The ADSP-218xN’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, ADSP-218xN series
members can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible data
moves and multifunction (one or two data moves with a com-
putation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-218xN assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram is an overall block diagram of the
ADSP-218xN series. The processor contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denor-
malization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, ADSP-218xN series members
execute looped code with zero overhead; no explicit jump
instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possi-
ble modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for
circular buffers.
Five internal buses provide efficient data transfer:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
Table 1. ADSP-218xN DSP Microcomputer Family
Device
Program Memory
(K words)
Data Memory
(K words)
ADSP-2184N 4 4
ADSP-2185N 16 16
ADSP-2186N 8 8
ADSP-2187N 32 32
ADSP-2188N 48 56
ADSP-2189N 32 48
Rev. A | Page 4 of 48 | August 2006
ADSP-218xN
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting ADSP-218xN series members to fetch two operands in a
single cycle, one from program memory and one from data
memory. ADSP-218xN series members can fetch an operand
from program memory and the next instruction in the
same cycle.
In lieu of the address and data bus for external memory connec-
tion, ADSP-218xN series members may be configured for 16-bit
Internal DMA port (IDMA port) connection to external sys-
tems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSP’s on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
ADSP-218xN to continue running from on-chip memory. Nor-
mal execution mode requires the processor to halt while buses
are granted.
ADSP-218xN series members can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORT), the
BDMA port, and the power-down circuitry. There is also a mas-
ter RESET signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
ADSP-218xN series members provide up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete syn-
chronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-218xN
SPORTs. For additional information on Serial Ports, refer to the
ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gen-
erated. Frame sync signals are active high or inverted, with
either of two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 bits to
16 bits and provide optional A-law and μ-law companding,
according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 word or 32-word, time-division multi-
plexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this
configuration.
ADSP-218xN
Rev. A | Page 5 of 48 | August 2006
MODES OF OPERATION
The ADSP-218xN series modes of operation appear in Table 2.
Setting Memory Mode
Memory Mode selection for the ADSP-218xN series is made
during chip reset through the use of the Mode C pin. This pin is
multiplexed with the DSP’s PF2 pin, so care must be taken in
how the mode selection is made. The two methods for selecting
the value of Mode C are active and passive.
Passive Configuration
Passive Configuration involves the use of a pull-up or pull-
down resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down resistance, on the
order of 10 kΩ, can be used. This value should be sufficient to
pull the pin to the desired level and still allow the pin to operate
as a programmable flag output without undue strain on the pro-
cessor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the pull-
up or pull-down resistance will hold the pin in a known state,
and will not switch.
Active Configuration
Active Configuration involves the use of a three-statable exter-
nal driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should be three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IDMA ACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven signal
and cannot be “wire-OR’ed.” Mode D = 1 and in host mode:
IACK is an open drain and requires an external pull-down, but
multiple IACK pins can be “wire-OR’ed” together.
INTERRUPTS
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
ADSP-218xN series members provide four dedicated external
interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared
with the PF7–4 pins). In addition, SPORT1 may be reconfig-
ured for IRQ0, IRQ1, FI, and FO, for a total of six external
interrupts. The ADSP-218xN also supports internal interrupts
from the timer, the byte DMA port, the two serial ports, soft-
ware, and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins
can be programmed to be either level- or edge-sensitive. IRQL0
and IRQL1 are level-sensitive and IRQE is edge-sensitive. The
priorities and vector addresses of all interrupts are shown in
Table 3.
Table 2. Modes of Operation
Mode D Mode C Mode B Mode A Booting Method
X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Full Memory Mode.
1
X 0 1 0 No automatic boot operations occur. Program execution starts at external memory
location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the
processor does not automatically use or wait for these operations.
0 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode. IACK has active pull-down. (Requires additonal hardware.)
0 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK has active pull-down.
1
1 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is
configured in Host Mode; IACK requires external pull-down. (Requires additonal
hardware.)
1 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held
off until the host writes to internal program memory location 0. Chip is configured in
Host Mode. IACK requires external pull-down.
1
1
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
Rev. A | Page 6 of 48 | August 2006
ADSP-218xN
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
ADSP-218xN series members mask all interrupts for one
instruction cycle following the execution of an instruction that
modifies the IMASK register. This does not affect serial port
autobuffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are 12 levels deep to allow interrupt, loop, and subroutine nest-
ing. The following instructions allow global enable or disable
servicing of the interrupts (including power-down), regardless
of the state of IMASK:
ENA INTS;
DIS INTS;
Disabling the interrupts does not affect serial port autobuffering
or DMA. When the processor is reset, interrupt servicing
is enabled.
LOW-POWER OPERATION
ADSP-218xN series members have three low-power modes that
significantly reduce the power dissipation when the device oper-
ates under standby conditions. These modes are:
• Power-Down
•Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
ADSP-218xN series members have a low-power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of power-
down features. Refer to the ADSP-218x DSP Hardware Refer-
ence, “System Interface” chapter, for detailed information about
the power-down feature.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscilla-
tor to save power (the processor automatically waits
approximately 4096 CLKIN cycles for the crystal oscillator
to start or stabilize), and letting the oscillator run to allow
200 CLKIN cycle start-up.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving
the power-down state.
•The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin (PWDACK) indicates when
the processor has entered power-down.
Idle
When the ADSP-218xN is in the Idle Mode, the processor waits
indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA, and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on ADSP-218xN series mem-
bers to let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
Table 3. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
Interrupt Vector Address
(Hex)
Reset (or Power-Up with PUCR = 1) 0x0000 (Highest Priority)
Power-Down (Nonmaskable) 0x002C
IRQ2 0x0004
IRQL1 0x0008
IRQL0 0x000C
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
IRQE 0x0018
BDMA Interrupt 0x001C
SPORT1 Transmit or IRQ1 0x0020
SPORT1 Receive or IRQ0 0x0024
Timer 0x0028 (Lowest Priority)
ADSP-218xN
Rev. A | Page 7 of 48 | August 2006
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xN series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming nor-
mal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xN series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Figure 2. Basic System Interface
Insert system interface diagram here
1/2 ⴛCLOCK
OR
CRYSTAL
FL0–2
CLKIN
XTAL
SERIAL
DEVICE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SERIAL
DEVICE
A0–A21
DATA
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
DATA
ADDR
DATA
ADDR
2048 LOCATIONS
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
D23–0
A13–0
D23–8
A10–0
D15–8
D23–16
A13–0
14
24
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
DATA23–0
ADSP-218xN
CS
CS
1/2 ⴛCLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0–2
SERIAL
DEVICE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
16
IDMA PORT
IRD/D6
IS/D4
IAL/D5
IACK/D3
IAD15-0
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
1
16
A0
DATA23–8
IOMS
BMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
HOST MEMORY MODE
FULL MEMORY MODE
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
WR
RD
SYSTEM
INTERFACE
OR
µCONTROLLER
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
IOMS
BMS
PMS
CMS
BR
BG
BGH
PWD
PWDACK
WR
RD
ADSP-218xN
DMS TWO 8K
DM SEGMENTS
PMS
ADDR13–0
IRQL1/PF6
IWR/D7
Rev. A | Page 8 of 48 | August 2006
ADSP-218xN
Clock Signals
ADSP-218xN series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the power-
down state. For additional information, refer to the ADSP-218x
DSP Hardware Reference, for detailed information on this
power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xN series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal instruc-
tion clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xN series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
RESET
The RESET signal initiates a master reset of the ADSP-218xN.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulse-width specification (t
RSP
).
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, the use of an exter-
nal Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from on-
chip program memory location 0x0000 once boot loading
completes.
POWER SUPPLIES
ADSP-218xN series members have separate power supply con-
nections for the internal (V
DDINT
) and external (V
DDEXT
) power
supplies. The internal supply must meet the 1.8 V requirement.
The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up to
3.6 V, regardless of the external supply voltage. This feature pro-
vides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V
components.
Figure 3. External Crystal Connections
CLKIN CLKOUTXTAL
DSP
1M⍀
ADSP-218xN
Rev. A | Page 9 of 48 | August 2006
MEMORY ARCHITECTURE
The ADSP-218xN series provides a variety of memory and
peripheral interface options. The key functional groups are Pro-
gram Memory, Data Memory, Byte Memory, and I/O. Refer to
Figure 4 through Figure 9, Table 4 on Page 11, and Table 5 on
Page 11 for PM and DM memory allocations in the ADSP-
218xN series.
Figure 4. ADSP-2184 Memory Architecture
Figure 5. ADSP-2185 Memory Architecture
Figure 6. ADSP-2186 Memory Architecture
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY 0
(RESERVED)
RESERVED
MODEB = 0
0x3FFF
0x2000
0x0000
0x0FFF
0x1000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x3000
0x2FFF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
4064 RESERVED
WORDS
DM OVERLAY 0
(RESERVED)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY 0
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY 0
(RESERVED)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0
(RESERVED)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
Rev. A | Page 10 of 48 | August 2006
ADSP-218xN
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The member
DSPs of this series have up to 48K words of Program Memory
RAM on chip, and the capability of accessing up to two 8K
external memory overlay spaces, using the external data bus.
Figure 7. ADSP-2187 Memory Architecture
Figure 8. ADSP-2188 Memory Architecture
Figure 9. ADSP-2189 Memory Architecture
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY 0,4,5
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY 0,4,5
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY
0,4,5,6,7
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY
0,4,5,6,7,8
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
PROGRAM MEMORY
PM OVERLAY 1,2
(EXTERNAL PM)
INTERNAL PM
PM OVERLAY 0,4,5
(INTERNAL PM)
MODEB = 0
0x3FFF
0x2000
0x0000
0x1FFF
0x3FFF
0x2000
0x0000
0x3FE0
0x3FDF
0x1FFF
DATA MEMORY
DM OVERLAY 1,2
(EXTERNAL DM)
INTERNAL DM
32 MEMORY-MAPPED
CONTROL REGISTERS
DM OVERLAY
0,4,5,6,7
(INTERNAL DM)
PROGRAM MEMORY
RESERVED
EXTERNAL PM
MODEB = 1
0x3FFF
0x2000
0x0000
0x1FFF
ADSP-218xN
Rev. A | Page 11 of 48 | August 2006
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is only 16 bits wide.
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped con-
trol registers. The ADSP-218xN series has up to 56K words of
Data Memory RAM on-chip. Part of this space is used by 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register and the wait state mode bit.
Data Memory (Host Mode) allows access to all internal mem-
ory. External overlay access is limited by a single external
address line (A0).
Memory-Mapped Registers (New to the ADSP-218xM and
N series)
ADSP-218xN series members have three memory-mapped reg-
isters that differ from other ADSP-21xx Family DSPs. The slight
modifications to these registers (Wait State Control, Program-
mable Flag and Composite Select Control, and System Control)
provide the ADSP-218xN’s wait state and BMS control features.
Default bit values at reset are shown; if no value is shown, the bit
is undefined at reset. Reserved bits are shown on a grey field.
These bits should always be written with zeros.
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional external
memory space called I/O space. This space is designed to sup-
port simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
I/O space supports 2048 locations of 16-bit wide data. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
Table 4. PMOVLAY Bits
Processor PMOVLAY Memory A13 A12–0
ADSP-2184N No Internal Overlay
Region
Not Applicable Not Applicable Not Applicable
ADSP-2185N 0 Internal Overlay Not Applicable Not Applicable
ADSP-2186N No Internal Overlay
Region
Not Applicable Not Applicable Not Applicable
ADSP-2187N 0, 4, 5 Internal Overlay Not Applicable Not Applicable
ADSP-2188N 0, 4, 5, 6, 7 Internal Overlay Not Applicable Not Applicable
ADSP-2189N 0, 4, 5 Internal Overlay Not Applicable Not Applicable
All Processors 1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF
All Processors 2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF
Table 5. DMOVLAY Bits
Processor DMOVLAY Memory A13 A12–0
ADSP-2184N No Internal Overlay Region Not Applicable Not Applicable Not Applicable
ADSP-2185N 0 Internal Overlay Not Applicable Not Applicable
ADSP-2186N No Internal Overlay Region Not Applicable Not Applicable Not Applicable
ADSP-2187N 0, 4, 5 Internal Overlay Not Applicable Not Applicable
ADSP-2188N 0, 4, 5, 6, 7, 8 Internal Overlay Not Applicable Not Applicable
ADSP-2189N 0, 4, 5, 6, 7 Internal Overlay Not Applicable Not Applicable
All Processors 1 External Overlay 1 0 13 LSBs of Address
Between 0x0000 and
0x1FFF
All Processors 2 External Overlay 2 1 13 LSBs of Address
Between 0x0000 and
0x1FFF
Rev. A | Page 12 of 48 | August 2006
ADSP-218xN
IOWAIT0–3 as shown in Figure 10, which in combination with
the wait state mode bit, specify up to 15 wait states to be auto-
matically generated for each of four regions. The wait states act
on address ranges, as shown in Table 6.
Note: In Full Memory Mode, all 2048 locations of I/O space are
directly addressable. In Host Memory Mode, only address pin
A0 is available; therefore, additional logic is required externally
to achieve complete addressability of the 2048 I/O
space locations.
Composite Memory Select
ADSP-218xN series members have a programmable memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal
is generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can com-
bine their functionality. Each bit in the CMSSEL register, when
set, causes the CMS signal to be asserted when the selected
memory select is asserted. For example, to use a 32K word
memory to act as both program and data memory, set the PMS
and DMS bits in the CMSSEL register and use the CMS pin to
drive the chip select of the memory, and use either DMS or PMS
as the additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
See Figure 11 and Figure 12 for illustration of the programma-
ble flag and composite control register and the system
control register.
Byte Memory Select
The ADSP-218xN’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and a flash memory could be connected to CMS. Because
at reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS sig-
nal to respond to BMS, enabling the flash memory.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data. Byte
memory is accessed using the BDMA feature. The byte memory
space consists of 256 pages, each of which is 16K ⴛ8bits.
The byte memory space on the ADSP-218xN series supports
read and write operations as well as four different data formats.
The byte memory uses data bits 15–8 for data. The byte mem-
ory uses data bits 23–16 and address bits 13–0 to create a 22-bit
address. This allows up to a 4 megabit ⴛ8 (32 megabit) ROM
or RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller (Figure 13) allows loading
and storing of program instructions and data using the byte
memory space. The BDMA circuit is able to access the byte
memory space while the processor is operating normally and
steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
Table 6. Wait States
Address Range Wait State Register
0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit
0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit
0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit
0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit
Figure 10. Wait State Control Register
Insert Wait State Control Register
DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
DM(0x3FFE)
WAIT STATE CONTROL
1111111111111111
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES,
RANGING FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
RANGING FROM 0 TO 15)
Figure 11. Programmable Flag and Composite Control Register
Figure 12. System Control Register
BMWAIT CMSSEL
0=DISABLECMS
1=ENABLECMS
DM(0x3FE6)
PFTYPE
0=INPUT
1=OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
1111101100000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROGRAMMABLE FLAG AND COMPOSITE
SELECT CONTROL
RESERVED,ALWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1=ENABLE
DM(0x3FFF)
SYSTEM CONTROL
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0=FI,FO,IRQ0,IRQ1,SCLK
1=SPORT1
DISABLE BMS
0 = ENABLE BMS
1=DISABLEBMS
PWAIT
PROGRAM MEMORY
WAIT STATES
0000010000000111
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS
SHOULD ALWAYS BE WRITTEN WITH ZEROS.
RESERVED
SET TO 0
ADSP-218xN
Rev. A | Page 13 of 48 | August 2006
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number of
8-bit accesses are done from the byte memory space to build the
word size selected. Table 7 shows the data formats supported by
the BDMA circuit.
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be on-
chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte mem-
ory accesses.
The BDMA Context Reset bit (BCR) controls whether the pro-
cessor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. Set these bits as indicated in
Figure 13.
Note: BDMA cannot access external overlay memory regions 1
and 2.
The BMWAIT field, which has four bits on ADSP-218xN series
members, allows selection up to 15 wait states for BDMA
transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and ADSP-218xN series members. The
port is used to access the on-chip program memory and data
memory of the DSP with only one DSP cycle per word over-
head. The IDMA port cannot, however, be used to write to the
DSP’s memory-mapped control registers. A typical IDMA
transfer process is shown as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selec-
tion into the DSP’s IDMA control registers. If Bit 15 = 1,
the values of Bits 7–0 represent the IDMA overlay; Bits
14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13–0
represent the starting address of internal memory to be
accessed and Bit 14 reflects PM or DM for access. Set
IDDMOVLAY and IDPMOVLAY bits in the IDMA over-
lay register as indicted in Table 8.
4. Host uses IS and IRD (or IWR) to read (or write) DSP
internal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
Figure 13. BDMA Control Register
Table 7. Data Formats
BTYPE
Internal Memory
Space Word Size Alignment
00 Program Memory 24 Full Word
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
11 Data Memory 8 LSBs
BDMA CONTROL
BMPAGE BTYPE
BDIR
0=LOADFROMBM
1=STORETOBM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0000000000001000
15 14 13 12 11109876543210
DM (0x3FE3)
BDMA
OVERLAY
BITS
(SEE TABLE 12)
Table 8. IDMA/BDMA Overlay Bits
Processor
IDMA/BDMA
PMOVLAY
IDMA/BDMA
DMOVLAY
ADSP-2184N 0 0
ADSP-2185N 0 0
ADSP-2186N 0 0
ADSP-2187N 0, 4, 5 0, 4, 5
ADSP-2188N 0, 4, 5, 6, 7 0, 4, 5, 6, 7, 8
ADSP-2189N 0, 4, 5 0, 4, 5, 6, 7
Rev. A | Page 14 of 48 | August 2006
ADSP-218xN
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-218xN
is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This
increases throughput as the address does not have to be sent for
each memory access.
IDMA port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or PM
access. The falling edge of the IDMA address latch signal (IAL)
or the missing edge of the IDMA select signal (IS) latches this
value into the IDMAA register.
Once the address is stored, data can be read from, or written to,
the ADSP-218xN’s on-chip memory. Asserting the select line
(IS) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-218xN that a particular transac-
tion is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch enable
(IAL) directs the ADSP-218xN to write the address onto the
IAD14–0 bus into the IDMA Control Register (Figure 14). If Bit
15 is set to 0, IDMA latches the address. If Bit 15 is set to 1,
IDMA latches into the OVLAY register. This register, also
shown in Figure 14, is memory-mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) cannot be
read back by the host.
When Bit 14 in 0x3FE7 is set to zero, short reads use the timing
shown in Figure 36 on Page 38. When Bit 14 in 0x3FE7 is set to
1, timing in Figure 37 on Page 39 applies for short reads in short
read only mode. Set IDDMOVLAY and IDPMOVLAY bits in
the IDMA overlay register as indicated in Table 8. Refer to the
ADSP-218x DSP Hardware Reference for additional details.
Note: In full memory mode all locations of 4M-byte memory
space are directly addressable. In host memory mode, only
address pin A0 is available, requiring additional external logic to
provide address information for the byte.
Bootstrap Loading (Booting)
ADSP-218xN series members have two mechanisms to allow
automatic loading of the internal program memory after reset.
The method for booting is controlled by the Mode A, B, and C
configuration bits.
When the mode pins specify BDMA booting, the ADSP-218xN
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is set
to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addres-
ses to boot memory must be constructed externally to the
ADSP-218xN. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
ADSP-218xN series members can also boot programs through
its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A
= 1, the ADSP-218xN boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execu-
tion is held off until the host writes to on-chip program memory
location 0.
BUS REQUEST AND BUS GRANT
ADSP-218xN series members can relinquish control of the data
and address buses to an external device. When the external
device requires access to memory, it asserts the Bus Request
Figure 14. IDMA OVLAY/Control Registers
IDMA OVERLAY
DM (0x3FE7)
RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY
000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORT READ
ONLY
0 = DISABLE
1 = ENABLE
IDMA CONTROL (U = UNDEFINED AT RESET)
DM (0x3FE0)
IDMAA ADDRESS
UUUUUUUUUUUUUUU
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMAD DESTINATION MEMORY
TYPE
0=PM
1=DM
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE
BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.
0
RESERVED SET TO 0
0
RESERVED SET TO 0
(SEE TABLE 12)
ADSP-218xN
Rev. A | Page 15 of 48 | August 2006
(BR) signal. If the ADSP-218xN is not performing an external
memory access, it responds to the active BR input in the follow-
ing processor cycle by:
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-218xN will not halt program
execution until it encounters an instruction that requires an
external memory access.
If an ADSP-218xN series member is performing an external
memory access when the external device asserts the BR signal, it
will not three-state the memory interfaces nor assert the BG sig-
nal until the processor cycle after the access completes. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when an ADSP-218xN series member
requires the external bus for a memory or BDMA access, but is
stopped. The other device can release the bus by deasserting bus
request. Once the bus is released, the ADSP-218xN deasserts BG
and BGH and executes the external memory access.
FLAG I/O PINS
ADSP-218xN series members have eight general-purpose pro-
grammable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the
ADSP-218xN’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, ADSP-218xN series
members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.
FL0 to FL2 are dedicated output flags. FI and FO are available as
an alternate configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device con-
figuration during reset.
INSTRUCTION SET DESCRIPTION
The ADSP-218xN series assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the follow-
ing benefits:
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical arith-
metic add instruction, such as AR = AX0 + AY0, resembles
a simple equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be
relocated to utilize on-chip memory and conform to the
ADSP-218xN’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional
jump, call, return, or arithmetic instructions, the condition
can be checked and the operation executed in the same
instruction cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction, with up to two fetches or one write
to processor memory space, during a single instruc-
tion cycle.
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware
development tools supports the ADSP-218xN series. The DSP
tools include an integrated development environment, an evalu-
ation kit, and a serial port emulator.
VisualDSP++
®
†
is an integrated development environment,
allowing for fast and easy development, debug, and deployment.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder); a linker; a
PROM-splitter utility; a cycle-accurate, instruction-level simu-
lator; a C compiler; and a C run-time library that includes DSP
and mathematical functions.
Debugging both C and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
†
VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. A | Page 16 of 48 | August 2006
ADSP-218xN
• Fill and dump memory
• Source level debugging
The VisualDSP++ IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the ADSP-
218xN development tools, including the syntax highlighting in
the VisualDSP++ editor. This capability controls how the devel-
opment tools process inputs and generate outputs.
The ADSP-2189M EZ-KIT Lite
®
†
provides developers with a
cost-effective method for initial evaluation of the powerful
ADSP-218xN DSP family architecture. The ADSP-2189M EZ-
KIT Lite includes a stand-alone ADSP-2189M DSP board sup-
ported by an evaluation suite of VisualDSP++. With this EZ-
KIT Lite, users can learn about DSP hardware and software
development and evaluate potential applications of the ADSP-
218xN series. The ADSP-2189M EZ-KIT Lite provides an evalu-
ation suite of the VisualDSP++ development environment with
the C compiler, assembler, and linker. The size of the DSP exe-
cutable that can be built using the EZ-KIT Lite tools is limited to
8K words.
The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
•DSP Demonstration Programs
• Evaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE
®
‡
Emulator provides an easier and
more cost-effective method for engineers to develop and opti-
mize DSP systems, shortening product development cycles for
faster time-to-market. ADSP-218xN series members integrate
on-chip emulation support with a 14-pin ICE-Port interface.
This interface provides a simpler target board connection that
requires fewer mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. ADSP-218xN series members
need not be removed from the target system when using the EZ-
ICE, nor are any adapters needed. Due to the small footprint of
the EZ-ICE connector, emulation can be supported in final
board designs.The EZ-ICE performs a full range of functions,
including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting
and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
Designing an EZ-ICE-Compatible System
ADSP-218xN series members have on-chip emulation support
and an ICE-Port, a special set of pins that interface to the EZ-
ICE. These features allow in-circuit emulation without replac-
ing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target sys-
tems must have a 14-pin connector to accept the EZ-ICE’s in-
circuit probe, a 14-pin plug.
Note: The EZ-ICE uses the same V
DD
voltage as the V
DD
voltage
used for V
DDEXT
. Because the input pins of the ADSP-218xN
series members are tolerant to input voltages up to 3.6 V,
regardless of the value of V
DDEXT
, the voltage setting for the EZ-
ICE must not exceed 3.3 V.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information
is being used (as discussed in Setting Memory Mode on Page 5),
it does not matter that the mode information is latched by an
emulator reset. However, if the RESET pin is being used as a
method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 15. This circuit forces the value located on the Mode A
pin to logic high, regardless of whether it is latched via the
RESET or ERESET pin.
The ICE-Port interface consists of the following ADSP-218xN
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and
ELOUT.
These ADSP-218xN pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the
ADSP-218xN and the connector must be kept as short as possi-
ble, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG, RESET,
and GND.
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
‡
EZ-ICE is a registered trademark of Analog Devices, Inc.
Figure 15. Mode A Pin/EZ-ICE Circuit
PROGRAMMABLE I/O
MODE A/PF0
RESET
ERESET
ADSP-218xN
1k⍀
ADSP-218xN
Rev. A | Page 17 of 48 | August 2006
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-218xN in the target system. This causes the proces-
sor to use its ERESET, EBR, and EBG pins instead of the RESET,
BR, and BG pins. The BG output is three-stated. These signals
do not need to be jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable and
a 14-pin female plug. The female plug is plugged onto the 14-
pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 16. This connector must be added to the target board
design to use the EZ-ICE. Be sure to allow enough room in the
system to fit the EZ-ICE probe onto the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1ⴛ0.1 inch. The pin strip header must have at least
0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE emula-
tor, it must comply with the following memory interface
guidelines:
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case device
timing requirements and switching characteristics as specified
in this data sheet. The performance of the EZ-ICE may
approach published worst-case specification for some memory
access timing requirements and switching characteristics.
Note: If the target does not meet the worst-case chip specifica-
tion for memory access parameters, the circuitry may not be
able to be emulated at the desired CLKIN frequency. Depending
on the severity of the specification violation, the system may be
difficult to manufacture, as DSP components statistically vary in
switching characteristic and timing requirements, within pub-
lished limits.
Restriction: All memory strobe signals on the ADSP-218xN
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed
when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design the system to be compatible with
the following system interface signal changes introduced by the
EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.
•EZ-ICE emulation ignores RESET
and BR, when
single-stepping.
•EZ-ICE emulation ignores RESET
and BR when in Emula-
tor Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
ADDITIONAL INFORMATION
This data sheet provides a general overview of ADSP-218xN
series functionality. For additional information on the architec-
ture and instruction set of the processor, refer to the ADSP-218x
DSP Hardware Reference and the ADSP-218x DSP Instruction
Set Reference.
Figure 16. Target Board Connector for EZ-ICE
ⴛ
12
34
56
78
910
11 12
13 14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Rev. A | Page 18 of 48 | August 2006
ADSP-218xN
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead LQFP
package and a 144-ball BGA package. In order to maintain max-
imum functionality and reduce package size and pin count,
some serial port, programmable flag, interrupt and external bus
pins have dual, multiplexed functionality. The external bus pins
are configured during RESET only, while serial port pins are
software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed
pins. In cases where pin functionality is reconfigurable, the
default state is shown in plain text in Table 9, while alternate
functionality is shown in italics.
Table 9. Common-Mode Pins
Pin Name No. of Pins I/O Function
RESET 1 I Processor Reset Input
BR 1IBus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1OMemory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2 1 I Edge- or Level-Sensitive Interrupt Request
1
PF7 I/O Programmable I/O Pin
IRQL1 1 I Level-Sensitive Interrupt Requests
1
PF6 I/O Programmable I/O Pin
IRQL0 1 I Level-Sensitive Interrupt Requests
1
PF5 I/O Programmable I/O Pin
IRQE 1 I Edge-Sensitive Interrupt Requests
1
PF4 I/O Programmable I/O Pin
Mode D 1 I Mode Select Input—Checked Only During RESET
PF3 I/O Programmable I/O Pin During Normal Operation
Mode C 1 I Mode Select Input—Checked Only During RESET
PF2 I/O Programmable I/O Pin During Normal Operation
Mode B 1 I Mode Select Input—Checked Only During RESET
PF1 I/O Programmable I/O Pin During Normal Operation
Mode A 1 I Mode Select Input—Checked Only During RESET
PF0 I/O Programmable I/O Pin During Normal Operation
CLKIN 1 I Clock Input
XTAL 1 O Quartz Crystal Output
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1–0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO
2
PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Acknowledge Control Output
FL0, FL1, FL2 3 O Output Flags
V
DDINT
2IInternal V
DD
(1.8 V) Power (LQFP)
V
DDEXT
4IExternal V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
GND 10 I Ground (LQFP)
ADSP-218xN
Rev. A | Page 19 of 48 | August 2006
MEMORY INTERFACE PINS
ADSP-218xN series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. Table 10 and Table 11 list the active signals at specific
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a sig-
nal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on
Page 41 and Table 28 on Page 43.
TERMINATING UNUSED PINS
Table 12 shows the recommendations for terminating unused
pins.
V
DDINT
4IInternal V
DD
(1.8 V) Power (BGA)
V
DDEXT
7IExternal V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (BGA)
GND 20 I Ground (BGA)
EZ-Port 9 I/O For Emulation Use
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
Table 9. Common-Mode Pins (Continued)
Pin Name No. of Pins I/O Function
Table 10. Full Memory Mode Pins (Mode C = 0)
Pin Name No. of Pins I/O Function
A13–0 14 O Address Output Pins for Program, Data, Byte, and I/O Spaces
D23–0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Table 11. Host Mode Pins (Mode C = 1)
Pin Name No. of Pins I/O Function
IAD15–0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Program, Data, or Byte Access
1
D23–8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR 1IIDMA Write Enable
IRD 1 I IDMA Read Enable
IAL 1 I IDMA Address Latch Pin
IS 1IIDMA Select
IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain
1
In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Table 12. Unused Pin Terminations
Pin Name
1
I/O
3-State
(Z)
2
Reset
State Hi-Z
3
Caused By Unused Configuration
XTAL O O Float
CLKOUT O O Float
4
A13–1 or O (Z) Hi-Z BR, EBR Float
IAD12–0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
Rev. A | Page 20 of 48 | August 2006
ADSP-218xN
D23–8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR II High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD IIBR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
D4 or I/O (Z) Hi-Z BR, EBR Float
IS II High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D2–0 or I/O (Z) Hi-Z BR, EBR Float
IAD15–13 I/O (Z) Hi-Z IS Float
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR II High (Inactive)
BG O (Z) O EE Float
BGH OO Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float
5
IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float
5
IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float
5
IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to
1, Let Float
5
PWD II High
SCLK0 I/O I Input = High or Low, Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O I High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low, Output = Float
RFS1/IRQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/IRQ1 I/O I High or Low
DT1/FO O O Float
EE I I Float
EBR II Float
EBG OO Float
Table 12. Unused Pin Terminations (Continued)
Pin Name
1
I/O
3-State
(Z)
2
Reset
State Hi-Z
3
Caused By Unused Configuration
ADSP-218xN
Rev. A | Page 21 of 48 | August 2006
ERESET II Float
EMS OO Float
EINT II Float
ECLK I I Float
ELIN I I Float
ELOUT O O Float
1
CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.
2
All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
3
Hi-Z = High Impedance.
4
If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
5
If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts
and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.
Table 12. Unused Pin Terminations (Continued)
Pin Name
1
I/O
3-State
(Z)
2
Reset
State Hi-Z
3
Caused By Unused Configuration
Rev. A | Page 22 of 48 | August 2006
ADSP-218xN
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
1
1
Specifications subject to change without notice.
K Grade (Commercial) B Grade (Industrial)
Unit
Min Max Min Max
V
DDINT
1.71 1.89 1.8 2.0 V
V
DDEXT
1.71 3.6 1.8 3.6 V
V
INPUT2
2
The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max V
IH
), but voltage compliance (on outputs, V
OH
) depends on the input V
DDEXT
, because V
OH
(max)
approximately equals V
DDEXT
(max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–A1, PF7–PF0) and input-
only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
V
IL
= – 0.3 V
IH
= + 3.6 V
IL
= – 0.3 V
IH
= + 3.6 V
T
AMB
0 70–40 +85°C
Parameter
1
Description Test Conditions Min Typ Max Unit
V
IH
Hi-Level Input Voltage
2,
3
@ V
DDEXT
= 1.71 V to 2.0 V,
V
DDINT
= max
@ V
DDEXT
= 2.1 V to 3.6 V,
V
DDINT
= max
1.25
1.7
V
V
V
IL
Lo-Level Input Voltage
2,
3
@ V
DDEXT
≤ 2.0 V,
V
DDINT
= min
@ V
DDEXT
≥ 2.0 V,
V
DDINT
= min
0.6
0.7
V
V
V
OH
Hi-Level Output Voltage
2,
4,
5
@ V
DDEXT
= 1.71 V to 2.0 V,
I
OH
= – 0.5 mA
@ V
DDEXT
= 2.1 V to 2.9 V,
I
OH
= – 0.5 mA
@ V
DDEXT
= 3.0 V to 3.6 V,
I
OH
= – 0.5 mA
@ V
DDEXT
= 1.71 V to 3.6 V,
I
OH
= – 100 μA
6
1.35
2.0
2.4
V
DDEXT
– 0.3
V
V
V
V
V
OL
Lo-Level Output Voltage
2,
4,
5
@ V
DDEXT
= 1.71 V to 3.6 V,
I
OL
= 2.0 mA
0.4 V
I
IH
Hi-Level Input Current
3
@ V
DDINT
= max,
V
IN
= 3.6 V
10 μA
I
IL
Lo-Level Input Current
3
@ V
DDINT
= max,
V
IN
= 0 V
10 μA
I
OZH
Three-State Leakage Current
7
@ V
DDEXT
= max,
V
IN
= 3.6 V
8
10 μA
I
OZL
Three-State Leakage Current
7
@ V
DDEXT
= max,
V
IN
= 0 V
8
10 μA
I
DD
Supply Current (Idle)
9
@ V
DDINT
= 1.8 V,
t
CK
= 12.5 ns,
T
AMB
= 25°C
6mA
I
DD
Supply Current (Dynamic)
10
@ V
DDINT
= 1.8 V,
t
CK
= 12.5 ns
11
,
T
AMB
= 25°C
25 mA
ADSP-218xN
Rev. A | Page 23 of 48 | August 2006
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
I
DD
Supply Current (Idle)
9
@ V
DDINT
= 1.9 V,
t
CK
= 12.5 ns,
T
AMB
= 25°C
6.5 mA
I
DD
Supply Current (Dynamic)
10
@ V
DDINT
= 1.9 V,
t
CK
= 12.5 ns
11
,
T
AMB
= 25°C
26 mA
I
DD
Supply Current (Power-Down)
12
@ V
DDINT
= 1.8 V,
T
AMB
= 25°C
in Lowest Power Mode
100 μA
C
I
Input Pin Capacitance
3,
6
@ V
IN
= 1.8 V,
f
IN
= 1.0 MHz,
T
AMB
= 25°C
8pF
C
O
Output Pin Capacitance
6, 7, 12,
13
@ V
IN
= 1.8 V,
f
IN
= 1.0 MHz,
T
AMB
= 25°C
8pF
1
Specifications subject to change without notice.
2
Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.
5
Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to V
DDEXT
and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.
8
0 V on BR.
9
Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD
or GND.
10
I
DD
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type
6, and 20% are idle instructions.
11
V
IN
= 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.
12
See ADSP-218x DSP Hardware Reference for details.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Parameter
1
Description Test Conditions Min Typ Max Unit
Parameter Rating
Internal Supply Voltage (V
DDINT
)
1
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
–0.3 V to +2.2 V
External Supply Voltage (V
DDEXT
)–0.3 V to +4.0 V
Input Voltage
2
2
Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1,
A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
–0.5 V to +4.0 V
Output Voltage Swing
3
3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2–0, BGH).
–0.5 V to V
DDEXT
+0.5 V
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-218xN features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 24 of 48 | August 2006
ADSP-218xN
ESD DIODE PROTECTION
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the core
and I/O power supplies, as shown in Figure 17. It protects the
ADSP-218xN processor from partially powering the I/O supply.
Including a Schottky diode will shorten the delay between the
supply ramps and thus prevent damage to the ESD diode pro-
tection circuitry. With this technique, if the core rail rises ahead
of the I/O rail, the Schottky diode pulls the I/O rail along with
the core rail.
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output: C ⴛ
V
DD2
ⴛ f
where:
C = load capacitance.
f = output switching frequency.
Example: In an application where external data memory is used
and no other outputs are active, power dissipation is calculated
as follows:
Assumptions:
• External data memory is accessed every cycle with 50% of
the address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• Application operates at V
DDEXT
= 3.3 V and t
CK
= 30 ns.
Total Power Dissipation = P
INT
+ (C ⴛV
DDEXT2
ⴛ f)
P
INT
= internal power dissipation from Figure 22 on Page 27.
(C ⴛ V
DDEXT2
ⴛ f) is calculated for each output, as in the exam-
ple in Table 13.
Figure 17. Dual Voltage Schottky Diode
I/O VOLTAGE
REGULATOR
CORE
VOLTAGE
REGULATOR
VDDEXT
VDDINT
ADSP-218xN
DC INPUT
SOURCE
Table 13. Example Power Dissipation Calculation
1
Parameters No. of Pins × C (pF) × V
DDEXT2
(V) × f (MHz) PD (mW)
Address 7 10 3.3
2
20.0 15.25
Data Output, WR 9103.3
2
20.0 19.59
RD 1103.3
2
20.0 2.18
CLKOUT, DMS 2103.3
2
40.0 8.70
45.72
1
Total power dissipation for this example is P
INT
+ 45.72 mW.
ADSP-218xN
Rev. A | Page 25 of 48 | August 2006
ENVIRONMENTAL CONDITIONS
TEST CONDITIONS Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
, as
shown in Figure 20. The time is the interval from when a refer-
ence signal reaches a high or low voltage level to when the
output voltages have changed by 0.5 V from the measured out-
put high or low voltage.
The decay time, t
DECAY
, is dependent on the capacitive load, C
L
,
and the current load, i
L
, on the output pin. It can be approxi-
mated by the following equation:
from which
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 20. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Table 14. Thermal Resistance
Rating Description
1
1
Where the Ambient Temperature Rating (T
AMB
) is:
T
AMB
= T
CASE
– (PD × θ
CA
)
T
CASE
= Case Temperature in °C
PD = Power Dissipation in W
Symbol
LQFP
(°C/W)
BGA
(°C/W)
Thermal Resistance (Case-
to-Ambient)
θ
CA
48 63.3
Thermal Resistance
(Junction-to-Ambient)
θ
JA
50 70.7
Thermal Resistance
(Junction-to-Case)
θ
JC
27.4
Figure 18. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Figure 19. Equivalent Loading for AC Measurements (Including All Fixtures)
1.5V
OUTPUT
INPUT
1.5V
2.0V
0.8V
TO
OUTPUT
PIN 50pF
1.5V
IOH
IOL
Figure 20. Output Enable/Disable
2.0V
1.0V
tENA
REFERENCE
SIGNAL
OUTPUT
tDECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
tDIS
tMEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) + 0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
tDECAY
CL0.5V×
iL
------------------------
=
tDIS tMEASURED tDECAY
–=
Rev. A | Page 26 of 48 | August 2006
ADSP-218xN
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently,
parameters cannot be added up meaningfully to derive
longer times.
Timing Notes
Switching characteristics specify how the processor changes its
signals. Designers have no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics tell
what the processor will do in a given circumstance. Switching
characteristics can also be used to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Frequency Dependency For Timing Specifications
t
CK
is defined as 0.5 t
CKI
. The ADSP-218xN uses an input clock
with a frequency equal to half the instruction rate. For example,
a 40 MHz input clock (which is equivalent to 25 ns) yields a
12.5 ns processor cycle (equivalent to 80 MHz). t
CK
values
within the range of 0.5 t
CKI
period should be substituted for all
relevant timing parameters to obtain the specification value.
Example: t
CKH
= 0.5 t
CK
– 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25 ns
Output Drive Currents
Figure 21 shows typical I-V characteristics for the output driv-
ers on the ADSP-218xN series.The curves represent the current
drive capability of the output drivers as a function of
output voltage.
Figure 23 shows the typical power-down supply current.
Capacitive Loading
Figure 24 and Figure 25 show the capacitive loading characteris-
tics of the ADSP-218xN.
Figure 21. Typical Output Driver Characteristics
for V
DDEXT
at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
VOL
SOURCE VOLTAGE – V
00.51.0
SOURCECURRENT–mA
60
0
–20
–40
–60
40
20
VDDEXT =3.6V@–40ⴗC
VDDEXT =3.3V@+25ⴗC
VDDEXT = 1.8/2.5V @ +85ⴗC
VDDEXT =2.5V@+85ⴗC
V
DDEXT
= 3.6V @ –40
ⴗ
C
80
–80 1.5 2.0 2.5 3.0 3.5 4.0
VDDEXT = 1.8/2.5V @ +85ⴗC
VOH VDDEXT =3.3V@+25ⴗC
VDDEXT =1.8V@+85ⴗC
ADSP-218xN
Rev. A | Page 27 of 48 | August 2006
Figure 22. Power vs. Frequency
2.0
POWER(P
IDLEn
)–mW
8.5mW
3.8mW
3.4mW
4.3mW
10.5mW
POWER, IDLE nMO DE S2
1/tCK –MHz
4.0
6.0
8.0
10.0
12.0
0.0
5.0
POWER(P
IDLE
)–mW
POWER, IDLE1, 2, 4
1/tCK –MHz
6.0
7.0
8.0
9.0
10.0
11.0
1/tCK –MHz
6055
POWER, INTERNAL1, 2, 3
POWER(P
INT
)–mW
20 65 70 75 80 85
35
40
45
50
55
60
25
30
NOTES
VALID FOR ALL TEMPERATURE GRADES.
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT
LOADS.
TYP ICAL POWER DISS IPATION AT 1.8V OR 1.9V VDDINT AND
25°C, EX CEPT WHERE SPE CIFIED.
IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS
EXECUTING FROM INTERNAL MEMORY. 50% OF THE
INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13,
14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE
INSTRUCTIONS.
IDLE REFERS TO STATE OF OPERATION DURING EXECUTION
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO
EITHE R VDD OR GND.
1
2
3
4
42mW
55mW
V
DDINT
=2.0V
50mW
V
DDINT
=1.9V
38mW
34mW
45mW
V
DDINT
=1.8V
30mW
40mW
V
DDINT
=1.71V
6055 65 70 75 80 8 5
12.0
13.0
14.0
15.0
10.5m W
13.5mW
VDDINT=2.0V
12mW
V
DDINT
=1.9V
9.5mW
8.5mW
10.5mW
V
DDINT
=1.8V
7.5mW
9mW
V
DDINT
=1.71V
6055 65 70 75 80 8 5
4.9mW
4.2mW 4.7mW
5.2mW
12.0mW
9.5mW
VDD CORE = 1.9V
VDD CORE = 1.8V
Figure 23. Typical Power-Down Current
Figure 24. Typical Output Rise Time vs. Load Capacitance (at Maximum
Ambient Operating Temperature)
Figure 25. Typical Output Valid Delay or Hold vs. Load Capacitance, C
L
(at
Maximum Ambient Operating Temperature)
NOTES
1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER
MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE
ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO
INPUT LOADS.
VDD =2.0
V
VDD =1.9
V
VDD =1.8
V
VDD =1.7
V
TEMPERATURE – °C
1
0
0
0
100
008525 55
10
CURRENT(LOGSCALE)–µA
CL–pF
RISETIME(0.4V–2.4V)–ns
30
300050 100 150 200 250
25
15
10
5
0
20
T=85ⴗC
VDD =0VTO2.0V
CL–pF
14
0
VALIDOUTPUTDELAYORHOLD–ns
50 100 150 250200
12
4
2
–2
10
8
NOMINAL
16
18
6
–4
–6
Rev. A | Page 28 of 48 | August 2006
ADSP-218xN
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter Min Max Unit
Timing Requirements:
t
CKI
CLKIN Period 25 40 ns
t
CKIL
CLKIN Width Low 8 ns
t
CKIH
CLKIN Width High 8 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 3 ns
t
CKH
CLKOUT Width High 0.5t
CK
– 3 ns
t
CKOH
CLKIN High to CLKOUT High 0 8 ns
Control Signals Timing Requirements:
t
RSP
RESET Width Low 5t
CK1
ns
t
MS
Mode Setup before RESET High 7 ns
t
MH
Mode Hold after RESET High 5 ns
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator
start-up time).
Figure 26. Clock Signals and Reset
tCKOH
tCKI
tCKIH
tCKIL
tCKH
tCKL
tMH
tMS
CLKIN
CLKOUT
MODE A D
RESET
tRSP
ADSP-218xN
Rev. A | Page 29 of 48 | August 2006
Interrupts and Flags
Table 16. Interrupts and Flags
Parameter Min Max Unit
Timing Requirements:
t
IFS
IRQx, FI, or PFx Setup before CLKOUT Low
1,
2,
3,
4
0.25t
CK
+ 10 ns
t
IFH
IRQx, FI, or PFx Hold after CLKOUT High
1,
2,
3,
4
0.25t
CK
ns
Switching Characteristics:
t
FOH
Flag Output Hold after CLKOUT Low
5
0.5t
CK
– 5 ns
t
FOD
Flag Output Delay from CLKOUT Low
5
0.5t
CK
+ 4 ns
1
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on
interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, FO.
Figure 27. Interrupts and Flags
tFOD
tFOH
tIFH
tIFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
Rev. A | Page 30 of 48 | August 2006
ADSP-218xN
Bus Request–Bus Grant
Table 17. Bus Request–Bus Grant
Parameter Min Max Unit
Timing Requirements:
t
BH
BR Hold after CLKOUT High
1
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
0.25t
CK
+ 2 ns
t
BS
BR Setup before CLKOUT Low
1
0.25t
CK
+ 8 ns
Switching Characteristics:
t
SD
CLKOUT High to xMS, RD, WR Disable
2
2
xMS = PMS, DMS, CMS, IOMS, BMS.
0.25t
CK
+ 8 ns
t
SDB
xMS, RD, WR Disable to BG Low 0 ns
t
SE
BG High to xMS, RD, WR Enable 0 ns
t
SEC
xMS, RD, WR Enable to CLKOUT High 0.25t
CK
– 3 ns
t
SDBH
xMS, RD, WR Disable to BGH Low
3
3
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
0ns
t
SEH
BGH High to xMS, RD, WR Enable
3
0ns
Figure 28. Bus Request–Bus Grant
CLKOUT
tSD
tSDB tSE
tSEC
tSDBH tSEH
tBS
BR
tBH
CLKOUT
PMS,DMS
BMS,RD
CMS,WR,
IOMS
BG
BGH
ADSP-218xN
Rev. A | Page 31 of 48 | August 2006
Memory Read
Table 18. Memory Read
Parameter Min Max Unit
Timing Requirements:
t
RDD
RD Low to Data Valid
1
0.5t
CK
– 5 + w ns
t
AA
A13–0, xMS to Data Valid
2
0.75t
CK
– 6 + w ns
t
RDH
Data Hold from RD High 0 ns
Switching Characteristics:
t
RP
RD Pulse Width 0.5t
CK
– 3 + w ns
t
CRD
CLKOUT High to RD Low 0.25t
CK
– 2 0.25t
CK
+ 4 ns
t
ASR
A13–0, xMS Setup before RD Low 0.25t
CK
– 3 ns
t
RDA
A13–0, xMS Hold after RD Deasserted 0.25t
CK
– 3 ns
t
RWR
RD High to RD or WR Low 0.5t
CK
– 3 ns
1
w = wait states 3 t
CK
.
2
xMS = PMS, DMS, CMS, IOMS, BMS.
Figure 29. Memory Read
CLKOUT
ADDRESS LINES1
DATA LINES2
tRDA
tRWR
tRP
tASR
tCRD
tRDD
tAA
tRDH
DMS,PMS,
BMS,IOMS,
CMS
RD
WR
1ADDRESS LINES FOR ACCESSES ARE: 2DATA LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) BDMA: D15–8
I/O SPACE: A10–0 I/O SPACE: D23–8
EXTERNAL PM AND DM: A13–0 EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
Rev. A | Page 32 of 48 | August 2006
ADSP-218xN
Memory Write
Table 19. Memory Write
Parameter Min Max Unit
Switching Characteristics:
t
DW
Data Setup before WR High
1
0.5t
CK
– 4 + w ns
t
DH
Data Hold after WR High 0.25t
CK
– 1 ns
t
WP
WR Pulse Width 0.5t
CK
– 3 + w ns
t
WDE
WR Low to Data Enabled 0 ns
t
ASW
A13–0, xMS Setup before WR Low
2
0.25t
CK
– 3 ns
t
DDR
Data Disable before WR or RD Low 0.25t
CK
– 3 ns
t
CWR
CLKOUT High to WR Low 0.25t
CK
– 2 0.25t
CK
+ 4 ns
t
AW
A13–0, xMS Setup before WR Deasserted 0.75t
CK
– 5 + w ns
t
WRA
A13–0, xMS Hold after WR Deasserted 0.25t
CK
– 1 ns
t
WWR
WR High to RD or WR Low 0.5t
CK
– 3 ns
1
w = wait states 3 t
CK
.
2
xMS = PMS, DMS, CMS, IOMS, BMS.
Figure 30. Memory Write
CLKOUT
tWP
tAW
tCWR
tDH
tWDE
tDW
tASW tWWR
tWRA
tDDR
DMS,PMS,
BMS,CMS,
IOMS
RD
WR
1ADDRESS LINES FOR ACCESSES ARE: 2DATA LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) BDMA: D15–8
I/O SPACE: A10–0 I/O SPACE: D23–8
EXTERNAL PM AND DM: A13–0 EXTERNAL DM: D23–8
EXTERNAL PM: D23–0
ADDRESS LINES1
DATA LINES2
ADSP-218xN
Rev. A | Page 33 of 48 | August 2006
Serial Ports
Table 20. Serial Ports
Parameter Min Max Unit
Timing Requirements:
t
SCK
SCLK Period 30 ns
t
SCS
DR/TFS/RFS Setup Before SCLK Low 4 ns
t
SCH
DR/TFS/RFS Hold After SCLK Low 7 ns
t
SCP
SCLKIN Width 12 ns
Switching Characteristics:
t
CC
CLKOUT High to SCLKOUT 0.25t
CK
0.25t
CK
+ 6 ns
t
SCDE
SCLK High to DT Enable 0 ns
t
SCDV
SCLK High to DT Valid 7 ns
t
RH
TFS/RFS
OUT
Hold after SCLK High 0 ns
t
RD
TFS/RFS
OUT
Delay from SCLK High 7 ns
t
SCDH
DT Hold after SCLK High 0 ns
t
TDE
TFS (Alt) to DT Enable 0 ns
t
TDV
TFS (Alt) to DT Valid 7 ns
t
SCDD
SCLK High to DT Disable 7 ns
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid 7 ns
Figure 31. Serial Ports
CLKOUT
SCLK
TFSOUT
RFSOUT
DT
ALTERNATE
FRAME
MODE
tCC tCC
tSCS tSCH
tRH
tSCDE tSCDH
tSCDD
tTDE
tRDV
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
DR
TFSIN
RFSIN
RFSOUT
TFSOUT
tTDV
tSCDV
tRD
tSCP
tSCK
TFSIN
RFSIN
ALTERNATE
FRAME
MO DE tRDV
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
tTDV
tTDE
tSCP
Rev. A | Page 34 of 48 | August 2006
ADSP-218xN
IDMA Address Latch
Table 21. IDMA Address Latch
Parameter Min Max Unit
Timing Requirements:
t
IALP
Duration of Address Latch
1,
2
10 ns
t
IASU
IAD15–0 Address Setup Before Address Latch End
2
5ns
t
IAH
IAD15–0 Address Hold After Address Latch End
2
3ns
t
IKA
IACK Low before Start of Address Latch
2,
3
0ns
t
IALS
Start of Write or Read After Address Latch End
2,
3
3ns
t
IALD
Address Latch Start After Address Latch End
1,
2
2ns
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
Figure 32. IDMA Address Latch
IACK
IAL
IS
IAD15–0
IRD OR IWR
tIKA
tIALP
tIASU tIAH
tIASU
tIALS
tIAH
tIALP
tIALD
ADSP-218xN
Rev. A | Page 35 of 48 | August 2006
IDMA Write, Short Write Cycle
Table 22. IDMA Write, Short Write Cycle
Parameter Min Max Unit
Timing Requirements:
t
IKW
IACK Low Before Start of Write
1
0ns
t
IWP
Duration of Write
1,
2
10 ns
t
IDSU
IAD15–0 Data Setup Before End of Write
2,
3,
4
3ns
t
IDH
IAD15–0 Data Hold After End of Write
2,
3,
4
2ns
Switching Characteristic:
t
IKHW
Start of Write to IACK High 10 ns
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
4
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
Figure 33. IDMA Write, Short Write Cycle
IAD15–0 DATA
tIKHW
tIKW
tIDSU
IACK
tIWP
tIDH
IS
IWR
Rev. A | Page 36 of 48 | August 2006
ADSP-218xN
IDMA Write, Long Write Cycle
Table 23. IDMA Write, Long Write Cycle
Parameter Min Max Unit
Timing Requirements:
t
IKW
IACK Low Before Start of Write
1
0ns
t
IKSU
IAD15–0 Data Setup Before End of Write
2,
3,
4
0.5t
CK
+ 5 ns
t
IKH
IAD15–0 Data Hold After End of Write
2,
3,
4
0ns
Switching Characteristics:
t
IKLW
Start of Write to IACK Low
4
1.5t
CK
ns
t
IKHW
Start of Write to IACK High 10 ns
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t
IDSU
, t
IDH
.
3
If Write Pulse ends after IACK Low, use specifications t
IKSU
, t
IKH
.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
Figure 34. IDMA Write, Long Write Cycle
IAD15–0 DATA
tIKHW
tIKW
IACK
IS
IWR
tIKLW
tIKH
tIKSU
ADSP-218xN
Rev. A | Page 37 of 48 | August 2006
IDMA Read, Long Read Cycle
Table 24. IDMA Read, Long Read Cycle
Parameter Min Max Unit
Timing Requirements:
t
IKR
IACK Low Before Start of Read
1
0ns
t
IRK
End of read After IACK Low
2
2ns
Switching Characteristics:
t
IKHR
IACK High After Start of Read
1
10 ns
t
IKDS
IAD15–0 Data Setup Before IACK Low 0.5t
CK
– 3 ns
t
IKDH
IAD15 –0 Data Hold After End of Read
2
0ns
t
IKDD
IAD15–0 Data Disabled After End of Read
2
10 ns
t
IRDE
IAD15–0 Previous Data Enabled After Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid After Start of Read 11 ns
t
IRDH1
IAD15–0 Previous Data Hold After Start of Read (DM/PM1)
3
2t
CK
– 5 ns
t
IRDH2
IAD15–0 Previous Data Hold After Start of Read (PM2)
4
t
CK
– 5 ns
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
Figure 35. IDMA Read, Long Read Cycle
tIRK
tIKR
PREVIOUS
DATA READ
DATA
tIKHR
tIKDS
tIRDV tIKDD
tIRDE tIKDH
IAD15–0
IACK
IS
IRD
tIRDH1 OR tIRDH2
Rev. A | Page 38 of 48 | August 2006
ADSP-218xN
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter
1, 2
Min Max Unit
Timing Requirements:
t
IKR
IACK Low Before Start of Read
3
0ns
t
IRP1
Duration of Read (DM/PM1)
4
10 2t
CK
– 5 ns
t
IRP2
Duration of Read (PM2)
5
10 t
CK
– 5 ns
Switching Characteristics:
t
IKHR
IACK High After Start of Read
3
10 ns
t
IKDH
IAD15–0 Data Hold After End of Read
6
0ns
t
IKDD
IAD15–0 Data Disabled After End of Read
6
10 ns
t
IRDE
IAD15–0 Previous Data Enabled After Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid After Start of Read 10 ns
1
Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is
disabled by default upon reset.
2
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
Second half of PM Read.
6
End of Read = IS High or IRD High.
Figure 36. IDMA Read, Short Read Cycle
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIRDV tIKDD
tIRDE tIKDH
IAD15–0
IACK
IS
IRD
ADSP-218xN
Rev. A | Page 39 of 48 | August 2006
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter
1
Min Max Unit
Timing Requirements:
t
IKR
IACK Low Before Start of Read
2
0ns
t
IRP
Duration of Read
3
10 ns
Switching Characteristics:
t
IKHR
IACK High After Start of Read
2
10 ns
t
IKDH
IAD15–0 Previous Data Hold After End of Read
3
0ns
t
IKDD
IAD15–0 Previous Data Disabled After End of Read
3
10 ns
t
IRDE
IAD15–0 Previous Data Enabled After Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid After Start of Read 10 ns
1
Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register
or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIR D V tIKDD
tIRDE tIKDH
IAD15–0
IACK
IS
IRD
LEGEND:
IMPLIES THAT IS AND IRD CAN BE
HELD INDEFINITELY BY HOST
Rev. A | Page 40 of 48 | August 2006
ADSP-218xN
LQFP PACKAGE PINOUT
The LQFP package pinout is shown Figure 38 and in Table 27.
Pin names in bold text in the table replace the plain-text-named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default, upon reset.
Figure 38. 100-Lead LQFP Pin Configuration
5
4
3
2
7
6
9
8
1
D19
D18
D17
D16
IRQE+PF4
IRQL0+PF5
GND
IRQL1+PF6
DT0
TFS0
SCLK0
V
DDEXT
DT1/FO
TFS1/IRQ1
DR1/FI
GND
SCLK1
ERESET
RESET
D15
D14
D13
D12
GND
D11
D10
D9
VDDEXT
GND
D8
D7/IWR
D6/IRD
D5/IAL
D4/IS
GND
VDDINT
D3/IACK
D2/IAD15
D1/IAD14
D0/IAD13
BG
EBG
BR
EBR
A4/IAD3
A5/ IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDDEXT
CLKOUT
GND
VDDINT
WR
RD
BMS
DMS
PMS
IOMS
CMS
71
72
73
74
69
70
67
68
65
66
75
60
61
62
63
58
59
56
57
54
55
64
52
53
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
11
10
16
15
14
13
18
17
20
19
22
21
12
24
23
25
ADSP-218xN
IRQ2+PF7
RFS0
DR0
EMS
EE
ELOUT
ECLK
ELIN
EINT
A3/IAD2
A2/IAD1
A1/IAD0
A0
PWDACK
BGH
FL0
FL1
FL2
D23
D22
D21
D20
GND
PF1[MODEB]
GND
PWD
V
DDEXT
PF0[MODEA]
PF2[MODEC]
PF3[MODED]
RFS1/IRQ0
ADSP-218xN
Rev. A | Page 41 of 48 | August 2006
Table 27. LQFP Package Pinout
Pin No. Pin Name
1A4/IAD3
2A5/IAD4
3GND
4A6/IAD5
5A7/IAD6
6A8/IAD7
7A9/IAD8
8A10/IAD9
9A11/IAD10
10 A12/IAD11
11 A13/IAD12
12 GND
13 CLKIN
14 XTAL
15 V
DDEXT
16 CLKOUT
17 GND
18 V
DDINT
19 WR
20 RD
21 BMS
22 DMS
23 PMS
24 IOMS
25 CMS
26 IRQE + PF4
27 IRQL0 + PF5
28 GND
29 IRQL1 + PF6
30 IRQ2 + PF7
31 DT0
32 TFS0
33 RFS0
34 DR0
35 SCLK0
36 V
DDEXT
37 DT1/FO
38 TFS1/IRQ1
39 RFS1/IRQ0
40 DR1/FI
41 GND
42 SCLK1
43 ERESET
44 RESET
45 EMS
46 EE
47 ECLK
48 ELOUT
49 ELIN
50 EINT
51 EBR
52 BR
53 EBG
54 BG
55 D0/IAD13
56 D1/IAD14
57 D2/IAD15
58 D3/IACK
59 V
DDINT
60 GND
61 D4/IS
62 D5/IAL
63 D6/IRD
64 D7/IWR
65 D8
66 GND
67 V
DDEXT
68 D9
69 D10
70 D11
71 GND
72 D12
73 D13
74 D14
75 D15
76 D16
77 D17
78 D18
79 D19
80 GND
81 D20
82 D21
83 D22
84 D23
85 FL2
86 FL1
87 FL0
88 PF3 [Mode D]
89 PF2 [Mode C]
90 V
DDEXT
91 PWD
92 GND
93 PF1 [Mode B]
94 PF0 [Mode A]
95 BGH
96 PWDACK
97 A0
98 A1/IAD0
99 A2/IAD1
100 A3/IAD2
Table 27. LQFP Package Pinout (Continued)
Pin No. Pin Name
Rev. A | Page 42 of 48 | August 2006
ADSP-218xN
BGA PACKAGE PINOUT
The BGA package pinout is shown in Figure 39 and in Table 28.
Pin names in bold text in the table replace the plain text named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default upon reset.
Figure 39. 144-Ball BGA Package Pinout (Bottom View)
IRQL0 +PF5IRQ2 +PF7NCCMSGNDDT1/FODR1/FIGNDNCEMSEEECLK
IRQE +PF4NC
IRQL1 +PF6
IOMSGNDPMSDR0GNDRESETELINELOUTEINT
NCNCNCBMSDMSRFS0TFS1/IRQ1SCLK1ERESETEBRBREBG
CLKOUT
VDDINT
NC
VDDEXT
VDDEXT
SCLK0D0/IAD13RFS1/IRQ0BGD1/IAD14
VDDINT
VDDINT
CLKINGNDGNDGND
VDDINT
DT0TFS0D2/IAD15D3/IACKGNDNCGND
XTALNCGNDA10/IAD9NCNCNCD6/IRDD5/IALNCNCD4/IS
A13/IAD12NCA12/IAD11A11/IAD10FL1NCNCD7/IWRD11D8NCD9
VDDEXT
VDDEXT
A8/IAD7FL0
PF0
[MODE A]
FL2
PF3
[MODE D]
GNDGND
VDDEXT
GNDD10
NCWRNCBGHA9/IAD8
PF1
[MODE B]
PF2
[MODE C]
NCD13D12NCGND
PWDACKA6/IAD5RDA5/IAD4A7/IAD6PWD
VDDEXT
D21D19D15NCD14
A4/IAD3A3/IAD2GNDNCNCGND
VDDEXT
D23D20D18D17D16
A2/IAD1A1/IAD0GNDA0NCGNDNCNCNCD22GNDGND
1
23456789101112
M
L
K
J
H
G
F
E
D
C
B
A
ADSP-218xN
Rev. A | Page 43 of 48 | August 2006
Table 28. BGA Package Pinout
Ball No. Pin Name
A01 A2/IAD1
A02 A1/IAD0
A03 GND
A04 A0
A05 NC
A06 GND
A07 NC
A08 NC
A09 NC
A10 D22
A11 GND
A12 GND
B01 A4/IAD3
B02 A3/IAD2
B03 GND
B04 NC
B05 NC
B06 GND
B07 V
DDEXT
B08 D23
B09 D20
B10 D18
B11 D17
B12 D16
C01 PWDACK
C02 A6/IAD5
C03 RD
C04 A5/IAD4
C05 A7/IAD6
C06 PWD
C07 V
DDEXT
C08 D21
C09 D19
C10 D15
C11 NC
C12 D14
D01 NC
D02 WR
D03 NC
D04 BGH
D05 A9/IAD8
D06 PF1 [MODE B]
D07 PF2 [MODE C]
D08 NC
D09 D13
D10 D12
D11 NC
D12 GND
E01 V
DDEXT
E02 V
DDEXT
E03 A8/IAD7
E04 FL0
E05 PF0 [MODE A]
E06 FL2
E07 PF3 [MODE D]
E08 GND
E09 GND
E10 V
DDEXT
E11 GND
E12 D10
F01 A13/IAD12
F02 NC
F03 A12/IAD11
F04 A11/IAD10
F05 FL1
F06 NC
F07 NC
F08 D7/IWR
F09 D11
F10 D8
F11 NC
F12 D9
G01 XTAL
G02 NC
G03 GND
G04 A10/IAD9
G05 NC
G06 NC
G07 NC
G08 D6/IRD
G09 D5/IAL
G10 NC
G11 NC
G12 D4/IS
H01 CLKIN
H02 GND
H03 GND
H04 GND
H05 V
DDINT
H06 DT0
H07 TFS0
H08 D2/IAD15
H09 D3/IACK
H10 GND
H11 NC
H12 GND
J01 CLKOUT
J02 V
DDINT
Table 28. BGA Package Pinout
(Continued)
Ball No. Pin Name
Rev. A | Page 44 of 48 | August 2006
ADSP-218xN
J03 NC
J04 V
DDEXT
J05 V
DDEXT
J06 SCLK0
J07 D0/IAD13
J08 RFS1/IRQ0
J09 BG
J10 D1/IAD14
J11 V
DDINT
J12 V
DDINT
K01 NC
K02 NC
K03 NC
K04 BMS
K05 DMS
K06 RFS0
K07 TFS1/IRQ1
K08 SCLK1
K09 ERESET
K10 EBR
K11 BR
K12 EBG
L01 IRQE + PF4
L02 NC
L03 IRQL1 + PF6
L04 IOMS
L05 GND
L06 PMS
L07 DR0
L08 GND
L09 RESET
L10 ELIN
L11 ELOUT
L12 EINT
M01 IRQL0 + PF5
M02 IRQL2 + PF7
M03 NC
M04 CMS
M05 GND
M06 DT1/FO
M07 DR1/FI
M08 GND
M09 NC
M10 EMS
M11 EE
M12 ECLK
Table 28. BGA Package Pinout
(Continued)
Ball No. Pin Name
ADSP-218xN
Rev. A | Page 45 of 48 | August 2006
OUTLINE DIMENSIONS
Figure 40. 144-Ball BGA [CSP_BGA] (BC-144-6)
Figure 41. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1)
SEATING
PLANE
0.25
MIN
DETAIL A
0.50
0.45
0.40
(BALL DIAMETER,
SEE NOTE 4)
0.12 MAX (BALL
COPLANARITY)
0.80
BSC
(BALL
PITCH)
8.80
BSC
SQ
A
B
C
D
E
F
G
J
H
K
L
M
12 11 10 8 76321
954
1.11
0.85
A1 CORNER
INDEX AREA
1.40
MAX
TOP VIEW
BALL A1
INDICATOR
DETAIL A
BOTTOM VIEW
10.10
10.00 SQ
9.90
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY
WITH JEDEC STANDARD MO-205-AC.
2. ACTUAL POSTION OF THE BALL GRID IS WITHIN
0.15 OF ITS IDEAL POSTION RELATIVE TO THE
PACKAGE EDGES.
3. CENTER DIMENSIONS ARE NOMINAL.
4. DIMENSION IN DRAWING IS FOR PB-FREE BALL.
PB-BEARING BALL DIMENSION IS 0.45/0.50/0.55.
COMPLIANT TO JEDEC STANDARDS MS-026-BED
TOP VIEW
(PINS DOWN)
1
25
26
51
50
75
76100
0.50 BSC 0.27
0.22
0.17
1.60 MAX
0.75
0.60
0.45
VIEW A
SEATING
PLANE
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08
MAX LEAD
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
12.00
REF
16.00 BSC SQ
14.00 BSC SQ
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
12°
TYP
Rev. A | Page 46 of 48 | August 2006
ADSP-218xN
SURFACE MOUNT DESIGN
Table 29 is provided as an aid to PCB design. For industry-stan-
dard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 29. BGA Data for Use with Surface Mount Design
Package
Ball Attach
Type
Solder Mask
Opening Ball Pad Size
144-Ball BGA
(BC-144-6)
Solder Mask
Defined
0.40 mm
diameter
0.50 mm
diameter
ADSP-218xN
Rev. A | Page 47 of 48 | August 2006
ORDERING GUIDE
Model
Temperature
Range
1
1
Ranges shown represent ambient temperature.
Instruction
Rate (MHz)
Package
Description
Package
Option
ADSP-2184NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2184NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2184NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2184NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2184NKSTZ-320
2
2
Z = Pb-free part.
0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2185NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2185NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2185NBSTZ-320
2
–40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2185NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2185NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2185NKSTZ-320
2
0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2186NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2186NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2186NBSTZ-320
2
–40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2186NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2186NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2186NKSTZ-320
2
0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2187NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2187NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2187NBSTZ-320
2
–40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2187NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2187NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2187NKSTZ-320
2
0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2188NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2188NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2188NBSTZ-320
2
–40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2188NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2188NKCAZ-320
2
0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2188NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2188NKSTZ-320
2
0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2189NBCA-320 –40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2189NBCAZ-320
2
–40°C to +85°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2189NBST-320 –40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2189NBSTZ-320
2
–40°C to +85°C 80 100-Lead LQFP ST-100-1
ADSP-2189NKCA-320 0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2189NKCAZ-320
2
0°C to 70°C 80 144-Ball CSP_BGA BC-144-6
ADSP-2189NKST-320 0°C to 70°C 80 100-Lead LQFP ST-100-1
ADSP-2189NKSTZ-320
2
0°C to 70°C 80 100-Lead LQFP ST-100-1
