SSE D MM 4826175 O124451 STO MMITLI intel. | INTEL CORP (UP/PRPHLS) | THA 63 a M87C51 Co CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 4 KBYTES OF EPROM PROGRAM MEMORY Military . m High Performance CHMOS EPROM __. m@ Programmable Serial Channel @ Quick-Pulse Programming Algorithm _ TTL- and CMOS-Compatible Logic . 2-Level Program Memory Lock '-Levels , m Boolean Processor m 64K External Program Memory Space m@ 128-Byte Data RAM = 64K External Data Memory Space @. 32 Programmable I/O Lines gm IDLE and POWER DOWN Modes @ Two 16-Bit Timer/Counters m@ ONCET Mode Facilitates System m 5S interrupt Sources Testing a @ Available in 40-Pin CERDIP, 44-Pin = Military Temperature Range: Leadiess Chip Carrier, 44-Pin Gull-wing 55C to + 125C = (Tc) and 44-Pin J-Lead Packages . : The M87C51 is the EPROM version of the M80C51BH. It is fabricated on Intels CHMOS II-E process. It contains 4 Kbytes of on-chip program memory that can be electrically programmed, and can be erased by ~ exposure to ultraviolet light. . . The M87C51. EPROM array uses a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbyte array can be programmed in about 12 seconds. , The. extremely low operating power, along with the two reduced power modes, Idle and Power Down, make this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port, and interrupt system: to continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Pa.0-FO.7 P2.0~P2.7 J. he DRIVERS DRIVERS RAM ADDR. PROGRAM ADOR. REGISTER svace POINTER BUrFER REGISTER Pc INCREMENTER INTERRUPT, SERIAL PORT, AND TKER BLOCKS PROGRAM COUNTER PSEN ALE & TIMING DPTR RST: Port1 * oRIvERS, Port 3 DRIVERS, P10 P17 PS.0-P3.7 271051-1 Figure 1. MCS-51 Architectural Block Diagram "March 1992 4-13 : Order Number: 271051-006SOE D Me 46ebl?S O1e44Se 437 MITLI Intel. DIP. P1004 : 4019 Veg - P1142 3910 Po.6 (ADO) | p1.2043 38.) P0.1 (D1) | P13 4 3790) Po.2 (A02) - Pats 367) P0.3 (403) P1sty6 3517) Po.4 (AD4) Pt.6Cy7 3410 Po.s (ADS) P1708 331) Po.6 (AD6) RESETE]9 325) PO.7 (A07) (RxD) P3.0 Ch 10 31 DEA/ Vpp (Tb) P3:1 11 30 ALE / PROG (INTO) P3.24 12 29/7) PSEN (NTi) P3313 2e p27 (ais) - (To) P3414 27268 (td), (11) P35 E915 26 2.5: (A13) (WR) P36 C116 259 p2.4 (A12): (RB) 3.70917 24009 P2.3 (AI1) XTALZ CY 18. 239 P2.2 (ato) XTALI E19 222.1 (49) Vs5 Cj 20 2192.0 (a8) * 271081 -2 Lcc gag8 INDEX enanre gota cORNERN, = greec2e2 Pee pees} P1st7 i. $39} P0.4/AD4 Pi.efa ? t3B] PO.S/ADS p749 i i37}p0.6/a06 rst{io} 136] P0.7/407 Pso]it '35]EA/Vpp nc]i2i MR/MT/MZ87C51 {34 Nc P3113 . 155] ALE/PROG P3.2]ts i32] PSEN P3.3[15! E3P2.7/a15 | P3.4 [16 S30] P2.6/A14 P3S wm 2g) P2.5/a15 ee gecusneerveruroarit ASME NS 7 NN AN =~ gee8 <<< 971051-20 M87C51 INTEL CORP (UP/PRPHLS) Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program Verification. External pullups are requied during program verification. Port 1: Port 1 is an 8- bit bidirectional (/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the inter- nal pullups. Port 1 also receives the low-order address bytes . . during EPROM Programming and program verifica- tion. Port 2: Port 2.is an 8-bit bidirectional 1/O port with internal pullups. Port 2 pins that. have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source - current (IIL, on the data sheet) because of the inter- nal pullups. Port 2 emits the high-order address byte during Figure 2. M87C51 Pin Connections , PIN DESCRIPTION Vec: Supply voltage during normal, Idle, and Power , Down operations... Vgs: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional VO port. As an output port each pin can sink 8 LS TTL: inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address. and data bus during accesses to external memory. In this application it uses strong internal pullups when emit- ting 1s. ~ 4-14 fetches from external.Program memory and during accesses to. external Data Memory that use 16-bit addresses (MOVX. @DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use 8-bit-addresses (MOVX @Ri), Port 2 emits the con- tents of the P2 Special Function Register. Port:2 also receives some control signals . and the high-order address bits during EPROM programming and program verification. Port 3: Port 3 is an 8-bit bidirectional |/O port with | internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IL, on the data sheet) because of the pull- ups. Port 3'also serves the functions of various special features of the MCS-51 Family, as listed below: Pin | Name .. Alternate Function - | P3.0 } RXD | Serial input line P3.1| TXD | Serial output line P3.2 | INTO | External Interrupt 0 P3.3 | INTT | External Interrupt 1 'P3.4| TO | Timer 0 external input. P3.5} 11 Timer.1 external input P3.6 |. WR} External Data Memory Write strobe: P3.7| RD | External Data Memory Read strobe56E D = 48eb475 Obe4453 373 mE ITLL intel. Port 3 also receives some control signals for EPROM Programming and program verification. RST: Reset input. A logic high on this pin, for two . machine cycles while the oscillator is running resets the device, An internal pulldown resistor permits a power-on reset to be generated using only an exter- nal capacitor to Voc: ALE/PROG: Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input. (PROG) during EPROM programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is KipPed during each access to external Data Memory. - PSEN: Program Store Enable is the Read strobe to External Program Memory. When the M87C51 is ex- . ecuting from Internal Program Memory, PSEN is in- active (high)..When the device is executing code from External Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to Exter- nal Data Memory. EA/Vpp: External Access enable. EA must be exter- nally pulled low in order to enable the M87C51 to fetch code from External Program Memory locations 0000Hto OFFFH. Note, however, that if either of the Lock Bits is programmed, the logic level at EA is internally latched during reset. EA must be strapped to Voc for internal program execution. : : This pin also. receives the 12. 75V programming sup- ply voltage (Vpp) during EPROM programming. XTAL1: Input to the inverting oscillator amplifier and input to. the internal clock generating circuits. XTAL2: Output from the inverting oscillator amplifi- er, mo, : . : OSCILLATOR CHARACTERISTICS XTAL1.and XTAL2 are the input and output, respec- tively, of an inverting amplifier: which can be config- ured for use as an on-chip oscillator, as. shown in Figure 3. . To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left uncon- nected, as shown in Figure 4. There are no require- ments on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is M87C51 INTEL CORP CUP/PRPHLS) 271051-3 Figure 3. Using the On-Chip Oscillator | NC XTAL2 EXTERNAL : OSCILLATOR _X TAL 1 SIGNAL 271051~4 Figure 4. External Clock Drive through: a divide-by-two flip-flop, but minimum and maximum high and low times specified o on the Data Sheet- must be observed. , , IDLE MODE In idle Mode, the CPU puts itself to.sleep while all . the on-chip peripherals. remain active. The mode is invoked by software. The content of the on-chip RAM and all the Special Functions Registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt.or by a hard- ware reset. It should be noted that when idle j is terminated by a hardware reset, the device normally resumes pro- gram execution, from where it left off, up to two ma- chine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminat- ed by reset, the instruction following the one that invokes Idle should not be one that writes to a & port pin or to external data memory. - POWER DOWN MODE In the Power Down mode the oscillator is stopped, - and the instruction that invokes Power Down is the last instruction executed. The on-chip RAM and 415 |56E D MM 4626175 O1244S54 2OT MBITLI intel. M87C51 INTEL CORP (UP/PRPHLS) Table 1. Status of the External Pins during Idle and Power Down Mode Menor ALE | PSEN PORTO PoRT1 | PORT2 | PORTS Idle - __ Internal 1 . 41 Data - Data Data . Data Idle ~ External 1 1 Float. Data Address Data Power Down Internal 0 0 Data Data ~ Data Data Power Down External 0) 0 Float Data Data Data NOTE: - . For more detailed information on the reduced power modes refer tothe current Intel Embedded Applications Handbook, and Application Note AP-252,.Designing with the 80C51 BH. Special Function Registers retain their values until the Power Down mode is terminated. The only exit from Power Down is a hardware reset. Reset redefines the SFRs but does not.change the on-chip-RAM. The reset should not be activated be- fore Vcc is restored to its normal operating level and must be held active long enough to allow the oscilla- tor to restart and stabilize. : _ DESIGN CONSIDERATIONS * The M87C51 is available in a hermetically sealed, ceramic package which includes a window that al- lows for.EPROM erasure when exposed to ultravio- fet light (see Erasure Characteristics). During-normal - operation, ambient. light may adversely affect the functionality of the chip. Therefore, applications which expose the M87C51 to ambient light may re- quire an opaque label over the window. if using the M87C51. to prototype for the M80C51BH, consult the Design Considerations sec- tion of.the M80C51BH data sheet. PROGRAM MEMORY LOCK The M87C51 contains two program memory lock schemes: Encrypted Verify and Lock Bits. . Encrypted Verify: The M87C51 implements a 32- byte EPROM Array that can be programmed by the customer, and which can then be used to encrypt the program code bytes during EPROM verification. The EPROM verification procedure is performed as usual, except that each code byte comes out logical- ly X-NORed. with one of the 32 key bytes. The key bytes are gone through in sequence. Therefore, to read the ROM code, one has to know the 32 key bytes in their proper sequence. : - Lock Bits: Also on the. chip are two Lock Bits which can be left uniprogrammed (U) or can. be pro- grammed (P) to obtain the following additional fea- tures: ; Bit1 | Sit2.| | Additional Features . U U none P U__j* Externally fetched code can not access internal Program Memory. * Further programming disabled. U P |(Reserved for Future definition.) Pp _P . |e Externally fetched code can not access internal Program Memory. Further programming disabled. * Program verification is disabled. When Lock Bit 1-is programmed, the logic level at the EA pin is sampled and latched during reset. f the device: is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary, that the latched value of EA be in agreement with the current logic level at that pin in order for the device to func- tion properly. : Doe ONCET MODE The ONCE (on-circuit emulation) mode facilitates testing and debugging of systems using the M87C51 without the MB7C51 having to be removed from the - circuit. The ONCE mode is invoked by: 4. Pull ALE low while the device is in reset and. PSEN is high. 2. Hold ALE low as RST is deactivated. _ While the device is in ONCE mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator cir- cuit remains active. While. the M87C51 is in this mode, an emulator or test CPU can be used to drive the circuit: Normal operation is restored when a nor- mal reset is applied. : 4-16SBE D MM 4826175 Obe4455 146 MMBITLI intel. _ Ms7cst a INTEL CORP (UP/PRPHLS) ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING, Stressing the device beyond the Absolute Storage Temperature an 656C to + 150C Maximum Ratings May cause permanent damage. Voltage on EA/Vpp Pin to Vgg .......0V:to +13.0V These are stress ratings only. Operation beyond the oS Operating Conditions is not recommended and ex- Voltage on Any Other Pinto Vgg_ -.0.5V to +6.5V tended exposure beyond the Operating Conditions Power Dissipation...............0.....2....1.5W may affect device reliability. (based on package heat transfer limitations, not de- . vice power consumption) Case Temperature Under Bias... 55C to + 125C Operating Conditions . _ Symbol Description Min Max Units Teo - Case Temperature (instant On) -55 | +125 C Voc _ Digital Supply Voltage 450 - - 5.50. | MN fosc 41 Oscillator Frequency 35 46 , _ MHz D.C. CHARACTERISTICS: (Over Specified Operating Conditions), - a Be " | Symbot Parameter : Min | Typ(); . (Max. <:| Unit]; . Comments Vit Input Low Voltage (Except EA) - 0.5 0.2 Voc 0.25|: V , Vit Input Low Voltage to EA 0 -) {0.2Vg-O.451 V. Vin Input High Voltage (Except XTAL1, RST) | 0.2 Vog+ 1.1 | Voo+0.5 Vv Vin1 _| Input High Voltage (XTAL1, RST) O.7Voct0.2} Voct0.5 | V- No. | Output Low Voltage (Ports 1,2,3) 0.45 V -TloL = 1.6mA (2) Vor1 _ | Output Low Voltage (Port 0, ALE, PSEN) oe 0.45 Vo Hot = 3.2 mA (2) . Vou | Output High Voltage (Ports 1, 2, 3) 24 V flow = 60 pA , 0.75 Voc V lion = 25 pA . 0.9 Voc V fio = -10HA Vou1 | Output High Voltage (Port din 2.4 V }ton = 800 pA , . External Bus Mode, ALE, PSEN) 0.75 Voc. V lio = 300 pA 0.9Vcc Vi {low = 80 pA (8) he Logical 0 Input Current (Ports 1, 2, 3) ; -75 BA | Vin = 0.45.V Ith. Logical 1-to-0 transition current - . . -750 pA - (4) (Ports 1, 2, 3) r . . . Iu Input Leakage Current (Port 0) +10 pA.10.45 < Vin < Voc Ioc Power Supply Current: , Active Mode @ 12 MHz (Figure 5) 11.5 35 = | mA Idle Mode @ 12 MHz (Figure 6) 1.3 6 - | mA (8) Power Down Mode (Figure 7) / 3 75 | pA RRST | internal Reset Pulldown Resistor 50 - 300 Ka Cio Pin Capacitance - , : : 10 pF 4-17. 58E DD MH 4826175 O124456 O42 MITLI intel. oo M87C51 INTEL CORP CUP/PRPHLS) D.C. CHARACTERISTICS: (Over Specitied Operating Conditions) (Continued) Co NOTES: : . 1.Typicals are based on a limited number of samples taken from early manufacturing lots. The values listed are at room temp, 5V. : . oO : : 2, Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vg_s of ALE and Ports 1_and 3: The noise is due to-external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1- to-0 transitioris during bus operations. in the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. , / . 3. Capacitive toading on Ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0:9 Vcc specification when the address bits are stabilizing. : : 4. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2V. ae oe. 5. loc is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5ns, Vi. = Vss + BY, Vin = Voc 0.5V measured with EA and RST connected to Vcc. Idle current is measured with EA and RST connected to Vgs. Power Down current is. measured with XTAL1, EA and RST connected to Vgg. (See Figures 5 through 8 for a graphic representation of the ioc test conditions. : : . . . : . Mec. Vee qlee : . loc BV eg li Voc _ Yee Ti Voc. Veet 2 po . PO KJ U RST. EA [~ a os & _ cock (NOY TAZ . crock (NC}=] XTAL2 SIGNAL XTALTS J SIGNAL XTALT mss - |. ois , 271051-16 , , 27108118 Figure 5. Icg Test Condition, Active Mode. Figure 6. Icc Test Condition, Idle Mode. All other pins are disconnected. All other pins are disconnected. Yee j lee Voc FE Veg PO: ys AL (NC)4 XTAL2 XTAL1 vs 271051-19 Figure 7. loc Test Condition, Power Down Mode. All other pins are disconnected, Vcc = 2V to 5.5V. . Vopr 0.5 sa ecnee ee 0.7 Voc 7, h 0.45V 0.2 Vog-0.1 TCHCX ane : TCHCL-| }- Telex _| be TCLCH TELCL 271051-17 Figure 8. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5ns. 4-48 .S58E 0D MM 4826375 O124457? T1959 MITLI intel. , M8751 = INTEL CORP (UP/PRPHLS) EXPLANATION OF THE AC SYMBOLS ppeewe LOW, or ALE. Each timing symbol has 5 characters. The first char- Q:Output data. acter is always a T (stands for time). The other R:READ signal. characters, depending on their positions, stand for T:Time. the name of a signal or the logical status of that V:Valid. signal. The following is a list of all the characters and W:WRITE signal. _ what they stand for. X:No longer a valid logic level. Z:Float. A:Address. oe C:Clock, / For example, D:Input data. : H:Logic level HIGH. . TAVLL = Time from Address Valid to ALE Low. Instruction (program memory contents). TLLPL = Time from ALE Low to PSEN Low. AC CHARACTERISTICS: (Over Specified Operating Conditions) Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Ose Variable Oscillator Units Min Max Min Max . 1/TCLCL | Oscillator Frequency : 3.5 12 MHz TLHLL ALE Pulse Width 127 2TCLCL40 : ns TAVLL Address Valid to ALE Low 28 TCLCL 55 ns TLLAX Address Hold After ALE Low 48 TCLCL 35 : ns TLLIV ALE tow to Valid Instr In 223 . | 4TCLCL110 ns TLUPL ALE Low to PSEN Low 43 . TCLCL 40 . ns TPLPH PSEN Pulse Width 205. | 8TCLCL45 ; f oS TPLIV PSEN Low to Valid Instr In 135 f. 38TCLCL115 ns TPXIX Input Instr Hold After PSEN | 0 0 ns TPXIZ Input Instr Float After PSEN . 58 TCLCL 25 ns TAVIV Address to Valid Instr In 302 STCLOL115 ns TPLAZ PSEN Low to Address Float 10 10 ns TRLRH RD Pulse Width 400 6TCLCL 100 ns - TWLWH_ | WR Pulse Width 400 6TCLCL 100 ns TRLDV RD Low to Valid Data In 242 STCLOL 175 ns _ TRHDX Data Hold After RD 0 : 0 ns TRHDZ__| Data Float After RD 97 ; ' 2TCLCL70' |. ns TLLDV "| ALE Low to Valid Data In . 507 8TCLCL 160 ns TAVDV | Address to Valid Data In 575 STCLCL 175 ns TELWL ALE.Low to RD or WR Low 200 300 | 3TCLCL50 3TCLCL+ 50 ns TAVWL _. | Address to RD or WA Low 203 _ ATCLCL 130 ns. TQVWX | Data Valid to WR Transition | 23 - TCLCL~60 | ons TWHOX | Data'Hold After WR 33 TCLCL50 ns TRLAZ RD Low to Address Float 0 0 . ns TWHLH RD or WR High to ALE High 43 123 TCLCL -- 40 TCLCL +40 ns 4-19S8E D MM 4626475 O124458 q55 MBITLI intel. M87C51 INTEL CORP CUP/PRPHLS) TLHLL ALE TLLPL TPLPH / TAVEL - PSEN TPLIV TPXIX INSTR IN PORT 0 PORT 2 AB~ AIS 271051-5 External Program Memory Read Cycle nby TRLRH TELWL - TRLDV TRHDZ -- TLLAX TRIAZ TRHDX DATA IN PORTO AQ-A7 FROM RCL TAVWL TAVDV P2.0=P2.7 OR A8S~A15 FROM DPH AB=A15 FROM PCH 271051-6 PORT 2. External Data Memory Read Cycle ALE PSEN TLLWL S TLLAX j OVX PORTO DATA OUT AQ~A7 FROM PCL INSTR. IN TAVWL So PORT2 P2.0=P2.7 OR A8-A15 FROM DPH . A8~A15 FROM PCH Bo 271051-7 External Data Memory Write Cycle... ao 4-20S8E D MM 4826175 01244595 695) MITLI intel. M87C51 _e INTEL CORP CUP/PRPHLS) EXTERNAL CLOCK DRIVE sy. , EXTERNAL CLOCK DRIVE WAVEFORM Symbol Parameter Min | Max | Units Be 1/TCLCL | Oscillator Frequency . Vecn0S "OTT , 87051 : 3.51 12 | MHz 87C51-16 3.5| 16 . 0.45V a 0:2Vec0.1 . : - + TCHCL- TCHCX =| High Time 20 ns - . / LO 271051-8 TCLCX | Low Time : 20 |. ns TCLCH | Rise Time . 20 | ns TCHCL | Fall Time 20 | ns SERIAL PORT TIMINGSHIFT REGISTER MODE (Over Specified Operating Conditions) | -|symbot| Parameter 12 MHz Osc _ Variable Oscillator J Units : . oe , Min | Max Min Max TXLXL Serial Port Clock Cycle Time - - 1.0 F2TCLOCL BS TQVXH | Output Data Setup to Clock Rising Edge 700 .| T0TCLCL-133] ~ ns TXHQX | Output Data Hold After Clock Rising Edge| 50. 2TCLCL 117 ns TXHDX | Input Data Hold After Clock Rising Edge | 0 FO ns TXHDV | Clock Rising Edge to Input Data Valid 700 1OTCLCL133; ns SHIFT REGISTER MODE TIMING WAVEFORMS INSTRUCTION] =O : 1 f 2 | & | 4 | 5 , 1.6 | 7 4 8 4 oo PoTXLXLy , . : TOVxH || pmnex . OUTPUT DATA Yo to: 2 X35 XX 4 eK sh hX 6 hUX 7 CO , aol TXHDX , . ' WRITE TO SBUF . 4 TXHDV ic r SET Ti INPUT DATA CLEAR RI 271051-9 A.C. TESTING: INPUT, OUTPUT WAVEFORMS . : FLOAT WAVEFORM Ver~0.5 v +0.1 oyr0.1 ce oe Voct0.9 2 de Vow + TIMING REFERENCE < on i : 2 Voc70-1 Vipap 0.1 POINTS Po) 40.1V 0.45V Loap~0- oL*O. 271051-10 . 271051-11 . For timing purposes a port pin is:no longer floating when a 100 AC inputs during testing are driven at Voc ~ 0.5 for a Logic 1 mV change from toad voltage occurs, and begins to float when a \ and 0.45V fora Logic * 0. Timing measurements are made at Viy 100 mV change from the joaded Vou/ Voi level occurs. loL/tou min for a Logic 1 and Vy max for a Logic 0. = +20mA. - 4-21INTEL COR EPROM CHARACTERISTICS The M87C51-is programmed by a modified Quick- Pulse Programming algorithm. It differs from older methods in the value used for Vpp. (Programming | Supply Voltage) and in the width and number of the ALE/PROG pulses. | _ The M87C51 contains two signature bytes that can be read and used by an EPROM programming sys- SAl D WS 4826175 O1244b0 503 MITLI ' MB7C51. . , P (UP/PRPHLS) tem to identify the device. The signature bytes iden- tify the device as an M87C51 manufactured by Intel. Table 2 shows the logic levels for reading the signa- ture byte, and for programming the Program Memo- ty, the Encryption Table, and the Lock Bits. The. cir- cuit configuration. and waveforms for Quick-Pulse Programming. are shown in Figures. 9 and 10. Figure 11 shows the circuit configuration for normal Pro- gram Memory verification. To cts Table 2. EPROM Programming Modes _ MODE rst | PSEN | Sure Ven p27 | P26 | P37 | P36 Read Signature 1 0 1 1 0 0 0 0. Program Code Data 1 0. o* Vep | 1 Oo 1} 4, Verity Code Data 1 0. 4 1 Oo. 0 1 oA! Pgm Encryption Table 1 Q o* _ Vpe_. 1 0 4 0 Pgm Lock Bit 1 1 O- -0* > Mpp 1 4 ap ote Pgm Lock Bit 2 1 0 ot Vpp 1 [4 -] 0 | 20 NOTES: - 4 = Valid high for that pin 0 = Valid-low for that pin - Mpp = 12.75V + 0.25V : Veco = 5_+10% during programming and verification *ALE/PROG receives 25 programming pulses while Vpp (+10 ps) and high for a minimum of 10 ps. is held at 12.75V. Each programming pulse is low for-100 ps +5V / Voc AO=A7 1 _ PO Baar ata os 1$$] RST > EAN pp Hmm. 4 , . . . . : ALE/PROG }- 25 100 zs PULSES TO GND 1P] P36 > / _ # , M7651 PSEN} 0 { pf P37 : P27 [e 1 - [ XTAL 2 72.6 /0 LI P2.0 : + XTALI =p23 Kae Vss . ~ 271081-12, Figure 9. Programming Configuration 4-2258E D MM 4826175 OL244b1 QUT MBITLI intel. M87C51 =. INTEL CORP (UP/PRPHLS) 4 2 1 ALE/PROG: LULL: Lf 0 4 ALE/PROG: 8 PULSES . 100 us _ ne pe JL f 271051-13 * Quick- Pulse Programming The setup for Microcontroller Quick-Pulse Program: ming is shown in Figure 9. Note that.the M87C51 is running with a 4 to 6 MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data trans- fers. . . The address of the EPROM location to be pro- grammed is applied to Ports 1 and 2, as shown in Figure 9.. The code byte to be programmed into that location is applied to Port 0. RST, PSEN, and pins of Ports 2 and.3 specified in Table 2 are held at the . Figure 10. PROG Waveforms ~ - Program Code Data levels indicated in Table 2. . - Then ALE/PROG is pulsed low 25 times as shown in Figure 10. To program the Encryption Table, repeat the 25- pulse programming Sequence for addresses 0 4-23 through 1FH, using the Pgm Encryption Table lev- els. Dont forget that after the Encryption Table is . programmed, verify cycles will- produce only enerypt- ed data. To program the Lock Bits, repeat the 25-pulse pro- gramming sequence using the Pgm Lock Bit lev- els. After one Lock Bit is programmed, further pro- gramming of the Code Memory and Encryption Ta- ble is disabled. However, the other Lock Bit can still be programmed. Note that the EA/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that volt- age level can cause permanent damage to the de- vice. The Vpp source should be well regulated and free of glitches and overshoot. .56E D MM 4426175 O1244b2 386 MBITLI intel. M87C51. INTEL CORP (UP/PRPHLS) +5V AO=A7__. WP1 {] rst EA/Vpp +# 1 _ ALE/PROG 1 1-] P3.6 ALE/ 06 . EN } 0 SO 87051. * ; 1-] P3.7 t. oe 2.7}-0 (ENABLE) [ XTAL2 P2.6 }-0 Lai p2.0|A-==,, + xTAL | -P23 AB=A11 Vss . 271051-14 * Figure 11. Program Verification Program Verification . bas If Lock Bit 2 has not been programmed, the on-chip Program Memory can be read out for program verifi- cation. The address of the Program Memory location to be read is applied to Ports.1 and 2 as shown in Figure 11. The other pins are held at the Verify Code Data levels indicated in Table 2. The con- tents. of the addressed location will be emitted on Program/Verify Algorithms Any algorithm in agreement with the conditions list-" ed in Table 2, and which satisfies the timing specifi- cations, is suitable. , Erasure Characteristics Port 0. External pullups are required on Port 0 for _ this operation. Detailed timing specifications are shown in later sections of this data sheet. lf the Encryption Table has been programmed, the . data presented at Port 0 will be the Exclusive NOR _ of the program byte with one ofthe encryption bytes. The user will have to know the Encryption Table contents in order to correctly decode the verification data. The Encryption Table itself can. not be read out. : Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and.031H, except that P3.6 and -P3.7 need to be pulled to a logic low. The values returned are: (030H) = 89H indicates manufactured by Intel (031H) = 57H indicates M87C51 Erasure of the EPROM begins:to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or.3 years in room level fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. os The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm?. Exposing the EPROM to an ultraviolet lamp of 12,000 W/cm? rating for 30 minutes, at a distance of about 1 inch, should be sufficient. . Erasure leaves the array in an all 1s state. 4-24.SBE DMM 4826475 0124463 212 MBITLI intel. M8751 INTEL CORP CUP/PRPHLS) EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS: , Ta = 21C to 27C, Voc = 5V 10%, Vgg = OV , Symbol Parameter Min Max Units Vpp Programming Supply Voltage 125 13.0 Vv Ipp Programming Supply Current 50 mA 1/TCLCL . _ Oscillator Frequency : 4 6 | MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold After PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold After PROG A8TCLCL TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL TSHGL. Vpp Setup to PROG Low 10 . : ps TGHSL Vpp Hold After PROG 10 BS TGLGH PROG Width 90 | 410 ys. TAVQV Address to Data Valid : 48TCLCL | TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float After ENABLE 0 48TCLCL TGHGL PROG High: to PROG Low 10: i , BS. EPROM Programming and Verification Waveforms PROGRAMMING * VERIFICATION T P41.0-P1.7 a P2.0-P2.3 eed ADDRESS. , si 1 TAVOV : PORT 0 <eeneerewerenmanisnnse} DATA IN DATA OUT Dr TOYGL- ~ + TGHDX - TAYGL! las euses [+e TGHAX ___ . ALE/PROG _. - TSHGL + TGHGL TGLGH \ . = . LOGIC 1 LOGIC 1 am,_/ . Loci LocIC.0 - peeltensH- , TELQV lTEHOZ . P27 . _ (ENABLE) __/ I : : : 271051-15 *FOR PROGRAMMING CONDITIONS SEE FIGURE 9. TFOR VERIFICATION CONDITIONS SEE FIGURE 11. 4-25