BSP250,115 - NXP Semiconductors / Philips Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of November 1994

File under Discrete Semiconductors, SC13b

1997 Jun 20

DISCRETE SEMICONDUCTORS

BSP250

P-channel enhancement mode

vertical D-MOS transistor

1997 Jun 20 2

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

FEATURES

•High-speed switching

•No secondary breakdown

•Very low on-resistance.

APPLICATIONS

•Low-loss motor and actuator drivers

•Power switching.

DESCRIPTION

P-channel enhancement mode vertical D-MOS transistor

in a SOT223 plastic SMD package.

CAUTION

The device is supplied in an antistatic package.

The gate-source input must be protected against static

discharge during transport or handling.

PINNING - SOT223

PIN SYMBOL DESCRIPTION

1 g gate

2 d drain

3 s source

4 d drain

Fig.1 Simplified outline and symbol.

handbook, halfpage

MAM121

123

Top view s

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS drain-source voltage (DC) −−30 V

VSD source-drain diode forward voltage IS=−1.25 A −−1.6 V

VGSO gate-source voltage (DC) open drain −±20 V

VGSth gate-source threshold voltage ID=−1 mA; VDS =V

GS −1−2.8 V

IDdrain current (DC) −−3A

DSon drain-source on-state resistance ID=−1 A; VGS =−10 V −0.25 Ω

Ptot total power dissipation Ts= 100 °C−5W

1997 Jun 20 3

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Pulse width and duty cycle limited by maximum junction temperature.

2. Device mounted on an epoxy printed-circuit board, 40 ×40 ×1.5 mm; mounting pad for drain lead minimum 6 cm2.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS drain-source voltage (DC) −−30 V

VGSO gate-source voltage (DC) open drain −±20 V

IDdrain current (DC) Ts≤100 °C−−3A

DM peak drain current note 1 −−12 A

Ptot total power dissipation Ts= 100 °C−5W

amb =25°C; note 2 −1.65 W

Tstg storage temperature −65 +150 °C

Tjoperating junction temperature −150 °C

Source-drain diode

ISsource current (DC) Ts≤100 °C−−1.5 A

ISM peak pulsed source current note 1 −−6A

Fig.2 Power derating curve.

handbook, halfpage

0 200

2.0

0.4

0.8

1.2

1.6

MLB885

Tamb (°C)

50 100 150

Ptot

(W)

δ= 0.01.

Soldering point temperature Ts= 100 °C.

(1) RDSon limitation.

Fig.3 SOAR.

handbook, halfpage

MLB835

VDS (V)

(A)

−10

−1

−10

−1−10

−10

−2

−10

−1

−10

1 ms

(1) tp =

10 µs

1997 Jun 20 4

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

THERMAL CHARACTERISTICS

Note

1. Device mounted on an epoxy printed-circuit board, 40 ×40 ×1.5 mm; mounting pad for drain lead minimum 6 cm2.

CHARACTERISTICS

Tj=25°C unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-a thermal resistance from junction to ambient note 1 75 K/W

Rth j-s thermal resistance from junction to soldering point 10 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V(BR)DSS drain-source breakdown voltage VGS = 0; ID=−10 µA−30 −−V

GSth gate-source threshold voltage VGS =V

DS; ID=−1mA −1−−2.8 V

IDSS drain-source leakage current VGS = 0; VDS =−24 V −−−100 nA

IGSS gate leakage current VGS =±20 V; VDS =0 −−±100 nA

IDon on-state drain current VGS =−10 V; VDS =−1V −3−−A

GS =−4.5 V; VDS =−5V −1−−A

DSon drain-source on-state resistance VGS =−4.5 V; ID=−0.5 A −0.33 0.4 Ω

VGS =−10 V; ID=−1A −0.22 0.25 Ω

yfsforward transfer admittance VDS =−20 V; ID=−1A 1 2 −S

iss input capacitance VGS = 0; VDS =−20 V; f = 1 MHz −250 −pF

Coss output capacitance VGS = 0; VDS =−20 V; f = 1 MHz −140 −pF

Crss reverse transfer capacitance VGS = 0; VDS =−20 V; f = 1 MHz −50 −pF

QGtotal gate charge VGS =−10 V; VDS =−15 V;

ID=−2.3 A −10 25 nC

QGS gate-source charge VGS =−10 V; VDS =−15 V;

ID=−2.3 A −1−nC

QGD gate-drain charge VGS =−10 V; VDS =−15 V;

ID=−2.3 A −3−nC

Switching times

ton turn-on time VGS =0to−10 V; VDD =−20 V;

ID=−1 A; RL=20Ω−20 80 ns

toff turn-off time VGS =−10 to 0 V; VDD =−20 V;

ID=−1 A; RL=20Ω−50 140 ns

Source-drain diode

VSD source-drain diode forward voltage VGD = 0; IS=−1.25 A −−−1.6 V

trr reverse recovery time IS=−1.25 A; di/dt = 100 A/µs−150 200 ns

1997 Jun 20 5

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

Fig.4 Capacitance as a function of drain source

voltage; typical values.

VGS =0.

j=25°C.

handbook, halfpage

600

400

200

0−10 −20 −30

MBE144

(pF)

VDS (V)

Ciss

Coss

Crss

Fig.5 Output characteristics; typical values.

Tj=25°C.

handbook, halfpage

0−2−10 −12

−10

−12

−8

−6

−2

−4

MBE149

−4−6−8V (V)

(A)

VGS =

−10 V

−6 V

−5 V

−4.5 V

−4 V

−3.5 V

−3 V

−2.5 V

−7.5 V

Fig.6 Transfer characteristic, typical values.

VDS =−10 V.

Tj=25°C.

handbook, halfpage

0−2−4−8

−16

−12

−4

−8

MBE150

−6

(A)

VGS (V)

Fig.7 Gate-source voltage as a function of total

gate charge.

VDD =−15 V.

ID=−3A.

handbook, halfpage

0−2−4−10−8

−10

−8

MBE145

−6

−4

−2

Qg (nC)

VGS

(V)

1997 Jun 20 6

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

Fig.8 Source current as a function of source-drain

diode forward voltage.

VGD =0.

(1) Tj= 150 °C.

(2) Tj=25°C.

(3) Tj=−55 °C.

handbook, halfpage

0−0.5 −1−1.5 −2−2.5

−6

−2

−4

MBE148

(A)

VSD (V)

(1) (2) (3)

Fig.9 Drain-source on-state resistance as a

function of gate-source voltage; typical

values.

−VDS ≥−I

D×R

DSon; Tj=25°C.

(1) ID=−0.1 A.

(2) ID=−0.5 A.

(3) ID=−1A.

(4) ID=−3A.

(5) ID=−6A.

handbook, halfpage

−100

(1) (4) (5)

VGS (V)

RDSon

(mΩ)

−2−4−6−8

104

103

102

MDA218

(2)(3)

Fig.10 Temperature coefficient of gate-source

threshold voltage.

handbook, halfpage

0.6

0.7

0.8

0.9

1.0

1.2

1.1

0 50 100 150−50

Tj (°C)

MBE138

Typical VGSth at ID=−1 mA; VDS =VGS =V

GSth.

kVGSth at Tj

VGSth at 25°C

--------------------------------------

Fig.11 Temperature coefficient of drain-source

on-resistance.

Typical RDSon at:

(1) ID=−1 A; VGS =−10 V.

(2) ID=−0.5 A; VGS =−4.5 V.

kRDSon at Tj

RDSon at 25 °C

-----------------------------------------

handbook, halfpage

0.6

0.8

1.0

1.2

1.4

1.8

1.6

0 50 100 150−50

Tj (°C)

MBE146

(1)

(2)

1997 Jun 20 7

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

Fig.12 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.

handbook, full pagewidth

tp (s) 1

MBE147

Rth j-s

(K/W)

10−1

10−610−510−410−310−210−1

δ=

δ =

0.75

0.5

0.1

0.05

0.33

0.01

0.02

0.2

1997 Jun 20 8

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

PACKAGE OUTLINE

UNIT A1bpcDEe

pQywv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.10

0.01

1.8

1.5 0.80

0.60

3.1

2.9 0.32

0.22 6.7

6.3 3.7

3.3 2.3

4.6 7.3

6.7 1.1

0.7 0.95

0.85 0.1 0.10.2

DIMENSIONS (mm are the original dimensions)

SOT223 96-11-11

97-02-28

detail X

vMA

0 2 4 mm

scale

132

Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223

1997 Jun 20 9

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode

vertical D-MOS transistor BSP250

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

Data Sheet Status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

1997 Jun 20 10

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode vertical

D-MOS transistor BSP250

NOTES

1997 Jun 20 11

Philips Semiconductors Product speciﬁcation

P-channel enhancement mode vertical

D-MOS transistor BSP250

NOTES

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Printed in The Netherlands 137107/00/02/pp12 Date of release: 1997 Jun 20 Document order number: 9397 750 02331