PCF8578T/1,112 - NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1998 Sep 08 2003 Apr 14

INTEGRATED CIRCUITS

PCF8578

LCD row/column driver for

dot matrix graphic displays

2003 Apr 14 2

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 BLOCK DIAGRAM

6 PINNING

7 FUNCTIONAL DESCRIPTION

7.1 Mixed mode

7.2 Row mode

7.3 Multiplexed LCD bias generation

7.4 Power-on reset

7.5 Internal clock

7.6 External clock

7.7 Timing generator

7.8 Row/column drivers

7.9 Display mode controller

7.10 Display RAM

7.11 Data pointer

7.12 Subaddress counter

7.13 I2C-bus controller

7.14 Input filters

7.15 RAM access

7.16 Display control

7.17 TEST pin

C-BUS PROTOCOL

8.1 Command decoder

9 CHARACTERISTICS OF THE I2C-BUS

9.1 Bit transfer

9.2 Start and stop conditions

9.3 System configuration

9.4 Acknowledge

10 LIMITING VALUES

11 HANDLING

12 DC CHARACTERISTICS

13 AC CHARACTERISTICS

14 APPLICATION INFORMATION

15 CHIP DIMENSIONS AND BONDING PAD

LOCATIONS

16 CHIP-ON-GLASS INFORMATION

17 PACKAGE OUTLINES

18 SOLDERING

18.1 Introduction to soldering surface mount

packages

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

19 DATA SHEET STATUS

20 DEFINITIONS

21 DISCLAIMERS

22 PURCHASE OF PHILIPS I2C COMPONENTS

2003 Apr 14 3

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

1 FEATURES

•Single chip LCD controller/driver

•Stand-alone or may be used with up to 32 PCF8579s

(40960 dots possible)

•40 driver outputs, configurable as 32⁄8,24⁄16,16⁄24 or

8⁄32 rows/columns

•Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32

•Externally selectable bias configuration, 5 or 6 levels

•1280-bit RAM for display data storage and scratch pad

•Display memory bank switching

•Auto-incremented data loading across hardware

subaddress boundaries (with PCF8579)

•Provides display synchronization for PCF8579

•On-chip oscillator, requires only 1 external resistor

•Power-on reset blanks display

•Logic voltage supply range 2.5 to 6 V

•Maximum LCD supply voltage 9 V

•Low power consumption

•I2C-bus interface

•TTL/CMOS compatible

•Compatible with most microcontrollers

•Optimized pinning for single plane wiring in multiple

device applications (with PCF8579)

•Space saving 56-lead plastic mini-pack and 64 pin quad

flat pack

•Compatible with chip-on-glass technology.

2 APPLICATIONS

•Automotive information systems

•Telecommunication systems

•Point-of-sale terminals

•Computer terminals

•Instrumentation.

3 GENERAL DESCRIPTION

The PCF8578 is a low power CMOS LCD row/column

driver, designed to drive dot matrix graphic displays at

multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device

has 40 outputs, of which 24 are programmable,

configurable as 32⁄8,24⁄16,16⁄24 or 8⁄32 rows/columns.

The PCF8578 can function as a stand-alone LCD

controller/driver for use in small systems, or for larger

systems can be used in conjunction with up to

32 PCF8579s for which it has been optimized. Together

these two devices form a general purpose LCD dot matrix

driver chip set, capable of driving displays of up to

40960 dots. The PCF8578 is compatible with most

microcontrollers and communicates via a two-line

bidirectionalbus(I2C-bus).Communicationoverheadsare

minimized by a display RAM with auto-incremented

addressing and display bank switching.

4 ORDERING INFORMATION

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

PCF8578T VSO56 plastic very small outline package; 56 leads SOT190-1

PCF8578U/2 −chip with bumps in tray −

PCF8578H LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 ×10 ×1.4 mm SOT314-2

2003 Apr 14 4

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

5 BLOCK DIAGRAM

Fig.1 Block diagram.

(1) Operates at LCD voltage levels, all other blocks operate at logic levels.

The pin numbers given in parenthesis refer to the LQFP64 package.

VSS

C39 - C32

R31/C31 - R8/C8

R7 - R0

17 - 56

(29 to 35, 37, 38 to 46

48 to 62, 63, 64, 1 to 6)

MSA842

VDD

PCF8578

VLCD

9 (20)

10 (21)

11 (22)

12 (23)

13 (24)

14 (25)

6 (12)

OUTPUT

CONTROLLER

ROW/COLUMN

DRIVERS

(1)

DISPLAY

MODE

CONTROLLER

Y DECODER

AND SENSING

AMPLIFIERS 32 x 40-BIT

DISPLAY RAM

X DECODER

DISPLAY

DECODER

RAM DATA POINTER

SUBADDRESS

COUNTER TIMING

GENERATOR

I C-BUS

CONTROLLER

INPUT

FILTERS COMMAND

DECODER

POWER-ON

RESET

OSCILLATOR

TEST

2 (8)

1 (7)

SCL

SDA

n.c. n.c. SA0

15, 16 (14, 15, 17 to 19

26 to 28 36, 47) 7 (13)

(16) 8

(11) 5

(10) 4

(9) 3

ROSC

OSC

CLK

SYNC

2003 Apr 14 5

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

6 PINNING

SYMBOL PIN DESCRIPTION

VSO56 LQFP64

SDA 1 7 I2C-bus serial data input/output

SCL 2 8 I2C-bus serial clock input

SYNC 3 9 cascade synchronization output

CLK 4 10 external clock input/output

VSS 5 11 ground (logic)

TEST 6 12 test pin (connect to VSS)

SA0 7 13 I2C-bus slave address input (bit 0)

OSC 8 16 oscillator input

VDD 9 20 positive supply voltage

V2 to V510 to 13 21 to 24 LCD bias voltage inputs

VLCD 14 25 LCD supply voltage

n.c. 15, 16 14, 15, 17 to 19,

26 to 28, 36, 47 not connected

C39 to C32 17 to 24 29 to 35, 37 LCD column driver outputs

R31/C31 to R8/C8 25 to 48 38 to 46, 48 to 62 LCD row/column driver outputs

R7 to R0 49 to 56 63, 64, 1 to 6 LCD row driver outputs

2003 Apr 14 6

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.2 Pin configuration (VSO56).

13 44

MSA839

R27/C27

R26/C26

R25/C25

R24/C24

R23/C23

R22/C22

R21/C21

R20/C20

R19/C19

R18/C18

R17/C17

R16/C16

R15/C15

R14/C14

R13/C13

R12/C12

R11/C11

R10/C10

R9/C9

R8/C8

R28/C28

R29/C29

R30/C30

R31/C31

C32

C33

C34

C35

C36

C37

C38

C39

n.c.

VLCD

VDD

OSC

SA0

TEST

CLK

SYNC

SCL

SDA

VSS

PCF8578T

2003 Apr 14 7

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.3 Pin configuration (LQFP64).

handbook, full pagewidth

PCF8578H

MBH588

SCL

CLK

TEST

SA0

n.c.

OSC

VSS

SYNC

SDA

R21/C21

R20/C20

R19/C19

R18/C18

R17/C17

R16/C16

R15/C15

R14/C14

R13/C13

R12/C12

R11/C11

R10/C10

R9/C9

R8/C8

R31/C31

C35

C34

C33

n.c.

C32

C39

n.c.

VLCD

VDD

C38

C37

C36

R30/C30

R29/C29

R28/C28

R27/C27

R26/C26

R24/C24

R25/C25

R23/C23

n.c.

R22/C22

2003 Apr 14 8

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

7 FUNCTIONAL DESCRIPTION

ThePCF8578row/columndriverisdesignedforusein one

of three ways:

•Stand-alone row/column driver for small displays

(mixed mode)

•Row/column driver with cascaded PCF8579s

(mixed mode)

•Row driver with cascaded PCF8579s (mixed mode).

7.1 Mixed mode

In mixed mode, the device functions as both a row and

column driver. It can be used in small stand-alone

applications,or for largerdisplays withup to15 PCF8579s

(31 PCF8579s when two slave addresses are used).

See Table 1 for common display configurations.

7.2 Row mode

In row mode, the device functions as a row driver with up

to 32 row outputs and provides the clock and

synchronization signals for the PCF8579. Up to 16

PCF8579s can normally be cascaded (32 when two slave

addresses are used).

Timing signals are derived from the on-chip oscillator,

whose frequency is determined by the value of the resistor

connected between OSC and VSS.

Commands sent on the I2C-bus from the host

microcontroller set the mode (row or mixed), configuration

(multiplex rate and number of rows and columns) and

control the operation of the device. The device may have

one of two slave addresses. The only difference between

these slave addresses is the least significant bit, which is

set by the logic level applied to SA0. The PCF8578 and

PCF8579also have subaddresses. Thesubaddress ofthe

PCF8578 is only defined in mixed mode and is fixed at 0.

The RAM may only be accessed in mixed mode and data

is loaded as described for the PCF8579.

Bias levels may be generated by an external potential

divider with appropriate decoupling capacitors. For large

displays, bias sources with high drive capability should be

used. A typical mixed mode system operating with up to

15 PCF8579s is shown in Fig.5 (a stand-alone system

would be identical but without the PCF8579s).

Table 1 Possible displays conﬁgurations

Notes

1. Using 15 PCF8579s.

2. Using 16 PCF8579s.

APPLICATION MULTIPLEX

RATE MIXED MODE ROW MODE TYPICAL APPLICATIONS

ROWS COLUMNS ROWS COLUMNS

Stand alone 1 : 8 8 32 −−small digital or

alphanumerical displays

1:16 16 24 −−

1:24 24 16 −−

1:32 32 8 −−

With PCF8579 1 : 8 8(1) 632(1) 8×4(2) 640(2) alphanumeric displays and

dot matrix graphic displays

1:16 16

(1) 624(1) 16 ×2(2) 640(2)

1:24 24

(1) 616(1) 24(2) 640(2)

1:32 32

(1) 608(1) 24(2) 640(2)

2003 Apr 14 9

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

7.3 Multiplexed LCD bias generation

The bias levels required to produce maximum contrast

depend on the multiplex rate and the LCD threshold

voltage (Vth). Vth is typically defined as the RMS voltage at

which the LCD exhibits 10% contrast. Table 2 shows the

optimum voltage bias levels for the PCF8578 as functions

of Vop (Vop =V

DD −VLCD), together with the discrimination

ratios (D) for the different multiplex rates. A practical value

for Vop is obtained by equating Voff(rms) with Vth. Figure 4

showsthe first 4 rowsof Table 2as graphs. Table 3shows

the relative values of the resistors required in the

configuration of Fig.5 to produce the standard multiplex

rates.

Table 2 Optimum LCD voltages

Table 3 Multiplex rates and resistor values for Fig.5

7.4 Power-on reset

At power-on the PCF8578 resets to a defined starting

condition as follows:

1. Display blank

2. 1 : 32 multiplex rate, row mode

3. Start bank, 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I2C-bus interface is initialized.

Data transfers on the I2C-bus should be avoided for 1 ms

following power-on, to allow completion of the reset action.

PARAMETER MULTIPLEX RATE

1:8 1:16 1:24 1:32

0.739 0.800 0.830 0.850

0.522 0.600 0.661 0.700

0.478 0.400 0.339 0.300

0.261 0.200 0.170 0.150

0.297 0.245 0.214 0.193

0.430 0.316 0.263 0.230

1.447 1.291 1.230 1.196

3.370 4.080 4.680 5.190

RESISTORS MULTIPLEX RATE (n)

n = 8 n = 16, 24, 32

R1 R R

R2 R

Vop

---------

Vop

---------

Vop

---------

Vop

---------

Voff rms()

----------------------

Von rms()

---------------------

DVon rms()

off rms()

----------------------

Vop

Vth

---------

n2–()R

3n–()Rn3–()R

Fig.4 Vbias/Vop as a function of the multiplex rate.

1:8 1:16 1:32

1.0

0.8

MSA838

1:24

0.6

0.4

0.2

multiplex rate

Vbias

Vop

Vbias =V

, V3, V4, V5. See Table 2.

2003 Apr 14 10

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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ROSC OSC

VSS

SDA

SA0 CLK SYNC V3

VDD

VLCD

VSS PCF8579

columns

SCL

VSS

SCLSDA

SA0

CLK SYNC

VDD

VLCD

PCF8578

VLCD

VDD

VSS VDD

VSS

LCD DISPLAY

VDD

VSS VDD

VLCD subaddress 1

VSS VDD

40 n

columns

rows

HOST

MICROCONTROLLER

SCL

SDA

MSA843

Fig.5 Typical mixed mode configuration.

2003 Apr 14 11

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.6 LCD row/column waveforms.

MSA841

VDD

LCD

Tframe

COLUMN

SYNC

VDD

LCD

ROW 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SYNC

VDD

LCD

COLUMN

VDD

LCD

ROW 0

23222120191817161514131211109876543210

SYNC

VDD

LCD

COLUMN

VDD

LCD

ROW 0

SYNC

14131211109876543210

VDD

LCD

COLUMN

VDD

LCD

ROW 0

01234567

OFF

1:8

1:16

1:24

1:32

column

display

2003 Apr 14 12

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.

MSA840

VDD

LCD

Tframe

ROW 1

R1 (t)

VDD

LCD

ROW 2

R2 (t)

VDD

LCD

COL 1

C1 (t)

VDD

LCD

COL 2

C2 (t)

dot matrix

1:8 multiplex rate

0.261 Vop

0 V

Vop

Vstate 1(t)

Vstate 2(t) 0.261 Vop

0.261 Vop

0 V

Vop

0.478 Vop

state 1 (OFF)

state 2 (ON)

Vstate 1 (t) =C1(t) R1(t):

on(rms)

88 1

8 1

()

0.430

Vstate 2 (t) = C2(t) R2(t):

off(rms)

=8 1

8 1

()

0.297

2()

general relationship (n = multiplex rate)

on(rms)

()

off(rms)

()

2003 Apr 14 13

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.

MSA836

VDD

LCD

Tframe

ROW 1

R1 (t)

VDD

LCD

ROW 2

R2 (t)

VDD

LCD

COL 1

C1 (t)

VDD

LCD

COL 2

C2 (t)

dot matrix

1:16 multiplex rate

state 1 (OFF)

state 2 (ON)

0.2 Vop

0 V

Vop

Vstate 1(t)

0.2 Vop

0 V

Vop

Vstate 2(t)

0.6 Vop

Vstate 1 (t) =C1(t) R1(t):

on(rms)

16 16 1

16 1

()

16 =0.316

Vstate 2 (t) = C2(t) R2(t):

off(rms)

=16 1

16 1

()

16 =0.254

2()

general relationship (n = multiplex rate)

on(rms)

()

off(rms)

()

2003 Apr 14 14

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

7.5 Internal clock

The clock signal for the system may be generated by the

internal oscillator and prescaler. The frequency is

determined by the value of the resistor ROSC, see Fig.9.

For normal use a value of 330 kΩ is recommended.

The clock signal, for cascaded PCF8579s, is output at

CLK and has a frequency 1⁄6 (multiplex rate 1 : 8, 1 : 16

and 1 : 32) or 1⁄8 (multiplex rate 1 : 24) of the oscillator

frequency.

Fig.9 Oscillator frequency as a function of

external oscillator resistor, ROSC.

To avoid capacitive coupling, which could adversely affect oscillator

stability, ROSC should be placed as closely as possible to the OSC

pin. If this proves to be a problem, a filtering capacitor may be

connected in parallel to ROSC.

MSA837

102103104

103

102

fOSC

(kHz)

R(kΩ)

OSC

7.6 External clock

If an external clock is used, OSC must be connected to

VDD and the external clock signal to CLK. Table 4

summarizes the nominal CLK and SYNC frequencies.

7.7 Timing generator

The timing generator of the PCF8578 organizes the

internal data flow of the device and generates the LCD

frame synchronization pulse SYNC, whose period is an

integer multiple of the clock period. In cascaded

applications, this signal maintains the correct timing

relationship between the PCF8578 and PCF8579s in the

system.

7.8 Row/column drivers

Outputs R0 to R7 and C32 to C39 are fixed as row and

column drivers respectively. The remaining 24 outputs

R8/C8 to R31/C31 are programmable and may be

configured (in blocks of 8) to be either row or column

drivers. The row select signal is produced sequentially at

each output from R0 up to the number defined by the

multiplex rate (see Table 1). In mixed mode the remaining

outputs are configured as columns. In row mode all

programmableoutputs (R8/C8 to R31/C31) aredefinedas

row drivers and the outputs C32 to C39 should be left

open-circuit.

Using a 1 : 16 multiplex rate, two sets of row outputs are

driven, thus facilitating split-screen configurations, i.e. a

row select pulse appears simultaneously at R0 and

R16/C16,R1and R17/C17 etc. Similarly, usinga multiplex

rate of 1 : 8, four sets of row outputs are driven

simultaneously. Driver outputs must be connected directly

to the LCD. Unused outputs should be left open-circuit.

In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are

rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32

R0 to R31/C31 are rows.

Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.

Notes

1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.

2. ROSC = 330 kΩ.

OSCILLATOR

FREQUENCY

fOSC(2) (Hz)

FRAME FREQUENCY

fSYNC (Hz) MULTIPLEX RATE (n) DIVISION

RATIO CLOCK FREQUENCY

fCLK (Hz)

12288 64 1 : 8, 1 : 16, 1 : 32 6 2048

12288 64 1 : 24 8 1536

2003 Apr 14 15

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

7.9 Display mode controller

The configuration of the outputs (row or column) and the

selection of the appropriate driver waveforms are

controlled by the display mode controller.

7.10 Display RAM

The PCF8578 contains a 32 ×40-bit static RAM which

stores the display data. The RAM is divided into 4 banks

of 40 bytes (4 ×8×40 bits). During RAM access, data is

transferred to/from the RAM via the I2C-bus. The first

eight columns of data (0 to 7) cannot be displayed but

are available for general data storage and provide

compatibility with the PCF8579. There is a direct

correspondence between X-address and column output

number.

7.11 Data pointer

The addressing mechanism for the display RAM is

realized using the data pointer. This allows an individual

databyte or aseriesofdatabytesto be written into,orread

from, the display RAM, controlled by commands sent on

the I2C-bus.

7.12 Subaddress counter

The storage and retrieval of display data is dependent on

the content of the subaddress counter. Storage takes

place only when the contents of the subaddress counter

agree with the hardware subaddress. The hardware

subaddress of the PCF8578, valid in mixed mode only, is

fixed at 0000.

7.13 I2C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave

address, commands and display data bytes. It performs

the conversion of the data input (serial-to-parallel) and the

data output (parallel-to-serial). The PCF8578 acts as an

I2C-bus slave transmitter/receiver in mixed mode, and as

a slave receiver in row mode. A slave device cannot

control bus communication.

7.14 Input ﬁlters

To enhance noise immunity in electrically adverse

environments, RC low-pass filters are provided on the

SDA and SCL lines.

7.15 RAM access

RAM operations are only possible when the PCF8578 is

in mixed mode.

In this event its hardware subaddress is internally fixed at

0000 and the hardware subaddresses of any PCF8579

used in conjunction with the PCF8578 must start at 0001.

There are three RAM ACCESS modes:

•Character

•Half-graphic

•Full-graphic.

These modes are specified by bits G1 to G0 of the RAM

ACCESS command. The RAM ACCESS command

controls the order in which data is written to or read from

the RAM (see Fig.10).

To store RAM data, the user specifies the location into

which the first byte will be loaded (see Fig.11):

•Device subaddress (specified by the DEVICE SELECT

command)

•RAM X-address (specified by the LOAD X-ADDRESS

command)

•RAM bank (specified by bits Y1 and Y0 of the RAM

ACCESS command).

Subsequent data bytes will be written or read according to

the chosen RAM ACCESS mode. Device subaddresses

are automatically incremented between devices until the

last device is reached. If the last device has

subaddress 15, further display data transfers will lead to a

wrap-around of the subaddress to 0.

7.16 Display control

The display is generated by continuously shifting rows of

RAM data to the dot matrix LCD via the column outputs.

The number of rows scanned depends on the multiplex

rate set by bits M1 and M0 of the SET MODE command.

The display status (all dots on/off and normal/inverse

video) is set by bits E1 and E0 of the SET MODE

command. For bank switching, the RAM bank

corresponding to the top of the display is set by bits

B1 and B0 of the SET START BANK command. This is

shown in Fig.12. This feature is useful when scrolling in

alphanumeric applications.

7.17 TEST pin

The TEST pin must be connected to VSS.

2003 Apr 14 16

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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MSA849

01234567891011

0246810121416182022

1357911131517192123

04 8 12 16 20 24 28 32 36 40 44

1 5 9 13 17 21 25 29 33 37 41 45

2 6 10 14 18 22 26 30 34 38 42 46

3 7 11 15 19 23 27 31 35 39 43 47

RAM data bytes are

written or read as

indicated above

full-graphic mode

LSB

MSB

bank 0

bank 1

bank 2

bank 3

PCF8578/PCF8579 system RAM

1 k 16

half-graphic mode

character mode

1 byte

4 bytes

RAM

2 bytes

4 bytes

40-bits

driver 1 driver 2 driver k

PCF8578/PCF8579 PCF8579

Fig.10 RAM ACCESS mode.

2003 Apr 14 17

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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MSA835

S011110 0A

slave address

/RW

110110 A

DEVICE SELECT

000100 A

LOAD X-ADDRESS

111000 A

RAM ACCESS

last command

S011110 1A

slave address

/RW

DATA A

READ

WRITE DATA A DATA A

DEVICE SELECT:

subaddress 12

RAM ACCESS:

character mode

bank 1

LOAD X-ADDRESS: X-address = 8

RAM

bank 0

bank 1

bank 2

bank 3

Fig.11 Example of commands specifying initial data byte RAM locations.

2003 Apr 14 18

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.

MSA851

bank 0

top of LCD

bank 1

bank 2

bank 3

LCD

RAM

2003 Apr 14 19

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

C-BUS PROTOCOL

Two 7-bit slave addresses (0111100 and 0111101) are

reserved for both the PCF8578 and PCF8579. The least

significant bit of the slave address is set by connecting

inputSA0to either 0 (VSS)or1(VDD).Therefore,twotypes

of PCF8578 or PCF8579 can be distinguished on the

same I2C-bus which allows:

1. One PCF8578 to operate with up to 32 PCF8579s on

the same I2C-bus for very large applications

2. The use of two types of LCD multiplex schemes on the

same I2C-bus.

InmostapplicationsthePCF8578willhavethesameslave

address as the PCF8579.

The I2C-bus protocol is shown in Fig.13.

All communications are initiated with a start condition (S)

from the I2C-bus master, which is followed by the desired

slaveaddress and read/write bit.All devices withthis slave

address acknowledge in parallel. All other devices ignore

the bus transfer.

In WRITE mode (indicated by setting the read/write bit

LOW) one or more commands follow the slave address

acknowledgement. The commands are also

acknowledged by all addressed devices on the bus.

The last command must clear the continuation bit C.

After the last command a series of data bytes may follow.

The acknowledgement after each byte is made only by the

(A0, A1, A2 and A3) addressed PCF8579 or PCF8578

with its implicit subaddress 0. After the last data byte

has beenacknowledged,the I2C-bus master issuesa stop

condition (P).

In READ mode, indicated by setting the read/write bit

HIGH, data bytes may be read from the RAM following the

slave address acknowledgement. After this

acknowledgement the master transmitter becomes a

master receiver and the PCF8578 becomes a slave

transmitter. The master receiver must acknowledge the

reception of each byte in turn. The master receiver must

signal an end of data to the slave transmitter, by not

generating an acknowledge on the last byte clocked out of

the slave. The slave transmitter then leaves the data line

HIGH, enabling the master to generate a stop condition

(P).

Display bytes are written into, or read from, the RAM at the

address specified by the data pointer and subaddress

counter.Boththedata pointer and subaddress counterare

automaticallyincremented,enablingastream of data to be

transferred either to, or from, the intended devices.

In multiple device applications, the hardware subaddress

pins of the PCF8579s (A0 to A3) are connected to VSS or

VDD to represent the desired hardware subaddress code.

If two or more devices share the same slave address, then

each device must be allocated a unique hardware

subaddress.

2003 Apr 14 20

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string

(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ

mode).

MSA830

S011110 0AC COMMAND AP

ADISPLAY DATA

slave address /RW

acknowledge by

all addressed

PCF8578s / PCF8579s

acknowledge

by A0, A1, A2 and A3

selected PCF8578s /

PCF8579s only

n 0 byte(s)n 0 byte(s)1 byte

update data pointers

and if necessary,

subaddress counter

(a)

MSA832

S011110 0AC COMMAND A

slave address

/RW

acknowledge by

all addressed

PCF8578s / PCF8579s

n 1 byte

(b)

ADATA

S011110 1A

slave address

/RW

1DATA

n bytes last byte

update data pointers

and if necessary

subaddress counter

acknowledge

from master no acknowledge

from master

at this moment master

transmitter becomes a

master receiver and

PCF8578/PCF8579 slave

receiver becomes a

slave transmitter

MSA831

S011110 1A DATA AP

1DATA

slave address

/RW

acknowledge by

all addressed

PCF8578s / PCF8579s

last byten bytes

update data pointers

and if necessary,

subaddress counter

(c)

acknowledge

from master no acknowledge

from master

2003 Apr 14 21

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

8.1 Command decoder

The command decoder identifies command bytes that

arrive on the I2C-bus. The most-significant bit of a

commandisthecontinuation bit C (see Fig.14). When this

bitisset, it indicates thatthe next byteto be transferred will

also be a command. If the bit is reset, it indicates the

conclusion of the command transfer. Further bytes will be

regarded as display data. Commands are transferred in

WRITE mode only.

The five commands available to the PCF8578 are defined

in Tables 5 and 6. Fig.14 General information of command byte.

MSA833

REST OF OPCODE

MSB LSB

C = 0; last command.

C = 1; commands continue.

Table 5 Summary of commands

Note

1. C = command continuation bit. D = may be a logic 1 or 0.

COMMAND OPCODE(1) DESCRIPTION

SET MODE C 1 0 D D D D D multiplex rate, display status, system type

SET START BANK C 1 1 1 1 1 D D deﬁnes bank at top of LCD

DEVICE SELECT C 1 1 0 D D D D deﬁnes device subaddress

RAM ACCESS C 1 1 1 D D D D graphic mode, bank select (D D D D ≥12 is not

allowed; see SET START BANK opcode)

LOAD X-ADDRESS C 0 D D D D D D 0 to 39

2003 Apr 14 22

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Table 6 Deﬁnition of PCF8578/PCF8579 commands

COMMAND OPCODE OPTIONS DESCRIPTION

SET MODE C 1 0 T E1 E0 M1 M0 see Table 7 deﬁnes LCD drive mode

see Table 8 deﬁnes display status

see Table 9 deﬁnes system type

SET START BANK C 1 1 1 1 1 B1 B0 see Table 10 deﬁnes pointer to RAM bank

corresponding to the top of the LCD;

useful for scrolling, pseudo-motion and

background preparation of new display

DEVICE SELECT C 1 1 0 A3 A2 A1 A0 see Table 11 four bits of immediate data, bits

A0 to A3, are transferred to the

subaddress counter to deﬁne one of

sixteen hardware subaddresses

RAM ACCESS C 1 1 1 G1 G0 Y1 Y0 see Table 12 deﬁnes theauto-increment behaviour of

the address for RAM access

see Table 13 two bits of immediate data, bits Y0 to

Y1, are transferred to the X-address

pointer to deﬁne one of forty display

RAM columns

LOAD X-ADDRESS C 0 X5 X4 X3 X2 X1 X0 see Table 14 six bits of immediate data, bits

X0 to X5, are transferred to the

X-address pointer to deﬁne one of forty

display RAM columns

2003 Apr 14 23

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Table 7 Set mode option 1

Table 8 Set mode option 2

Table 9 Set mode option 3

Table 10 Set start bank option 1

LCD DRIVE MODE BITS

M1 M0

1 : 8 MUX (8 rows) 0 1

1 : 16 MUX (16 rows) 1 0

1 : 24 MUX (24 rows) 1 1

1 : 32 MUX (32 rows) 0 0

DISPLAY STATUS BITS

E1 E0

Blank 0 0

Normal 0 1

All segments on 1 0

Inverse video 1 1

SYSTEM TYPE BIT T

PCF8578 row only 0

PCF8578 mixed mode 1

START BANK POINTER BITS

B1 B0

Bank 0 0 0

Bank 1 0 1

Bank 2 1 0

Bank 3 1 1

Table 11 Device select option 1

Table 12 RAM access option 1

Note

1. See opcode for SET START BANK in Table 6.

Table 13 Device select option 1

Table 14 Device select option 1

DESCRIPTION BITS

Decimal value 0 to 15 A3 A2 A1 A0

RAM ACCESS MODE BITS

G1 G0

Character 0 0

Half-graphic 0 1

Full-graphic 1 0

Not allowed (note 1) 1 1

DESCRIPTION BITS

Decimal value 0 to 3 Y1 Y0

DESCRIPTION BITS

Decimal value 0 to 39 X5 X4 X3 X2 X1 X0

2003 Apr 14 24

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

9 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a serial clock line (SCL) which

must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this moment will be interpreted as control signals.

9.2 Start and stop conditions

Bothdataand clock lines remain HIGHwhen the bus isnot

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH, is defined as the STOP condition (P).

9.3 System conﬁguration

Adevice transmitting a messageis a 'transmitter',a device

receiving a message is the 'receiver'. The device that

controls the message flow is the 'master' and the devices

which are controlled by the master are the 'slaves'.

9.4 Acknowledge

The number of data bytes transferred between the start

and stop conditions from transmitter to receiver is

unlimited. Each data byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put

on the bus by the transmitter, whereas the master

generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also a

master must generate an acknowledge after the reception

of each byte that has been clocked out of the slave

transmitter. The device that acknowledges must pull down

the SDA line during the acknowledge clock pulse, so that

the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration). A master receiver must

signal the end of a data transmission to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event the transmitter

must leave the data line HIGH to enable the master to

generate a stop condition.

Fig.15 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

2003 Apr 14 25

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.16 Definition of start and stop condition.

MBA608

SDA

SCL P

STOP condition

SDA

SCL

START condition

Fig.17 System configuration.

MBA605

MASTER

TRANSMITTER /

RECEIVER SLAVE

TRANSMITTER /

RECEIVER MASTER

TRANSMITTER MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

Fig.18 Acknowledgement on the I2C-bus.

The general characteristics and detailed specification of the I2C-bus are available on request.

handbook, full pagewidth

MBA606 - 1

START

condition

SCL FROM

MASTER

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

clock pulse for

acknowledgement

1289

2003 Apr 14 26

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take

normal precautions appropriate to handling MOS devices (see

“Handling MOS devices”

SYMBOL PARAMETER MIN. MAX. UNIT

VDD supply voltage −0.5 +8.0 V

VLCD LCD supply voltage VDD −11 VDD V

VI1 input voltage SDA, SCL, CLK, TEST, SA0 and OSC VSS −0.5 VDD +0.5 V

VI2 input voltage V2 to V5VLCD −0.5 VDD +0.5 V

Vo1 output voltage SYNC and CLK VSS −0.5 VDD +0.5 V

Vo2 output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39 VLCD −0.5 VDD +0.5 V

IIDC input current −10 +10 mA

IODC output current −10 +10 mA

IDD, ISS, ILCD VDD, VSS or VLCD current −50 +50 mA

Ptot total power dissipation per package −400 mW

Popower dissipation per output −100 mW

Tstg storage temperature −65 +150 °C

2003 Apr 14 27

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

12 DC CHARACTERISTICS

VDD = 2.5 to 6 V; VSS =0V;V

LCD =V

DD −3.5 V to VDD −9V;T

amb =−40 to +85 °C; unless otherwise speciﬁed.

Notes

1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.

2. Resets all logic when VDD <V

POR.

3. Periodically sampled; not 100% tested.

4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input

(V2to V5, VDD and VLCD) when the specified current flows through one output under the following conditions

(see Table 2):

a) Vop =V

DD −VLCD =9V.

b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2−VLCD ≥6.65 V; V5−VLCD ≤2.35 V; ILOAD = 150 µA.

c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3−VLCD ≥4.70 V; V4−VLCD ≤4.30 V; ILOAD = 100 µA.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDD supply voltage 2.5 −6.0 V

VLCD LCD supply voltage VDD −9−VDD −3.5 V

IDD1 supply current external clock fCLK = 2 kHz; note 1 −615 µA

DD2 supply current internal clock ROSC = 330 kΩ−20 50 µA

VPOR power-on reset level note 2 0.8 1.3 1.8 V

Logic

VIL LOW level input voltage VSS −0.3VDD V

VIH HIGH level input voltage 0.7VDD −VDD V

IOL1 LOW level output current at SYNC

and CLK VOL =1V; V

DD =5V 1 −− mA

IOH1 HIGH level output current at SYNC

and CLK VOH =4V; V

DD =5V −−−1mA

OL2 LOW level output current at SDA VOL = 0.4 V; VDD =5V 3 −− mA

IL1 leakage current at SDA, SCL, SYNC,

CLK, TEST and SA0 Vi=V

DD or VSS −−+1mA

L2 leakage current at OSC Vi=V

DD −−+1µA

iinput capacitance at SCL and SDA note 3 −−5pF

LCD outputs

IL3 leakage current at V2 to V5Vi=V

DD or VLCD −2−+2µA

DC DC component of LCD drivers

R0 to R7, R8/C8 to R31/C31 and

C32 to C39

−±20 −mV

RROW output resistance R0 to R7 and

R8/C8 to R31/C31 row mode; note 4 −1.5 3 kΩ

RCOL output resistance R8/C8 to R31/C31

and C32 to C39 column mode; note 4 −36 kΩ

2003 Apr 14 28

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

13 AC CHARACTERISTICS

All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;

VSS =0V; V

LCD =V

DD −3.5 V to VDD −9 V; Tamb =−40 to +85 °C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

fCLK1 clock frequency at multiplex rates of 1 : 8,

1 : 16 and 1 : 32 ROSC = 330 kΩ; VDD = 6 V 1.2 2.1 3.3 kHz

fCLK2 clock frequency at multiplex rates of

1:24 R

OSC = 330 kΩ; VDD = 6 V 0.9 1.6 2.5 kHz

tPSYNC SYNC propagation delay −−500 ns

tPLCD driver delays VDD −VLCD =9V;

with test loads −−100 µs

I2C-bus

fSCL SCL clock frequency −−100 kHz

tSW tolerable spike width on bus −−100 ns

tBUF bus free time 4.7 −−µs

SU;STA start condition set-up time repeated start codes only 4.7 −−µs

HD;STA start condition hold time 4.0 4.0 −µs

LOW SCL LOW time 4.7 −−µs

HIGH SCL HIGH time 4.0 −−µs

rSCL and SDA rise time −−1µs

fSCL and SDA fall time −−0.3 µs

tSU;DAT data set-up time 250 −−ns

tHD;DAT data hold time 0 −−ns

tSU;STO stop condition set-up time 4.0 −−µs

Fig.19 AC test loads.

handbook, full pagewidth

MSA829

3.3 kΩ1.5 kΩ

0.5 VDD VDD

SDA

SYNC, CLK

1 nF

C39 to C32,

R31/C31 to R8/C8

and R7 to R0

2003 Apr 14 29

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Fig.20 Driver timing waveforms.

MSA834

0.7 VDD

0.3 VDD

1/ fCLK

tPSYNC

0.7 VDD

0.3 VDD

SYNC

CLK

0.5 V

tPLCD

C39 to C32,

R31/C31 to R8/C8

and R7 to R0 (V V = 9 V)

DD LCD

tPSYNC

Fig.21 I2C-bus timing waveforms.

handbook, full pagewidth

SDA

MGA728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

2003 Apr 14 30

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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14 APPLICATION INFORMATION

OSC

SDA SA0

CLK

SYNC VLCD

SCL VSS V3V4

VDD

PCF8578

V2V5

LCD DISPLAY

MSA844

R7 R8/

C8 R9/

C9 R10/

C10 R11/

C11 R12/

C12 R13/

C13 R14/

C14 R15/

C15 R16/

C16 R17/

C17 R18/

C18 R19/

C19 R20/

C20 R21/

C21 R22/

C22 R23/

C23 R24/

C24 R25/

C25 R26/

C26

R6R5R4R3R2R1R0 R27/

C27

C32 R31/

C31 R30/

C30 R29/

C29 R28/

C28C33C34C35C36C37C38C39

n.c.n.c.

TEST

OSC

Fig.22 Stand-alone application using 8 rows and 32 columns.

2003 Apr 14 31

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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Fig.23 Segment driver application for up to 384 segments.

(1) Can be used for creating blinking characters.

016 17 39

R15

LCD

DISPLAY

RAM

PCF8578

Bank

(Using 1:16 mux, the first

character data must be

loaded in bank 0 and 1

starting at byte number 16)

one line of 24 digits 7 segment

one line of 12 digits star-burst

(mux 1:16)

Total: 384 segments

PCF8578: Segment Driver

Application

1-byte

LSB

MSB

112

MLB423

(1)

C16 C17 C39

ALTERNATE DISPLAY BANK

FREE RAM

2003 Apr 14 32

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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ROSC

OSC

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 0

VSS

SCLSDA

SA0

CLK SYNC

VDD

VLCD

PCF8578

(ROW MODE)

VLCD

VDD

VSS

unused columns

SCL

SDA

VDD

VSS

rows

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 1

VDD

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns

VDD

subaddress k 1

1:32 multiplex rate

32 x 40 x k dots (k 16)

(20480 dots max.)

LCD DISPLAY

VDD

(4 2 3)R

VSS

MSA845

Fig.24 Typical LCD driver system with 1 : 32 multiplex rate.

2003 Apr 14 33

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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ROSC

OSC

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 0

VSS

SCL

SDA

SA0

CLK SYNC

VDD

VLCD

PCF8578

(ROW MODE)

VLCD

VDD

VSS VDD

VSS

unused columns

rows

SCL

SDA

VDD

VSS

1:16 multiplex rate

16 x 40 x k dots (k 16)

(10240 dots max.)

rows

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

subaddress 0

VDD VSS

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

VDD VSS

subaddress k 1

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 1

VDD

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns

VDD

subaddress k 1

1:16 multiplex rate

16 x 40 x k dots (k 16)

(10240 dots max.)

LCD DISPLAY

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

subaddress 1

VDD VSS

VDD

MSA847

Fig.25 Split screen application with 1 : 16 multiplex rate for improved contrast.

2003 Apr 14 34

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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ROSC

OSC

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 0

VSS

SCL

SDA

SA0

CLK SYNC

VDD

VLCD

PCF8578

(ROW MODE)

VLCD

VDD

VSS VDD

VSS

unused columns

SCL

SDA

VDD

VSS

1:32 multiplex rate

32 x 40 x k dots (k 16)

(20480 dots max.)

rows

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

subaddress 0

VDD VSS

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

VDD VSS

subaddress k 1

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns subaddress 1

VDD

VSS SCL SDA SA0

CLKSYNC

VDD

VLCD

VSS VSS

PCF8579

columns

VDD

subaddress k 1

1:32 multiplex rate

32 x 40 x k dots (k 16)

(20480 dots max.)

LCD DISPLAY

VSS

SCLSDASA0 CLK SYNC V3

VDD

VLCD

VDD

PCF8579

columns

subaddress 1

VDD VSS

VDD

(4 2 3)R

MSA846

Fig.26 Split screen application with 1 : 32 multiplex rate.

2003 Apr 14 35

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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SDA VLCD

SCL

VSS

VDD

PCF8578

LCD DISPLAY

MSA852

OSC

n.c.

R31/C31

RRRR (4 2 3)R

n.c.

C0 C27 C28 C39

PCF8579

n.c.

C0 C27 C28 C39

PCF8579

to other

PCF8579s

Fig.27 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).

2003 Apr 14 36

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS

Fig.28 Bonding pad locations.

Chip area: 14.93 mm2.

Bonding pad dimensions: 120 µm×120 µm.

The numbers given in the small squares refer to the pad numbers.

MBH589

VDD

VSS

SDA

4.88

3.06 mm

VLCD

OSC

SA0

TEST

CLK

SCL

C39

C38

C37

C36

C35

C34

C33

C32

R31/C31

R30/C30

R29/C29

R28/C28

R27/C27

R26/C26

R25/C25

R24/C24

R23/C23

SYNC

R8/C8

R9/C9

R10/C10

R11/C11

R12/C12

R13/C13

R14/C14

R15/C15

R16/C16

R17/C17

R18/C18

R19/C19

R20/C20

R21/C21

R22/C22

PCF8578

123456 53 52 51 50

313029282726252423222120

2003 Apr 14 37

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

Table 15 Bonding pad locations (dimensions in µm); all x/y coordinates are referenced to centre of chip, see Fig.28

PAD NUMBER SYMBOL x y PINS

VSO56 LQFP64

1 SDA 174 2241 1 7

2 SCL −30 2241 2 8

3SYNC −234 2241 3 9

4 CLK −468 2241 4 10

SS −726 2241 5 11

6 TEST −1014 2241 6 12

7 SA0 −1308 2241 7 13

8 OSC −1308 1917 8 16

DD −1308 1113 9 20

10 V2−1308 873 10 21

11 V3−1308 663 11 22

12 V4−1308 459 12 23

13 V5−1308 255 13 24

14 VLCD −1308 51 14 25

15 C39 −1308 −1149 17 29

16 C38 −1308 −1353 18 30

17 C37 −1308 −1557 19 31

18 C36 −1308 −1773 20 32

19 C35 −1308 −1995 21 33

20 C34 −1308 −2241 22 34

21 C33 −1014 −2241 23 35

22 C32 −726 −2241 24 37

23 R31/C31 −468 −2241 25 38

24 R30/C30 −234 −2241 26 39

25 R29/C29 −30 −2241 27 40

26 R28/C28 174 −2241 28 41

27 R27/C27 468 −2241 29 42

28 R26/C26 672 −2241 30 43

29 R25/C25 876 −2241 31 44

30 R24/C24 1080 −2241 32 45

31 R23/C23 1308 −2241 33 46

32 R22/C22 1308 −1977 34 48

33 R21/C21 1308 −1731 35 49

34 R20/C20 1308 −1515 36 50

35 R19/C19 1308 −1305 37 51

36 R18/C18 1308 −1101 38 52

37 R17/C17 1308 −897 39 53

38 R16/C16 1308 −693 40 54

2003 Apr 14 38

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

39 R15/C15 1308 −489 41 55

40 R14/C14 1308 −285 42 56

41 R13/C13 1308 −81 43 57

42 R12/C12 1308 123 44 58

43 R11/C11 1308 351 45 59

44 R10/C10 1308 603 46 60

45 R9/C9 1308 1101 47 61

46 R8/C8 1308 1305 48 62

47 R7 1308 1515 49 63

48 R6 1308 1731 50 64

49 R5 1308 1977 51 1

50 R4 1308 2241 52 2

51 R3 1080 2241 53 3

52 R2 876 2241 54 4

53 R1 672 2241 55 5

54 R0 468 2241 56 6

−n.c. −−15, 16 14, 15, 17 to 19,

26 to 28, 36, 47

PAD NUMBER SYMBOL x y PINS

VSO56 LQFP64

2003 Apr 14 39

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

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16 CHIP-ON-GLASS INFORMATION

MSA850

VDD

PCF8578

VLCD

PCF8579

C39

C38

C37

VDD

VLCD

n.c.

VSS

TEST

SA0

CLK

SCL

SDA

SYNC

VDD

VLCD

SA0

OSC

C39

C38

VSS

TEST

CLK

SCL

SDA

SYNC

ROSC

R0 to R31

SYNC

SCL

SDA

VSS

CLK

VLCD

SYNC

SCL

SDA

VSS

CLK

C0 C1 C2

LCD

DISPLAY

VDD

Fig.29 Typical chip-on-glass application (viewed from the underside of the chip).

If inputs SA0 and A0 to A3 are left unconnected they are internally pulled to VDD.

2003 Apr 14 40

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

17 PACKAGE OUTLINES

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

0.3

0.1 3.0

2.8 0.25 0.42

0.30 0.22

0.14 21.65

21.35 11.1

11.0 0.75 15.8

15.2 1.45

1.30 0.90

0.55 7

0.1 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

1.6

1.4

SOT190-1 97-08-11

03-02-19

detail X

vMA

(A )

56 29

281

pin 1 index

0.012

0.004 0.12

0.11 0.017

0.012 0.0087

0.0055 0.85

0.84 0.44

0.43 0.0295

2.25

0.089

0.62

0.60 0.057

0.051 0.035

0.022

0.004

0.2

0.008 0.004

0.063

0.055

0.01

0 5 10 mm

scale

VSO56: plastic very small outline package; 56 leads SOT190-1

max.

3.3

0.13

Notes

1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

2003 Apr 14 41

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

UNIT A

max. A1A2A3bpcE

(1) eH

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 10.1

9.9 0.5 12.15

11.85 1.45

1.05 7

0.12 0.11 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2 MS-026136E10 00-01-19

03-02-25

D(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

EA1

detail X

(A )

HA2

vMB

vMA

48 33

pin 1 index

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

2003 Apr 14 42

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

18 SOLDERING

18.1 Introduction to soldering surface mount

packages

Thistextgives a very brief insight to acomplextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certainsurface mount ICs,butitisnotsuitable for finepitch

SMDs. In these situations reflow soldering is

recommended.

18.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

totheprinted-circuit board by screen printing,stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferably be kept:

•below 220 °C for all the BGA packages and packages

with a thickness ≥2.5mm and packages with a

thickness <2.5 mm and a volume ≥350 mm3 so called

thick/large packages

•below 235 °C for packages with a thickness <2.5 mm

and a volume <350 mm3 so called small/thin packages.

18.3 Wave soldering

Conventional single wave soldering is not recommended

forsurface mount devices (SMDs)orprinted-circuitboards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackages with leadsonfoursides,thefootprint must

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

18.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2003 Apr 14 43

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

18.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. Formoredetailedinformationon the BGA packages refertothe

“(LF)BGAApplicationNote

”(AN01026);orderacopy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE(1) SOLDERING METHOD

WAVE REFLOW(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable

PLCC(4), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(4)(5) suitable

SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable

2003 Apr 14 44

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

19 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL DATA SHEET

STATUS(1) PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

20 DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseoratanyotherconditionsabovethosegiveninthe

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentation orwarrantythatsuch applicationswillbe

suitable for the specified use without further testing or

modification.

21 DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorselling theseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

2003 Apr 14 45

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

22 PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the

components in the I2C system provided the system conforms to the I2C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2003 Apr 14 46

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

NOTES

2003 Apr 14 47

Philips Semiconductors Product speciﬁcation

LCD row/column driver for

dot matrix graphic displays PCF8578

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Philips Semiconductors – a world wide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands 403512/05/pp48 Date of release: 2003 Apr 14 Document order number: 9397 750 11026