MT48LC2M32B2TG-6 - Micron

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

2 Meg x 32

Configuration 512K x 32 x 4 banks

Refresh Count 4K

Row Addressing 2K (A0-A10)

Bank Addressing 4 (BA0, BA1)

Column Addressing 256 (A0-A7)

PIN ASSIGNMENT (TOP VIEW)

86-PIN TSOP

FEATURES

• PC100 functionality

• Fully synchronous; all signals registered on

positive edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 4,096-cycle refresh (15.6µs/row)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2, and 3

OPTIONS MARKING

• Configuration

2 Meg x 32 (512K x 32 x 4 banks) 2M32B2

• Plastic Package - OCPL1

86-pin TSOP (400 mil) TG

• Timing (Cycle Time)

5ns (200 MHz) -5

5.5ns (183 MHz) -55

6ns (166 MHz) -6

7ns (143 MHz) -7

• Operating Temperature Range

Commercial (0° to +70°C) None

Extended (-40°C to +85°C) IT2

NOTE: 1. Off-center parting line

2. Available on -7

Part Number Example:

MT48LC2M32B2TG-7

Note: The # symbol indicates signal is active LOW.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM0

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQM1

CLK

CKE

DQM3

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

SYNCHRONOUS

DRAM

MT48LC2M32B2 - 512K x 32 x 4 banks

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/sdramds

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

GRADE FREQUENCY CL = 3* TIME TIME

-5 200 MHz 4.5ns 1.5ns 1ns

-55 183 MHz 5ns 1.5ns 1ns

-6 166 MHz 5.5ns 1.5ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

*CL = CAS (READ) latency

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst se-

quence.

The 64Mb SDRAM uses an internal pipelined archi-

tecture to achieve high-speed operation. This archi-

tecture is compatible with the 2n rule of prefetch archi-

tectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while ac-

cessing one of the other three banks will hide the

precharge cycles and provide seamless, high-speed,

random-access operation.

The 64Mb SDRAM is designed to operate in 3.3V,

low-power memory systems. An auto refresh mode is

provided, along with a power-saving, power-down

mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-

nously burst data at a high data rate with automatic

column-address generation, the ability to interleave

between internal banks to hide precharge time and

the capability to randomly change column addresses

on each clock cycle during a burst access.

GENERAL DESCRIPTION

The 64Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 67,108,864-bits. It

is internally configured as a quad-bank DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the

16,777,216-bit banks is organized as 2,048 rows by 256

columns by 32 bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, which is then followed by

a READ or WRITE command. The address bits regis-

tered coincident with the ACTIVE command are used

to select the bank and row to be accessed (BA0, BA1

select the bank, A0-A10 select the row). The address

bits registered coincident with the READ or WRITE com-

mand are used to select the starting column location

for the burst access.

64Mb (x32) SDRAM PART NUMBER

PART NUMBER ARCHITECTURE

MT48LC2M32B2TG 2 Meg x 32

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

TABLE OF CONTENTS

Functional Block Diagram - 2 Meg x 32 ................. 4

Pin Descriptions ..................................................... 5

Functional Description ......................................... 6

Initialization ...................................................... 6

Mode Register ............................................... 6

Burst Length ............................................ 6

Burst Type ............................................... 7

CAS Latency ............................................ 8

Operating Mode ...................................... 8

Write Burst Mode .................................... 8

Commands ............................................................ 9

Truth Table 1 (Commands and DQM Operation) ............ 9

Command Inhibit ............................................. 10

No Operation (NOP) .......................................... 10

Load Mode Register ........................................... 10

Active ................................................................ 10

Read ................................................................ 10

Write ................................................................ 10

Precharge ........................................................... 10

Auto Precharge .................................................. 10

Burst Terminate ................................................. 11

Auto Refresh ...................................................... 11

Self Refresh ........................................................ 11

Operation ............................................................... 12

Bank/Row Activation ........................................ 12

Reads ................................................................ 13

Writes ................................................................ 19

Precharge ........................................................... 21

Power-Down ...................................................... 21

Clock Suspend .................................................. 22

Burst Read/Single Write .................................... 22

Concurrent Auto Precharge .............................. 23

Write with Auto Precharge ............................... 24

Truth Table 2 (CKE) ................................................ 25

Truth Table 3 (Current State, Same Bank) ..................... 26

Truth Table 4 (Current State, Different Bank) ................. 28

Absolute Maximum Ratings .................................. 30

DC Electrical Characteristics

and Operating Conditions ...................................... 30

IDD Specifications and Conditions ......................... 30

Capacitance ............................................................ 32

AC Electrical Characteristics (Timing Table) .... 32

AC Electrical Characteristics ................................... 34

Timing Waveforms

Initialize and Load Mode Register .................... 36

Power-Down Mode .......................................... 37

Clock Suspend Mode ........................................ 38

Auto Refresh Mode ........................................... 39

Self Refresh Mode ............................................. 40

Reads

Read – Single Read ....................................... 41

Read – Without Auto Precharge ................. 42

Read – With Auto Precharge ....................... 43

Alternating Bank Read Accesses .................. 44

Read – Full-Page Burst ................................. 45

Read – DQM Operation .............................. 46

Writes

Write – Single Write ..................................... 47

Write – Without Auto Precharge ................ 48

Write – With Auto Precharge ...................... 49

Alternating Bank Write Accesses ................. 50

Write – Full-Page Burst ................................ 51

Write – DQM Operation ............................. 52

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32 SDRAM

RAS#

CAS#

CLK

CS#

WE#

CKE

A0-A10,

BA0, BA1

DQM0-

DQM3

256

(x32)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(2,048 x 256 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

2048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0-

DQ31

DATA

INPUT

DATA

OUTPUT

BANK1

BANK0

BANK2

BANK3

4 4

REFRESH

COUNTER

MODE REGISTER

CONTROL

LOGIC

COMMAND

DECODE

ROW-

ADDRESS

MUX

ADDRESS

COLUMN-

ADDRESS

COUNTER/

LATCH

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

68 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst

counter and controls the output registers.

67 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where

CKE becomes asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down and self refresh

modes, providing low standby power. CKE may be tied HIGH.

20 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS# provides for external bank selection on systems with multiple banks.

CS# is considered part of the command code.

17, 18, 19 WE#, CAS#, Input Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the

RAS# command being entered.

16, 71, 28, 59 DQM0- Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal

DQM3 for write accesses and an output enable signal for read accesses. Input data

is masked during a WRITE cycle. The output buffers are placed in a High-Z

state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ0-

DQ7; DQM1 corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23;

and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same

state when referenced as DQM.

22, 23 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied.

25-27, 60-66, 24 A0-A10 Input Address Inputs: A0-A10 are sampled during the ACTIVE command (row-

address A0-A10) and READ/WRITE command (column-address A0-A7 with A10

defining auto precharge) to select one location out of the memory array in

the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

2, 4, 5, 7, 8, 10, 11, 13, DQ0-DQ31 Input/ Data I/Os: Data bus.

74, 76, 77, 79, 80, 82, 83, Output

85, 31, 33, 34, 36, 37, 39,

40, 42, 45, 47, 48, 50, 51,

53, 54, 56

14, 21, 30, 57, 69, 70, 73 NC – No Connect: These pins should be left unconnected. Pin 70 is reserved

for SSTL reference voltage supply.

3, 9, 35, 41, 49, 55, 75, 81 V

Q Supply DQ Power Supply: Isolated on the die for improved noise immunity.

6, 12, 32, 38, 46, 52, 78, 84 V

Q Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

1, 15, 29, 43 V

Supply Power Supply: +3.3V ±0.3V. (See note 27 on page 35.)

44, 58, 72, 86 V

Supply Ground.

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

FUNCTIONAL DESCRIPTION

In general, this 64Mb SDRAM (512K x 32 x 4 banks) is

a quad-bank DRAM that operates at 3.3V and includes

a synchronous interface (all signals are registered on

the positive edge of the clock signal, CLK). Each of the

16,777,216-bit banks is organized as 2,048 rows by 256

columns by 32-bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, which is then followed by

a READ or WRITE command. The address bits regis-

tered coincident with the ACTIVE command are used

to select the bank and row to be accessed (BA0 and BA1

select the bank, A0-A10 select the row). The address

bits (A0-A7) registered coincident with the READ or

WRITE command are used to select the starting col-

umn location for the burst access.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-

mation covering device initialization, register defini-

tion, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other

than those specified may result in undefined opera-

tion. Once power is applied to VDD and VDDQ (simulta-

neously) and the clock is stable (stable clock is defined

as a signal cycling within timing constraints specified

for the clock pin), the SDRAM requires a 100µs delay

prior to issuing any command other than a COMMAND

INHIBIT or a NOP. Starting at some point during this

100µs period and continuing at least through the end

of this period, COMMAND INHIBIT or NOP commands

should be applied.

Once the 100µs delay has been satisfied with at

least one COMMAND INHIBIT or NOP command hav-

ing been applied, a PRECHARGE command should be

applied. All banks must then be precharged, thereby

placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles

are complete, the SDRAM is ready for Mode Register

programming. Because the Mode Register will power

up in an unknown state, it should be loaded prior to

applying any operational command.

MODE REGISTER

The Mode Register is used to define the specific

mode of operation of the SDRAM. This definition in-

cludes the selection of a burst length, a burst type, a

CAS latency, an operating mode and a write burst mode,

as shown in Figure 1. The Mode Register is programmed

via the LOAD MODE REGISTER command and will re-

tain the stored information until it is programmed again

or the device loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-

leaved), M4-M6 specify the CAS latency, M7 and M8

specify the operating mode, M9 specifies the write burst

mode, and M10 is reserved for future use.

The Mode Register must be loaded when all banks

are idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating

either of these requirements will result in unspecified

operation.

Burst Length

Read and write accesses to the SDRAM are burst

oriented, with the burst length being programmable,

as shown in Figure 1. The burst length determines the

maximum number of column locations that can be ac-

cessed for a given READ or WRITE command. Burst

lengths of 1, 2, 4, or 8 locations are available for both the

sequential and the interleaved burst types, and a full-

page burst is available for the sequential type. The

full-page burst is used in conjunction with the BURST

TERMINATE command to generate arbitrary burst

lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-

lected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached. The block is uniquely se-

lected by A1-A7 when the burst length is set to two; by

A2-A7 when the burst length is set to four; and by A3-A7

when the burst length is set to eight. The remaining

(least significant) address bit(s) is (are) used to select

the starting location within the block. Full-page bursts

wrap within the page if the boundary is reached.

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

NOTE: 1. For a burst length of two, A1-A7 select the block-

of-two burst; A0 selects the starting column

within the block.

2. For a burst length of four, A2-A7 select the block-

of-four burst; A0-A1 select the starting column

within the block.

3. For a burst length of eight, A3-A7 select the block-

of-eight burst; A0-A2 select the starting column

within the block.

4. For a full-page burst, the full row is selected and

A0-A7 select the starting column.

5. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

6. For a burst length of one, A0-A7 select the unique

column to be accessed, and mode register bit M3

is ignored.

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

200-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7 Cn, Cn + 1, Cn + 2

Page Cn + 3, Cn + 4... Not Supported

(256) (Location 0 -256) …Cn - 1,

Cn…

Figure 1

Mode Register Definition

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 1.

000

001

010

011

100

101

110

111

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard operation

All other states reserved

Defined

Burst Type

Sequential

Interleave

CAS Latency

Reserved

000

001

010

011

100

101

110

111

Burst Length

Burst lengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M1M2

M4M5M6

M6 - M0

M8 M7

Op Mode

A10

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

1. *Should program

A10, BA0, and BA1= “0”

to ensure compatibility

with future device

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64Mb: x32

SDRAM

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

- 5 - - ≤ 200

-55 - - ≤ 183

- 6 ≤ 50 ≤ 100 ≤ 166

- 7 ≤ 50 ≤ 100 ≤ 143

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values for

M7 and M8 are reserved for future use and/or test

modes. The programmed burst length applies to both

READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with

future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; when

M9 = 1, the programmed burst length applies to READ

bursts, but write accesses are single-location (nonburst)

accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, be-

tween the registration of a READ command and the

availability of the first piece of output data. The la-

tency can be set to one, two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available by

clock edge n + m. The DQs will start driving as a result of

the clock edge one cycle earlier (n + m - 1), and provided

that the relevant access times are met, the data will be

valid by clock edge n + m. For example, assuming that

the clock cycle time is such that all relevant access times

are met, if a READ command is registered at T0 and the

latency is programmed to two clocks, the DQs will start

driving after T1 and the data will be valid by T2, as

shown in Figure 2. Table 2 below indicates the operat-

ing frequencies at which each CAS latency setting can

be used.

Figure 2

CAS Latency

Table 2

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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64Mb: x32

SDRAM

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H

Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H

Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active 8

Write Inhibit/Output High-Z ––––H – High-Z 8

appear following the Operation section; these tables

provide current state/next state information.

Commands

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a written descrip-

tion of each command. Three additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 define the op-code written to the Mode Register.

3. A0-A10 provide row address, BA0 and BA1 determine which bank is made active.

4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while

A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from

or written to.

5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and

BA0 and BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0

controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls

DQ24-DQ31.

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64Mb: x32

SDRAM

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM, re-

gardless of whether the CLK signal is enabled. The

SDRAM is effectively deselected. Operations already

in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to an SDRAM which is selected (CS# is

LOW). This prevents unwanted commands from being

registered during idle or wait states. Operations already

in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0-A10. See

mode register heading in the Register Definition sec-

tion. The LOAD MODE REGISTER command can only

be issued when all banks are idle, and a subsequent

executable command cannot be issued until tMRD is

met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The

value on the BA0 and BA1 inputs selects the bank, and

the address provided on inputs A0-A10 selects the row.

This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A

PRECHARGE command must be issued before open-

ing a different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0 and BA1

(B1) inputs selects the bank, and the address provided

on inputs A0-A7 selects the starting column location.

The value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

READ burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Read data

appears on the DQs subject to the logic level on the

DQM inputs two clocks earlier. If a given DQMx signal

was registered HIGH, the corresponding DQs will be

High-Z two clocks later; if the DQMx signal was regis-

tered LOW, the corresponding DQs will provide valid

data. DQM0 corresponds to DQ0-DQ7, DQM1 corre-

sponds to DQ8-DQ15, DQM2 corresponds to DQ16-

DQ23 and DQM3 corresponds to DQ24-DQ31.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0 and BA1

inputs selects the bank, and the address provided on

inputs A0-A7 selects the starting column location. The

value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

WRITE burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array

subject to the DQM input logic level appearing coinci-

dent with the data. If a given DQM signal is registered

LOW, the corresponding data will be written to memory;

if the DQM signal is registered HIGH, the correspond-

ing data inputs will be ignored, and a WRITE will not be

executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in all

banks. The bank(s) will be available for a subsequent

row access a specified time (tRP) after the PRECHARGE

command is issued. Input A10 determines whether

one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0

and BA1 select the bank. Otherwise BA0 and BA1 are

treated as “Don’t Care.” Once a bank has been

precharged, it is in the idle state and must be activated

prior to any READ or WRITE commands being issued to

that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the

same individual-bank PRECHARGE function de-

scribed above, without requiring an explicit command.

This is accomplished by using A10 to enable auto

precharge in conjunction with a specific READ or WRITE

command. A PRECHARGE of the bank/row that is ad-

dressed with the READ or WRITE command is auto-

matically performed upon completion of the READ or

WRITE burst, except in the full-page burst mode, where

auto precharge does not apply. Auto precharge is non-

persistent in that it is either enabled or disabled for

each individual READ or WRITE command.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. The user

must not issue another command to the same bank

until the precharge time (tRP) is completed. This is

determined as if an explicit PRECHARGE command

was issued at the earliest possible time, as described

for each burst type in the Operation section of this data

sheet.

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64Mb: x32

SDRAM

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated,

as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analagous to CAS#-BEFORE-RAS#

(CBR) REFRESH in conventional DRAMs. This com-

mand is nonpersistent, so it must be issued each time

a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”

during an AUTO REFRESH command. The 64Mb

SDRAM requires 4,096 AUTO REFRESH cycles every

64ms (tREF), regardless of width option. Providing a

distributed AUTO REFRESH command every 15.625µs

will meet the refresh requirement and ensure that each

row is refreshed. Alternatively, 4,096 AUTO REFRESH

commands can be issued in a burst at the minimum

cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the

SDRAM retains data without external clocking. The SELF

REFRESH command is initiated like an AUTO REFRESH

command except CKE is disabled (LOW). Once the SELF

REFRESH command is registered, all the inputs to the

SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM pro-

vides its own internal clocking, causing it to perform its

own AUTO REFRESH cycles. The SDRAM must remain

in self refresh mode for a minimum period equal to

tRAS and may remain in self refresh mode for an indefi-

nite period beyond that.

The procedure for exiting self refresh requires a se-

quence of commands. First, CLK must be stable (stable

clock is defined as a signal cycling within timing con-

straints specified for the clock pin) prior to CKE going

back HIGH. Once CKE is HIGH, the SDRAM must have

NOP commands issued (a minimum of two clocks) for

tXSR because time is required for the completion of any

internal refresh in progress.

Upon exiting SELF REFRESH mode, AUTO REFRESH

commands must be issued every 15.625ms or less as

both SELF REFRESH and AUTO REFRESH utililze the

row refresh counter.

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64Mb: x32

SDRAM

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be is-

sued to a bank within the SDRAM, a row in that bank

must be “opened.” This is accomplished via the AC-

TIVE command, which selects both the bank and the

row to be activated. See Figure 3.

After opening a row (issuing an ACTIVE command),

a READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) should

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock edge

after the ACTIVE command on which a READ or WRITE

command can be issued. For example, a tRCD specifi-

cation of 20ns with a 125 MHz clock (8ns period) results

in 2.5 clocks, rounded to 3. This is reflected in Figure 4,

which covers any case where 2 < tRCD (MIN)/tCK - 3.

(The same procedure is used to convert other specifi-

cation limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous

active row has been “closed” (precharged). The mini-

mum time interval between successive ACTIVE com-

mands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row-access over-

head. The minimum time interval between successive

ACTIVE commands to different banks is defined by

tRRD.

Figure 4

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK - 3

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD (MIN)

tRCD (MIN) = 20ns, tCK = 8ns

tRCD (MIN) x tCK

where x = number of clocks for equation to be true.

tRCD (MIN) +0.5 tCK

tCK tCK tCK

DON’T CARE

Figure 3

Activating a Specific Row in a

Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10 ROW

ADDRESS

HIGH

BA0, BA1 BANK

ADDRESS

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64Mb: x32

SDRAM

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go High-Z. A

full-page burst will continue until terminated. (At the

end of the page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-

length READ burst may be immediately followed by

data from a READ command. In either case, a continu-

ous flow of data can be maintained. The first data ele-

ment from the new burst follows either the last ele-

ment of a completed burst or the last desired data ele-

ment of a longer burst that is being truncated. The new

READ command should be issued x cycles before the

clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This

is shown in Figure 7 for CAS latencies of one, two and

READs

READ bursts are initiated with a READ command,

as shown in Figure 5.

The starting column and bank addresses are pro-

vided with the READ command, and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the ge-

neric READ commands used in the following illustra-

tions, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-

lowing the CAS latency after the READ command. Each

subsequent data-out element will be valid by the next

positive clock edge. Figure 6 shows general timing for

each possible CAS latency setting.

Figure 5

READ Command

Figure 6

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

A10

BA0, 1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A8, A9

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64Mb: x32

SDRAM

three; data element n + 3 is either the last of a burst of

four or the last desired of a longer burst. This 64Mb

SDRAM uses a pipelined architecture and therefore

does not require the 2n rule associated with a prefetch

architecture. A READ command can be initiated on any

Figure 7

Consecutive READ Bursts

clock cycle following a previous READ command. Full-

speed random read accesses can be performed to the

same bank, as shown in Figure 8, or each subsequent

READ may be performed to a different bank.

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 0 cycles

NOTE: Each READ command may be to either bank. DQM is LOW.

CAS Latency = 1

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ NOP

X = 2 cycles

CAS Latency = 3

DON’T CARE

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64Mb: x32

SDRAM

Figure 8

Random READ Accesses

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

DOUT

READ

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK,

COL a

BANK,

COL x

BANK,

COL m

CLK

DOUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

DOUT

READ READ READ NOP

BANK,

COL a

BANK,

COL x

BANK,

COL m

CLK

DOUT

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

DOUT

READ READ READ

BANK,

COL a

BANK,

COL x

BANK,

COL m

CAS Latency = 1

CAS Latency = 2

CAS Latency = 3

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64Mb: x32

SDRAM

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-

length READ burst may be immediately followed by

data from a WRITE command (subject to bus turn-

around limitations). The WRITE burst may be initiated

on the clock edge immediately following the last (or last

desired) data element from the READ burst, provided

that I/O contention can be avoided. In a given system

design, there may be a possibility that the device driv-

ing the input data will go Low-Z before the SDRAM DQs

go High-Z. In this case, at least a single-cycle delay

should occur between the last read data and the WRITE

command.

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS BANK,

COL n

WRITE

DIN b

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

Figure 10

READ to WRITE with

Extra Clock Cycle

Figure 9

READ to WRITE

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

DQ DOUT n

COMMAND

DIN b

ADDRESS BANK,

COL n

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ

command ma

be to an

bank

and the WRITE command

The DQM input is used to avoid I/O contention, as

shown in Figures 9 and 10. The DQM signal must be

asserted (HIGH) at least two clocks prior to the WRITE

command (DQM latency is two clocks for output buff-

ers) to suppress data-out from the READ. Once the

WRITE command is registered, the DQs will go High-Z

(or remain High-Z), regardless of the state of the DQM

signal; provided the DQM was active on the clock just

prior to the WRITE command that truncated the READ

command. If not, the second WRITE will be an invalid

WRITE. For example, if DQM was low during T4 in Fig-

ure 10, then the WRITEs at T5 and T7 would be valid,

while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for input

buffers) to ensure that the written data is not masked.

Figure 9 shows the case where the clock frequency al-

lows for bus contention to be avoided without adding a

NOP cycle, and Figure 10 shows the case where the

additional NOP is needed.

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64Mb: x32

SDRAM

Figure 11

READ to PRECHARGE

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same

bank (provided that auto precharge was not acti-

vated), and a full-page burst may be truncated with a

PRECHARGE command to the same bank. The

PRECHARGE command should be issued x cycles be-

fore the clock edge at which the last desired data ele-

ment is valid, where x equals the CAS latency minus

one. This is shown in Figure 11 for each possible CAS

latency; data element n + 3 is either the last of a burst of

four or the last desired of a longer burst. Following the

PRECHARGE command, a subsequent command to

the same bank cannot be issued until tRP is met. Note

that part of the row precharge time is hidden during

the access of the last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the

optimum time (as described above) provides the same

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE ACTIVE

tRP

NOTE: DQM is LOW.

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK a,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE ACTIVE

tRP

BANK a,

ROW

BANK

(a or all)

DON’T CARE

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

BANK a,

COL

BANK a,

ROW

BANK

(a or all)

BANK a,

COL

BANK a,

ROW

BANK

(a or all)

X = 2 cycles

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64Mb: x32

SDRAM

Figure 12

Terminating a READ Burst

operation that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropri-

ate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to trun-

cate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length READ

bursts may be truncated with a BURST TERMINATE

command, provided that auto precharge was not acti-

vated. The BURST TERMINATE command should be

issued x cycles before the clock edge at which the last

desired data element is valid, where x equals the CAS

latency minus one. This is shown in Figure 12 for each

possible CAS latency; data element n + 3 is the last

desired data element of a longer burst.

DON’T CARE

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

NOTE: DQM is LOW.

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

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64Mb: x32

SDRAM

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 13.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge

is either enabled or disabled for that access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the ge-

neric WRITE commands used in the following

illustrations,auto precharge is disabled.

During WRITE bursts, the first valid data-in ele-

ment will be registered coincident with the WRITE com-

mand. Subsequent data elements will be registered on

each successive positive clock edge. Upon completion

of a fixed-length burst, assuming no other commands

have been initiated, the DQs will remain High-Z and

any additional input data will be ignored (see Figure

14). A full-page burst will continue until terminated.

(At the end of the page, it will wrap to column 0 and

continue.)

Data for any WRITE burst may be truncated with a

subsequent WRITE command, and data for a fixed-

length WRITE burst may be immediately followed by

data for a WRITE command. The new WRITE command

Figure 15

WRITE to WRITE

can be issued on any clock following the previous WRITE

command, and the data provided coincident with the

new command applies to the new command. An ex-

ample is shown in Figure 15. Data n + 1 is either the last

of a burst of two or the last desired of a longer burst.

This 64Mb SDRAM uses a pipelined architecture and

therefore does not require the 2n rule associated with a

prefetch architecture. A WRITE command can be initi-

ated on any clock cycle following a previous WRITE

command. Full-speed random write accesses within a

page can be performed to the same bank, as shown in

Figure 16, or each subsequent WRITE may be per-

formed to a different bank.

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOPWRITE

DIN

n + 1

NOP

BANK,

COL n

Figure 14

WRITE Burst

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A0–A7

A10

BA0, 1

A8, A9

Figure 13

WRITE Command

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL n

BANK,

COL b

n + 1

NOTE: DQM is LOW. Each WRITE command may

be to any bank.

DON’T CARE

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64Mb: x32

SDRAM

quency, in auto precharge mode. In addition, when

truncating a WRITE burst, the DQM signal must be

used to mask input data for the clock edge prior to, and

the clock edge coincident with, the PRECHARGE com-

mand. An example is shown in Figure 18. Data n + 1 is

either the last of a burst of two or the last desired of a

longer burst. Following the PRECHARGE command, a

subsequent command to the same bank cannot be

issued until tRP is met. The precharge will actually be-

gin coincident with the clock-edge (T2 in Figure 18) on

a “one-clock” tWR and sometime between the first and

second clock on a “two-clock” tWR (between T2 and T3

in Figure 18.)

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the

optimum time (as described above) provides the same

operation that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropri-

ate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to trun-

cate fixed-length or full-page bursts.

Figure 18

WRITE to PRECHARGE

Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-

length WRITE burst may be immediately followed by a

READ command. Once the READ command is regis-

tered, the data inputs will be ignored, and WRITEs will

not be executed. An example is shown in Figure 17.

Data n + 1 is either the last of a burst of two or the last

desired of a longer burst.

Data for a fixed-length WRITE burst may be fol-

lowed by, or truncated with, a PRECHARGE command

to the same bank (provided that auto precharge was

not activated), and a full-page WRITE burst may be

truncated with a PRECHARGE command to the same

bank. The PRECHARGE command should be issued

tWR after the clock edge at which the last desired input

data element is registered. The “two-clock” write-back

requires at least one clock plus time, regardless of fre-

Figure 17

WRITE to READ

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

DIN

n + 1

DOUT

READ NOP NOP

BANK,

COL b

NOP

DOUT

b + 1

T4 T5

Figure 16

Random WRITE Cycles

DON’T CAR

CLK

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

WRITE WRITE WRITE

BANK,

COL a

BANK,

COL x

BANK,

COL m

NOTE: Each WRITE command ma

be to an

bank. DQM is LOW.

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE PRECHARGE NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

tWR

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE PRECHARGE NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

tWR

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed

length of two.

BANK a,

ROW

NOP

tWR = 2 CLK (when tWR > tCK)

tWR = 1 CLK (tCK > tWR)

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64Mb: x32

SDRAM

Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When

truncating a WRITE burst, the input data applied coin-

cident with the BURST TERMINATE command will be

ignored. The last data written (provided that DQM is

LOW at that time) will be the input data applied one

clock previous to the BURST TERMINATE command.

This is shown in Figure 19, where data n is the last

desired data element of a longer burst.

Figure 21

Power-Down

DON’T CARE

tRAS

tRCD

tRC

All banks idle

Input buffers gated off

Exit power-down mode.

(

)(

)

(

)(

)

(

)(

)

tCKS > t

CKS

COMMAND NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

(

)(

)

(

)(

)

Figure 20

PRECHARGE Command

Figure 19

Terminating a WRITE Burst

CLK

T2T1T0

COMMAND

ADDRESS BANK,

COL n

WRITE BURST

TERMINATE

COMMAND

DIN

(ADDRESS)

(DATA)

NOTE: DQMs are LOW.

PRECHARGE

The PRECHARGE command (Figure 20) is used to

deactivate the open row in a particular bank or the

open row in all banks. The bank(s) will be available for

a subsequent row access some specified time (tRP) af-

ter the PRECHARGE command is issued. Input A10

determines whether one or all banks are to be

precharged, and in the case where only one bank is to

be precharged, inputs BA0 and BA1 select the bank.

When all banks are to be precharged, inputs BA0 and

BA1 are treated as “Don’t Care.” Once a bank has been

precharged, it is in the idle state and must be activated

prior to any READ or WRITE commands being issued to

that bank.

POWER-DOWN

Power-down occurs if CKE is registered LOW coinci-

dent with a NOP or COMMAND INHIBIT when no ac-

cesses are in progress (see Figure 21). If power-down

occurs when all banks are idle, this mode is referred to

as precharge power-down; if power-down occurs when

there is a row active in either bank, this mode is referred

to as active power-down. Entering power-down deacti-

vates the input and output buffers, excluding CKE, for

maximum power savings while in standby. The device

may not remain in the power-down state longer than

the refresh period (64ms) since no refresh operations

are performed in this mode.

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired

clock edge (meeting tCKS).

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

HIGH

All Banks

Bank Selected

A0–A9

BA0, 1

BANK

ADDRESS

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64Mb: x32

SDRAM

DON’T CARE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1

n + 2

Figure 22

CLOCK SUSPEND During WRITE Burst

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

Figure 23

CLOCK SUSPEND During READ Burst

CLOCK SUSPEND

The clock suspend mode occurs when a column ac-

cess/burst is in progress and CKE is registered LOW. In

the clock suspend mode, the internal clock is deacti-

vated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is

sampled LOW, the next internal positive clock edge is

suspended. Any command or data present on the in-

put pins at the time of a suspended internal clock edge

is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as

long as the clock is suspended. (See examples in Fig-

ures 22 and 23.)

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will re-

sume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the Mode

result in the access of a single column location (burst of

one), regardless of the programmed burst length. READ

commands access columns according to the pro-

grammed burst length and sequence, just as in the

normal mode of operation (M9 = 0).

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

CONCURRENT AUTO PRECHARGE

An access command to (READ or WRITE) another

bank while an access command with auto precharge

enabled is executing is not allowed by SDRAMs, unless

the SDRAM supports CONCURRENT AUTO

PRECHARGE. Micron SDRAMs support CONCURRENT

AUTO PRECHARGE. Four cases where CONCURRENT

AUTO PRECHARGE occurs are defined below.

READ with auto precharge

1. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a READ

on bank n, CAS latency later. The PRECHARGE to

bank n will begin when the READ to bank m is regis-

tered (Figure 24).

2. Interrupted by a WRITE (with or without auto

precharge): A WRITE to bank m will interrupt a READ

on bank n when registered. DQM should be used

two clocks prior to the WRITE command to prevent

bus contention. The PRECHARGE to bank n will

begin when the WRITE to bank m is registered (Fig-

ure 25).

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND READ - AP

BANK nNOP NOPNOPNOP

OUT

a + 1

OUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CAS Latency = 3 (BANK n)

Figure 24

READ With Auto Precharge Interrupted by a READ

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

NOPNOPNOPNOP

d + 1

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with D

-d at T4.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON’T CARE

Figure 25

READ With Auto Precharge Interrupted by a WRITE

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

tRP - BANK m

OUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

Figure 26

WRITE With Auto Precharge Interrupted by a READ

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

d + 1

a + 1

a + 2

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK n

tWR - BANK m

Figure 27

WRITE With Auto Precharge Interrupted by a WRITE

WRITE WITH AUTO PRECHARGE

3. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a WRITE

on bank n when registered, with the data-out ap-

pearing CAS latency later. The PRECHARGE to bank

n will begin after tWR is met, where tWR begins when

the READ to bank m is registered. The last valid

WRITE to bank n will be data-in registered one clock

prior to the READ to bank m (Figure 26).

4. Interrupted by a WRITE (with or without auto

precharge): A WRITE to bank m will interrupt a

WRITE on bank n when registered. The PRECHARGE

to bank n will begin after tWR is met, where tWR

begins when the WRITE to bank m is registered. The

last valid data WRITE to bank n will be data regis-

tered one clock prior to a WRITE to bank m (Figure

27).

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

TRUTH TABLE 2 – CKE

(Notes: 1-4)

CKEn-1 CKEnCURRENT STATE COMMANDnACTIONnNOTES

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock Suspend

L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6

Clock Suspend X Exit Clock Suspend 7

H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend Entry

H H See Truth Table 3

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock

edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met.

COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR

period. A minimum of two NOP commands must be provided during tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next

command at clock edge n + 1.

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64Mb: x32

SDRAM

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

L L H H ACTIVE (Select and activate row)

Idle L L L H AUTO REFRESH 7

LLLLLOAD MODE REGISTER 7

L L H L PRECHARGE 11

L H L H READ (Select column and start READ burst) 10

Row Active L H L L WRITE (Select column and start WRITE burst) 10

L L H L PRECHARGE (Deactivate row in bank or banks) 8

Read L H L H READ (Select column and start new READ burst) 10

(Auto L H L L WRITE (Select column and start WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

Write L H L H READ (Select column and start READ burst) 10

(Auto L H L L WRITE (Select column and start new WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the

commands shown are those allowed to be issued to that bank when in that state. Exceptions are

covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND

INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock

edge occurring during these states. Allowable commands to the other bank are determined by its

current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met.

Once tRP is met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once

tRCD is met, the bank will be in the row active state.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and

ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

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64Mb: x32

SDRAM

NOTE (continued):

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and

ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP

commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.

Once tRC is met, the SDRAM will be in the all banks idle state.

Accessing Mode

tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle

state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.

Once tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for

precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto

precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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64Mb: x32

SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

Idle XXXXAny Command Otherwise Allowed to Bank m

Row L L H H ACTIVE (Select and activate row)

Activating, L H L H READ (Select column and start READ burst) 7

Active, or L H L L WRITE (Select column and start WRITE burst) 7

Precharging L L H L PRECHARGE

Read L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start new READ burst) 7, 10

Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11

Disabled) L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start READ burst) 7, 12

Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13

Disabled) L L H L PRECHARGE 9

Read L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14

Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15

L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start READ burst) 7, 8, 16

Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17

L L H L PRECHARGE 9

NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n

and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a

state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and

ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

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64Mb: x32

SDRAM

NOTE (continued):

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all

banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented

by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has

been interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the

READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the

WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should

be used one clock prior to the WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the

READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out

appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior

to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the

WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE

to bank n will be data-in registered one clock prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to

bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin

when the READ to bank m is registered (Figure 24).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the

WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two

clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will

begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ

to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS

latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the

READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior

to the READ to bank m (Figure 26).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE

to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to

bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD, VDDQ Supply

Relative to VSS .............................................. -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to VSS .............................................. -1V to +4.6V

Operating Temperature, TA............................ 0°C to +70°C

Extended Temperature .......................... -40°C to +85°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ........................................................ 1W

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 6, 27; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VDD, VDDQ 3 3.6 V 27

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD + 0.3 V 22

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22

INPUT LEAKAGE CURRENT:

Any input 0V ≤ VIN ≤ VDD II-5 5 µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQIOZ -5 5 µA

OUTPUT LEVELS: VOH 2.4 – V

Output High Voltage (IOUT = -4mA)

Output Low Voltage (IOUT = 4mA) VOL –0.4V

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1, 6, 11, 13, 27; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -5 -55 UNITS NOTES

OPERATING CURRENT: Active Mode; IDD1200 190 mA 3, 18,

Burst = 2; READ or WRITE; t

RC = tRC (MIN); 19, 26

CAS latency = 3

STANDBY CURRENT: Power-Down Mode; IDD222mA

CKE = LOW; All banks idle

STANDBY CURRENT: Active Mode; CS# = HIGH; IDD380 70 mA 3, 12,

CKE = HIGH; All banks active after tRCD met;

19, 26

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst; IDD4280 260 mA 3, 18,

READ or WRITE; All banks active, 19, 26

CAS latency = 3

AUTO REFRESH CURRENT: tRFC = tRFC (MIN) IDD5225 225 mA 3, 12,

CAS latency = 3; CKE, CS# = HIGH 18, 19,

26, 29

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD622mA4

MAX

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1, 6, 11, 13, 27; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -6 -7 UNITS NOTES

OPERATING CURRENT: Active Mode; IDD1150 130 mA 3, 18,

Burst = 2; READ or WRITE; t

RC = tRC (MIN); 19, 26

CAS latency = 3

STANDBY CURRENT: Power-Down Mode; IDD222mA

CKE = LOW; All banks idle

STANDBY CURRENT: Active Mode; CS# = HIGH; IDD360 50 mA 3, 12,

CKE = HIGH; All banks active after tRCD met; 19, 26

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst; IDD4180 160 mA 3, 18,

READ or WRITE; All banks active, 19, 26

CAS latency = 3

AUTO REFRESH CURRENT: tRFC = tRFC (MIN) IDD5225 225 mA 3, 12,

CAS latency = 3; CKE, CS# = HIGH 18, 19,

26, 29

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD622mA4

MAX

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11; notes appear on page 35)

AC CHARACTERISTICS -5 -55

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from CLK CL = 3 tAC (3) 4.5 5 ns

(pos. edge) CL = 2 tAC (2) - - ns

CL = 1 tAC (1) - - ns

Address hold time tAH 1 1 ns

Address setup time tAS 1.5 1.5 ns

CLK high-level width tCH 2 2 ns

CLK low-level width tCL 2 2 ns

Clock cycle time CL = 3 tCK (3) 5 5.5 ns 23

CL = 2 tCK (2) - - ns 23

CL = 1 tCK (1) - - ns 23

CKE hold time tCKH 1 1 ns

CKE setup time tCKS 1.5 1.5 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns

Data-in hold time tDH 1 1 ns

Data-in setup time tDS 1.5 1.5 ns

Data-out high-impedance time CL = 3 tHZ (3) 4.5 5 ns 10

CL = 2 tHZ (2) - - ns 10

CL = 1 tHZ (1) - - ns 10

Data-out low-impedance time tLZ 1 1 ns

Data-out hold time tOH 1.5 2 ns

ACTIVE to PRECHARGE command tRAS 38.7 120k 38.7 120k ns

ACTIVE to ACTIVE command period tRC 55 55 ns

AUTO REFRESH period tRFC 60 60 ns

ACTIVE to READ or WRITE delay tRCD 15 16.5 ns

Refresh period (4,096 rows) tREF 64 64 ms

PRECHARGE command period tRP 15 16.5 ns

ACTIVE bank a to ACTIVE bank b command tRRD 10 11 ns 25

Transition time tT 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 2 2 tCK 24

Exit SELF REFRESH to ACTIVE command tXSR 55 55 ns 20

CAPACITANCE

(Note: 2; notes appear on page 35)

PARAMETER SYMBOL MIN MAX UNITS

Input Capacitance: CLK CI12.5 4.0 p F

Input Capacitance: All other input-only pins CI22.5 4.0 pF

Input/Output Capacitance: DQs CIO 4.0 6.5 pF

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11; notes appear on page 35)

AC CHARACTERISTICS -6 -7

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from CLK CL = 3 tAC (3) 5.5 5.5 ns

(pos. edge) CL = 2 tAC (2) 7.5 8 ns

CL = 1 tAC (1) 17 17 ns

Address hold time tAH 1 1 ns

Address setup time tAS 1.5 2 ns

CLK high-level width tCH 2.5 2.75 ns

CLK low-level width tCL 2.5 2.75 ns

Clock cycle time CL = 3 tCK (3) 6 7 ns 23

CL = 2 tCK (2) 10 10 ns 23

CL = 1 tCK (1) 20 20 ns 23

CKE hold time tCKH 1 1 ns

CKE setup time tCKS 1.5 2 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 2 ns

Data-in hold time tDH 1 1 ns

Data-in setup time tDS 1.5 2 ns

Data-out high-impedance time CL = 3 tHZ (3) 5.5 5.5 ns 10

CL = 2 tHZ (2) 7.5 8 ns 10

CL = 1 tHZ (1) 17 17 ns 10

Data-out low-impedance time tLZ 1 1 ns

Data-out hold time tOH 2 2.5 ns

ACTIVE to PRECHARGE command tRAS 42 120k 42 120k ns

ACTIVE to ACTIVE command period tRC 60 70 ns

AUTO REFRESH period tRFC 60 70 ns

ACTIVE to READ or WRITE delay tRCD 18 20 ns

Refresh period (4,096 rows) tREF 64 64 ms

PRECHARGE command period tRP 18 20 ns

ACTIVE bank a to ACTIVE bank b command tRRD 12 14 ns 25

Transition time tT 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1CLK+ 1CLK+ tCK 24

6ns 7ns

12ns 14ns ns 28

Exit SELF REFRESH to ACTIVE command tXSR 70 70 ns 20

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35)

PARAMETER SYMBOL -5 -55 -6 -7 UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 1111

tCK 17

CKE to clock disable or power-down entry mode tCKED 1111

tCK 14

CKE to clock enable or power-down exit setup mode tPED 1111

tCK 14

DQM to input data delay tDQD 0000

tCK 17

DQM to data mask during WRITEs tDQM 0000

tCK 17

DQM to data high-impedance during READs tDQZ 2222

tCK 17

WRITE command to input data delay tDWD 0000

tCK 17

Data-in to ACTIVE command CL = 3 tDAL (3) 5555

tCK 15, 21

CL = 2 tDAL (2) - - 4 4 tCK 15, 21

CL = 1 tDAL (1) - - 3 3 tCK 15, 21

Data-in to PRECHARGE command tDPL 2222

tCK 16, 21

Last data-in to burst STOP command tBDL 1111

tCK 17

Last data-in to new READ/WRITE command tCDL 1111

tCK 17

Last data-in to PRECHARGE command tRDL 2222

tCK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2222

tCK 26

Data-out to high-impedance from PRECHARGE command CL = 3 tROH (3) 3333

tCK 17

CL = 2 tROH (2) - - 2 2 tCK 17

CL = 1 tROH (1) - - – 1 tCK 17

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

13. IDD specifications are tested after the device is prop-

erly initialized.

14. Timing actually specified by tCKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s)

specified as a reference only at minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-

eter.

18. The IDD current will decrease as the CAS latency is

reduced. This is due to the fact that the maximum

cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times dur-

ing this period.

21. Based on tCK = 143 MHz for -7, 166 MHz for -6,

183 MHz for -55, and 200 MHz for -5.

22. VIH overshoot: VIH(MAX) = VDDQ + 1.2V for a pulse

width ≤ 3ns, and the pulse width cannot be greater

than one third of the cycle rate. VIL undershoot:

VIL(MIN) = -1.2V for a pulse width ≤ 3ns, and the

pulse width cannot be greater than one third of the

cycle rate.

23. The clock frequency must remain constant during

access or precharge states (READ, WRITE, includ-

ing tWR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. tCK = 7ns for -7, 6ns for -6, 5.5ns for -5.5, and

5ns for -5.

27. VDD(MIN) = 3.135V for -6, -55, and -5 speed grades.

28. Check factory for availability of specially screened

devices having tWR = 10ns. tWR = 1 tCK for 100 MHz

and slower (tCK = 10ns and higher) in manual

precharge.

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V;

f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.

AC can range from 0pF to 6pF.

3. IDD is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle

time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indi-

cate cycle time at which proper operation over the

full temperature range (0°C ≤ T

A ≤ +70°C and

-40°C ≤ TA ≤ +85°C for IT parts) is ensured.

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,

before proper device operation is ensured. (VDD

and VDDQ must be powered up simultaneously. VSS

and VSSQ must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the tREF refresh requirement is

exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between VIH

and VIL (or between VIL and VIH) in a monotonic

manner.

9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves

the open circuit condition; it is not a reference to

VOH or VOL. The last valid data element will meet

tOH before going High-Z.

11. AC timing and IDD tests have VIL = .25 and VIH = 2.75,

with timing referenced to 1.5V crossover point.

12. Other input signals are allowed to transition no

more than once in any two-clock period and are

otherwise at valid VIH or VIL levels.

Q30p

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

INITIALIZE AND LOAD MODE REGISTER

*CAS latency indicated in parentheses.

NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.

2. Outputs are guaranteed High-Z after command is issued.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tMRD222

tCK

tRFC 60 60 70 n s

tRP 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCLK (3) 5 6 7 ns

tCLK (2) 10 10 ns

tCLK (1) 20 20 ns

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1 BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register

1, 2, 5

tCMH

tCMS

Precharge

all banks

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tRP

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tCKS

Power-up:

and

CK stable

T = 100µs

(MIN)

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

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ALL

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High-Z

tCKH

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DQM 0-3

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NOP

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tCMH

tCMS tCMH

tCMS

A0-A9 ROW

tAH

tAS

CODE

tAH

tAS

CODE

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A10 ROW

tAH

tAS

CODE

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ALL BANKS

SINGLE BANK

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DON’T CARE

UNDEFINED

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

POWER-DOWN MODE 1

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCK (1) 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

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tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

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All banks idle

BA0, BA1

BANK

BANK(S)

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High-Z

tAH

tAS

tCKH

tCKS

DQM 0-3

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A0-A9

ROW

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ALL BANKS

SINGLE BANK

A10

ROW

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T0 T1 T2 Tn + 1 Tn + 2

DON’T CARE

UNDEFINED

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

CLOCK SUSPEND MODE 1

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tHZ (3) 4.5 5.5 5.5 ns

tHZ (2) – 7.5 8 ns

tHZ (1) – 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) 7.5 8 ns

tAC (1) 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) – 10 10 ns

tCK (1) – 20 20 ns

tCKH 1 1 1 ns

tCH

tCL

tCK

tAC

tLZ

DQM0-3

CLK

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

OUT

tAC

tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

OUT

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

BA0, BA1

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

AUTO REFRESH MODE

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tRFC 60 60 70 n s

tRP 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

UNDEFINEDDON’T CARE

tCH

tCL

tCK

CKE

CLK

tRFC

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tRP

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COMMAND

tCMH

tCMS

NOPNOP

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BANK

ACTIVE

AUTO

REFRESH

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NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC

High-Z

BANK(S)

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tAH

tAS

tCKH

tCKS

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NOP

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ROW

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ALL BANKS

SINGLE BANK

A10

ROW

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T0 T1 T2 Tn + 1 To + 1

BA0, BA1

A0–A9

DQM 0–3

DON’T CARE

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

SELF REFRESH MODE

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRP 15 18 20 ns

tXSR 55 70 70 n s

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCH

tCL

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

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DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP

BANK(S)

High-Z

tCKS

AUTO

REFRESH

> tRAS

tCKH

tCKS

ALL BANKS

SINGLE BANK

A10

T0 T1 T2 Tn + 1 To + 1 To + 2

BA0, BA1

DQM 0-3

A0-A9

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64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

SINGLE READ1

*CAS latency indicated in parentheses.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9

BA0, BA1

A10

tOH

DOUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

COMMAND

tCMH

tCMS

PRECHARGEACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

tCKH

tCKS

COLUMN

T0 T1 T2 T4T3 T5

DON’T CARE

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8, A9 = “Don’t Care.”

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tHZ (3) 4.5 5.5 5.5 ns

tHZ (2) - 7.5 8 ns

tHZ (1) - 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 ns

tRC D 15 18 20 ns

tRP 15 18 20 ns

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

READ – WITHOUT AUTO PRECHARGE 1

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCMH111ns

tCMS 1.5 1.5 2 ns

tHZ (3) 4.5 5.5 5.5 ns

tHZ (2) - 7.5 8 ns

tHZ (1) - 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 ns

tRC D 15 18 20 ns

tRP 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

CKE

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

DON’T CARE

UNDEFINED

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

READ – WITH AUTO PRECHARGE 1

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

CKE

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tHZ

tOH

OUT

+ 3

tAC

tOH

tAC

tOH

tAC

OUT

+ 2D

OUT

+ 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCMH111ns

tCMS 1.5 1.5 2 ns

tHZ (3) 4.5 5.5 5.5 ns

tHZ (2) - 7.5 8 ns

tHZ (1) - 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 ns

tRC D 15 18 20 ns

tRP 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

ALTERNATING BANK READ ACCESSES 1

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 ns

tRC D 15 18 20 ns

tRP 15 18 20 ns

tRR D 10 12 14 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

tCKH 1.5 1 1 ns

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

CLK

A10

tOH

DOUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

DOUT b

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 4 BANK 4 BANK 0

CKE

tCKH

tCKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 4 CAS Latency - BANK 4

RC - BANK 0

RRD

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

READ – FULL-PAGE BURST 1

NOTE: 1. For this example, the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

3. Page left open; no tRP.

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tHZ (3) 4.5 5 5.5 ns

tHZ (2) - 7.5 8 ns

tHZ (1) - 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRC D 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.5 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

CKE

CLK

A10

tOH

Dout m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC

tOH

OUT

m+1

ROW

tHZ

tOH

OUT

m+1

tAC

tOH

OUT

m+2

tAC

tOH

OUT

m-1

tAC

tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

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Full page completed

256 locations within same row

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

(

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)

(

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)

NOP

(

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)

(

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)

tAH

tAS

BANK

(

)(

)

(

)(

)

BANK

tCKH

tCKS

(

)(

)

(

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)

(

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)

(

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)

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

READ – DQM OPERATION 1

tCH

tCL

tCK

tRCD CAS Latency

CKE

CLK

A10

tCMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

DOUT m

tOH

DOUT m + 3DOUT m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAC

tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

NOTE: 1. For this example, the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tHZ (3) 4.5 5 5.5 ns

tHZ (2) - 7.5 8 ns

tHZ (1) - 17 17 ns

tLZ111ns

tOH 1.5 2 2.5 ns

tRC D 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAC (3) 4.6 5.5 5.5 ns

tAC (2) - 7.5 8 ns

tAC (1) - 17 17 ns

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) - 10 10 ns

tCK (1) - 20 20 ns

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

SINGLE WRITE

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 n s

tRC D 15 18 20 ns

tRP 15 18 20 ns

tWR 2 tCK 12 14 n s

*CAS latency indicated in parentheses.

DON’T CARE

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

CMH

CMS

ACTIVE NOP WRITE NOP PRECHARGE ACTIVE

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6

NOP

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 10ns is required between <DIN m> and the PRECHARGE command, regardless of frequency, to meet tWR.

3. A8, A9 = “Don’t Care.”

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

WRITE – WITHOUT AUTO PRECHARGE 1

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

4. tWR of 1 CLK available if running 100 MHz or slower. Check factory for availability.

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCMH111ns

tCMS 1.5 1.5 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 n s

tRC D 15 18 20 ns

tRP 15 18 20 ns

tWR42 tC K 12 14 n s

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 2 2 ns

DISABLE AUTO PRECHARGE

ALL BANKs

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

DON’T CARE

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE NOPPRECHARGE ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DQM 0-3

BA0, BA1

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

tCMS 1.5 1.5 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tRAS 38.7 120,000 42 120,000 42 120,000 ns

tRC 55 60 70 n s

tR C D 15 18 20 n s

tRP 15 18 20 ns

tWR 2 tCK 1 CLK+ 1 CLK+ ns

WRITE – WITH AUTO PRECHARGE 1

NOTE: 1. For this example, the burst length = 4.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 2 2 ns

tCMH 1 1 1 ns

DON’T CARE

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

COMMAND

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

ALTERNATING BANK WRITE ACCESSES 1

tCH

tCL

tCK

CLK

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

CMH

CMS

NOP NOPACTIVE NOP WRITE NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

DQM /

DQML, DQMH

A0-A9

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1 BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b

COLUMN m

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

RC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

NOTE: 1. For this example, the burst length = 4.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tDH111ns

tDS 1.5 1.5 2 ns

tRAS 38.7 42 120,000 42 120,000 ns

tRC 55 60 70 n s

tRC D 15 18 20 ns

tRP 15 18 20 ns

tRR D 10 12 14 ns

tWR 2 tCK 1 CLK+ 1 CLK+ ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCKH 1 1 1 ns

tCKS 1.5 2 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

WRITE – FULL-PAGE BURST

NOTE: 1. A8 and A9 = “Don’t Care.”

2. tWR must be satisfied prior to PRECHARGE command.

3. Page left open; no tRP.

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 1.5 2 ns

tCMH111ns

tCMS 1.5 2 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tRC D 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

tCH

tCL tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate. Can

use BURST TERMINATE

command to stop.

2, 3

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Full page completed

DON’T CARE

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

(

)(

)

(

)(

)

(

)(

)

(

)(

)

DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

tDH

tDS tDH

tDS

DIN m - 1

tDH

tDS

tAH

tAS

BANK

(

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)

(

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)

BANK

tCMH

tCKH

tCKS

(

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(

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(

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(

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(

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(

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256 locations within same row

COLUMN m

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

WRITE – DQM OPERATION 1

NOTE: 1. For this example, the burst length = 4.

2. A8 and A9 = “Don’t Care.”

*CAS latency indicated in parentheses.

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tCKH 1 1 1 ns

tCKS 1.5 2 2 ns

tCMH111ns

tCMS 1.5 1.5 2 ns

tDH111ns

tDS 1.5 1.5 2 ns

tRC D 15 18 20 ns

TIMING PARAMETERS

-5 -6 -7

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

tAH111ns

tAS 1.5 1.5 2 ns

tCH 2 2.5 2.75 ns

tCL 2 2.5 2.75 ns

tCK (3) 5 6 7 ns

tCK (2) 10 10 ns

tCK (1) 20 20 ns

DON’T CARE

tCH

tCL

tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND

NOPNOP NOPACTIVE NOP WRITE NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

BA0, BA1

DQM 0-3

A0-A9

64Mb: x32 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32

SDRAM

86-PIN PLASTIC TSOP (400 MIL)

SEE DETAIL A

R 1.00

(2X)

R .75 (2X)

.50

TYP

.61

10.16 ±.08

.50 ±.10

11.76 ±.10

PIN #1 ID

DETAIL A

22.22 ±.08

0.20 +.07

-.03

.15 +.03

-.02

.10 +.10

-.05

1.20 MAX

.10

.25

GUAGE

PLANE

.80

TYP

.10 (2X)

2.80 (2X)

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.025mm

per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.