ISO113B - Texas Instruments High-Performance Analog

ISO113

Low-Cost, High-Voltage, Internally Powered

OUTPUT ISOLATION AMPLIFIER

FEATURES

●SELF-CONTAINED ISOLATED SIGNAL

AND OUTPUT POWER

●SMALL PACKAGE SIZE: Double-Wide

(0.6") Sidebraze DIP

●CONTINUOUS AC BARRIER RATING:

1500Vrms

●WIDE BANDWIDTH: 20kHz Small Signal,

20kHz Full Power

●BUILT-IN ISOLATED OUTPUT POWER:

±10V to ±18V Input, ±50mA Output

●MULTICHANNEL SYNCHRONIZATION

CAPABILITY

●BOARD AREA ONLY 0.72in.2 (4.6cm2)

APPLICATIONS

●4mA TO 20mA V/I CONVERTERS

●MOTOR AND VALVE CONTROLLERS

●ISOLATED RECORDER OUTPUTS

●MEDICAL INSTRUMENTATION OUTPUTS

●GAS ANALYZERS

DESCRIPTION

The ISO113 output isolation amplifier provides both

signal and output power across an isolation barrier in

a small double-wide DIP package. The ceramic non-

hermetic hybrid package with side-brazed pins con-

tains a transformer-coupled DC/ DC converter and a

capacitor-coupled signal channel.

Extra power is available on the isolated output side for

driving external loads. The converter is protected from

shorts to ground with an internal current limit, and the

soft-start feature limits the initial currents from the

power source. Multiple-channel synchronization can

be accomplished by applying a TTL clock signal to

paralleled Sync pins. The Enable control is used to

turn off transformer drive while keeping the signal

channel modulator active. This feature provides a

convenient way to reduce quiescent current for low

power applications.

The wide barrier pin spacing and internal insulation

allow for the generous 1500Vrms continuous rating.

Reliability is assured by 100% barrier breakdown

testing that conforms to UL1244 test methods. Low

barrier capacitance minimizes AC leakage currents.

These specifications and built-in features make the

ISO113 easy to use, and provides for compact PC

board layout.

Duty Cycle Modulator Duty Cycle Demodulator

Rectifiers, Filters

Oscillators, Driver

OUT

–V

CC2

Sync*

Enable

CC1

Ps Gnd

CC2

–V

CC1

Gnd 1

Com 1

Sense

–V

Sync

*Ground if not used

Gnd 2

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Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

ISO113

SBOS159

ISO113 2

SPECIFICATIONS

ELECTRICAL

At TA = +25°C and VCC1 = ±15V, ±15mA output, current unless otherwise noted.

ISO113 ISO113B

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ISOLATION

Rated Continuous Voltage

AC, 60Hz TMIN to TMAX 1500 ✻Vrms

DC TMIN to TMAX 2121 ✻VDC

Test Breakdown, 100% AC, 60Hz 10s 5657 ✻Vpk

Isolation-Mode Rejection 1500Vrms, 60Hz 130 ✻dB

2121VDC 160 ✻dB

Barrier Impedance 1012 || 9 ✻Ω || pF

Leakage Current 240Vrms, 60Hz 1 2 ✻✻µA

GAIN

Nominal 1✻V/V

Initial Error ±0.3 ±0.5 ✻✻%FSR

Gain vs Temperature ±60 ±100 ±20 ±50 ppm/°C

Nonlinearity VO = –10V to 10V ±0.05 ±0.1 ±0.03 ±0.05 %FSR

VO = –5V to 5V ±0.02 ±0.04 ±0.012 ±0.02 %FSR

INPUT OFFSET VOLTAGE

Initial Offset ±20 ±60 ✻✻mV

vs Temperature ±300 ±500 ±100 ±250 µV/°C

vs Power Supplies VCC2 = ±10 to ±18V 0.9 ✻mV/V

vs Output Supply Load IO = 0 to ±50mA ±0.3 ✻mV/mA

SIGNAL INPUT

Voltage Range Output Voltage in Range ±10 ±15 ✻✻ V

Resistance 200 ✻kΩ

SIGNAL OUTPUT

Voltage Range ±10 ±12.5 ✻✻ V

Current Drive ±5 ±15 ✻✻ mA

Ripple Voltage, 800kHz Carrier 25 ✻mVp-p

400Ω/4.7nF (See Figure 4) 5 ✻mVp-p

Capacitive Load Drive 1000 ✻pF

Voltage Noise 4✻µV/√Hz

FREQUENCY RESPONSE

Small Signal Bandwidth 20 ✻kHz

Slew Rate 1.5 ✻V/µs

Settling Time 0.1%, –10/10V 75 ✻µs

POWER SUPPLIES

Rated Voltage, VCC1 ±15 ✻V

Voltage Range ±10 ±18 ✻✻V

Input Current IO = ±15mA +90/–4.5 ✻mA

IO = 0mA +60/–4.5 ✻mA

Ripple Current No Filter 60 ✻mAp-p

CIN = 1µF3 ✻mAp-p

Rated Output Voltage Load = 15mA ±14.25 ±15 ±15.75 ✻✻✻ V

Output 50mA Balanced Load 10 ✻V

100mA Single-Ended Load 10 ✻V

Load Regulation Balanced Load 0.3 ✻%/mA

Line Regulation 1.12 ✻V/V

Output Voltage vs Temperature 2.5 ✻mV/°C

Voltage Balance, ±VCC2 0.05 ✻%

Voltage Ripple (800kHz) No External Capacitors 50 ✻mVp-p

CEXT = 1µF5 ✻mVp-p

Output Capacitive Load 1✻µF

Sync Frequency Sync-Pin Grounded(2) 1.6 ✻MHz

TEMPERATURE RANGE

Specification –25 +85 ✻✻°C

Operating –25 +85 ✻✻°C

Storage –25 +125 ✻✻°C

✻ Specifications same as ISO113.

NOTE: (1) Conforms to UL1244 test methods. 100% tested at 1500Vrms for 1 minute. (2) If using external synchronization with a TTL-level clock, frequency should

be between 1.2MHz and 2MHz with a duty-cycle greater than 25%.

ISO113

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Without Damage .................................................................... ±18V

VIN, Sense Voltage............................................................................. ±50V

Com1 to Gnd1................................................................................................................±200mV

Enable, Sync......................................................................... Gnd to +VCC1

Continuous Isolation Voltage ..................................................... 1500Vrms

VISO, dv/dt ..................................................................................... 20kV/µs

Junction Temperature .................................................................... +150°C

Storage Temperature...................................................... –25°C to +125°C

Lead Temperature,10s .................................................................. +300°C

Output Short to Gnd Duration .................................................. Continuous

±VCC2 to Gnd 2 Duration .......................................................... Continuous

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

Gnd 1

Com 1

–V

Enable 1

CC2

Sync

–V

Gnd 2

Sense

Ps Gnd

OUT

CC1

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA

ISO113 24-Pin DIP 231 –25°C to +85°C

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ISO113/2K5” will get a single 2500-

piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

ISO113 4

TYPICAL PERFORMANCE CURVES

At TA = +25°C,VCC1 = ±15VDC, ±15mA output, current unless otherwise noted.

RECOMMENDED RANGE OF ISOLATION VOLTAGE

100 1k 10k 100k 1M 10M

10k

2.1k

100

Maximum Isolation Voltage (Vpk)

Barrier Voltage Rating

Non-Specified

Signal

Operation

2100V

at 75kHz

Operational

Region

Isolation Voltage Frequency (Hz)

IMR/LEAKAGE vs FREQUENCY

140

130

120

110

100

10 100 1k 10k 100k

10mA

1mA

100µA

10µA

1µA

100nA

Leakage at

1500Vrms

Leakage at

240Vrms

IMR

Isolation Voltage Frequency (Hz)

Isolation-Mode Rejection (dB)

Barrier Leakage Current (rms)

DISTORTION vs FREQUENCY

Frequency (Hz)

10 100 10k

0.1

0.01

THD + N (%)

V = 2Vp-p

V = 20Vp-p

GAIN/PHASE vs FREQUENCY

1k100 10k 100k

Small Signal Frequency (Hz)

–3

–9

–12

–15

–6

Gain (dB)

135

180

Phase Shift (°)

Gain

Phase

–10

–20

Output Voltage (V)

Time (µs)

0 50 100

LARGE SIGNAL TRANSIENT RESPONSE ISOLATED POWER SUPPLY

LOAD REGULATION AND EFFICIENCY

±V Supply Output Current (mA)

CC1

20 20

40 30

60 40

±V Output Voltage (V)

CC1

Output Voltage

Single-Ended Loads

Efficiency (%)

Output Voltage

Balanced Loads

Balanced Load Efficiency

ISO113

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C,VCC1 = ±15VDC, ±15mA output current, unless otherwise noted.

ISOLATED POWER SUPPLY LINE REGULATION

9 10111213141516171819

+V (V)

CC1

±V (V)

CC2

±15mA Load

1.12V/V

ISOLATION POWER SUPPLY VOLTAGE

vs TEMPERATURE

–25 0 25 50 75 100

Temperature (°C)

–1

–2

V (%)∆

CC2

ISOLATED SUPPLY VOLTAGE AND V

vs SYNC FREQUENCY

1 1.5 2 2.5

2.5

–2.5

–5

250

125

–125

–250

∆V (mA)

CC2

Sync Frequency (MHz)

CC2

ISO113 6

FIGURE 1. Signal and Power Connections.

THEORY OF OPERATION

The block diagram on the front page shows the isolation

amplifier’s synchronized signal and power configuration,

which eliminate beat frequency interference. A proprietary

800kHz oscillator chip, power MOSFET transformer driv-

ers, patented square core wirebonded transformer, and single

chip diode bridge provide power to the output side of the

isolation amplifier as well as external loads. The signal

channel capacitively couples a duty-cycle encoded signal

across the ceramic high-voltage barrier built into the pack-

age. A proprietary transmitter-receiver pair of integrated

circuits, laser trimmed at wafer level, and coupled through a

pair of matched “fringe” capacitors, results in a simple,

reliable design.

SIGNAL AND POWER CONNECTIONS

Figure 1 shows the proper power supply and signal connec-

tions. All power supply pins should be bypassed as shown

with the π filter for +VCC1, an option recommended if more

than ±15mA are drawn from the isolated supply. Separate

rectifier output pins (±VCC2) and amplifier supply input pins

(±VC) allow additional ripple filtering and/or regulation. The

separate input common pin and output sense are low current

inputs tied to the signal source ground, and output load,

respectively, to minimize errors due to IR drop in long

conductors. Otherwise, connect Com 1 to Gnd 1, and Sense

to VOUT at the ISO113 socket. The enable pin may be left

open if the ISO113 is continuously operated. If not, a TTL

low level will disable the internal DC/ DC converter. The

Sync input must be grounded for unsynchronized operation

while a 1.2MHz to 2MHz TTL clock signal provides syn-

chronization of multiple units.

The ISO113 isolation amplifier contains a transformer-

coupled DC/DC converter that is powered from the input

side of the isolation amplifier. All power supply pins (2, 4,

13, 14, 15, and 16) of the ISO113 have an internal 0.1µF

capacitor to ground. L1 is used to slow down fast changes in

the input current to the DC/DC converter. C1 is used to help

regulate the voltage ripple caused by the current demands of

the converter. L1, C1, and C2 are optional, however, recom-

mended for low noise applications.

The DC/DC converter creates an unregulated ±15V output

to ±VCC2. If the ISO113 is the only device using the DC/DC

converter for power, pins 13 and 14 and pins 15 and 16 can

be connected directly without CO or LO in the circuit. If an

external capacitor is used in this configuration, it should not

exceed 1µF. This configuration is possible because the

isolation amplifier and the DC/DC converter are synchro-

nized internally.

If additional devices are powered by the DC/DC converter

of the ISO113, the application may require that the ripple

voltage of the ISO113 converter be attenuated, in which

case, LO and CO should be added to the circuit. The inductor

is used to attenuate the ripple current and a higher value

capacitor can be used to reduce the ripple voltage even

further.

OPTIONAL GAIN AND OFFSET ADJUSTMENTS

Rated gain accuracy and offset performance can be achieved

with no external adjustments, but the circuit of Figure 2a may

be used to provide a gain trim of ±0.5% for the values shown.

Greater range may be provided by increasing the size of R1 and

R2. Every 2kΩ increase in R1 will give an additional 1%

CC1

–V

CC1

Isolation Barrier

16 15 14 13

–V

CC2

Com 1Gnd 1

SyncEnable +V

CC1

–V

CC1

(1) (2)

ISO 113

Gnd

Sense

OUT

Gnd 2

91112

1234

1µF

10µF

Tantalum

23 22 21

(3)

NOTES: (1) Enable = pin open or TTL high. (2) Ground sync if not used.

(3) π filter reduces ripple current; L

= 10µH, <10Ω.

* Optional Filtering

For L

0 ≤ L

< 10µH

< 1µF

For L

≥ 10µH, <10Ω

≤ 10µF

Supply

Outputs

–

ISO113

FIGURE 2b. Gain Setting.

FIGURE 2a. Gain Adjust.

V21

1kΩ

11 10

2kΩV

OUT

V21

11 10

Sense

OUT

Gain = 1 + (R

+ R

/200k)

adjustment range, with R2 ≥ 2R1. If safety or convenience

dictate location of the adjustment potentiometer on the other

side of the barrier from the position shown in Figure 2a, the

position of R1 and R2 may be reversed.

Gains greater than 1 may be obtained by using the circuit of

Figure 2b. Note that the effect of input referred errors will be

multiplied at the output in proportion to the increase in gain.

Also, the small-signal bandwidth will be decreased in in-

verse proportion to the increase in gain. In most instances, a

precision gain block at the input of the isolation amplifier

will provide better overall performance.

Figure 3 shows a method for trimming VOS of the ISO113.

This circuit may be applied to Signal Com1. With the values

shown, ±15V supplies and unity gain, the circuit will pro-

vide ±150mV adjustment range and 0.25mV resolution with

a typical trim potentiometer. The output will have some

sensitivity to power supply variations. For a ±100mV trim,

power supply sensitivity is 8mV/V at the output.

11 10

Sense

VOUT

400Ω

4.7nF

V21

FIGURE 4. Ripple Reduction.

MULTICHANNEL SYNCHRONIZATION

Synchronization of multiple ISO113s can be accomplished

by connecting pin 3 of each device to an external TTL level

oscillator, as shown in Figure 7. The PWS750-1 oscillator is

convenient because its nominal synchronizing output fre-

quency is 1.6MHz, resulting in a 800kHz carrier in the

ISO113 (its nominal unsynchronized value). The open col-

lector output typically switches 7.5mA to a 0.2V low level

so that the external pull up resistor can be chosen for

different pull-up voltages as shown in Figure 7. The number

of channels synchronized by one PWS750-1 is determined

by the total capacitance of the sync voltage conductors. They

must be less than 1000pF to ensure TTL level switching at

800kHz. At higher frequencies the capacitance must be

proportionally lower.

Customers can supply their own TTL level synchronization

logic, provided the frequency is between 1.2MHz and 2MHz,

and the duty cycle is greater than 25%.

Single or multichannel synchronization with reduced power

dissipation for applications requiring less than ±15mA from

VCC1 is accomplished by driving both the Sync input pin (3)

and Enable pin (1) with the TTL oscillator as shown in

Figure 5.

CC1

1MΩ

10kΩ

Signal Com 1

100kΩ

or +V

CC2

–V

CC1

or –V

CC2

FIGURE 3. VOS Adjust.

OPTIONAL OUTPUT FILTER

Figure 4 shows an optional output ripple filter that reduces

the 800kHz ripple voltage to <5mVp-p without compromis-

ing DC performance. The small signal bandwidth is ex-

tended above 30kHz as a result of this compensation.

TTL Oscillation

ISO

123

15 14 1316

113

External

Load

<15mA

+VCC1

IQ(Reduced)

ISOLATION BARRIER VOLTAGE

The typical performance of the ISO113 under conditions of

barrier voltage stress is indicated in the first two perform-

ance curves—Recommended Range of Isolation Voltage

and IMR/ Leakage vs Frequency. At low barrier modulation

FIGURE 5. Reduced Power Dissipation.

ISO113 8

levels, errors can be determined by the IMRR characteristic.

At higher barrier voltages, typical performance is obtained

as long as the dv/dt across the barrier is below the shaded

area in the first curve. Otherwise, the signal channel will be

interrupted, causing the output to distort, and/or shift DC

level. This condition is temporary, with normal operation

resuming as soon as the transient subsides. Permanent dam-

age to the integrated circuits occurs only if transients exceed

20kV/µs. Even in this extreme case, the barrier integrity is

assured.

HIGH VOLTAGE TESTING

The ISO113 was designed to reliably operate with 1500Vrms

continuous isolation barrier voltage. To confirm barrier

integrity, a two-step breakdown test is performed on 100%

of the units. First, an 5657V peak, 60Hz barrier potential is

applied for 10s to verify that the dielectric strength of the

insulation is above this level. Following this exposure, a

1500Vrms, 60Hz potential is applied for one minute to

conform to UL1244. Life-test results show reliable opera-

tion under continuous rated voltage and maximum operating

temperature conditions.

APPLICATIONS

FIGURE 7. Synchronized-Multichannel Isolation.

23 22 21

1µF

ISO

2341

10µF

+15V

–15V

15 14 1316

10 11 129

VN2222

250

0.1%

Ω

20k

6.2V

113

Ω

R≤Ω600

I = 0 20mA

0 5V

FIGURE 6. Isolated Current Loop Driver.

NOTES:

(

)

PWS750-1 can s

nc > 20 ISO113s.

(

)

pass supplies as shown in Fi

ure 1.

12 14 11

RPWS750-1

CC1

R = 7.5

CC1

–V

CC1

23 22 21

ISO

23 4

IN1

15 14 1316

10 129

113

OUT1

Additional

Channels

Ωk

Sync ≈1.6MHz

23 22 21

ISO

23 4

IN2

15 14 1316

10 129

113

OUT2

PACKAGE OPTION ADDENDUM

www.ti.com 12-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ISO113 NRND CDIP SB JVB 16 TBD Call TI Call TI

ISO113B NRND CDIP SB JVB 16 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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