A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 FEATURES AND BENEFITS * * * * * * * * * * * * * * * * * Automotive AEC-Q100 qualified 2.8 to 36 VIN operating range, 40 VIN maximum Buck or buck-boost pre-regulator (VREG) Adjustable PWM switching frequency: 250kHz to 2.4MHz PWM frequency can be synchronized to external clock Adjustable synchronous buck regulator (1.25 VNOM) 3.3V (3V3) and 5V (V5) internal LDO regulators with foldback short-circuit protections 5V (V5P) internal tracking LDO regulator with foldback short-circuit and short-to-battery protections TRACK sets either 3V3 or V5 as the reference for V5P Power-on reset (NPOR) with fixed delay of 15ms Programmable watchdog timer with activation delay Active-low watchdog timer enable pin (WDENn) Dual bandgaps for increased reliability: BGVREF, BGFAULT MODE pin sets the NPOR undervoltage threshold for V5 and V5P Fixed POK5V undervoltage threshold for V5 and V5P Logic enable input (ENB) for microprocessor control Two ignition enable inputs (ENBAT1 and ENBAT2) Continued on next page... APPLICATIONS Electronic Power Steering (EPS) Transmission Control Units (TCU) Advanced Braking Systems (ABS) Emissions Control Modules Other automotive applications PACKAGE: 38-Pin eTSSOP (suffix LV) DESCRIPTION The A4408 is power management IC that uses a buck or buck-boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage, complete with control, diagnostics, and protections. The output of the pre-regulator supplies a 5V/115mAMAX tracking/protected LDO, a 3.3V/165mAMAX LDO, a 5V/325mAMAX LDO, and an adjustable output synchronous buck regulator (1.25VTYP/700 mADC). Designed to supply CAN or microprocessor power supplies in high-temperature environments, the A4408 is ideal for underhood applications. Enable inputs to the A4408 include a logic-level (ENB) and two high-voltage (ENBAT1 and ENBAT2) inputs. The A4408 provides flexibility by including a TRACK pin to set the reference of the tracking regulator to either the 5V or the 3.3V output, so the A4408 can be adapted across multiple platforms with different sensors and supply rails. The MODE pin selects the NPOR undervoltage threshold for the V5 and V5P outputs. Diagnostic outputs from the A4408 include a power-on-reset output (NPOR). POK5V indicates the status of the 5V and 5V protected LDOs. Fault Flag 0 (FF0) and Fault Flag 1 (FF1) retain the last fault to reset the microcontroller. Dual bandgaps, one for regulation and one for fault checking, improve longterm reliability of the A4408. The A4408 contains a watchdog timer that can be programmed to accept a wide range of clock frequencies (WDADJ). The watchdog timer has a fixed activation delay to accommodate processor startup. The watchdog timer has an enable/disable pin (active low, WDENn) to facilitate initial factory programming or field reflash programming. Protection features include under- and overvoltage lockout on all four CPU supply rails. In case of a shorted output, all linear regulators feature foldback overcurrent protection. In addition, Continued on next page... Not to scale 5.35 V (VREG) Buck-Boost Pre-Regulator Dual Bandgaps 3.3 V LDO (3V3) with Foldback Protection Charge Pump 1.25 V (1V25) Synchronous Buck Regulator FF0 / FF1, UV, HIC, TSD, WD Programmable Watchdog Timer with Activation Delay 5 V LDO (V5) with Foldback Protection 3V3 POK5V Output NPOR Output V5 Tracking Control 2:1 MUX 5 V LDO (V5P) with Tracking, Foldback, and Short to VBAT Protection REF Figure 1: A4408 Simplified Block Diagram A4408-DS, Rev. 7 MCO-0000129 January 31, 2019 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 FEATURES AND BENEFITS (continued) DESCRIPTION (continued) * * * * the V5P output is protected from a short-to-battery event. Both switching regulators include pulse-by-pulse current limit, hiccup mode short-circuit protection, LX short-circuit protection, missing asynchronous diode protection (VREG), and thermal shutdown. FF0, FF1 Fault Flags--last microcontroller RESET indicators Slew rate control pin helps reduce EMI/EMC Frequency dithering helps reduce EMI/EMC Overvoltage and undervoltage protection for all four CPU supply rails * Pin-to-pin and pin-to-ground tolerant at every pin * Thermal shutdown protection * -40C to 150C junction temperature range The A4408 is supplied in a low profile (1.2mm maximum height) 38-lead eTSSOP package (suffix "LV") with exposed thermal pad. SELECTION GUIDE [1] Part Number Package Packing [1] Lead Frame A4408KLVTR-T 38-pin eTSSOP with thermal pad 4000 pieces per 7-inch reel 100% matte tin Contact Allegro for additional packing options. SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS [2] Characteristic VIN Symbol Notes VVIN ENBAT1, ENBAT2 VENBATx With current limiting resistor[3] IENBATx LX1, SLEW VV5P Unit V -13 to 40 V -0.3 to 8 V 75 mA -0.3 to VVIN + 0.3 V t < 250 ns -1.5 V t < 50 ns VVIN + 3 V V -0.3 to 50 V VCP, CP1, CP2 V5P Rating -0.3 to 40 Independent of VVIN All other pins -1 to 40 V -0.3 to 7 V Junction Temperature TJ -40 to 150 C Storage Temperature Range Tstg -40 to 150 C Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability [3] The higher ENBAT1 and ENBAT2 ratings (-13 V and 40 V) are measured at node "A" in the following circuit configuration: [2] Node "A" 450 ENBATx VEN + - A4408 GND THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Junction to Ambient Thermal Resistance RJA [4] Additional Test Conditions [4] Value Unit 30 C/W eTSSOP-38 (LV) Package thermal information available on the Allegro website. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Features and Benefits1 Description1 Applications1 Package1 Simplified Block Diagram1 Selection Guide2 Absolute Maximum Ratings2 Thermal Characteristics2 Functional Block Diagram / Typical Schematic 4 Pinout Diagram and Terminal List Table6 Electrical Characteristics7 Buck And Buck-Boost Pre-Regulator Specifications7 Adjustable Synchronous Buck Regulator10 Linear Regulator (LDO)12 Control Inputs13 Diagnostic Outputs15 Watchdog Timer (WDT)18 Functional Description19 Overview19 Buck-Boost Pre-Regulator (VREG)19 Adjustable Sync. Buck Regulator (1V25/ADJ)20 Low-Dropout Linear Regulators (LDOs)21 Tracking Input (TRACK)21 Watchdog Timer (WDT)21 Dual Bandgaps (BGVREG, BGFAULT)22 Adjustable Frequency and Sync. (FSET/SYNC)22 Frequency Dithering and LX1 Slew Rate Control22 Enable Inputs (ENB, ENBAT)23 Bias Supply (VCC) 23 Charge Pump (VCP, CP1, CP2)23 Table of Contents Startup and Shutdown Sequences23 Fault Reporting (NPOR, MODE, POK5V)24 Fault Flags (FF0, FF1)24 Startup and Shutdown Logic Table25 Summary of Fault Mode Operation Table26 Timing Diagrams28 Design and Component Selection37 PWM Switching Frequency (RFSET)37 Charge Pump Capacitors 37 Pre-Regulator Ouput Inductor (L1)37 Pre-Regulator Output Capacitance37 Pre-Regulator Ceramic Input Capacitance38 Pre-Regulator Asynchronous Diode (D1)38 Pre-Regulator Boost MOSFET (Q1)38 Pre-Regulator Boost Diode (D2)38 Pre-Regulator Soft-Start and Hiccup Timing (CSS1)38 Pre-Regulator Compensation (RZ1, CZ1, CP1)39 Synchronous Buck Component Selection40 Setting the Output Voltage (RFB1 and RFB2)40 Synchronous Buck Output Inductor (L2)40 Synchronous Buck Output Capacitance40 Synchronous Buck Compensation (RZ2, CZ2, CP2)41 Synchronous Buck Soft-Start and Hiccup Timing41 Linear Regulators42 Internal Bias (VCC) 42 Signal Pins (NPOR, POK5V, FF0, FF1)42 RC Snubber Calculations (RSNUBx, CSNUBx)43 PCB Layout Recommendations45 Input/Output Structures53 Package Outline Drawing54 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 0.22 F 1.0 F VREG VIN VIN 2 x4.7 F 50 V 1210 100 F 50 V / 250 m KEY_SW BG1_UV 0.1 F 0603 EN VCC CVCC 1 F CP1 100 pF VCC COMP1 RZ1 22.1 k CSS1 22 nF OSC2 BUCK-BOOST PRE-REGULATOR (VREG) (w/ Hiccup Mode) VREG ON VCP UV OSC1 BG1_UV, BG2_UV VCC UV, VCP UV VIN(UVLO) *VCP OV, *D1MISSING *SLEW UV/OV *ILIM,LX1, *OV > t dOV 20 k CLK1MHz NPOR ON/OFF VCC MODE VSS1RST SS_OK 0.47 F I1V25/FBadj VSS2RST * indicates a latched fault TSD RST WDFAULT BGVREF WDADJ,FAULT FBADJ ON ADJUSTABLE SYNCHRONOUS BUCK REGULATOR (1.25 VTYP) (w/ Hiccup Mode) WDSTART 1V25/ FBadj DEGLITCH t dFILT UV DETECT MPOR FBADJ UV 3V3 UV V5 UV V5P UV V5 FOLDBACK V5P V_IGN 7.5 k 7.5 V MMSZ 4693T1 2.2 F FOLDBACK 3V3 5V LDO BGVREF LDOs ON IENBAT1(BIAS) DEGLITCH tdFILT 3.3VTYP 2.6VTYP 650 k IENBAT2(BIAS) WD OSC WDENn WDENn RADJ 64.9 k for 20 ms V5 325 mAMAX V5 60 k WDSTART V5 (or VCC) FALLING SU/SD DELAY t dLDO(OFF) 20 k Last RESET State (latched) SET NPOR CLEAR Latches LX1 GND GND WATCHDOG TIMER CLK1MHz 20 k FF0 FF1 SU/SD SS_OK WDCLK WDENn = 0 or OPEN enables WD ON/OFF V5+V5P+3V3+FBADJ+VCP UV HICVREG+HIC1V25+TSD WDFAULT WDADJ,FAULT WDIN 3V3 165 mAMAX 3V3 2.2 F WDADJ CLKIN D5 MSS1P5 2.2 F 3.3 V LDO 1 3.3VTYP 2.6VTYP 650 k ENBAT2 0.22 F * V5P 115 mAMAX V5P ENBAT1 0.22 F * 3.3 k 7.5 V MMSZ 4693T1 2:1 MUX V5 60 k Short to VBAT Protection CP2 47 pF RZ2 6.81 k CZ2 1.5 nF CSS2 10 nF FOLDBACK 0 ENB * For negative V_IGN or V_ACC transient suppression COMP2 LDOs ON IBTRACK Microcontroller Enable 7.5 k FBADJ ON SELECT TRACK 1V25/FBadj 5V TRACKING LDO REF VREG ON STARTUP / SHUTDOWN SEQUENCE 2.49 k [1] SS2 BGFAULT SU/SD 1.25 V 3 x10 F 16 V / X7R / 1206 L2 4.7 H, 95 m 700 mA IHLP1616BZER4R7M11 (27 - 30 F @ 1.25 V) 1 APEAK PGND PGND 3.3V DEGLITCH t dFILT POK,L LX2 LX2 COMP2 & SS2 Reset CLK @ f OSC OV/UV DETECT & DELAYS UV,L1 or UV,L2 POK5V 3.3 k 2 k VREG MPOR MASTER IC POR (MPOR) D2 SS3P4 Q1: NVTFS4823N or SQS420EN or STL10N3LLH5 LG COMP1 and SS1 Reset IBMODE 20 k LXb D1 SS3P4 LX1 STOP PWM FSET UV/OV 5 x10 F 16 V / X7R / 1206 (38 - 43 F @ 5.3 V) L1 6.8 H, 50 m IHLP2525CZER6R8M01 LX1 FB VCC V_ACC RSLEW 22.1 k BG2_UV BGVREF CLK1MHz CLK @ f OSC RFSET 8.66 k POK5V SLEW 75 m FSET/SYNC NPOR BG2 SS1 CZ1 1.5 nF SYNC (optional) VIN(START) VIN(STOP) CP helper circuit. These components required if VVIN < 6V. ISLEW Charge Pump BGFAULT VIN(UVLO) 0.1 F 50 V VCP UV/OV BG1 BG VREF LDO 3.6 V D4 MSS1P5 D3 BAS16J CP2 Din SS3P4 VCP CP1 VBAT ONE SHOT WDFAULT 2 msTYP LX2 LXb 0603 50 V 0603 50 V 0603 50 V 1206 1/4 W 0603 1/10 W 0603 1/10 W Snubbers reduce ringing and high-frequency noise/emissions A4408 Figure 2: Functional Block Diagram/Typical Schematic Buck-Boost Mode (fOSC = 2 MHz) [1] For optimal no-load operation. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 D4 MSS1P5 0.1 F 50 V L1 4.7 H, 37 m IHLP2525CZER4R7M01 COMP1 CP1 27 pF D3 BAS16J CP2 A4408 CP1 These components required if VVIN < 6 V LX1 LX1 RZ1 13.3 k CZ1 2.7 nF 5.35 VTYP D1 SS2P4 3x10 F 16 V/X7R/1206 (23 - 26 F @ 5.3 V) LG VREG 0.47 F Figure 3: Functional Block Diagram Modifications for Buck Only Mode, fOSC = 2 MHz Power Derating at VVIN = 3 to 36 V 120% Percent of Maximum Load 100% 80% 60% 40% fSW = 500 kHz 20% fSW = 2 MHz 10% -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature (C) Figure 4: Thermal Derating for Buck-Boost Operation Down to 3V Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 Terminal List Table VCP 1 38 CP2 VIN 2 37 CP1 Number Name VIN 3 36 LX1 1 VCP Charge pump reservoir capacitor 35 LX1 2, 3 VIN Input voltage 34 SLEW 4, 9 GND Ground 5 MODE 6 VCC GND 4 MODE 5 VCC 6 33 LG SS1 7 32 VREG 31 V5 COMP1 8 30 LX2 GND 9 TRACK 10 PAD 29 LX2 NPOR 11 28 PGND POK5V 12 27 PGND FF0 13 26 COMP2 FF1 14 25 1V25/FBADJ FSET/SYNC 15 24 SS2 ENBAT1 16 23 V5P ENBAT2 17 22 WDENn ENB 18 21 WDADJ 3V3 19 20 WDIN Package LV, 38-Pin eTSSOP Pinout Diagram Function Sets UV threshold for V5/V5P in NPOR logic. MODE pin does not affect POK5V threshold. GND/low-NPORUV is set high at VV5x(UV,L1). Open/ high-NPORUV is set low at VV5x(UV,L2). Internal voltage regulator bypass capacitor pin 7 SS1 8 COMP1 Error amplifier compensation network pin for buck-boost pre-regulator Soft-start programming pin for buck-boost pre-regulator 10 TRACK Tracking control: Open/High - V5P tracks 3V3, GND/Low - V5P tracks V5 11 NPOR Active-low, open-drain regulator fault detection output 12 POK5V Power OK output indicating when either V5 or V5P rail is undervoltage (UV). POK5VUV threshold is always at VV5x(POK,L). 13, 14 FF0, FF1 Open-drain, latched Fault Flag (FFx) outputs indicate last type of fault to reset microcontroller. FF0 and FF1 bits are only valid if NPOR has first transitioned high. FF0 and FF1 latches are reset when all A4408 enable inputs are low and soft-start voltages have decayed below reset thresholds. See Table 2 for more details. 15 FSET/ SYNC 16 ENBAT1 17 ENBAT2 18 ENB Logic enable input from microcontroller 19 3V3 3.3V regulator output 20 WDIN 21 WDADJ 22 WDENn 23 V5P 5V tracking/protected regulator output Soft-start programming pin for adjustable synchronous buck regulator Frequency setting and synchronization input Ignition enable input from key/switch via 1k of resistance Ignition enable input from key/switch via 1k of resistance Watchdog refresh input (rising edge triggered) from microcontroller or DSP Watchdog wait/delay time is programmed by connecting RADJ from this pin to ground Watchdog enable pin: Open/Low - WD is enabled, High - WD is disabled 24 SS2 25 1V25/ FBadj 26 COMP2 27, 28 PGND 29, 30 LX2 Switching node for adjustable synchronous buck regulator 5V regulator output 31 V5 32 VREG 33 LG 34 SLEW 35, 36 LX1 37, 38 CP1, CP2 - PAD Feedback pin for 1.25V (or adjustable) synchronous buck regulator Error amplifier compensation network pin for 1.25V synchronous regulator Power ground for adjustable synchronous regulator and its gate driver Output of buck-boost and input for LDOs and adjustable synchronous buck regulator Boost gate drive output for buck-boost pre-regulator Slew rate adjustment for rise time of LX1 Switching node for buck-boost pre-regulator Charge pump capacitor connections Exposed thermal pad Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - BUCK AND BUCK-BOOST PRE-REGULATOR[1]: Valid at 3.6 V[2] < VVIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit After VVIN > VVIN(START), and VENB > 2V or VENBATx > 3.5V, Buck-Boost Mode 2.8 13.5 36 V After VVIN > VVIN(START), and VENB > 2V or VENBATx > 3.5V, Buck Mode 5.7 13.5 36 V GENERAL SPECIFICATIONS Operating Input Voltage VVIN VIN UVLO START Voltage VVIN(START) VVIN rising 5.1 5.4 5.7 V VIN UVLO STOP Voltage VVIN(STOP) VVIN falling 2.53 2.64 2.78 V VIN UVLO Hysteresis VVIN(HYS) VVIN(START) VVIN(STOP) - 2.7 - V VVIN = 13.5V, VENBATx 3.6V or VENB 2V, VVREG = 5.6V (no PWM) - 13 - mA VVIN = 13.5V, VENBATx 2.2V and VENB 0.8V - - 10 A 1.8 2.0 2.2 MHz IQ Supply Quiescent Current [1] IQ(SLEEP) PWM SWITCHING FREQUENCY AND DITHERING RFSET = 8.66 k Oscillator Frequency fOSC PWM Switching Frequency Foldback Thresholds fSW Frequency Dithering fOSC RFSET = 19.1 k - 1.0 - MHz RFSET = 52.3 k [3] 343 400 457 kHz VVREG > 2.7V, VVIN rising, fOSC fOSC/2 18.7 19.5 20.3 V VREG > 2.7 V, VVIN falling, fOSC/2 fOSC - 18.5 - V [3] VREG > 2.7 V, VVIN rising, fOSC/2 fOSC - 7.5 - V VREG > 2.7 V, VVIN falling, fOSC fOSC/2 6.7 7.0 7.4 V - 12 - % As a percent of fOSC Dither/Slew Start Threshold VIN(DS,ON) 8.5 9.0 9.5 V Dither/Slew Stop Threshold VIN(DS,OFF) 7.8 8.3 8.8 V VIN Dithering/Slew Hysteresis VIN(DS,HYS) - 700 - mV VVCP - VVIN, VVIN = 13.5 V, VVREG = 5.5 V, IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V, VENB = 3.3 V 4.1 6.6 - V VVCP - VVIN, VVIN = 6.5 V, VVREG = 5.5 V, IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V, VENB = 3.3 V 3.6 4.4 - V - 65 - kHz - 4.65 - V 155 170 185 C - 20 - C CHARGE PUMP (VCP) Output Voltage VVCP Switching Frequency fSW(CP) VCC PIN VOLTAGE Output Voltage VVCC VVREG = 5.35 V Thermal Shutdown Threshold [3] TTSD TJ rising Thermal Shutdown Hysteresis THYS THERMAL PROTECTION [3] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [1] Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - BUCK AND BUCK-BOOST PRE-REGULATOR (continued) [1]: Valid at 3.6 V[2] < VVIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VVREG VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.25 A 5.25 5.35 5.45 V VCOMP1 for 0% duty cycle - 400 - mV VVIN = 13.5 V, 10% to 90%, IVREG = 1 A, RSLEW = 22.1 k - 0.9 - V/ns VVIN = 13.5 V, 10% to 90%, IVREG = 1 A, RSLEW = 150 k - 0.3 - V/ns VVIN = 13.5 V, 90% to 10%, IVREG = 1 A - 1.5 - V/ns OUTPUT VOLTAGE SPECIFICATIONS Buck Output Voltage - Regulating PULSE-WIDTH MODULATION (PWM) PWM Ramp Offset LX1 Rising Slew Rate Control [3] VPWM1OFFS LX1RISE LX1 Falling Slew Rate [3] LX1FALL Buck Minimum On-Time tON(MIN,BUCK) - 85 160 ns DMAX(BUCK) - 100 - % 20 - % Buck Maximum Duty Cycle Boost Duty Cycle (LG Pin) COMP1 to LX1 Current Gain Slope Compensation [3] DMIN(BST) [3] After VVIN > VVIN(START), VVIN = 6.5 V - DMAX(BST) After VVIN > VVIN(START), VVIN = 3.5 V 53 61 66 % - 4.5 - A/V fOSC = 2 MHz 1.04 1.48 1.92 A/s fOSC = 400 kHz 0.22 0.33 0.44 A/s VVIN = 13.5 V, TJ = 40C [3], IDS = 0.1 A - 50 65 m VVIN = 13.5 V, TJ = 25C gmPOWER1 SE1 INTERNAL MOSFET MOSFET On-Resistance MOSFET Leakage RDSon IFET(LKG) [4], - 75 90 m VVIN = 13.5 V, TJ = 150C, IDS = 0.1 A IDS = 0.1 A - 150 180 m VENBATx 2.2V and VENB 0.8V, VLX1 = 0V, VVIN = 16V, -40C < TJ < 85C [4] - - 10 A VENBATx 2.2V and VENB 0.8V, VLX1 = 0V, VVIN = 16V, -40C < TJ < 150C - 50 150 A ERROR AMPLIFIER Open-Loop Voltage Gain [3] Transconductance AVOL1 gmEA1 - 60 - dB VSS1 = 750 mV 550 750 950 A/V VSS1 = 500 mV 275 375 500 A/V IEA1 - 75 - A Maximum Output Voltage VEA1VO(max) 1.3 1.7 2.1 V Minimum Output Voltage VEA1VO(min) - - 300 mV - 1 - k Output Current COMP1 Pull-Down Resistance RCOMP1 HICCUP1 = 1 or FAULT1 = 1 or VENBATx 2.2V and VENB 0.8V, latched until VSS1 < VSS1(RST) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] Specifications at 25C or 85C are guaranteed by design and characterization, not production tested. [1] Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - BUCK AND BUCK-BOOST PRE-REGULATOR (continued) [1]: Valid at 3.6V < VVIN < 36 V[2], -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 4.6 - 5.5 V BOOST MOSFET (LG) GATE DRIVER LG High Output Voltage VLG(ON) VVIN = 6 V, VVREG = 5.35 V LG Low Output Voltage VLG(OFF) VVIN = 13.5 V, VVREG = 5.35 V - 0.2 0.4 V LG Source Current [1] ILG(ON) VVIN = 6 V, VVREG = 5.35 V, VLG = 1 V - -300 - mA LG Sink Current [1] ILG(OFF) VVIN = 13.5 V, VVREG = 5.35 V, VLG = 1 V - 150 - mA - 400 - mV mV SOFT-START SS1 Offset Voltage VSS1(OFFS) VSS1 rising due to ISS1(SU) SS1 Fault/Hiccup Reset Voltage VSS1(RST) VSS1 falling due to HICCUP1 = 1 or FAULT1 = 1 or VENBATx 2.2V and VENB 0.8V 140 200 275 SS1 Startup (Source) Current ISS1(SU) VSS1 = 1V, HICCUP1 = FAULT1 = 0 -10 -20 -30 A SS1 Hiccup (Sink) Current ISS1(HIC) VSS1 = 0.5 V, HICCUP1 = 1 5 10 15 A SS1 Delay Time [3] tSS1(DLY) CSS1 = 22 nF - 440 - s SS1 Ramp Time [3] tSS1 CSS1 = 22 nF - 880 - s FAULT1 = 1 or IC disabled, latched until VSS1 < VSS1(RST) - 3 - k 0V < VVREG < 1.3VTYP, VCOMP1 = VEA1VO(max) - fOSC/8 - - SS1 Pull-Down Resistance SS1 PWM Frequency Foldback RPD(SS1) fSW1(SS) 0V < VVREG < 1.3VTYP, VCOMP1 < VEA1VO(max) - fOSC/4 - - 1.3 VTYP < VVREG < 2.7 VTYP - fOSC/2 - - VVREG > 2.7 VTYP - fOSC - - VSS1 > VHIC1(EN), VVREG < 1.3 VTYP, VCOMP1 = VEA1VO(max) - 30 - PWM cycles VSS1 > VHIC1(EN), VVREG > 1.3 VTYP, VCOMP1 = VEA1VO(max) - 120 - PWM cycles HICCUP MODE Hiccup1 OCP PWM Counts tHIC1(OCP) CURRENT PROTECTIONS Pulse-by-Pulse Current Limit LX1 Short-Circuit Current Limit ILIM1(ton,min) ILIM(LX1) VVIN < 7.0V, tON = tON(MIN) 4.1 4.6 5.1 A VVIN > 7.0V, tON = tON(MIN) 2.5 2.8 3.3 A Latched fault 6.0 7.0 - A MISSING ASYNCHRONOUS DIODE (D1) PROTECTION Detection Level VD(OPEN) -1.9 -1.5 -1.0 V Time Filtering [3] tD(OPEN) 50 - 250 ns For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [1] [2] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - ADJUSTABLE SYNCHRONOUS BUCK REGULATOR[1]: Valid at 3.6 V[2] < VVIN < 36V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 1.23 1.25 1.27 V FEEDBACK REFERENCE VOLTAGE Feedback Voltage Accuracy V1V25/FBadj 50mA < I1V25 < 700mA PULSE-WIDTH MODULATION (PWM) PWM Ramp Offset VPWM2(OFFS) VCOMP2 for 0% duty cycle High-Side MOSFET Minimum On-Time tON(MIN) High-Side MOSFET Minimum Off-Time tOFF(MIN) Gate Driver Non-Overlap Time [3] COMP2 to LX2 Current Gain Slope Compensation [3] Does not include total gate driver non-overlap time, tNO - 350 - mV - 65 105 ns - 100 125 ns tNO - 15 - ns gmPOWER2 - 3.7 - A/V fOSC = 2 MHz 0.45 0.63 0.81 A/s fOSC = 400 kHz 0.12 0.14 0.19 A/s TA = 25C [4], IDS = 100 mA - 200 235 m IDS = 100 mA - - 400 m VVREG = 5.5 V - 12 - ns VENBATx 2.2V and VENB 0.8V, VLX2 = 0V, VVREG = 5.5V, 40C < TJ < 85C [4] - - 2 A VENBATx 2.2V and VENB 0.8V, VLX2 = 0V, VVREG = 5.5V, -40C < TJ < 150C - 3 15 A TA = 25C [4], IDS = 100 mA - 55 65 m SE2 INTERNAL MOSFETS High-Side MOSFET On-Resistance LX2 Node Rise/Fall Time [3] High-Side MOSFET Leakage [2] Low-Side MOSFET On-Resistance Low-Side MOSFET Leakage [2] RDSon(HS) tR/F(LX2) IDSS(HS) RDSon(LS) IDSS (LS) IDS = 100 mA - - 110 m VENBATx 2.2V and VENB 0.8V, VLX2 = 5.5V, 40C < TJ < 85C [4] - - 1 A VENBATx 2.2V and VENB 0.8V, VLX2 = 5.5V, -40C <TJ < 150C - 8 25 A VCOMP2 = 0.8V, VFB(ADJ) regulated so that ICOMP2 = 0 A - -150 -350 nA ERROR AMPLIFIER Feedback Input Bias Current [2] Open-Loop Voltage Gain [3] Transconductance I1V25/FBAdj AVOL2 gmEA2 - 60 - dB 515 900 1350 A/V 0 V < VSS2 < 500 mV - 250 - A/V VCOMP2 = 1.5 V - 50 - A ICOMP2 = 0 A, VSS2 > 500 mV Source and Sink Current IEA2 Maximum Output Voltage VEA2VO(max) 1.00 1.25 1.50 V Minimum Output Voltage VEA2VO(min) - - 150 mV - 1.5 - k COMP2 Pull-Down Resistance RCOMP2 HICCUP2 = 1 or FAULT2 = 1 or VENBATx 2.2 V and VENB 0.8 V, latched until VSS2 < VSS2(RST) For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] Specifications at 25C or 85C are guaranteed by design and characterization, not production tested. [1] Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - ADJUSTABLE SYNCHRONOUS BUCK REGULATOR[1] (continued): Valid at 3.6 V[2] < VVIN < 36V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 120 200 270 mV - 100 120 mV -10 -20 -30 A SOFT-START SS2 Offset Voltage SS2 Fault/Hiccup Reset Voltage SS2 Startup (Source) Current VSS2(OFFS) VSS2 rising due to ISS2(SU) VSS2(RST) VSS2 falling due to HICCUP2 = 1 or FAULT2 = 1 or VENBATx 2.2V and VENB 0.8V ISS2(SU) VSS2 = 1V, HICCUP2 = FAULT2 = 0 SS2 Hiccup (Sink) Current ISS2(HIC) VSS2 = 0.5 V, HICCUP2 = 1 5 10 20 A SS2 to V1V25 Delay Time [3] tSS2(DLY) CSS2 = 10 nF - 100 - s tSS2 CSS2 = 10 nF - 625 - s FAULT2 = 1 or VENBATx 2.2V and VENB 0.8V, latched until VSS2 < VSS2(RST) - 2 - k V1V25/FBadj < 450mVTYP - fOSC/4 - - 450mVTYP < V1V25/FBadj < 780mVTYP - fOSC/2 - - V1V25/FBadj > 780mVTYP - fOSC - - VSS2 rising - 2.3 - V V1V25 Ramp Time [3] SS2 Pull-Down Resistance RPD(SS2) SS2 PWM Frequency Foldback fSW2(SS) HICCUP MODE Hiccup2 OCP Enable Threshold Hiccup2 OCP Counts VHIC2(EN) tHIC2(OCP) VSS2 > VHIC2(EN), V1V25/FBadj < 450mVTYP - 30 - PWM cycles VSS2 > VHIC2(EN), V1V25/FBadj > 450mVTYP - 120 - PWM cycles 1.8 2.1 2.7 A - 500 - mA CURRENT PROTECTIONS High-Side MOSFET Pulse-by-Pulse Current Limit ILIM2(5%) Low-Side MOSFET Reverse Current Limit ILIM2(LS) Duty cycle = 5% For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] Specifications at 25C or 85C are guaranteed by design and characterization, not production tested. [1] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 ELECTRICAL CHARACTERISTICS - V5 and V5P LINEAR REGULATOR (LDO) [1]: Valid at 3.6 V[2] < VVIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 4.9 5.0 5.1 V F V5 AND V5P LINEAR REGULATORS V5 Accuracy and Load Regulation V5 Output VV5 Capacitance [3] COUT(V5) V5P Accuracy and Load Regulation VV5P 10 mA < IV5 < 325 mA, VVREG = 5.25 V 1.0 - 22 4.9 5.0 5.1 V 1.5 2.2 4.1 F VVCP = 8.60V, TRACK = 1, IV5 = 265mA, IV5P = 35mA, I3V3 = 75mA, I1V25 = 250mA 1) TA = 150C, VVIN = 5.26V, VVREG = 5.14V 2) TA = 40C [3], VVIN = 5.04V, VVREG = 4.97V 4.82 - - V VVCP = 7.70V, TRACK = 1, IV5 = 265mA, IV5P = 35mA, I3V3 = 75mA, I1V25 = 250mA 1) TA = 150C, VVIN = 4.26V, VVREG = 4.14V 2) TA = 40C [3], VVIN = 4.04V, VVREG = 3.97V 3.65 - - V VVIN = 2.8V, VVREG = 5.25V, VVCP 7.5V, TRACK = 1, IV5 = 310mA, IV5P = 110mA, I3V3 = 100mA, I1V25 = 500mA 4.82 4.90 - V V5P/3V3 Tracking Ratio VV5P / V3V3 1.508 1.515 1.523 - V5P/3V3 Tracking Accuracy TRACK3V3 3V < V3V3 < 3.3V, TRACK = 1, I3V3 = IV5P = 75mA -0.5 - +0.5 % V5P/V5 Tracking Accuracy TRACKV5 3.5V < VV5 < 5.0V, TRACK = 0, IV5P = IV5 = 75mA -25 - +25 mV V5P Output Capacitance [3] V5 and V5P Minimum Output Voltage, Buck Only Mode [3] COUT(V5P) VV5x(MIN1) (5.5 VBAT) VV5x(MIN2) (4.5 VBAT) V5 and V5P Minimum Output Voltage, Buck-Boost Mode [3][4] 10 mA < IV5P < 115 mA, VVREG = 5.25 V VV5x(MIN3) V5P TRACKING V5P OVERCURRENT PROTECTION V5P Current Limit [1] ILIM(V5P) VV5P = 5 V -210 -285 - mA V5P Foldback Current [1] IFBK(V5P) VV5P = 0 V -30 -60 -90 mA V5 Current Limit [1] ILIM(V5) VV5 = 5 V -350 -500 - mA V5 Foldback Current [1] IFBK(V5) VV5 = 0 V -40 -75 -180 mA V5P Startup Time [3] tSU(V5P) CV5P 2.9 F, Load = 45 5% (110 mA) - 175 565 s V5 Startup Time tSU(V5) CV5 2.9 F, Load = 16 5% (310 mA) - 150 530 s V5 OVERCURRENT PROTECTION V5P AND V5 STARTUP TIMING [3] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] See B/B schematic, CP helper circuit required when V VIN < 6V. [1] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 ELECTRICAL CHARACTERISTICS - 3V3 LDO and CONTROL INPUTS [1]: Valid at 3.6 V[2] < VVIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 3.23 3.30 3.37 V 1.0 - 22 F VVCP = 8.80V, TRACK = 1, IV5 = 265mA, IV5P = 35mA, I3V3 = 75mA, I1V25 = 250mA 1) TA = 150C, VVIN = 5.26V, VVREG = 5.14V 2) TA = 40C [3], VVIN = 5.04V, VVREG = 4.97V 3.23 3.30 - V VVCP = 6.80V, TRACK = 1, IV5 = 265mA, IV5P = 35mA, I3V3 = 75mA, I1V25 = 250mA 1) TA = 150C, VVIN = 4.26V, VVREG = 4.14V 2) TA = 40C [3], VVIN = 4.04V, VVREG = 3.97V 3.20 - - V ILIM(3V3) V3V3 = 3.3 V -185 -260 - mA IFBK(3V3) V3V3 = 0 V -15 -40 -65 mA tSU(3V3) C3V3 2.9 F, Load = 33 5% (100 mA) - 170 550 s 3V3 LINEAR REGULATORS 3V3 Accuracy and Load Regulation 3V3 Output Capacitance [3] 3V3 Minimum Output Voltage, Buck Only Mode [3] V3V3 10 mA < I3V3 < 165 mA, VVREG = 5.25 V COUT(3V3) V3V3(MIN1) (5.5 VBAT) V3V3(MIN2) (4.5 VBAT) 3V3 OVERCURRENT PROTECTION 3V3 Current Limit [1] 3V3 Foldback Current [1] 3V3 STARTUP TIMING 3V3 Startup Time [3] IGNITION ENABLE (ENBAT1 AND ENBAT2) INPUTS ENBAT1, ENBAT2 Thresholds ENBAT1, ENBAT2 Hysteresis ENBAT1, ENBAT2 Bias Current [2] ENBAT1, ENBAT2 Resistance VENBATx(H) VENBATx rising 2.9 3.3 3.5 V VENBATx(L) VENBATx falling 2.2 2.6 2.9 V VENBATx(H) - VENBATx(L) - 700 - mV TJ = 25C [4], VENBATx = 3.51V - 28 45 A VENBATx(HYS) IENBATx(BIAS) TJ = 150C, VENBATx = 3.51V - 35 55 A RENBATx VENBATx < 1.2V - 650 - k VENB(H) VENB rising - - 2.0 V VENB(L) VENB falling 0.8 - - V IENB(IN) VENB = 3.3V - - 175 A RENB VENB = 0.8V - 60 - k 10 15 20 s 15 50 100 s LOGIC ENABLE (ENB) INPUT ENB Thresholds ENB Bias Current [1] ENB Resistance ENB/ENBATX FILTER/DEGLITCH Enable Filter/Deglitch Time tdEN(FILT) ENB/ENBATX SHUTDOWN DELAY LDO Shutdown Delay tdLDO(OFF) Measure tdLDO(OFF) from the falling edge of ENB and ENBAT1 and ENBAT2 to time when all LDOs begin to decay For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] Specifications at 25C or 85C are guaranteed by design and characterization, not production tested. [1] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - 3V3 LDO and CONTROL INPUTS [1] (continued): Valid at 3.6 V[2] < VVIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit TRACK AND MODE INPUTS TRACK and MODE Thresholds TRACK and MODE Bias Current [1] VTH, VMH VTRACK or VMODE rising - - 2.0 V VTL, VML VTRACK or VMODE falling 0.8 - - V - -50 - A No external SYNC signal - 800 - mV IBTRACK, IBMODE FSET/SYNC INPUT FSET/SYNC Pin Voltage VFSET/SYNC FSET/SYNC Open Circuit (Undercurrent) Detection Time tFSET/SYNC(UC) PWM switching disabled upon detection - 3 - s FSET/SYNC Short Circuit (Overcurrent) Detection Time tFSET/SYNC(OC) PWM switching disabled upon detection - 3 - s 250 - - kHz Sync. Minimum Frequency fSYNC(MIN) Sync. High Threshold VSYNC(IH) VSYNC rising - - 2.0 V Sync. Low Threshold VSYNC(IL) VSYNC falling 0.5 - - V Sync. Input Duty Cycle DCSYNC - - 80 % Sync. Input Pulse Width twSYNC 200 - - ns Sync. Input Transition Times [3] ttSYNC - 10 15 ns VSLEW - 800 - mV SLEW INPUT SLEW Pin Operating Voltage SLEW Open Circuit (Undercurrent) Detection Time tSLEW(UC) PWM latched off if open - 3 - s SLEW Short Circuit (Overcurrent) Detection Time tSLEW(OC) PWM latched off if shorted - 3 - s - -100 - nA SLEW Bias Current [1] ISLEW For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] The lowest operating voltage is only valid if the conditions V VIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. [3] Ensured by design and characterization, not production tested. [4] Specifications at 25C or 85C are guaranteed by design and characterization, not production tested. [1] Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - DIAGNOSTIC OUTPUTS [1]: Valid at 3.6 V[2] < VIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit NPOR OV/UV PROTECTION THRESHOLDS V5 OV Thresholds V5 OV Hysteresis V5 UV Thresholds V5P Output Disconnect Threshold V5P OV Thresholds VV5(OV,H) VV5 rising 5.15 5.33 5.50 V VV5(OV,L) VV5 falling - 5.30 - V VV5(OV,HYS) VV5(OV,H) - VV5(OV,L) 15 30 50 mV VV5(UV,H) VV5 rising, independent of the MODE pin - 4.68 - V VV5(UV,L1) VV5 falling, VMODE = 0V or GND 4.50 4.65 4.80 V VV5(UV,L2) VV5 falling, VMODE = 5V or open 3.00 3.13 3.27 V VV5P(DISC) VV5P rising - 7.2 - V VV5P(OV,H) VV5P rising 5.15 5.35 5.50 V VV5P(OV,L) VV5P falling - 5.29 - V VV5P(OV,H) - VV5P(OV,L) 45 60 75 mV V5P OV Hysteresis VV5P(OV,HYS) VV5P(UV,H) VV5 rising, independent of the MODE pin - 4.68 - V V5P UV Thresholds VVP5(UV,L1) VV5P falling, VMODE = 0V or GND 4.50 4.65 4.80 V VV5P(UV,L2) VV5P falling, VMODE = 5V or open 3.00 3.13 3.27 V V3V3(OV,H) V3V3 rising 3.41 3.52 3.60 V V3V3(OV,L) V3V3 falling - 3.48 - V 3V3 OV Thresholds 3V3 OV Hysteresis 3V3 UV Thresholds 3V3 UV Hysteresis 1V25/FBadj OV Thresholds 1V25/FBadj OV Hysteresis 1V25/FBadj UV Thresholds 1V25/FBadj UV Hysteresis [1] [2] V3V3(OV,HYS) V3V3(OV,H) - V3V3(OV,L) 25 35 50 mV V3V3(UV,H) V3V3 rising - 3.12 - V V3V3(UV,L) V3V3 falling 2.97 3.07 3.17 V 40 50 60 mV V3V3(UV,HYS) V3V3(UV,H) - V3V3(UV,L) V1V25(OV,H) V1V25/FBadj rising 1.29 1.32 1.35 V V1V25(OV,L) V1V25/FBadj falling - 1.30 - V V3V3(OV,HYS) V1V25(OV,H) - V1V25(OV,L) 15 22 30 mV V1V25(UV,H) V1V25 rising, triggers LDOs on - 1.20 - V V1V25(UV,L) V1V25 falling 1.15 1.18 1.21 V 10 17 25 mV V1V25(UV,HYS) V1V25(UV,H) - V1V25(UV,L) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - DIAGNOSTIC OUTPUTS (continued) [1]: Valid at 3.6 V[2] < VIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 6.40 8.00 9.60 ms 12 15 18 ms ENB and ENBAT1 and ENBAT2 low to NPOR low - 15 23 s ENB or ENBAT1 or ENBAT2 high, VVIN 2.5V, INPOR = 4mA - 150 400 mV ENB or ENBAT1 or ENBAT2 high, VVIN = 1.5V, INPOR = 2mA - - 800 mV VNPOR = 3.3V - - 2 A Applies to undervoltage of 3V3, 1V25/FBadj, V5, and V5P voltages 10 15 20 s NPOR OV DELAY TIME (First silicon will shut down if an OV is detected) Overvoltage Detection Delay tdOV V5P, V5, 3V3, and 1V25/FBadj over voltage detection delay time NPOR TURN-ON AND TURN-OFF DELAYS NPOR Turn-On Delay tdNPOR(ON) NPOR Turn-Off Propagation Delay tdNPOR(OFF) NPOR OUTPUT VOLTAGES NPOR Output Low Voltage NPOR Leakage Current [1] VNPOR(L) INPOR(LKG) NPOR AND POK5V UV FILTERING/DEGLITCH UV Filter/Deglitch Times tdFILT POK5V UV PROTECTION THRESHOLDS V5 and V5P Rising Thresholds VV5x(POK,H) VV5 or VV5P rising, independent of the MODE pin - 4.68 - V V5 and V5P Falling Thresholds VV5x(POK,L) VV5 or VV5P falling, independent of the MODE pin 4.50 4.65 4.80 V ENB = 1 or ENBAT1 = 1 or ENBAT2 = 1, VVIN 2.5V, IPOK5V = 4mA - 150 400 mV ENB = 1 or ENBAT1 = 1, ENBAT2 = 1, VVIN = 1.5V, IPOK5V = 2mA - - 800 mV VPOK5V = 3.3V - - 2 A POK5V OUTPUT VOLTAGES POK5V Output Voltage POK5V Leakage Current [1] [2] VPOK5V(L) IPOK5V(LKG) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - DIAGNOSTIC OUTPUTS (continued) [1]: Valid at 3.6 V[2] < VIN < 36 V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VREG, VCP, AND BG THRESHOLDS VREG OV Thresholds VREG OV Hysteresis VREG UV Thresholds VREG UV Hysteresis VCP OV Thresholds VCP UV Thresholds VCP UV Hysteresis BGREF and BGFAULT UV Thresholds [3] VVREG(OV,H) VVREG rising, LX1 PWM disabled 5.50 5.65 5.90 V VVREG(OV,L) VVREG falling, LX1 PWM enabled - 5.55 - V VREG(OV,HYS) VVREG(OV,H) - VVREG(OV,L) VVREG(UV,H) VVREG rising, triggers rise of SS2 VVREG(UV,L) VVREG falling VVREG(UV,HYS) VVREG(UV,H) - VVREG(UV,L) - 100 - mV 4.14 4.38 4.62 V - 4.28 - V - 100 - mV VVCP(OV,H) VVCP rising, latches all regulators off 11.0 12.5 14.0 V VVCP(UV,H) VVCP rising, PWM enabled - 3.2 - V VVCP(UV,L) VVCP falling, PWM disabled - 2.8 - V VVCP(UV,HYS) VBGx(UV) VVCP(UV,H) - VVCP(UV,L) VBGVREF or VBGFAULT rising - 400 - mV 1.00 1.05 1.10 V 0.8 1.0 1.2 ms LAST MICROCONTROLLER (OR DSP) RESET STATE INDICATORS (FF0 AND FF1) FF0, FF1 UV Detection Delay tdFFx(UV) NPOR due to UV to FF0/FF1 latching FF0, FF1 Output Voltage VFFx(LO) IFFx = 4mA - - 400 mV IFFx VFFx = 3.3V - - 1 A FF0, FF1 Leakage Current [1] [1] [2] [3] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 ELECTRICAL CHARACTERISTICS - WATCHDOG TIMER (WDT) [1]: Valid at 3.6 V[2] < VVIN < 36V, -40C < TA = TJ < 150C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit WD ENABLE/ INPUT (WDENn) WDENn Voltage Thresholds WDENn Input Resistance VWDENn(LO) VWDENn falling, WDT enabled 0.8 - - V VWDENn(HI) VWDENn rising, WDT disabled - - 2.0 V - 60 - k RWD(ENn) WD IN VOLTAGE THRESHOLDS AND CURRENT WDIN Input Voltage Thresholds WDIN Input Current [1] VWDIN(LO) VWDIN falling, WDADJ pulled low by RADJ VWDIN(HI) VWDIN rising, WDADJ charging IWDIN 0.8 - - V - - 2.0 V VWDIN = 5V -10 1 10 A 20 50 80 % Default 120 140 160 ms Metal Option 24 30 36 ms RADJ = 32.4k 8.0 10 12 ms RADJ = 324k 80 100 120 ms 1.6 2.0 2.4 ms WD IN TIMING SPECIFICATIONS WDIN Duty Cycle Watchdog Activation Delay DWDIN tdWD(START) WD PROGRAMMING (WD ADJ) WD Timeout, Slow Clock tWD(TO,SLOW) WD ONE-SHOT TIME WD Pulse Time after WD Fault [1] [2] tWD(FAULT) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP - VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satisfied before VVIN is reduced. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 FUNCTIONAL DESCRIPTION Overview The A4408 is a power management IC designed for automotive applications. It contains a pre-regulator plus four DC postregulators to create the voltages necessary for typical automotive applications such as electrical power steering and automatic transmission control. The pre-regulator can be configured as a buck or buck-boost regulator. Buck-boost is required for applications that must work at extremely low battery voltages. This pre-regulator generates a fixed 5.35V and can deliver up to 1A to power the internal or external post-regulators. These post-regulators generate the various voltage levels for the end system. The A4408 includes four internal post-regulators: three linear regulators and one adjustable output synchronous buck regulator. The synchronous buck regulator was designed to deliver 1.25V/700mA but will produce higher voltages if a feedback resistor divider is used. Buck-Boost Pre-Regulator (VREG) Figure 5: A4408 Buck-Boost operation at full load VVIN slew rates ranging from 0.3V/ms to 1.6V/ms Typical of an automotive START/STOP waveform VVIN(TYP) = 12 V, VVIN(MIN) = 2.9 V, 10 ms/DIV CH1=VIN, CH2=VREG, CH3=V5, CH4=3V3, M1=1V25, M2=V5P The pre-regulator incorporates an internal high-side buck switch and a boost switch gate driver. An external freewheeling Schottky diode and an LC filter are required to complete the buck converter. By adding a MOSFET and a Schottky diode, the boost configuration can maintain all outputs with input voltages as low as 2.8V. The A4408 includes a compensation pin (COMP1) and a soft-start pin (SS1) for the pre-regulator. The A4408 can maintain its outputs over a wide range of input voltages and slew rates. Actual boost performance is shown in Figure 5 and Figure 6 with voltages swinging between 2.9 and 18V, and VVIN slew rates ranging from 0.3 to 100V/ms. The buck-boost pre-regulator provides protection and diagnostic functions. 1. 2. 3. 4. 5. 6. Overvoltage protection High voltage rating for load dump Switch-node-to-ground short-circuit protection Open freewheeling diode protection Pulse-by-pulse current limit Hiccup short circuit protection - lab measurement shown in Figure 7 and detailed timing diagram shown in Figure 5 Figure 6: A4408 Buck-Boost operation at full load VVIN slew rates of 100V/ms V5P deviates less than 0.2% VVIN(TYP) = 12 V, VVIN(MIN) = 4 V, VVIN(MAX) = 18V CH1=VIN, CH2=VREG, CH3=V5, CH4=V5P, 500s/DIV Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 2.4 2.3 2.2 2.1 2.0 ILIM (A) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 Figure 7: Pre-Regulator Hiccup Mode Operation when VREG is Shorted to GND and CSS1 = 22nF CH1=VREG, CH2=COMP1, CH3=SS1, CH4=IL1, 1ms/DIV For the pre-regulator, hiccup mode is enabled when PWM switching begins. If VVREG is less than 1.3 V, the number of overcurrent pulses (OCP) is limited to only 30. If VVREG is greater than 1.3 V, the number of OCP pulses is increased to 120 to accommodate the possibility of starting into a relatively high output capacitance. 5 Max_2MHz TYP_2MHz Min_2MHz Max_400kHz TYP_400kHz Min_400kHz 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Duty Cycle (%) Figure 8: Synchronous Buck Pulse-by-Pulse Current Limit The synchronous buck is powered by the 5.35V pre-regulator output. An external LC filter is required to complete the synchronous buck regulator. The A4408 includes a compensation pin (COMP2) and a soft-start pin (SS2) for the synchronous buck. Adjustable Synchronous Buck Regulator (1V25/ADJ) The A4408 integrates the high-side and low-side MOSFETs necessary for implementing an adjustable output synchronous buck regulator. The synchronous buck is optimized for 1.25VOUT/700 mADC/1APEAK but can produce higher output voltages if a feedback resistor divider is inserted between VOUT and the 1V25/FBadj pin. The synchronous buck's pulse-by-pulse current limit depends on duty cycle and switching frequency, as shown in Figure 8. An internal current sense amplifier sources 80to 100A to the LX2 pin. At no load, this current will slowly charge the output capacitors and raise the output voltage. Therefore, the system must always sink at least 100A, or a pull-down resistor (<2.49k) should be used as shown in the Applications Schematic. Protection and safety functions provided by the synchronous buck are: 1. 2. 3. 4. 5. Undervoltage detection Overvoltage detection Switch-node-to-ground short-circuit protection Pulse-by-pulse current limit Hiccup short-circuit protection; lab measurement shown in Figure 9 and detailed timing diagram shown in Figure 23 Figure 9: Synchronous Buck Hiccup Mode Operation when 1V25 is Shorted to GND and CSS2 = 10 nF CH1=1V25, CH2=COMP2, CH3=SS2, CH4=IL2, 500 s/DIV For the synchronous buck, hiccup mode is enabled when VSS2 = VHIC2(EN) (1.2 VTYP). If V1V25/FBadj is less than 450 mVTYP, the number of overcurrent pulses (OCP) is limited to only 30. If V1V25/FBadj is greater than 450 mVTYP, the number of OCP pulses is increased to 120 to accommodate the possibility of starting into a relatively high output capacitance. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 Low-Dropout Linear Regulators (LDOs) The A4408 has three low-dropout linear regulators (LDOs), one 3.3 V/165 mAMAX (3V3), one 5 V/325 mAMAX (V5), and one high-voltage protected 5 V/115 mAMAX (V5P). The switching pre-regulator efficiently regulates the battery voltage to an intermediate value to power the LDOs. This pre-regulator topology reduces LDO power dissipation and junction temperature. 5V TRACKING LDO VREG REFERENCE IBTRACK SEL TRACK All linear regulators provide the following protection features: 1. Undervoltage and overvoltage detection 2. Current limit (ILIM) with foldback short-circuit protection (IFBK); see Figure 10 The protected 5 V regulator (V5P) includes protection against accidental short-circuit to the battery voltage. This makes this output most suitable for powering remote sensors or circuitry via a wiring harness where short-to-battery is possible. 100% 2:1 MUX 0 1 V5 3V3 Figure 11: The V5P reference is set by the TRACK input. Watchdog Timer (WDT) The A4408 watchdog timer monitors the time between rising edges of a clock (i.e. the clock period) applied to the WDIN pin. This clock should be generated by the primary microcontroller or DSP. A watchdog fault will occur if the time between rising edges is longer than the time set by the resistor (RADJ) at the watchdog programming pin (WDADJ). A watchdog fault will pulse NPOR low for tWD(FAULT) (typically 2ms). The watchdog circuitry is shown in Figure 12. WDADJ CLKIN WDENn Vx V5P RADJ WD OSC WDCLK WDIN WDENn Window Watchdog Timer WDFAULT WDSTART Figure 12: Watchdog Timer Block Diagram The watchdog time is programmable via the WDADJ pin according to the following equation: Ix IFBKmin IFBKtyp ILIMmin ILIMtyp Figure 10: Typical LDO Foldback Characteristics Tracking Input (TRACK) The V5P LDO is a tracking regulator. It can be set to use either V5 or 3V3 as its reference by setting the TRACK input pin to a logic low or high. If the TRACK input is left unconnected, an internal current source will set the TRACK pin to a logic high. RADJ = 3.240 x tWD(TO,SLOW) where tWD(TO,SLOW) is the longest expected clock period (in ms) and RADJ is the external resistor value (in k) needed from the WDADJ pin to ground. A detailed watchdog timing diagram is shown in Figure 24. The watchdog is enabled when two conditions are met: 1. The WDENn pin is a logic low, and 2. All the regulators (1V25/FBadj, 3V3, V5, and V5P) have been above their undervoltage thresholds for the watchdog start delay time, tdWD(START) (140msTYP). Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 21 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 The watchdog start delay allows the microcontroller or DSP to complete its initialization routines before delivering a clock to the WDIN pin. A timing diagram documenting tdWD(START) is shown in Figure 25. After regulator startup, if the WDIN clock is missing (i.e. stuck low or stuck high) for at least tdWD(START) + tWD(TO,SLOW) the A4408 will set NPOR, reset its counters, and repeat the watchdog startup delay. NPOR will periodically pulse low as long as no WDIN clock is applied. A timing diagram for the missing clock situation is shown in Figure 25. Dual Bandgaps (BGVREF, BGFAULT) Dual bandgaps, or references, are implemented within the A4408. One bandgap (BGVREF) is dedicated solely to closed-loop control of the output voltages. The second bandgap (BGFAULT) is employed for fault monitoring functions. Having redundant bandgaps improves reliability of the A4408. If the reference bandgap is out of specification (BGVREF), then the output voltages will be out of specification and the monitoring bandgap will report a fault condition by setting NPOR and/or POK5V low. If the monitoring bandgap is out of specification (BGFAULT), then the outputs will remain in regulation, but the monitoring circuits will report a fault condition by setting NPOR and/or POK5V low. The reference and monitoring bandgap circuits include two smaller secondary bandgaps that are used to detect undervoltage of the main bandgaps during power-up. Adjustable Frequency and Synchronization (FSET/SYNC) The PWM switching frequency of the A4408 is adjustable from 250 kHz to 2.4 MHz. Connecting a resistor from the FSET/ SYNC pin to ground sets the switching frequency. An FSET resistor with 1% tolerance is recommended. The FSET resistor can be calculated using the following equation: RFSET = ( 21,693 fOSC ) - 2.215 where RFSET is in k and fOSC is the desired oscillator (PWM) frequency in kHz. A graph of switching frequency versus FSET resistor values is shown in Figure 13. The PWM frequency of the A4408 may be increased or decreased by applying a clock to the FSET/SYNC pin. The clock must satisfy the voltage thresholds and timing requirements shown in the Electrical Characteristics table. 2.4 PWM Switching Frequency vs RFSET 2.2 2.0 PWM Switching Frequency (MHz) A4408 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 RFSET (K) Figure 13: Switching Frequency vs. FSET Resistor Values Frequency Dithering and LX1 Slew Rate Control The A4408 includes two innovative techniques to help reduce EMI/EMC for demanding automotive applications. First, the A4408 performs pseudo-random dithering of the PWM frequency. Dithering the PWM frequency spreads the energy above and below the base frequency set by RFSET. A typical fixedfrequency PWM regulator will create distinct "spikes" of energy at fOSC, and at higher frequency multiples of fOSC. Conversely, the A4408 spreads the spectrum around fOSC, thus creating a lower magnitude at any comparable frequency. Frequency dithering is disabled if SYNC is used or VVIN drops below approximately 8.3 V. Second, the A4408 includes a pin to adjust the rising slew rate of the LX1 pin by simply changing the value of the resistor from the SLEW pin to ground. Slower rise times of LX1 reduce ringing and high-frequency harmonics of the regulator. The rise time may be adjusted to be relatively long and will increase thermal dissipation of the pre-regulator if set too high. Typical LX1 slew rates are shown in Table 1. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 22 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 RSLEW (k) LX1 Rising Slew Rate (V/ns) LX1 10%-90% Transition Time at 12VVIN (ns) 8.66 1.06 9.1 22.1 0.90 10.7 46.4 0.79 12.1 71.5 0.65 14.8 100 0.50 19.2 121 0.38 25.2 150 0.29 33.1 Enable Inputs (ENB, ENBAT) Two enable pins are available on the A4408. A logic high on either of these pins enables the A4408. One enable (ENB) is logic-level compatible for microcontroller or DSP control. The other input (ENBAT) must be connected to the high-voltage ignition (IGN) or accessory (ACC) switch through a relatively low-value series resistance, 2 to 3.6 k. For transient suppression, it is strongly recommended that a 0.22 to 0.47 F capacitor be placed after the series resistance to form a low-pass filter to the ENBAT pin as shown in the Applications Schematic. Bias Supply (VCC) The bias supply (VCC) is generated by an internal linear regulator. This supply is the first rail to start up. Most of the internal control circuitry is powered by this supply. The bias supply includes some unique features to ensure reliable operation of the A4408. These features include: 1. 2. 3. 4. Input voltage (VVIN) undervoltage lockout Undervoltage detection Short-to-ground protection Operation from either VLDO3.6V or VVREG, whichever is higher Charge Pump (VCP, CP1, CP2) A charge pump provides the voltage necessary to drive the highside N-channel MOSFETs in the pre-regulator and the linear regulators. Two external capacitors are required for charge pump operation. During the first half of the charge pump cycle, the flying capacitor between pins CP1 and CP2 is charged from either VVIN or VVREG, whichever is highest. During the second half of the charge pump cycle, the voltage on the flying capacitor charges the VCP capacitor. For most conditions, the VVCP minus VVIN voltage is regulated to approximately 6.5 V. The charge pump can provide enough current to operate the pre-regulator and the LDOs at 2.2 MHz (full load) and 125C ambient, provided VVIN is greater than 6V. Optional components D3, D4, and CP3 (refer to Figure 14) must be included if VVIN drops below 6V. Diode D3 should be a silicon diode rated for at least 200 mA/50 V with less than 50 A of leakage current when VR = 13 V and TA = 125C. Diode D4 should be a 1 A Schottky diode with a very low forward voltage (VF) rated to withstand at least 30 V. CP2 0.22 F Required if VREG is fully loaded and VVIN < 6.0 V CP2 Table 1: Typical LX1 Rising Slew Rate vs. RSLEW; LX1 Snubber 8.66 / 330pF CP1 A4408 D3 BAS16J D4 MSS1P5 CP3 0.1 F/50 V LX1 LX1 LG Figure 14: Charge pump enhancement components D3, D4, and CP3 are required if VVIN < 6V. The charge pump incorporates some protection features: 1. Undervoltage lockout of PWM switching 2. Overvoltage "latched" shutdown of the A4408 Startup and Shutdown Sequences The startup and shutdown sequences of the A4408 are fixed. If no faults exist and ENBAT or ENB transition high, the A4408 will perform its startup routine. If ENBAT and ENB are low for at least tdEN(FILT) + tdLDO(OFF) (typically 65 s), the A4408 will enter a shutdown sequence. The startup and shutdown sequences are summarized in Table 3 and shown in timing diagrams in Figure 18 and Figure 19. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 23 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Fault Reporting (NPOR, MODE, POK5V) The A4408 includes two open-drain outputs to report regulator status. The NPOR circuit monitors all regulator outputs for underand overvoltage (1V25/FBadj, 3V3, V5, V5P), the watchdog timer output (WDFAULT), and the thermal monitor (TSD). The POK5V circuit monitors the V5 and V5P output for undervoltage. The NPOR and POK5V block diagrams are shown in Figure 15. The MODE input pin modifies the NPOR circuit to raise or lower the 5V undervoltage thresholds. If the MODE pin is low, the undervoltage thresholds are relatively high, at VV5(UV,L1). If the MODE pin is high, the undervoltage thresholds are set much lower, at VV5(UV,L2). The MODE pin does not influence the POK5V circuit. The POK5V undervoltage threshold is always at VV5(POK,L). The MODE input is shown in Figure 15. Timing diagrams of the MODE pin functionality is shown in Figure 16 and Figure 17. There is a delay from the time all regulator voltages have risen above their undervoltage thresholds to the rising edge of NPOR, tdNPOR(ON). This delay allows the microcontroller or DSP plenty of time to fully power-up and complete its initialization routines. The NPOR circuit also incorporates a delay, tdOV, between the instant any regulator output exceeds its overvoltage threshold and when NPOR transitions low. There is minimal NPOR delay if any fault, other than overvoltage, occurs that requires NPOR to transition low. There are no significant delays in the POK5V output after V5 or V5P have risen above or fallen below their undervoltage thresholds. Timing diagram in this datasheet shows the functionality of NPOR and POK5V. OV/UV DETECT & DELAYS NPOR TSD WDFAULT WDADJ(FAULT) The V5P monitor is unique: if V5P is accidently connected to the battery voltage, then NPOR will bypass the normal overvoltage delay and set itself low immediately. Timing diagrams showing overvoltage possibilities for V5P are shown in Figure 21. The fault modes and their effects on NPOR and POK5V are covered in detail in Table 4. Fault Flags (FF0, FF1) The A4408 also includes two open-drain fault flags: FF0 and FF1. If a fault condition occurs and NPOR transitions low, FF0 and FF1 will be latched into one of three states to retain the type of fault: undervoltage of any regulator or charge pump (including V5P disconnect), hiccup mode (or TSD), or watchdog fault. A fourth state indicates no-fault. Fault flag functionality is summarized in Table 2 and shown in most timing diagrams in this datasheet. FF0 and FF1 are only valid if NPOR has first transitioned high. This means the A4408 must successfully complete the startup sequence and NPOR transitions high. The FF0 and FF1 latches are reset when all enable inputs are low and the soft-start capacitor voltages (SS1, SS2) have decayed below their reset thresholds. Table 2: FF0 and FF1 Fault Flag Status Conditions FF0 FF1 Type of Fault Detected When NPOR Low Low Undervoltage (Synchronous buck, 3V3, V5, V5P, or VCP), or VV5P > VV5P(DISC) Low Hi-Z VREG or Synchronous buck in hiccup mode, or thermal shutdown (TSD) Hi-Z Low Watchdog Timer (WDT) fault Hi-Z Hi-Z No fault, default condition WDSTART IBMODE UV,L1 or UV,L2 MODE UV DETECT POK5V POK,L DEGLITCH tdFILT DEGLITCH tdFILT BGFAULT 1V25/ FBadj 3.3V V5 V5P Both VREG and the synchronous buck do not enter hiccup mode for a specific number of PWM cycles. Therefore, when setting FF0 and FF1, precedence is given to detecting a hiccup condition (i.e. an undervoltage will occur before hiccup mode is set). To accomplish this, the undervoltage detection is delayed by tdFFx(UV). Figure 15: Fault Reporting Circuit Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 24 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 Table 3: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram) Regulator Control Bits (0 = OFF, 1 = ON) A4408 Status Signals EN A4408 MODE MPOR VSS1/2 LOW VREG UV 1V25 UV 3xLDO UV VREG ON 1V25 ON LDOs ON X 1 X X X X 0 0 0 0 0 1 1 1 1 0 0 0 OFF 1 0 0 1 1 1 1 0 0 STARTUP 1 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 RESET 1 0 0 0 0 0 1 1 1 RUN 0 0 0 0 0 0 1 1 1 tdEN(FILT) + tdLDO(OFF) 0 0 0 0 0 0 1 1 0 SHUTDOWN 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 Pause 0 0 1 1 1 1 0 0 0 OFF X = DON'T CARE EN = ENBAT1 + ENBAT2 + ENB VSS1/2 LOW = VSS1 < VSS1(RST) x VSS2 < VSS2(RST) 3 x LDO UV = 3V3_UV + V5_UV + V5P_UV MPOR = VVIN(UVLO) + VCC_UV + VCP_UV + BG1_UV + BG2_UV + FSET_UV/OV + TSD + SLEW_UV/OV (latched) + VCP_OV (latched) + D1MISSING (latched) + ILIM(LX1) (latched) + OV > tdOV (latched) Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 25 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Table 4: Summary of Fault Mode Operation FAULT TYPE and CONDITION A4408 RESPONSE TO FAULT NPOR POK5V V5SNR/ V5CAN/V5P LATCHED FAULT? RESET METHOD V5P Short to VBAT NPOR and POK5V transition low soon after V5P disconnect occurs. Low when V5PSENSE decays Low when V5PSENSE decays NO Check for short circuits on V5P V5, V5P, 3V3, or Synchronous Buck Overvoltage If the OV condition persists for more than tdOV, then set NPOR low and turn off all regulators. Immediately set low after tdOV Low only if V5 or V5P are too low YES Check for short circuits then cycle EN or VIN V5 or V5P Undervoltage Closed-loop control will try to raise the voltage, but may be constrained by the foldback current limit. Low Low NO Remove the short circuit or decrease the load 3V3 or Synchronous Buck Undervoltage Closed-loop control will try to raise the voltage, but may be constrained by the foldback or pulse-bypulse current limit Low Not affected NO Remove the short circuit or decrease the load V5 or V5P Overcurrent Foldback current limit will reduce the output voltage. Low if V5 or V5P are too low Low if V5 or V5P are too low NO Remove the short circuit or decrease the load 3V3 Overcurrent Foldback current limit will reduce the output voltage. Low if V3V3 < V3V3(UV,L) Not affected NO Remove the short circuit or decrease the load 1V25/FBadj pin open circuit (Synchronous buck output set to 1.25V, i.e. no FB divider) The 1V25/FBadj pin will be pulled high by an internal current source; COMP2 will respond by going low; LX2 will operate at zero cycle; and the synchronous buck output 0V. Low High NO Repair the open circuit, check the 1V25 circuitry Synchronous Buck Output Shorted to Ground, VSS2 < VHIC2(EN), V1V25 < 450mV Continues to PWM, but turns off LX2 when the highside MOSFET current exceeds ILIM2. Low Not affected NO Remove the short circuit Synchronous Buck Overcurrent VSS2 > VHIC2(EN), V1V25/FBadj < 450mV Enters hiccup mode after 30 OCP faults. Low Not affected NO Decrease the load Synchronous Buck Overcurrent VSS2 > VHIC2(EN), V1V25/FBadj > 450mV Enters hiccup mode after 120 OCP faults. Low if V1V25/FBadj < V1V25(UV,L) Not affected NO Decrease the load VREG Pin Open Circuit VVREG will decay to 0V; LX1 will switch at maximum duty cycle so the voltage on the output capacitors will be very close to VVIN. Low if 3V3, 1V25/ FBadj, V5, or V5P are too low Low if V5 or V5P are too low NO Connect the VREG pin VREG Overcurrent VVREG < 1.3V, VCOMP1 = VEA1(VO,MAX) Enters hiccup mode after 30 OCP faults. Low Low NO Decrease the load VREG Overcurrent VVREG > 1.3V, VCOMP1 = VEA1(VO,MAX) Enters hiccup mode after 120 OCP faults. Low if 3V3, 1V25/ FBadj, V5, or V5P are too low Low if V5 or V5P are too low NO Decrease the load VREG Overvoltage VVREG > VREG(OV,H) Temporarily stop PWM switching of LX1. High High NO None VREG Asynchronous Diode (D1) Missing Results in an MPOR after 1 detection, so all regulators are shut off. Low if 3V3, 1V25/ FBadj, V5, or V5P are too low Low if V5 or V5P are too low YES Populate D1 then cycle EN or VIN Continued on next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 26 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Table 4: Summary of Fault Mode Operation (continued) FAULT TYPE and CONDITION A4408 RESPONSE TO FAULT NPOR POK5V V5SNR/ V5CAN/V5P LATCHED FAULT? RESET METHOD Asynchronous Diode (D1) Short-Circuited or LX1 Shorted to Ground Results in an MPOR after 2 detections of the highside MOSFET current exceeding ILIM(LX1), so all regulators are off. Low if 3V3, 1V25/ FBadj, V5, or V5P are too low Low if V5 or V5P are too low YES Remove the short, then cycle EN or VIN Slew Pin Open Circuit (SLEW_OV) Results in an MPOR, so all regulators are off. Low Low YES Connect SLEW pin then cycle EN or VIN Slew Pin Shorted to Ground (SLEW_UV) Results in an MPOR, so all regulators are off. Low Low YES Remove the short, then cycle EN or VIN FSET/SYNC Pin Shorted to Ground or Open Circuit LX1 operates at a default oscillator frequency of 1MHz; VREG achieves 5.35V; boost function is disabled; synchronous buck and LDOs remain disabled. Low Low NO Remove short circuit, connect the pin, or populate RFSET Charge Pump (VCP) Overvoltage Results in an MPOR, so all regulators are off. Low Low YES Check VCP/CP1/ CP2, then cycle EN or VIN Charge Pump (VCP) Undervoltage Results in an MPOR, so all regulators are off. Low Low NO Check VCP/CP1/ CP2 VCP Pin Open Circuit Results in VCP_UV and an MPOR, so all regulators are off. Low Low NO Connect the VCP pin or populate CCP VCP Pin Shorted to Sround Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in MPOR, so all regulators are off. Low Low NO Remove the short circuit and replace the A4408 CP1 or CP2 Pin Open Circuit Results in VCP_UV and an MPOR, so all regulators are off. Low Low NO Connect the CP1 or CP2 pins CP1 Pin Shorted to Ground Results in VCP_UV and an MPOR, so all regulators are off. Low Low NO Remove the short circuit CP2 Pin Shorted to Ground Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in MPOR so all regulators are off. Low Low NO Remove the short circuit and replace the A4408 BGVREF or BGFAULT Undervoltage Results in an MPOR, so all regulators are off. Low Low NO Raise VIN or wait for BGs to power up BGVREF or BGFAULT Overvoltage If BGVREF is too high, all regulators will appear to be OV (because BGFAULT is good). If BGFAULT is too high, all regulators will appear to be UV (because BGVREF is good). Low Low NO Replace the A4408 VCC Undervoltage or Shorted to Ground Results in an MPOR, so all regulators are off. Low Low NO Raise VIN or remove short from VCC pin WDADJ pin Shorted to Ground or Open Circuit A WDADJ fault sets the NPOR output low. The remainder of the A4408 operates normally. Low High NO Remove the short circuit or connect the pin Thermal Shutdown Results in an MPOR, so all regulators are off. Low Low NO Let the A4408 cool Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 27 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 TIMING DIAGRAMS (Not to Scale) 12 V VIN (Pin) ~5 V ~4 V VVIN(STOP) VV5(POK,L) VV5(UV,L1) V5 VV5P(POK,L) VV5P(UV,L1) V5P VV5P > VV5P(POK,H) and VV5 > VV5(POK,H) POK5V VV5P < VV5P(POK,L) or VV5 < VV5(POK,L) NPOR VV5P < VV5P(UV,L1) or VV5 < VV5(UV,L1) WDSTART tdFILT tdFILT VV5P > VV5P(UV,H) and VV5 > VV5(UV,H) tdFILT tdFILT + tdNPOR(ON) NPOR forces WDSTART LOW tdWD(START) FF0 Grey, lined areas indicate Hi-Z FF1 NPOR latches FF0 and FF1 after tdFFx(UV) tdFFx(UV) Figure 16: Low VIN Operation with MODE = Low, and ENB or ENBAT High Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 28 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 12 V VIN (Pin) ~5 V ~4 V VVIN(STOP) VV5(POK,L) VV5(UV,L2) V5 VV5P(POK,L) V5P VV5P(UV,L2) POK5V VV5P < VV5P(POK,L) or VV5 < VV5(POK,L) VV5P > VV5P(POK,H) and VV5 > VV5(POK,H) tdFILT tdFILT NPOR WDSTART Grey, lined areas indicate Hi-Z FF0 FF1 Figure 17: Low VIN Operation with MODE = High, and ENB or ENBAT High Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 29 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 EN ENB and ENBAT1 and ENBAT2 = 1 SHUTDOWN SEQUENCE MUST FINISH BEFORE RESTART IS ACKNOWLEDGED ENB or ENBAT1 or ENBAT2 = 0 tdEN(FILT) t < tdEN(FILT) SS1 VSS1(RST) VSS1(OFFS) COMP1 tdLDO(OFF) VPWM1(OFFS) fOSC / 8 fOSC / 4 fOSC / 2 f OSC LX1 tSS1 VREG 5.35 V VVREG(UV,H) tSS1(DLY) SS2 VSS2(OFFS) COMP2 LX2 VSS2(RST) VPWM2(OFFS) fOSC / 4 fOSC / 2 f OSC tSS2 1V25 tSS2(DLY) V1V25(UV,H) V3V3(UV,H) VV5P(UV,H) VV5P(POK,H) t < tdFILT VV5(UV,H) VV5P(POK,H) t < tdFILT V5 POK5V NPOR WDSTART Indicates Hi-Z state VV5P > VV5P(POK,H) and VV5 > VV5(POK,H) VV5P(UV,Lx) VV5P(POK,L) VV5(UV,Lx) VV5P(POK,L) VV5P < VV5P(POK,L) or VV5 < VV5(POK,L) tdFILT tdFILT tdFILT + tdNPOR(ON) VV5P > VV5P(UV,H) and VV5 > VV5(UV,H) and V3V3 > V 3V3(UV,H) and V1V25 > V1V25(UV,H) V3V3 < V3V3(UV,L) and VV5P < VV5P(UV,Lx) and VV5 < VV5(UV,Lx) V3V3(UV,L) 3V3 V5P 1V25, 3V3, V5P, V5 are all UV V1V25(UV,L) tdWD(START) tdNPOR(OFF) EN forces NPOR LOW NPOR forces WDSTART LOW FF0 FF1 CLEAR FF0/FF1 EN=0, VSS1RST=1, VSS2RST=1 Figure 18: Startup and Shutdown due to EN while VVIN = 12VDC Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 30 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 EN ENB or ENBAT1 or ENBAT2 = 1 ENB and ENBAT1 and ENBAT2 = 0 12 V VIN ~5.45 V @ 25C VVIN > VVIN(START) VVIN(START) VVIN < VVIN(STOP) SS1 Discharged by RPDSS1 VSS1(OFFS) COMP1 VSS1 < VSS1(RST) and VSS2 < VSS2(RST) VPWM1(OFFS) fOSC / 8 fOSC / 4 fOSC / 2 100% Duty Cycle f OSC LX1 f OSC tSS1 VREG VVREG(UV,H) tSS1(DLY) SS2 COMP2 LX2 VSS2 < VSS2(RST) Discharged by RPDSS2 VSS2(OFFS) VPWM2(OFFS) fOSC / 4 fOSC / 2 f OSC f OSC tSS2 1V25 3V3 V5 V5P POK5V tSS2(DLY) V1V25(UV,H) V3V3(UV,H) VV5(UV,H) VV5(POK,H) VV5(POK,L) EN=0, VSS1RST=1, VSS2RST=1 VV5P < VV5P(POK,L) or VV5 < VV5(POK,L) VV5P(UV,H) VV5P(POK,H) tdFILT tdFILT + tdNPOR(ON) VV5P > VV5P(UV,H) and VV5 > VV5(UV,H) and V3V3 > V3V3(UV,H) and V1V25 > V1V25(UV,H) VV5(UV,Lx) VV5P < VV5P(UV,Lx) or VV5 < VV5(Uv,Lx) or V3V3 < VV3V(Uv,Lx) or V1V25 < V1V25(UV,Lx) VV5P > VV5P(POK,H) and VV5 > VV5(POK,H) NPOR WDSTART V3V3(UV,L) tdWD(START) tdFILT tdFILT NPOR forces WDSTART LOW FF0 FF1 CLEAR FF0/FF1 tdFFx(UV) Figure 19: Startup and Dropout/Shutdown due to VVIN while EN = 1 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 31 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 A LATCHED FAULT CAN BE RESET BY EN LOW IF: VSS1 < VSS1(RST) and VSS2 < VSS2(RST) EN SS1 ENB and ENBAT1 and ENBAT2 = 0 VSS1(OFFS) VSS1(RST) VPWM1(OFFS) COMP1 LX1 f OSC f OSC VVREG(OV,H) VREG f OSC VVREG(OV,L) OV of VREG does not shutdown the A4408, it temporarily suspends LX1 switching SS2 VSS1 < VSS1(RST) and VSS2 < VSS2(RST) VSS2(RST) COMP2 VPWM2(OFFS) f OSC LX2 1V25 VSS2(OFFS) f OSC V1V25(UV,H) V1V25(UV,L) t < tdOV t < tdFILT V3V3(OV,H) 3V3 V3V3(UV,H) t < tdOV t < tdFILT V5 t < tdFILT t > tdOV VV5(UV,H) VV5(POK,L) V3V3 OV IS SHOWN, IDENTICAL CASES IF: VV5 > VV5(OV,H) or V1V25 > V1V25(OV,H) t < tdOV VV5P(UV,H) t < tdFILT t < tdOV V5P POK5V NPOR WDSTART VV5P < VV5P(POK,L) or VV5 < VV5(POK,L) Any OV with t > tdOV forces NPOR LOW NPOR forces WDSTART LOW VV5P > VV5P(POK,H) and VV5 > VV5(POK,H) tdFILT VV5P > VV5P(UV,H) and VV5 > V V5(UV,H) and V3V3 > V3V3(UV,H) and V1V25 > V1V25(UV,H) tdFILT tdFILT or tdNPOR(ON) tdWD(START) FF0 FF1 Figure 20: Overvoltage of VREG, Synchronous Buck, 3V3, or V5 with Reset by EN Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 32 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 SS1 SS1 SS1 COMP1 COMP1 COMP1 LX1 OV forces LX1 to stop switching f OSC LX1 f OSC LX1 VREG VREG VREG SS2 SS2 SS2 COMP2 COMP2 COMP2 LX2 OV forces LX2 to stop switching f OSC LX2 f OSC LX2 1V25 1V25 1V25 3V3 3V3 3V3 V5 V5 V5 VVBAT VVBAT VV5P(DISC) V5P V5P t = tdOV VV5P(DISC) VV5P(OV,H) t = tdOV V5P POK5V POK5V after tdFILT and VV5 < VV5(POK,L) POK5V POK5V NPOR NPOR set LOW due to any OV NPOR NPOR WDSTART NPOR forces WDSTART LOW WDSTART WDSTART FF0 FF0 FF0 FF1 FF1 FF1 CASE 1: VV5P(OV,H) < VV5P < VV5P(DISC) and t > tdOV f OSC VVBAT VV5P(DISC) VV5P(OV,H) VV5P(OV,L) VV5P(OV,H) f OSC CASE 2: VV5P > VV5P(OV,H) but t < tdOV POK5V after tdFILT and VV5P(SENSE) < VV5P(POK,L) NPOR after tdFILT and VV5P(SENSE) < VV5P(UV,Lx) NPOR forces WDSTART LOW CASE 3: VV5P > VV5P(DISC) Figure 21: Possible Overvoltage Cases for V5P Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 33 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 UV of V5 or V5P VREG 1.3 VTYP SS1 VSS1(RST) VSS1(OFFS) EN_HIC1 HIC1 OCP1 tHIC1(OCP) tHIC1(OCP) tHIC1(OCP) VEA(VO,MAX) , OCL1 = 1 COMP1 VPWM1(OFFS) fOSC/4 LX1 fOSC fOSC/8 NPOR FF0 To detect Hiccup mode, UV sensing must be delayed by tdFFx(UV) FF1 tdFFx(UV) VREG shorted to ground Figure 22: Hiccup Mode Operation when VREG is shorted to GND Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 34 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 1V25/ FBadj 450 mVTYP VHIC2(EN) SS2 VSS2(RST) VSS2(OFFS) EN_HIC2 HIC2 OCP2 tHIC2(OCP) tHIC2(OCP) tHIC2(OCP) VEA2(VO,MAX) , OCL2=1 COMP2 VPWM2(OFFS) fOSC/4 LX2 fOSC fOSC/8 NPOR FF0 To detect Hiccup mode, UV sensing must be delayed by tdFFx(UV) FF1 tdFFx(UV) Synchronous buck output shorted to ground Figure 23: Hiccup Mode Operation when the Synchronous Buck output is shorted to GND Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 35 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 NPOR tWD(TO,SLOW) set to 20 ms (4 ms) t < 16 ms WDSTART tdWD(START) t > 24 ms t < 16 ms CLKIN t WD(FAULT) WDFAULT FF0 FF1 NPOR latches FF0 and FF1 Figure 24: Typical Watchdog Timer Operation WD will not indicate a fault if the rising edges of CLKIN occur within 16ms of each other. WD will indicate a fault if the rising edges of CLKIN occur more than 24ms apart. STARTUP NPOR WDSTART tdFILT + tdNPOR(ON) tdWD(START) CLKIN WDFAULT tdWD(START) tdWD(START) tWD(TO,SLOW) tWD(TO,SLOW) tWD(TO,SLOW) tdWD(START) tdNPOR(ON) All Regs_OK t WD(FAULT) t WD(FAULT) t WD(FAULT) tdWD(START) + tWD(TO,SLOW) + tWD(FAULT) FF0 FF1 NPOR latches FF0 and FF1 Figure 25: Watchdog Timer Operation Showing Start Delay and Missing CLKIN After startup, if CLKIN is stuck low (or high), NPOR will periodically pulse LOW for 2ms. The time between NPOR fault indications will be tdWD(START) + tWD(TO,SLOW) + tWD(FAULT). Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 36 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 DESIGN AND COMPONENT SELECTION PWM Switching Frequency (RFSET) When the PWM switching frequency is chosen, the designer should be aware of the minimum controllable on-time, tON(MIN), of the A4408. If the system's required on-time is less than the A4408 minimum controllable on-time, then switch node jitter will occur and the output voltage will have increased ripple or oscillations. The PWM switching frequency should be calculated using equation 1, where tON(MIN) is the minimum controllable on-time of the A4408 (85 nsTYP) and VVIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). fOSC < 5.35 V tON(MIN) x VVIN(MAX) Charge Pump Capacitors The charge pump requires two capacitors: a 1 F connected from pin VCP to VIN, and a 0.22 F connected between pins CP1 and CP2. These capacitors should be high-quality ceramic capacitors, such as X5R or X7R, with voltage ratings of at least 16 V. Pre-Regulator Output Inductor (L1) For peak current-mode control, it is well known that the system will become unstable when the duty cycle is above 50% without adequate Slope Compensation (SE). However, the slope compensation in the A4408 is a fixed value based on the oscillator frequency (fOSC). Therefore, it's important to calculate an inductor value so the falling slope of the inductor current (SF) will work well with the A4408 fixed slope compensation. Equation 2 can be used to calculate a range of values for the output inductor for the pre-regulator. In equation 2, slope compensation (SE1) is a function of the switching frequency (fOSC) according to equation 3, and VF is the asynchronous diodes forward voltage. SE1 = 7.188x10 x fOSC + 0.0425 -4 If equation 2 yields an inductor value that is not a standard value, then the next highest standard value should be used. The final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. The inductor should not saturate given the peak operating current according to equation 4. In equation 4, VVIN(MAX) is the maximum continuous input voltage, such as 18 V, and VF is the asynchronous diodes forward voltage. IPEAK1 = 5.1 A - (1) If the A4408 synchronization function is used, then the base oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency according to equation 1. (5.25 V + VF ) (5.45 V + VF ) L1 SE1 SE1 2 When using equations 2 and 3, fOSC is in kHz, SE1 is in A/s, and L1 will be in H. (2) (4) After an inductor is chosen, it should be tested during output short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the inductor or the regulator are not damaged when the output is shorted to ground at maximum continuous input voltage and the highest expected ambient temperature. The inductor ripple current can be calculated using equation 5. IL1 = (VVIN - 5.35 V) x 5.35 V fOSC x L1 x VVIN (5) Pre-Regulator Output Capacitance The output capacitors filter the output voltage to provide an acceptable level of ripple voltage, and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. Within the first few PWM cycles, the deviation of VVREG will depend mainly on the magnitude of the load step (ILOAD1), the value of the output inductor (L1), the output capacitance (COUT), and the maximum duty cycle of the pre-regulator (DMAX1). Equations 6 and 7 can be used to calculate a minimum output capacitance to maintain VVREG within 1% of its target for a 750mA load step at only 6 VVIN. L1 x (750 mA) 2 x (6.0 V - 5.25 V) x (0.01 x 5.25 V) x DMAX1 2 COUT(VREG) DMAX = (3) SE1 x (5.25 V + VF ) 1.1 x fOSC x (VVIN(MAX)+ VF ) ( 1 fOSC ) -80 ns x fOSC (6) (7) After the load transient occurs, the output voltage will deviate Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 37 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 from its nominal value until the error amplifier can bring the output voltage back to its nominal value. The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. Selection of the compensation components (RZ1, CZ1, CP1) are discussed in more detail in the Pre-Regulator Compensation section of this datasheet. The output voltage ripple (VVREG) is a function of the output capacitors parameters: COUT, ESRCo, and ESLCo according to equation 8. VVREG The type of output capacitors will determine which terms of equation 8 are dominant. For the A4408 and automotive environments, only ceramic capacitors are recommended. The ESRCO and ESLCO of ceramic capacitors are virtually zero, so the peakto-peak output voltage ripple of VVREG will be dominated by the third term of equation 8. (9) Pre-Regulator Ceramic Input Capacitance The ceramic input capacitors must limit the voltage ripple at the VIN pin to a relatively low voltage during maximum load. Equation 10 can be used to calculate the minimum input capacitance, CIN IVREG(MAX) x 0.25 0.90 x fOSC x 50 mVPP (10) where IVREG(MAX) is the maximum current from the pre-regulator, IVREG(MAX) = IV5 + IV5P + I3V3 + The highest peak current in the asynchronous diode (D1) occurs during overload and is limited by the A4408. Equation 4 can be used to calculate this current. The highest average current in the asynchronous diode occurs when VVIN is at its maximum, DBOOST = 0%, and DBUCK = minimum (10%), IAVG = (1 - DBUCK) x IVREG(MAX) = 0.9 x IVREG(MAX) VVIN - VVREG IL (8) = IL x ESRCo + x ESLCo + LO 8 x fOSC x COUT IL VVREG(PP) = 8 x fOSC x COUT Pre-Regulator Asynchronous Diode (D1) VOUT(ADJ)x IOUT(ADJ) + 20 mA (11) 5.25 V x 80% A good design should consider the DC bias effect on a ceramic capacitor--as the applied voltage approaches the rated value, the capacitance value decreases. The X7R-type capacitors should be the primary choices due to their stability versus both DC bias and temperature. For all ceramic capacitors, the DC bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size (i.e. 1206/16 V or 1210/50 V). Also, for improved EMI/EMC performance, it is recommended that two small capacitors be placed as close as physically possible to the VIN pins to address frequencies above 10 MHz. For example, a 0.1 F/X7R/0603 and a 220 pF/COG/0402 capacitor will address frequencies up to 20 MHz and 200 MHz, respectively. (12) where IVREG(MAX) is calculated using equation 11. Pre-Regulator Boost MOSFET (Q1) The maximum RMS current in the boost MOSFET (Q1) occurs when VVIN is very low and the boost operates at its maximum duty cycle, IQ1(RMS) = DMAX(BST) x [(I PEAK1 - IL1 2 ) + I12 ] 2 L1 (13) where IPEAK1 and IL1 are derived using equations 4 and 5, respectively, and DMAX(BST) is identified in the Electrical Characteristics table. The boost MOSFET should have a total gate charge of less than 14 nC at a VGS of 5 V. The VDS rating of the boost MOSFET should be at least 20 V. Several recommended part numbers are shown in the Functional Block Diagram / Typical Schematic. Pre-Regulator Boost Diode (D2) In buck mode, the maximum average current in this diode is simply the output current, calculated with equation 11. However, in buckboost mode, the peak currents in this diode may increase significantly. The A4408 will limit the current to the value calculated by equation 4. Pre-Regulator Soft-Start and Hiccup Timing (CSS1) The soft-start time of the pre-regulator is determined by the value of the capacitance at the soft-start pin (CSS1). If the A4408 is starting into a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. This occurs because the total of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors (IC(OUT) = COUT x VOUT / tSS) is higher than the pulse-by-pulse current threshold, as shown in Figure 26. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 38 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 Pre-Regulator Compensation (RZ1, CZ1, CP1) } ILIM ILOAD Although the A4408 can operate in buck-boost mode at low input voltages, it still can be considered a buck converter when examining the control loop. The following equations can be used to calculate the compensation components. Output Capacitor Current, IC(OUT) tSS Figure 26: Output Current (ICO) During Startup To avoid prematurely triggering hiccup mode, the soft-start time (tSS1) should be calculated using equation 14, tSS1 = 5.35 V x COUT IC(OUT) (14) where COUT is the output capacitance, and IC(OUT) is the amount of current allowed to charge the output capacitance during softstart (recommend 0.1 A < IC(OUT) < 0.3 A). Higher values of IC(OUT) result in faster soft-start time, and lower values of IC,OUT ensure that hiccup mode is not falsely triggered. Allegro recommends starting the design with an IC(OUT) of 0.1 A and increasing it only if the soft-start time is too slow. Then, CSS1 can be calculated based on equation 15: ISS1(SU) x tSS1 CSS1 0.8 V (15) If a non-standard capacitor value for CSS1 is calculated, the next higher value should be used. The voltage at the soft-start pin will start from 0 V and will be charged by the soft-start current (ISS1(SU)). However, PWM switching will not begin immediately because the voltage at the soft-start pin must rise above the soft-start offset voltage (VSS1(OFFS)). The soft-start delay (tSS1(DLY)) can be calculated using equation 16. tSS1(DLY) = CSS1 x VSS1(OFFS) ISS1(SU) (16) When the A4408 is in hiccup mode, the soft-start capacitor sets the hiccup period. During a startup attempt, the soft-start pin charges the soft-start capacitor with ISS1(SU) and discharges the same capacitor with ISS1(HIC) between startup attempts. First, select the target crossover frequency for the final system. While switching at over 2 MHz, the crossover is governed by the required phase margin. Since a type II compensation scheme is used, the system is limited to the amount of phase that can be added. Hence, a crossover frequency (fC1) in the region of 35kHz is selected. The total system phase will drop off at crossover frequencies about 100kHz. The RZ1 calculation is based on the gain required to set the crossover frequency and can be calculated by equation 17. 13.38 x x fC1 x COUT RZ1 = (17) gmPOWER1 x gmEA1 The series capacitor (CZ1) along with the resistor (RZ1) set the location of the compensation zero. This zero should be placed no lower than 1/4 of the crossover frequency and should be kept to minimum value. Equation 18 can be used to estimate this capacitor value. CZ1 > 4 2 x RZ1 x fC1 (18) Allegro recommends adding a small capacitor (CP1) in parallel with the series combination of RZ1/CZ1 to roll off the error amps gain at high frequency. This capacitor usually helps reduce LX1 pulse-width jitter, but if too large, it will also decrease the loop's phase margin. Allegro recommends using this capacitor to set a pole at approximately 5x the loop's crossover frequency (fC1), as shown in equation 19. If a non-standard capacitor value results, the next higher available value should be used. CP1 1 2 x RZ1 x 5 x fC1 (19) An Excel-based design tool is available from Allegro that accepts customer specifications and recommends values for both the power and compensation components. The pre-regulator bode plot in Figure 27 was generated with this tool. The bandwidth of this system (fC1) is 30kHz, the phase margin (PM1) is 61degrees, and the gain margin (GM1) is 25dB. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 39 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 The ratio of the feedback resistors can be calculated based on equation 20. RFB1 VOUT(ADJ) -1 = (20) R 1.25 V FB2 ( ) Synchronous Buck Output Inductor (L2) Equation 21 can be used to calculate a range of values for the output inductor for the synchronous buck regulator. Slope compensation (SE2) can be calculated using equation 22. VOUT(ADJ) VOUT(ADJ) L2 (21) SE2 2 x SE2 SE2 = 3.063x10-4x fOSC + 0.0175 (22) When working with equations 21 and 22, fOSC is in kHz, SE2 is in A/s, and L2 will be in H. Figure 27: Bode Plot for the Pre-Regulator RZ1 = 22.1 k, CZ1 = 1.5 nF, CP1 = 47 pF Lo = 4.7 H, Co = 5 x 10 F/16 V/1206 Synchronous Buck Component Selection Similar design methods can be used for the synchronous buck; however, the complexity of variable input voltage and boost operation are removed. Setting the Output Voltage (RFB1 and RFB2) The A4408 was optimized to deliver 1.25V from the synchronous buck--where the output of the synchronous buck is connected directly to the FB1V25/ADJ pin. The absence of a resistor divider from VOUT to the FB1V25/ADJ pin results in robust fault conditions (i.e. if the feedback trace is open, the output of the synchronous buck will be 0V). If required, the output of the synchronous buck may be programmed from 1.25 to 3.3V. This is achieved by adding a resistor divider from its output to ground and connecting the center point to the FB1V25/ADJ pin, as shown in Figure 28. L2 VOUT(ADJ) LX2 ADJ. SYNC. BUCK REGULATOR RFB1 1V25/FBADJ RFB2 A4408 Figure 28: Setting the Synchronous Buck Output If equation 21 yields an inductor value that is not a standard value, then the next closest available value should be used. The final inductor value should allow for 10%-20% of initial tolerance and 20%-30% for inductor saturation. The inductor should not saturate given the peak current at overload according to equation 23. SE2 x VOUT(ADJ) IPEAK2 = 2.4 A - (23) 1.1 x fOSC x 5.45 V Once the inductor value is known, the ripple current can be calculated using equation 24. (5.35 V x VOUT(ADJ) )x VOUT(ADJ) IL2 = (24) fOSC x L2 x 5.35 V Synchronous Buck Output Capacitance Within the first few PWM cycles, the deviation of VOUT(ADJ) will depend mainly on the magnitude of the load step (ILOAD2), the value of the output inductor (L2), the output capacitance (COUT(ADJ)), and the maximum duty cycle of the synchronous converter (DMAX2). Equations 25 and 26 can be used to calculate a minimum output capacitance to maintain 1.25V within 1.2% of its target for a 400 mA load step. L2 x (400 mA) 2 x VOUT(ADJ) x (0.012 x 1.25V) x DMAX2 2 COUT(1V25) DMAX2 = ( 1 fOSC ) - 110 ns x fOSC (25) (26) After the load transient occurs, the output voltage will deviate from its nominal value until the error amplifier can bring the output voltage back to its nominal value. The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. Selection of the compensation components (RZ2, CZ2, CP2) are discussed in more detail in the Synchronous Buck Compensation section of this datasheet. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 40 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 Allegro recommends the use of ceramic capacitors for the synchronoous buck. The peak-to-peak voltage ripple of the synchronous buck (VOUT(ADJ,PP)) can be calculated with equation 27. For the synchronous buck, select 100 kHz for the crossover frequency (fC2) of the synchronous buck. Then, equation 28 can be used to calculate RZ2. VOUT(ADJ)x 2 x f C2 x COUT(ADJ) 1.25 V x gmPOWER2 x gmEA2 (28) The series capacitor (CZ2) along with the resistor (RZ2) set the location of the compensation zero. This zero should be placed no lower than 1/4 of the crossover frequency and should be kept to minimum value. Equation 29 can be used to estimate this capacitor value. 4 CZ2 > 2 x R Z2 x f C2 (29) Allegro recommends adding a small capacitor (CP2) in parallel with the series combination of RZ2/CZ2 to roll off the error amp gain at high frequency. This capacitor usually helps reduce LX2 pulse-width jitter, but if too large, it will also decrease the loop's phase margin. Allegro recommends using this capacitor to set a pole at approximately 8x the loop's crossover frequency (fC2), as shown in equation 30. If a non-standard capacitor value results, use the next higher available value. CP2 1 2 x R Z2 x 8 x f C2 (30) Allegro's Excel-based design tool accepts specifications for the synchronous buck and recommends values for both the power and compensation components. The synchronous buck bode plot in Figure 29 was generated with this tool. The bandwidth of this system (fC2) is 90kHz, the phase margin (PM2) is 56 degrees, and the gain margin (GM2) is 17dB. 150 135 120 40 105 90 75 20 60 45 0 30 Phase - Again, similar techniques as used with the pre-regulator can be used to compensate the synchronous buck. RZ2 = 165 (27) Synchronous Buck Compensation (RZ2, CZ2, CP2) 180 60 Gain - dB IL2 VVOUT(ADJ,PP) = 8 x fOSC x COUT(ADJ) Synchronous Buck Bode Plot 80 15 0 -20 -15 -30 -40 Gain -45 Phase -60 -60 100 1000 10000 Frequency - Hz 100000 -75 1000000 Figure 29: Bode Plot for the Sync. Buck at 1.25 VOUT RZ2 = 6.81 k, CZ2 = 1.5 nF, CP2 = 47 pF L2 = 4.7 H, COUT(ADJ) = 3 x 10 F/16 V/1206 Synchronous Buck Soft-Start and Hiccup Timing The soft-start time of the synchronous buck is determined by the value of the capacitance at the soft-start pin (CSS2). If the A4408 is starting into a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. To avoid prematurely triggering hiccup mode, the soft-start time (tSS2) should be calculated according to equation 31, tSS2 = VOUT(ADJ)x COUT(ADJ) IC(OUT) (31) where VOUT(ADJ) is the output voltage, COUT(ADJ) is the output capacitance, IC(OUT) is the amount of current allowed to charge the output capacitance during soft-start (recommend 75 mA < IC(OUT) < 150 mA). Higher values of IC(OUT) result in faster softstart times and lower values of IC(OUT) ensure that hiccup mode is not falsely triggered. For the synchronous buck, Allegro recommends starting the design with an IC(OUT) of 100 mA and increasing it only if the soft-start time is too slow. Then, CSS2 can be selected based on equation 32, CSS2 > ISS2(SU) x tSS2 1.25 V Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com (32) 41 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 If a non-standard capacitor value for CSS2 is calculated, the next larger value should be used. The voltage at the soft-start pin will start from 0 V and will be charged by the soft-start current (ISS2(SU)). However, PWM switching will not begin instantly because the voltage at the soft-start pin must rise above the soft-start offset voltage (VSS2(OFFS)). The softstart delay (tSS2(DLY)) can be calculated using equation 33, tSS2(DLY) = CSS2 x ( IV ) SS2(OFFS) SS2(SU) (33) When the A4408 is in hiccup mode, the soft-start capacitor sets the hiccup period. During a startup attempt, the soft-start pin charges the soft-start capacitor with ISS2(SU) and discharges the same capacitor with ISS1(HIC) between startup attempts. Linear Regulators The three linear regulators only require a single ceramic capacitor located near the A4408 to ensure stable operation. The range of acceptable values is shown in the Electrical Characteristics table. A 2.2 F capacitor per regulator is a good starting point. As the LDO outputs are routed throughout the PCB, it is recommended that a 0.1 F/0603 ceramic capacitor be placed as close as possible to each load point for local filtering and highfrequency noise reduction. Also, since the V5P output may be used to power remote circuitry, its load may include external wiring. The inductance of this wiring will cause LC-type ringing and negative spikes at the V5P pin if a "fast" short-to-ground occurs. It is recommended that a small Schottky diode be placed close to the V5P pin to limit the negative voltages, as shown in the Applications Schematic. The MSS1P5 (or equivalent) is a good choice. Internal Bias (VCC) The internal bias voltage should be decoupled at the VCC pin using a 1 F ceramic capacitor. It is not recommended to use this pin as a source. Signal Pins (NPOR, POK5V, FF0, FF1) The A4408 has many signal-level pins. The NPOR, POK5V, FF0, and FF1 are open-drain outputs and require external pull-up resistors. Allegro recommends sizing the external pull-up resistors so each pin will sink less than 2 mA when it is a logic Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 42 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 low. RC Snubber Calculations (RSNUBx, CSNUBx) Allegro strongly recommends including provisions for RC snubbers from LX1, LX2, and LXb to ground, as shown in the Applications Schematic. The LX1 and LX2 snubbers are required to meet automotive EMC requirements. The LXb snubber may be needed to reduce system noise when VVIN is less than 7V and the boost MOSFET (LG pin) starts switching. If the A4408 is used in buck-only mode, the LXb snubber is not necessary. A simple method to calculate the RC snubber component values is presented here. Figure 31: Typical LX1 ring frequency at turn-on without a snubber and VVIN = 12V: fRING = 192MHz After the ring frequency has been measured, the total capacitance at the LX node must be estimated. For the buck-boost preregulator, the LX1 pin (5 to 10pF), the PCB (10 to 30pF), and the asynchronous diode will all contribute to the capacitance. The asynchronous diode junction capacitance (~70pF at 12VR) is usually shown in the datasheet, as shown in Figure 32. For the synchronous buck, there is no external diode, so the total capacitance will consist of the LX2 pin, the internal synchronous MOSFET (10 to 20pF), and the PCB. Use the tip-and-barrel technique on a oscilloscope probe to measure the frequency of the turn-on ringing of the LX node without an RC snubber. The oscilloscope bandwidth must be set to its maximum, at least 200MHz. The tip-and-barrel oscilloscope probe technique is show in Figure 30. Typical LX ringing and frequency without a snubber are shown in Figure 31. Figure 32: Typical diode junction capacitance The total capacitance is calculated using equation 34, CTOT = CDIODE + CLX1_PIN + CPCB(34) Figure 30: Measuring LX ringing with tip-and-barrel = 70pF + 7.5pF + 20pF = 97.5pF Knowing the ring frequency and the total capacitance, the inductive component of the ringing can be calculated using equation 35. 1 (35) 4 x 2 x fRING2 x CTOT 1 LRING = = 7.05 nH 2 4 x x 192 MHz2 x 97.5 pF LRING = The snubber resistor is calculated using equation 36. RSNUB = RSNUB = LRING CTOT (36) 7.05 nH = 8.66 (standard value) 97.5 pF Finally, the snubber capacitor can be calculated using equa- Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 43 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 tion37. If equation 37 results in a non-standard value, use the next higher standard value. 1 (37) 2.5 x fRING x RSNUB 1 CSNUB = = 270 pF (standard) 2.5 x 192 MHz x 8.66 CSNUB = versus ambient temperature Figure 34 shows the LX waveform with the RC snubber components, 8.66 + 270pF--the 192MHz high-frequency ringing has been eliminated. It is very important to calculate the power dissipated by the resistor at the maximum steady-state (DC) input operating voltage, using equation 38. Once the maximum power dissipation is known, an adequate component considering power derating at the maximum ambient temperature can be chosen. In this example, VVIN(MAX,DC) = 18V and fOSC = 2.2MHz is used. PSNUB = 1/2 x CSNUB x VVIN2 x fSW(38) PSNUB= 1/2 x 270pF x18V2 x 2.2MHz = 96mW To support 100mW at high ambient temperature, a 1206 size resistor is needed. A 1206 size resistor can dissipate 250mW up to 100C and 100mW (40%) up to almost 135C, as shown in Figure 33. Typical Resistor Power Derating vs. Temperature 110 Figure 34: LX1 waveform including an RC snubber consisting of 8.66 + 270pF 100 Power Rating (%) 90 80 70 60 50 40 30 20 10 0 25 35 45 55 65 75 85 95 105 115 125 135 145 155 165 Ambient Temperature (C) Figure 33: Resistor power derating Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 44 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 PCB LAYOUT RECOMMENDATIONS Figure 35: Charge Pump capacitor C1 and C2. Place these components near pins 1, 2, 37, and 38. Figure 36: Recommended placement and connection of the two charge pump capacitors. 1) Start the layout by placing these components near pins 1, 2, 37, and 38. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 45 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 37: The most critical power component connections for the pre-regulator. Place these components onto the PCB layout after the charge pump capacitors. Figure 38: Recommended placement and routing of the most critical power components. 1) All of these components must be on the same layer as the A4408 (U1). 2) Routing between these components must not be interrupted by other traces. 3) Input capacitors (C34, C3, C4, C5, and C6) are located very close to the VIN pins. 4) Minimize the total loop area from C34/C6/C5 through U1 + D1. 5) The six ground vias "North" of C3 are placed so they only conduct DC current. 6) The switch node trace (LX1) is very short and just wide enough to carry about 3A. 7) High frequency currents passing through D1 are directly routed to C34, C6, C5, and C4. 8) The snubber components connect directly from the LX1 node to ground. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 46 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 39: VREG capacitors (C8-C14) and PGND connections. The VREG capacitors are the input bypass capacitors for the synchronous buck. Place these capacitors so the loop from the VREG to PGND is short and uninterrupted. Figure 40: Recommended placement of the VREG capacitors and their PGND connection. 1) Place these components on the same layer as the A4408 (U1). 2) Minimize the loop from capacitors C8-C12 to the VREG pin and PGND pin. 3) The ground connection from the capacitors to the PGND pins is uninterrupted. 4) Connect the two PGND pins to the thermal pad (i.e. ground) under the A4408. 5) Note, the LX2 trace (pins 23 and 24) uses a via to avoid interrupting the PGND trace. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 47 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 41: Recommended placement and routing of the Boost MOSFET and diode (Q1, D2), local bypass capacitors (C33, C35), and snubber components (RN3, CN3). 1) Minimize the hot loop between C33/C35 to D2 and to Q2. 2) Place a connection to the ground plane outside the hot loop (see 4 vias next to C35). 3) Include a thermal area on the bottom of the PCB (blue polygon) as thermal relief for Q1. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 48 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 42: Synchronous buck output capacitors (C16-C18), snubber (RN2, CN2), and feedback resistor divider (RFB1, RFB2). Figure 43: Recommended placement and routing of the synchronous buck inductor (L2), snubber (RN2, CN2), output capacitors (C16-C18), and feedback resistor divider (RFB1, RFB2). 1) Minimize the length and width of the LX2 trace. The width should accommodate 2.4AMAX. 2) The LX2 trace is on the bottom layer so the VREG capacitors can connect directly to PGND. 3) The snubber is on the same layer as the inductor and is grounded at PGND. 4) The feedback trace (1V25/FBADJ) is routed to the point of loading and after any filtering (B2). 5) If used, the feedback resistor divider (RFB1, RFB2) must be located near the FBADJ pin. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 49 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 44: LDO (V5P) output capacitor and negative clamp diode (C22, D5). Figure 45: Recommended placement and routing of the LDO (V5P), output capacitor (C22), and negative clamp diode (D5). 1) Place the output capacitor and negative clamp diode close to the V5P output pin. 2) Connect these two components to the ground plane near the A4408. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 50 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 46: The COMP1 (RZ1, CZ1, CP1) and COMP2 (RZ2, CZ2, CP2) components. Figure 47: Recommended placement and routing of COMP1 and COMP2 components. 1) These components can by placed on the bottom of the PCB, near pins 9 and 20. 2) Place a via very close to pins 9 and 20. 3) Keep noisy traces, like LX1 and LX2, as far away as possible from these components. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 51 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Figure 48: The gate drive from LG (pin 33) to the boost MOSFET. Figure 49: Recommended routing of the gate driver to the boost MOSFET. 1) It is best to keep the gate drive trace (LG) short and on the same layer as U1 and Q1 (i.e. no vias). 2) Here, the trace routes on the top layer and makes a short vertical run under L1. 3) The return path for the gate driver is layer #2, which is a ground plane. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 52 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 INPUT/OUTPUT STRUCTURES NPOR, POK5V, V5, 3V3, VREG, ENB, ENBAT1, ENBAT2, FF0, FF1, FBADJ, COMP1, COMP2, SS1, SS2, FSET/SYNC, TRACK, MODE, WDIN, WDENn, WDADJ, VCC, LG VCP, CP1, CP2 CP1 CP2 6.7 V PIN VCP 9V 42 V VREG, LX2 VIN, LX1, SLEW VREG SLEW VIN LX2 9V 42 V LX1 V5P GND, PGND V5P 42 V GND PGND Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 53 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 A4408 PACKAGE OUTLINE DRAWING For Reference Only - Not for Tooling Use (Reference JEDEC MO-153 BDT-1) Dimensions in millimeters NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 9.70 0.10 8 0 6.50 0.10 38 0.20 0.09 B 3.00 0.10 4.40 0.10 6.40 BSC A 0.60 0.15 1.00 REF 1 2 0.25 BSC SEATING PLANE GAUGE PLANE Branded Face C 38X 0.90 0.05 1.10 MAX 0.10 C 0.27 0.17 SEATING PLANE 0.15 0.00 0.50 BSC 0.50 0.30 38 1.70 3.00 A Terminal #1 mark area 6.5 B Exposed thermal pad (bottom surface) PCB Layout Reference View C Reference land pattern layout (reference IPC7351 SOP50P640X120-39M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 1 2 C 6.00 Figure 50: Package LV, 38-Pin eTSSOP Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 54 A4408 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1 Revision History Number Date Description - September 23, 2016 1 January 27, 2017 2 June 22, 2017 Initial release Updated Transconductance max value (page 8, 2nd condition), Pulse-by-Pulse Current Limit max value (page 9, 2nd condition), Low-Side MOSFET Leakage max value (page 10, 2nd condition), Transconductance min and max values (page 10, 1st condition), High-Side MOSFET Pulse-by-Pulse Current Limit max value (page 11). Deleted High-Side MOSFET Pulse-by-Pulse Current Limit 2nd condition (page 11). Added footnote to Boost Duty Cycle (LG Pin) 1st condition (page 8). Added Input/Output Structures (page 53). 3 September 12, 2017 Corrected Minimum and Maximum Output Voltage symbols (page 8). Added footnote to SS1 Delay and Ramp Time (page 9). Added footnote to SS2 to V1V25 Delay Time and V1V25 Ramp Time (page 11). Updated V1V25 Ramp Time typical value (page 11). Corrected tSS1(DLY) and tSS2(DLY) symbols (pages 30, 31, 39, 42). Corrected equation 32 (page 41). Corrected equation 33 (page 42). 4 September 29, 2017 Updated Thermal Characteristics table (page 2). 5 October 4, 2017 Corrected Hiccup Mode test conditions (page 9). Updated Adjustable Synchronous Buck Regulator section (page 20). Updated Bias Supply section (page 23). 6 January 23, 2018 Updated V5 Current Limit minimum value (page 12). 7 January 31, 2019 Minor editorial updates. Copyright (c)2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 55