The A4408 is power management IC that uses a buck or
buck-boost pre-regulator to efficiently convert automotive
battery voltages into a tightly regulated intermediate voltage,
complete with control, diagnostics, and protections. The
output of the pre-regulator supplies a 5 V / 115 mAMAX
tracking/protected LDO, a 3.3 V / 165 mAMAX LDO, a
5 V / 325 mAMAX LDO, and an adjustable output synchronous
buck regulator (1.25 VTYP
/ 700 mADC). Designed to supply
CAN or microprocessor power supplies in high-temperature
environments, the A4408 is ideal for underhood applications.
Enable inputs to the A4408 include a logic-level (ENB) and
two high-voltage (ENBAT1 and ENBAT2) inputs. The A4408
provides flexibility by including a TRACK pin to set the
reference of the tracking regulator to either the 5 V or the 3.3 V
output, so the A4408 can be adapted across multiple platforms
with different sensors and supply rails. The MODE pin selects
the NPOR undervoltage threshold for the V5 and V5P outputs.
Diagnostic outputs from the A4408 include a power-on-reset
output (NPOR). POK5V indicates the status of the 5 V and
5 V protected LDOs. Fault Flag 0 (FF0) and Fault Flag 1 (FF1)
retain the last fault to reset the microcontroller. Dual bandgaps,
one for regulation and one for fault checking, improve long-
term reliability of the A4408.
The A4408 contains a watchdog timer that can be programmed
to accept a wide range of clock frequencies (WDADJ). The
watchdog timer has a fixed activation delay to accommodate
processor startup. The watchdog timer has an enable/disable pin
(active low, WDENn) to facilitate initial factory programming
or field reflash programming.
Protection features include under- and overvoltage lockout on
all four CPU supply rails. In case of a shorted output, all linear
regulators feature foldback overcurrent protection. In addition,
A4408-DS, Rev. 7
MCO-0000129
• Automotive AEC-Q100 qualified
• 2.8 to 36 VIN operating range, 40 VIN maximum
• Buck or buck-boost pre-regulator (VREG)
• Adjustable PWM switching frequency: 250 kHz to 2.4 MHz
• PWM frequency can be synchronized to external clock
• Adjustable synchronous buck regulator (1.25 VNOM)
• 3.3V (3V3) and 5V (V5) internal LDO regulators with
foldback short-circuit protections
• 5V (V5P) internal tracking LDO regulator with foldback
short-circuit and short-to-battery protections
• TRACK sets either 3V3 or V5 as the reference for V5P
• Power-on reset (NPOR) with fixed delay of 15 ms
• Programmable watchdog timer with activation delay
• Active-low watchdog timer enable pin (WDENn)
• Dual bandgaps for increased reliability: BGVREF, BGFAULT
• MODE pin sets the NPOR undervoltage threshold for V5
and V5P
• Fixed POK5V undervoltage threshold for V5 and V5P
• Logic enable input (ENB) for microprocessor control
• Two ignition enable inputs (ENBAT1 and ENBAT2)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
PACKAGE: 38-Pin eTSSOP (suffix LV)
Figure 1: A4408 Simplified Block Diagram
Not to scale
A4408
5.35 V
(VREG)
Buck-Boost
Pre-Regulator
3.3 V LDO
(3V3)
with Foldback
Protection
1.25 V
(1V25)
Synchronous Buck
Regulator
Programmable
Watchdog Timer
with Activation
Delay
Dual
Bandgaps
Charge
Pump
FF0 / FF1,
UV, HIC,
TSD, WD
POK5V
Output
NPOR
Output
Tracking
Control
2:1 MUX
3V3
V5 REF
5 V LDO
(V5P)
with Tracking,
Foldback, and
Short to VBAT
Protection
5 V LDO
(V5)
with Foldback
Protection
Continued on next page...
FEATURES AND BENEFITS DESCRIPTION
APPLICATIONS
□Electronic Power Steering (EPS)
□Transmission Control Units (TCU)
□Advanced Braking Systems (ABS)
□Emissions Control Modules
□Other automotive applications
Continued on next page...
January 31, 2019
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number Package Packing [1] Lead Frame
A4408KLVTR-T 38-pin eTSSOP with thermal pad 4000 pieces per 7-inch reel 100% matte tin
[1] Contact Allegro for additional packing options.
• FF0, FF1 Fault Flags—last microcontroller RESET indicators
• Slew rate control pin helps reduce EMI/EMC
• Frequency dithering helps reduce EMI/EMC
• Overvoltage and undervoltage protection for all four CPU
supply rails
• Pin-to-pin and pin-to-ground tolerant at every pin
• Thermal shutdown protection
• −40°C to 150°C junction temperature range
the V5P output is protected from a short-to-battery event. Both
switching regulators include pulse-by-pulse current limit, hiccup
mode short-circuit protection, LX short-circuit protection, missing
asynchronous diode protection (VREG), and thermal shutdown.
The A4408 is supplied in a low profile (1.2 mm maximum height)
38-lead eTSSOP package (suffix “LV”) with exposed thermal pad.
FEATURES AND BENEFITS (continued) DESCRIPTION (continued)
ABSOLUTE MAXIMUM RATINGS [2]
Characteristic Symbol Notes Rating Unit
VIN VVIN −0.3 to 40 V
ENBAT1, ENBAT2 VENBATx
With current limiting resistor
[3] −13 to 40 V
−0.3 to 8 V
IENBATx ±75 mA
LX1, SLEW
−0.3 to VVIN + 0.3 V
t < 250 ns −1.5 V
t < 50 ns VVIN + 3 V V
VCP, CP1, CP2 −0.3 to 50 V
V5P VV5P Independent of VVIN −1 to 40 V
All other pins −0.3 to 7 V
Junction Temperature TJ−40 to 150 °C
Storage Temperature Range Tstg −40 to 150 °C
[2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may aect device reliability
[3] The higher ENBAT1 and ENBAT2 ratings (–13 V and 40 V) are measured at node “A” in the following circuit conguration:
+
-
Node “A”
≥450 Ω
VEN
ENBATx
GND
A4408
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions [4] Value Unit
Junction to Ambient Thermal Resistance RθJA eTSSOP-38 (LV) Package 30 °C/W
[4] Additional thermal information available on the Allegro website.
SPECIFICATIONS
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table of Contents
Features and Benefits 1
Description 1
Applications 1
Package 1
Simplified Block Diagram 1
Selection Guide 2
Absolute Maximum Ratings 2
Thermal Characteristics 2
Functional Block Diagram / Typical Schematic 4
Pinout Diagram and Terminal List Table 6
Electrical Characteristics 7
Buck And Buck-Boost Pre-Regulator Specifications 7
Adjustable Synchronous Buck Regulator 10
Linear Regulator (LDO) 12
Control Inputs 13
Diagnostic Outputs 15
Watchdog Timer (WDT) 18
Functional Description 19
Overview 19
Buck-Boost Pre-Regulator (VREG) 19
Adjustable Sync. Buck Regulator (1V25/ADJ) 20
Low-Dropout Linear Regulators (LDOs) 21
Tracking Input (TRACK) 21
Watchdog Timer (WDT) 21
Dual Bandgaps (BGVREG, BGFAULT) 22
Adjustable Frequency and Sync. (FSET/SYNC) 22
Frequency Dithering and LX1 Slew Rate Control 22
Enable Inputs (ENB, ENBAT) 23
Bias Supply (VCC) 23
Charge Pump (VCP, CP1, CP2) 23
Startup and Shutdown Sequences 23
Fault Reporting (NPOR, MODE, POK5V) 24
Fault Flags (FF0, FF1) 24
Startup and Shutdown Logic Table 25
Summary of Fault Mode Operation Table 26
Timing Diagrams 28
Design and Component Selection 37
PWM Switching Frequency (RFSET) 37
Charge Pump Capacitors 37
Pre-Regulator Ouput Inductor (L1) 37
Pre-Regulator Output Capacitance 37
Pre-Regulator Ceramic Input Capacitance 38
Pre-Regulator Asynchronous Diode (D1) 38
Pre-Regulator Boost MOSFET (Q1) 38
Pre-Regulator Boost Diode (D2) 38
Pre-Regulator Soft-Start and Hiccup Timing (CSS1) 38
Pre-Regulator Compensation (RZ1, CZ1, CP1) 39
Synchronous Buck Component Selection 40
Setting the Output Voltage (RFB1 and RFB2) 40
Synchronous Buck Output Inductor (L2) 40
Synchronous Buck Output Capacitance 40
Synchronous Buck Compensation (RZ2, CZ2, CP2) 41
Synchronous Buck Soft-Start and Hiccup Timing 41
Linear Regulators 42
Internal Bias (VCC) 42
Signal Pins (NPOR, POK5V, FF0, FF1) 42
RC Snubber Calculations (RSNUBx, CSNUBx) 43
PCB Layout Recommendations 45
Input/Output Structures 53
Package Outline Drawing 54
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2×4.7μF
50 V
1210
0.1μF
0603
VBAT
KEY_SW
BG
VREF
LDOs ON
A4408
VIN
VIN
FOLDBACK
V5
2.2µF
5V
LDO
3V3
2.2µF
3.3V
LDO
FOLDBACK
SYNC
(optional)
VCC
SS1
COMP1
0.47 μF
BG
VREF
75 mΩ
VREG
5×10 μF
16 V/X7R/1206
(38 – 43μF @ 5.3V)
BUCK-BOOST
PRE-REGULATOR
(VREG)
(w/ Hiccup Mode)
FB
LX1
LX1
LG
2kΩ
COMP1 and SS1 Reset
VCP UV
VREG ON
STOP PWM
VSS1
RST
VSS2RST
SS_OK
MPOR
MASTER
IC POR
(MPOR)
* indicates a
latched fault
3.3VTYP↑
2.6VTYP↓
CLK
1MHz
OSC2
WATCHDOG
TIMER WD
FAULT
ONE SHOT
2ms
TYP
WD
OSC
WDADJ
RADJ
64.9 kΩ for 20ms
WDCLK
WDIN
CLKIN WDENn = 0 or OPEN enables WD
60 kΩ
WDENn
WDENn
WDSTART CLK1MHz
ENBAT2
3.3VTYP↑
2.6VTYP↓
650 kΩ
ENBAT1
650 kΩ
ENB
60 kΩ
GND
GND
TSD
FSET/SYNC
REF
V5 3V3
2:1
MUX
01
SELECT
TRACK
STARTUP /
SHUTDOWN
SEQUENCE
FBADJ ON
LDOs ON
VREG ON
RFSET
8.66 kΩ
100 μF
50 V/ 250 mΩ
Din
SS3P4
D1
SS3P4
D2
SS3P4
L1 6.8μH, 50mΩ
IHLP2525CZER6R8M01
V5P
FOLDBACK
5V
TRACKING
LDO
Short to
VBAT
Protection
2.2µF
ADJUSTABLE
SYNCHRONOUS
BUCK
REGULATOR
(1.25V
TYP)
(w/ Hiccup Mode)
CLK @ f
OSC
LX2
PGND
PGND
LX2
COMP2
SS2
1V25/FBadj
BGVREF
COMP2 & SS2 Reset
CSS2
10 nF
RZ2
6.81 kΩ
CZ2
1.5nF
CP2
47 pF
3×10 μF
16 V/X7R/1206
(27 – 30 μF @ 1.25V)
L2 4.7μH, 95mΩ
IHLP1616BZER4R7M11
1.25 V
700m
A
1A
PEAK
SU/SD
0.1μF
50 V
D3
BAS16J
D4
MSS1P5
CP helper circuit.
These components
required if VVIN < 6V.
WDADJ,FAULT
VCP
Charge
Pump
VCP
UV/OV
1.0μF
I
ENBAT1(BIAS)
IENBAT2(BIAS)
IBTRACK
ISLEW
CLK @ f
OSC
FSET UV/OV
OSC1
CP2
CP1
0.22 μF
CSS1
22 nF
RZ1
22.1 kΩ
CZ1
1.5nF
CP1
100 pF
CVCC
1μF
D5
MSS1P5
VREG
EN
LDO
3.6V
BG1_UV
BG1 BG
VREF
BG2
BG
FAULT
BG2_UV
VIN(START)
VIN(STOP)
VIN(UVLO)
VCC
Microcontroller
Enable
0.22 µF *
* For negative V_IGN or
V_ACC transient
suppression
V_IGN3.3kΩ
7.5kΩ7.5V
MMSZ
4693T1
0.22 µF *
V_ACC
3.3kΩ
7.5kΩ7.5V
MMSZ
4693T1
Q1:
NVTFS4823N or
SQS420EN or
STL10N3LLH5
V5
325 mAMAX
3V3
165mAMAX
V5P
115mAMAX
20 kΩ
NPOR
VCC
POK5V
20 kΩ
VCC
OV/UV DETECT
& DELAYS
1V25/
FBadj
3.3V
NPOR
DE-
GLITCH
tdFILT
WDSTART
WDFAULT
WDADJ,FAULT
POK5V
BGFAULT
DE-
GLITCH
tdFILT
V5
V5P
FF1
Last RESET State
(latched)
ON/OFF RST
CLK1MHz
CLEAR Latches
SS_OK
MODE
IBMODE
UV,L1 or
UV,L2
UV DETECT
POK,L
SU/SD
NPORSET
20 kΩ
V5
(or VCC)
FF0
20 kΩ
V5+V5P+3V3+FBADJ+VCP UV
WDFAULT
HICVREG+HIC1V25+TSD
DE-
GLITCH
tdFILT
FALLING
DELAY
tdLDO(OFF)
ON/OFF SU/SD
VCC UV, VCP UV
BG1_UV, BG2_UV
*VCP OV, *D1MISSING
*SLEW UV/OV
*ILIM,LX1, *OV > tdOV
VIN(UVLO)
V5 UV
FBADJ UV
3V3 UV
MPOR
V5P UV
FBADJ ON
I1V25/FBadj
LXbLX1LX2
0603
50 V
0603
50 V
0603
50 V
1206
1/4W
0603
1/10 W
0603
1/10 W
Snubbers reduce ringing and
high-frequency noise/emissions
LXb
SLEW
RSLEW
22.1 kΩ
2.49 kΩ
[1]
Figure 2: Functional Block Diagram/Typical Schematic
Buck-Boost Mode (fOSC = 2 MHz)
[1] For optimal no-load operation.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
COMP1
LX1
LX1
LG
VREG
CP1
CP2
CP1
27 pF RZ1
13.3 kΩ
CZ1
2.7 nF
These components
required if V< 6 V
VIN
D3
BAS16J
D4
MSS1P5
0.1 µF
50 V
L1 4.7 µH, 37 mΩ
IHLP2525CZER4R7M01
3×10 µF
16 V/X7R/1206
(23–26 µF @ 5.3 V)
D1
SS2P4
5.35 VTYP
0.47 µF
A4408
Figure 3: Functional Block Diagram Modications for Buck Only Mode, fOSC = 2 MHz
fSW = 500 kHz
fSW = 2 MHz
Ambient Temperature (°C)
Percent of Maximum Load
Power Derating at VVIN = 3 to 36 V
120%
100%
80%
60%
40%
20%
10%
-40 -20 0 20 40 60 80 100 120 140 160
Figure 4: Thermal Derating for Buck-Boost Operation Down to 3 V
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Terminal List Table
Number Name Function
1 VCP Charge pump reservoir capacitor
2, 3 VIN Input voltage
4, 9 GND Ground
5 MODE Sets UV threshold for V5/V5P in NPOR logic. MODE pin does not affect
POK5V threshold. GND/low–NPORUV is set high at VV5x(UV,L1). Open/
high–NPORUV is set low at VV5x(UV,L2).
6 VCC Internal voltage regulator bypass capacitor pin
7 SS1 Soft-start programming pin for buck-boost pre-regulator
8 COMP1 Error amplifier compensation network pin for buck-boost pre-regulator
10 TRACK Tracking control: Open/High – V5P tracks 3V3, GND/Low – V5P tracks V5
11 NPOR Active-low, open-drain regulator fault detection output
12 POK5V Power OK output indicating when either V5 or V5P rail is undervoltage
(UV). POK5VUV threshold is always at VV5x(POK,L).
13, 14 FF0, FF1 Open-drain, latched Fault Flag (FFx) outputs indicate last type of fault
to reset microcontroller. FF0 and FF1 bits are only valid if NPOR has
first transitioned high. FF0 and FF1 latches are reset when all A4408
enable inputs are low and soft-start voltages have decayed below reset
thresholds. See Table 2 for more details.
15 FSET/
SYNC
Frequency setting and synchronization input
16 ENBAT1 Ignition enable input from key/switch via 1 kΩ of resistance
17 ENBAT2 Ignition enable input from key/switch via 1 kΩ of resistance
18 ENB Logic enable input from microcontroller
19 3V3 3.3 V regulator output
20 WDIN Watchdog refresh input (rising edge triggered) from microcontroller or
DSP
21 WDADJ Watchdog wait/delay time is programmed by connecting RADJ from this
pin to ground
22 WDENn Watchdog enable pin: Open/Low – WD is enabled, High – WD is disabled
23 V5P 5 V tracking/protected regulator output
24 SS2 Soft-start programming pin for adjustable synchronous buck regulator
25 1V25/
FBadj
Feedback pin for 1.25 V (or adjustable) synchronous buck regulator
26 COMP2 Error amplifier compensation network pin for 1.25 V synchronous
regulator
27, 28 PGND Power ground for adjustable synchronous regulator and its gate driver
29, 30 LX2 Switching node for adjustable synchronous buck regulator
31 V5 5 V regulator output
32 VREG Output of buck-boost and input for LDOs and adjustable synchronous
buck regulator
33 LG Boost gate drive output for buck-boost pre-regulator
34 SLEW Slew rate adjustment for rise time of LX1
35, 36 LX1 Switching node for buck-boost pre-regulator
37, 38 CP1, CP2 Charge pump capacitor connections
–PAD Exposed thermal pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PAD
VCP
VIN
VIN
GND
MODE
VCC
SS1
COMP1
GND
TRACK
NPOR
POK5V
FF0
FF1
FSET/SYNC
ENBAT1
ENBAT2
ENB
3V3
CP2
CP1
LX1
LX1
SLEW
LG
VREG
V5
LX2
LX2
PGND
PGND
COMP2
1V25/FBADJ
SS2
V5P
WDENn
WDADJ
WDIN
Package LV, 38-Pin eTSSOP
Pinout Diagram
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
GENERAL SPECIFICATIONS
Operating Input Voltage VVIN
After VVIN > VVIN(START), and VENB > 2 V or
VENBATx > 3.5 V, Buck-Boost Mode 2.8 13.5 36 V
After VVIN > VVIN(START), and VENB > 2 V or
VENBATx > 3.5 V, Buck Mode 5.7 13.5 36 V
VIN UVLO START Voltage VVIN(START) VVIN rising 5.1 5.4 5.7 V
VIN UVLO STOP Voltage VVIN(STOP) VVIN falling 2.53 2.64 2.78 V
VIN UVLO Hysteresis VVIN(HYS) VVIN(START) ‒ VVIN(STOP) – 2.7 – V
Supply Quiescent Current [1]
IQ
VVIN = 13.5 V, VENBATx ≥ 3.6 V or
VENB ≥ 2 V, VVREG = 5.6 V (no PWM) – 13 – mA
IQ(SLEEP)
VVIN = 13.5 V, VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V – – 10 µA
PWM SWITCHING FREQUENCY AND DITHERING
Oscillator Frequency fOSC
RFSET = 8.66 kΩ 1.8 2.0 2.2 MHz
RFSET = 19.1 kΩ [3] – 1.0 – MHz
RFSET = 52.3 kΩ [3] 343 400 457 kHz
PWM Switching Frequency
Foldback Thresholds fSW
VVREG > 2.7 V, VVIN rising, fOSC → fOSC/2 18.7 19.5 20.3 V
VREG > 2.7 V, VVIN falling, fOSC/2 → fOSC – 18.5 – V
VREG > 2.7 V, VVIN rising, fOSC/2 → fOSC – 7.5 – V
VREG > 2.7 V, VVIN falling, fOSC → fOSC/2 6.7 7.0 7.4 V
Frequency Dithering ΔfOSC As a percent of fOSC – ±12 – %
Dither/Slew Start Threshold VIN(DS,ON) 8.5 9.0 9.5 V
Dither/Slew Stop Threshold VIN(DS,OFF) 7.8 8.3 8.8 V
VIN Dithering/Slew Hysteresis VIN(DS,HYS) – 700 – mV
CHARGE PUMP (VCP)
Output Voltage VVCP
VVCP – VVIN, VVIN = 13.5 V, VVREG = 5.5 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
4.1 6.6 – V
VVCP – VVIN, VVIN = 6.5 V, VVREG = 5.5 V,
IVCP = 6.5 mA, VCOMP1 = VCOMP2 = 0 V,
VENB = 3.3 V
3.6 4.4 – V
Switching Frequency fSW(CP) – 65 – kHz
VCC PIN VOLTAGE
Output Voltage VVCC VVREG = 5.35 V – 4.65 – V
THERMAL PROTECTION
Thermal Shutdown Threshold [3] TTSD TJ rising 155 170 185 °C
Thermal Shutdown Hysteresis [3] THYS – 20 – °C
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR
[1]:
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
OUTPUT VOLTAGE SPECIFICATIONS
Buck Output Voltage – Regulating VVREG VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.25 A 5.25 5.35 5.45 V
PULSE-WIDTH MODULATION (PWM)
PWM Ramp Offset VPWM1OFFS VCOMP1 for 0% duty cycle – 400 – mV
LX1 Rising Slew Rate Control [3] LX1RISE
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 22.1 kΩ – 0.9 – V/ns
VVIN = 13.5 V, 10% to 90%, IVREG = 1 A,
RSLEW = 150 kΩ – 0.3 – V/ns
LX1 Falling Slew Rate [3] LX1FALL VVIN = 13.5 V, 90% to 10%, IVREG = 1 A – 1.5 – V/ns
Buck Minimum On-Time tON(MIN,BUCK) – 85 160 ns
Buck Maximum Duty Cycle DMAX(BUCK) – 100 – %
Boost Duty Cycle (LG Pin) DMIN(BST) [3] After VVIN > VVIN(START), VVIN = 6.5 V – 20 – %
DMAX(BST) After VVIN > VVIN(START), VVIN = 3.5 V 53 61 66 %
COMP1 to LX1 Current Gain gmPOWER1 – 4.5 – A/V
Slope Compensation [3] SE1
fOSC = 2 MHz 1.04 1.48 1.92 A/µs
fOSC = 400 kHz 0.22 0.33 0.44 A/µs
INTERNAL MOSFET
MOSFET On-Resistance RDSon
VVIN = 13.5 V, TJ = ‒40°C [3], IDS = 0.1 A – 50 65 mΩ
VVIN = 13.5 V, TJ = 25°C [4], IDS = 0.1 A – 75 90 mΩ
VVIN = 13.5 V, TJ = 150°C, IDS = 0.1 A – 150 180 mΩ
MOSFET Leakage IFET(LKG)
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX1 = 0 V,
VVIN = 16 V, −40°C < TJ < 85°C [4] – – 10 µA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX1 = 0 V,
VVIN = 16 V, −40°C < TJ < 150°C – 50 150 µA
ERROR AMPLIFIER
Open-Loop Voltage Gain [3] AVOL1 – 60 – dB
Transconductance gmEA1
VSS1 = 750 mV 550 750 950 µA/V
VSS1 = 500 mV 275 375 500 µA/V
Output Current IEA1 – ±75 – µA
Maximum Output Voltage VEA1VO(max) 1.3 1.7 2.1 V
Minimum Output Voltage VEA1VO(min) – – 300 mV
COMP1 Pull-Down Resistance RCOMP1
HICCUP1 = 1 or FAULT1 = 1 or VENBATx ≤ 2.2 V
and VENB ≤ 0.8 V, latched until VSS1 < VSS1(RST)
–1–kΩ
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] Specications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR (continued) [1]:
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
BOOST MOSFET (LG) GATE DRIVER
LG High Output Voltage VLG(ON) VVIN = 6 V, VVREG = 5.35 V 4.6 – 5.5 V
LG Low Output Voltage VLG(OFF) VVIN = 13.5 V, VVREG = 5.35 V – 0.2 0.4 V
LG Source Current [1] ILG(ON) VVIN = 6 V, VVREG = 5.35 V, VLG = 1 V – −300 – mA
LG Sink Current [1] ILG(OFF) VVIN = 13.5 V, VVREG = 5.35 V, VLG = 1 V – 150 – mA
SOFT-START
SS1 Offset Voltage VSS1(OFFS) VSS1 rising due to ISS1(SU) – 400 – mV
SS1 Fault/Hiccup Reset Voltage VSS1(RST)
VSS1 falling due to HICCUP1 = 1 or FAULT1 = 1
or VENBATx ≤ 2.2 V and VENB ≤ 0.8 V 140 200 275 mV
SS1 Startup (Source) Current ISS1(SU) VSS1 = 1 V, HICCUP1 = FAULT1 = 0 −10 −20 −30 µA
SS1 Hiccup (Sink) Current ISS1(HIC) VSS1 = 0.5 V, HICCUP1 = 1 5 10 15 µA
SS1 Delay Time [3] tSS1(DLY) CSS1 = 22 nF – 440 – µs
SS1 Ramp Time [3] tSS1 CSS1 = 22 nF – 880 – µs
SS1 Pull-Down Resistance RPD(SS1)
FAULT1 = 1 or IC disabled, latched until
VSS1 < VSS1(RST)
–3–kΩ
SS1 PWM Frequency Foldback fSW1(SS)
0 V < VVREG < 1.3 VTYP
, VCOMP1 = VEA1VO(max) – fOSC/8 – –
0 V < VVREG < 1.3 VTYP
, VCOMP1 < VEA1VO(max) – fOSC/4 – –
1.3 VTYP < VVREG < 2.7 VTYP – fOSC/2 – –
VVREG > 2.7 VTYP – fOSC – –
HICCUP MODE
Hiccup1 OCP PWM Counts tHIC1(OCP)
VSS1 > VHIC1(EN), VVREG < 1.3 VTYP
, VCOMP1 =
VEA1VO(max)
– 30 – PWM
cycles
VSS1 > VHIC1(EN), VVREG > 1.3 VTYP
, VCOMP1 =
VEA1VO(max)
– 120 – PWM
cycles
CURRENT PROTECTIONS
Pulse-by-Pulse Current Limit ILIM1(ton,min)
VVIN < 7.0 V, tON = tON(MIN) 4.1 4.6 5.1 A
VVIN > 7.0 V, tON = tON(MIN) 2.5 2.8 3.3 A
LX1 Short-Circuit Current Limit ILIM(LX1) Latched fault 6.0 7.0 – A
MISSING ASYNCHRONOUS DIODE (D1) PROTECTION
Detection Level VD(OPEN) −1.9 −1.5 −1.0 V
Time Filtering [3] tD(OPEN) 50 – 250 ns
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR (continued) [1]:
Valid at 3.6V < VVIN < 36 V
[2], –40°C < TA = TJ < 150°C, unless otherwise specied.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
FEEDBACK REFERENCE VOLTAGE
Feedback Voltage Accuracy V1V25/FBadj 50 mA < I1V25 < 700 mA 1.23 1.25 1.27 V
PULSE-WIDTH MODULATION (PWM)
PWM Ramp Offset VPWM2(OFFS) VCOMP2 for 0% duty cycle −350 −mV
High-Side MOSFET Minimum On-Time tON(MIN) −65 105 ns
High-Side MOSFET Minimum Off-Time tOFF(MIN)
Does not include total gate driver non-overlap
time, tNO
−100 125 ns
Gate Driver Non-Overlap Time [3] tNO −15 −ns
COMP2 to LX2 Current Gain gmPOWER2 −3.7 −A/V
Slope Compensation [3] SE2
fOSC = 2 MHz 0.45 0.63 0.81 A/μs
fOSC = 400 kHz 0.12 0.14 0.19 A/μs
INTERNAL MOSFETS
High-Side MOSFET On-Resistance RDSon(HS)
TA = 25°C [4], IDS = 100 mA −200 235 mΩ
IDS = 100 mA − − 400 mΩ
LX2 Node Rise/Fall Time [3] tR/F(LX2) VVREG = 5.5 V −12 −ns
High-Side MOSFET Leakage [2] IDSS(HS)
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 0 V,
VVREG = 5.5 V, ‒40˚C < TJ < 85˚C [4] − − 2μA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 0 V,
VVREG = 5.5 V, −40°C < TJ < 150°C −3 15 μA
Low-Side MOSFET On-Resistance RDSon(LS)
TA = 25°C [4], IDS = 100 mA −55 65 mΩ
IDS = 100 mA − − 110 mΩ
Low-Side MOSFET Leakage [2] IDSS (LS)
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 5.5 V,
‒40˚C < TJ < 85˚C [4] − − 1μA
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, VLX2 = 5.5 V,
−40°C <TJ < 150°C −8 25 μA
ERROR AMPLIFIER
Feedback Input Bias Current [2] I1V25/FBAdj
VCOMP2 = 0.8 V, VFB(ADJ) regulated so that
ICOMP2 = 0 A −–150 −350 nA
Open-Loop Voltage Gain [3] AVOL2 −60 – dB
Transconductance gmEA2
ICOMP2 = 0 μA, VSS2 > 500 mV 515 900 1350 μA/V
0 V < VSS2 < 500 mV – 250 – μA/V
Source and Sink Current IEA2 VCOMP2 = 1.5 V −±50 − μA
Maximum Output Voltage VEA2VO(max) 1.00 1.25 1.50 V
Minimum Output Voltage VEA2VO(min) – – 150 mV
COMP2 Pull-Down Resistance RCOMP2
HICCUP2 = 1 or FAULT2 = 1 or
VENBATx ≤ 2.2 V and VENB ≤ 0.8 V, latched until
VSS2 < VSS2(RST)
−1.5 − kΩ
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] Specications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – ADJUSTABLE SYNCHRONOUS BUCK REGULATOR
[1]:
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
SOFT-START
SS2 Offset Voltage VSS2(OFFS) VSS2 rising due to ISS2(SU) 120 200 270 mV
SS2 Fault/Hiccup Reset Voltage VSS2(RST)
VSS2 falling due to HICCUP2 = 1 or FAULT2 = 1
or VENBATx ≤ 2.2 V and VENB ≤ 0.8 V −100 120 mV
SS2 Startup (Source) Current ISS2(SU) VSS2 = 1 V, HICCUP2 = FAULT2 = 0 −10 −20 −30 µA
SS2 Hiccup (Sink) Current ISS2(HIC) VSS2 = 0.5 V, HICCUP2 = 1 5 10 20 µA
SS2 to V1V25 Delay Time [3] tSS2(DLY) CSS2 = 10 nF – 100 – µs
V1V25 Ramp Time [3] tSS2 CSS2 = 10 nF – 625 – µs
SS2 Pull-Down Resistance RPD(SS2)
FAULT2 = 1 or VENBATx ≤ 2.2 V and
VENB ≤ 0.8 V, latched until VSS2 < VSS2(RST)
–2–kΩ
SS2 PWM Frequency Foldback fSW2(SS)
V1V25/FBadj < 450 mVTYP – fOSC/4 – –
450 mVTYP < V1V25/FBadj < 780 mVTYP – fOSC/2 – –
V1V25/FBadj > 780 mVTYP – fOSC – –
HICCUP MODE
Hiccup2 OCP Enable Threshold VHIC2(EN) VSS2 rising – 2.3 – V
Hiccup2 OCP Counts tHIC2(OCP)
VSS2 > VHIC2(EN), V1V25/FBadj < 450 mVTYP – 30 – PWM
cycles
VSS2 > VHIC2(EN), V1V25/FBadj > 450 mVTYP – 120 – PWM
cycles
CURRENT PROTECTIONS
High-Side MOSFET Pulse-by-Pulse
Current Limit ILIM2(5%) Duty cycle = 5% 1.8 2.1 2.7 A
Low-Side MOSFET Reverse
Current Limit ILIM2(LS) – 500 – mA
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] Specications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – ADJUSTABLE SYNCHRONOUS BUCK REGULATOR
[1] (continued):
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
V5 AND V5P LINEAR REGULATORS
V5 Accuracy and Load Regulation VV5 10 mA < IV5 < 325 mA, VVREG = 5.25 V 4.9 5.0 5.1 V
V5 Output Capacitance [3] COUT(V5) 1.0 – 22 µF
V5P Accuracy and Load Regulation VV5P 10 mA < IV5P < 115 mA, VVREG = 5.25 V 4.9 5.0 5.1 V
V5P Output Capacitance [3] COUT(V5P) 1.5 2.2 4.1 µF
V5 and V5P Minimum Output
Voltage, Buck Only Mode [3]
VV5x(MIN1)
(5.5 VBAT)
VVCP = 8.60 V, TRACK = 1, IV5 = 265 mA,
IV5P = 35 mA, I3V3 = 75 mA, I1V25 = 250 mA
1) TA = 150°C, VVIN = 5.26 V, VVREG = 5.14 V
2) TA = ‒40°C [3], VVIN = 5.04 V, VVREG = 4.97 V
4.82 – – V
VV5x(MIN2)
(4.5 VBAT)
VVCP = 7.70 V, TRACK = 1, IV5 = 265 mA,
IV5P = 35 mA, I3V3 = 75 mA, I1V25 = 250 mA
1) TA = 150°C, VVIN = 4.26 V, VVREG = 4.14 V
2) TA = ‒40°C [3], VVIN = 4.04 V, VVREG = 3.97 V
3.65 – – V
V5 and V5P Minimum Output
Voltage, Buck-Boost Mode [3][4] VV5x(MIN3)
VVIN = 2.8 V, VVREG = 5.25 V, VVCP ≥ 7.5 V,
TRACK = 1, IV5 = 310 mA, IV5P = 110 mA,
I3V3 = 100 mA, I1V25 = 500 mA
4.82 4.90 – V
V5P TRACKING
V5P/3V3 Tracking Ratio VV5P ÷ V3V3 1.508 1.515 1.523 –
V5P/3V3 Tracking Accuracy TRACK3V3
3 V < V3V3 < 3.3 V, TRACK = 1,
I3V3 = IV5P = 75 mA −0.5 – +0.5 %
V5P/V5 Tracking Accuracy TRACKV5
3.5 V < VV5 < 5.0 V, TRACK = 0,
IV5P = IV5 = 75 mA −25 – +25 mV
V5P OVERCURRENT PROTECTION
V5P Current Limit [1] ILIM(V5P) VV5P = 5 V −210 −285 – mA
V5P Foldback Current [1] IFBK(V5P) VV5P = 0 V −30 −60 −90 mA
V5 OVERCURRENT PROTECTION
V5 Current Limit [1] ILIM(V5) VV5 = 5 V −350 −500 – mA
V5 Foldback Current [1] IFBK(V5) VV5 = 0 V −40 −75 −180 mA
V5P AND V5 STARTUP TIMING
V5P Startup Time [3] tSU(V5P) CV5P ≤ 2.9 µF, Load = 45 Ω ±5% (110 mA) – 175 565 µs
V5 Startup Time [3] tSU(V5) CV5 ≤ 2.9 µF, Load = 16 Ω ±5% (310 mA) – 150 530 µs
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] See B/B schematic, CP helper circuit required when VVIN < 6 V.
ELECTRICAL CHARACTERISTICS – V5 and V5P LINEAR REGULATOR (LDO) [1]:
Valid at 3.6 V
[2] < VVIN < 36 V, −40°C < TA = TJ < 150°C, unless otherwise specied.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS – 3V3 LDO and CONTROL INPUTS [1]:
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
3V3 LINEAR REGULATORS
3V3 Accuracy and Load Regulation V3V3 10 mA < I3V3 < 165 mA, VVREG = 5.25 V 3.23 3.30 3.37 V
3V3 Output Capacitance [3] COUT(3V3) 1.0 – 22 µF
3V3 Minimum Output Voltage, Buck
Only Mode [3]
V3V3(MIN1)
(5.5 VBAT)
VVCP = 8.80 V, TRACK = 1, IV5 = 265 mA,
IV5P = 35 mA, I3V3 = 75 mA, I1V25 = 250 mA
1) TA = 150°C, VVIN = 5.26 V, VVREG = 5.14 V
2) TA = ‒40°C [3], VVIN = 5.04 V, VVREG = 4.97 V
3.23 3.30 – V
V3V3(MIN2)
(4.5 VBAT)
VVCP = 6.80 V, TRACK = 1, IV5 = 265 mA,
IV5P = 35 mA, I3V3 = 75 mA, I1V25 = 250 mA
1) TA = 150°C, VVIN = 4.26 V, VVREG = 4.14 V
2) TA = ‒40°C [3], VVIN = 4.04 V, VVREG = 3.97 V
3.20 – – V
3V3 OVERCURRENT PROTECTION
3V3 Current Limit [1] ILIM(3V3) V3V3 = 3.3 V −185 −260 – mA
3V3 Foldback Current [1] IFBK(3V3) V3V3 = 0 V −15 −40 −65 mA
3V3 STARTUP TIMING
3V3 Startup Time [3] tSU(3V3) C3V3 ≤ 2.9 µF, Load = 33 Ω ±5% (100 mA) – 170 550 µs
IGNITION ENABLE (ENBAT1 AND ENBAT2) INPUTS
ENBAT1, ENBAT2 Thresholds VENBATx(H) VENBATx rising 2.9 3.3 3.5 V
VENBATx(L) VENBATx falling 2.2 2.6 2.9 V
ENBAT1, ENBAT2 Hysteresis VENBATx(HYS) VENBATx(H) – VENBATx(L) – 700 – mV
ENBAT1, ENBAT2 Bias Current [2] IENBATx(BIAS)
TJ = 25°C [4], VENBATx = 3.51 V – 28 45 µA
TJ = 150°C, VENBATx = 3.51 V – 35 55 µA
ENBAT1, ENBAT2 Resistance RENBATx VENBATx < 1.2 V – 650 – kΩ
LOGIC ENABLE (ENB) INPUT
ENB Thresholds VENB(H) VENB rising – – 2.0 V
VENB(L) VENB falling 0.8 – – V
ENB Bias Current [1] IENB(IN) VENB = 3.3 V – – 175 µA
ENB Resistance RENB VENB = 0.8 V – 60 – kΩ
ENB/ENBATX FILTER/DEGLITCH
Enable Filter/Deglitch Time tdEN(FILT) 10 15 20 µs
ENB/ENBATX SHUTDOWN DELAY
LDO Shutdown Delay tdLDO(OFF)
Measure tdLDO(OFF) from the falling edge of
ENB and ENBAT1 and ENBAT2 to time when
all LDOs begin to decay
15 50 100 µs
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] Specications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS – 3V3 LDO and CONTROL INPUTS [1] (continued):
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
TRACK AND MODE INPUTS
TRACK and MODE Thresholds VTH, VMH VTRACK or VMODE rising – – 2.0 V
VTL, VML VTRACK or VMODE falling 0.8 – – V
TRACK and MODE Bias Current [1] IBTRACK,
IBMODE
– –50 – µA
FSET/SYNC INPUT
FSET/SYNC Pin Voltage VFSET/SYNC No external SYNC signal – 800 – mV
FSET/SYNC Open Circuit
(Undercurrent) Detection Time tFSET/SYNC(UC) PWM switching disabled upon detection – 3 – µs
FSET/SYNC Short Circuit
(Overcurrent) Detection Time tFSET/SYNC(OC) PWM switching disabled upon detection – 3 – µs
Sync. Minimum Frequency fSYNC(MIN) 250 – – kHz
Sync. High Threshold VSYNC(IH) VSYNC rising – – 2.0 V
Sync. Low Threshold VSYNC(IL) VSYNC falling 0.5 – – V
Sync. Input Duty Cycle DCSYNC – – 80 %
Sync. Input Pulse Width twSYNC 200 – – ns
Sync. Input Transition Times [3] ttSYNC – 10 15 ns
SLEW INPUT
SLEW Pin Operating Voltage VSLEW – 800 – mV
SLEW Open Circuit (Undercurrent)
Detection Time tSLEW(UC) PWM latched off if open – 3 – µs
SLEW Short Circuit (Overcurrent)
Detection Time tSLEW(OC) PWM latched off if shorted – 3 – µs
SLEW Bias Current [1] ISLEW –−100 – nA
[1] For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
[4] Specications at 25°C or 85°C are guaranteed by design and characterization, not production tested.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
15
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
NPOR OV/UV PROTECTION THRESHOLDS
V5 OV Thresholds VV5(OV,H) VV5 rising 5.15 5.33 5.50 V
VV5(OV,L) VV5 falling – 5.30 – V
V5 OV Hysteresis VV5(OV,HYS) VV5(OV,H) – VV5(OV,L) 15 30 50 mV
V5 UV Thresholds
VV5(UV,H) VV5 rising, independent of the MODE pin – 4.68 – V
VV5(UV,L1) VV5 falling, VMODE = 0 V or GND 4.50 4.65 4.80 V
VV5(UV,L2) VV5 falling, VMODE = 5 V or open 3.00 3.13 3.27 V
V5P Output Disconnect Threshold VV5P(DISC) VV5P rising – 7.2 – V
V5P OV Thresholds VV5P(OV,H) VV5P rising 5.15 5.35 5.50 V
VV5P(OV,L) VV5P falling – 5.29 – V
V5P OV Hysteresis VV5P(OV,HYS) VV5P(OV,H) – VV5P(OV,L) 45 60 75 mV
V5P UV Thresholds
VV5P(UV,H) VV5 rising, independent of the MODE pin – 4.68 – V
VVP5(UV,L1) VV5P falling, VMODE = 0 V or GND 4.50 4.65 4.80 V
VV5P(UV,L2) VV5P falling, VMODE = 5 V or open 3.00 3.13 3.27 V
3V3 OV Thresholds V3V3(OV,H) V3V3 rising 3.41 3.52 3.60 V
V3V3(OV,L) V3V3 falling – 3.48 – V
3V3 OV Hysteresis V3V3(OV,HYS) V3V3(OV,H) – V3V3(OV,L) 25 35 50 mV
3V3 UV Thresholds V3V3(UV,H) V3V3 rising – 3.12 – V
V3V3(UV,L) V3V3 falling 2.97 3.07 3.17 V
3V3 UV Hysteresis V3V3(UV,HYS) V3V3(UV,H) – V3V3(UV,L) 40 50 60 mV
1V25/FBadj OV Thresholds V1V25(OV,H) V1V25/FBadj rising 1.29 1.32 1.35 V
V1V25(OV,L) V1V25/FBadj falling – 1.30 – V
1V25/FBadj OV Hysteresis V3V3(OV,HYS) V1V25(OV,H) – V1V25(OV,L) 15 22 30 mV
1V25/FBadj UV Thresholds V1V25(UV,H) V1V25 rising, triggers LDOs on – 1.20 – V
V1V25(UV,L) V1V25 falling 1.15 1.18 1.21 V
1V25/FBadj UV Hysteresis V1V25(UV,HYS) V1V25(UV,H) – V1V25(UV,L) 10 17 25 mV
[1] Negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS [1]: Valid at 3.6 V
[2] < VIN < 36 V, –40°C < TA = TJ < 150°C,
unless otherwise specied.
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
16
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Characteristic Symbol Test Conditions Min. Typ. Max. Unit
NPOR OV DELAY TIME (First silicon will shut down if an OV is detected)
Overvoltage Detection Delay tdOV
V5P, V5, 3V3, and 1V25/FBadj over voltage
detection delay time 6.40 8.00 9.60 ms
NPOR TURN-ON AND TURN-OFF DELAYS
NPOR Turn-On Delay tdNPOR(ON) 12 15 18 ms
NPOR Turn-Off Propagation Delay tdNPOR(OFF)
ENB and ENBAT1 and ENBAT2 low to NPOR
low – 15 23 µs
NPOR OUTPUT VOLTAGES
NPOR Output Low Voltage VNPOR(L)
ENB or ENBAT1 or ENBAT2 high,
VVIN ≥ 2.5 V, INPOR = 4 mA – 150 400 mV
ENB or ENBAT1 or ENBAT2 high,
VVIN = 1.5 V, INPOR = 2 mA – – 800 mV
NPOR Leakage Current [1] INPOR(LKG) VNPOR = 3.3 V – – 2 µA
NPOR AND POK5V UV FILTERING/DEGLITCH
UV Filter/Deglitch Times tdFILT
Applies to undervoltage of 3V3, 1V25/FBadj,
V5, and V5P voltages 10 15 20 µs
POK5V UV PROTECTION THRESHOLDS
V5 and V5P Rising Thresholds VV5x(POK,H)
VV5 or VV5P rising,
independent of the MODE pin – 4.68 – V
V5 and V5P Falling Thresholds VV5x(POK,L)
VV5 or VV5P falling,
independent of the MODE pin 4.50 4.65 4.80 V
POK5V OUTPUT VOLTAGES
POK5V Output Voltage VPOK5V(L)
ENB = 1 or ENBAT1 = 1 or ENBAT2 = 1,
VVIN ≥ 2.5 V, IPOK5V = 4 mA – 150 400 mV
ENB = 1 or ENBAT1 = 1, ENBAT2 = 1,
VVIN = 1.5 V, IPOK5V = 2 mA – – 800 mV
POK5V Leakage Current IPOK5V(LKG) VPOK5V = 3.3 V – – 2 µA
[1] Negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued) [1]:
Valid at 3.6 V
[2] < VIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
17
Allegro MicroSystems, LLC
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Characteristic Symbol Test Conditions Min. Typ. Max. Unit
VREG, VCP, AND BG THRESHOLDS
VREG OV Thresholds VVREG(OV,H) VVREG rising, LX1 PWM disabled 5.50 5.65 5.90 V
VVREG(OV,L) VVREG falling, LX1 PWM enabled – 5.55 – V
VREG OV Hysteresis VREG(OV,HYS) VVREG(OV,H) – VVREG(OV,L) – 100 – mV
VREG UV Thresholds VVREG(UV,H) VVREG rising, triggers rise of SS2 4.14 4.38 4.62 V
VVREG(UV,L) VVREG falling – 4.28 – V
VREG UV Hysteresis VVREG(UV,HYS) VVREG(UV,H) – VVREG(UV,L) – 100 – mV
VCP OV Thresholds VVCP(OV,H) VVCP rising, latches all regulators off 11.0 12.5 14.0 V
VCP UV Thresholds VVCP(UV,H) VVCP rising, PWM enabled – 3.2 – V
VVCP(UV,L) VVCP falling, PWM disabled – 2.8 – V
VCP UV Hysteresis VVCP(UV,HYS) VVCP(UV,H) – VVCP(UV,L) – 400 – mV
BGREF and BGFAULT UV Thresholds [3] VBGx(UV) VBGVREF or VBGFAULT rising 1.00 1.05 1.10 V
LAST MICROCONTROLLER (OR DSP) RESET STATE INDICATORS (FF0 AND FF1)
FF0, FF1 UV Detection Delay tdFFx(UV) NPOR↓ due to UV to FF0/FF1 latching 0.8 1.0 1.2 ms
FF0, FF1 Output Voltage VFFx(LO) IFFx = 4 mA – – 400 mV
FF0, FF1 Leakage Current [1] IFFx VFFx = 3.3 V – – 1 µA
[1] Negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
[3] Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued) [1]:
Valid at 3.6 V
[2] < VIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
18
Allegro MicroSystems, LLC
955 Perimeter Road
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Characteristic Symbol Test Conditions Min. Typ. Max. Unit
WD ENABLE / INPUT (WDENn)
WDENn Voltage Thresholds VWDENn(LO) VWDENn falling, WDT enabled 0.8 – – V
VWDENn(HI) VWDENn rising, WDT disabled – – 2.0 V
WDENn Input Resistance RWD(ENn) – 60 – kΩ
WDIN VOLTAGE THRESHOLDS AND CURRENT
WDIN Input Voltage Thresholds VWDIN(LO) VWDIN falling, WDADJ pulled low by RADJ 0.8 – – V
VWDIN(HI) VWDIN rising, WDADJ charging – – 2.0 V
WDIN Input Current [1] IWDIN VWDIN = 5 V −10 ±1 10 µA
WDIN TIMING SPECIFICATIONS
WDIN Duty Cycle DWDIN 20 50 80 %
Watchdog Activation Delay tdWD(START)
Default 120 140 160 ms
Metal Option 24 30 36 ms
WD PROGRAMMING (WDADJ)
WD Timeout, Slow Clock tWD(TO,SLOW)
RADJ = 32.4 kΩ 8.0 10 12 ms
RADJ = 324 kΩ 80 100 120 ms
WD ONE-SHOT TIME
WD Pulse Time after WD Fault tWD(FAULT) 1.6 2.0 2.4 ms
[1] Negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or pin (sinking).
[2] The lowest operating voltage is only valid if the conditions VVIN > VVIN(START) and VVCP – VVIN > VCP(UV,H) and VVREG > VVREG(UV,H) are satised before VVIN is reduced.
ELECTRICAL CHARACTERISTICS – WATCHDOG TIMER (WDT) [1]:
Valid at 3.6 V
[2] < VVIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specied.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
19
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Overview
The A4408 is a power management IC designed for automotive
applications. It contains a pre-regulator plus four DC post-
regulators to create the voltages necessary for typical automotive
applications such as electrical power steering and automatic
transmission control.
The pre-regulator can be configured as a buck or buck-boost
regulator. Buck-boost is required for applications that must work
at extremely low battery voltages. This pre-regulator generates
a fixed 5.35 V and can deliver up to 1 A to power the internal
or external post-regulators. These post-regulators generate the
various voltage levels for the end system.
The A4408 includes four internal post-regulators: three linear
regulators and one adjustable output synchronous buck regulator.
The synchronous buck regulator was designed to deliver
1.25 V / 700 mA but will produce higher voltages if a feedback
resistor divider is used.
Buck-Boost Pre-Regulator (VREG)
The pre-regulator incorporates an internal high-side buck switch
and a boost switch gate driver. An external freewheeling Schottky
diode and an LC filter are required to complete the buck con-
verter. By adding a MOSFET and a Schottky diode, the boost
configuration can maintain all outputs with input voltages as low
as 2.8 V. The A4408 includes a compensation pin (COMP1) and a
soft-start pin (SS1) for the pre-regulator.
The A4408 can maintain its outputs over a wide range of input
voltages and slew rates. Actual boost performance is shown in
Figure 5 and Figure 6 with voltages swinging between 2.9 and
18 V, and VVIN slew rates ranging from 0.3 to 100V/ms.
The buck-boost pre-regulator provides protection and diagnostic
functions.
1. Overvoltage protection
2. High voltage rating for load dump
3. Switch-node-to-ground short-circuit protection
4. Open freewheeling diode protection
5. Pulse-by-pulse current limit
6. Hiccup short circuit protection – lab measurement shown in
Figure 7 and detailed timing diagram shown in Figure 5
Figure 5: A4408 Buck-Boost operation at full load
VVIN slew rates ranging from 0.3 V/ms to 1.6 V/ms
Typical of an automotive START/STOP waveform
VVIN(TYP) = 12 V, VVIN(MIN) = 2.9 V, 10 ms/DIV
CH1=VIN, CH2=VREG, CH3=V5, CH4=3V3, M1=1V25, M2=V5P
Figure 6: A4408 Buck-Boost operation at full load
VVIN slew rates of 100 V/ms ‒
V5P deviates less than 0.2%
VVIN(TYP) = 12 V, VVIN(MIN) = 4 V, VVIN(MAX) = 18 V
CH1=VIN, CH2=VREG, CH3=V5, CH4=V5P, 500 µs/DIV
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
20
Allegro MicroSystems, LLC
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Figure 7: Pre-Regulator Hiccup Mode Operation when
VREG is Shorted to GND and CSS1 = 22 nF
CH1=VREG, CH2=COMP1, CH3=SS1, CH4=IL1, 1 ms/DIV
For the pre-regulator, hiccup mode is enabled when PWM
switching begins. If VVREG is less than 1.3 V, the number of
overcurrent pulses (OCP) is limited to only 30. If VVREG is
greater than 1.3 V, the number of OCP pulses is increased to 120
to accommodate the possibility of starting into a relatively high
output capacitance.
Adjustable Synchronous Buck Regulator
(1V25/ADJ)
The A4408 integrates the high-side and low-side MOSFETs
necessary for implementing an adjustable output synchro-
nous buck regulator. The synchronous buck is optimized for
1.25 VOUT
/ 700 mADC
/ 1 APEAK but can produce higher output
voltages if a feedback resistor divider is inserted between VOUT
and the 1V25/FBadj pin. The synchronous buck’s pulse-by-pulse
current limit depends on duty cycle and switching frequency, as
shown in Figure 8.
An internal current sense amplifier sources 80 to 100 µA to the
LX2 pin. At no load, this current will slowly charge the output
capacitors and raise the output voltage. Therefore, the system must
always sink at least 100 µA, or a pull-down resistor (<2.49 kΩ)
should be used as shown in the Applications Schematic.
Protection and safety functions provided by the synchronous
buck are:
1. Undervoltage detection
2. Overvoltage detection
3. Switch-node-to-ground short-circuit protection
4. Pulse-by-pulse current limit
5. Hiccup short-circuit protection; lab measurement shown in
Figure 9 and detailed timing diagram shown in Figure 23
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95
ILIM (A)
Duty Cycle (%)
Max_2MHz TYP_2MHz Min_2MHz
Max_400kHz TYP_400kHz Min_400kHz
Figure 8: Synchronous Buck Pulse-by-Pulse
Current Limit
The synchronous buck is powered by the 5.35 V pre-regulator
output. An external LC filter is required to complete the synchro-
nous buck regulator. The A4408 includes a compensation pin
(COMP2) and a soft-start pin (SS2) for the synchronous buck.
Figure 9: Synchronous Buck Hiccup Mode Operation
when 1V25 is Shorted to GND and CSS2 = 10 nF
CH1=1V25, CH2=COMP2, CH3=SS2, CH4=IL2, 500 µs/DIV
For the synchronous buck, hiccup mode is enabled when VSS2
= VHIC2(EN) (1.2 VTYP). If V1V25/FBadj is less than 450 mVTYP,
the number of overcurrent pulses (OCP) is limited to only 30.
If V1V25/FBadj is greater than 450 mVTYP, the number of OCP
pulses is increased to 120 to accommodate the possibility of
starting into a relatively high output capacitance.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
21
Allegro MicroSystems, LLC
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Low-Dropout Linear Regulators (LDOs)
The A4408 has three low-dropout linear regulators (LDOs), one
3.3 V / 165 mAMAX (3V3), one 5 V / 325 mAMAX (V5), and one
high-voltage protected 5 V / 115 mAMAX (V5P). The switching
pre-regulator efficiently regulates the battery voltage to an inter-
mediate value to power the LDOs. This pre-regulator topology
reduces LDO power dissipation and junction temperature.
All linear regulators provide the following protection features:
1. Undervoltage and overvoltage detection
2. Current limit (ILIM) with foldback short-circuit protection
(IFBK); see Figure 10
The protected 5 V regulator (V5P) includes protection against
accidental short-circuit to the battery voltage. This makes this
output most suitable for powering remote sensors or circuitry via
a wiring harness where short-to-battery is possible.
100%
IFBKmin IFBKtyp ILIMmin ILIMtyp
Ix
Vx
Figure 10: Typical LDO Foldback Characteristics
Tracking Input (TRACK)
The V5P LDO is a tracking regulator. It can be set to use either
V5 or 3V3 as its reference by setting the TRACK input pin to a
logic low or high. If the TRACK input is left unconnected, an
internal current source will set the TRACK pin to a logic high.
VREG
IBTRACK
SEL
V5 3V3
REFERENCE
5V
TRACKING
LDO
V5P
2:1
MUX
TRACK
01
Figure 11: The V5P reference is set
by the TRACK input.
Watchdog Timer (WDT)
The A4408 watchdog timer monitors the time between rising
edges of a clock (i.e. the clock period) applied to the WDIN pin.
This clock should be generated by the primary microcontroller
or DSP. A watchdog fault will occur if the time between rising
edges is longer than the time set by the resistor (RADJ) at the
watchdog programming pin (WDADJ). A watchdog fault will
pulse NPOR low for tWD(FAULT) (typically 2 ms). The watchdog
circuitry is shown in Figure 12.
WDADJ
WDIN
WDENn
WDSTART
RADJ
WDCLK
CLK
IN
WD
ENn WDFAULT
WD
OSC Window
Watchdog
Timer
Figure 12: Watchdog Timer Block Diagram
The watchdog time is programmable via the WDADJ pin accord-
ing to the following equation:
RADJ = 3.240 × tWD(TO,SLOW)
where tWD(TO,SLOW) is the longest expected clock period (in ms)
and RADJ is the external resistor value (in kΩ) needed from the
WDADJ pin to ground. A detailed watchdog timing diagram is
shown in Figure 24.
The watchdog is enabled when two conditions are met:
1. The WDENn pin is a logic low, and
2. All the regulators (1V25/FBadj, 3V3, V5, and V5P) have
been above their undervoltage thresholds for the watchdog
start delay time, tdWD(START) (140 msTYP).
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Allegro MicroSystems, LLC
955 Perimeter Road
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The watchdog start delay allows the microcontroller or DSP to
complete its initialization routines before delivering a clock to the
WDIN pin. A timing diagram documenting tdWD(START) is shown
in Figure 25.
After regulator startup, if the WDIN clock is missing (i.e. stuck
low or stuck high) for at least tdWD(START) + tWD(TO,SLOW) the
A4408 will set NPOR, reset its counters, and repeat the watchdog
startup delay. NPOR will periodically pulse low as long as no
WDIN clock is applied. A timing diagram for the missing clock
situation is shown in Figure 25.
Dual Bandgaps (BGVREF, BGFAULT)
Dual bandgaps, or references, are implemented within the
A4408. One bandgap (BGVREF) is dedicated solely to closed-loop
control of the output voltages. The second bandgap (BGFAULT)
is employed for fault monitoring functions. Having redundant
bandgaps improves reliability of the A4408.
If the reference bandgap is out of specification (BGVREF), then
the output voltages will be out of specification and the monitor-
ing bandgap will report a fault condition by setting NPOR and/or
POK5V low.
If the monitoring bandgap is out of specification (BGFAULT), then
the outputs will remain in regulation, but the monitoring circuits
will report a fault condition by setting NPOR and/or POK5V low.
The reference and monitoring bandgap circuits include two
smaller secondary bandgaps that are used to detect undervoltage
of the main bandgaps during power-up.
Adjustable Frequency and Synchronization
(FSET/SYNC)
The PWM switching frequency of the A4408 is adjustable from
250 kHz to 2.4 MHz. Connecting a resistor from the FSET/
SYNC pin to ground sets the switching frequency. An FSET
resistor with ±1% tolerance is recommended. The FSET resistor
can be calculated using the following equation:
R
=
FSET fOSC
21,693
()
– 2.215
where RFSET is in kΩ and fOSC is the desired oscillator (PWM)
frequency in kHz.
A graph of switching frequency versus FSET resistor values is
shown in Figure 13.
The PWM frequency of the A4408 may be increased or decreased
by applying a clock to the FSET/SYNC pin. The clock must sat-
isfy the voltage thresholds and timing requirements shown in the
Electrical Characteristics table.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
51015202530354045505560657075808590
PWM Switching Frequency (MHz)
RFSET (KΩ)
PWM Switching Frequency vs RFSET
Figure 13: Switching Frequency
vs. FSET Resistor Values
Frequency Dithering and LX1 Slew Rate Control
The A4408 includes two innovative techniques to help reduce
EMI/EMC for demanding automotive applications.
First, the A4408 performs pseudo-random dithering of the PWM
frequency. Dithering the PWM frequency spreads the energy
above and below the base frequency set by RFSET. A typical fixed-
frequency PWM regulator will create distinct “spikes” of energy
at fOSC, and at higher frequency multiples of fOSC. Conversely,
the A4408 spreads the spectrum around fOSC
, thus creating a
lower magnitude at any comparable frequency. Frequency dither-
ing is disabled if SYNC is used or VVIN drops below approxi-
mately 8.3 V.
Second, the A4408 includes a pin to adjust the rising slew rate of
the LX1 pin by simply changing the value of the resistor from the
SLEW pin to ground. Slower rise times of LX1 reduce ringing
and high-frequency harmonics of the regulator. The rise time may
be adjusted to be relatively long and will increase thermal dissi-
pation of the pre-regulator if set too high. Typical LX1 slew rates
are shown in Table 1.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Table 1: Typical LX1 Rising Slew Rate vs. RSLEW;
LX1 Snubber 8.66 Ω / 330 pF
RSLEW (kΩ)
LX1 Rising
Slew Rate
(V/ns)
LX1 10%-90%
Transition Time at
12 VVIN (ns)
8.66 1.06 9.1
22.1 0.90 10.7
46.4 0.79 12.1
71.5 0.65 14.8
100 0.50 19.2
121 0.38 25.2
150 0.29 33.1
Enable Inputs (ENB, ENBAT)
Two enable pins are available on the A4408. A logic high on
either of these pins enables the A4408. One enable (ENB) is
logic-level compatible for microcontroller or DSP control. The
other input (ENBAT) must be connected to the high-voltage
ignition (IGN) or accessory (ACC) switch through a relatively
low-value series resistance, 2 to 3.6 kΩ. For transient suppres-
sion, it is strongly recommended that a 0.22 to 0.47 µF capacitor
be placed after the series resistance to form a low-pass filter to
the ENBAT pin as shown in the Applications Schematic.
Bias Supply (VCC)
The bias supply (VCC) is generated by an internal linear regulator.
This supply is the first rail to start up. Most of the internal control
circuitry is powered by this supply. The bias supply includes
some unique features to ensure reliable operation of the A4408.
These features include:
1. Input voltage (VVIN) undervoltage lockout
2. Undervoltage detection
3. Short-to-ground protection
4. Operation from either VLDO3.6V or VVREG, whichever is higher
Charge Pump (VCP, CP1, CP2)
A charge pump provides the voltage necessary to drive the high-
side N-channel MOSFETs in the pre-regulator and the linear
regulators.
Two external capacitors are required for charge pump opera-
tion. During the first half of the charge pump cycle, the flying
capacitor between pins CP1 and CP2 is charged from either VVIN
or VVREG, whichever is highest. During the second half of the
charge pump cycle, the voltage on the flying capacitor charges
the VCP capacitor. For most conditions, the VVCP minus VVIN
voltage is regulated to approximately 6.5 V.
The charge pump can provide enough current to operate the
pre-regulator and the LDOs at 2.2 MHz (full load) and 125°C
ambient, provided VVIN is greater than 6 V. Optional components
D3, D4, and CP3 (refer to Figure 14) must be included if VVIN
drops below 6 V. Diode D3 should be a silicon diode rated for at
least 200 mA / 50 V with less than 50 µA of leakage current when
VR = 13 V and TA = 125°C. Diode D4 should be a 1 A Schottky
diode with a very low forward voltage (VF) rated to withstand at
least 30 V.
Required if VREG
is fully loaded and
V< 6.0 V
VIN
D3
BAS16J
D4
MSS1P5
CP3
0.1 µF/50 V
LX1
LX1
LG
CP1
CP2
CP2
0.22 µF
Figure 14: Charge pump enhancement components D3,
D4, and CP3 are required if VVIN < 6 V.
The charge pump incorporates some protection features:
1. Undervoltage lockout of PWM switching
2. Overvoltage “latched” shutdown of the A4408
Startup and Shutdown Sequences
The startup and shutdown sequences of the A4408 are fixed. If
no faults exist and ENBAT or ENB transition high, the A4408
will perform its startup routine. If ENBAT and ENB are low for
at least tdEN(FILT) + tdLDO(OFF) (typically 65 µs), the A4408 will
enter a shutdown sequence. The startup and shutdown sequences
are summarized in Table 3 and shown in timing diagrams in Fig-
ure 18 and Figure 19.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
24
Allegro MicroSystems, LLC
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Fault Reporting (NPOR, MODE, POK5V)
The A4408 includes two open-drain outputs to report regulator
status. The NPOR circuit monitors all regulator outputs for under-
and overvoltage (1V25/FBadj, 3V3, V5, V5P), the watchdog timer
output (WDFAULT), and the thermal monitor (TSD). The POK5V
circuit monitors the V5 and V5P output for undervoltage. The
NPOR and POK5V block diagrams are shown in Figure 15.
The MODE input pin modifies the NPOR circuit to raise or lower
the 5 V undervoltage thresholds. If the MODE pin is low, the
undervoltage thresholds are relatively high, at VV5(UV,L1). If the
MODE pin is high, the undervoltage thresholds are set much lower,
at VV5(UV,L2). The MODE pin does not influence the POK5V cir-
cuit. The POK5V undervoltage threshold is always at VV5(POK,L).
The MODE input is shown in Figure 15. Timing diagrams of the
MODE pin functionality is shown in Figure 16 and Figure 17.
There is a delay from the time all regulator voltages have risen
above their undervoltage thresholds to the rising edge of NPOR,
tdNPOR(ON). This delay allows the microcontroller or DSP plenty of
time to fully power-up and complete its initialization routines. The
NPOR circuit also incorporates a delay, tdOV
, between the instant
any regulator output exceeds its overvoltage threshold and when
NPOR transitions low. There is minimal NPOR delay if any fault,
other than overvoltage, occurs that requires NPOR to transition
low. There are no significant delays in the POK5V output after V5
or V5P have risen above or fallen below their undervoltage thresh-
olds. Timing diagram in this datasheet shows the functionality of
NPOR and POK5V.
OV/UV DETECT
& DELAYS
1V25/
FBadj
3.3V
NPOR
DE-
GLITCH
tdFILT
WDSTART
WDFAULT
WDADJ(FAULT)
POK5V
BGFAULT
DE-
GLITCH
tdFILT
V5
V5P
MODE
IBMODE
UV,L1 or
UV,L2
UV DETECT
POK,L
TSD
Figure 15: Fault Reporting Circuit
The V5P monitor is unique: if V5P is accidently connected to the
battery voltage, then NPOR will bypass the normal overvoltage
delay and set itself low immediately. Timing diagrams showing
overvoltage possibilities for V5P are shown in Figure 21.
The fault modes and their effects on NPOR and POK5V are cov-
ered in detail in Table 4.
Fault Flags (FF0, FF1)
The A4408 also includes two open-drain fault flags: FF0 and
FF1. If a fault condition occurs and NPOR transitions low, FF0
and FF1 will be latched into one of three states to retain the type
of fault: undervoltage of any regulator or charge pump (including
V5P disconnect), hiccup mode (or TSD), or watchdog fault. A
fourth state indicates no-fault. Fault flag functionality is sum-
marized in Table 2 and shown in most timing diagrams in this
datasheet.
FF0 and FF1 are only valid if NPOR has first transitioned high.
This means the A4408 must successfully complete the startup
sequence and NPOR transitions high.
The FF0 and FF1 latches are reset when all enable inputs are low
and the soft-start capacitor voltages (SS1, SS2) have decayed
below their reset thresholds.
Table 2: FF0 and FF1 Fault Flag Status Conditions
FF0 FF1 Type of Fault Detected When NPOR↴
Low Low Undervoltage (Synchronous buck, 3V3, V5,
V5P, or VCP), or VV5P > VV5P(DISC)
Low Hi-Z VREG or Synchronous buck in hiccup mode,
or thermal shutdown (TSD)
Hi-Z Low Watchdog Timer (WDT) fault
Hi-Z Hi-Z No fault, default condition
Both VREG and the synchronous buck do not enter hiccup mode
for a specific number of PWM cycles. Therefore, when setting
FF0 and FF1, precedence is given to detecting a hiccup condi-
tion (i.e. an undervoltage will occur before hiccup mode is set).
To accomplish this, the undervoltage detection is delayed by
tdFFx(UV).
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
25
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table 3: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram)
A4408 Status Signals Regulator Control Bits
(0 = OFF, 1 = ON) A4408
MODE
EN MPOR VSS1/2 LOW VREG UV 1V25 UV 3×LDO UV VREG ON 1V25 ON LDOs ON
X 1 X X X X 0 0 0 RESET
001111000 OFF
1 0 0 1 1 1 1 0 0 STARTUP
100011110 ↓
100001111 ↓
100000111 RUN
000000111tdEN(FILT) + tdLDO(OFF)
0 0 0 0 0 0 1 1 0 SHUTDOWN
000001100 ↓
000011000 ↓
000011000 ↓
000111 0 0 0 Pause
001111000 OFF
X = DON’T CARE
EN = ENBAT1 + ENBAT2 + ENB
VSS1/2 LOW = VSS1 < VSS1(RST) × VSS2 < VSS2(RST)
3 × LDO UV = 3V3_UV + V5_UV + V5P_UV
MPOR = VVIN(UVLO) + VCC_UV + VCP_UV + BG1_UV + BG2_UV + FSET_UV/OV + TSD
+ SLEW_UV/OV (latched) + VCP_OV (latched) + D1MISSING (latched) + ILIM(LX1) (latched) + OV > tdOV (latched)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
26
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table 4: Summary of Fault Mode Operation
FAULT TYPE and
CONDITION A4408 RESPONSE TO FAULT NPOR
POK5V
V5SNR/
V5CAN/V5P
LATCHED
FAULT? RESET METHOD
V5P Short to VBAT NPOR and POK5V transition low soon after
V5P disconnect occurs.
Low when
V5PSENSE
decays
Low when
V5PSENSE
decays
NO Check for short
circuits on V5P
V5, V5P, 3V3, or Synchronous
Buck Overvoltage
If the OV condition persists for more than tdOV, then
set NPOR low and turn off all regulators.
Immediately
set low after
tdOV
Low only if
V5 or V5P
are too low
YES
Check for short
circuits then cycle
EN or VIN
V5 or V5P Undervoltage Closed-loop control will try to raise the voltage, but
may be constrained by the foldback current limit. Low Low NO
Remove the
short circuit or
decrease the load
3V3 or Synchronous Buck
Undervoltage
Closed-loop control will try to raise the voltage, but
may be constrained by the foldback or pulse-by-
pulse current limit
Low Not
affected NO
Remove the
short circuit or
decrease the load
V5 or V5P Overcurrent Foldback current limit will reduce the output voltage.
Low if V5 or
V5P are too
low
Low if V5
or V5P are
too low
NO
Remove the
short circuit or
decrease the load
3V3 Overcurrent Foldback current limit will reduce the output voltage. Low if V3V3
< V3V3(UV,L)
Not
affected NO
Remove the
short circuit or
decrease the load
1V25/FBadj pin open circuit
(Synchronous buck output set to
1.25 V, i.e. no FB divider)
The 1V25/FBadj pin will be pulled high by an
internal current source; COMP2 will respond by
going low; LX2 will operate at zero cycle; and the
synchronous buck output ≈ 0 V.
Low High NO
Repair the open
circuit, check the
1V25 circuitry
Synchronous Buck Output
Shorted to Ground, VSS2 <
VHIC2(EN), V1V25 < 450 mV
Continues to PWM, but turns off LX2 when the high-
side MOSFET current exceeds ILIM2.Low Not
affected NO Remove the short
circuit
Synchronous Buck Overcurrent
VSS2 > VHIC2(EN),
V1V25/FBadj < 450 mV
Enters hiccup mode after 30 OCP faults. Low Not
affected NO Decrease the
load
Synchronous Buck Overcurrent
VSS2 > VHIC2(EN),
V1V25/FBadj > 450 mV
Enters hiccup mode after 120 OCP faults.
Low if
V1V25/FBadj
< V1V25(UV,L)
Not
affected NO Decrease the
load
VREG Pin Open Circuit
VVREG will decay to 0 V; LX1 will switch at maximum
duty cycle so the voltage on the output capacitors
will be very close to VVIN.
Low if 3V3,
1V25/
FBadj, V5,
or V5P are
too low
Low if V5
or V5P are
too low
NO Connect the
VREG pin
VREG Overcurrent
VVREG < 1.3 V,
VCOMP1 = VEA1(VO,MAX)
Enters hiccup mode after 30 OCP faults. Low Low NO Decrease the
load
VREG Overcurrent
VVREG > 1.3 V,
VCOMP1 = VEA1(VO,MAX)
Enters hiccup mode after 120 OCP faults.
Low if 3V3,
1V25/
FBadj, V5,
or V5P are
too low
Low if V5
or V5P are
too low
NO Decrease the
load
VREG Overvoltage
VVREG > VREG(OV,H)
Temporarily stop PWM switching of LX1. High High NO None
VREG Asynchronous Diode (D1)
Missing
Results in an MPOR after 1 detection, so all
regulators are shut off.
Low if 3V3,
1V25/
FBadj, V5,
or V5P are
too low
Low if V5
or V5P are
too low
YES Populate D1 then
cycle EN or VIN
Continued on next page...
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
27
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FAULT TYPE and
CONDITION A4408 RESPONSE TO FAULT NPOR
POK5V
V5SNR/
V5CAN/V5P
LATCHED
FAULT? RESET METHOD
Asynchronous Diode (D1)
Short-Circuited or
LX1 Shorted to Ground
Results in an MPOR after 2 detections of the high-
side MOSFET current exceeding ILIM(LX1), so all
regulators are off.
Low if 3V3,
1V25/
FBadj, V5,
or V5P are
too low
Low if V5
or V5P are
too low
YES
Remove the
short, then cycle
EN or VIN
Slew Pin Open Circuit
(SLEW_OV) Results in an MPOR, so all regulators are off. Low Low YES
Connect SLEW
pin then cycle EN
or VIN
Slew Pin Shorted to Ground
(SLEW_UV) Results in an MPOR, so all regulators are off. Low Low YES
Remove the
short, then cycle
EN or VIN
FSET/SYNC Pin Shorted to
Ground or Open Circuit
LX1 operates at a default oscillator frequency of 1 MHz;
VREG achieves 5.35 V; boost function is disabled;
synchronous buck and LDOs remain disabled.
Low Low NO
Remove short
circuit, connect
the pin, or
populate RFSET
Charge Pump (VCP) Overvoltage Results in an MPOR, so all regulators are off. Low Low YES
Check VCP/CP1/
CP2, then cycle
EN or VIN
Charge Pump (VCP)
Undervoltage Results in an MPOR, so all regulators are off. Low Low NO Check VCP/CP1/
CP2
VCP Pin Open Circuit Results in VCP_UV and an MPOR, so all regulators
are off. Low Low NO
Connect the VCP
pin or populate
CCP
VCP Pin Shorted to Sround
Results in high current from the charge pump and
(intentional) fusing of an internal trace. Also results
in MPOR, so all regulators are off.
Low Low NO
Remove the
short circuit
and replace the
A4408
CP1 or CP2 Pin Open Circuit Results in VCP_UV and an MPOR,
so all regulators are off. Low Low NO Connect the CP1
or CP2 pins
CP1 Pin Shorted to Ground Results in VCP_UV and an MPOR,
so all regulators are off. Low Low NO Remove the short
circuit
CP2 Pin Shorted to Ground
Results in high current from the charge pump and
(intentional) fusing of an internal trace. Also results
in MPOR so all regulators are off.
Low Low NO
Remove the
short circuit
and replace the
A4408
BGVREF or BGFAULT Undervoltage Results in an MPOR, so all regulators are off. Low Low NO
Raise VIN or wait
for BGs to power
up
BGVREF or BGFAULT Overvoltage
If BGVREF is too high, all regulators will appear to be
OV (because BGFAULT is good).
If BGFAULT is too high, all regulators will appear to be
UV (because BGVREF is good).
Low Low NO Replace the
A4408
VCC Undervoltage or
Shorted to Ground Results in an MPOR, so all regulators are off. Low Low NO
Raise VIN or
remove short
from VCC pin
WDADJ pin Shorted to Ground or
Open Circuit
A WDADJ fault sets the NPOR output low. The
remainder of the A4408 operates normally. Low High NO
Remove the short
circuit or connect
the pin
Thermal Shutdown Results in an MPOR, so all regulators are off. Low Low NO Let the A4408
cool
Table 4: Summary of Fault Mode Operation (continued)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
28
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
t
dFILT
+ t
dNPOR(ON)
t
dWD(START)
VIN
(Pin)
V5
V5P
NPOR
WDSTART
POK5V
12 V
V
V5P
< VV5P(POK,L) or
V
V5
< VV5(POK,L)
V
VIN(STOP)
t
dFILT
~5 V
~4 V
VV5(POK,L)
VV5P(POK,L)
t
dFILT
VV5(UV,L1)
VV5P(UV,L1)
t
dFILT
V
V5P
< VV5P(UV,L1)
or
V
V5
< VV5(UV,L1)
V
V5P
> VV5P(POK,H)
and
V
V5
> VV5(POK,H)
V
V5P
> VV5P(UV,H)
and
V
V5
> VV5(UV,H)
FF0
FF1
NPOR↓ latches FF0 and FF1 after t
dFFx(UV)
Grey, lined areas indicate Hi-Z
t
dFFx(UV)
NPOR↓ forces WDSTART LOW
Figure 16: Low VIN Operation with MODE = Low, and ENB or ENBAT High
TIMING DIAGRAMS
(Not to Scale)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
29
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 17: Low VIN Operation with MODE = High, and ENB or ENBAT High
12 V
V
V5(UV,L2)
VVIN(STOP)
tdFILT
~5 V
~4 V
V
V5(POK,L)
V
V5P(UV,L2)
V
V5P(POK,L)
tdFILT
VV5P < V
V5P(POK,L)
or
VV5 < V
V5(POK,L)
VV5P > V
V5P(POK,H)
and
VV5 > V
V5(POK,H)
V5
V5P
NPOR
WD
START
POK5V
FF0
FF1
VIN
(Pin)
Grey, lined areas indicate Hi-Z
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
30
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
t < t
dFILT
t
dFILT
t
dFILT
t < t
dEN(FILT)
t
SS2
LX1
1V25
3V3
V5
V5P
NPOR
WDSTART
POK5V
SS1
COMP1
f
OSC
VREG
5.35 V
LX2
SS2
V
SS2(OFFS)
COMP2
f
OSC
V
VREG(UV,H)
V
1V25(UV,H)
V
V5(UV,H)
V
V5P(POK,H)
V
V5P(UV,H)
V
V5P(POK,H)
V
3V3(UV,H)
t
SS1
t
SS1(DLY)
t
SS2(DLY)
NPOR↓ forces WD
START
LOW
V
3V3(UV,L)
V
3V3
< V
3V3(UV,L)
and
V
V5P
< V
V5P(UV,Lx)
and
V
V5
< V
V5(UV,Lx)
V
1V25(UV,L)
1V25,3V3,V5P,V5
are all UV
V
SS1(OFFS)
EN
V
V5P
> V
V5P(POK,H)
and
V
V5
> V
V5(POK,H)
t
dLDO(OFF)
SHUTDOWN SEQUENCE MUST FINISH
BEFORE RESTART IS ACKNOWLEDGED
V
PWM1(OFFS)
V
PWM2(OFFS)
FF0
FF1
V
V5P
< V
V5P(POK,L)
or
V
V5
< V
V5(POK,L)
EN↓ forces NPOR LOW
f
OSC
/ 8
/ 4
/ 2
f
OSC
/ 4
/ 2
CLEAR
FF0/FF1
V
SS1(RST)
V
SS2(RST)
EN=0, VSS1
RST
=1, VSS2
RST
=1
V
V5P
> V
V5P(UV,H)
and
V
V5
> V
V5(UV,H)
and
V
3V3
> V
3V3(UV,H)
and
V
1V25
> V
1V25(UV,H)
t
dWD(START)
t
dNPOR(OFF)
t
dFILT
+ t
dNPOR(ON)
t < t
dFILT
Indicates
Hi-Z state
V
V5(UV,Lx)
V
V5P(POK,L)
V
V5P(UV,Lx)
V
V5P(POK,L)
f
OSC
f
OSC
t
dEN(FILT)
f
OSC
ENB and ENBAT1 and ENBAT2 = 1 ENB or ENBAT1 or ENBAT2 = 0
Figure 18: Startup and Shutdown due to EN while VVIN = 12 VDC
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
31
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
EN
t
dFILT
t
dFILT
t
SS2
LX1
VIN
1V25
3V3
V5
V5P
NPOR
WD
START
POK5V
SS1
COMP1
f
OSC
VREG
LX2
SS2
V
SS2(OFFS)
COMP2
f
OSC
12 V
V
VREG(UV,H)
V
1V25(UV,H)
t
SS1
t
SS1(DLY)
t
SS2(DLY)
V
SS1(OFFS)
~5.45V @ 25°C
f
OSC
f
OSC
Discharged by RPD
SS1
Discharged by RPD
SS2
V
SS2
< V
SS2(RST)
V
VIN
< V
VIN(STOP)
V
PWM2(OFFS)
V
PWM1(OFFS)
V
VIN(START)
f
OSC
/ 4
f
OSC
/ 2
f
OSC
/ 8
f
OSC
/ 4
f
OSC
/ 2
FF0
FF1
V
V5P(UV,H)
V
V5P(POK,H)
V
V5(UV,H)
V
V5(POK,H)
V
3V3(UV,H)
V
V5P
> V
V5P(POK,H)
and
V
V5
> V
V5(POK,H)
V
V5P
< V
V5P(POK,L)
or
V
V5
< V
V5(POK,L)
V
V5P
< V
V5P(UV,Lx)
or
V
V5
< V
V5(Uv,Lx)
or
V
3V3
< V
V3V(Uv,Lx)
or
V
1V25
< V
1V25(UV,Lx)
CLEAR
FF0/FF1
V
V5(UV,Lx)
V
V5(POK,L)
V
3V3(UV,L)
t
dFFx(UV)
t
dFILT
100% Duty
Cycle
V
SS1
< V
SS1(RST)
and
V
SS2
< V
SS2(RST)
V
V5P
> V
V5P(UV,H)
and
V
V5
> V
V5(UV,H)
and
V
3V3
> V
3V3(UV,H)
and
V
1V25
> V
1V25(UV,H)
NPOR↓ forces WD
START
LOW
t
dFILT
+ t
dNPOR(ON)
V
VIN
> V
VIN(START)
t
dWD(START)
EN=0, VSS1
RST
=1, VSS2
RST
=1
ENB or ENBAT1 or ENBAT2 = 1ENB and ENBAT1 and ENBAT2 = 0
Figure 19: Startup and Dropout/Shutdown due to VVIN while EN = 1
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
32
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A LATCHED FAULT CAN BE RESET BY EN LOW IF:
V
SS1
< V
SS1(RST)
and V
SS2
< V
SS2(RST)
t
dFILT
t
dFILT
t < t
dFILT
t < t
dFILT
LX1
1V25
3V3
V5
V5P
NPOR
WDSTART
POK5V
SS1
COMP1
f
OSC
VREG
LX2
SS2
V
SS2(OFFS)
COMP2
f
OSC
V
VREG(OV,H)
V
1V25(UV,L)
V
V5P(UV,H)
V
V5(UV,H)
V
3V3(OV,H)
NPOR↓ forces WD
START
LOW
V
3V3(UV,H)
V
1V25(UV,H)
V
SS1(OFFS)
EN
Any OV with t > t
dOV
forces NPOR LOW
V
VREG(OV,L)
f
OSC
f
OSC
V
V5P
> V
V5P(UV,H)
and
V
V5
> V
V5 (UV,H)
and
V
3V3
> V
3V3(UV,H)
and
V
1V25
> V
1V25(UV,H)
f
OSC
V
SS1(RST)
V
SS2(RST)
t < t
dFILT
t < t
dFILT
t > t
dOV
V
PWM1(OFFS)
V
PWM2(OFFS)
V
V5P
> V
V5P(POK,H)
and
V
V5
> V
V5(POK,H)
V
V5P
< V
V5P(POK,L)
or
V
V5
< V
V5(POK,L)
OV of VREG does not shutdown the A4408,
it temporarily suspends LX1 switching
t
dFILT
or t
dNPOR(ON)
t < t
dOV
t < tdOV
t < t
dOV
t < t
dOV
FF0
FF1
t
dWD(START)
V
V5(POK,L)
V3V3 OV IS SHOWN,
IDENTICAL CASES IF:
V
V5
> V
V5(OV,H)
or
V
1V25
> V
1V25(OV,H)
V
SS1
< V
SS1(RST)
and
V
SS2
< V
SS2(RST)
ENB and ENBAT1 and ENBAT2 = 0
Figure 20: Overvoltage of VREG, Synchronous Buck, 3V3, or V5 with Reset by EN
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
33
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 21: Possible Overvoltage Cases for V5P
NPOR set LOW
due to any OV
NPOR↓ forces
WD
START
LOW
POK5V↓ after t
dFILT
and V
V5
< V
V5(POK,L)
CASE 1: V
V5P(OV,H)
< V
V5P
< V
V5P(DISC)
and t > t
dOV
t = t
dOV
f
OSC
f
OSC
OV forces LX1
to stop switching
V
V5P(OV,H)
V
VBAT
V
V5P(DISC)
LX1
1V25
3V3
V5
V5P
NPOR
WD
START
POK5V
SS1
COMP1
VREG
LX2
SS2
COMP2
FF0
FF1
OV forces LX2
to stop switching
CASE 2: V
V5P
> V
V5P(OV,H)
but t < t
dOV
V
V5P(OV,H)
V
VBAT
V
V5P(DISC)
t = t
dOV
V
V5P(OV,L)
V5P
NPOR
WD
START
POK5V
FF0
FF1
f
OSC
f
OSC
LX1
1V25
3V3
V5
SS1
COMP1
VREG
LX2
SS2
COMP2
NPOR↓ forces
WD
START
LOW
V
V5P(OV,H)
V
VBAT
V
V5P(DISC)
CASE 3: V
V5P
> V
V5P(DISC)
V5P
NPOR
WD
START
POK5V
FF0
FF1
f
OSC
f
OSC
LX1
1V25
3V3
V5
SS1
COMP1
VREG
LX2
SS2
COMP2
NPOR↓ after tdFILT and
VV5P(SENSE)
< VV5P(UV,Lx)
POK5V↓ after tdFILT and
VV5P(SENSE)
< VV5P(POK,L)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 22: Hiccup Mode Operation when VREG is shorted to GND
tHIC1(OCP)
VSS1(RST)
LX1
SS1
COMP1
EN_HIC1
OCP1
HIC1
VSS1(OFFS)
V
EA(VO,MAX)
, OCL1= 1
VPWM1(OFFS)
FF0
FF1
NPOR
VREG
1.3 VTYP
t
dFFx(UV)
To detect Hiccup mode, UV sensing must be delayed by t
dFFx(UV)
UV of V5 or V5P
VREG shorted to ground
tHIC1(OCP)
tHIC1(OCP)
fOSC
fOSC/4
fOSC/8
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
35
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Figure 23: Hiccup Mode Operation when the Synchronous Buck output is shorted to GND
V
SS2(RST)
LX2
SS2
COMP2
EN_HIC2
OCP2
HIC2
VHIC2(EN)
V
SS2(OFFS)
VPWM2(OFFS)
FF0
FF1
NPOR
1V25/
FBadj
450 mVTYP
t
dFFx(UV)
To detect Hiccup mode, UV sensing must be delayed by t
dFFx(UV)
Synchronous buck output shorted to ground
V
EA2(VO,MAX)
, OCL2=1
fOSC
fOSC/4
fOSC/8
tHIC2(OCP) tHIC2(OCP) tHIC2(OCP)
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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NPOR↓ latches FF0 and FF1
t > 24 ms
t < 16 ms
t
WD(FAULT)
NPOR
WD
START
CLK
IN
WD
FAULT
t
WD(TO,SLOW)
set to 20 ms (±4ms)
t < 16 ms t
dWD(START)
FF0
FF1
Figure 24: Typical Watchdog Timer Operation
WD will not indicate a fault if the rising edges of CLKIN occur within 16 ms of each other.
WD will indicate a fault if the rising edges of CLKIN occur more than 24 ms apart.
NPOR↓ latches FF0 and FF1
t
dWD(START)
‒ t
dNPOR(ON)
t
WD(FAULT)
t
WD(FAULT)
t
WD(TO,SLOW)
t
WD(FAULT)
NPOR
WD
START
CLK
IN
WD
FAULT
t
WD(TO,SLOW)
STARTUP
t
WD(TO,SLOW)
t
dWD(START)
t
dWD(START)
t
dWD(START)
t
dWD(START)
+ t
WD(TO,SLOW)
+ t
WD(FAULT)
t
dFILT
+ t
dNPOR(ON)
All Regs_OK
FF0
FF1
Figure 25: Watchdog Timer Operation Showing Start Delay and Missing CLKIN
After startup, if CLKIN is stuck low (or high), NPOR will periodically pulse LOW for 2 ms.
The time between NPOR fault indications will be tdWD(START) + tWD(TO,SLOW) + tWD(FAULT).
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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PWM Switching Frequency (RFSET)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable on-time, tON(MIN),
of the A4408. If the system’s required on-time is less than the
A4408 minimum controllable on-time, then switch node jitter
will occur and the output voltage will have increased ripple or
oscillations.
The PWM switching frequency should be calculated using equa-
tion 1, where tON(MIN) is the minimum controllable on-time of
the A4408 (85 nsTYP) and VVIN(MAX) is the maximum required
operational input voltage (not the peak surge voltage).
fOSC <
5.35 V
t× V
ON(MIN) VIN(MAX)
(1)
If the A4408 synchronization function is used, then the base
oscillator frequency should be chosen such that jitter will not
result at the maximum synchronized switching frequency accord-
ing to equation 1.
Charge Pump Capacitors
The charge pump requires two capacitors: a 1 µF connected from
pin VCP to VIN, and a 0.22 µF connected between pins CP1 and
CP2. These capacitors should be high-quality ceramic capacitors,
such as X5R or X7R, with voltage ratings of at least 16 V.
Pre-Regulator Output Inductor (L1)
For peak current-mode control, it is well known that the system
will become unstable when the duty cycle is above 50% without
adequate Slope Compensation (SE). However, the slope compen-
sation in the A4408 is a fixed value based on the oscillator fre-
quency (fOSC). Therefore, it’s important to calculate an inductor
value so the falling slope of the inductor current (SF) will work
well with the A4408 fixed slope compensation.
Equation 2 can be used to calculate a range of values for the
output inductor for the pre-regulator. In equation 2, slope com-
pensation (SE1) is a function of the switching frequency (fOSC)
according to equation 3, and VF is the asynchronous diodes
forward voltage.
(2)
(5.25 V+ V)
F
SE1 SE1
≤L1≤
(5.45 V+ V)
F
2
(3)
S= 7.188×10-4× f+ 0.0425
E1 OSC
When using equations 2 and 3, fOSC is in kHz, SE1 is in A/µs, and
L1 will be in µH.
If equation 2 yields an inductor value that is not a standard value,
then the next highest standard value should be used. The final
inductor value should allow for 10%-20% of initial tolerance and
20%-30% of inductor saturation.
The inductor should not saturate given the peak operating cur-
rent according to equation 4. In equation 4, VVIN(MAX) is the
maximum continuous input voltage, such as 18 V, and VF is the
asynchronous diodes forward voltage.
(4)
S× (5.25 V+ V)
E1 F
1.1 × f× (V + V)
OSCVIN(MAX)
I= 5.1 A–
PEAK1
F
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be moni-
tored using a current probe. A good design should ensure the
inductor or the regulator are not damaged when the output is
shorted to ground at maximum continuous input voltage and the
highest expected ambient temperature.
The inductor ripple current can be calculated using equation 5.
(5)
(V –5.35 V) × 5.35 V
VIN
fL× V
OSC1VIN
×
I=
L1
Δ
Pre-Regulator Output Capacitance
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
Within the first few PWM cycles, the deviation of VVREG will
depend mainly on the magnitude of the load step (ΔILOAD1), the
value of the output inductor (L1), the output capacitance (COUT),
and the maximum duty cycle of the pre-regulator (DMAX1).
Equations 6 and 7 can be used to calculate a minimum output
capacitance to maintain VVREG within 1% of its target for a
750 mA load step at only 6 VVIN.
(6)
L1 × (750 mA)2
2 × (6.0 V–5.25 V) × (0.01 × 5.25 V) × DMAX1
C≥
OUT(VREG)
(7)
DMAX =1
fOSC
× fOSC
–80 ns
()
After the load transient occurs, the output voltage will deviate
DESIGN AND COMPONENT SELECTION
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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from its nominal value until the error amplifier can bring the
output voltage back to its nominal value. The speed at which the
error amplifier will bring the output voltage back to its setpoint
will depend mainly on the closed-loop bandwidth of the system.
Selection of the compensation components (RZ1, CZ1, CP1) are
discussed in more detail in the Pre-Regulator Compensation sec-
tion of this datasheet.
The output voltage ripple (ΔVVREG) is a function of the output
capacitors parameters: COUT, ESRCo, and ESLCo according to
equation 8.
(8)
V=I× ESR+
VREG LCo
V–V
VIN VREG
LO
× ESL+
Co
I
L
8 × fOSCOUT
× C
ΔΔ
Δ
The type of output capacitors will determine which terms of
equation 8 are dominant. For the A4408 and automotive environ-
ments, only ceramic capacitors are recommended. The ESRCO
and ESLCO of ceramic capacitors are virtually zero, so the peak-
to-peak output voltage ripple of VVREG will be dominated by the
third term of equation 8.
ΔI
L
8 × fOSC OUT
× C
(9)
ΔVVREG(PP)=
Pre-Regulator Ceramic Input Capacitance
The ceramic input capacitors must limit the voltage ripple at the
VIN pin to a relatively low voltage during maximum load. Equa-
tion 10 can be used to calculate the minimum input capacitance,
I× 0.25
VREG(MAX)
0.90 × fOSCPP
× 50 mV
(10)
CIN ≥
where IVREG(MAX) is the maximum current from the pre-regulator,
(11)
I= I+ +
VREG(MAX)V5 V5P 3V3
II+
V×
OUT(ADJ) OUT(ADJ)
I
5.25 V× 80%
+ 20 mA
A good design should consider the DC bias effect on a ceramic
capacitor—as the applied voltage approaches the rated value, the
capacitance value decreases. The X7R-type capacitors should be
the primary choices due to their stability versus both DC bias and
temperature. For all ceramic capacitors, the DC bias effect is even
more pronounced on smaller case sizes, so a good design will use
the largest affordable case size (i.e. 1206/16 V or 1210/50 V).
Also, for improved EMI/EMC performance, it is recommended
that two small capacitors be placed as close as physically possible
to the VIN pins to address frequencies above 10 MHz. For exam-
ple, a 0.1 µF/X7R/0603 and a 220 pF/COG/0402 capacitor will
address frequencies up to 20 MHz and 200 MHz, respectively.
Pre-Regulator Asynchronous Diode (D1)
The highest peak current in the asynchronous diode (D1) occurs
during overload and is limited by the A4408. Equation 4 can be
used to calculate this current.
The highest average current in the asynchronous diode occurs
when VVIN is at its maximum, DBOOST = 0%, and DBUCK = mini-
mum (10%),
IAVG = (1 – DBUCK) × IVREG(MAX) = 0.9 × IVREG(MAX) (12)
where IVREG(MAX) is calculated using equation 11.
Pre-Regulator Boost MOSFET (Q1)
The maximum RMS current in the boost MOSFET (Q1) occurs
when VVIN is very low and the boost operates at its maximum
duty cycle,
(13)
I=
Q1(RMS) D×
MAX(BST) I–
PEAK1
ΔIL1 ΔIL1
2
2
+
12
)
(
[]
√
where IPEAK1 and ΔIL1 are derived using equations 4 and 5,
respectively, and DMAX(BST) is identified in the Electrical Charac-
teristics table.
The boost MOSFET should have a total gate charge of less than
14 nC at a VGS of 5 V. The VDS rating of the boost MOSFET
should be at least 20 V. Several recommended part numbers are
shown in the Functional Block Diagram / Typical Schematic.
Pre-Regulator Boost Diode (D2)
In buck mode, the maximum average current in this diode is simply
the output current, calculated with equation 11. However, in buck-
boost mode, the peak currents in this diode may increase signifi-
cantly. The A4408 will limit the current to the value calculated by
equation 4.
Pre-Regulator Soft-Start and Hiccup Timing
(CSS1)
The soft-start time of the pre-regulator is determined by the value
of the capacitance at the soft-start pin (CSS1).
If the A4408 is starting into a very heavy load, a very fast soft-
start time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the total of the full
load current, the inductor ripple current, and the additional cur-
rent required to charge the output capacitors (IC(OUT) = COUT ×
VOUT / tSS) is higher than the pulse-by-pulse current threshold, as
shown in Figure 26.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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ILIM
ILOAD
Output
Capacitor
Current, IC(OUT)
tSS
}
Figure 26: Output Current (ICO) During Startup
To avoid prematurely triggering hiccup mode, the soft-start time
(tSS1) should be calculated using equation 14,
(14)
tSS1 = 5.35 V×
C
OUT
IC(OUT)
where COUT is the output capacitance, and IC(OUT) is the amount
of current allowed to charge the output capacitance during soft-
start (recommend 0.1 A < IC(OUT) < 0.3 A). Higher values of
IC(OUT) result in faster soft-start time, and lower values of IC,OUT
ensure that hiccup mode is not falsely triggered. Allegro recom-
mends starting the design with an IC(OUT) of 0.1 A and increasing
it only if the soft-start time is too slow.
Then, CSS1 can be calculated based on equation 15:
(15)
CSS1 ≥
I
SS1(SU) SS1
× t
0.8 V
If a non-standard capacitor value for CSS1 is calculated, the next
higher value should be used.
The voltage at the soft-start pin will start from 0 V and will be
charged by the soft-start current (ISS1(SU)). However, PWM
switching will not begin immediately because the voltage at
the soft-start pin must rise above the soft-start offset voltage
(VSS1(OFFS)). The soft-start delay (tSS1(DLY)) can be calculated
using equation 16.
(16)
tSS1(DLY) SS1
= C×
V
SS1(OFFS)
ISS1(SU)
When the A4408 is in hiccup mode, the soft-start capacitor sets
the hiccup period. During a startup attempt, the soft-start pin
charges the soft-start capacitor with ISS1(SU) and discharges the
same capacitor with ISS1(HIC) between startup attempts.
Pre-Regulator Compensation (RZ1, CZ1, CP1)
Although the A4408 can operate in buck-boost mode at low
input voltages, it still can be considered a buck converter when
examining the control loop. The following equations can be used
to calculate the compensation components.
First, select the target crossover frequency for the final system.
While switching at over 2 MHz, the crossover is governed by
the required phase margin. Since a type II compensation scheme
is used, the system is limited to the amount of phase that can be
added. Hence, a crossover frequency (fC1) in the region of 35 kHz
is selected. The total system phase will drop off at crossover
frequencies about 100 kHz. The RZ1 calculation is based on the
gain required to set the crossover frequency and can be calculated
by equation 17.
(17)
RZ1 =
13.38 ×π× f× C
C1 OUT
gmPOWER1 EA1
× gm
The series capacitor (CZ1) along with the resistor (RZ1) set the
location of the compensation zero. This zero should be placed no
lower than ¼ of the crossover frequency and should be kept to
minimum value. Equation 18 can be used to estimate this capaci-
tor value.
(18)
CZ1 >4
2×πR× f
Z1 C1
Allegro recommends adding a small capacitor (CP1) in parallel
with the series combination of RZ1/CZ1 to roll off the error amps
gain at high frequency. This capacitor usually helps reduce LX1
pulse-width jitter, but if too large, it will also decrease the loop’s
phase margin.
Allegro recommends using this capacitor to set a pole at approxi-
mately 5× the loop’s crossover frequency (fC1), as shown in equa-
tion 19. If a non-standard capacitor value results, the next higher
available value should be used.
(19)
CP1 ≈
1
2×πR× 5 × f
Z1 C1
An Excel-based design tool is available from Allegro that accepts
customer specifications and recommends values for both the
power and compensation components. The pre-regulator bode
plot in Figure 27 was generated with this tool. The bandwidth
of this system (fC1) is 30 kHz, the phase margin (PM1) is
61 degrees, and the gain margin (GM1) is 25 dB.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 27: Bode Plot for the Pre-Regulator
RZ1 = 22.1 kΩ, CZ1 = 1.5 nF, CP1 = 47 pF
Lo = 4.7 µH, Co = 5 × 10 µF/16 V/1206
Synchronous Buck Component Selection
Similar design methods can be used for the synchronous buck;
however, the complexity of variable input voltage and boost
operation are removed.
Setting the Output Voltage (RFB1 and RFB2)
The A4408 was optimized to deliver 1.25 V from the synchro-
nous buck—where the output of the synchronous buck is con-
nected directly to the FB1V25/ADJ pin. The absence of a resistor
divider from VOUT to the FB1V25/ADJ pin results in robust fault
conditions (i.e. if the feedback trace is open, the output of the
synchronous buck will be 0 V).
If required, the output of the synchronous buck may be pro-
grammed from 1.25 to 3.3V. This is achieved by adding a resistor
divider from its output to ground and connecting the center point
to the FB1V25/ADJ pin, as shown in Figure 28.
LX2
1V25/FBADJ
ADJ. SYNC.
BUCK
REGULATOR
RFB2
RFB1
L2 VOUT(ADJ)
A4408
Figure 28: Setting the Synchronous Buck Output
The ratio of the feedback resistors can be calculated based on
equation 20.
(20)
=
V
OUT(ADJ)
1.25 V
R
FB1
R
FB2
–1
()
Synchronous Buck Output Inductor (L2)
Equation 21 can be used to calculate a range of values for the out-
put inductor for the synchronous buck regulator. Slope compensa-
tion (SE2) can be calculated using equation 22.
(21
)
V
OUT(ADJ)
2 ×S
E2
≤L2≤
V
OUT(ADJ)
SE2
(22)
SE2 OSC
= 3.063×10-4× f+ 0.0175
When working with equations 21 and 22, fOSC is in kHz, SE2 is in
A/µs, and L2 will be in µH.
If equation 21 yields an inductor value that is not a standard
value, then the next closest available value should be used. The
final inductor value should allow for 10%-20% of initial toler-
ance and 20%-30% for inductor saturation.
The inductor should not saturate given the peak current at over-
load according to equation 23.
(23)
S× V
E2 OUT(ADJ)
I= 2.4A–
PEAK2
1.1 × fOSC × 5.45 V
Once the inductor value is known, the ripple current can be calcu-
lated using equation 24.
(24)
(5.35 V× VV
OUT(ADJ) OUT(ADJ)
) ×
ΔI=
L2 f
OSC
× L2 × 5.35 V
Synchronous Buck Output Capacitance
Within the first few PWM cycles, the deviation of VOUT(ADJ)
will depend mainly on the magnitude of the load step (ΔILOAD2),
the value of the output inductor (L2), the output capacitance
(COUT(ADJ)), and the maximum duty cycle of the synchronous
converter (DMAX2). Equations 25 and 26 can be used to calculate
a minimum output capacitance to maintain 1.25 V within 1.2% of
its target for a 400 mA load step.
(25)
L2 × (400 mA)2
2 × V × (0.012 × 1.25V) × D
OUT(ADJ) MAX2
C≥
OUT(1V25)
(26)
DMAX2 =1
f
OSC
× fOSC
–110 ns
()
After the load transient occurs, the output voltage will deviate
from its nominal value until the error amplifier can bring the
output voltage back to its nominal value. The speed at which the
error amplifier will bring the output voltage back to its setpoint
will depend mainly on the closed-loop bandwidth of the system.
Selection of the compensation components (RZ2, CZ2, CP2) are
discussed in more detail in the Synchronous Buck Compensation
section of this datasheet.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Allegro recommends the use of ceramic capacitors for the syn-
chronoous buck. The peak-to-peak voltage ripple of the synchro-
nous buck (ΔVOUT(ADJ,PP)) can be calculated with equation 27.
ΔI
L2
8 × fOSC OUT(ADJ)
× C (27)
ΔVVOUT(ADJ,PP) =
Synchronous Buck Compensation (RZ2, CZ2,
CP2)
Again, similar techniques as used with the pre-regulator can be
used to compensate the synchronous buck.
For the synchronous buck, select 100 kHz for the crossover fre-
quency (fC2) of the synchronous buck. Then, equation 28 can be
used to calculate RZ2.
V× 2π × f× C
OUT(ADJ) C2 OUT(ADJ)
1.25 V × gmPOWER2 EA2
× gm (28)
R
Z2 =
The series capacitor (CZ2) along with the resistor (RZ2) set the
location of the compensation zero. This zero should be placed no
lower than ¼ of the crossover frequency and should be kept to
minimum value. Equation 29 can be used to estimate this capaci-
tor value.
4
2π × R× f
Z2 C2
(29)
CZ2 >
Allegro recommends adding a small capacitor (CP2) in parallel
with the series combination of RZ2/CZ2 to roll off the error amp
gain at high frequency. This capacitor usually helps reduce LX2
pulse-width jitter, but if too large, it will also decrease the loop’s
phase margin.
Allegro recommends using this capacitor to set a pole at approxi-
mately 8× the loop’s crossover frequency (fC2), as shown in equa-
tion 30. If a non-standard capacitor value results, use the next
higher available value.
1
2π × R× 8 × f
Z2 C2
(30)
CP2 ≈
Allegro’s Excel-based design tool accepts specifications for the
synchronous buck and recommends values for both the power
and compensation components. The synchronous buck bode plot
in Figure 29 was generated with this tool. The bandwidth of this
system (fC2) is 90 kHz, the phase margin (PM2) is 56 degrees,
and the gain margin (GM2) is 17 dB.
-75
-60
-45
-30
-15
0
15
30
45
60
75
90
105
120
135
150
165
180
-60
-40
-20
0
20
40
60
80
100 1000 10000 100000 1000000
Phase - °
Gain - dB
Frequency - Hz
Synchronous Buck Bode Plot
Gain Phase
Figure 29: Bode Plot for the Sync. Buck at 1.25 VOUT
RZ2 = 6.81 kΩ, CZ2 = 1.5 nF, CP2 = 47 pF
L2 = 4.7 µH, COUT(ADJ) = 3 × 10 µF/16 V/1206
Synchronous Buck Soft-Start and Hiccup Timing
The soft-start time of the synchronous buck is determined by the
value of the capacitance at the soft-start pin (CSS2).
If the A4408 is starting into a very heavy load, a very fast soft-
start time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. To avoid prematurely triggering hiccup
mode, the soft-start time (tSS2) should be calculated according to
equation 31,
C
OUT(ADJ)
IC(OUT)
(31)
tSS2 OUT(ADJ)
= V×
where VOUT(ADJ) is the output voltage, COUT(ADJ) is the output
capacitance, IC(OUT) is the amount of current allowed to charge
the output capacitance during soft-start (recommend 75 mA <
IC(OUT) < 150 mA). Higher values of IC(OUT) result in faster soft-
start times and lower values of IC(OUT) ensure that hiccup mode is
not falsely triggered. For the synchronous buck, Allegro recom-
mends starting the design with an IC(OUT) of 100 mA and increas-
ing it only if the soft-start time is too slow.
Then, CSS2 can be selected based on equation 32,
I
SS2(SU) SS2
× t
1.25 V (32)
CSS2 >
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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If a non-standard capacitor value for CSS2 is calculated, the next
larger value should be used.
The voltage at the soft-start pin will start from 0 V and will be
charged by the soft-start current (ISS2(SU)). However, PWM switch-
ing will not begin instantly because the voltage at the soft-start pin
must rise above the soft-start offset voltage (VSS2(OFFS)). The soft-
start delay (tSS2(DLY)) can be calculated using equation 33,
V
SS2(OFFS)
ISS2(SU)
(33)
t= C
SS2(DLY) SS2 ×
()
When the A4408 is in hiccup mode, the soft-start capacitor sets
the hiccup period. During a startup attempt, the soft-start pin
charges the soft-start capacitor with ISS2(SU) and discharges the
same capacitor with ISS1(HIC) between startup attempts.
Linear Regulators
The three linear regulators only require a single ceramic capacitor
located near the A4408 to ensure stable operation. The range of
acceptable values is shown in the Electrical Characteristics table.
A 2.2 μF capacitor per regulator is a good starting point.
As the LDO outputs are routed throughout the PCB, it is
recommended that a 0.1 µF/0603 ceramic capacitor be placed as
close as possible to each load point for local filtering and high-
frequency noise reduction.
Also, since the V5P output may be used to power remote
circuitry, its load may include external wiring. The inductance of
this wiring will cause LC-type ringing and negative spikes at the
V5P pin if a “fast” short-to-ground occurs. It is recommended
that a small Schottky diode be placed close to the V5P pin to limit
the negative voltages, as shown in the Applications Schematic.
The MSS1P5 (or equivalent) is a good choice.
Internal Bias (VCC)
The internal bias voltage should be decoupled at the VCC pin
using a 1 μF ceramic capacitor. It is not recommended to use this
pin as a source.
Signal Pins (NPOR, POK5V, FF0, FF1)
The A4408 has many signal-level pins. The NPOR, POK5V,
FF0, and FF1 are open-drain outputs and require external pull-up
resistors. Allegro recommends sizing the external pull-up
resistors so each pin will sink less than 2 mA when it is a logic
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 31: Typical LX1 ring frequency at turn-on
without a snubber and VVIN = 12 V: fRING = 192 MHz
After the ring frequency has been measured, the total capacitance
at the LX node must be estimated. For the buck-boost pre-
regulator, the LX1 pin (5 to 10 pF), the PCB (10 to 30 pF), and
the asynchronous diode will all contribute to the capacitance. The
asynchronous diode junction capacitance (~70 pF at 12 VR) is
usually shown in the datasheet, as shown in Figure 32.
For the synchronous buck, there is no external diode, so the total
capacitance will consist of the LX2 pin, the internal synchronous
MOSFET (10 to 20 pF), and the PCB.
Figure 32: Typical diode junction capacitance
The total capacitance is calculated using equation 34,
CTOT = CDIODE + CLX1_PIN + CPCB (34)
= 70 pF + 7.5 pF + 20 pF = 97.5 pF
Knowing the ring frequency and the total capacitance, the induc-
tive component of the ringing can be calculated using equation 35.
1
4 × π2 × fRING2 × CTOT
(35)
LRING =
1
4 × π
2
× 192 MHz
2
× 97.5 pF
LRING
==
7.05 nH
The snubber resistor is calculated using equation 36.
(36)
LRING
CTOT
√
RSNUB =
7.05 nH
97.5 pF
√
R
SNUB = = 8.66 Ω (standard value)
Finally, the snubber capacitor can be calculated using equa-
low.
RC Snubber Calculations (RSNUBx, CSNUBx)
Allegro strongly recommends including provisions for RC
snubbers from LX1, LX2, and LXb to ground, as shown in the
Applications Schematic. The LX1 and LX2 snubbers are required
to meet automotive EMC requirements. The LXb snubber may
be needed to reduce system noise when VVIN is less than 7 V
and the boost MOSFET (LG pin) starts switching. If the A4408
is used in buck-only mode, the LXb snubber is not necessary. A
simple method to calculate the RC snubber component values is
presented here.
Use the tip-and-barrel technique on a oscilloscope probe to mea-
sure the frequency of the turn-on ringing of the LX node without
an RC snubber. The oscilloscope bandwidth must be set to its
maximum, at least 200 MHz. The tip-and-barrel oscilloscope
probe technique is show in Figure 30. Typical LX ringing and
frequency without a snubber are shown in Figure 31.
Figure 30: Measuring LX ringing with tip-and-barrel
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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versus ambient temperature
Figure 34 shows the LX waveform with the RC snubber compo-
nents, 8.66 Ω + 270 pF—the 192 MHz high-frequency ringing
has been eliminated.
Figure 34: LX1 waveform including an RC snubber
consisting of 8.66 Ω + 270 pF
tion 37. If equation 37 results in a non-standard value, use the
next higher standard value.
1
2.5 × fRING × RSNUB
(37)
CSNUB =
1
2.5
× 192 MHz
× 8.66 Ω
CSNUB
==
270 pF (standard)
It is very important to calculate the power dissipated by the
resistor at the maximum steady-state (DC) input operating volt-
age, using equation 38. Once the maximum power dissipation is
known, an adequate component considering power derating at the
maximum ambient temperature can be chosen. In this example,
VVIN(MAX,DC) = 18 V and fOSC = 2.2 MHz is used.
PSNUB = ½ × CSNUB × VVIN2 × fSW (38)
PSNUB= ½ × 270 pF ×18 V2 × 2.2 MHz = 96 mW
To support 100 mW at high ambient temperature, a 1206 size
resistor is needed. A 1206 size resistor can dissipate 250 mW up
to 100°C and 100 mW (40%) up to almost 135°C, as shown in
Figure 33.
0
10
20
30
40
50
60
70
80
90
100
110
25 35 45 55 65 75 85 95 105 115 125 135 145 155 165
Power Rating (%)
Ambient Temperature (°C)
Typical Resistor Power Derating vs. Temperature
Figure 33: Resistor power derating
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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PCB LAYOUT RECOMMENDATIONS
Figure 35: Charge Pump capacitor C1 and C2.
Place these components near pins 1, 2, 37, and 38.
Figure 36: Recommended placement and connection of the two charge pump capacitors.
1) Start the layout by placing these components near pins 1, 2, 37, and 38.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 37: The most critical power component connections for the pre-regulator.
Place these components onto the PCB layout after the charge pump capacitors.
Figure 38: Recommended placement and routing of the most critical power components.
1) All of these components must be on the same layer as the A4408 (U1).
2) Routing between these components must not be interrupted by other traces.
3) Input capacitors (C34, C3, C4, C5, and C6) are located very close to the VIN pins.
4) Minimize the total loop area from C34/C6/C5 through U1 + D1.
5) The six ground vias “North” of C3 are placed so they only conduct DC current.
6) The switch node trace (LX1) is very short and just wide enough to carry about 3 A.
7) High frequency currents passing through D1 are directly routed to C34, C6, C5, and C4.
8) The snubber components connect directly from the LX1 node to ground.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 39: VREG capacitors (C8-C14) and PGND connections.
The VREG capacitors are the input bypass capacitors for the synchronous buck.
Place these capacitors so the loop from the VREG to PGND is short and uninterrupted.
Figure 40: Recommended placement of the VREG capacitors and their PGND connection.
1) Place these components on the same layer as the A4408 (U1).
2) Minimize the loop from capacitors C8-C12 to the VREG pin and PGND pin.
3) The ground connection from the capacitors to the PGND pins is uninterrupted.
4) Connect the two PGND pins to the thermal pad (i.e. ground) under the A4408.
5) Note, the LX2 trace (pins 23 and 24) uses a via to avoid interrupting the PGND trace.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 41: Recommended placement and routing of the Boost MOSFET and diode (Q1, D2),
local bypass capacitors (C33, C35), and snubber components (RN3, CN3).
1) Minimize the hot loop between C33/C35 to D2 and to Q2.
2) Place a connection to the ground plane outside the hot loop (see 4 vias next to C35).
3) Include a thermal area on the bottom of the PCB (blue polygon) as thermal relief for Q1.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 42: Synchronous buck output capacitors (C16-C18), snubber (RN2, CN2),
and feedback resistor divider (RFB1, RFB2).
Figure 43: Recommended placement and routing of the synchronous buck inductor (L2),
snubber (RN2, CN2), output capacitors (C16-C18), and feedback resistor divider (RFB1, RFB2).
1) Minimize the length and width of the LX2 trace. The width should accommodate 2.4 AMAX.
2) The LX2 trace is on the bottom layer so the VREG capacitors can connect directly to PGND.
3) The snubber is on the same layer as the inductor and is grounded at PGND.
4) The feedback trace (1V25/FBADJ) is routed to the point of loading and after any filtering (B2).
5) If used, the feedback resistor divider (RFB1, RFB2) must be located near the FBADJ pin.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 44: LDO (V5P) output capacitor and negative clamp diode (C22, D5).
Figure 45: Recommended placement and routing of the LDO (V5P),
output capacitor (C22), and negative clamp diode (D5).
1) Place the output capacitor and negative clamp diode close to the V5P output pin.
2) Connect these two components to the ground plane near the A4408.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 46: The COMP1 (RZ1, CZ1, CP1) and COMP2 (RZ2, CZ2, CP2) components.
Figure 47: Recommended placement and routing of COMP1 and COMP2 components.
1) These components can by placed on the bottom of the PCB, near pins 9 and 20.
2) Place a via very close to pins 9 and 20.
3) Keep noisy traces, like LX1 and LX2, as far away as possible from these components.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Figure 48: The gate drive from LG (pin 33) to the boost MOSFET.
Figure 49: Recommended routing of the gate driver to the boost MOSFET.
1) It is best to keep the gate drive trace (LG) short and on the same layer as U1 and Q1 (i.e. no vias).
2) Here, the trace routes on the top layer and makes a short vertical run under L1.
3) The return path for the gate driver is layer #2, which is a ground plane.
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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INPUT/OUTPUT STRUCTURES
NPOR, POK5V, V5, 3V3, VREG, ENB, ENBAT1,
ENBAT2, FF0, FF1, FB
ADJ
, COMP1, COMP2,
SS1, SS2, FSET/SYNC, TRACK, MODE, WD
IN
,
WD
ENn
, WD
ADJ
, VCC, LG
VCP, CP1, CP2
VIN, LX1, SLEWVREG, LX2
V5P GND, PGND
GND PGND
42 V
V5P
42 V
LX1
VIN
SLEW
9 V
PIN
9 V
LX2
VREG
42 V
VCP
CP2
CP1
6.7 V
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-153 BDT-1)
Dimensions in millimeters
NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
1.10 MAX
0.90 ±0.05
0.15
0.00
0.27
0.17
0.20
0.09
8º
0º
0.60 ±0.15 1.00 REF
C
SEATING
PLANE
C0.10
38X
0.50 BSC
0.25 BSC
21
38
9.70 ±0.10
6.50 ±0.10
4.40 ±0.10 6.40 BSC
GAUGE PLANE
SEATING PLANE
A
B
B
Exposed thermal pad (bottom surface)
3.00 ±0.10
Branded Face
C
6.00
0.50
0.30
1.70
3.00
6.5
38
21
C
PCB Layout Reference View
Terminal #1 mark area
Reference land pattern layout (reference IPC7351 SOP50P640X120-39M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Figure 50: Package LV, 38-Pin eTSSOP
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Watchdog Timer, NPOR, and FF0/FF1
A4408
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Allegro MicroSystems, LLC
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For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– September 23, 2016 Initial release
1 January 27, 2017
Updated Transconductance max value (page 8, 2nd condition),
Pulse-by-Pulse Current Limit max value (page 9, 2nd condition),
Low-Side MOSFET Leakage max value (page 10, 2nd condition),
Transconductance min and max values (page 10, 1st condition),
High-Side MOSFET Pulse-by-Pulse Current Limit max value (page 11).
Deleted High-Side MOSFET Pulse-by-Pulse Current Limit 2nd condition (page 11).
Added footnote to Boost Duty Cycle (LG Pin) 1st condition (page 8).
2 June 22, 2017 Added Input/Output Structures (page 53).
3 September 12, 2017
Corrected Minimum and Maximum Output Voltage symbols (page 8).
Added footnote to SS1 Delay and Ramp Time (page 9).
Added footnote to SS2 to V1V25 Delay Time and V1V25 Ramp Time (page 11).
Updated V1V25 Ramp Time typical value (page 11).
Corrected tSS1(DLY) and tSS2(DLY) symbols (pages 30, 31, 39, 42).
Corrected equation 32 (page 41).
Corrected equation 33 (page 42).
4 September 29, 2017 Updated Thermal Characteristics table (page 2).
5 October 4, 2017
Corrected Hiccup Mode test conditions (page 9).
Updated Adjustable Synchronous Buck Regulator section (page 20).
Updated Bias Supply section (page 23).
6 January 23, 2018 Updated V5 Current Limit minimum value (page 12).
7 January 31, 2019 Minor editorial updates.
Copyright ©2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
