10 LOW Ron CAG13, 13A, 13C, DUAL FET ANALOG GATES 13D, 24, 27, SPST AND DPST 27-10, 42 WILL CONNECT AS SPDT AND DPDT BREAK BEFORE MAKE ACTION PG.1 OF 3 +10V SIGNAL LEVELS WORK FROM DTL, TTL, HNIL AND MOS LOGIC 20 Ver SIGNAL LEVELS AC OR DC WITH CAG42 ELECTRICAL SPECIFICATIONS: Ta =+25C Vcc = +15V, VEE = ~18V (unless otherwise specified) TYPE An CAG24 PARAMETER SYMBOL TEST CONDITIONS MINJ TYP] MAX. MINJ TYPIMAX.| UNITS * Power Drain Pt/Ckt. VIN= + 3V | 65 | 90 ] 5 6 mW * Logic 1 Current lin (1) VIN=+2.4V | 320} 400 | 32 40 rN * Logic 0 Current lin (0) ViIn=+0V {}{ | 50 ~| { 50 LA TYPE ALL EXCEPT CAG27 CAG27,CAG27-10 CAG27-10 PARAMETER SYMBOL TEST CONDITIONS MINI TYP] MAX, MINI TYP.J.MAX.) UNITS * Drain to Gate Capacitance Cadgo VoG=10V, Is=0, f=140KHz _ 6 8 | 18 25 pfd * Source to Gate Capacitance Csgo Vse=10V, |p=0, f=140KHz -| 6 8 | 18 25 pfd * Signal Current Limit ISIG-LIM Vos=2V, Ves=0 10 - _ 100} _ mA Off Leakage Current ID (off) VsiG=Vsic (MIN) | 0.5] 1.0 10.5 } 3.0 nA * Off Leakage Current (Pee) Vsic=Vsic (MIN) _ 1 2 - 1 2 uA SYMBOL (Units) Vsic (V) Rds(Q) Ras(125 C) (2) **ton (usec) **tott (usec) PARAMETER Soe O ANGE ON GESISPARCELON AES e ance| TURN-ON TIME | TURN-OFF TIME TYPE PKG. [DIA] MIN. |TYP{MAX] MIN.TYP.[MAX.} MINJTYP.AMAX.] MINJTYP.[MAX.] MINETYPIMAX. CAG13 TO-100 {| L1 -10 | {+10 | 20 | 35 | 50 | | 100 | 04 40.5 [0.2] 05 CAG13A TQ-100 | L1 10 | | +10 | 20 | 35 | 50 | - | 100 104 {0.5 10.2] 0.5 CAG13C TO-87 {| L2 10 | [+10 |] 20 | 35 | 50 ~ | 4} 100 {04 {0.5 ~ 10.2] 0.5 CAG13D TO-8 L3 10 | +10 20 | 35 | 50 | | 100 |04 40.5 {0.2 ] 0.5 CAG24 TO-8 L3 6 | +10 15 | 25 | 30 -|- 60 {3.0 | 10 110] 10 CAG27 TO-8 L3 6 | +10 3 5 6 -|- 12 | 2.0 |3.0 11.0] 3.0 CAG27-10 TO-8 L3 6 | +10 4 7 10 -|- | 20 |2.0 [3.0 {1.0 | 3.0 CAG42 TO-100 | L1 10 | | +10 20 | 35 | 50 | {100 |0.7 [1.0 }04 | 1.0 * These parameters guaranteed but may not be tested. ** Includes Propagation Delay ew \ TELEDYNE 147 Sherman Street, Cambridge, Mass. 02140 CRYSTALONICS Tel: (617) 491-1670 TWX: 710-320-1196 MAXIMUM RATINGS PARAMETER SYMBOL MIN.ITYP. | MAX. UNITS Operating Temperature Top ~55 | - 14125 C Storage Temperature Tstg -65| - |4+150 C Pos. Supply Voltage Vec 0 15 18 Vv Neg. Supply Voltage VEE -6 |-15 } -18 V The series consists of 2 completely separate FET Analog Switch Circuits capable of switching up to 10V signals and being con- trolled directly from most logic circuits. Besides its inherent zero offset voltage and low Ron the circuit is unique in that it turns off faster than on allowing multiplexing without cross talk. When in the off or open state the FET gate is AC grounded lowering high fre- quency signal feedthrough by at least 10 dB over otherwise equi- valent circuits. Separate Logic grounds allow over +10V_ noise immunity with respect to signal or supply grounds. Logic 1 (>2.4V) opens contacts Logic 0 (<0.6V) closes contacts See Page 12 for other logic connections: NOTES: LOGIC LOGIC GND. 1} The CAG42 will switch AC as well as DC signals. The other circuits may present difficulties when attempting to pass high level AC signals. See ap- plication note Fet Analog Gate fails to switch AC. 2) The CAG13C, CAG13D, CAG24 and CAG27 will have access to the FET gate leads for compensation. 3) The CAG24 is specifically for low power drain applications and is corn- patible with Low Level Logic. 4 It draws approximately 1.0 mA from the signal source. 5 The CAG13A is Direct Coupled for AC switching without compensation. SWITCHING TIMES are measured with a 300 Ohm load. When used as a SPDT switch, the turn-off time may appear longer than specified if switch- ing into a high impedance load. The apparent toff is then actually the sett ling time of the FET capacitance and load impedance. CAG13 thru CAG27-10 (page 2 of 3) PHYSICAL DIMENSIONS ARE IN ACCORDANCE WITH JEDEC TO 8 (TO 6) OUTLINE EXCEPT FOR * CAN HEIGHT & PIN CONFIGURATION ee} 470 MAK je 4 030-130 MAX + r, ceaost me 019 H09 oe bia 2 re ous Tilt TO-87 o7s0 0031 07S 0016 oh ors 0002 14 at 114) PLACES a) 0080 INDEX WP TT + COOOCOO OoNsa Tre 9.005: G00 0.015 an oa = Tye 0020 REF Vee Vec 11 12 EQUIVALENT CIRCUITS Rds 1.0pf Cago Csgo TY Cago TCsgo x2 x2 ID 15K (OFF) vec VEE ON OFF LOGIC CONNECTIONS ON (CLOSED) OFF (OPEN) LOGIC (OV) (+3V) Loaic 0 Loaic 1 DTL/TTL oe t> eh> NORMAL +3V +3V DTL/TTL Logic 1 Logic 0 INVERTED (+3V) (Ov) = = 5 | > MOS Logic 0 Logic 1 (OV) (-10V) O +3V DTL/TTL DOUBLE = THROW LOGIC ON RESISTANCE VS. TEMPERATURE Ros Normalized to 25C Value Ves=0 Ips=10 mA +50 +75 Temperature~(C) Ron Increases 0.7%/ +25 +100 +120 Cc CAG13 Thru CAG27-10 (page 3 of 3) Vsic RANGE VS. Vcc AND VEE 10 VSIG PEAK 6t 30 Rds = LL oO 2 4 YY Rds = 502 1000 8 to 25C Value 8 lott Normalized 3 15 10 5 0 5 VEE SUPPLY VOLTAGES 10 VCC 15 20 OFF LEAKAGE CURRENT VS. TEMPERATURE 7 Y 25 40 so 60 70 Temperature (C) a0 9 100