MB91F585AMGPMC-GTE1 - CYPRESS SEMICONDUCTOR

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MB91580M/S S eries, FR 81S

32-bit Microcontroller Datasheet

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-04665 Rev *A Revised March 29, 2016

MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK

MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK

MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK

This series is a Cypress 32-bit microcontroller for automobile motor control. They use the FR81S CPU that is

compatible with the FR family.

Features

FR81S CPU Core

 32-bit RISC, load/store architecture, pipeline 5-stage

structure

 Maximum operating frequency: 128MHz (Source

oscillation= 4.0MHz, 32 multiplied ( PLL clock

multiplication system) )

 General-purpose register: 32 bits × 16 sets

 16-bit fixed length instructions (basic instructions), 1

instruction per cycle

 Instructions appropriate to embedded applications

 Memory-to-memory transfer instructions

 Bit manipulation instructions

 Barrel shif t instr u cti ons

 High-level language suppor t in struc tio ns

 Function entry/exit instructions

 Register conte nt mult i-load and store inst ructions

 Bit search ins tructio ns

Logical 1 detection, 0 detection, and change-point

detection

 Branch instructions with delay slot

Overhead decrement during branch proce s s

 Register interlock function

Easy assembler writing

 Built-in multiplier and instruction level support

 Signed 32-bit multip lic at io n: 5 cy cle s

 Signed 16-bit multip lic at io n: 3 cy cle s

 Interrupt (PC/PS saving)

6 cycles (16 priority levels)

 The Harvard architecture allows simultaneous

execution of program and data access.

 Instruction compatibility with the FR family

 Built-in memory protection function (MPU)

 Eight protection areas can be specified

commonly for instructions and data.

 Control acces s priv ilege in both privilege mode

and user mode

 Built-in FPU (floating-point operation)

 IEEE754 compli ant

 Floating-point register: 32 bits × 16 sets

Peripheral functions

 Clock generation (SSCG function is available)

 Main oscillation (4 MHz to 20 MHz)

 PLL m ultiplication rate:1 to 32 times

 CR oscill ation

 Oscillation frequency: 100kHz, with frequency

accuracy ± 50% (pre-trimming)

 Trimming is enabled

 To be used as a count clock of hardware

watchdog

 Oscillati on stop feature dur i ng st an dby is not

available

MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F

584AMK/F585AMK

MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F5

84ASK/F585ASK

 Oscillati on stop feature dur i ng st an dby is

available

MB91F583AMG/F584AMG/F585AMG/F583AMH

/F584AMH/F585AMH

MB91F583ASG/F584ASG/F585ASG/F583ASH/

F584ASH/F585ASH

 Built-in program fla sh memory ca pacity

MB91F583: 256 +64 Kby t es

MB91F584: 384 +64 Kby t es

MB91F585: 512 +64 Kby t es

 Built-in data flash (WorkFlash) 64 Kbytes

 Built-in RAM capacity

 Main RAM

MB91F583: 32 Kbyte s

MB91F584: 48 Kbyte s

MB91F585: 48 Kbyte s

 Backup RAM 8 Kbytes

 General-pur po se port:

MB91F583AM/F584AM/F585AM 76 ports

Including eight I2C pseudo open drain

corresponding ports

MB91F583AS/F584AS/F585AS 44ports

Including two I2C pseudo open drain

corresponding ports

Document Number: 002-04665 Rev *A Page 2 of 175

MB91580M/S Series

 DMA controller

 Up to 8 channels can be started simultaneously.

 2 transfer factors (Internal peripheral request and

software)

 External interrupt input

MB91F583AM/F584AM/F585AM: 8 channels

MB91F583AS/F584AS/F585AS: 7 channels

Level ("H" / "L") or edge detection (rising or falling)

enabled

 Multi-function serial commu nic ation (bu ilt-in

transmissi on/receptio n FIFO memor y )

MB91F583AM/F584AM/F585AM: 4 channels

MB91F583AS/F584AS/F585AS: 2 channels

 UART (Asynchronous serial interface)

• Full-duplex double bufferi ng sy stem , 64-byte

transmission FIFO memory, 64-byte reception

FIFO memory

• Parity or no parity is selectable.

• Built-in dedicated baud rate generator

• An external clock can be used as the transfer

clock

• Parity, frame, and overrun error detection

functions provided

• DMA transfer supported

 CSIO (Synchr ono us seri al inte rface)

• Full-duplex double bufferi ng sy stem , 64-byte

transmission FIFO memory, 64-byte reception

FIFO memory

• SPI supported; master and slave systems

supported; 5 to 16, 20, 24, 32-bit dat a leng t h

can be set.

• Built-in dedicated baud rate generator (Master

operation)

• An external clock can be entered. (Slave

operation)

• Overrun error detection function is provid ed.

• Built-in chip selection function

• DMA transfer supported

 LIN interface (v2.1)

• Full-duplex double bufferi ng sy stem , 64-byte

transmission FIFO memory, 64-byte reception

FIFO memory

• LIN protocol revision2.1 supported.

• Master and slave sy ste ms suppor ted

• Framing error and overrun error detection

• LIN sync break generation and detection; LIN

sync delimiter generation

• Built-in dedicated baud rate generator

• An external clock can be adjusted by the

reload counter.

• DMA transfer supported

 I2C

• MB91F583AM/F584AM/F585AM: Supported

for 3 channels: ch.0, ch .2,a nd c h.3

MB91F583AS/F584AS/F585AS: Supported for

1 channel: ch.0

• Full-duplex double bufferi ng sy stem , 64-byte

transmission FIFO memory, 64-byte reception

FIFO memory

• Standard mode (Max. 100 kbps) / high -speed

mode (Max. 400 kbps) supported

• DMA transfer supported (for transmission only)

 CAN contr oller (CAN)

MB91F583AM/F584AM/F585AM: 2 channels

MB91F583AS/F584AS/F585AS: 1 channel

 Transfer speed: Up to 1Mbps

 64-transmission/reception message buffering

 FlexRay controller

MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584A

MJ/F585AMJ/

F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F58

5ASJ: 1 unit (ch.A/ch.B)

 FlexRay Specifications Version 2.1 supported

 Up to 128 message buffers

 8K bytes of message RAM

 Variable length of message buf fer s

 Each message buf fer can be allocated as a part

of reception buffer, transmission buffer or

reception FIFO memory

 Host access to the message buffer via input and

output buffers

 Filtering for slot counter, cycle counter and

channels

 Maskable interrupts are supported

 PPG: 16 bits × 6 channe ls

 Reload timer: 16 bits × 4 channels

 A/D converter (successive approximation type)

 12-bit resolution

MB91F583AM/F584AM/F585AM: 3 units (23

channels)

MB91F583AS/F584AS/F585AS: 3

units (17 channels)

 Conversio n time: 1 µs

 Free-run timer

16 bits × 6 channels (1 channel can be selected for

input capture, and 1 channel for output compare.)

 Input capture: 16 bits × 4 channels (linked to the

free-run timer)

 Output compare: 16 bits × 7 channels (linked to the

free-run timer)

 Wa v ef orm generator: 2 units (7 channels)

 10-bit D/A converter: 1 channel

 Calibration: The hardware watchdog for CR

oscillation drive

The CR oscillation frequency can be trimmed.

Document Number: 002-04665 Rev *A Page 3 of 175

MB91580M/S Series

 Clock Supervisor

 Anomaly supervisory feature (by damaged

quartz, etc.) of external main oscillation (4MHz)

 When anomaly is detected, clock is switched to

CR.

 Up/ down counter: 2 channels

 8/16-bit Up/ down counter

 Base timer: 2 channels

 16-bit timer

 Any of four PWM/PPG/PWC/reload timer

functions can be selected and used.

 As for the functions of PWC and reload tim er, 2

channels of cascade mode can be used as 32-bit

timer.

 CRC generation

 Watchdog timer

 Hardware watchdog

 Software watchdog

 NMI

 Interrupt controller

 Interrupt request batch read

Multiple interrupts from peripherals can be read by a

se ries of r egisters.

 I/O relocation (MB91F583AM/F584AM/F585AM)

Change of pin positio n of peri p heral functions

 Low-pow er consumption mod e

 Sleep/Stop/Watch

 Stop (Power shutdown)/Watch (Power shutdown)

 Power-on reset

 Low-voltage detection reset (external low-voltage

detection)

 Low-voltage detection reset (internal low-voltage

detection)

 Package

MB91F583AM/F584AM/F585AM: LQFP-100

MB91F583AS/F584AS/F585AS: LQFP-64

 CMOS 90 nm technology

 Power supplies

 Single 5V power supply

 The voltage step-down circuit brings the 5.0V

down to generate 1.2V internally

 I/O 5.0V

Document Number: 002-04665 Rev *A Page 4 of 175

MB91580M/S Series

Contents

1. Product Lineup ............................................................................................................................................. 5

2. Pin Assignment ........................................................................................................................................... 11

3. Pin Description ........................................................................................................................................... 13

4. I/O Circuit Type ........................................................................................................................................... 25

5. Handling Precautions ................................................................................................................................. 31

6. Handling Devices ........................................................................................................................................ 34

7. Block Diagram............................................................................................................................................. 37

8. Memory Map ................................................................................................................................................ 39

9. I/O Map ......................................................................................................................................................... 40

10. Interrupt Vector Table ........................................................................................................................... 117

11. Electrical Characteristics ..................................................................................................................... 124

11.1 Absolute Maximum Ratings .................................................................................................................... 124

11.2 DC Characteristics .................................................................................................................................. 127

11.3 AC Characteristics .................................................................................................................................. 134

11.3.1 M ain Clock Timing .............................................................................................................................. 134

11.3.2 Reset inpu t .......................................................................................................................................... 137

11.3.3 Power-on Conditions .......................................................................................................................... 138

11.3.4 Multi-function Serial ............................................................................................................................ 139

11.3.5 Timer Input Timing .............................................................................................................................. 157

11.3.6 Trigger Input Timing ............................................................................................................................ 157

11.3.7 NM I Input Timing ................................................................................................................................. 158

11.3.8 Low-voltage Detection (External Low-voltage Detection).................................................................... 159

11.3.9 Low-voltage Detection (Internal Low-voltage Detection) ..................................................................... 159

11.4 A/D Converter ......................................................................................................................................... 160

11.4.1 Electrical Characteristics .................................................................................................................... 160

11.4.2 Definit ion of Terms .............................................................................................................................. 161

11.4.3 Notes on Using A/D Converter ............................................................................................................ 161

11.5 D/A Converter ......................................................................................................................................... 163

11.6 Flash memory ......................................................................................................................................... 163

11.6.1 Electrical Characteristics .................................................................................................................... 163

11.6.2 Notes .................................................................................................................................................. 164

12. Example Characteristics ...................................................................................................................... 165

13. Ordering Information ............................................................................................................................ 169

14. Package Dimensions ............................................................................................................................ 170

15. Major Changes ...................................................................................................................................... 172

Document Number: 002-04665 Rev *A Page 5 of 175

MB91580M/S Series

1. Product Lineup

MB91580AM Series Product Lineup Comparison

 Memory size

Items

MB91F583AMG

MB91F583AMH

MB91F583AMJ

MB91F583AMK

MB91F584AMG

MB91F584AMH

MB91F584AMJ

MB91F584AMK

MB91F585AMG

MB91F585AMH

MB91F585AMJ

MB91F585AMK

Flash memory capacity (program ) 256+64 Kbytes 384+64 Kbytes 512+64 K byt es

Flash memory capacity (work) 64 Kbytes

RAM capacity (main) 32 Kbytes 48 K byt es 48 K byt es

RAM capacity (backup) 8 Kbytes

 Function

Items MB91F583AMG

MB91F584AMG

MB91F585AMG

MB91F583AMH

MB91F584AMH

MB91F585AMH

MB91F583AMJ

MB91F584AMJ

MB91F585AMJ

MB91F583AMK

MB91F584AMK

MB91F585AMK

System clock

On-chip PLL clock multiplication system

(Up to 32 times of multiplication)

Minimum instruct i on execution t ime: 7.81ns

(128MHz, source oscillat i on 4MHz × 32 times of multiplication)

CR oscillation Provided

Oscillation stop feature

during standby Provided Provided Not provided Not provided

External bus int erface Not provided

DMA transfer 8 channels

16-bit base timer 2 channels

Free-run timer 6 channels

Input capture 4 channels

Output compare 7 channels

Waveform generator 2 units (7 channels)

16-bit reload timer 4 channels

PPG 6 channels

External interrupt 8 channels

A/D converter 3 units (23 channels)

R/D converter Not provided

D/A converter Provided

Up/ down counter 2 channels

Multi-function serial interface 4 channels

CAN 64msb × 2 channels (ch.0/ch.1)

FlexRay 128msb ×

1 unit

(ch.A / ch.B) Not provided 128msb ×

1 unit

(ch.A / ch.B) Not provided

Software watchdog Provided

Hardware watchdog Provided

Document Number: 002-04665 Rev *A Page 6 of 175

MB91580M/S Series

Items MB91F583AMG

MB91F584AMG

MB91F585AMG

MB91F583AMH

MB91F584AMH

MB91F585AMH

MB91F583AMJ

MB91F584AMJ

MB91F585AMJ

MB91F583AMK

MB91F584AMK

MB91F585AMK

CRC generation 2 channels

Low-voltage detection reset

(internal low-voltage detection) Provided

Low-voltage detection reset

(external low-voltage

detection) Provided

Device package LQFP-100

Debug interfac e Built-in OCD (On Chip Debug Unit)

Document Number: 002-04665 Rev *A Page 7 of 175

MB91580M/S Series

MB91580AS Series Product Lineup Comparison

 Memory size

Items

MB91F583ASG

MB91F583ASH

MB91F583ASJ

MB91F583ASK

MB91F584ASG

MB91F584ASH

MB91F584ASJ

MB91F584ASK

MB91F585ASG

MB91F585ASH

MB91F585ASJ

MB91F585ASK

Flash memory capacity (program) 256+64 Kbytes 384+64 K byt es 512+64 Kbytes

Flash memory capacity (work) 64 Kbytes

RAM capacity (main) 32 Kbytes 48 K byt es 48 K byt es

RAM capacity (backup) 8 Kbytes

 Function

Items

MB91F583ASG

MB91F584ASG

MB91F585ASG

MB91F583ASH

MB91F584ASH

MB91F585ASH

MB91F583ASJ

MB91F584ASJ

MB91F585ASJ

MB91F583ASK

MB91F584ASK

MB91F585ASK

System clock

On-chip PLL clock multiplication system

(Up to 32 times of multiplication)

Minimum instruct i on execution t ime: 7.81ns

(128MHz, source oscillat i on 4MHz × 32 times of multiplication)

CR oscillation Provided

Oscillation stop feature

during standby Provided Provided Not provided Not provided

External bus int erface Not provided

DMA transfer 8 channels

16-bit base timer 2 channels

Free-run timer 6 channels

Input capture 4 channels

Output compare 7 channels

Waveform generator 2 units (7 channels)

16-bit reload timer 4 channels

PPG 6 channels

External interrupt 7 channels

A/D converter 3 units (17 channels)

R/D converter Not provided

D/A converter Provided

Up/ down counter 2 channels

Multi-function serial interface 2 channels

CAN 64msb × 1 channel (ch.0)

FlexRay 128msb ×

1unit

(ch.A / ch.B) Not provided 128msb ×

1unit

(ch.A / ch.B) Not provided

Software watchdog Provided

Hardware watchdog Provided

CRC generation 2 channels

Document Number: 002-04665 Rev *A Page 8 of 175

MB91580M/S Series

Items MB91F583ASG

MB91F584ASG

MB91F585ASG

MB91F583ASH

MB91F584ASH

MB91F585ASH

MB91F583ASJ

MB91F584ASJ

MB91F585ASJ

MB91F583ASK

MB91F584ASK

MB91F585ASK

Low-voltage detection reset

(internal low-voltage detection) Provided

Low-voltage detection reset

(external low-voltage

detection) Provided

Device package LQFP-64

Debug interfac e Built-in OCD (On Chip Debug Unit)

Document Number: 002-04665 Rev *A Page 9 of 175

MB91580M/S Series

MB91580L Series Product Lineup Comparison

 Memory size

Items

MB91F585LA

MB91F585LB

MB91F585LC

MB91F585LD

MB91F586LA

MB91F586LB

MB91F586LC

MB91F586LD

MB91F587LA

MB91F587LB

MB91F587LC

MB91F587LD

Flash memory capacity (program) 512+64 Kbytes 768+64 K byt es 1024+64 Kbytes

Flash memory capacity (work) 64 Kbytes

RAM capacity (main) 48 Kbytes 64 K byt es 96 Kbytes

RAM capacity (backup) 8 Kbytes

 Function

Items MB91F585LA

MB91F586LA

MB91F587LA

MB91F585LB

MB91F586LB

MB91F587LB

MB91F585LC

MB91F586LC

MB91F587LC

MB91F585LD

MB91F586LD

MB91F587LD

System clock

On-chip PLL clock multiplication system

(Up to 32 times of multiplica tion )

Minimum instruct i on execution t ime: 7.81ns

(128MHz, source oscillat i on 4MHz × 32 times of multiplication)

CR oscillation Provided

Oscillation stop feature

during standby Provided Provided Not provided Not provided

External bus int erface Not provided A ddress: 22 bits

Data: 16 bits Not provided Address: 22 bits

Data: 16 bits

DMA transfer 8 channels

16-bit base timer 2 channels

Free-run timer 6 channels

Input capture 8 channels

Output compare 12 channels

Waveform generator 2 units (12 channels)

16-bit reload timer 4 channels

PPG 24 channels

External interrupt 8 channels

A/D converter 3 units (24 channels)

R/D converter Provided Not provided Provided Not provided

D/A converter Not provided Provided Not provided Provided

Up/ down counter 2 channels

Multi-function serial interface 5 channels

CAN 64 msb × 3 channels (ch.0/ch.1/ch.2)

FlexRay 128 msb × 1 unit (ch.A / ch.B)

Software watchdog Provided

Hardware watchdog Provided

CRC generation 1 channel

Document Number: 002-04665 Rev *A Page 10 of 175

MB91580M/S Series

Items MB91F585LA

MB91F586LA

MB91F587LA

MB91F585LB

MB91F586LB

MB91F587LB

MB91F585LC

MB91F586LC

MB91F587LC

MB91F585LD

MB91F586LD

MB91F587LD

Low-voltage detection reset

(internal low-voltage detection) Provided

Low-voltage detection reset

(external low-voltage detection) Provided

Device package LQFP-144

Debug interfac e Built-in OCD (On Chip Debug Unit)

Note: For details on the MB91580L series, see the "MB91580L Series HARDWARE MANUAL".

Document Number: 002-04665 Rev *A Page 11 of 175

MB91580M/S Series

2. Pin Assignment

LQFP-100 Pin A ssignment MB91F583AM/F584AM/F585AM

(TOP VIEW)

VCC5

P070/TIN0/INT3

P047/TOT0/INT2/ADTG2

P046/ADTG0/MM

P087

P086

P085/SCS3

VSS

P084/SCK3

P083/SOT3

P082/SIN3

RSTX

P045/RX0/INT1

P044/TX0

VSS

P081/SCK0_1

P080/SOT0_1

P043/SIN0_1/ADTG1/MONCLK

DEBUGIF

VCC5

100

VSS 1

P071/TIN1/AIN0/INT4 3

P001 4

P072/TOT1/BIN0/RTO6 5

P050/RTO5/ZIN0 6

P002 7

P051/RTO4/AIN1/FRCK5 8

P0039

P052/RTO3/BIN1/FRCK4 10

69 P064/SCK2

P004 11

68 P037/AN8

P053/RTO2/ZIN1/FRCK3 12

67 NMIX

P005 13

66 P063/SOT2

P054/RTO1/FRCK2 14

65 P062/SIN2

64 P036/AN9/TIOA0/TIN2

63 P035/AN10/TIOB0/TOT2

P006 15

75 VSS

P055/RTO0/FRCK1 16

P007 17

62 P034/AN11/TIOA1/TIN3

VCC5 25

61 P033/AN12/TIOB1/TOT3

60 P061/TX1

P011/AN1/IN1 20

P010/AN0/IN0 19

P056/DTTI0/FRCK0 18 59 P060/RX1/INT7

P012/AN2/IN2 21

P013/AN3/IN3 22

P014/AN4/TRG1 23

P015/AN5 24

55 P032/AN13

54 P031/AN14

53 P030/DAOUT

52 P097/AN23

58 AVCC1

57 AVRH1

56 AVSS1/AVRL1

51VSS

P016/AN6/INT6

AVCC0

P017/AN7/INT5

AVRH0

AVSS0/AVRL0

P090/AN16

VSS

P091/AN17

P092/AN18

P020/SCK1/TRG0

P021/SIN1/TXENB/INT0

P022/SOT1/RXDB

P023/SCS1/TXDB

P024/PPG0/STOPWT

P025/PPG1/TXENA

P026/PPG2/RXDA

P027/PPG3/TXDA

P093/AN19/PPG4

P094/AN20/PPG5

P095/AN21

P096/AN22

P100

P101

P102

VCC5

LQFP-100

MD1

MD0

72 P041/SCK0_0

71 P040/SOT0_0

70 P065/SCS2

74 P042/SIN0_0

73 P066

P000 2

(FPT-100P-M20)

Document Number: 002-04665 Rev *A Page 12 of 175

MB91580M/S Series

LQFP-64 Pin A ssignment MB91F583AS/F584AS/F585AS

(TOP VIEW)

VCC5

P070/TIN0/INT3

P047/TOT0/INT2/ADTG2

P046/ADTG0/MM

VSS

RSTX

P045/RX0/INT1

P044/TX0

VSS

MD1

MD0

P043/ADTG1/MONCLK

DEBUGIF

VSS 1

P072/TOT1/BIN0/RTO6 3

P050/RTO5/ZIN0 4

P051/RTO4/AIN1/FRCK5 5

P052/RTO3/BIN1/FRCK4 6

P053/RTO2/ZIN1/FRCK3 7

P054/RTO1/FRCK2 8

P055/RTO0/FRCK1 9

P056/DTTI0/FRCK0 10

42 P035/AN10/TIOB0/TOT2

P010/AN0/IN0 11

41 P034/AN11/TIOA1/TIN3

P011/AN1/IN1 12

40 P033/AN12/TIOB1/TOT3

P012/AN2/IN2 13

P013/AN3/IN3 14 36 P032/AN13

P014/AN4/TRG1 15

38 AVRH1

37 AVSS1/AVRL1

33VSS

39 AVCC1

P015/AN5 16

35 P031/AN14

34 P030/DAOUT

AVCC0

P017/AN7/INT5

AVRH0

AVSS0/AVRL0

P020/SCK1/TRG0

P021/SIN1/TXENB/INT0

P016/AN6/INT6

P022/SOT1/RXDB

P023/SCS1/TXDB

P024/PPG0/STOPWT

P025/PPG1/TXENA

P026/PPG2/RXDA

P027/PPG3/TXDA

P093/AN19/PPG4

P094/AN20/PPG5

VCC5

LQFP-64

45 P037/AN8

44 NMIX

43 P036/AN9/TIOA0/TIN2

47 P041/SCK0_0

48 P042/SIN0_0

46 P040/SOT0_0

P071/TIN1/AIN0/INT4 2

(FPT-64P-M24)

Document Number: 002-04665 Rev *A Page 13 of 175

MB91580M/S Series

3. Pin Description

MB91F583AM/F584AM/F585AM

Pin No. Pin name I/O circuit

type* Function

83 X0 A Main clock oscill ation i nput pin

84 X1 Main cl ock osci l l ation output pi n

67 NMIX B Interrupt input pin without mask

88 RSTX B External reset input pin

81 MD0 C Mode pin 0 (with high-voltage control)

82 MD1 C Mode pin 1 (with high-voltage control)

2 P000 D General-purpose I /O port

4 P001 D General-purpose I /O port

7 P002 D General-purpose I /O port

9 P003 D General-purpose I /O port

11 P004 D General-purpose I /O port

13 P005 D General-purpose I /O port

15 P006 D General-purpose I /O port

17 P007 D General-purpose I /O port

P010

General-purpose I/ O port

IN0 16-bit i nput c apture ch.0 external pulse input pin

AN0 ADC analog 0 input pin

P011

General-purpose I/ O port

IN1 16-bit i nput c apture ch.1 external pulse input pin

AN1 ADC analog 1 input pin

P012

General-purpose I/ O port

IN2 16-bit i nput c apture ch.2 external pulse input pin

AN2 ADC analog 2 input pin

P013

General-purpose I/ O port

IN3 16-bit i nput c apture ch.3 external pulse input pin

AN3 ADC analog 3 input pin

P014

General-purpose I/ O port

TRG1 PPG ch.4, ch.5 external trigger

AN4 ADC analog 4 input pin

24 P015 F General-purpose I/ O port

AN5 ADC analog 5 input pin

P016

General-purpose I/ O port

AN6 ADC analog 6 input pin

INT6 INT6 external int errupt i nput pin

Document Number: 002-04665 Rev *A Page 14 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

P017

General-purpose I/ O port

AN7 ADC analog 7 input pin

INT5 INT5 external int errupt i nput pin

P020

General-purpose I/ O port

SCK1 Multi-function serial ch.1 clock I/O pin

TRG0 PP G ch.0 to ch.3 external trigger

P021

General-purpose I/ O port

SIN1 Multi-f unction serial ch.1 serial data input pi n

TXENB FlexRay ch.B operat i on enabl e output pin

INT0 INT0 external int errupt i nput pin

P022

General-purpose I/ O port

SOT1 Multi-function serial ch.1 serial data output pin

RXDB FlexRay c h.B data input pin

P023

General-purpose I/ O port

SCS1 Multi-func tion serial ch. 1 serial c hip select I/O pin

TXDB Fl exRay c h.A operation enable output pin

P024

General-purpose I/ O port

PPG0 PPG ch.0 output pin

STOPWT FlexRay Stopwatch input pin

P025

General-purpose I/ O port

PPG1 PPG ch.1 output pin

TXENA FlexRay ch.A operat i on enabl e output pin

P026

General-purpose I/ O port

PPG2 PPG ch.2 output pin

RXDA FlexRay c h.A data input pin

P027

General-purpose I/ O port

PPG3 PPG ch.3 output pin

TXDA Fl exRay c h.A dat a output pin

53 P030 M General-purpose I/ O port

DAOUT DAC analog output pin

54 P031 F General-purpose I/ O port

AN14 ADC analog 14 i nput pin

Document Number: 002-04665 Rev *A Page 15 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

55 P032 F General-purpose I/ O port

AN13 ADC analog 13 i nput pin

P033

General-purpose I/ O port

TIOB1 Base timer ch.1 TIOB input pin

TOT3 Reload timer ch.3 output pin

AN12 ADC analog 12 i nput pin

P034

General-purpose I/ O port

TIOA1 Base timer ch.1 TIOA I/O pin

TIN3 Reload tim er ch.3 event input pin

AN11 ADC analog 11 i nput pin

P035

General-purpose I/ O port

TIOB0 Base timer ch.0 TIOB input pin

TOT2 Reload timer ch.2 output pin

AN10 ADC analog 10 i nput pin

P036

General-purpose I/ O port

TIOA0 Base timer ch.0 TIOA output pin

TIN2 Reload tim er ch.2 event input pin

AN9 ADC analog 9 input pin

68 P037 F General-purpose I/ O port

AN8 ADC analog 8 input pin

P040

General-purpose I/ O port

SOT0_0 Multi-function serial ch.0 serial data output pin (0)/

I2C ch.0 serial data I/O pin (SDA)

P041

General-purpose I/ O port

SCK0_0 Multi-function serial ch.0 clock I/O pin (0)/

I2C c h.0 clock I/ O pin (SC L)

74 P042 D General-purpos e I/O port

SIN0_0 Multi-function serial ch.0 serial data input pin (0)

P043

General-purpose I/ O port

SIN0_1 Multi-function serial ch.0 serial data input pin (1)

ADTG1 A/D converter ch.8 to ch.14 external trigger input pin

MONCLK Clock monitor output pin

86 P044 D General-purpos e I/O port

TX0 CA N transmission data 0 output pin

Document Number: 002-04665 Rev *A Page 16 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

P045

General-purpose I/ O port

RX0 CAN reception dat a 0 input pin

INT1 INT1 external int errupt i nput pin

P046

General-purpose I/ O port

ADTG0 A/D converter ch.0 to ch.7 external trigger input pin

MM Clock s upervisor m ai n clock stop detection output pin

P047

General-purpose I/ O port

TOT0 Reload timer ch.0 output pin

INT2 INT2 external int errupt i nput pin

ADTG2 A/D converter ch.16-ch.23 external trigger input pin

P050

General-purpose I/ O port

RTO5 Waveform generator ch.5 output pin

ZIN0 Up/down counter ch. 0 ZIN input pin

P051

General-purpose I/ O port

RTO4 W aveform generator ch.4 output pin

AIN1 Up/down counter ch.1 AIN input pin

FRCK5 Free-run t imer ch.5 external clock input pin

P052

General-purpose I/ O port

RTO3 Waveform generator ch.3 output pin

BIN1 Up/down counter ch.1 BIN input pin

FRCK4 Free-run t imer ch.4 external clock input pin

P053

General-purpose I/ O port

RTO2 Waveform generator ch.2 output pin

ZIN1 Up/down counter ch. 1 ZIN input pin

FRCK3 Free-run t imer ch.3 external clock input pin

P054

General-purpose I/ O port

RTO1 Waveform generator ch.1 output pin

FRCK2 Free-run t imer ch.2 external clock input pin

P055

General-purpose I/ O port

RTO0 Waveform generator ch.0 output pin

FRCK1 Free-run t imer ch.1 external clock input pin

P056

General-purpose I/ O port

DTTI0 Waveform generator output stop signal input pin 0

FRCK0 Free-run t imer ch.0 external clock input pin

P060

General-purpose I/ O port

RX1 CAN reception dat a 1 input pin

INT7 INT7 external int errupt i nput pin

Document Number: 002-04665 Rev *A Page 17 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

60 P061 D General-purpose I /O port

TX1 CA N transmission data 1 output pin

65 P062 D General-purpos e I/O port

SIN2 Multi-f unction serial ch.2 serial data input pi n

P063

General-purpose I/ O port

SOT2 Multi-function seri al ch. 2 serial data output pin/

I2C ch.2 serial data I/O pin (SDA)

P064

General-purpose I/ O port

SCK2 Multi-function serial ch.2 clock I/O pin/

I2C c h.2 clock I/ O pin (SC L)

70 P065 D General-purpos e I/O port

SCS2 Multi-function serial ch.2 serial chip select I/O pin

73 P066 D General-purpose I /O port

P070

General-purpose I/ O port

TIN0 Reload tim er ch.0 event input pin

INT3 INT3 external int errupt i nput pin

P071

General-purpose I/ O port

TIN1 Reload tim er ch.1 event input pin

AIN0 Up/down counter ch.0 AIN input pin

INT4 INT4 external int errupt i nput pin

P072

General-purpose I/ O port

TOT1 Reload timer ch.1 output pin

BIN0 Up/down counter ch.0 BIN input pin

RTO6 Waveform generator ch.6 output pin

P080

General-purpose I/ O port

SOT0_1 Multi-function seri al ch. 0 serial data output pin (1)/

I2C ch.0 serial data I/O pin (1) (SDA)

P081

General-purpose I/ O port

SCK0_1 Multi-function serial ch.0 clock I/O pin (1)/

I2C ch.0 clock I/O pin (1) (SCL)

89 P082 D General-purpos e I/O port

SIN3 Multi-f unction serial ch.3 serial data input pi n

P083

General-purpose I/ O port

SOT3 Multi-function seri al ch. 3 serial data output pin/

I2C ch.3 serial data I/O pin (SDA)

P084

General-purpose I/ O port

SCK3 Multi-function serial ch.3 clock I/O pin/

I2C c h.3 clock I/ O pin (SC L)

Document Number: 002-04665 Rev *A Page 18 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

94 P085 D General-purpos e I/O port

SCS3 Multi-func tion serial ch. 3 serial c hip select I/O pin

95 P086 D General-purpose I /O port

96 P087 D General-purpose I /O port

32 P090 F General-purpose I/ O port

AN16 ADC analog 16 i nput pin

33 P091 F General-purpose I/ O port

AN17 ADC analog 17 i nput pin

34 P092 F General-purpose I/ O port

AN18 ADC analog 18 i nput pin

P093

General-purpose I/ O port

PPG4 PPG ch.4 output pin

AN19 ADC analog 19 i nput pin

P094

General-purpose I/ O port

PPG5 PPG ch.5 output pin

AN20 ADC analog 20 i nput pin

45 P095 F General-purpose I/ O port

AN21 ADC analog 21 i nput pin

46 P096 F General-purpose I/ O port

AN22 ADC analog 22 i nput pin

52 P097 F General-purpose I/O port

AN23 ADC analog 23 i nput pin

47 P100 D General-purpose I /O port

48 P101 D General-purpose I /O port

49 P102 D General-purpose I /O port

77 DEBUGIF I DEBUG I/F pin

28 AVCC0 - A/D converter analog power supply

58 AVCC1 - A/D converter analog power supply

30 AVRH0 - A/D converter upper limit reference voltage

57 AVRH1 - A/D converter upper limit reference voltage

31 AVSS0 - A/D converter GND

AVRL0 A/D converter lower limit referenc e voltage

56 AVSS1 - A/D converter GND

AVRL1 A/D converter lower limit referenc e voltage

93 C - External capacity c onnect i on output pin

25, 50, 76,

100 VCC5 - +5.0V power supply

Document Number: 002-04665 Rev *A Page 19 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

1, 26, 51,

75, 85, 92 VSS - GND

* For I/O circuit types, see 4 I/O Circuit T ype

Document Number: 002-04665 Rev *A Page 20 of 175

MB91580M/S Series

MB91F583AS/F584AS/F585AS

Pin No. Pin name I/O circuit

type* Function

53 X0 A Main clock oscill ation i nput pin

54 X1 Main cl ock osci l l ation output pi n

44 NMIX B Interrupt input pin without mask

58 RSTX B External reset input pin

51 MD0 C Mode pin 0 (with high-voltage control)

52 MD1 C Mode pin 1 (with high-voltage control)

P010

General-purpose I/ O port

IN0 16-bit i nput c apture ch.0 external pulse input pin

AN0 ADC analog 0 input pin

P011

General-purpose I/ O port

IN1 16-bit i nput c apture ch.1 external pulse input pin

AN1 ADC analog 1 input pin

P012

General-purpose I/ O port

IN2 16-bit i nput c apture ch.2 external pulse input pin

AN2 ADC analog 2 input pin

P013

General-purpose I/ O port

IN3 16-bit i nput c apture ch.3 external pulse input pin

AN3 ADC analog 3 input pin

P014

General-purpose I/ O port

TRG1 PP G ch.4, ch.5 external tri gger

AN4 ADC analog 4 input pin

16 P015 F General-purpose I/ O port

AN5 ADC analog 5 input pin

P016

General-purpose I/ O port

AN6 ADC analog 6 input pin

INT6 INT6 external int errupt i nput pin

P017

General-purpose I/ O port

AN7 ADC analog 7 input pin

INT5 INT5 external int errupt i nput pin

P020

General-purpose I/ O port

SCK1 Multi-function serial ch.1 clock I/O pin

TRG0 PP G ch.0 to ch.3 external trigger

P021

General-purpose I/ O port

SIN1 Multi-f unction serial ch.1 serial data input pi n

TXENB FlexRay ch.B operat i on enabl e output pin

INT0 INT0 external int errupt i nput pin

Document Number: 002-04665 Rev *A Page 21 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

P022

General-purpose I/ O port

SOT1 Multi-function seri al ch. 1 serial data output pin

RXDB FlexRay c h.B data input pin

P023

General-purpose I/ O port

SCS1 Multi-function serial c h.1 serial chip select I/O pin

TXDB Fl exRay c h.B dat a output pin

P024

General-purpose I/ O port

PPG0 PPG ch.0 output pin

STOPWT FlexRay Stopwatch input pin

P025

General-purpose I/ O port

PPG1 PPG ch.1 output pin

TXENA FlexRay ch.A operat i on enabl e output pin

P026

General-purpose I/ O port

PPG2 PPG ch.2 output pin

RXDA FlexRay c h.A data input pin

P027

General-purpose I/ O port

PPG3 PPG ch.3 output pin

TXDA Fl exRay c h.A dat a output pin

34 P030 M General-purpose I/ O port

DAOUT DAC analog output pin

35 P031 F General-purpose I/ O port

AN14 ADC analog 14 i nput pin

36 P032 F General-purpose I/ O port

AN13 ADC analog 13 i nput pin

P033

General-purpose I/ O port

TIOB1 Base timer ch.1 TIOB input pin

TOT3 Reload timer ch.3 output pin

AN12 ADC analog 12 i nput pin

P034

General-purpose I/ O port

TIOA1 Base timer ch.1 TIOA I/O pin

TIN3 Reload tim er ch.3 event input pin

AN11 ADC analog 11 i nput pin

P035

General-purpose I/ O port

TIOB0 Base timer ch.0 TIOB input pin

TOT2 Reload timer ch.2 output pin

AN10 ADC analog 10 i nput pin

Document Number: 002-04665 Rev *A Page 22 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

P036

General-purpose I/ O port

TIOA0 Base timer ch.0 TIOA output pin

TIN2 Reload tim er ch.2 event input pin

AN9 ADC analog 9 input pin

45 P037 F General-purpose I/ O port

AN8 ADC analog 8 input pin

46 P040 H General-purpos e I/O port

SOT0_0 Multi-function serial ch.0 serial data output pin(0)/

I2C ch.0 serial data I/O pin (0) (SDA)

47 P041 H General-purpos e I/O port

SCK0_0 Multi-function serial ch.0 clock I/O pin (0)/

I2C ch.0 clock I/O pin (0) (SCL)

48 P042 D General-purpos e I/O port

SIN0_0 Multi-function serial ch.0 serial data input pin (0)

P043

General-purpose I/ O port

ADTG1 A/D converter ch.8 to ch.14 external trigger input pin

MONCLK Clock monitor output pin

56 P044 D General-purpos e I/O port

TX0 CA N transmission data 0 output pin

P045

General-purpose I/ O port

RX0 CAN reception dat a 0 input pin

INT1 INT1 external interrupt i nput pin

P046

General-purpose I/ O port

ADTG0 A/D converter ch.0 to ch.7 external trigger input pin

MM Clock s upervisor m ai n clock stop detection output pin

P047

General-purpose I/ O port

TOT0 Reload timer ch.0 output pin

INT2 INT2 external int errupt i nput pin

ADTG2 A/D converter ch.19 to ch.20 external trigger input pin

P050

General-purpose I/ O port

RTO5 Waveform generator ch.5 output pin

ZIN0 Up/down counter ch. 0 ZIN input pin

P051

General-purpose I/O port

RTO4 Waveform generator ch.4 output pin

AIN1 Up/down counter ch.1 AIN input pin

FRCK5 Free-run t imer ch.5 external clock input pin

Document Number: 002-04665 Rev *A Page 23 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

P052

General-purpose I/ O port

RTO3 Waveform generator ch.3 output pin

BIN1 Up/down counter ch.1 BIN input pin

FRCK4 Free-run t imer ch.4 external clock input pin

P053

General-purpose I/ O port

RTO2 Waveform generator ch.2 output pin

ZIN1 Up/down counter ch. 1 ZIN input pin

FRCK3 Free-run t imer ch.3 external clock input pin

P054

General-purpose I/ O port

RTO1 Waveform generator ch.1 output pin

FRCK2 Free-run t imer ch.2 external clock input pin

P055

General-purpose I/ O port

RTO0 Waveform generator ch.0 output pin

FRCK1 Free-run timer ch.1 external clock input pi n

P056

General-purpose I/ O port

DTTI0 Waveform generator output stop signal input pin 0

FRCK0 Free-run t imer ch.0 external clock input pin

P070

General-purpose I/ O port

TIN0 Reload tim er ch.0 event input pin

INT3 INT3 external int errupt i nput pin

P071

General-purpose I/ O port

TIN1 Reload tim er ch.1 event input pin

AIN0 Up/down counter ch.0 AIN input pin

INT4 INT4 external int errupt i nput pin

P072

General-purpose I/ O port

TOT1 Reload timer ch.1 output pin

BIN0 Up/down counter ch.0 BIN input pin

RTO6 Waveform generator ch.6 output pin

P093

General-purpose I/ O port

PPG4 PPG ch.4 output pin

AN19 ADC analog 19 i nput pin

P094

General-purpose I/ O port

PPG5 PPG ch.5 output pin

AN20 ADC analog 20 i nput pin

49 DEBUGIF I DEBUG I/F pin

18 AVCC0 - A/D converter analog power supply

39 AVCC1 - A/D converter analog power supply

Document Number: 002-04665 Rev *A Page 24 of 175

MB91580M/S Series

Pin No. Pin name I/O circuit

type* Function

20 AVRH0 - A/D converter upper limit reference volt age

38 AVRH1 - A/D converter upper limit reference voltage

21 AVSS0 - A/D converter GND

AVRL0 A/D converter lower limit referenc e voltage

37 AVSS1 - A/D converter GND

AVRL1 A/D converter lower limit referenc e voltage

60 C - External capacity c onnect i on output pin

32, 64 VCC5 - +5.0V power supply

1, 33, 55, 59 VSS - GND

* For I/O circuit types, see 4 I/O Circuit T ype

Document Number: 002-04665 Rev *A Page 25 of 175

MB91580M/S Series

4. I/O Circuit Ty p e

Type Circuit Remarks

Clock input

Standby control signal

Oscillation feedback resistor: Approx. 1

MΩ

Pull-up resistor

CMOS hysteresis input

 CMOS hysteresis input

 With 50 kΩ pull-up resistor

N-ch Mode input

High withstand voltage mode

input

High withstand voltage control

N-ch

 Schmitt input

 With high withstand voltage control

Document Number: 002-04665 Rev *A Page 26 of 175

MB91580M/S Series

Type Circuit Remarks

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

P-ch P-ch

N-ch

 General-pur po se I/O port

 CMOS level output

IOH=-2/-5mA, IOL=2/5mA

 With 50kΩ pull-up resistor control

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

 Automotive input (0.8Vcc/0.5Vcc)

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

P-ch P-ch

N-ch

 General-pur po se I/O port

 CMOS level output

IOH=-2/-5mA, IOL=2/5mA

 With 50 kΩ pull-up resistor contr ol

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

During sta ndby, the input value

retains the previous value.

 Automotive input (0.8Vcc/0.5Vcc)

During sta ndby, the input value

retains the previous value.

Document Number: 002-04665 Rev *A Page 27 of 175

MB91580M/S Series

Type Circuit Remarks

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

Analog input

P-ch P-ch

N-ch

 With analog input, general-purpose

I/O port

 CMOS level output

IOH=-2/-5mA, IOL=2/5mA

 With 50 kΩ pull-up resistor contr ol

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

 Automotive input (0.8Vcc/0.5Vcc)

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

Analog input

P-ch P-ch

N-ch

 With analog input, general-purpose

I/O port

 CMOS level output

IOH=-2/-5mA, IOL=2/5mA

 With 50 kΩ pull-up resistor contr ol

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

During sta ndby, the input value

retains the previous value.

 Automotive input (0.8Vcc/0.5Vcc)

During sta ndby, the input value

retains the previous value.

Document Number: 002-04665 Rev *A Page 28 of 175

MB91580M/S Series

Type Circuit Remarks

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

P-ch P-ch

N-ch

 With I2C, general-purp os e I/O por t

 CMOS level output

IOH=-3mA, IOL= 3mA (at I2C output)

IOH=-2/-5mA, IOL=2/5mA (other than

above)

 With 50 kΩ pull-up resistor contr ol

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

 Automotive input (0.8Vcc/0.5Vcc)

TTL schmitt input

Digital output

Open drain I/O

Document Number: 002-04665 Rev *A Page 29 of 175

MB91580M/S Series

Type Circuit Remarks

Pull-up control

Digital output

FlexRay input

Automotive input

Standby control

P-ch P-ch

N-ch

Analog output

 With analog output,

general-purpose I/O port

 CMOS level output

IOH=-2/-4mA, IOL=2/4mA

 With 50 kΩ pull-up resistor contr ol

 FlexRay input (0.7Vcc/0.3Vcc)

 Automotive input (0.8Vcc/0.5Vccc)

Pull-up control

Digital output

FlexRay input

Automotive input

Standby control

P-ch P-ch

N-ch

Analog output

 With analog output,

general-purpose I/O port

 CMOS level output

IOH=-2/-4mA, IOL=2/4mA

 With 50 kΩ pull-up resistor contr ol

 FlexRay input (0.7Vcc/0.3Vcc)

During sta ndby, the input value

retains the previous value.

 Automotive input (0.8Vcc/0.5Vcc)

During sta ndby, the input value

retains the previous value.

Document Number: 002-04665 Rev *A Page 30 of 175

MB91580M/S Series

Type Circuit Remarks

Pull-up control

Digital output

CMOS hysteresis input

Automotive input

Standby control

P-ch P-ch

N-ch

D/A converter output

 With D/A converter output,

general-purpose I/O port

 CMOS level output

IOH=-2/-5mA, IOL=2/5mA

 With 50 kΩ pull-up resistor contr ol

 CMOS hysteresis input

(0.7Vcc/0.3Vcc)

 Automotive input (0.8Vcc/0.5Vcc)

Document Number: 002-04665 Rev *A Page 31 of 175

MB91580M/S Series

5. Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the

conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions

that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress

semicondu ctor dev ic es.

5.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

 Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in

excess of cert ain established limits, called absolute maximum ratings. Do not exceed these ratings.

 Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's

electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges

may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their sales representative

beforehand.

 Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply

and input/output functions.

1. Preventing Over-Voltage and Ov er-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause

deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to

prevent such overv oltage or over-current conditions at the design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause

large current flows. Such conditions if present for extended periods of time can damage the device.

Therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such

pins should be connected through an appropriate resistance to a power supply pin or ground pin.

 Latch-up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. W hen subjected

to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing

large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is

called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause

injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to

abnormal noise, surge levels, etc.

2. Be sure that abnormal current flows do not occur during the power-on sequence.

 Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from

electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the

design of products.

Document Number: 002-04665 Rev *A Page 32 of 175

MB91580M/S Series

 Fail-Safe Design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss

from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire

protection, and prevention of over-current levels and other abnormal operating conditions.

 Precautions Related to Usage of Devices

Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other

offi ce equi pm ent, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation

may directly affect human lives or cause physical injury or property damage, or where extremely high levels of

reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating

controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use.

The company will not be responsible for damages arising from such use without prior approval.

5.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, f or heat res istanc e duri ng

soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount

conditions, cont act your sales repres entative.

 Lead Insertio n Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on

the board, or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and

using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually

causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting

processes should conform to Cypress recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to

contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket

contacts and IC leads be verified before mounting.

 Surface M ount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more

easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased

susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established

a ranking of mounting conditions for each product. Us ers are advised to mount packages in accordance with Cypress

ranking of recommended conditions.

 Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,

junction strength may be reduced under some conditions of use.

 Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause

absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause

surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:

1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store

products in locations where temperature changes are slight.

2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures

between 5°C and 30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,

with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.

4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Document Number: 002-04665 Rev *A Page 33 of 175

MB91580M/S Series

 Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress

recommended conditions for baking.

Condition: 125°C/24 h

 Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the

following pre caut ion s:

1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion

generation may be needed to remove electricity.

2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resis tan c e (on the

level of 1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock

loads is recommended.

4. Ground all fixtures and instruments, or protect with anti-static measure s.

5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

5.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.

For reliable performance, do the following:

1. Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels

are anticipated, consider anti-humidity processing.

2. Discharge of Static Electricity

W hen high-vo ltage charg es ex ist clos e to semiconductor devices, discharges can cause abnormal operation. In such

cases, use anti-static measures or processing to prevent discharges.

3. Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the

device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.

4. Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should

provide shield ing as appr opr i at e.

5. Smoke, Fla me

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If

devices begin to smoke or burn, there is danger of the release of toxi c gases.

Customers considering the use of Cypress products in other special environmental conditions should consult with

sales representatives.

Document Number: 002-04665 Rev *A Page 34 of 175

MB91580M/S Series

6. Handling Devices

The latch-up prevention and pin processing are explai ned below.

 For latch-up prevention

If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings

is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply

current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from

exceeding the maximum ratings in device application.

Also, the analog power supplies (AVCC0, AVCC1, AVRH0, AVRH1) and analog input must not exceed the digital

power supply (VCC5) when the power supply to the analog system is turned on or off.

In the correct power-on sequence, turn on the digital power supply voltage (VCC5) and analog power supply voltages

(AVCC0, AVCC1, AVRH0, AVRH1) simultaneously. Alternatively, turn on the digital power supply voltage (VCC5) first,

and then turn on the analog power supplies (AVCC0, AVCC1, AVRH0, AVRH1).

 Treatment of unused pins

If unused input pins are left open, they may cause a permanent damage to the device due to device malfunction or

latch-up. Connect a 2kΩ or higher resistor to each of unused input pins for pull-u p or pull-down processing.

Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state

and treated in the same way as for the input pins.

 Power supply pins

The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be at the

same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external

power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised

ground level, and fulfill the total output current standard, etc. As shown in following figure, all VSS power supply pins

must be treated in the similar way. If multiple VCC or VSS systems are connected, the device cannot operate correctly

even within the guaranteed operating range.

 Power Supply Input Pins

VCC

VSS

VCC

Document Number: 002-04665 Rev *A Page 35 of 175

MB91580M/S Series

The power supply pins should be connected to VCC and VSS of this device at the low impedance from the power

supply source.

In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is

recommended to use as a bypass capacitor between VCC and VSS pins.

 Crystal oscillation circuit

An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to

lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded t o th e close

position to the device.

The printed circuit board artwork is recommended to surround the X0 and X1 pi ns by ground circuits.

 Mode pin (MD[1:0])

Connect the MD[1:0] mode pin to the VCC or VSS pin directly.

To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode

pin and VCC or VSS pin on the printed circuit board. Also, use the low-impedance pin connection.

 During pow er-on

To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to have 50μs or

longer (betw een 0.2V and 2.7 V ) during pow er -on.

 Notes during PLL clock operation

When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue

to operate at the free running frequency of the self oscillator circuit built in the PLL. This operation is not guaranteed.

 Treatment of A/D converter power supply pins

Connect the pins to have AVCC0 = AVCC1 = AVRH0 = AVRH1 = VCC,

AVSS0/ AVRL0 = AVSS1/ AVRL1 = VSS even if the A/D converter is not used.

 Note on using ex ternal cloc k

The external clock is unsupported.

External direct clock input cannot use.

Document Number: 002-04665 Rev *A Page 36 of 175

MB91580M/S Series

 Power-on sequence of A/D converter power supply analog inputs

Be sure to turn on the digital power supply (VCC5) first, and then turn on the A/D converter power supplies (AVCC0,

AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and analog inputs (AN0 to AN14, AN16 to AN23). Also, turn off the A/D

converter power supplies (AVCC0, AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and analog inputs (AN0 to AN14, AN16

to AN23) first, and then turn off the digital power supply (VCC5). When the AVRH0 and AVRH1 pin voltages are turned

on or off, they must not exceed AVCC0 and AVCC1. Even if a common analog input pin is used as an input port, its

input voltage must not exceed AVCC0 or AVCC1. (However, the analog power supply voltage and digital power supply

voltage can be turned on or off simultaneously.)

 Treatment of C pin

This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the

internal stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the

latest dat a sheet .

 Function Switching of a Multiplexed Port

To switch between the port function and the multiplexed pin function, use the PFR (port function register). For details,

see "I/O PORTS" in Hardware Manual.

 Low-power Consumption Mode

To set Sleep mode / Watch mode / Stop mode, or Watch mode (power-off) / Stop mode (power-off), see the section

"Launching Sleep mode / Watch mode / Stop mode" or "Launching Watch mode (power-off) / Stop mode (power-off)"

of "POWER CONSUMPTION CONTROL" in Hardware Manual, and follow the procedures.

Do not perform the following when using a monitor debugger.

•Do not set a break point for the low-power consumption transition program.

•Do not execute an operation step for the low-power consumption transition program.

 Notes When Writing Data in a Register Having the Status Flag

When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, take

care not to clear its status flag erroneously.

The program must be written not to clear the flag to the status bit, and to set the control bits to have the desired value.

Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a

single bit only.) The Byte, Half-word, or Word access must be used to write data in the control bits and status flag

simultaneously. During this time, take care not to clear other bits (in this case, the bits of status flag) erroneously.

Note: These points can be ignored because the bit instructions already take the points into consideration for

registers that support read-modify-write (RMW) operations. These points must be considered when using the bit

instructions for registers that do not support RMW operations.

Document Number: 002-04665 Rev *A Page 37 of 175

MB91580M/S Series

7. Block Diagram

 MB91F583AM/F584AM/F585AM

From Master

To Slave

From Master

To Slave

MD0,M D1,P040

SOT0_0-1,SOT1-3,

DAOUT

NMIX

MONCLK

RX0-1,

TX0-1

AIN0-1, BIN0-1,

ZIN0-1

I / O Port

XBS Crossbar Switch

FR81s CPU core

Instruction

On-chip bus Layer 2

Peripheral bus bridge

16 32

Wild register

I / O Port

On-chip bus Layer 1

Debug Interface

Regulator

On-chip bus XBS

M P U

BackUp

RAM

DMAC

RAMECC

Power-on r es et

CR oscillat or

Flash

RAM

Data

INT0-7

DTTI0,RTO0-6

IN0-3

ADTG0-2,

AN0-14, 16-23

FRCK0-5

SIN0_0-1, SI N1-3,

SCK0_0-1, SCK1-3,

SCS1-3

RSTX

Diagnosis

RXDA-B,TXDA-B,

TXENA-B,STOPWT

TIOA0-1, TIOB0-1

TIN0-3, TOT0-3

TRG0-1, PPG0-5

Main Flas h/W or k Flash

Bus

performance

counter

Operating

mode regist er

Bus bridge

FlexRay (1unit)

CAN (2ch)

Bus diagnosis register

Flash control register

RAMECC/Diagnosis

(XBS-RAM)

Asynchronous bus br idge

(PCLK1 PCLK2)

Asynchronous bus br idge

(PCLK1 PCLK2)

FlexRay c loc k c ontrol

PPG (6ch)

Clock Monitor

CAN presc aler

I/O port setting

Base t im er ( 2c h)

Reload timer ( 4c h)

U/D counter ( 2c h)

WDT 1 c alibr ation

32-bit per ipheral bus

16-bit per ipheral bus

CRC (2ch)

Waveform gener ator (2 units ( 7c h) )

Out put com par e ( 7c h)

A/D c onv er ter

Free- r un timer ( 6c h)

Input c apture ( 4c h)

D/A c onv er ter

Multi- function serial interface ( 4c h)

Bus bridge

(32-bit 16-bit)

Delay inter r upt

Int er r upt controller

Wat c hdog timer ( S W and HW)

Int er r upt reques t batc h r ead

Gener at ion/ cl ear of D M A t r ansfer r eques t

Clock control r egis ter

(fr equenc y div iding s ett ing)

Reset c ontrol r egis ter

Low-power consumption setting register

CR oscillat ion ( trim m ing)

NMI

Regulator c ontrol

Clock Super v is or

Power shutdown control

Ext er nal interr upt input ( 8c h)

Clock control

(clock setting, main timer, PLL timer)

Low-volt age detection (int er nal

low-volt age detection)

Low-volt age detection (external

low-volt age detection)

Input c ut - of f

inhibiting signal

Motor c ont r ol ext ension f unct ion

(PCLK2 MTRCLK)

Document Number: 002-04665 Rev *A Page 38 of 175

MB91580M/S Series

 MB91F583AS/F584AS/F585AS

FromMaster

To Slave

From Master

To Slave

MD0,MD1,P040

SOT0_0,SOT1,

DAOUT

NMIX

MONCLK

RX0,

TX0

AIN0-1,BIN0-1,

ZIN0-1

I / O Port

XBS Crossbar Switch

FR81s CPU core

Instruction

Peripheral bus bridge

16 32

Wild register

I / O Port

Debug Interface

On-chip bus XBS

MPU

BackUp

RAM

Flash

RAM

Data

INT0-6

DTTI0,RTO0-6

IN0-3

ADTG0-2,

AN0-14, 19, 20

FRCK0-5

SIN0_0, SIN1,

SCK0_0, SCK1,

SCS1

RSTX

RXDA-B,TXDA-B,

TXENA-B,STOPWT

TIOA0-1, TIOB0-1

TIN0-3, TOT0-3

TRG0-1, PPG0-5

Main Flas h/W or k Flash

Regulator

CR oscillat or

Power-on r es et

On-chip bus Layer 2

On-chip bus Layer 1

Bus

performance

counter

DMAC

Operating

mode regist er

Bus bridge

FlexRay (1unit)

CAN (1ch)

Bus diagnosis register

Flash control register

RAMECC/Diagnosis

(XBS-RAM)

RAMECC /

Diagnosis

FlexRay c loc k c ontrol

PPG (6ch)

Clock Monitor

CAN presc aler

I/O port setting

Base t im er ( 2c h)

Reload timer ( 4c h)

U/D counter ( 2c h)

WDT 1 c alibr ation

Asynchronous bus br idge

(PCLK1 PCLK2)

Asynchronous bus br idge

(PCLK1 PCLK2)

Motor c ont r ol ext ension f unct ion

(PCLK2 MTRCLK)

Delay inter r upt

Int er r upt controller

Wat c hdog timer ( S W and HW )

Int er r upt reques t bat c h r ead

Gener at ion/ cl ear of D M A t r ansfer request

Clock control r egis ter

(fr equenc y div iding s ett ing)

Reset c ontrol r egis ter

Low-power consumption setting register

32-bit per ipheral bus

16-bit per ipheral bus

CRC (2ch)

Waveform gener ator ( 2 units (7c h) )

Out put com par e ( 7c h)

A/D c onv er ter

Free- r un timer ( 6c h)

Input c apture ( 4c h)

D/A c onv er ter

Multi- function ser ial interf ac e ( 2c h)

Bus bridge

(32-bit 16-bit)

Input c ut - of f

inhibiting signal

CR oscillat ion ( trim m ing)

NMI

Regulator c ontrol

Clock Super v is or

Power shutdown control

Ext er nal interr upt input ( 7c h)

Clock control

(clock setting, main timer, PLL timer)

Low-volt age detection (internal

low-volt age detection)

Low-volt age detection (ex ternal

low-volt age detection)

Document Number: 002-04665 Rev *A Page 39 of 175

MB91580M/S Series

8. Memory Map

MB91F583AM/F583AS MB91F584AM/F584AS MB91F585AM/F585AS

0000_0000 H0000_0000 H0000_0000 H

0000_4000 HBackUp RAM(8KB) 0000_4000 HBackUp RAM(8KB) 0000_4000 HBackUp RAM(8KB)

0000_6000 H0000_6000 H0000_6000 H

0001_0000 H0001_0000 H0001_0000 H

0001_8000 H0001_C000 H

0007_0000 H0007_0000 H0007_0000 H

000C_0000 H000E_0000 H

0010_0000 H

0033_0000 H0033_0000 H0033_0000 H

0034_0000 H0034_0000 H0034_0000 H

FFFF_FFFF HFFFF_FFFF HFFFF_FFFF H

Reserved

IO area

Reserved

0001_C000 H

Interrupt vector table

Reset vector table

Reserved

RAM(32KB) RAM(48KB)

Reserved Reserved

RAM(48KB)

Reserved

Interrupt vector table

Reset vector table

000F_FC00 H000F_FC00 H

0010_0000 H

Reserved

0010_0000 H

Interrupt vector table

Reset vector table

Reserved

000F_FC00 H

Flash memory

(256+64)KB Flash memory

(384+64)KB Flash memory

(512+64)KB

WorkFlash

64KB WorkFlash

64KB

Document Number: 002-04665 Rev *A Page 40 of 175

MB91580M/S Series

9. I/O Map

The following I/O map shows the relationship between memory space and registers for peripheral resources.

Legend of I/O Map

The initial register values aft er r eset are indicated as follo ws:

"1": Init ial va lue "1"

"0": Init ial va lue "0"

"X": Initial value undefined

"-": Reserved bit/U n defi ned bit

"*": Initial value "0" or "1" according to the setting

Note:

It is prohibited to access addresses not described here.

Read/ Wri te attr i bute (R: Read W: Write)

Data access attribute

B: Byte

H: Half

-word

W: Word

(Note)

The access by the data access attribute

not described

is disabled.

Initi al register value aft er reset

Address

Address offs et val ue /Re gi ste r nam e

Block

Base timer 1

A/D convert er

000090H

000094H

000098H

00009CH

0000A0H

0000A4H

0000A8H

+ 0 + 1 + 2 + 3

BT1TMR [R] H

00000000 00000000

BT1TMCR [R/W] B,H,W

00000000 00000000

BT1STC [R/W] B

00000000

BT1PCSR/BT1PRLL [R/W] H

00000000 00000000

BT1PDUT/BT1PRLH/BT1DTBF [R/W] H

00000000 00000000

BTSEL [R/ W] B

----0000

ADERH [R/W] B, H, W

00000000 00000000

BTSSSR [W] B, H

--------------11

ADERL [R/W] B, H, W

00000000 00000000

ADCS1 [R/W] B,H,W

00000000

ADCS0 [R/W] B,H,W

00000000

ADCR1 [R] B,H,W

------XX

ADCR0 [R] B,H,W

XXXXXXXX

ADCT1 [R/W] B,H,W

00010000

ADCT0 [R/W] B,H,W

00101100

ADSCH [R/W] B,H,W

---00000

ADECH [R/W] B,H,W

---00000

Document Number: 002-04665 Rev *A Page 41 of 175

MB91580M/S Series

 MB91F583AM/F584AM/F585AM

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000000H PDR00[R/W] B,H,W

XXXXXXXX P DR0 1[R/W] B,H,W

XXXXXXXX P DR0 2[R/W] B,H,W

XXXXXXXX P DR0 3[R/W] B,H,W

XXXXXXXX

Port data register

000004H PDR04[R/W] B,H,W

XXXXXXXX P DR0 5[R/W] B,H,W

-XXXXXXX PDR06[R/W ] B, H,W

-XXXXXXX PDR07[R/W ] B, H,W

-----XXX

000008H PDR08[R/W] B,H,W

XXXXXXXX P DR0 9[R/W] B,H,W

XXXXXXXX P DR1 0[R/W] B,H,W

-----XXX -

00000CH - - - -

000010H

000038H

- - - - Reserved

00003CH

WDTCR0[R/W]

B,H,W

-0--0000

WDTCPR0[W]

B,H,W

00000000

WDTCR1[R]

B,H,W

----0010

WDTCPR1[W]

B,H,W

00000000 Watchdog timer [S]

000040H - - - Reserved

000044H DICR[R/W] B

-------0 - - - Delay interrupt

000048H

00005CH

- - Reserved

000060H TMRLRA0[R/W] H

XXXXXXX X XXXX XX XX TMR0[ R] H

XXXXXXX X XXXX XX XX Reload t imer 0

000064H TMRLRB0[R/W] H

XXXXXXX X XXXX XX XX TMCSR0[R/W] B,H,W

00000000 0-000000

000068H

00007CH

- - - - Reserved

000080H BT0TMR[ R] H

00000000 00000000 BT 0 T MCR[ R/W] H

-0000000 00000000

Base timer 0

000084H BT0TMCR2[ R/W] B

-------0 BT0STC[R/W] B

-0-0-0-0 - -

000088H BT0PCSR/BT0PRLL[R/W] H

00000000 00000000

BT0PDUT/BT0PRLH/BT0DTBF

[R/W] H

00000000 00000000

00008CH - - - -

000090H BT1TMR[ R] H

00000000 00000000 BT 1 T MCR[ R/W] H

-0000000 00000000

Base timer 1

000094H BT1TMCR2[ R/W] B

-------0 BT1STC[R/W] B

-0-0-0-0 - -

000098H BT1PCSR/BT1PRLL[R/W] H

00000000 00000000 BT 1 P DUT/ BT 1PRLH/BT1DT BF[R/W] H

00000000 00000000

00009CH BTSEL01[R/W] B

----0000 - BTSSSR[W] B,H

-------- ------11 Bas e timer 0,1

Document Number: 002-04665 Rev *A Page 42 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0000A0H

0000FCH

- - - - Reserved

000100H TMRLRA1[R/W] H

XXXXXXX X XXXX XX XX TMR1[ R] H

XXXXXXX X XXXX XX XX Reload timer 1

000104H TMRLRB1[R/W] H

XXXXXXX X XXXX XX XX TMCS R1[R/W] B,H,W

00000000 0-000000

000108H TMRLRA2[R/W] H

XXXXXXX X XXXX XX XX TMR2[ R] H

XXXXXXX X XXXX XX XX Reload t imer 2

00010CH TMRLRB2[R/W] H

XXXXXXX X XXXX XX XX TMCS R2[R/W] B,H,W

00000000 0-000000

000110H TMRLRA3[R/W] H

XXXXXXX X XXXX XX XX TMR3[ R] H

XXXXXXX X XXXX XX XX Reload t imer 3

000114H TMRLRB3[R/W] H

XXXXXXX X XXXX XX XX TMCS R3[R/W] B,H,W

00000000 0-000000

000118H

00011CH

- - - - Reserved

000120H IRPR0H[ R] B, H,W

00------ IRPR0L[R] B,H,W

00------ IRPR1H[R] B,H,W

00------ IRPR1L[R] B,H,W

--------

Interrupt request

batch read register

000124H IRPR2H[ R] B, H,W

--------

IRPR2L[R]

B,H,W *5

0000----

IRPR3H[ R] B, H,W

00------ IRPR3L[R] B,H,W

00------

000128H IRPR4H[ R] B, H,W

00------ IRPR4L[R] B,H,W

000000-- IRPR5H[R] B,H,W

00------ IRPR5L[R] B,H,W

00------

00012CH IRPR6H[ R] B, H,W

0000---- IRPR6L[R] B,H,W

00------ IRPR7H[R] B,H,W

00------ IRPR7L[R] B,H,W

--------

000130H IRPR8H[ R] B, H,W

-------- IRPR8L[R] B,H,W

00------ IRPR9H[R] B,H,W

00------ IRPR9L[R] B,H,W

00------

000134H IRPR10H[R] B,H,W

00------ IRPR10L[R] B,H,W

00------ IRPR11H[R] B,H,W

00------ IRPR11L[R] B,H,W

0000000-

000138H IRPR12H[R] B,H,W

0000000- IRPR12L[R] B,H,W

00000000 IRPR13H[R] B,H,W

0000000- IRPR13L[R] B,H,W

00000000

00013CH IRPR14H[ R] B,H,W

00------ IRPR14L[R] B,H,W

00------ IRPR15H[R] B,H,W

00000000 IRPR15L[R] B,H,W

0000----

000140 H IRPR16H[R] B,H,W

00------ IRPR16L[R] B,H,W

00------ IRPR17H[R] B,H,W

00------ IRPR17L[R]B,H,W

--------

000144 H

IRPR18H[R]

B,H,W

--------

IRPR18L[R]

B,H,W

000000-- - -

000148H

0001FCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 43 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000200H PCN0[R/W] B,H,W

00000000 000000-0 PCSR0[W] H,W

XXXXXXX X XXXX XX XX PPG0

000204H PDUT0[W ] H,W

XXXXXXX X XXXX XX XX P T MR0[ R] H,W

11111111 11111111

000208H PCN1[R/W] B,H,W

00000000 000000-0 PCSR1[W] H,W

XXXXXXX X XXXX XX XX PPG1

00020CH PDUT1[W] H,W

XXXXXXX X XXXX XX XX P T MR1[ R] H,W

11111111 11111111

000210H PCN2[R/W] B,H,W

00000000 000000-0 PCSR2[W] H,W

XXXXXXX X XXXX XX XX PPG2

000214H PDUT2[W ] H,W

XXXXXXX X XXXX XX XX P T MR2[ R] H,W

11111111 11111111

000218H PCN3[R/W] B,H,W

00000000 000000-0 PCSR3[W] H,W

XXXXXXX X XXXX XX XX PPG3

00021CH PDUT3[W] H,W

XXXXXXX X XXXX XX XX P T MR3[ R] H,W

11111111 11111111

000220H PCN4[R/W] B,H,W

00000000 000000-0 PCSR4[W] H,W

XXXXXXX X XXXX XX XX PPG4

000224H PDUT4[W] H ,W

XXXXXXX X XXXX XX XX P T MR4[ R] H,W

11111111 11111111

000228H PCN5[R/W] B,H,W

00000000 000000-0 PCSR5[W] H,W

XXXXXXX X XXXX XX XX PPG5

00022CH PDUT5[W] H,W

XXXXXXX X XXXX XX XX P T MR5[ R] H,W

11111111 11111111

000230H

0002BCH

- - Reserved

0002C0H GTRS0[R/W] B ,H,W

-0000000 -0000000 G TRS1[R/W] B ,H,W

-0000000 -0000000

PPG Control

0002C4H GTRS2[R/W] B,H,W

-0000000 -0000000 -

0002C8H - -

0002CCH - -

0002D0H - -

0002D4H - -

0002D8H GTREN0[ R/W] H,W

-------- --000000 -

0002DCH - - Reserved

0002E0H - GATEC0[R/W] B,H,W

------00 - GATEC2[R/W] B,H,W

------00

PPG GATE Control

0002E4H - GATEC4[R/W] B,H,W

------00 - -

0002E8H - - - -

Document Number: 002-04665 Rev *A Page 44 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0002ECH - - - - Reserved

0002F0H RCRH0[W] H,W

00000000 RCRL0[W] B,H,W

00000000 UDCRH0[R] H,W

00000000 UDCRL0[ R] B,H,W

00000000 U/D c ounter 0

0002F4H CCR0[R/W] B,H

00000000 -0001000 - CSR0[R] B

00000000

0002F8H RCRH1[W] H,W

00000000 RCRL1[W] B,H,W

00000000 UDCRH1[R] H,W

00000000 UDCRL1[ R] B,H,W

00000000 U/D c ounter 1

0002FCH CCR1[R/W] B,H

00000000 -0001000 - CSR1[R] B

00000000

000300H - Reserved

000304H - - - - Reserved

000308H - Reserved

00030CH - - - -

Document Number: 002-04665 Rev *A Page 45 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000310H - - MPUCR[R/W] H

000000-0 ----0100

MPU [S]

(Only the CPU can

access this area)

000314H - - - -

000318H -

00031CH - - -

000320H DPVAR [R] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000324H - - DPVSR[R/W] H

-------- 00000--0

000328H DEAR[R] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

00032CH - - DESR[R/W] H

-------- 00000--0

000330H PABR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0000

000334H - - PACR0 [R/W] H

000000-0 00000--0

000338H PABR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

00033CH - - PACR1[R/W] H

000000-0 00000--0

000340H PABR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000344H - - PACR2 [R/W] H

000000-0 00000--0

000348H PABR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

00034CH - - PACR3[R/W] H

000000-0 00000--0

000350H PABR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000354H - - PACR4 [R/W] H

000000-0 00000--0

000358H PABR5[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

00035CH - - PACR5[R/W] H

000000-0 00000--0

000360H PABR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000364H - - PACR6 [R/W] H

000000-0 00000--0

Document Number: 002-04665 Rev *A Page 46 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000368H PABR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000 MPU [ S]

(Only the CPU can

access this area)

00036CH - - PACR7[R/W] H

000000-0 00000--0

000370H -

Reserved [S]

000374H - - -

000378H -

00037CH - - -

000380H -

000384H - - -

000388H -

00038CH - - -

000390H -

000394H - - -

Reserved [S]

000398H -

00039CH - - -

0003A0H -

0003A4H - - -

0003A8H -

0003ACH - - -

0003B0H

0003CCH

- - - - Reserved [S]

0003D0H -

Reserved [S]

0003D4H -

0003D8H -

0003DCH -

0003E0H

0003FCH

- - - - Reserved [S]

000400H ICSEL0[R/W] B,H,W

-----000 ICSEL1[R/W] B,H,W

-------0 ICSEL2[R/W] B,H,W

-------0 ICSEL3[R/W] B,H,W

-------0

Generation and

clear of DMA

transfer request

000404H ICSEL4[R/W] B,H,W

-------0 ICSEL5[R/W] B,H,W

-------0 ICSEL6[R/W] B,H,W

-------0 ICSEL7[R/W] B,H,W

-----000

000408H ICSEL8[R/W] B,H,W

-------0 ICSEL9[R/W] B,H,W

-------0 ICSEL10[R/W] B,H,W

------00 ICSEL11[R/W] B,H,W

-------0

00040CH ICSEL12[R/W] B,H,W

-------0 ICSEL13[R/W] B,H,W

-------0 ICSEL14[R/W] B,H,W

-------0 ICSEL15[R/W] B,H,W

-------0

Document Number: 002-04665 Rev *A Page 47 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000410H ICSEL16[R/W] B,H,W

-------0 ICSEL17[R/W] B,H,W

-------0 ICSEL18[R/W] B,H,W

-------0 ICSEL19[R/W] B,H,W

-------0

Generation and

clear of DMA

transfer request

000414H ICSEL20[R/W] B,H,W

-------0 ICSEL21[R/W] B,H,W

-----000 ICSEL22[R/W] B,H,W

-----000 ICSEL23[R/W] B,H,W

-----000

000418H ICSEL24[R/W] B,H,W

-----000 ICSEL25[R/W] B,H,W

-----000 ICSEL26[R/W] B,H,W

-------0 ICSEL27[R/W] B,H,W

-------0

00041CH - - - -

000420H - - - -

000424H

00043CH

- - - - Reserved

000440H ICR00[R/W] B,H,W

---11111 ICR01 [R/W] B,H,W

---11111 ICR02[R/W] B,H,W

---11111 ICR03 [R/W] B,H,W

---11111

Interrupt controller

[S]

000444H ICR04[R/W] B,H,W

---11111 ICR05 [R/W] B,H,W

---11111 ICR06 [R/W] B,H,W

---11111 ICR07 [R/W] B,H,W

---11111

000448H ICR08[R/W] B,H,W

---11111 ICR09 [R/W] B,H,W

---11111 ICR10 [R/W] B,H,W

---11111 ICR11 [R/W] B,H,W

---11111

00044CH ICR12[R/W] B,H,W

---11111 ICR13 [R/W] B,H,W

---11111 ICR14 [R/W] B,H,W

---11111 ICR15 [R/W] B,H,W

---11111

000450H ICR16[R/W] B,H,W

---11111 ICR17 [R/W] B,H,W

---11111 ICR18 [R/W] B,H,W

---11111 ICR19 [R/W] B,H,W

---11111

000454H ICR20[R/W] B,H,W

---11111 ICR21 [R/W] B,H,W

---11111 ICR22 [R/W] B,H,W

---11111 ICR23 [R/W] B,H,W

---11111

000458H ICR24[R/W] B,H,W

---11111 ICR25 [R/W] B,H,W

---11111 ICR26 [R/W] B,H,W

---11111 ICR27 [R/W] B,H,W

---11111

00045CH ICR28[R/W] B ,H,W

---11111 ICR29 [R/W] B,H,W

---11111 ICR30 [R/W] B,H,W

---11111 ICR31 [R/W] B,H,W

---11111

000460H ICR32[R/W] B,H,W

---11111 ICR33 [R/W] B,H,W

---11111 ICR34 [R/W] B,H,W

---11111 ICR35 [R/W] B,H,W

---11111

000464H ICR36[R/W] B,H,W

---11111 ICR37[R/W] B,H,W

---11111 ICR38 [R/W] B,H,W

---11111 ICR39 [R/W] B,H,W

---11111

000468H ICR40[R/W] B,H,W

---11111 ICR41 [R/W] B,H,W

---11111 ICR42 [R/W] B,H,W

---11111 ICR43 [R/W] B,H,W

---11111

00046CH ICR44[R/W] B,H,W

---11111 ICR45 [R/W] B,H,W

---11111 ICR46 [R/W] B,H,W

---11111 ICR47 [R/W] B,H,W

---11111

000470H

00047CH

- - - - Reserved [S]

Document Number: 002-04665 Rev *A Page 48 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000480H

RSTRR[R]

B,H,W

XXXX--XX

RSTCR[R/W] B,H,W

111----0 STBCR[R/W] B,H,W

000---11* -

Reset control [S]

Power

consumption

control [S]

* Writing to STBCR

by DMA is

disabled.

000484H - - - - Reserved [S]

000488H DIVR0[R/W] B,H,W

000----- - DIVR2[R/W] B,H,W

0011---- - Clock control [S]

00048CH - - - - Reserved [S]

000490H IORR0[R/W] B,H,W

-0000000 IORR1[R/W] B,H,W

-0000000 IORR2[R/W] B,H,W

-0000000 IORR3[R/W] B,H,W

-0000000 DMA transfer

request from a

peripheral [S]

000494H IORR4[R/W] B,H,W

-0000000 IORR5[R/W] B,H,W

-0000000 IORR6[R/W] B,H,W

-0000000 IORR7[R/W] B,H,W

-0000000

000498H - - - -

00049CH - - - -

0004A0H - - - - Reserved

0004A4H CANPRE[R/W] B,H,W

---00000 - - - CA N presc al er

0004A8H

0004ACH

- - - - Reserved

0004B0H - - - - Reserved

0004B4H

0004C0H

- - - - Reserved

0004C4H CUCR1[R/W] B,H,W

-------- ---0--00 CUT D1[R/W] B,H,W

11000011 01010000 WDT1 calibration

0004C8H CUTR1[R] B,H,W

-------- 00000000 00000000 00000000

0004CCH

0004DCH

- - - - Reserved

0004E0H - - CSCFG[R/W] B,H,W

---0---- CMCFG[R/W] B,H,W

00000000 Clock monitor

0004E4H - - - -

0004E8H

PLL2DIVM[R/W]

B,H,W

----0000

PLL2DIVN[R/W]

B,H,W

-0000000

PLL2DIVG[R/W]

B,H,W

----0000

PLL2MULG[R/W]

B,H,W

00000000 FlexRay

clock control *5

0004ECH

PLL2CTRL[R/W]

B,H,W

----0000

PLL2DIVK[R/W]

B,H,W

-------0

CLKR2[R/W] B,H,W

000--000 -

Document Number: 002-04665 Rev *A Page 49 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0004F0H

0004FCH

- - - - Reserved

000500H - Reserved

000504H - Reserved

000508H

00050CH

- - - - Reserved

000510H CSELR[R/W] B,H,W

-0----00 CMONR[R] B,H,W

-01---00 MTMCR[R/W] B,H,W

00001111 - Clock control [S]

000514H PLLCR[R/W] B,H,W

00-00000 11110000 CST B R[R/W] B,H,W

----0000 PT MCR[ R/W] B,H,W

00------

000518H - - CPUAR[R/W] B,H,W

0---XXXX - Reset [S]

00051CH - - - Reserved [S]

000520H

CCPSSELR[R/W]

B,H,W

-------0 - - CCPSDIVR[R/W]

B,H,W

-000-000

Clock control 2

000524H - CCPLLFBR[R/W]

B,H,W

-0000000

CCSSFBR0[R/W]

B,H,W

--000000

CCSSFBR1[R/W]

B,H,W

---00000

000528H - CCSSCCR0[R/W]

B,H,W

----0000

CCSSCCR1[R/W]

B,H,W

000----- --------

00052CH - CCCGRCR0[R/W]

B,H,W

00----00

CCCGRCR1[R/W]

B,H,W

00000000

CCCGRCR2[R/W]

B,H,W

00000000

000530H - - CCPMUCR0[R/W]

B,H,W

0-----00

CCPMUCR1[R/W]

B,H,W

0--00000

000534H - - - -

000538H - - - -

00053CH - - - -

000540H

00054CH

- - - - Reserved

000550H EIRR0[R/W] B,H,W

XXXXXXXX ENIR0[R/W] B,H,W

00000000 EL VR0[R/W] B,H,W

00000000 00000000 External interrupt

(INT0 to 7)

000554H

000568H

- - - - Reserved

00056CH - CSVCR[R/W] B

-0--1--0 - - CSV

Document Number: 002-04665 Rev *A Page 50 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000570H CRTR[R/W] B,H,W

01111111 - - - WDT1 calibration

(trimming)

000574H

00057CH

- - - - Reserved

000580H REGS EL [R /W] B,H,W

01--110- - - - Regulator c ontrol

000584H LVD5R[R/W] B,H,W

-------1 LVD5F[R/W] B,H,W

001100-1

LVD[R/W]

B,H,W

01000--0 - Low-voltage

detection

000588H

00058CH

- - - - Reserved

000590H

PMUSTR [ R/W]

B,H,W

0-----1X

PMUCTLR[R/W]

B,H,W

0-00----

PWRTMCTL[R/W]

B,H,W

-----011 -

PMU

000594H - PMUINTF1[R/W]

B,H,W

00000000

PMUINTF2[R/W]

B,H,W

-00----- -

000598H - - - -

00059CH - - - -

0005A0H

0005FCH

- - - - Reserved

000600H

00060CH

- - - - Reserved [S]

000610H

00063CH

- - - - Reserved [S]

000640H

00064CH

- - - - Reserved [S]

000650H

00067CH

- - - - Reserved [S]

000680H

00068CH

- - - - Reserved [S]

000690H

0006BCH

- - - - Reserved [ S]

Document Number: 002-04665 Rev *A Page 51 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0006C0H

0006CCH

- - - - Reserved [S]

0006D0H

0006F0H

- - - - Reserved

0006F4H - Reserved

0006F8H

0006FCH

- - - - Reserved

000700H - Reserved

000704H

00070CH

- - - - Reserved

000710H BPCCRA[R/W] B

00000000 BPCCRB[R/W] B

00000000 BPCCRC[R/W] B

00000000 -

Bus performance

counter

000714H BPCTR A[R/W] W

00000000 00000000 00000000 00000000

000718H BPCTR B[R/W] W

00000000 00000000 00000000 00000000

00071CH BPCTRC[R/W] W

00000000 00000000 00000000 00000000

000720H

0007F8H

- - - - Reserved

0007FCH BMODR[R] B,H,W

XXXXXXXX - - - Operation mode

000800H

00083CH

- - - - Reserved [S]

000840H FCTLR[R/W] H

-0--1000 0--0---- - FSTR[R/W] B

-----001 Flash memory

000844H - - - - Reserved [S]

000848H

000854H

- - - - Reserved [S]

000858H - - WREN[R/W] H

00000000 00000000 Wild register [S]

00085CH

00087CH

- - - - Reserved [S]

Document Number: 002-04665 Rev *A Page 52 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000880H WRAR00[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

Wild register [S]

000884H WRDR00[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000888H WRAR01[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

00088CH WRDR01[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000890H WRAR02[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

000894H WRDR02[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000898H WRAR03[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

00089CH WRDR03[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008A0H WRAR04[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008A4H WRDR04[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008A8H WRAR05[R/W] W

-------- --XXXXXX XXXXX XX X XXXXXX--

0008ACH WRDR05[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008B0H WRAR06[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008B4H WRDR06[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008B8H WRAR07[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008BCH WRDR07[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008C0H WRAR08[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008C4H WRDR08[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008C8H WRAR09[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008CCH WRDR09[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

Document Number: 002-04665 Rev *A Page 53 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0008D0H WRAR10[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

Wild register [S]

0008D4H WRDR10[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008D8H WRAR11[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008DCH WRDR11[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008E0H WRAR12[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008E4H WRDR12[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008E8H WRAR13[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008ECH WRDR13[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008F0H WRAR14[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008F4H WRDR14[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008F8H WRAR15[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008FCH WRDR15[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000900H

000BF8H

- - - - Reserved

000BFCH - UER[W] B,H,W

-------- -------X OCDU

Document Number: 002-04665 Rev *A Page 54 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000C00H DCCR0[R/W] W

0----000 --00--00 00000000 0-000000

DMA controller [S]

000C04H DCSR0[R/W ] H

0------- -----000 DT CR0[R/W] H

00000000 00000000

000C08H DSAR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C0CH DDAR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C10H DCCR1[R/W] W

0----000 --00--00 00000000 0-000000

000C14H DCSR1[R/W ] H

0------- -----000 DT CR1[R/W] H

00000000 00000000

000C18H DSAR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C1CH DDAR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C20H DCCR2[R/W] W

0----000 --00--00 00000000 0-000000

000C24H DCSR2[R/W ] H

0------- -----000 DT CR2[R/W] H

00000000 00000000

000C28H DSAR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C2CH DDAR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C30H DCCR3[R/W] W

0----000 --00--00 00000000 0-000000

000C34H DCSR3[R/W ] H

0------- -----000 DT CR3[R/W] H

00000000 00000000

000C38H DSAR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C3CH DDAR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C40H DCCR4[R/W] W

0----000 --00--00 00000000 0-000000

000C44H DCSR4[R/W ] H

0------- -----000 DT CR4[R/W] H

00000000 00000000

Document Number: 002-04665 Rev *A Page 55 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000C48H DSAR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

DMA controller [S]

000C4CH DDAR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C50H DCCR5[R/W] W

0----000 --00--00 00000000 0-000000

000C54H DCSR5[R/W ] H

0------- -----000 DT CR5[R/W] H

00000000 00000000

000C58H DSAR5[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C5CH DDAR5[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C60H DCCR6[R/W] W

0----000 --00--00 00000000 0-000000

000C64H DCSR6[R/W ] H

0------- -----000 DT CR6[R/W] H

00000000 00000000

000C68H DSAR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C6CH DDAR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C70H DCCR7[R/W] W

0----000 --00--00 00000000 0-000000

000C74H DCSR7[R/W ] H

0------- -----000 DT CR7[R/W] H

00000000 00000000

000C78H DSAR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C7CH DDAR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C80H

000DF0H

- - - -

000DF4H - - DNMIR[R/W] B

0------0 DILVR[R/W] B

---11111

000DF8H DMACR[R/W] W

0------- -------- 0------- --------

000DFCH - - - - Reserved [S]

000E00H DDR00[R/W] B,H

00000000 DDR01[R/W] B,H

00000000 DDR02[R/W] B,H

00000000 DDR03[R/W] B,H

00000000

Data direction

000E04H DDR04[R/W] B,H

00000000 DDR05[R/W] B,H

-0000000 DDR06[R/W] B,H

-0000000 DDR07[R/W] B,H

-----000

000E08H DDR08[R/W] B,H

00000000 DDR09[R/W] B,H

00000000 DDR10[R/W] B,H

-----000 -

000E0CH - - - -

Document Number: 002-04665 Rev *A Page 56 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000E10H

000E1CH

- - - - Reserved

000E20H PFR00[R/W] B,H

00000000 PFR01[R/W] B,H

00000000 PFR02[R/W] B,H

00000000 PFR03[R/W] B,H

00000000

Port function

000E24H PFR04[R/W] B,H

00000000 PFR05[R/W] B,H

-0000000 PFR06[R/W] B,H

-0000000 PFR07[R/W] B,H

-----000

000E28H PFR08[R/W] B,H

00000000 PFR09[R/W] B,H

00000000 PFR10[R/W] B,H

-----000 -

000E2CH - - - -

000E30H

000E3CH

- - - - Reserved

000E40H PDDR00[R] B,H,W

XXXXXXXX PDDR01[R] B,H,W

XXXXXXXX PDDR02[R] B,H,W

XXXXXXXX PDDR03[R] B,H,W

XXXXXXXX

Input data direct

read register

000E44H PDDR04[R] B,H,W

XXXXXXXX PDDR05[R] B,H,W

-XXXXXXX PDDR06[R] B,H,W

-XXXXXXX PDDR07[R] B,H,W

-----XXX

000E48H PDDR08[R] B,H,W

XXXXXXXX PDDR09[R] B,H,W

XXXXXXXX PDDR10[R] B,H,W

-----XXX -

000E4CH - - - -

000E50H

000E5CH

- - - - Reserved

000E60H EPFR00[R/W] B,H

------00 EPFR01[R/W] B, H

---00000 EPFR02[R/W] B, H

--000000 EPFR03[R/W] B, H

--000000

Extended port

function regist er

000E64H - - EPFR06[R/W ] B,H

------00 EPFR07[R/W] B, H

----0000

000E68H

EPFR08[R/W]

B,H *5

----0000

EPFR09[R/W] B,H

-------0 EPFR10[R/W] B,H

-0000000 -

000E6CH - - EPF R1 4[R/W] B,H

--0-0-0- -

000E70H - - - -

000E74H - - - -

000E78H - - - -

000E7CH - - - -

000E80H - - - -

000E84H

000EBCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 57 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000EC0H PPER0 0 [R /W] B,H

00000000 PPER01[R /W] B,H

00000000 PPER02[R /W] B,H

00000000 PPER03[R /W] B,H

00000000

Port pull-up/down

enable register

000EC4H PPER0 4 [R /W] B,H

00000000 PPER05[R /W] B,H

-0000000 PPER06 [R /W] B,H

-0000000 PPER07 [R /W] B,H

-----000

000EC8H PPER0 8 [R /W] B,H

00000000 PPER09[R /W] B,H

00000000 PPER10[R /W] B,H

-----000 -

000ECCH - - - -

000ED0H

000EDCH

- - - - Reserved

000EE0H PILR00[R/W] B,H

11111111 PILR01[R/W] B,H

11111111 PILR02[R/W] B,H

11111111 PILR03[R/W] B,H

11111111

Port input level

selection register

000EE4H PILR04[R/W] B,H

11111111 PILR05[R/W] B,H

-1111111 PILR06[R/W] B,H

-1111111 PILR07[R/W] B,H

-----111

000EE8H PILR08[R/W] B,H

11111111 PILR09[R/W] B,H

11111111 PILR10[R/W] B,H

-----111 -

000EECH - - - -

000EF0H

000EFCH

- - - - Reserved

000F00H

000F1CH

- - - - Reserved

000F20H PODR00[R/W] B,H

00000000 PODR01[R/W] B,H

00000000 PODR02[R/W] B,H

00000000 PODR03[R/W] B,H

00000000

Port output drive

000F24H PODR04[R/W] B,H

00000000 PODR05[R/W] B,H

-0000000 PODR06[R/W] B,H

-0000000 PODR07[R/W] B,H

-----000

000F28H PODR08[R/W] B,H

00000000 PODR09[R/W] B,H

00000000 PODR10[R/W] B,H

-----000 -

000F2CH - - - -

000F30H

000F3CH

- - - - Reserved

000F40H PORTEN[R/W] B,H,W

------00 - - - Port input enable

000F44H KEYCDR[R/W] H

00000000 00000000 - - Port key code

000F48H ADERH[R/W] B,H

-------- 11111111 ADERL[R/W] B,H

-1111111 11111111 Analog i nput

enable regist er

000F4CH DAER[ R/W] B, H

-------0 - - - Analog out put

enable regist er

Document Number: 002-04665 Rev *A Page 58 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000F50H

000FFCH

- - - - Reserved

001000H SACR[ R/W] B, H,W

-------0

PICD[R/W]

B,H,W

----0011 - - Synchronous/asyn

chronous switch

control

001004H

0010BCH

- - - - Reserved

0010C0H - - - CRCCR[R/W] B,H,W

-0000000

CRC arithm etic

operation 0

0010C4H CRCINIT[R/W] B,H,W

11111111 11111111 11111111 11111111

0010C8H CRCIN[R/W ] B, H,W

00000000 00000000 00000000 00000000

0010CCH CRCR[R] B,H,W

11111111 11111111 11111111 11111111

0010D0H - - - CRCCR1[R/W] B,H,W

-0000000

CRC arithm etic

operation 1

0010D4H CRCINIT1[R/W] B,H,W

11111111 11111111 11111111 11111111

0010D8H CRCIN1[R/W ] B, H,W

00000000 00000000 00000000 00000000

0010DCH CRCR1[R] B, H,W

11111111 11111111 11111111 11111111

0010E0H

0010FCH

- - - - Reserved

001100H TCG S[R/W] B ,H,W

------00 - - TCGSE[R/W] B,H,W

--000000

Free-run timer

simultaneous

activation

001104H CPCLRB0/CPCLR0[ R/W] H,W

11111111 11111111 TCDT 0[R/W] H,W

00000000 00000000 Free-run timer 0

001108H TCCS0[R/W] B,H,W

00000000 01000000 ----0000 --------

00110CH CPCLRB1/ CPCLR1[R/W] H,W

11111111 11111111 TCDT 1[R/W] H,W

00000000 00000000 Free-run timer 1

001110H TCCS1[R/W] B,H, W

00000000 01000000 ----0000 --------

001114H CPCLRB2/CPCLR2[ R/W] H,W

11111111 11111111 TCDT 2[R/W] H,W

00000000 00000000 Free-run timer 2

001118H TCCS2[R/W] B,H, W

00000000 01000000 ----0000 --------

Document Number: 002-04665 Rev *A Page 59 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00111CH CPCLRB3/ CPCLR3[R/W] H,W

11111111 11111111 TCDT 3[R/W] H,W

00000000 00000000 Free-run timer 3

001120H TCCS3[R/W] B,H, W

00000000 01000000 ----0000 --------

001124H CPCLRB4/CPCLR4[ R/W] H,W

11111111 11111111 TCDT 4[R/W] H,W

00000000 00000000 Free-run timer 4

001128H TCCS4[R/W] B,H, W

00000000 01000000 ----0000 --------

00112CH CPCLRB5/ CPCLR5[R/W] H,W

11111111 11111111 TCDT5[R/W] H,W

00000000 00000000 Free-run timer 5

001130H TCCS5[R/W] B,H, W

00000000 01000000 ----0000 --------

001134H FRS0[R/W] B,H,W

-------- -000-000 -000-000 -000-000

Free-run timer

selection

001138H FRS1[R/W] B,H,W

-------- -------- -000-000 -000-000

00113CH FRS2[R/W] B,H,W

-------- -000-000 -000-000 -000-000

001140H -

001144H FRS4[R/W] B,H,W

-000-000 -000-000 -000-000 -000-000

001148H FRS5[R/W] B,H,W

-----000 -000-000 -000-000 -000-000

00114CH FRS6[R/W] B,H,W

-000-000 -000-000 -000-000 -000-000

001150H -

001154H OCCPB0/OCCP0[R/W ] H,W

00000000 00000000 OCCP B1/OCCP1[ R/W] H,W

00000000 00000000 Output compare

0/1

001158H OCS01[R/W] B,H,W

-110--00 00001100 - OCMOD01[R/W]

B,H,W

------00

00115CH OCCPB2/ O CCP2[R/W] H,W

00000000 00000000 OCCPB3/OCCP3[R/W] H,W

00000000 00000000 Output compare

2/3

001160H OCS23[R/W] B,H,W

-110--00 00001100 - OCMOD23[R/W]

B,H,W

------00

001164H OCCPB4/OCCP4[R/W ] H,W

00000000 00000000 OCCP B5/OCCP5[ R/W] H,W

00000000 00000000 Output compare

4/5

001168H OCS45[R/W] B,H,W

-110--00 00001100 - OCMOD45[R/W]

B,H,W

------00

Document Number: 002-04665 Rev *A Page 60 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00116CH OCCPB6/ O CCP6[R/W] H,W

00000000 00000000 OCCP B7/OCCP7[ R/W] H,W

00000000 00000000 Output compare

6/7

001170H OCS67[R/W] B,H,W

-110--00 00001100 - OCMOD67[R/W]

B,H,W

------00

001174H OCCPB8/OCC P8[R/W] H,W

00000000 00000000 OCCP B9/OCCP9[ R/W] H,W

00000000 00000000 Output compare

8/9

001178H OCS89[R/W] B,H,W

-110--00 00001100 - OCMOD89[R/W]

B,H,W

------00

00117CH OCCPB10/OCCP10[R/W ] H,W

00000000 00000000 OCCP B11/OCCP11[R/W] H,W

00000000 00000000 Output compare

10/11

001180H OCS1011[R/W] B,H,W

-110--00 00001100 - OCMOD1011

[R/W] B,H,W

------00

001184H IPCP 0[R] H,W

00000000 00000000 IPCP1[R] H,W

00000000 00000000 Input capture 0/1

001188H ICS01[R/W] B,H,W

------00 00000000 - LSYNS [R /W] B,H,W

----0000

00118CH IPCP2[R] H,W

00000000 00000000 IPCP3[R] H,W

00000000 00000000 Input capture 2/3

001190H ICS23[R/W] B,H,W

------00 00000000 - -

001194H - - Reserved

001198H - - -

00119CH - - Reserved

0011A0H - - -

0011A4H DTSR[R/W] B,H,W

------10 - - - DTTI selection

0011A8H TMRR0[R/W] H,W

00000000 00000001 TMRR1[ R/W] H,W

00000000 00000001

Waveform

generator

0/1/2

0011ACH TMRR2[R/W] H,W

00000000 00000001 - -

0011B0H DTSCR0[R/W] B,H,W

00000000 DTSCR1[R/W] B,H,W

00000000 DTSCR2[R/W] B,H,W

00000000 -

0011B4H - DTIR0[R/W] B,H,W

000000-- - DTMNS 0[R/W] B,H,W

00---000

0011B8H - SIGCR10[R/W] B,H,W

00000000 - SIGCR20[R/W] B,H,W

000000-1

0011BCH PICS0[R/W] B,H,W

000000-- -------- -------- --------

Document Number: 002-04665 Rev *A Page 61 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0011C0H TMRR3[R/W] H,W

00000000 00000001 TMRR4[R/W] H,W

00000000 00000001 Waveform

generator

3/4/5

0011C4H TMRR5[R/W] H,W

00000000 00000001 - -

0011C8H DTSCR3[R/W] B,H,W

00000000 DTSCR4[R/W] B,H,W

00000000 DTSCR5[R/W] B,H,W

00000000 -

0011CCH - DTIR1[R/W] B,H,W

000000-- - DTMNS 1[R/W] B,H,W

00---000 Waveform

generator

3/4/5

0011D0H - SIGCR11[R/W] B,H,W

00000000 - SIGCR21[R/W] B,H,W

-------1

0011D4H -

0011D8H - - - -

12-bit A/D

converter

0011DCH ADTSS[R/W] B,H,W

-------0 - - -

0011E0H ADTS E[R/W] B ,H,W

-------- 00000000 -0000000 00000 000

0011E4H ADCOMP0/ADCOMPB0[R/W] H,W

00000000 00000000 ADCO MP 1/ADCOMPB1[ R/W] H,W

00000000 00000000

0011E8H ADCOMP2/ADCOMPB2[R/W] H,W

00000000 00000000 ADCO MP 3/ADCOMPB3[ R/W] H,W

00000000 00000000

0011ECH ADCOMP4/ ADCOMPB4[R/W] H,W

00000000 00000000 ADCOMP5/ADCO MPB5 [ R/W] H,W

00000000 00000000

0011F0H ADCOMP6/ ADCOMPB6[R/W] H,W

00000000 00000000 ADCO MP 7/ADCOMPB7[ R/W] H,W

00000000 00000000

0011F4H ADCOMP8/ ADCOMPB8[R/W] H,W

00000000 00000000 ADCO MP 9/ADCOMPB9[ R/W] H,W

00000000 00000000

0011F8H ADCOMP10/ADCOMPB10[R/W] H,W

00000000 00000000 ADCOMP11/ADCOMPB11[R/W] H,W

00000000 00000000

0011FCH ADCOMP12/ADCOMPB12[R/W] H,W

00000000 00000000 ADCOMP13/ADCOMPB13[R/W] H,W

00000000 00000000

001200H ADCOMP14/ADCOMPB14[R/W] H,W

00000000 00000000 -

001204H ADCOMP16/ADCOMPB16[R/W] H,W

00000000 00000000 ADCOMP17/ADCOMPB17[R/W] H,W

00000000 00000000

001208H ADCOMP18/ADCOMPB18[R/W] H,W

00000000 00000000 ADCOMP19/ADCOMPB19[R/W] H,W

00000000 00000000

00120CH ADCOMP20/ADCOMPB20[R/W] H,W

00000000 00000000 ADCOMP21/ADCOMPB21[R/W] H,W

00000000 00000000

001210H ADCOMP22/ADCOMPB22[R/W] H,W

00000000 00000000 ADCOMP23/ADCOMPB23[R/W] H,W

00000000 00000000

001214H - - - -

Document Number: 002-04665 Rev *A Page 62 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001218H - - - -

12-bit A/D

converter

00121CH - - - -

001220H - - - -

001224H ADTCS0[R/W] B,H,W

00000000 0010-000 ADT CS 1 [R/W] B,H,W

00000000 0010-000

001228H ADTCS2[R/W] B,H,W

00000000 0010-000 ADT CS 3 [R/W] B,H,W

00000000 0010-000

00122CH ADTCS4[R/W] B,H,W

00000000 0010-000 ADT CS 5 [R/W] B,H,W

00000000 0010-000

001230H ADTCS6[R/W] B,H,W

00000000 0010-000 ADTCS7[R/W] B,H,W

00000000 0010-000

001234H ADTCS8[R/W] B,H,W

00000000 0010-000 ADT CS 9 [R/W] B,H,W

00000000 0010-000

001238H ADTCS10 [R/W] B,H,W

00000000 0010-000 ADT CS 1 1[R/W] B,H,W

00000000 0010-000

00123CH ADTCS12[R/W] B,H,W

00000000 0010-000 ADTCS13[R/W] B,H,W

00000000 0010-000

001240H ADTCS14 [R/W] B,H,W

00000000 0010-000 -

001244H ADTCS16 [R/W] B,H,W

00000000 00100000 ADT CS17[R/W] B,H,W

00000000 00100000

001248H ADTCS18 [R/W] B,H,W

00000000 00100000 ADT CS19[R/W] B,H,W

00000000 00100000

00124CH ADTCS20[R/W] B,H,W

00000000 00100000 ADT CS21[R/W] B,H,W

00000000 00100000

001250H ADTCS22 [R/W] B,H,W

00000000 00100000 ADT CS23[R/W] B,H,W

00000000 00100000

001254H - - - -

001258H - - - -

00125CH - - - -

001260H - - - -

001264H ADTCD0[R] B, H,W

10--0000 00000000 ADT CD1 [R] B,H,W

10--0000 00000000

001268H ADTCD2[R] B, H,W

10--0000 00000000 ADT CD3 [R] B,H,W

10--0000 00000000

00126CH ADTCD4[R] B, H,W

10--0000 00000000 ADT CD5 [R] B,H,W

10--0000 00000000

001270H ADTCD6[R] B, H,W

10--0000 00000000 ADT CD7 [R] B,H,W

10--0000 00000000

001274H ADTCD8[R] B, H,W

10--0000 00000000 ADT CD9 [R] B,H,W

10--0000 00000000

Document Number: 002-04665 Rev *A Page 63 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001278H ADTCD10[R] B,H,W

10--0000 00000000 ADTCD11[R] B,H,W

10--0000 00000000

12-bit A/D

converter

00127CH ADTCD12[R] B,H,W

10--0000 00000000 ADTCD13[R] B,H,W

10--0000 00000000

001280H ADTCD14[R] B,H,W

10--0000 00000000 -

001284H ADTCD16[R] B,H,W

10--0000 00000000 ADTCD17[R] B,H,W

10--0000 00000000

001288H ADTCD18[R] B,H,W

10--0000 00000000 ADTCD19[R] B,H,W

10--0000 00000000

00128CH ADTCD20[R] B,H, W

10--0000 00000000 ADTCD21[R] B,H,W

10--0000 00000000

001290H ADTCD22[R] B,H,W

10--0000 00000000 ADTCD23[R] B,H,W

10--0000 00000000

001294H - - - -

001298H - - - -

00129CH - - - -

0012A0H - - - -

0012A4H ADCS0[R/W] B,H,W

0------- -------- ADCH0[R] B,H,W

-----000 ADMD0[R/W] B,H,W

----0000

0012A8H ADCS1[R/W] B,H,W

0------- -------- ADCH1[R] B,H,W

-----000 ADMD1[R/W] B,H,W

----0000

0012ACH ADCS2[R/W] B,H,W

0------- -------- ADCH2[R] B,H,W

-----000 ADMD2[R/W] B,H,W

----0000

0012B0H MTRCSR[R/W] B,H,W

-------0 - - - Motor cont rol

extension function

0012B4H

RTOSEL0[R/W]

B,H,W

--000000

RTOSEL1[R/W]

B,H,W

-------0 - -

0012B8H

0012FCH

- - - - Reserved

001300H - - - -

Reserved

001304H - - - -

001308H - - - -

00130CH - - - -

001310H - - - -

001314H - - - -

001318H - - - -

00131CH - - - -

001320H - - - -

001324H - -

Document Number: 002-04665 Rev *A Page 64 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001328H

00132CH

- - - - Reserved

001330H - -

001334H

0013FCH

- - - - Reserved

001400H DACR[R/W ] B, H,W

-------0 - DADR[R/W] H,W

------XX XXXXXX XX DAC

001404H

0014FCH

- - - - Reserved

001500H

SCR0/(IBCR0)

[R/W] B,H,W

0--00000

SMR0[R/W ] B, H,W

000000-0

SSR0[R/W]

B,H,W

0--00011

ESCR0/(IBSR0)

[R/W] B,H,W

00000000 Multi F unct i on

Serial I/F 0

*1: Byte access is

possible only for

access to lower 8

bits.

*2: Reserved

because I2C mode

is not set

immediately after

reset

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

001504H -/(RDR10/(TDR10))[R/W] B,H,W

-------- -------- *3 RDR00/(TDR00)[R/W] B,H,W

-------0 00000000 *1

001508H SACSR0[R/W] B,H,W

0----000 00000000 STMR0[ R ] B,H,W

00000000 00000000

00150CH STMCR0[R/W ] B, H,W

00000000 00000000 -/(S FUR0) [R/W] B,H,W

-------- -------- *4

001510H - - -/(SFLR10) [ R/W]

B,H,W

-------- *4

-/(SFLR00) [R/W]

B,H,W

-------- *4

001514H - - - -

001518H - - - -

00151CH BGR 0[R/W] H,W

00000000 00000000 -/(ISMK0)[R/W] B,H,W

-------- *2 -/(ISBA0)[R/W] B,H,W

-------- *2

001520H FCR10[R/W ] B, H,W

00-00100 FCR00[R/W] B,H,W

-0000000 F BYT E20 [R/W] B, H,W

00000000 FBYTE10[R/W] B,H,W

00000000

Document Number: 002-04665 Rev *A Page 65 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001524H

SCR1[R/W]

B,H,W

0--00000

SMR1[R/W ] B, H,W

000000-0

SSR1[R/W]

B,H,W

0--00011

ESCR1[R/W] B,H,W

00000000

Multi Function

Serial I/F 1

*1: Byte access is

possible only for

access to lower 8

bits.

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

001528H -/(RDR11/(TDR11))[R/W] B,H,W

-------- -------- *3 RDR01/(TDR01)[R/W] B,H,W

-------0 00000000 *1

00152CH SACSR1[R/W] B,H,W

0----000 00000000 STMR1[ R ] B,H,W

00000000 00000000

001530H STMCR1[R/W] B,H,W

00000000 00000000 -/(S CSCR1/SFUR1) [R/W] B,H,W

-------- -------- *3 *4

001534H

-/(SCSTR31) [R/W]

B,H,W

-------- *3

-/(SCSTR21) [R/W]

B,H,W

-------- *3

-/(SCSTR11/

SFLR11) [R/W] B,H,W

-------- *3 *4

-/(SCSTR01/

SFLR01) [R/W] B,H,W

-------- *3 *4

001538H - - - -

00153CH - - - TBYTE01[R/W]

B,H,W

00000000

001540H BGR 1[R /W] H,W

00000000 00000000 - -

001544H FCR11[R/W ] B, H,W

00-00100 FCR01[R/W] B,H,W

-0000000 F BYT E21 [R/W] B, H,W

00000000 FBYTE11[R/W] B,H,W

00000000

001548H

SCR2/(IBCR2)

[R/W] B,H,W

0--00000

SMR2[R/W ] B, H,W

000000-0

SSR2[R/W]

B,H,W

0--00011

ESCR2/(IBSR2)

[R/W] B,H,W

00000000 Multi F unct i on

Serial I/F 2

*1: Byte a ccess is

possible only for

access to lower 8

bits.

*2: Reserved

because I2C mode

is not set

immediately after

reset

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

00154CH -/(RDR12/(TDR12))[R/W] B,H,W

-------- -------- *3 RDR02/(TDR02)[R/W] B,H,W

-------0 00000000 *1

001550H SACSR2[R/W] B,H,W

0----000 00000000 STMR2[ R ] B,H,W

00000000 00000000

001554H STMCR2[R/W] B,H,W

00000000 00000000 -/(S CSCR2/SFUR2) [R/W] B,H,W

-------- -------- *3 *4

001558H

-/(SCSTR32) [R/W]

B,H,W

-------- *3

-/(SCSTR22) [R/W]

B,H,W

-------- *3

-/(SCSTR12/

SFLR12) [R/W] B,H,W

-------- *3 *4

-/(SCSTR02/

SFLR02) [R/W] B,H,W

-------- *3 *4

00155CH - - - -

001560H - - - TBYTE02[R/W]

B,H,W

00000000

001564H BGR 2[R /W] H,W

00000000 00000000 -/(ISMK2)[R/W] B,H,W

-------- *2 -/(ISBA2)[R/W] B,H,W

-------- *2

001568H FCR12[R/W ] B, H,W

00-00100 FCR02[R/W] B ,H,W

-0000000 F BYT E22 [R/W] B, H,W

00000000 FBYTE12[R/W] B,H,W

00000000

Document Number: 002-04665 Rev *A Page 66 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00156CH

SCR3/(IBCR3)

[R/W] B,H,W

0--00000

SMR3[R/W ] B, H,W

000000-0

SSR3[R/W]

B,H,W

0--00011

ESCR3/(IBSR3)

[R/W] B,H,W

00000000 Multi F unct i on

Serial I/F 3

*1: Byte access is

possible only for

access to lower 8

bits.

*2: Reserved

because I2C mode

is not set

immediately after

reset

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

001570H -/(RDR13/(TDR13))[R/W] B,H,W

-------- -------- *3 RDR03/(TDR03)[R/W] B,H,W

-------0 00000000 *1

001574H SACSR3[R/W] B,H,W

0----000 00000000 STMR3[ R ] B,H,W

00000000 00000000

001578H STMCR3[R/W] B,H,W

00000000 00000000 -/(S CSCR3/SFUR3) [R/W] B,H,W

-------- -------- *3 *4

00157CH

-/(SCSTR33) [R/W]

B,H,W

-------- *3

-/(SCSTR23) [R/W]

B,H,W

-------- *3

-/(SCSTR13/

SFLR13) [R/W] B,H,W

-------- *3 *4

-/(SCSTR03/

SFLR03) [R/W] B,H,W

-------- *3 *4

001580H - - - -

001584H - - - TBYTE03[R/W]

B,H,W

00000000

001588H BGR 3[R /W] H,W

00000000 00000000 -/(ISMK3)[R/W] B,H,W

-------- *2 -/(ISBA3)[R/W] B,H,W

-------- *2

00158CH FCR13[R/W ] B,H,W

00-00100 FCR03[R/W] B ,H,W

-0000000 F BYT E23 [R/W] B, H,W

00000000 FBYTE13[R/W] B,H,W

00000000

001590H

001FFCH

- - - - Reserved

002000H CTRLR0[R/W] B,H,W

-------- 000-0001 STATR0[R/W] B,H,W

-------- 00000000

CAN 0

64msb

002004H ERRCNT0 [R] B, H,W

00000000 00000000 BTR0[R/W] B,H,W

-0100011 00000001

002008H INTR0[ R] B, H,W

00000000 00000000 TESTR0[R/W] B,H,W

-------- X00000--

00200CH BRPER0[R/W] B,H,W

-------- ----0000 -

002010H IF1CRE Q0 [ R/W] B, H,W

0------- 00000001 IF1CMSK0[R/W] B,H,W

-------- 00000000

002014H IF1MSK20[R/W] B,H,W

11-11111 11111111 IF1MSK10[R/W] B,H,W

11111111 11111111

002018H IF1ARB20[R/W] B,H,W

00000000 00000000 IF1ARB10[R/W] B,H, W

00000000 00000000

00201CH IF1MCTR0[ R/W] B,H,W

00000000 0---0000 -

002020H IF1DTA10[R/W] B,H,W

00000000 00000000 IF1DTA20[R/W] B,H,W

00000000 00000000

002024H IF1DTB10[R/W] B,H,W

00000000 00000000 IF1DTB20[R/W] B,H,W

00000000 00000000

Document Number: 002-04665 Rev *A Page 67 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

002028H,

00202CH - -

CAN 0

64msb

002030H,

002034H Reserved (IF1 data mirror)

002038H,

00203CH - -

002040H IF2CRE Q0 [ R/W] B, H,W

0------- 00000001 IF2CMSK0[R/W] B,H,W

-------- 00000000

002044H IF2MSK20[R/W] B,H,W

11-11111 11111111 IF2MSK10[R/W] B,H,W

11111111 11111111

002048H IF2ARB20[R/W] B,H,W

00000000 00000000 IF2ARB10[R/W] B,H, W

00000000 00000000

00204CH IF2MCTR0[ R/W] B,H,W

00000000 0---0000 -

002050H IF2DTA10[R/W] B,H,W

00000000 00000000 IF2DTA20[R/W] B,H,W

00000000 00000000

002054H IF2DTB10[R/W] B,H,W

00000000 00000000 IF2DTB20[R/W] B,H,W

00000000 00000000

002058H,

00205CH - -

002060H,

002064H Reserved (IF2 data mirror)

002068H

00207CH

- -

002080H TREQR20[R] B,H,W

00000000 00000000 TRE Q R10 [R] B,H,W

00000000 00000000

002084H TREQR40[R] B,H,W

00000000 00000000 TRE Q R30 [R] B,H,W

00000000 00000000

002088H - -

00208CH - -

002090H NEWDT20[ R] B, H,W

00000000 00000000 NEWDT10[R] B,H,W

00000000 00000000

002094H NEWDT40[ R] B, H,W

00000000 00000000 NEWDT30[R] B,H,W

00000000 00000000

002098H - -

00209CH - -

0020A0H INTPND20[R] B,H,W

00000000 00000000 INT PND10[R] B,H,W

00000000 00000000

0020A4H INTPND40[R] B,H,W

00000000 00000000 INT PND30[R] B,H,W

00000000 00000000

0020A8H - -

0020ACH - -

Document Number: 002-04665 Rev *A Page 68 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0020B0H M SG VAL 2 0 [R] B,H,W

00000000 00000000 MSGVAL10 [R] B,H,W

00000000 00000000

CAN 0

64msb

0020B4H M SG VAL 4 0 [R] B,H,W

00000000 00000000 MSGVAL30 [R] B,H,W

00000000 00000000

0020B8H - -

0020BCH - -

0020C0H

0020FCH

- -

002100H CTRLR1[R/W] B,H,W

-------- 000-0001 STATR1[R/W] B,H,W

-------- 00000000

CAN 1

64msb

002104H ERRCNT1 [R] B, H,W

00000000 00000000 BTR1[R/W] B,H,W

-0100011 00000001

002108H INTR1[ R] B, H,W

00000000 00000000 TESTR1[R/W] B,H,W

-------- X00000--

00210CH BRPER1[R/W] B,H,W

-------- ----0000 -

002110H IF1CRE Q1 [ R/W] B, H,W

0------- 00000001 IF1CMSK1[R/W] B,H,W

-------- 00000000

002114H IF1MSK21[R/W] B,H,W

11-11111 11111111 IF1MSK11[R/W] B,H,W

11111111 11111111

002118H IF1ARB21[R/W] B,H,W

00000000 00000000 IF1ARB11[R/W] B,H, W

00000000 00000000

00211CH IF1MCTR1[ R/W] B,H,W

00000000 0---0000 -

002120H IF1DTA11[R/W] B,H,W

00000000 00000000 IF1DTA21[R/W] B,H,W

00000000 00000000

002124H IF1DTB11[R/W] B,H,W

00000000 00000000 IF1DTB21[R/W] B,H,W

00000000 00000000

002128H,

00212CH - -

002130H,

002134H Reserved (IF1 data mirror)

002138H,

00213CH - -

002140H IF2CRE Q1 [ R/W] B, H,W

0------- 00000001 IF2CMSK1[R/W] B,H,W

-------- 00000000

002144H IF2MSK21[R/W] B,H,W

11-11111 11111111 IF2MSK11[R/W] B,H,W

11111111 11111111

002148H IF2ARB21[R/W] B,H,W

00000000 00000000 IF2ARB11[R/W] B,H, W

00000000 00000000

00214CH IF2MCTR1[ R/W] B,H,W

00000000 0---0000 -

Document Number: 002-04665 Rev *A Page 69 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

002150H IF2DTA11[R/W] B,H,W

00000000 00000000 IF2DTA21[R/W] B,H,W

00000000 00000000

CAN 1

64msb

002154H IF2DTB11[R/W] B,H,W

00000000 00000000 IF2DTB21[R/W] B,H,W

00000000 00000000

002158H,

00215CH - -

002160H,

002164H Reserved (IF2 data mirror)

002168H

00217CH

- -

002180H TREQR21[R] B,H,W

00000000 00000000 TRE Q R11 [R] B,H,W

00000000 00000000

002184H TREQR41[R] B,H,W

00000000 00000000 TRE Q R31 [R] B,H,W

00000000 00000000

002188H - -

00218CH - -

002190H NEWDT21[ R] B, H,W

00000000 00000000 NEWDT11[ R] B, H,W

00000000 00000000

002194H NEWDT41[ R] B, H,W

00000000 00000000 NEWDT31[R] B,H,W

00000000 00000000

002198H - -

00219CH - -

0021A0H INTPND21[R] B,H,W

00000000 00000000 INT PND11[R] B,H,W

00000000 00000000

0021A4H INTPND41[R] B,H,W

00000000 00000000 INT PND31[R] B,H,W

00000000 00000000

0021A8H - -

0021ACH - -

0021B0H M SG VAL 2 1 [R] B,H,W

00000000 00000000 MSGVAL11 [R] B,H,W

00000000 00000000

0021B4H M SG VAL 4 1 [R] B,H,W

00000000 00000000 MSGVAL31 [R] B,H,W

00000000 00000000

0021B8H - -

0021BCH - -

0021C0H

0021FCH

- -

002200H

0022FCH

- - Reserved

Document Number: 002-04665 Rev *A Page 70 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

002300H DFCTLR[R/W] B,H,W

-0------ -------- - DFST R[R/W] B,H,W

-----001

WorkFlash

002304H - - - -

002308H

FLIFCTLR[R/W]

B,H,W

---0--00 - FLIFFER1[R/W]

B,H,W

--------

FLIFFER2[R/W]

B,H,W

--------

00230CH

002FFCH

- - - - Reserved

003000H SEEARX[R] B, H,W

--000000 00000000 DEEARX[R] B,H,W

--000000 00000000 XBS RAM

ECC control

003004H EECS RX[R/W ] B, H,W

----00-0 - EFEARX[R/W] B,H,W

--000000 00000000

003008H - EFECRX [R/W] B,H,W

-------0 00000000 00000000

00300CH TEAR0X[R] B, H,W

000----- -------- --000000 00000000

XBS RAM

diagnosis register

003010H TEAR1X[R] B, H,W

000----- -------- --000000 00000000

003014H TEAR2X[R] B, H,W

000----- -------- --000000 00000000

003018H TAEARX[R/W] B,H,W

--101111 11111111 TASARX[R/W] B,H,W

--000000 00000000

00301CH TFECRX[R/W] B,H,W

----0000 TI CRX[R/W] B,H,W

----0000 TTCRX[R/W] B,H,W

------00 00001100

003020H TSRCRX[R/W] B,H,W

0------- - - TKCCRX[R/W] B, H,W

00----00

003024H SEEARA[R] B,H,W

--000000 00000000 DEEARA[R] B,H,W

--000000 00000000 Back up RA M

ECC control

003028H EECSRA[R/W] B,H,W

----00-0 - EFEARA[R/W] B,H,W

--000000 00000000

00302CH - EFECRA[R/W] B,H,W

-------0 00000000 00000000

Document Number: 002-04665 Rev *A Page 71 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

003030H TEAR0A[R] B,H,W

000----- -------- -----000 00000000

Backup RAM

diagnosis register

003034H TEAR1A[R] B,H,W

000----- -------- -----000 00000000

003038H TEAR2A[R] B,H,W

000----- -------- -----000 00000000

00303CH TAEARA[R/W] B,H,W

-----111 11111111 TASARA[R/W] B,H,W

-----000 00000000

003040H TFECRA[R/W] B,H,W

----0000 TI CRA[R/W] B,H,W

----0000 TTCRA[R/W] B,H,W

------00 00001100

003044H TSRCRA[R/W] B,H,W

0------- - - TKCCRA[R/W] B, H,W

00----00

003048H

0030FCH

- - - - Reserved

003100H BUSDI GSR0[R/W] H,W

00000000 0-----00 BUSDIGSR1[ R/W] H,W

00000000 0-----00

Bus diagnosis

003104H BUSDI GSR2[R/W] H,W

00000000 0-----00 BUSTSTR0[ R/W] H,W

00--0000 00000000

003108H BUSADR0[R] W

00000000 00000000 00000000 00000000

00310CH BUSADR1[R] W

00000000 00000000 00000000 00000000

003110H BUSADR2[R] W

00000000 00000000 00000000 00000000

003114H - BUSDIGSR3[R/W] H,W

00000000 0-----00

003118H BUSDI GSR4[R/W] H,W

00000000 0-----00 BUSTSTR1[ R/W] H,W

00--0000 00000000

00311CH -

003120H BUSADR3[R] W

00000000 00000000 00000000 00000000

003124H BUSADR4[R] W

00000000 00000000 00000000 00000000 Bus diagnos is

003128H

003FFCH

- - - - Reserved

004000H

005FFCH

Backup RAM Backup RAM area

006000H

00CFFCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 72 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D000H CIF0[R] W

00000100 11111111 01011011 11111111 FlexRay

CIF *5

00D004H CIF1[R/W] W

00000000 -------0 -0000000 --------

00D008H

00D00CH

- - - - Reserved

00D010H -

FlexRay

GIF *5

00D014H -

00D018H - - - -

00D01CH LCK[R/W] W

-------- -------- -------- 00000000

00D020H EIR[R / W] W

-----000 -----000 ----0000 00000000

FlexRay

INT *5

00D024H SIR[R / W] W

------00 ------00 00000000 00000000

00D028H EILS[R / W] W

-----000 -----000 ----0000 00000000

00D02CH SILS[R / W] W

------11 ------11 11111111 11111111

00D030H EIES[R/W] W

-----000 -----000 ----0000 00000000

00D034H EIER[R/W] W

-----000 -----000 ----0000 00000000

00D038H SIES[R/W] W

------00 ------00 00000000 00000000

00D03CH SIER[R/W] W

------00 ------00 00000000 00000000

00D040H ILE[R / W] W

-------- -------- -------- ------00

00D044H T0C[R/W] W

--000000 00000000 -0000000 ------00

00D048H T1C[R/W] W

--000000 00000010 -------- ------00

00D04CH ST PW1 [ R /W] W

--000000 00000000 --000000 -0000000

00D050H STPW2[R] W

-----000 00000000 -----000 00000000

00D054H

00D07CH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 73 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D080H SUCC1[R/W] W

----1100 01000000 00010-00 1---0000

FlexRay

SUC *5

00D084H SUCC2[R/W] W

----0001 ---00000 00000101 00000100

00D088H SUCC3[R/W] W

-------- -------- -------- 00010001

00D08CH NEMC[R/W] W

-------- -------- -------- ----0000 FlexRay

NEM *5

00D090H PRTC1[R/W] W

000010-0 01001100 0000-110 00110011 FlexRay

PRT *5

00D094H PRTC2[R/W] W

--001111 00101101 --001010 --001110

00D098H MHDC[R/W] W

---00000 00000000 -------- -0000000 FlexRay

MHD *5

00D09CH - Reserved

00D0A0H GTUC1[R/W] W

-------- ----0000 00000010 10000000

FlexRay

GTU *5

00D0A4H GTUC2[R/W] W

-------- ----0010 --000000 00001010

00D0A8H GTUC3[R/W] W

-0000010 -0000010 00000000 00000000

00D0ACH GTUC4[R/W] W

--000000 00001000 --000000 00000111

00D0B0H GTUC5[R/W] W

00001110 ---00000 00000000 00000000

00D0B4H GTUC6[R/W] W

-----000 00000010 -----000 00000000

00D0B8H GTUC7[R/W] W

------00 00000010 ------00 000001 00

00D0BCH GTUC8[R/W] W

---00000 00000000 -------- --000010

00D0C0H GTUC9[R/W] W

-------- ------00 ---00001 --000001

00D0C4H GTUC10[R/W] W

-----000 00000010 --000000 00000101

00D0C8H GTUC11[R/W] W

-----000 -----000 ------00 ------00

00D0CCH

00D0FCH

- Reserved

Document Number: 002-04665 Rev *A Page 74 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D100H CCSV[R] W

--000000 00010000 -100--00 00000000 FlexRay

SUC *5

00D104H CCEV[R] W

-------- -------- ---00000 00--0000

00D108H

00D10CH - Reserved

00D110H SCV[R ] W

-----000 00000000 -----000 00000000

FlexRay

GTU *5

00D114H MTCCV[R] W

-------- --000000 --000000 00000000

00D118H RCV[R] W

-------- -------- ----0000 00000000

00D11CH OCV[R] W

-------- -----000 00000000 00000000

00D120H SFS[R] W

-------- ----0000 00000000 00000000

FlexRay

GTU *5

00D124H S WNIT[R ] W

-------- -------- ----0000 00000000

00D128H ACS[R / W] W

-------- -------- ---00000 ---00000

00D12CH -

00D130H ESID1[R] W

-------- -------- 00----00 00000000

00D134H ESID2[R] W

-------- -------- 00----00 00000000

00D138H ESID3[R] W

-------- -------- 00----00 00000000

00D13CH ESID4[R] W

-------- -------- 00----00 00000000

00D140H ESID5[R] W

-------- -------- 00----00 00000000

00D144H ESID6[R] W

-------- -------- 00----00 00000000

00D148H ESID7[R] W

-------- -------- 00----00 00000000

00D14CH ESID8[R] W

-------- -------- 00----00 00000000

00D150H ESID9[R] W

-------- -------- 00----00 00000000

00D154H ESID10[R] W

-------- -------- 00----00 00000000

00D158H ESID11[R] W

-------- -------- 00----00 00000000

Document Number: 002-04665 Rev *A Page 75 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D15CH ESID12[R] W

-------- -------- 00----00 00000000

FlexRay

GTU *5

00D160H ESID13[R] W

-------- -------- 00----00 00000000

00D164H ESID14[R] W

-------- -------- 00----00 00000000

00D168H ESID15[R] W

-------- -------- 00----00 00000000

00D16CH -

00D170H OSID1 [R ] W

-------- -------- 00----00 00000000

00D174H OSID2 [R ] W

-------- -------- 00----00 00000000

00D178H OSID3 [R ] W

-------- -------- 00----00 00000000

00D17CH OSID4[R] W

-------- -------- 00----00 00000000

00D180H OSID5 [R ] W

-------- -------- 00----00 00000000

00D184H OSID6 [R ] W

-------- -------- 00----00 00000000

00D188H OSID7 [R ] W

-------- -------- 00----00 00000000

00D18CH OSID8[R] W

-------- -------- 00----00 00000000

00D190H OSID9 [R ] W

-------- -------- 00----00 00000000

00D194H OSID1 0[R ] W

-------- -------- 00----00 00000000

00D198H OSID1 1[R ] W

-------- -------- 00----00 00000000

00D19CH OSID12 [R ] W

-------- -------- 00----00 00000000

00D1A0H OSID13 [R ] W

-------- -------- 00----00 00000000

00D1A4H OSID14 [R ] W

-------- -------- 00----00 00000000

00D1A8H OSID15 [R ] W

-------- -------- 00----00 00000000

00D1ACH - Reserved

Document Number: 002-04665 Rev *A Page 76 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D1B0H NMV1[R] W

00000000 00000000 00000000 00000000

FlexRay

NEM *5

00D1B4H NMV2[R] W

00000000 00000000 00000000 00000000

00D1B8H NMV3[R] W

00000000 00000000 00000000 00000000

00D1BCH

00D2FCH

- Reserved

00D300H MRC[R/W] W

-----001 10000000 00000000 00000000

FlexRay

MHD *5

00D304H FRF[R/W] W

-------1 10000000 ---00000 00000000

00D308H FRFM[R/W] W

-------- -------- ---00000 000000--

00D30CH FCL[R/W] W

-------- -------- -------- 10000000

00D310H MHDS[R/W] W

-0000000 -0000000 -0000000 00000000

00D314H LDTS[R] W

-----000 00000000 -----000 00000000

00D318H FSR[R] W

-------- -------- 00000000 -----000

00D31CH MHDF[R/W] W

-------- -------- -------0 00000000

00D320H TXRQ1[R] W

00000000 00000000 00000000 00000000

00D324H TXRQ2[R] W

00000000 00000000 00000000 00000000

00D328H TXRQ3[R] W

00000000 00000000 00000000 00000000

00D32CH TXRQ4[R] W

00000000 00000000 00000000 00000000

00D330H NDAT1[R] W

00000000 00000000 00000000 00000000

00D334H NDAT2[R] W

00000000 00000000 00000000 00000000

00D338H NDAT3[R] W

00000000 00000000 00000000 00000000

Document Number: 002-04665 Rev *A Page 77 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D33CH NDAT4[R] W

00000000 00000000 00000000 00000000

FlexRay

MHD *5

00D340H MBSC1[R] W

00000000 00000000 00000000 00000000

00D344H MBSC2[R] W

00000000 00000000 00000000 00000000

00D348H MBSC3[R] W

00000000 00000000 00000000 00000000

00D34CH MBSC4[R] W

00000000 00000000 00000000 00000000

00D350H

00D3ECH

- Reserved

00D3F0H CREL[R] W

00010000 00111001 00000010 00000110 FlexRay

GIF *5

00D3F4H ENDN[R] W

10000111 01100101 01000011 00100001

00D3F8H

00D3FCH

- Reserved

00D400H

00D4FCH

WRDSn[1-64][R/W] W

00000000 00000000 00000000 00000000

FlexRay

IBF *5

00D500H WRHS1[R/W] W

--000000 -0000000 -----000 00000000

00D504H WRHS2[R/W] W

-------- -0000000 -----000 00000000

00D508H WRHS3[R/W] W

-------- -------- -----000 00000000

00D50CH -

00D510H IBCM[R/W] W

-------- ------00 -------- -----000

00D514H IBCR[R/ W] W

0------- -0000000 0------- -0000000

00D518H

00D5FCH

- Reserved

Document Number: 002-04665 Rev *A Page 78 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D600H

00D6FCH

RDDSn[1-64][R] W

00000000 00000000 00000000 00000000

FlexRay

OBF *5

00D700H RDHS1[R] W

--000000 -0000000 -----000 00000000

00D704H RDHS2[R] W

-0000000 -0000000 -----000 0000 0000

00D708H RDHS3[R] W

--000000 --000000 -----000 00000000

00D70CH MBS[R] W

--000000 --000000 00-00000 00000000

00D710H OBCM[R/W] W

-------- ------00 -------- ------00

00D714H OBCR[R/W] W

-------- -0000000 0-----00 -0000000

00D718H

00D7FCH

- Reserved

00D800H

00EFFCH

- Reserved

00F000H

00FEFCH

- Reserved [S]

00FF00H DSUCR[R/W] B,H,W

-------- -------0 - - OCDU [S]

00FF04H

00FF0CH

- - - - Reserved [S]

00FF10H PCSR[R/W] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX OCDU [S]

00FF14H PS SR [R /W] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

00FF18H

00FFF4H

- - - - Reserved [S]

00FFF8H E DIR1[R] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX OCDU [S]

00FFFCH E DIR0[R] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and

writing to these registers in the user mode.

*5: For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ has corresponding

functions.

Document Number: 002-04665 Rev *A Page 79 of 175

MB91580M/S Series

The following registers are reserved registers for models without the FlexRay function.

000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H

Document Number: 002-04665 Rev *A Page 80 of 175

MB91580M/S Series

 I/O Map (MB91F583AS/F584AS/F585AS)

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000000H - PDR0 1[R/W] B,H,W

XXXXXXXX P DR0 2[R/W] B,H,W

XXXXXXXX P DR0 3[R/W] B,H,W

XXXXXXXX

Port data register

000004H PDR04[R/W] B,H,W

XXXXXXXX P DR0 5[R/W] B,H,W

-XXXXXXX - PDR07[R/W] B,H,W

-----XXX

000008H - PDR0 9[R/W] B,H,W

---XX--- - -

00000CH - - - -

000010H

000038H

- - - - Reserved

00003CH

WDTCR0[R/W]

B,H,W

-0--0000

WDTCPR0[W]

B,H,W

00000000

WDTCR1[R]

B,H,W

----0010

WDTCPR1[W]

B,H,W

00000000 Watchdog timer [S]

000040H - - - Reserved

000044H DICR[R/W] B

-------0 - - - Delay interrupt

000048H

00005CH

- - Reserved

000060H TMRLRA0[R/W] H

XXXXXXX X XXXX XX XX TMR0[ R] H

XXXXXXX X XXXX XX XX Reload t imer 0

000064H TMRLRB0[R/W] H

XXXXXXX X XXXX XX XX TMCS R0[R/W] B,H,W

00000000 0-000000

000068H

00007CH

- - - - Reserved

000080H BT 0T MR[ R] H

00000000 00000000 BT 0 T MCR[ R/W] H

-0000000 00000000

Base timer 0

000084H

BT0TMCR2

[R/W] B

-------0

BT0STC

[R/W] B

-0-0-0-0 - -

000088H

BT0PCSR/BT0PRLL

[R/W] H

00000000 00000000

BT0PDUT/BT0PRLH/BT0DTBF

[R/W] H

00000000 00000000

00008CH - - - -

Document Number: 002-04665 Rev *A Page 81 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000090H BT 1T MR[ R] H

00000000 00000000 BT 1 T MCR[ R/W] H

-0000000 00000000

Base timer 1

000094H

BT1TMCR2

[R/W] B

-------0

BT1STC

[R/W] B

-0-0-0-0 - -

000098H

BT1PCSR/BT1PRLL

[R/W] H

00000000 00000000

BT1PDUT/BT1PRLH/BT1DTBF

[R/W] H

00000000 00000000

00009CH BTSEL01[R/W] B

----0000 - BTSSSR[W] B,H

-------- ------11 Bas e timer 0, 1

0000A0H

0000FCH

- - - - Reserved

000100H TMRLRA1[R/W] H

XXXXXXX X XXXX XX XX TMR1[ R] H

XXXXXXX X XXXXXXXX Rel oad timer 1

000104H TMRLRB1[R/W] H

XXXXXXX X XXXX XX XX TMCS R1[R/W] B,H,W

00000000 0-000000

000108H TMRLRA2[R/W] H

XXXXXXX X XXXX XX XX TMR2[ R] H

XXXXXXX X XXXX XX XX Reload t imer 2

00010CH TMRLRB2[R/W] H

XXXXXXX X XXXX XX XX TMCS R2[R/W] B,H,W

00000000 0-000000

000110H TMRLRA3[R/W] H

XXXXXXX X XXXX XX XX TMR3[ R] H

XXXXXXX X XXXX XX XX Reload t imer 3

000114H TMRLRB3[R/W] H

XXXXXXX X XXXX XX XX TMCS R3[R/W] B,H,W

00000000 0-000000

000118H

00011CH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 82 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000120H IRPR0H[R] B,H,W

00------ IRPR0L[R] B,H,W

00------ IRPR1H[R] B,H,W

00------ IRPR1L[R] B,H,W

--------

Interrupt request

batch read register

000124H IRPR2H[R] B,H,W

--------

IRPR2L[R]

B,H,W *5

0000----

IRPR3H[ R] B, H,W

00------ IRPR3L[R] B,H,W

00------

000128H IRPR4H[R] B,H,W

00------ IRPR4L[R] B,H,W

000000-- IRPR5H[R] B,H,W

00------ IRPR5L[R] B,H,W

00------

00012CH IRP R6H[R] B,H,W

0000---- IRPR6L[R] B,H,W

00------ IRPR7H[R] B,H,W

00------ IRPR7L[R] B,H,W

--------

000130H IRPR8H[R] B,H,W

-------- IRPR8L[R] B,H,W

00------ IRPR9H[R] B,H,W

00------ IRPR9L[R] B,H,W

00------

000134H IRPR10H[R] B,H,W

00------ IRPR10L[R] B,H,W

00------ IRPR11H[R] B,H,W

00------ IRPR11L[R] B,H,W

0000000-

000138H IRPR12H[R] B,H,W

0000000- IRPR12L[R] B,H,W

00000000 IRPR13H[R] B,H,W

0000000- IRPR13L[ R] B,H,W

---00---

00013CH IRP R14 H[R] B,H,W

00------ IRPR14L[R] B,H,W

00------ IRPR15H[R] B,H,W

00000000 IRPR15L[R] B,H,W

0000----

000140 H IRPR16H[R] B,H,W

00------ IRPR16L[R] B,H,W

-------- IRPR17H[R] B,H,W

--------

IRPR17L[R]

B,H,W

--------

000144 H IRPR18H[R]B,H,W

-------- IRPR18L[R]B,H,W

000000-- - -

000148H

0001FCH

- - - - Reserved

000200H PCN0[R/W] B,H,W

00000000 000000-0 PCSR0 [W] H,W

XXXXXXX X XXXX XX XX PPG0

000204H PDUT 0[W] H,W

XXXXXXX X XXXX XX XX P T MR0[ R] H,W

11111111 11111111

000208H PCN1[R/W] B,H,W

00000000 000000-0 PCSR1 [W] H,W

XXXXXXX X XXXX XX XX PPG1

00020CH PDUT1 [W] H,W

XXXXXXX X XXXX XX XX P T MR1[ R] H,W

11111111 11111111

000210H PCN2[R/W] B,H,W

00000000 000000-0 PCSR2 [W] H,W

XXXXXXX X XXXX XX XX PPG2

000214H PDUT 2[W] H,W

XXXXXXX X XXXXXXXX PTMR2[R] H,W

11111111 11111111

000218H PCN3[R/W] B,H,W

00000000 000000-0 PCSR3 [W] H,W

XXXXXXX X XXXX XX XX PPG3

00021CH PDUT3 [W] H,W

XXXXXXX X XXXX XX XX P T MR3[ R] H,W

11111111 11111111

Document Number: 002-04665 Rev *A Page 83 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000220H PCN4[R/W] B,H,W

00000000 000000-0 PCSR4 [W] H,W

XXXXXXX X XXXX XX XX PPG4

000224H PDUT 4[W] H,W

XXXXXXX X XXXX XX XX P T MR4[ R] H,W

11111111 11111111

000228H PCN5[R/W] B,H,W

00000000 000000-0 PCSR5 [W] H,W

XXXXXXX X XXXX XX XX PPG5

00022CH PDUT5 [W] H,W

XXXXXXX X XXXX XX XX P T MR5[ R] H,W

11111111 11111111

000230H

0002BCH

- - Reserved

0002C0H G TRS 0[R/W] B,H,W

-0000000 -0000000 G TRS1[R/W] B ,H,W

-0000000 -0000000

PPG Control

0002C4H G TRS 2[R/W] B,H,W

-0000000 -0000000 -

0002C8H - -

0002CCH - -

0002D0H - -

0002D4H - -

0002D8H GTRE N0[R/W] H,W

-------- --000000 -

0002DCH - - Reserved

0002E0H - GATEC0[R/W] B,H,W

------00 - GATEC2[R/W] B,H,W

------00

PPG GATE Control

0002E4H - GATEC4[R/W] B,H,W

------00 - -

0002E8H - - - -

0002ECH - - - - Reserved

0002F0H

RCRH0[W]

H,W

00000000

RCRL0[W]

B,H,W

00000000

UDCRH0[R]

H,W

00000000

UDCRL0[R] B, H,W

00000000 U/D c ounter 0

0002F4H CCR0[R/W] B,H

00000000 -0001000 - CSR0[R] B

00000000

0002F8H

RCRH1[W]

H,W

00000000

RCRL1[W]

B,H,W

00000000

UDCRH1[R]

H,W

00000000

UDCRL1[R] B, H,W

00000000 U/D c ounter 1

0002FCH CCR1[R/W] B,H

00000000 -0001000 - CSR1[R] B

00000000

000300H - Reserved

000304H - - - - Reserved

000308H - Reserved

00030CH - - - -

Document Number: 002-04665 Rev *A Page 84 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000310H - - MPUCR[R/W] H

000000-0 ----0100

MPU [S]

(Only the CPU can

access this area)

000314H - - - -

000318H -

00031CH - - -

000320H DPVAR[R ] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000324H - - DPVSR[R/W] H

-------- 00000--0

000328H DEAR[R] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

00032CH - - DESR[ R/W] H

-------- 00000--0

000330H PABR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000334H - - PACR0[R/W] H

000000-0 00000--0

000338H PABR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

00033CH - - PACR1[R/W] H

000000-0 00000--0

000340H PABR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000344H - - PACR2[R/W] H

000000-0 00000--0

000348H PABR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

00034CH - - PACR3[R/W] H

000000-0 00000--0

000350H PABR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000354H - - PACR4[R/W] H

000000-0 00000--0

000358H PABR5[R/W] W

XXXXXXX X XXXX XXXX XXXX XX XX XXXX0 000

00035CH - - PACR5[R/W] H

000000-0 00000--0

000360H PABR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000

000364H - - PACR6[R/W] H

000000-0 00000--0

Document Number: 002-04665 Rev *A Page 85 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000368H PABR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX0 000 MPU [ S]

(Only the CPU can

access this area)

00036CH - - PACR7[R/W] H

000000-0 00000--0

000370H -

Reserved [S]

000374H - - -

000378H -

00037CH - - -

000380H -

000384H - - -

000388H -

00038CH - - -

000390H -

000394H - - -

Reserved [S]

000398H -

00039CH - - -

0003A0H -

0003A4H - - -

0003A8H -

0003ACH - - -

0003B0H

0003CCH

- - - - Reserved [S]

0003D0H -

Reserved [S]

0003D4H -

0003D8H -

0003DCH -

0003E0H

0003FCH

- - - - Reserved [S]

Document Number: 002-04665 Rev *A Page 86 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000400H ICSEL0[R/W] B,H,W

-----000 ICSEL1[R/W] B,H,W

-------0 ICSEL2[R/W] B,H,W

-------0 ICSEL3[R/W] B,H,W

-------0

Generation and

clear of DMA

transfer request

000404H ICSEL4[R/W] B,H,W

-------0 ICSEL5[R/W] B,H,W

-------0 ICSEL6[R/W] B,H,W

-------0 ICSEL7[R/W] B,H,W

-----000

000408H ICSEL8[R/W] B,H,W

-------0 ICSEL9[R/W] B,H,W

-------0 ICSEL10[R/W] B,H,W

------00 ICSEL11[R/W] B,H,W

-------0

00040CH ICSEL12[R/W] B,H,W

-------0 ICSEL13[R/W] B,H,W

-------0 ICSEL14[R/W] B,H,W

-------0 ICSEL15[R/W] B,H,W

-------0

000410H ICSEL16[R/W] B,H,W

-------0 ICSEL17[R/W] B,H,W

-------0 ICSEL18[R/W] B,H,W

-------0 ICSEL19[R/W] B,H,W

-------0

000414H ICSEL20[R/W] B,H,W

-------0 ICSEL21[R/W] B,H,W

-----000 ICSEL22[R/W] B,H,W

-----000 ICSEL23[R/W] B,H,W

-----000

000418H ICSEL24[R/W] B,H,W

-----000 ICSEL25[R/W] B,H,W

-----000 ICSEL26[R/W] B,H,W

-------0 ICSEL27[R/W] B,H,W

-------0

00041CH - - - -

000420H - - - -

000424H

00043CH

- - - - Reserved

000440H ICR00[R/W] B,H,W

---11111 ICR01 [R/W] B,H,W

---11111 ICR02 [R/W] B,H,W

---11111 ICR03 [R/W] B,H,W

---11111

Interrupt controller

[S]

000444H ICR04[R/W] B,H,W

---11111 ICR05 [R/W] B,H,W

---11111 ICR06 [R/W] B,H,W

---11111 ICR07 [R/W] B,H,W

---11111

000448H ICR08[R/W] B,H,W

---11111 ICR09 [R/W] B,H,W

---11111 ICR10 [R/W] B,H,W

---11111 ICR11 [R/W] B,H,W

---11111

00044CH ICR12[R/W] B,H,W

---11111 ICR13 [R/W] B,H,W

---11111 ICR14 [R/W] B,H,W

---11111 ICR15 [R/W] B,H,W

---11111

000450H ICR16[R/W] B,H,W

---11111 ICR17 [R/W] B,H,W

---11111 ICR18 [R/W] B,H,W

---11111 ICR19 [R/W] B,H,W

---11111

000454H ICR20[R/W] B,H,W

---11111 ICR21 [R/W] B,H,W

---11111 ICR22 [R/W] B,H,W

---11111 ICR23 [R/W] B,H,W

---11111

000458H ICR24[R/W] B,H,W

---11111 ICR25 [R/W] B,H,W

---11111 ICR26 [R/W] B,H,W

---11111 ICR27 [R/W] B,H,W

---11111

00045CH ICR28[R/W] B,H,W

---11111 ICR29 [R/W] B,H,W

---11111 ICR30 [R/W] B,H,W

---11111 ICR31 [R/W] B,H,W

---11111

000460H ICR32[R/W] B,H,W

---11111 ICR33 [R/W] B,H,W

---11111 ICR34 [R/W] B,H,W

---11111 ICR35 [R/W] B,H,W

---11111

000464H ICR36[R/W] B,H,W

---11111 ICR37 [R/W] B,H,W

---11111 ICR38 [R/W] B,H,W

---11111 ICR39 [R/W] B,H,W

---11111

000468H ICR40[R/W] B,H,W

---11111 ICR41 [R/W] B,H,W

---11111 ICR42 [R/W] B,H,W

---11111 ICR43 [R/W] B,H,W

---11111

00046CH ICR44[R/W] B,H,W

---11111 ICR45 [R/W] B,H,W

---11111 ICR46 [R/W] B,H,W

---11111 ICR47 [R/W] B,H,W

---11111

Document Number: 002-04665 Rev *A Page 87 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000470H

00047CH

- - - - Reserved [S]

000480H

RSTRR[R]

B,H,W

XXXX--XX

RSTCR[R/W] B,H, W

111----0 STBCR[R/W] B,H,W

000---11 * -

Reset control [S]

Power

consumption

control [S]

* Writing to STBCR

by DMA is

disabled.

000484H - - - - Res erved [ S]

000488H DIVR0[R/W] B,H,W

000----- - DIVR2[R/W] B,H,W

0011---- - Clock control [S]

00048CH - - - - Res erved [ S]

000490H IORR0[R/W] B,H,W

-0000000 IORR1[R/W] B,H,W

-0000000 IORR2[R/W] B,H,W

-0000000 IORR3[R/W] B,H,W

-0000000 DMA transfer

request from a

peripheral [S]

000494H IORR4[R/W] B,H,W

-0000000 IORR5[R/W] B,H,W

-0000000 IORR6[R/W] B,H,W

-0000000 IORR7[R/W] B,H,W

-0000000

000498H - - - -

00049CH - - - -

0004A0H - - - - Reserved

0004A4H CANPRE[R/W] B,H,W

---00000 - - - CA N prescal er

0004A8H

0004ACH

- - - - Reserved

0004B0H - - - - Reserved

0004B4H

0004C0H

- - - - Reserved

0004C4H CUCR1[R/W] B,H,W

-------- ---0--00 CUT D1[R/W] B,H,W

11000011 01010000 WDT1 calibration

0004C8H CUTR1[R] B,H,W

-------- 00000000 00000000 00000000

0004CCH

0004DCH

- - - - Reserved

0004E0H - - CSCFG[R/W] B,H,W

---0---- CMCFG[R/W] B,H,W

00000000 Clock monitor

0004E4H - - - -

Document Number: 002-04665 Rev *A Page 88 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0004E8H

PLL2DIVM[R/W]

B,H,W

----0000

PLL2DIVN[R/W]

B,H,W

-0000000

PLL2DIVG[R/W]

B,H,W

----0000

PLL2MULG[R/W]

B,H,W

00000000 FlexRay

clock control *5

0004ECH

PLL2CTRL[R/W]

B,H,W

----0000

PLL2DIVK[R/W]

B,H,W

-------0

CLKR2[R/W] B,H,W

000--000 -

0004F0H

0004FCH

- - - - Reserved

000500H - Reserved

000504H - Reserved

000508H

00050CH

- - - - Reserved

000510H CSELR[R/W] B,H,W

-0----00 CMONR[R] B,H,W

-01---00 MTMCR[R/W] B,H,W

00001111 - Clock control [S]

000514H PLLCR[R/W] B,H,W

00-00000 11110000 CST B R[R/W] B,H,W

----0000 PT MCR[ R/W] B,H,W

00------

000518H - - CPUAR[R/W] B,H,W

0---XXXX - Reset [S]

00051CH - - - Reserved [S]

000520H

CCPSSELR[R/W]

B,H,W

-------0 - - CCPSDIVR[R/W]

B,H,W

-000-000

Clock control 2

000524H - CCPLLFBR[R/W]

B,H,W

-0000000

CCSSFBR0[R/W]

B,H,W

--000000

CCSSFBR1[R/W]

B,H,W

---00000

000528H - CCSSCCR0[R/W]

B,H,W

----0000

CCSSCCR1[R/W] B,H,W

000----- --------

00052CH - CCCGRCR0[R/W]

B,H,W

00----00

CCCGRCR1[R/W]

B,H,W

00000000

CCCGRCR2[R/W]

B,H,W

00000000

000530H - - CCPMUCR0[R/W]

B,H,W

0-----00

CCPMUCR1[R/W]

B,H,W

0--00000

000534H - - - -

000538H - - - -

00053CH - - - -

000540H

00054CH

- - - - Reserved

000550H EIRR0[R/W] B,H,W

-XXXXXXX ENIR0[R/W] B,H, W

-0000000 ELVR0[R /W] B ,H,W

--000000 00000000 External interrupt

(INT0 to 6)

Document Number: 002-04665 Rev *A Page 89 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000554H

000568H

- - - - Reserved

00056CH - CSVCR[R/W] B

-0--1--0 - - CSV

000570H CRTR[ R/W] B,H,W

01111111 - - - WDT1 calibration

(trimming)

000574H

00057CH

- - - - Reserved

000580H REGSEL[R /W] B,H,W

01--110- - - - Regulator c ont rol

000584H LVD5R[R/W] B,H,W

-------1 LVD5F[R/W] B,H,W

001100-1

LVD[R/W]

B,H,W

01000--0 - Low-voltage

detection

000588H

00058CH

- - - - Reserved

000590H

PMUSTR [ R/W]

B,H,W

0-----1X

PMUCTLR[R/W]

B,H,W

0-00----

PWRTMCTL[R/W]

B,H,W

-----011 -

PMU

000594H - PMUINTF1[R/W]

B,H,W

00000000

PMUINTF2[R/W]

B,H,W

-00----- -

000598H - - - -

00059CH - - - -

0005A0H

0005FCH

- - - - Reserved

000600H

00060CH

- Reserved [S]

000610H

00063CH

- - - - Reserved [S]

000640H

00064CH

- Reserved [S]

000650H

00067CH

- - - - Reserved [S]

000680H

00068CH

- Reserved [S]

Document Number: 002-04665 Rev *A Page 90 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000690H

0006BCH

- - - - Reserved [S]

0006C0H

0006CCH

- Reserved [S]

0006D0H

0006F0H

- - - - Reserved

0006F4H - Reserved

0006F8H

0006FCH

- - - - Reserved

000700H - Reserved

000704H

00070CH

- - - - Reserved

000710H BPCCRA[R/W] B

00000000 BPCCRB[R/W] B

00000000 BPCCRC[R/W] B

00000000 -

Bus performance

counter

000714H BPCTRA[R / W] W

00000000 00000000 00000000 00000000

000718H BPCTRB[R / W] W

00000000 00000000 00000000 00000000

00071CH BPCTRC[R/W] W

00000000 00000000 00000000 00000000

000720H

0007F8H

- - - - Reserved

0007FCH BMODR[R] B,H,W

XXXXXXXX - - - Operation mode

000800H

00083CH

- - - - Reserved [S]

000840H FCTLR[R/W] H

-0--1000 0--0---- - FSTR[R/W] B

-----001 Flash memory

000844H - - - - Res erved [ S]

000848H

000854H

- - - - Reserved [S]

000858H - - WREN[R/W] H

00000000 00000000 Wild register [S]

Document Number: 002-04665 Rev *A Page 91 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00085CH

00087CH

- - - - Reserved [S]

000880H WRAR00[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

Wild register [S]

000884H WRDR00[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000888H WRAR01[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

00088CH WRDR01[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000890H WRAR02[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

000894H WRDR02[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000898H WRAR03[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

00089CH WRDR03[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008A0H WRAR04[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008A4H WRDR04[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008A8H WRAR05[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008ACH WRDR05[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008B0H WRAR06[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008B4H WRDR06[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008B8H WRAR07[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008BCH WRDR07[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXXXXXX

0008C0H WRAR08[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008C4H WRDR08[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008C8H WRAR09[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008CCH WRDR09[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

Document Number: 002-04665 Rev *A Page 92 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0008D0H WRAR10[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

Wild register [S]

0008D4H WRDR10[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008D8H WRAR11[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008DCH WRDR11[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008E0H WRAR12[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008E4H WRDR12[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008E8H WRAR13[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008ECH WRDR13[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008F0H WRAR14[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008F4H WRDR14[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

0008F8H WRAR15[R/W] W

-------- --XXXX XX XXX XX XXX XXXXX X--

0008FCH WRDR15[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000900H

000BF8H

- - - - Reserved

000BFCH - UE R[W] B,H,W

-------- -------X OCDU

Document Number: 002-04665 Rev *A Page 93 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000C00H DCCR0[R/W] W

0----000 --00--00 00000000 0-000000

DMA controller [S]

000C04H DCSR0[ R/W] H

0------- -----000 DT CR0[R/W] H

00000000 00000000

000C08H DSAR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C0CH DDAR0[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C10H DCCR1[R/W] W

0----000 --00--00 00000000 0-000000

000C14H DCSR1[ R/W] H

0------- -----000 DT CR1[R/W] H

00000000 00000000

000C18H DSAR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXXXXXX

000C1CH DDAR1[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C20H DCCR2[R/W] W

0----000 --00--00 00000000 0-000000

000C24H DCSR2[ R/W] H

0------- -----000 DT CR2[R/W] H

00000000 00000000

000C28H DSAR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C2CH DDAR2[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C30H DCCR3[R/W] W

0----000 --00--00 00000000 0-000000

000C34H DCSR3[ R/W] H

0------- -----000 DT CR3[R/W] H

00000000 00000000

000C38H DSAR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C3CH DDAR3[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C40H DCCR4[R/W] W

0----000 --00--00 00000000 0-000000

000C44H DCSR4[ R/W] H

0------- -----000 DT CR4[R/W] H

00000000 00000000

Document Number: 002-04665 Rev *A Page 94 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000C48H DSAR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

DMA c ontroller [S]

000C4CH DDAR4[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C50H DCCR5[R/W] W

0----000 --00--00 00000000 0-000000

000C54H DCSR5[ R/W] H

0------- -----000 DT CR5[R/W] H

00000000 00000000

000C58H DSAR5[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXXXXXX

000C5CH DDAR5[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C60H DCCR6[R/W] W

0----000 --00--00 00000000 0-000000

000C64H DCSR6[ R/W] H

0------- -----000 DT CR6[R/W] H

00000000 00000000

000C68H DSAR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C6CH DDAR6[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C70H DCCR7[R/W] W

0----000 --00--00 00000000 0-000000

000C74H DCSR7[ R/W] H

0------- -----000 DT CR7[R/W] H

00000000 00000000

000C78H DSAR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C7CH DDAR7[R/W] W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

000C80H

000DF0H

- - - -

000DF4H - - DNMIR[R/W] B

0------0 DILVR[R/W] B

---11111

000DF8H DMACR[R/W] W

0------- -------- 0------- --------

000DFCH - - - - Res erved [ S]

000E00H - DDR01[R/W] B,H

00000000 DDR02[R/W] B,H

00000000 DDR03[R/W] B,H

00000000

Data direction

000E04H DDR04[R/W] B,H

00000000 DDR05[R/W] B,H

-0000000 - DDR07[R/W] B,H

-----000

000E08H - DDR09[R/W] B,H

---00--- - -

000E0CH - - - -

Document Number: 002-04665 Rev *A Page 95 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000E10H

000E1CH

- - - - Reserved

000E20H - PFR01[R/W] B,H

00000000 PFR02[R/W] B,H

00000000 PFR03[R/W] B,H

00000000

Port function

000E24H PFR04[R/W] B,H

00000000 PFR05[R/W] B,H

-0000000 - PFR07[R/W] B,H

-----000

000E28H - PFR09[R/W] B,H

---00--- - -

000E2CH - - - -

000E30H

000E3CH

- - - - Reserved

000E40H - PDDR01[R] B,H,W

XXXXXXXX PDDR02[R] B,H,W

XXXXXXXX PDDR03[R] B,H,W

XXXXXXXX

Input data direct

read register

000E44H PDDR04[R] B,H,W

XXXXXXXX PDDR05[R] B,H,W

-XXXXXXX - PDDR07[R] B,H,W

-----XXX

000E48H - PDDR09[R] B,H,W

---XX--- - -

000E4CH - - - -

000E50H

000E5CH

- - - - Reserved

000E60H EPFR00[R/W] B,H

-------0 EPFR01[R/W] B,H

------00 EPFR02[R/W] B, H

-----000 EPFR03[R/W] B, H

--000000

Extended port

function regist er

000E64H - - EPFR06[R/W] B, H

------00 EPFR07[R/W] B,H

----0000

000E68H

EPFR08[R/W]

B,H *5

----0000

EPFR09[R/W] B,H

-------0 EP FR10[R/W] B,H

-0000000 -

000E6CH - - - -

000E70H - - - -

000E74H - - - -

000E78H - - - -

000E7CH - - - -

000E80H - - - -

000E84H

000EBCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 96 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000EC0H - PPER01[R /W] B,H

00000000 PPER02[R /W] B,H

00000000 PPER03[R /W] B,H

00000000

Port pull-up/down

enable regist er

000EC4H PPER04[R /W] B,H

00000000 PPER05[R /W] B,H

-0000000 - PPER07[R /W] B,H

-----000

000EC8H - PPER09[R /W] B,H

---00--- - -

000ECCH - - - -

000ED0H

000EDCH

- - - - Reserved

000EE0H - PILR01[R/W] B,H

11111111 PILR02[R/W] B,H

11111111 PILR03[R/W] B,H

11111111

Port input level

selection register

000EE4H PILR04[R/W] B,H

11111111 PILR05[R/W] B,H

-1111111 - PILR07[R/W] B,H

-----111

000EE8H - PILR09[R/W] B,H

---11--- - -

000EECH - - - -

000EF0H

000EFCH

- - - - Reserved

000F00H

000F1CH

- - - - Reserved

000F20H - PODR01[R/W] B,H

00000000 PODR02[R/W] B,H

00000000 PODR03[R/W] B,H

00000000

Port output drive

000F24H PODR04[R/W] B,H

00000000 PODR05[R/W] B,H

-0000000 - PODR07[R/W] B,H

-----000

000F28H - PODR09[R/W] B,H

---00--- - -

000F2CH - - - -

000F30H

000F3CH

- - - - Reserved

000F40H PORTEN[R/W] B,H,W

------00 - - - P ort input enable

000F44H KEY CDR[R/W] H

00000000 00000000 - - Port key code

000F48H ADERH[R/W] B,H

-------- ---11--- ADERL[R/W] B,H

-1111111 11111111 Analog i nput

enable regist er

000F4CH DAE R[R/W] B,H

-------0 - - - Analog out put

enable regist er

Document Number: 002-04665 Rev *A Page 97 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

000F50H

000FFCH

- - - - Reserved

001000H SA CR[R/W] B,H,W

-------0

PICD[R/W]

B,H,W

----0011 - - Synchronous/asyn

chronous switch

control

001004H

0010BCH

- - - - Reserved

0010C0H - - - CRCCR[R/W] B,H,W

-0000000

CRC arithm etic

operation 0

0010C4H CRCINIT[R/W] B,H,W

11111111 11111111 11111111 11111111

0010C8H CRCIN[ R/W] B,H,W

00000000 00000000 00000000 00000000

0010CCH CRCR[R] B,H,W

11111111 11111111 11111111 11111111

0010D0H - - - CRCCR1[R/W] B,H,W

-0000000

CRC arithm etic

operation 1

0010D4H CRCINIT1[R/W] B,H,W

11111111 11111111 11111111 11111111

0010D8H CRCIN1[ R/W] B,H,W

00000000 00000000 00000000 00000000

0010DCH CRCR1[R] B,H,W

11111111 11111111 11111111 11111111

0010E0H

0010FCH

- - - - Reserved

001100H TCGS[R/W] B,H,W

------00 - - TCGSE[R/W] B,H,W

--000000

Free-run timer

simultaneous

activation

001104H CPCLRB0/CP CLR0[R/W] H,W

11111111 11111111 TCDT 0[R/W] H,W

00000000 00000000 Free-run timer 0

001108H TCCS0[R/W] B,H,W

00000000 01000000 ----0000 --------

00110CH CPCLRB 1 /CPCLR1[ R/W] H,W

11111111 11111111 TCDT1[R/W] H,W

00000000 00000000 Free-run timer 1

001110H TCCS1[R/W] B,H,W

00000000 01000000 ----0000 --------

001114H CPCLRB2/CP CLR2[R/W] H,W

11111111 11111111 TCDT 2[R/W] H,W

00000000 00000000 Free-run timer 2

001118H TCCS2[R/W] B,H,W

00000000 01000000 ----0000 --------

Document Number: 002-04665 Rev *A Page 98 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00111CH CPCLRB 3 /CPCLR3[ R/W] H,W

11111111 11111111 TCDT 3[R/W] H,W

00000000 00000000 Free-run timer 3

001120H TCCS3[R/W] B,H,W

00000000 01000000 ----0000 --------

001124H CPCLRB4/CP CLR4[R/W] H,W

11111111 11111111 TCDT 4[R/W] H,W

00000000 00000000 Free-run timer 4

001128H TCCS4[R/W] B,H,W

00000000 01000000 ----0000 --------

00112CH CPCLRB 5 /CPCLR5[ R/W] H,W

11111111 11111111 TCDT 5[R/W] H,W

00000000 00000000 Free-run timer 5

001130H TCCS5[R/W] B,H,W

00000000 01000000 ----0000 --------

001134H FRS0[R/W] B,H,W

-------- -000-000 -000-000 -000-000

Free-run timer

selection

001138H FRS1[R/W] B,H,W

-------- -------- -000-000 -000-000

00113CH FRS2[R/W] B,H,W

-------- -000-000 -000-000 -000-000

001140H -

001144H FRS4[R/W] B,H,W

-000-000 -000-000 -000-000 -000-000

001148H FRS5[R/W] B,H,W

-----000 -000-000 -000-000 -000-000

00114CH FRS6[R/W] B,H,W

-------- -----000 -000---- --------

001150H -

001154H OCCPB0/OCCP0[ R/W] H,W

00000000 00000000 OCCP B1/OCCP1[ R/W] H,W

00000000 00000000 Output compare

0/1

001158H OCS01[R/W] B,H,W

-110--00 00001100 - OCMOD01[R/W]

B,H,W

------00

00115CH OCCPB2/OCCP2[ R/W] H,W

00000000 00000000 OCCP B3/OCCP3[ R/W] H,W

00000000 00000000 Output compare

2/3

001160H OCS23[R/W] B,H,W

-110--00 00001100 - OCMOD23[R/W]

B,H,W

------00

001164H OCCPB4/OCCP4[ R/W] H,W

00000000 00000000 OCCP B5/OCCP5[ R/W] H,W

00000000 00000000 Output compare

4/5

001168H OCS45[R/W] B,H,W

-110--00 00001100 - OCMOD45[R/W]

B,H,W

------00

Document Number: 002-04665 Rev *A Page 99 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00116CH OCCPB6/OCCP6[ R/W] H,W

00000000 00000000 OCCPB7/OCCP7 [R/W] H,W

00000000 00000000 Output compare

6/7

001170H OCS67[R/W] B,H,W

-110--00 00001100 - OCMOD67[R/W]

B,H,W

------00

001174H OCCPB8/OCCP8[ R/W] H,W

00000000 00000000 OCCP B9/OCCP9[ R/W] H,W

00000000 00000000 Output compare

8/9

001178H OCS89[R/W] B,H,W

-110--00 00001100 - OCMOD89[R/W]

B,H,W

------00

00117CH OCCPB10/OCCP10[ R/W] H,W

00000000 00000000 OCCP B11/OCCP11[R/W] H,W

00000000 00000000 Output compare

10/11

001180H

OCS1011[R/W]

B,H,W

-110--00 00001100 - OCMOD1011

[R/W] B,H,W

------00

001184H IPCP0[R] H,W

00000000 00000000 IPCP1[R] H,W

00000000 00000000 Input capture 0/1

001188H

ICS01[R/W]

B,H,W

------00 00000000 - LSYNS [R /W] B,H,W

------00

00118CH IP CP2[R] H,W

00000000 00000000 IPCP3[R] H,W

00000000 00000000 Input capture 2/3

001190H ICS 23 [R/W] B,H,W

------00 00000000 - -

001194H - - Reserved

001198H - - -

00119CH - - Reserved

0011A0H - - -

0011A4H DTSR[R/W] B,H,W

------10 - - - DTTI selection

0011A8H TMRR0[R/W] H,W

00000000 00000001 TMRR1[ R/W] H,W

00000000 00000001

Waveform

generator

0/1/2

0011ACH TMRR2[R/W] H,W

00000000 00000001 - -

0011B0H DTSCR0[R/W] B,H,W

00000000 DTSCR1[R/W] B,H,W

00000000 DTSCR2[R/W] B,H,W

00000000 -

0011B4H - DTIR0[R/W] B,H, W

000000-- - DTMNS 0[R/W] B,H,W

00---000

0011B8H - SIGCR10[R/W] B,H,W

00000000 - SIGCR20[R/W] B,H,W

000000-1

0011BCH PICS0[R/W] B,H,W

000000-- -------- -------- --------

Document Number: 002-04665 Rev *A Page 100 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0011C0H TMRR3[R/W] H,W

00000000 00000001 TMRR4[ R/W] H,W

00000000 00000001

Waveform

generator

3/4/5

0011C4H TMRR5[R/W] H,W

00000000 00000001 - -

0011C8H DTSCR3[R/W] B,H,W

00000000 DTSCR4[R/W] B,H,W

00000000 DTSCR5[R/W] B,H,W

00000000 -

0011CCH - DTIR1[R/W] B,H,W

000000-- - DTMNS 1[R/W] B,H,W

00---000

0011D0H - SIGCR11[R/W] B,H,W

00000000 - SIGCR21[R/W] B,H,W

-------1

0011D4H -

Document Number: 002-04665 Rev *A Page 101 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

0011D8H - - - -

12-bit A/D

converter

0011DCH ADTS S[R/W] B, H,W

-------0 - - -

0011E0H ADT SE[ R /W] B, H,W

-------- ---00--- -0000000 00000000

0011E4H ADCOMP0/ADCOMPB0[R/W] H,W

00000000 00000000 ADCO MP 1/ADCOMPB1[ R/W] H,W

00000000 00000000

0011E8H ADCOMP2/A DCO MPB2[R/W] H,W

00000000 00000000 ADCO MP 3/ADCOMPB3[ R/W] H,W

00000000 00000000

0011ECH ADCOMP 4/ADCOMPB4[R/W] H,W

00000000 00000000 ADCO MP 5/ADCOMPB5[ R/W] H,W

00000000 00000000

0011F0H ADCOMP 6/ADCOMPB6[R/W] H,W

00000000 00000000 ADCOMP7/ADCOMPB7[R /W] H,W

00000000 00000000

0011F4H ADCOMP 8/ADCOMPB8[R/W] H,W

00000000 00000000 ADCO MP 9/ADCOMPB9[ R/W] H,W

00000000 00000000

0011F8H ADCOMP10/ADCOMPB10[R/W] H,W

00000000 00000000 ADCOMP11/ADCOMPB11[R/W] H,W

00000000 00000000

0011FCH ADCOMP12/ADCOMPB12[R/W] H,W

00000000 00000000 ADCOMP13/ADCOMPB13[R/W] H,W

00000000 00000000

001200H ADCOMP14/ADCOMPB14[R/W] H,W

00000000 00000000 -

001204H - -

001208H - ADCOMP19/ADCOMPB19[R/W] H,W

00000000 00000000

00120CH ADCOMP20/ADCOMPB20[R/W] H,W

00000000 00000000 -

001210H - -

001214H - - - -

001218H - - - -

00121CH - - - -

001220H - - - -

001224H ADT CS0[R/W] B,H,W

00000000 0010-000 ADT CS 1 [R/W] B,H,W

00000000 0010-000

001228H ADT CS2[R/W] B,H,W

00000000 0010-000 ADT CS 3 [R/W] B,H,W

00000000 0010-000

00122CH ADTCS4[R/W] B,H,W

00000000 0010-000 ADT CS 5 [R/W] B,H,W

00000000 0010-000

001230H ADT CS6[R/W] B,H,W

00000000 0010-000 ADT CS 7 [R/W] B,H,W

00000000 0010-000

Document Number: 002-04665 Rev *A Page 102 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001234H ADT CS8[R/W] B,H,W

00000000 0010-000 ADT CS 9 [R/W] B,H,W

00000000 0010-000

12-bit A/D

converter

001238H ADT CS10[R/W] B,H,W

00000000 0010-000 ADT CS 1 1[R/W] B,H,W

00000000 0010-000

00123CH ADTCS12[R/W] B,H,W

00000000 0010-000 ADT CS 1 3[R/W] B,H,W

00000000 0010-000

001240H ADT CS14[R/W] B,H,W

00000000 0010-000 -

001244H - -

001248H - A DT CS19[R/W] B,H,W

00000000 00100000

00124CH ADTCS20[R/W] B,H,W

00000000 00100000 -

001250H - -

001254H - - - -

001258H - - - -

00125CH - - - -

001260H - - - -

001264H ADT CD0[R] B,H,W

10--0000 00000000 ADT CD1 [R] B,H,W

10--0000 00000000

001268H ADT CD2[R] B,H,W

10--0000 00000000 ADT CD3 [R] B,H,W

10--0000 00000000

00126CH ADTCD4 [ R] B, H,W

10--0000 00000000 ADT CD5 [R] B,H,W

10--0000 00000000

001270H ADT CD6[R] B,H,W

10--0000 00000000 ADT CD7 [R] B,H,W

10--0000 00000000

001274H ADT CD8[R] B,H,W

10--0000 00000000 ADT CD9 [R] B,H,W

10--0000 00000000

001278H ADTCD10[R] B,H,W

10--0000 00000000 ADTCD11[R] B,H,W

10--0000 00000000

00127CH ADTCD12[R] B,H,W

10--0000 00000000 ADTCD13[R] B,H,W

10--0000 00000000

001280H ADTCD14[R] B,H,W

10--0000 00000000 -

001284H - -

001288H - ADTCD19[R] B,H,W

10--0000 00000000

00128CH ADTCD20[R] B,H,W

10--0000 00000000 -

001290H - -

001294H - - - -

001298H - - - -

Document Number: 002-04665 Rev *A Page 103 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00129CH - - - -

12-bit A/D

converter

0012A0H - - - -

0012A4H

ADCS0[R/W]

B,H,W

0------- --------

ADCH0[R]

B,H,W

-----000

ADMD0[R/W] B,H,W

----0000

0012A8H

ADCS1[R/W]

B,H,W

0------- --------

ADCH1[R]

B,H,W

-----000

ADMD1[R/W] B,H,W

----0000

0012ACH

ADCS2[R/W]

B,H,W

0------- --------

ADCH2[R]

B,H,W

-----000

ADMD2[R/W] B,H,W

----0000

0012B0H MTRCSR[R/W ] B, H,W

-------0 - - - Motor control

extension function

0012B4H

RTOSEL0[R/W]

B,H,W

--000000

RTOSEL1[R/W]

B,H,W

-------0 - -

0012B8H

0012FCH

- - - - Reserved

001300H - - - -

Reserved

001304H - - - -

001308H - - - -

00130CH - - - -

001310H - - - -

001314H - - - -

001318H - - - -

00131CH - - - -

001320H - - - -

001324H - -

001328H

00132CH

- - - -

001330H - -

001334H

0013FCH

- - - - Reserved

001400H DACR[R/W] B,H,W

-------0 - DADR[R/W]

H,W

------XX XXXXXXXX DAC

001404H

0014FCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 104 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

001500H

SCR0/(IBCR0)

[R/W] B,H,W

0--00000

SMR0

[R/W] B,H,W

000000-0

SSR0

[R/W] B,H,W

0--00011

ESCR0/(IBSR0)

[R/W] B,H,W

00000000 Multi F unct i on

Serial I/F 0

*1: Byte access is

possible only for

access to lower 8

bits.

*2: Reserved

because I2C mode

is not set

immediately after

reset

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

001504H -/(RDR10/(TDR10))[R/W] B,H,W

-------- -------- *3 RDR00/(TDR00)[R/W] B,H,W

-------0 00000000 *1

001508H SACSR0[R/W] B,H,W

0----000 00000000 STMR0[ R ] B,H,W

00000000 00000000

00150CH STMCR0[R/W] B,H,W

00000000 00000000 -/(S FUR0) [R/W] B,H,W

-------- -------- *4

001510H - - -/(SFLR10) [R/W]

B,H,W

-------- *4

-/(SFLR00) [R/W]

B,H,W

-------- *4

001514H - - - -

001518H - - - -

00151CH BGR0 [R/W] H,W

00000000 00000000 -/(ISMK0)[R/W] B,H,W

-------- *2 -/(ISBA0)[R/W] B,H,W

-------- *2

001520H FCR10[R/W] B,H,W

00-00100 FCR00[R/W] B ,H,W

-0000000 F BYT E20 [R/W] B, H,W

00000000 FBYTE10[R/W] B,H,W

00000000

001524H SCR1[R/W] B,H,W

0--00000 SMR1[ R/W] B,H,W

000000-0 SS R1 [R/W] B,H,W

0--00011 ESCR1[R/W] B,H,W

00000000

Multi Function

Serial I/F 1

*1: Byte access is

possible only for

access to lower 8

bits.

*3: Reserved

because CSIO

mode is not set

immediately after

reset

*4: Reserved

because LIN2.1

mode is not set

immediately after

reset

001528H -/(RDR11/(TDR11))[R/W] B,H,W

-------- -------- *3 RDR01/(TDR01)[R/W] B,H,W

-------0 00000000 *1

00152CH SACSR1[R/W] B,H,W

0----000 00000000 STMR1[ R ] B,H,W

00000000 00000000

001530H ST MCR1[ R/W] B,H,W

00000000 00000000 -/(S CSCR1/SFUR1) [R/W] B,H,W

-------- -------- *3 *4

001534H

-/(SCSTR31) [R/W]

B,H,W

-------- *3

-/(SCSTR21) [R/W]

B,H,W

-------- *3

-/(SCSTR11/

SFLR11) [R/W] B,H,W

-------- *3 *4

-/(SCSTR01/

SFLR01) [R/W] B,H,W

-------- *3 *4

001538H - - - -

00153CH - - - TBYTE01[R/W]

B,H,W

00000000

001540H BG R1 [R/W] H,W

00000000 00000000 - -

001544H FCR11[R/W] B,H,W

00-00100 FCR01[R/W] B ,H,W

-0000000 F BYT E21 [R/W] B, H,W

00000000 FBYTE11[R/W] B,H,W

00000000

001548H

001FFCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 105 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

002000H CTRLR0[R/W] B,H,W

-------- 000-0001 STATR0[R/W] B,H,W

-------- 00000000

CAN 0

64msb

002004H ERRCNT 0 [R] B,H,W

00000000 00000000 BTR0[R/W] B,H,W

-0100011 00000001

002008H INT R0[R] B,H,W

00000000 00000000 TESTR0[R/W] B,H,W

-------- X00000--

00200CH BRPER0[R/W] B,H,W

-------- ----0000 -

002010H IF 1CREQ0[R/W] B,H,W

0------- 00000001 IF1CMSK0[R/W] B,H,W

-------- 00000000

002014H IF1MSK20[R/W] B,H,W

11-11111 11111111 IF1MSK10[R/W] B,H,W

11111111 11111111

002018H IF1ARB20[R/W] B,H,W

00000000 00000000 IF1ARB10[R/W] B,H, W

00000000 00000000

00201CH IF1 MCTR0[R/W] B,H,W

00000000 0---0000 -

002020H IF1DTA10[R/W] B,H,W

00000000 00000000 IF1DTA20[R/W] B,H,W

00000000 00000000

002024H IF1DTB10[R/W] B,H,W

00000000 00000000 IF1DTB20[R/W] B,H,W

00000000 00000000

002028H,

00202CH - -

002030H,

002034H Reserved (IF 1 dat a mirror)

002038H,

00203CH - -

002040H IF 2CREQ0[R/W] B,H,W

0------- 00000001 IF2CMSK 0[R/W] B,H,W

-------- 00000000

002044H IF2MSK20[R/W] B,H,W

11-11111 11111111 IF2MSK10[R/W] B,H,W

11111111 11111111

002048H IF2ARB20[R/W] B,H,W

00000000 00000000 IF2ARB10[R/W] B,H, W

00000000 00000000

00204CH IF2 MCTR0[R/W] B,H,W

00000000 0---0000 -

002050H IF2DTA10[R/W] B,H,W

00000000 00000000 IF2DTA20[R/W] B,H,W

00000000 00000000

002054H IF2DTB10[R/W] B,H,W

00000000 00000000 IF2DTB20[R/W] B,H,W

00000000 00000000

002058H,

00205CH - -

002060H,

002064H Reserved (IF 2 dat a mirror)

Document Number: 002-04665 Rev *A Page 106 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

002068H

00207CH

- -

CAN 0

64msb

002080H TRE QR2 0[R] B,H,W

00000000 00000000 TRE Q R10 [R] B,H,W

00000000 00000000

002084H TRE QR4 0[R] B,H,W

00000000 00000000 TRE Q R30 [R] B,H,W

00000000 00000000

002088H - -

00208CH - -

002090H NEWDT20[R] B,H,W

00000000 00000000 NEWDT10[R] B, H,W

00000000 00000000

002094H NEWDT40[R] B,H,W

00000000 00000000 NEWDT30[R] B,H,W

00000000 00000000

002098H - -

00209CH - -

0020A0H INTPND20[R] B,H,W

00000000 00000000 INT PND10[R] B,H,W

00000000 00000000

0020A4H INTPND40[R] B,H,W

00000000 00000000 INT PND30[R] B,H,W

00000000 00000000

0020A8H - -

0020ACH - -

0020B0H MSGVAL 2 0 [R] B,H,W

00000000 00000000 MSGVAL10 [R] B,H,W

00000000 00000000

0020B4H MSGVAL 4 0 [R] B,H,W

00000000 00000000 MSGVAL30 [R] B,H,W

00000000 00000000

0020B8H - -

0020BCH - -

0020C0H

0020FCH

- -

002100H

0022FCH

- - Reserved

002300H DFCTLR[R/W] B,H,W

-0------ -------- - DFST R[R/W] B,H,W

-----001

WorkFlash

002304H - - - -

002308H

FLIFCTLR[R/W]

B,H,W

---0--00 - FLIFFER1[R/W]

B,H,W

--------

FLIFFER2[R/W]

B,H,W

--------

00230CH

002FFCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 107 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

003000H SEE ARX[R] B,H,W

--000000 00000000 DEEARX[R] B,H,W

--000000 00000000 XBS RAM

ECC control

003004H EE CSRX[R/W] B,H,W

----00-0 - EFEARX[R/W] B,H,W

--000000 00000000

003008H - EFECRX[R/W] B,H,W

-------0 00000000 00000000

00300CH TEAR0X[R] B,H,W

000----- -------- --000000 00000000

XBS RAM

diagnosis register

003010H TE AR1X[R] B,H,W

000----- -------- --000000 00000000

003014H TE AR2X[R] B,H,W

000----- -------- --000000 00000000

003018H TAEARX[R/W] B,H,W

--101111 11111111 TASARX[R/W] B,H,W

--000000 00000000

00301CH TFECRX[R/W] B,H,W

----0000 TI CRX[R/W] B,H,W

----0000

TTCRX[R/W]

B,H,W

------00 00001100

003020H TS RCRX[R/W] B,H,W

0------- - - TKCCRX[R/W] B,H,W

00----00

003024H SEEARA[R] B,H,W

--000000 00000000 DEEARA[R] B,H,W

--000000 00000000

Backup RAM

ECC control

003028H EECSRA[R/W] B,H,W

----00-0 - EFEARA[R/W]

B,H,W

--000000 00000000

00302CH - EFECRA[R /W] B,H,W

-------0 00000000 00000000

003030H TE AR0A[R] B,H,W

000----- -------- -----000 00000000

Backup RAM

diagnosis register

003034H TE AR1A[R] B,H,W

000----- -------- -----000 00000000

003038H TE AR2A[R] B,H,W

000----- -------- -----000 00000000

00303CH TAEARA[R/W] B,H,W

-----111 11111111 TASARA[R/W] B,H,W

-----000 00000000

003040H TFECRA[R/W] B,H,W

----0000 TI CRA[R/W] B,H,W

----0000

TTCRA[R/W]

B,H,W

------00 00001100

003044H TS RCRA[R/W] B,H,W

0------- - - TKCCRA [R/W] B,H,W

00----00

003048H

0030FCH

- - - - Reserved

Document Number: 002-04665 Rev *A Page 108 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

003100H BUS DIGSR0[R/W] H,W

00000000 0-----00 BUSDI GSR1[R/W] H,W

00000000 0-----00

Bus diagnosis

003104H BUS DIGSR2[R/W] H,W

00000000 0-----00 BUSTSTR0[ R/W] H,W

00--0000 00000000

003108H BUSADR0[R] W

00000000 00000000 00000000 00000000

00310CH BUSADR1[R] W

00000000 00000000 00000000 00000000

003110H BUSADR2[R] W

00000000 00000000 00000000 00000000

003114H - B USDIGSR3[ R/W] H,W

00000000 0-----00

003118H BUS DIGSR4[R/W] H,W

00000000 0-----00 BUSTSTR1[ R/W] H,W

00--0000 00000000

00311CH -

003120H BUSADR3[R] W

00000000 00000000 00000000 00000000

003124H BUSADR4[R] W

00000000 00000000 00000000 00000000

003128H

003FFCH

- - - - Reserved

004000H

005FFCH

Backup RAM Backup RAM area

006000H

00CFFCH

- - - - Reserved

00D000H CIF0[R] W

00000100 11111111 01011011 11111111 FlexRay

CIF *5

00D004H CIF1[R/W] W

00000000 -------0 -0000000 --------

00D008H

00D00CH

- - - - Reserved

00D010H -

FlexRay

GIF *5

00D014H -

00D018H - - - -

00D01CH LCK[R/W] W

-------- -------- -------- 00000000

Document Number: 002-04665 Rev *A Page 109 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D020H EIR[R/W] W

-----000 -----000 ----0000 00000000

FlexRay

INT *5

00D024H SIR[R/W] W

------00 ------00 00000000 00000000

00D028H EILS[R/W] W

-----000 -----000 ----0000 00000000

00D02CH SILS[R/ W] W

------11 ------11 11111111 11111111

00D030H EIES[R/W] W

-----000 -----000 ----0000 00000000

00D034H EIER[R/W] W

-----000 -----000 ----0000 00000000

00D038H SIES[R/W] W

------00 ------00 00000000 00000000

00D03CH SIER[R/W] W

------00 ------00 00000000 00000000

00D040H ILE[R/W] W

-------- -------- -------- ------00

00D044H T0C[R/W] W

--000000 00000000 -0000000 ------00

00D048H T1C[R/W] W

--000000 00000010 -------- ------00

00D04CH STPW1 [ R /W] W

--000000 00000000 --000000 -0000000

00D050H STPW2[R] W

-----000 00000000 -----000 00000000

00D054H

00D07CH

- - - - Reserved

00D080H SUCC1[R/W] W

----1100 01000000 00010-00 1---0000

FlexRay

SUC *5

00D084H SUCC2[R/W] W

----0001 ---00000 00000101 00000100

00D088H SUCC3[R/W] W

-------- -------- -------- 00010001

00D08CH NEMC[R/W] W

-------- -------- -------- ----0000 FlexRay

NEM *5

00D090H PRTC1[R/W] W

000010-0 01001100 0000-110 00110011 FlexRay

PRT *5

00D094H PRTC2[R/W] W

--001111 00101101 --001010 --001110

00D098H MHDC[R/W] W

---00000 00000000 -------- -0000000 FlexRay

MHD *5

Document Number: 002-04665 Rev *A Page 110 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D09CH - Reserved

00D0A0H GTUC1[R/W] W

-------- ----0000 00000010 10000000

FlexRay

GTU *5

00D0A4H GTUC2[R/W] W

-------- ----0010 --000000 00001010

00D0A8H GTUC3[R/W] W

-0000010 -0000010 00000000 00000000

00D0ACH GTUC4[R/W] W

--000000 00001000 --000000 00000111

00D0B0H GTUC5[R/W] W

00001110 ---00000 00000000 00000000

00D0B4H GTUC6[R/W] W

-----000 00000010 -----000 00000000

00D0B8H GTUC7[R/W] W

------00 00000010 ------00 000001 00

00D0BCH GTUC8[R/W] W

---00000 00000000 -------- --000010

00D0C0H GTUC9[R/W] W

-------- ------00 ---00001 --000001

00D0C4H GTUC10[R/W] W

-----000 00000010 --000000 00000101

00D0C8H GTUC11[R/W] W

-----000 -----000 ------00 ------00

00D0CCH

00D0FCH

- Reserved

00D100H CCSV[R] W

--000000 00010000 -100--00 00000000 FlexRay

SUC *5

00D104H CCEV[R] W

-------- -------- ---00000 00--0000

00D108H

00D10CH - Reserved

Document Number: 002-04665 Rev *A Page 111 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D110H SCV[R] W

-----000 00000000 -----000 00000000

FlexRay

GTU *5

00D114H MTCCV[R] W

-------- --000000 --000000 00000000

00D118H RCV[R] W

-------- -------- ----0000 00000000

00D11CH OCV[R] W

-------- -----000 00000000 00000000

00D120H SFS[R] W

-------- ----0000 00000000 00000000

00D124H SWNIT [R] W

-------- -------- ----0000 00000000

00D128H ACS[R/ W] W

-------- -------- ---00000 ---00000

00D12CH -

00D130H ESID1[R] W

-------- -------- 00----00 00000000

00D134H ESID2[R] W

-------- -------- 00----00 00000000

00D138H ESID3[R] W

-------- -------- 00----00 00000000

00D13CH ESID4[R] W

-------- -------- 00----00 00000000

Document Number: 002-04665 Rev *A Page 112 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D140H ESID5[R] W

-------- -------- 00----00 00000000

FlexRay

GTU *5

00D144H ESID6[R] W

-------- -------- 00----00 00000000

00D148H ESID7[R] W

-------- -------- 00----00 00000000

00D14CH ESID8[R] W

-------- -------- 00----00 00000000

00D150H ESID9[R] W

-------- -------- 00----00 00000000

00D154H ESID10[R] W

-------- -------- 00----00 00000000

00D158H ESID11[R] W

-------- -------- 00----00 00000000

00D15CH ESID12[R] W

-------- -------- 00----00 00000000

00D160H ESID13[R] W

-------- -------- 00----00 00000000

00D164H ESID14[R] W

-------- -------- 00----00 00000000

00D168H ESID15[R] W

-------- -------- 00----00 00000000

00D16CH -

00D170H OSID1[R ] W

-------- -------- 00----00 00000000

00D174H OSID2[R ] W

-------- -------- 00----00 00000000

00D178H OSID3[R ] W

-------- -------- 00----00 00000000

00D17CH OSID4[R ] W

-------- -------- 00----00 00000000

00D180H OSID5[R ] W

-------- -------- 00----00 00000000

00D184H OSID6[R ] W

-------- -------- 00----00 00000000

00D188H OSID7[R ] W

-------- -------- 00----00 00000000

00D18CH OSID8[R] W

-------- -------- 00----00 00000000

00D190H OSID9[R ] W

-------- -------- 00----00 00000000

00D194H OSID10[R] W

-------- -------- 00----00 00000000

Document Number: 002-04665 Rev *A Page 113 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D198H OSID11[R] W

-------- -------- 00----00 00000000

FlexRay

GTU *5

00D19CH OSID12[R ] W

-------- -------- 00----00 00000000

00D1A0H OSID13[R ] W

-------- -------- 00----00 00000000

00D1A4H OSID14[R ] W

-------- -------- 00----00 00000000

00D1A8H OSID15[R ] W

-------- -------- 00----00 00000000

00D1ACH - Reserved

00D1B0H NMV1[R] W

00000000 00000000 00000000 00000000

FlexRay

NEM *5

00D1B4H NMV2[R] W

00000000 00000000 00000000 00000000

00D1B8H NMV3[R] W

00000000 00000000 00000000 00000000

00D1BCH

00D2FCH

- Reserved

Document Number: 002-04665 Rev *A Page 114 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D300H MRC[R/W] W

-----001 10000000 00000000 00000000

FlexRay

MHD *5

00D304H FRF[R/W] W

-------1 10000000 ---00000 00000000

00D308H FRFM[R/W] W

-------- -------- ---00000 000000--

00D30CH FCL[R/W] W

-------- -------- -------- 10000000

00D310H MHDS[R/W] W

-0000000 -0000000 -0000000 00000000

00D314H LDTS[R] W

-----000 00000000 -----000 00000000

00D318H FSR[R] W

-------- -------- 00000000 -----000

00D31CH MHDF[R/W] W

-------- -------- -------0 00000000

00D320H TXRQ1[R] W

00000000 00000000 00000000 00000000

00D324H TXRQ2[R] W

00000000 00000000 00000000 00000000

00D328H TXRQ3[R] W

00000000 00000000 00000000 00000000

00D32CH TXRQ4[R] W

00000000 00000000 00000000 00000000

00D330H NDAT1[R] W

00000000 00000000 00000000 00000000

00D334H NDAT2[R] W

00000000 00000000 00000000 00000000

00D338H NDAT3[R] W

00000000 00000000 00000000 00000000

00D33CH NDAT4[R] W

00000000 00000000 00000000 00000000

00D340H MBSC1[R] W

00000000 00000000 00000000 00000000

00D344H MBSC2[R] W

00000000 00000000 00000000 00000000

00D348H MBSC3[R] W

00000000 00000000 00000000 00000000

00D34CH MBSC4[R] W

00000000 00000000 00000000 00000000

00D350H

00D3ECH

- Reserved

Document Number: 002-04665 Rev *A Page 115 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D3F0H CREL[R] W

00010000 00111001 00000010 00000110 FlexRay

GIF *5

00D3F4H ENDN[R] W

10000111 01100101 01000011 00100001

00D3F8H

00D3FCH

- Reserved

00D400H

00D4FCH

WRDSn[1-64][R/W] W

00000000 00000000 00000000 00000000

FlexRay

IBF *5

00D500H WRHS1[R/W] W

--000000 -0000000 -----000 00000000

00D504H WRHS2[R/W] W

-------- -0000000 -----000 00000000

00D508H WRHS3[R/W] W

-------- -------- -----000 00000000

00D50CH -

00D510H IBCM[R/W] W

-------- ------00 -------- -----000

00D514H IBCR[R/W] W

0------- -0000000 0------- -0000000

00D518H

00D5FCH

- Reserved

00D600H

00D6FCH

RDDSn[1-64][R] W

00000000 00000000 00000000 00000000

FlexRay

OBF *5

00D700H RDHS1[R] W

--000000 -0000000 -----000 00000000

00D704H RDHS2[R] W

-0000000 -0000000 -----000 0000 0000

00D708H RDHS3[R] W

--000000 --000000 -----000 00000000

00D70CH MBS[R] W

--000000 --000000 00-00000 00000000

00D710H OBCM[R/W] W

-------- ------00 -------- ------00

00D714H OBCR[R/W] W

-------- -0000000 0-----00 -0000000

00D718H

00D7FCH

- Reserved

Document Number: 002-04665 Rev *A Page 116 of 175

MB91580M/S Series

Address Address offset value/ Reg i ster name Block

+0 +1 +2 +3

00D800H

00EFFCH

- Reserved

00F000H

00FEFCH

- Reserved [S]

00FF00H DSUCR[R/W ] B, H,W

-------- -------0 - - OCDU [S]

00FF04H

00FF0CH

- - - - Reserved [S]

00FF10H PCSR[R/W] B, H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX OCDU [S]

00FF14H PSSR[R /W] B,H ,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

00FF18H

00FFF4H

- - - - Reserved [S]

00FFF8H EDIR1[R] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXXXXXX OCDU [S]

00FFFCH EDIR0[R] B,H,W

XXXXXXX X XXXX XX XX XXXXXX XX XXXX XXXX

[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and

writing to these registers in the user mode.

*5: For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ has corresponding

functions.

The following registers are reserved registers for models without the FlexRay function.

000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H

Document Number: 002-04665 Rev *A Page 117 of 175

MB91580M/S Series

10. I nterrupt Vector Ta ble

 MB91F583AM/F584AM/F585AM

Interrupt factor

Interrupt number

Inter

rupt

level

Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

Reset

3FCH

000FFFFCH

Sy stem reserved

3F8H

000FFFF8H

System reserved

3F4H

000FFFF4H

Sy stem reserved

3F0H

000FFFF0H

Sy stem reserved

3ECH

000FFFECH

FPU exception

3E8H

000FFFE8H

Instruction acc ess protect i on violation

exception

6 06 - 3E4H 000FFFE4H - -

Data access protection violation exception

3E0H

000FFFE0H

Data access error interrupts

3DCH

000FFFDCH

INTE instruction

3D8H

000FFFD8H

Instruction break

3D4H

000FFFD4H

Sy stem reserved

3D0H

000FFFD0H

Sy stem reserved

3CCH

000FFFCCH

Sy stem reserved

3C8H

000FFFC8H

Exception of invalid i nst ructi on

3C4H

000FFFC4H

NMI request

Error generation at internal bus diagnosis

RAM double-bit error

Backup RAM double-bit error

15 0F 15(FH

)

Fixed 3C0H 000FFFC0H - 

External interrupt 0-7 16 10

ICR0

3BCH 000FFFBCH 0 -

Reload timer 0 / 1 17 11

ICR0

3B8H 000FFFB8H 1 

Reload timer 2 / 3 18 12

ICR0

3B4H 000FFFB4H 2 

Multifunction serial interface ch.0

(reception completed)/

Multifunction serial interface ch.0

(status)

19 13 ICR0

3 3B0H 000FFFB0H 3*2 

Multifunction serial interface ch.0

(transmission completed)

20 14

ICR0

3ACH 000FFFACH 4 -

Multifunction serial interface ch.1

(reception completed)/

Multifunction serial interface ch.1

(status)

21 15 ICR0

5 3A8H 000FFFA8H 5*2 

Multifunction serial interface ch.1

(transmission completed)

22 16

ICR0

3A4H 000FFFA4H 6 -

Multifunction serial interface ch.2

(reception completed)/

Multifunction serial interface ch.2

(status)

23 17 ICR0

7 3A0H 000FFFA0H 7*2 

Multifunction serial interface ch.2

(transmission completed)

24 18

ICR0

39CH 000FFF9CH 8 -

Multifunction serial interface ch.3

(reception completed)/

Multifunction serial interface ch.3

(status)

25 19 ICR0

9 398H 000FFF98H 9*2 

Multifunction serial interface ch.3

(transmission completed)

26 1A

ICR1

394H 000FFF94H 10 -

*4 27 1B

ICR1

390H 000FFF90H - -

*4 28 1C

ICR1

38CH 000FFF8CH - -

Document Number: 002-04665 Rev *A Page 118 of 175

MB91580M/S Series

Interrupt factor

Interrupt number

Inter

rupt

level

Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

CAN 0 29 1D

ICR1

388H 000FFF88H - -

CAN 1 30 1E

ICR1

384H 000FFF84H - -

FlexRay 0 *5 31 1F

ICR1

380H 000FFF80H - -

FlexRay 1 *5 32 20

ICR1

37CH 000FFF7CH - -

FlexRay timer 0 *5 33 21

ICR1

378H 000FFF78H - -

FlexRay timer 1 *5 34 22

ICR1

374H 000FFF74H - -

RAM diagnosis completed

RAM initialization completed

Error generation at RAM diagnosis

Backup RAM diagnosis completed

Backup RAM initializati on com pleted

Error generation at Backup RAM diagnosis

35 23 ICR1

9 370H 000FFF70H - 

Main timer/PLL timer/

PLL gear for FlexRay*5/

PLL alarm for FlexRay

36 24 ICR2

0 36CH 000FFF6CH 20*3 

Clock calibration unit

(CR oscillati on)

37 25

ICR2

368H 000FFF68H - -

U/D counter 0 / 1 38 26

ICR2

364H 000FFF64H 22 

Free-run timer 0 (0 detection) /

(compare clear)

39 27

ICR2

360H 000FFF60H 23 

Free-run timer 1 (0 detection) /

(compare clear)

40 28

ICR2

35CH 000FFF5CH 24 

Free-run timer 2 (0 detection) /

(compare clear)

PPG 0 / 1 / 2 / 3

41 29 ICR2

5 358H 000FFF58H 25 

Free-run timer 3 (0 detection) /

(compare clear)

42 2A

ICR2

354H 000FFF54H 26 

Free-run timer 4 (0 detection) /

(compare clear)

43 2B

ICR2

350H 000FFF50H 27 

Free-run timer 5 (0 detection) /

(compare clear)

PPG 4 / 5

44 2C ICR2

8 34CH 000FFF4CH 28 

ICU 0 (fetching) / ICU 1 (fetching) 45 2D

ICR2

348H 000FFF48H 29 

ICU 2 (fetching) / ICU 3 (fetching) 46 2E

ICR3

344H 000FFF44H 30 

*4 47 2F

ICR3

340H 000FFF40H - -

*4 48 30

ICR3

33CH 000FFF3CH - -

OCU 0 (match) / O CU 1 (matc h) 49 31

ICR3

338H 000FFF38H 33 

OCU 2 (match) / O CU 3 (matc h) 50 32

ICR3

334H 000FFF34H 34 

OCU 4 (match) / O CU 5 (matc h) 51 33

ICR3

330H 000FFF30H 35 

OCU 6 (match) / O CU 7 (matc h) 52 34

ICR3

32CH 000FFF2CH 36 

OCU 8 (match) / O CU 9 (matc h) 53 35

ICR3

328H 000FFF28H 37 

OCU 10 (match) / OCU 11 (match) 54 36

ICR3

324H 000FFF24H 38 

Document Number: 002-04665 Rev *A Page 119 of 175

MB91580M/S Series

Interrupt factor

Interrupt number

Inter

rupt

level

Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

WG dead timer underflow 0 / 1 / 2

WG dead timer reload 0 / 1 / 2

WG DTTI 0

55 37 ICR3

9 320H 000FFF20H 39 

WG dead timer underflow 3 / 4 / 5

WG dead timer reload 3 / 4 / 5

WG DTTI 1

56 38 ICR4

0 31CH 000FFF1CH 40 

AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 57 39

ICR4

318H 000FFF18H 41 

AD converter 8 / 9 / 10 / 11 / 12 / 13 / 14 58 3A

ICR4

314H 000FFF14H 42 

AD converter 16 / 17 / 18 / 19 / 20 / 21 / 22

/ 23

59 3B

ICR4

310H 000FFF10H 43 

Base timer 0 IRQ 0/

base timer 0 IRQ 1

60 3C

ICR4

30CH 000FFF0CH 44 

Base timer 1 IRQ 0/

base timer 1 IRQ 1

61 3D

ICR4

308H 000FFF08H 45 

DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 62 3E

ICR4

304H 000FFF04H - 

Delay interrupt 63 3F

ICR4

300H 000FFF00H - -

Sy stem reserved

2FCH

000FFEFCH

Sy stem reserved

2F8H

000FFEF8H

Used with the INT instruction.

255

2F4

000H

000FFEF4

000FFC00H

- -

*1 :Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN

(resource nu mber) is as sig ned .

*2 :The multi-function serial interface status does not support DMA transfer caused by I2C reception.

*3 :"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.

*4 :For MB91F583AM/F584AM/F585AM, the interrupt vectors are unused.

*5 :For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ have corresponding

functions.

Document Number: 002-04665 Rev *A Page 120 of 175

MB91580M/S Series

 MB91F583AS/F584AS/F585AS

Interrupt factor

Interrupt number

Inter

rupt

level Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

Reset

3FCH

000FFFFCH

System res erv ed

3F8H

000FFFF8H

Sy stem reserved

3F4H

000FFFF4H

Sy stem reserved

3F0H

000FFFF0H

Sy stem reserved

3ECH

000FFFECH

FPU exception

3E8H

000FFFE8H

Instruction acc ess protect i on violation

exception

6 06 - 3E4H 000FFFE4H - -

Data access protection violation exception

3E0H

000FFFE0H

Data access error interrupts

3DCH

000FFFDCH

INTE instruction

3D8H

000FFFD8H

Instruction break

3D4H

000FFFD4H

Sy stem reserved

3D0H

000FFFD0H

Sy stem reserved

3CCH

000FFFCCH

Sy stem reserved

3C8H

000FFFC8H

Exception of invalid i nst ructi on

3C4H

000FFFC4H

NMI request

Error generation at internal bus diagnosis

RAM double-bit error

Backup RAM double-bit error

15 0F 15(FH

)

Fixed 3C0H 000FFFC0H - 

External interrupt 0-6 16 10 ICR0

3BCH 000FFFBCH 0 -

Reload timer 0 / 1 17 11 ICR0

3B8H 000FFFB8H 1 

Reload timer 2 / 3 18 12 ICR0

3B4H 000FFFB4H 2 

Multifunction serial interface ch.0 (reception

completed)/

Multifunction serial interface ch.0

(status)

19 13 ICR0

3 3B0H 000FFFB0H 3*2 

Multifunction serial interface ch.0

(transmission completed)

20 14 ICR0

3ACH 000FFFACH 4 -

Multifunction serial interface ch.1 (reception

completed)/

Multifunction serial interface ch.1

(status)

21 15 ICR0

5 3A8H 000FFFA8H 5*2 

Multifunction serial interface ch.1

(transmission completed)

22 16 ICR0

3A4H 000FFFA4H 6 -

*4 23 17 ICR0

3A0H 000FFFA0H - -

*4 24 18 ICR0

39CH 000FFF9CH - -

*4 25 19 ICR0

398H 000FFF98H - -

Document Number: 002-04665 Rev *A Page 121 of 175

MB91580M/S Series

Interrupt factor

Interrupt number

Inter

rupt

level Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

*4 26 1A ICR1

394H 000FFF94H - -

*4 27 1B ICR1

390H 000FFF90H - -

*4 28 1C ICR1

38CH 000FFF8CH - -

CAN 0 29 1D ICR1

388H 000FFF88H - -

*4 30 1E ICR1

384H 000FFF84H - -

FlexRay 0 *5 31 1F ICR1

380H 000FFF80H - -

FlexRay 1 *5 32 20 ICR1

37CH 000FFF7CH - -

FlexRay timer 0 *5 33 21 ICR1

378H 000FFF78H - -

FlexRay timer 1 *5 34 22 ICR1

374H 000FFF74H - -

RAM diagnosis completed

RAM initialization completed

Error generation at RAM diagnosis

Backup RAM diagnosis completed

Backup RAM initializati on com pleted

Error generation at Backup RAM diagnosis

35 23 ICR1

9 370H 000FFF70H - 

Main timer/PLL timer/

PLL gear for FlexRay*5/

PLL alarm for FlexRay

36 24 ICR2

0 36CH 000FFF6CH 20*3 

Clock calibrati on unit

(CR oscillati on )

37 25 ICR2

368H 000FFF68H - -

U/D counter 0 / 1 38 26 ICR2

364H 000FFF64H 22 

Free-run timer 0 (0 detection) /

(compare clear)

39 27 ICR2

360H 000FFF60H 23 

Free-run timer 1 (0 detection) /

(compare clear)

40 28 ICR2

35CH 000FFF5CH 24 

Free-run timer 2 (0 detection) /

(compare clear)

PPG 0 / 1 / 2 / 3

41 29 ICR2

5 358H 000FFF58H 25 

Free-run timer 3 (0 detection) /

(compare clear)

42 2A ICR2

354H 000FFF54H 26 

Free-run timer 4 (0 detection) /

(compare clear)

43 2B ICR2

350H 000FFF50H 27 

Free-run timer 5 (0 detection) /

(compare clear)

PPG 4 / 5

44 2C ICR2

8 34CH 000FFF4CH 28 

Document Number: 002-04665 Rev *A Page 122 of 175

MB91580M/S Series

Interrupt factor

Interrupt number

Inter

rupt

level Offset TBR default

address RN*1

Interrupt

request

batch read

target

Decimal Hexa

decimal

ICU 0 (fetching) / ICU 1 (fetching) 45 2D ICR2

348H 000FFF48H 29 

ICU 2 (fetching) / ICU 3 (fetching) 46 2E ICR3

344H 000FFF44H 30 

*4 47 2F ICR3

340H 000FFF40H - -

*4 48 30 ICR3

33CH 000FFF3CH - -

OCU 0 (match) / O CU 1 (matc h) 49 31 ICR3

338H 000FFF38H 33 

OCU 2 (match) / O CU 3 (matc h) 50 32 ICR3

334H 000FFF34H 34 

OCU 4 (match) / O CU 5 (matc h) 51 33 ICR3

330H 000FFF30H 35 

OCU 6 (match) / OC U 7 (mat ch) 52 34 ICR3

32CH 000FFF2CH 36 

OCU 8 (match) / O CU 9 (matc h) 53 35 ICR3

328H 000FFF28H 37 

OCU 10 (match) / OCU 11 (match) 54 36 ICR3

324H 000FFF24H 38 

WG dead timer underflow 0 / 1 / 2

WG dead timer reload 0 / 1 / 2

WG DTTI 0

55 37 ICR3

9 320H 000FFF20H 39 

WG dead timer underflow 3 / 4 / 5

WG dead timer reload 3 / 4 / 5

WG DTTI 1

56 38 ICR4

0 31CH 000FFF1CH 40 

AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 57 39 ICR4

318H 000FFF18H 41 

AD converter 8 / 9 / 10 / 11 / 12 / 13 / 14 58 3A ICR4

314H 000FFF14H 42 

AD converter 19 / 20 59 3B ICR4

310H 000FFF10H 43 

Base timer 0 IRQ 0/

base timer 0 IRQ 1

60 3C ICR4

30CH 000FFF0CH 44 

Base timer 1 IRQ 0/

base timer 1 IRQ 1

61 3D ICR4

308H 000FFF08H 45 

DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 62 3E ICR4

304H 000FFF04H - 

Delay interrupt 63 3F ICR4

300H 000FFF00H - -

Sy stem reserved

2FCH

000FFEFCH

Sy stem reserved

2F8H

000FFEF8H

Used with the INT instruction. 66

255

- 2F4H

000H

000FFEF4H

000FFC00H

- -

Document Number: 002-04665 Rev *A Page 123 of 175

MB91580M/S Series

*1 :Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN

(resource nu mber) is as sig ned .

*2 :The multi-function serial interface status does not support DMA transfer caused by I2C reception.

*3 :"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.

*4 :For MB91F583AS/F584AS/F585AS, the inter r upt ve ctors are unused.

*5 :For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ have correspond ing fun ctio ns

Document Number: 002-04665 Rev *A Page 124 of 175

MB91580M/S Series

11. Electrical Characteristics

11.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage

*1, *2

VCC VSS-0.3 VSS+6.0 V

Analog power supply voltage*1 ,*2 AVCC VSS-0.3 VSS+6.0 V Avcc ≤ Vcc

Analog referenc e voltage*1 AVRH VSS-0.3 VSS+6.0 V AVRH ≤ AVCC

Input volt age*1 VI VSS-0.3 VCC+0.3 V

Analog pin input voltage

VIA VSS-0.3 VCC+0.3 V

Output voltage

VO VSS-0.3 VCC+0.3 V

Maximum clamp current ICLAMP - 4 mA *9

Total maximum clamp current Σ|ICLAMP | - 20 mA *9

"L" level maximum output current*3

IOL1 - 7 mA When setting to 2mA*6

IOL2 - 14 mA When setting to 4mA

IOL3 - 17.5 mA When setting to 5mA *8

"L" level average output current*4

IOLAV1 - 2 mA When setting to 2mA

IOLAV2 - 4 mA When setting to 4mA

IOLAV3 - 5 mA When setting to 5mA

"L" level total output current

ΣIOL - 50 mA *6

"H" level maximum output current*3

IOH1 - -7 mA When setting to 2mA *6

IOH2 - -14 mA When setting to 4mA

IOH3 - -17.5 mA When setting to 5mA *8

"H" level average output current*4

IOHAV1 - -2 mA When setting to 2mA

IOHAV2 - -4 mA When setting to 4mA

IOHAV3 - -5 mA When setting to 5mA

"H" level total output current

ΣIOH - -50 mA *6

Power consumption PD - 690 mW

Operating tem perature TA -40 +125 °C *10, *11

Storage temperature Tstg -55 +150 °C

*1: These p arameters are based on the condit ion that VSS=AVSS =0.0V.

*2: Caution must be taken that AVCC does not exceed VCC.

*3: The maximum output current is defined as the value of the peak current flowing through any one of the

corresponding pins.

*4: The average output current is defined as the value of the average current flowing through any one of the

corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.

*5: The total output current is defined as the maxi m um current value flowing through all of corresponding pins.

*6: Corresponding pins: General-purpose ports

*7: Corresponding pins: General-purpose ports of P021 to P023, P025 to P027

*8: Corresponding pins: General-purpose ports other than those of P021 to P023, P025 to P027

Document Number: 002-04665 Rev *A Page 125 of 175

MB91580M/S Series

*9: • Corresponding pins: General-purpose ports

• Use the devices within recommended operating conditions.

• Use the devices with direct voltage (current).

• The + B signal should always be applied by connecting a limiting resistor between the + B signal and the

microcontroller.

• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not

exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.

• Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the + B

input potential can increase the potential at the Vcc pin via a protective diode, possibly affecting other devices.

• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied

through the pin, the microcontroller may operate incompletely.

• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset

may not function in the power supply voltage.

• Do not leave + B input pins open.

Sample recommended circuit

MB91580M/S series

+B input (12 to 16V)

Protective diode Limiting resistor

current

*10: To use this product at TA=125°C, equip this on a multilayer board wi th four or more layers.

To equip this on a single-layer board, change the operating conditions (operating frequency, power supply voltage,

etc) to use this at the power consumption PD=415mW or lower, or use this at TA=105°C or lower.

*11: When it is used exceeding TA=125°C, contact your sales representative.

WARNING

Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage,

current or temperature) in excess of absolute maximum ratings. Do not exc eed any of these ratings.

Document Number: 002-04665 Rev *A Page 126 of 175

MB91580M/S Series

11.2 Recommended Operating Conditions (VSS= AVSS=0.0V)

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage

VCC 4.5 5.5 V Recommended operation guarantee range

AVCC 4.5 5.5 V

VCC 3.7 5.5 V Operation guarantee range

AVCC 3.7 5.5 V

Smoothi ng capacit or*1 CS 4.7

(tolerance within ± 50%) µF

Use a ceramic capacitor or a capacitor that has

the similar frequenc y characterist ic s.

Use a capacitor with a capacitance greater than

CS as the smoothing capacitor on the VCC pin.

Operating

temperature TA -40 +125 °C *2

*1: For connection of smoothing capacitor CS, see the figure below.

*2: When it is used exceeding TA=125°C, contact your sales representative.

C Pin Connection Diagram

WARNING

The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device. All of the device's electrical characteristics are warranted when the device is operated under these conditions.

Any use of semiconductor devices will be under their recommended operating condition. Operation under any

conditions other than these conditions may adversely affect reliability of device and could result in device failure. No

warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If

you are considering application under any conditions other than listed herein, please contact sales representatives

beforehand.

Document Number: 002-04665 Rev *A Page 127 of 175

MB91580M/S Series

11.3 DC Characteristics (TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Typ Max

"H" level input

voltage

VIH1

P000 to P007

P010 to P017,

P020, P024,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

When CMOS

schmitt input

level is selected 0.7 × VCC - VCC+0.3 V

VIH2

P000 to P007

P010 to P017,

P020 to P027,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

When

Automotive

input level is

selected

0.8 × VCC - VCC+0.3 V

VIH3 P021 to P023,

P025 to P027

When FlexRay

input level is

selected 0.7 × VCC - VCC+0.3 V

VIH4 RSTX, NMIX - 0.7 × VCC - VCC+0.3 V

VIH5 MD0, MD 1 - 0.7 × VCC - VCC+0.3 V

VIH6 DEBUGIF - 2.0 - VCC+0.3 V

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 128 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min

Typ

Max

"L" level input

voltage

VIL1

P000 to P007

P010 to P017,

P020, P024,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

When CMOS

schmitt input

level is selected Vss-0.3 - 0.3 × VCC V

VIL2

P000 to P007

P010 to P017,

P020 to P027,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

When

Automotive

input level is

selected

Vss-0.3 - 0.5 × VCC V

VIL3 P021 to P023,

P025 to P027

When FlexRay

input level is

selected Vss-0.3 - 0.3 × VCC V

VIL4 RSTX, NMIX - Vss-0.3 - 0.3 × VCC V

VIL5 MD0, MD 1 - Vss-0.3 - 0.3 × VCC V

VIL6 DEBUGIF - Vss-0.3 - 0.8 V

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 129 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%,VSS= AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min

Typ

Max

"H" level output

voltage

VOH1

P000 to P007

P010 to P017,

P020 to P027,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

Vcc=4.5V

IOH=-2.0mA Vcc-0.5 - Vcc V

VOH2 P021 to P023,

P025 to P027 Vcc=4.5V

IOH=-4.0mA Vcc-0.5 - Vcc V When

FlexRay is

selected

VOH3

P000 to P007

P010 to P017,

P020, P024,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

Vcc=4.5V

IOH=-5.0mA Vcc-0.5 - Vcc V

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 130 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min

Typ

Max

"L" level output

voltage

VOL1

P000 to P007

P010 to P017,

P020 to P027,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

Vcc=4.5V

IOL=2.0mA 0 - 0.4 V

VOL2 P021 to P023,

P025 to P027 Vcc=4.5V

IOL=4.0mA 0 - 0.4 V When FlexRay is

selected

VOL3

P000 to P007

P010 to P017,

P020, P024,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

Vcc=4.5V

IOL=5.0mA 0 - 0.4 V

VOL4

P040, P041,

P063*, P064*,

P080*, P081*,

P083*,P084*

Vcc=4.5V

IOL=3.0mA 0 - 0.4 V I2C shared pin

(when I2C is

selected)

VOL5 DEBUGIF Vcc=2.7V

IOL=25.0mA 0 - 0.25 V

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 131 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min

Typ

Max

Input Leak

Current IIL All input pins Vcc= AVCC=5.5V

VSS < VI < VCC -5 - +5 µA

Pull-up

resistance

RUP1 RSTX, NMIX - 25 - 100 kΩ

RUP2

P000 to P007*,

P010 to P017,

P020 to P027,

P030 to P037,

P040 to P047,

P050 to P056,

P060 to P066*,

P070 to P072,

P080 to P087*,

P090 to P092*,

P093, P094,

P095 to P097*,

P100 to P102*

When pull-up

resistanc e is

selected 25 - 100 kΩ

Input Capacitor CIN

Other thanVCC,

VSS, AVCC,

AVSS,

- - 5 15 pF

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 132 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min

Typ

Max

Power supply

current ICC VCC5

Normal

operations

FCP=128MHz,

FCPM=128MHz,

FCPP=32MHz

- 80 110 mA FlexRay =ON

- 73 103 mA FlexRay =OFF

Normal

operations

FCP=128MHz,

FCPM=32MHz,

FCPP=32MHz

- 77 107 mA FlexRay =ON

- 70 100 mA FlexRay =OFF

Normal

operations

FCP=80MHz,

FCPM=80MHz,

FCPP=40MHz

- 62 89 mA FlexRay =ON

- 57 85 mA FlexRay =OFF

Normal

operations

FCP=80MHz,

FCPM=40MHz,

FCPP=40MHz

- 61 88 mA FlexRay =ON

- 56 84 mA FlexRay =OFF

Flash write

FCP=128MHz,

FCPM=128MHz,

FCPP=32MHz

- 95 125 mA *

Flash erase

FCP=128MHz,

FCPM=128MHz,

FCPP=32MHz

- 95 125 mA *

*: This series has 2 types of flash; main flash and WorkFlash; however, this is the specification when only one of those

is written/erased.

Document Number: 002-04665 Rev *A Page 133 of 175

MB91580M/S Series

(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Typ Max

Power supply

current

ICCS

VCC5

CPU sleep

FCP=128MHz,

FCPm=128MHz,

FCPP=32MHz

- 41 66 mA *1, *2 ,*3, *4

ICCBS

Bus sleep

FCP=128MHz,

FCPm=128MHz,

FCPP=32MHz

- 19 45 mA *1, *2 ,*3 ,*4

ICCT Clock mode

4MHz source

oscillation

- 1.2 1.8 mA When using external cl oc k*5

TA=25°C, *1, *2 ,*3 ,*4

- 2.7 3.3 mA When using crystal

TA=25°C, *1, *2, *3, *4

ICCTS

Clock mode

shutdown

4MHz source

oscillation

- 0.3 0.4 mA When using external cl oc k*5

TA=25°C, *1, *2

- 1.8 1.9 mA When using crystal

TA=25°C, *1, *2

- 0.7 0.8 mA When usi ng ex ter nal cl oc k*5

TA=25°C, *3, *4

- 2.2 2.3 mA When using crystal

TA=25°C, *3 ,*4

ICCH STOP mode - 0.6 1.1 mA TA=25°C, *1 ,*2

- 1.0 1.6 mA TA=25°C, *3 ,*4

ICCHS STOP mode

shutdown

- 0.1 0.2 mA TA=25°C, *1, *2

- 0.5 0.6 mA TA=25°C, *3, *4

*1:MB91F583AMG/F584AMG/F585AMG/F583AMH/F584AMH/F585AMH

*2:MB91F583ASG/F584ASG/F585ASG/F583ASH/F584ASH/F585ASH

*3:MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F584AMK/F585AMK

*4:MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F584ASK/F585ASK

*5: The power supply current is the current value when the external clock is supplied from the X1 pin. Note that

the power supply current value when using the external clock is different from that using the oscillator.

Document Number: 002-04665 Rev *A Page 134 of 175

MB91580M/S Series

11.4 AC Characte ristic s

11.4.1 Main Clock Timing

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Typ Max

Source oscillation clock

frequency FC X0, X1 - 4 - 20 MHz

Source oscillation clock

cycle time tCYL X0, X1 - 50 - 250 ns

Internal operat i ng clock

frequency*

FCP - - - - 128 MHz CP U clock

FCPP - - - - 40 MHz Peripheral bus cl ock

FCPM - - - - 128 MHz Motor cl ock

Internal operat i ng clock

cycle time*

tCP - - 7.82 - - ns CPU clock

tCPP - - 25 - - ns Peripheral bus clock

tCPM - - 7.82 - - ns Motor clock

CAN PLL jitt er

(during lock) tPJ - - -10 - +10 ns

Built-in CR oscillation

frequency FCCR - - 50 100 150 kHz

*: The maximum/minimum value is defined when using the main clock and PLL clock.

 X0,X1 clock timing

CYL

Document Number: 002-04665 Rev *A Page 135 of 175

MB91580M/S Series

 CAN PLL jitter

Ideal clock

PLL output

Slow

Fast

t1 t2 t3

tn-1 tn

Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.

 Guaranteed operation range

Internal operation clock frequency vs. Power supply voltage

Internal operation clock frequency FCP (MHz)

1284

3.7

5.5

Power supply voltage VCC (V)

MB91F58x guaranteed

operation range

PLL guaranteed

operation range

4.5

MB91F58x recommended

guaranteed operation range

Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less.

Document Number: 002-04665 Rev *A Page 136 of 175

MB91580M/S Series

Oscillation clock frequency vs. Internal operation clock frequency

Internal operation clock frequency

Main

clock

PLL clock

Multipli

ed by 1

Multipli

ed by 2

Multipli

ed by 3

Multipli

ed by 4

...

Multiplied

by 20

...

Multiplied

by 32

Oscillation

clock

frequency

4MH

2MH

z 4MHz 8MHz 12MHz 16MHz ...

80MHz ... 128MHz

 Example of oscillation circuit

X1X0

R=330Ω

C2=12pFC1=12pF

4MHz

Note: If it is impossible to start the oscillation within or equal to 20ms when starting from the

oscillation stop state, the clock supervisor performs a detection of oscillation stop and moves

to the fail safe operation.

Design your print circuit board so that the oscillator can start oscillation within 20ms.

In addition, when configuring the oscillator circuit, it is recommended to ask matching

evaluation of the circuit to oscillator manufacturers for the design.

Document Number: 002-04665 Rev *A Page 137 of 175

MB91580M/S Series

AC characteristics are specified by the following measurement reference voltage values.

Input Signal Wav efor m Output Signal Wav efor m

Hysteresis Input Pin (Automotive)

0.5Vcc

0.8Vcc

Output Pin

0.8V

2.4V

Hystere s is Input Pin (CMOS s c hmitt)

0.3Vcc

0.7Vcc

Hysteresis Input Pin (FlexRay)

0.35Vcc

0.65Vcc

11.4.2 Reset input

(TA: Recom mended operating condit ion s, Vcc =5.0V±10%, Vss=AVss=0.0V)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Max

Reset input time tRSTL RSTX -

10 - µs During normal

operation

Oscillation tim e of

oscillator*

+0.1 - ms At Stop mode

100 - µs At Clock mode

Reset

input removal

width 1 - µs

*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For crystal

oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several

hundred µs and several ms, and for an external clock, the time is 0 ms.

RSTX 0.2Vcc 0.2Vcc

RSTL

Document Number: 002-04665 Rev *A Page 138 of 175

MB91580M/S Series

In Stop mode

0.2 V

100

RSTX

90% of

amplitude

Internal operation

clock

Oscillation time

of oscillator Oscillation stabilization

waiting time

Instruction

execution

Internal reset

tRSTL

11.4.3 Power-on Conditions

(TA: Recommende d oper ati ng con diti ons , VSS=0.0V)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Typ Max

Level detection

voltage - VCC5 - 2.024 2.200 2.376 V When turning on

power

Level detection

hysteresis width - VCC5 - - 100 - mV During voltage

drop

Level detection

time - - - - - 30 μs *1

Slope detection

undetected

standard - VCC5 VCC=level detecti on

release level - - 4 mV/μs *2

Power off time tOFF VCC5 - 50 - - ms *3

*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to

generate or release after the power supply voltage has exceeded the detection voltage range.

*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope detection.

This is the standard when the power supply fluctuation is stable.

*3: This time is to start the slope detection at next power on after power down and internal charge loss.

Document Number: 002-04665 Rev *A Page 139 of 175

MB91580M/S Series

11.4.4 Multi-function Serial

CSIO timing (SMR:MD2-0="010"b)

Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect lev el "H" (S M R: SCI NV =0)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*

Master mode

CL=50pF

4tCPP - ns

SCK ↓ ⇒ SOT

delay time tSLOVI

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

-30 +30 ns

Valid SIN ⇒ SCK ↑

setup time tIVSHI SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*, SIN1,

SIN2*, SI N 3 *

30 - ns

SCK ↑ ⇒ Valid SIN hold

time tSHIXI 0 - ns

Serial clock "H"pulse

width tSHSL SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*

Slave mode

CL=50pF

tCPP+10 - ns

Serial clock "L"pulse

width tSLSH 2tCPP-10 - ns

SCK ↓ ⇒ SOT

delay time tSLOVE

SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

- 30 ns

Valid SIN ⇒ SCK ↑

setup time tIVSHE SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*, SIN1,

SIN2*, SI N 3 *

10 - ns

SCK ↑ ⇒ Valid SIN hold

time tSHIXE 20 - ns

SCK fall time tF SCK0_0, SCK0_1

SCK1, SCK2*, SCK3* - 5 ns

SCK rise time tR SCK0_0, SCK0_1

SCK1, SCK2*, SCK3* - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

Notes:

 This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operat ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 140 of 175

MB91580M/S Series

SCYC

SLOVI

IVSHI

SHIXI

SCK

SOT

SIN V

Master Mode

SLSH

SLOVE

IVSHE

SHIXE

SCK

SOT

SIN V

SHSL

Slave Mode

Document Number: 002-04665 Rev *A Page 141 of 175

MB91580M/S Series

Normal synchr ono us tran sfer (SCR:SPI=0) and serial clock output signal detect level "L" (SMR:SCINV=1)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*

Master mode

CL=50pF

4tCPP - ns

SCK ↑ ⇒ SOT

delay time tSHOVI

SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

-30 +30 ns

Valid SIN ⇒ SCK ↓

setup time tIVSLI SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3*

30 - ns

SCK ↓ ⇒ Valid SIN hold

time tSLIXI 0 - ns

Serial clock "H"pulse

width tSHSL SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*

Slave mode

CL=50pF

tCPP+10 - ns

Serial clock "L"pulse

width tSLSH 2tCPP-10 - ns

SCK ↑ ⇒ SOT

delay time tSHOVE

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

- 30 ns

Valid SIN ⇒ SCK ↓

setup time tIVSLE SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3*

10 - ns

SCK ↓ ⇒ Valid SIN hold

time tSLIXE 20 - ns

SCK fall time tF SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3* - 5 ns

SCK rise time tR SCK0_0, SCK0_1

SCK1, SCK2*, SCK3* - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

Notes:

 This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operat ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 142 of 175

MB91580M/S Series

SCYC

SHOVI

IVSLI

SLIXI

SCK

SOT

SIN V

Master Mode

SHSL

SHOVE

IVSLE

SLIXE

SCK

SOT

SIN V

SLSH

Slave Mode

Document Number: 002-04665 Rev *A Page 143 of 175

MB91580M/S Series

SPI compatible (SCR:SPI=1) and serial clock output signal detect level "H" (SMR:SCINV=0)

(TA: Recommended operating conditions, VCC =5.0V±10% , VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*

Master mode

CL=50pF

4tCPP - ns

SCK ↑ ⇒ SOT

delay time tSHOVI

SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3 *,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

-30 +30 ns

Valid SIN ⇒ SCK ↓

setup time tIVSLI SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3*

30 - ns

SCK ↓ ⇒ Valid SIN

hold time tSLIXI 0 - ns

SOT ⇒ SCK ↓

delay time tSOVLI

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3 *,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

2tCPP-30 - ns

Serial clock "H"pulse

width tSHSL SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*

Slave mode

CL=50pF

tCPP+10 - ns

Serial clock "L"pulse

width tSLSH 2tCPP-10 - ns

SCK ↑ ⇒ SOT

delay time tSHOVE

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3 *,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

- 30 ns

Valid SIN ⇒ SCK ↓

setup time tIVSLE SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3 *

10 - ns

SCK ↓ ⇒ Valid SIN

hold time tSLIXE 20 - ns

SCK fall time tF SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3* - 5 ns

SCK rise time tR SCK0_0, SCK0_1

SCK1, SCK2*, SCK3* - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

Notes:

 This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operat ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 144 of 175

MB91580M/S Series

SCYC

SOVLI

SLIXI

SCK

SOT

SIN V

IVSLI

SHOVI

Master Mode

tSLSH

VIL

tSLIXE

VIH

VIL

VOH

VOL

SCK

SOT

SIN VIH

VIL

VIH

VOH

VOL

tIVSLE

tSHOVE VIL

VIH VIH

VIL

tSHSL

*: Changes when writing to TDR register

Slave Mode

Document Number: 002-04665 Rev *A Page 145 of 175

MB91580M/S Series

SPI compatible (SCR:SPI=1) and serial clock output signal detect level "L" (SMR:SCINV=1)

(TA: Recommended op er atin g cond itio ns, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*

Master mode

CL=50pF

4tCPP - ns

SCK ↓ ⇒ SOT

delay time tSLOVI

SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

-30 +30 ns

Valid SIN ⇒ SCK ↑

setup time tIVSHI SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3*

30 - ns

SCK ↑ ⇒ Valid SIN

hold time tSHIXI 0 - ns

SOT ⇒ SCK ↑

delay time tSOVHI

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

2tCPP-30 - ns

Serial clock

"H" pulse width tSHSL SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*

Slave mode

CL=50pF

tCPP+10 - ns

Serial clock

"L" pulse width tSLSH 2tCPP-10 - ns

SCK ↓ ⇒ SOT

delay time tSLOVE

SCK0_0, SCK0_1

SCK1, SCK2*, SCK3*,

SOT0_0, SOT0_1*,

SOT1, SOT2*, SOT3*

- 30 ns

Valid SIN ⇒ SCK ↑

setup time tIVSHE SCK0_0, SCK0_1*,

SCK1, SCK2*, SCK3*,

SIN0_0, SIN0_1*,

SIN1, SIN2*, SIN3*

10 - ns

SCK ↑ ⇒ Valid SIN

hold time tSHIXE 20 - ns

SCK fall time tF SCK0_0, SCK0_1*,

SCK1, SCK2*,

SCK3* - 5 ns

SCK rise time tR SCK0_0, SCK0_1

SCK1, SCK2*,

SCK3* - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

Notes:

 This is the AC characteristic in CLK synchronized mode.



CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operat ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 146 of 175

MB91580M/S Series

SCYC

SOVHI

SHIXI

SCK

SOT

SIN V

IVSHI

SLOVI

Master Mode

SHSL

SHIXE

SCK

SOT

SIN V

IVSHE

SLOVE

SLSH

*: Changes when writing to TDR register

Slave Mode

Document Number: 002-04665 Rev *A Page 147 of 175

MB91580M/S Series

When the serial chip sele ct is used (SCSCR:CSEN=1)

 Serial clock output signal detect level "H" (SMR:SCINV=0)

 Serial chip sele ct ina ctiv e lev el "H" (SCSCR:CSLVL=1)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

SCS ↓ ⇒ SCK ↓

setup time tCSSI SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Master mode

CL=50pF

tCSSU*1+0 tCSSU*1+50 ns

SCK ↑ ⇒ SCS ↑

hold time tCSHI tCSHD*2-50 tCSHD*2+0 ns

SC S des elect time tCSDI SCS1, SCS2*4, SCS3*4 -50+5tCPP

+tCSDS*3 +50+5tCPP

+tCSDS*3 ns

SCS ↓ ⇒ SCK ↓

setup time tCSSE SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Slave mode

CL=50pF

3tCPP+30 - ns

SCK ↑ ⇒ SCS ↑

hold time tCSHE 0 - ns

SC S des elect time tCSDE SCS1, SCS2*4, SCS3*4 3tCPP+30 - ns

SCS ↓ ⇒ SOT

delay time tDSE SCS1, SCS2*4,

SCS3*4,

SOT1, SOT2*4,

SOT3*4

- 40 ns

SCS ↑ ⇒ SOT

delay time tDEE 0 - ns

*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select tim ing oper ation clock

*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select tim ing oper ation clock

*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing oper a tion clo ck

*4: Only available with MB91F583AM/F584AM/F585AM

For details of *1, *2 and *3 above, see Hardware Manual.

Notes:



This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operat ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 148 of 175

MB91580M/S Series

SCK output

SOT

(Normal Sync transfer)

SOT

(SPI compatible)

CSSI

SCS output

CSHI

CSDI

Master Mode

SCK input

SOT

(Normal Sync

transfer)

SOT

(SPI compatible)

CSSE

SCS input

CSHE

CSDE

DSE

DEE

Slave Mode

Document Number: 002-04665 Rev *A Page 149 of 175

MB91580M/S Series

When the serial chip sele ct is used (SCSCR:CSEN=1)

 Serial clock output signal detect level "L" (SMR:SCINV=1)

 Serial chip sele ct ina ctive lev el "H" (SCSCR:CS LVL=1)

(TA: Recommende d oper a ting con diti on s , VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

SCS ↓ ⇒ SCK ↑

setup time tCSSI SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Master mode

CL=50pF

tCSSU*1+0 tCSSU*1+50 ns

SCK ↓ ⇒ SCS ↑

hold time tCSHI tCSHD*2-50 tCSHD*2+0 ns

SCS desel ect time tCSDI SCS1, SCS2*4,

SCS3*4 -50+5tCPP

+tCSDS*3 +50+5tCPP

+tCSDS*3 ns

SCS ↓ ⇒ SCK ↑

setup time tCSSE SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4

Slave mode

CL=50pF

3tCPP+30 - ns

SCK ↓ ⇒ SCS ↑

hold time tCSHE 0 - ns

SCS desel ect time tCSDE SCS1, SCS2*4,

SCS3*4 3tCPP+30 - ns

SCS ↓ ⇒ SOT

delay time tDSE SCS1, SCS2*4,

SCS3*4,

SOT1, SOT2*4,

SOT3*4

- 40 ns

SCS ↑ ⇒ SOT

delay time tDEE 0 - ns

*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select tim ing oper ation clock

*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select tim ing oper ation clock

*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing oper a tion clo ck

*4: Only available with MB91F583AM/F584AM/F585AM

For details of *1, *2 and *3 above, see Hardware Manual.

Notes:

 This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the in terna l oper at ion cl ock used and other p ara meters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 150 of 175

MB91580M/S Series

SCK output

SOT

(Normal Sync transfer)

SOT

(SPI compatible)

CSSI

SCS output

CSHI

CSDI

Master Mode

SCK input

SOT

(Normal Sync

transfer)

SOT

(SPI compatible)

tCSSE

SCS input

tCSHE tCSDE

tDSE

tDEE

Slave Mode

Document Number: 002-04665 Rev *A Page 151 of 175

MB91580M/S Series

When the serial chip sele ct is used (SCSCR:CSEN=1)

 Serial clock output signal detect level "H" (SMR:SCINV=0)

 Serial chip select inactiv e lev el "L" (SCSCR:CSLVL=0)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

SCS ↑ ⇒ SCK ↓

setup time tCSSI SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Master mode

CL=50pF

tCSSU*1+0 tCSSU*1+50 ns

SCK ↑ ⇒ SCS ↓

hold time tCSHI tCSHD*2-50 tCSHD*2+0 ns

SC S des elect time tCSDI SCS1, SCS2*4, SCS3*4 -50+5tCPP

+tCSDS*3 +50+5tCPP

+tCSDS*3 ns

SCS ↑ ⇒ SCK ↓

setup time tCSSE SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Slave mode

CL=50pF

3tCPP+30 - ns

SCK ↑ ⇒ SCS ↓

hold time tCSHE 0 - ns

SC S des elect time tCSDE SCS1, SCS2*4, SCS3*4 3tCPP+30 - ns

SCS ↑ ⇒ SOT

delay time tDSE SCS1, SCS2*4, SCS3*4,

SOT1, SOT2*4,

SOT3*4

- 40 ns

SCS ↓ ⇒ SOT

delay time tDEE 0 - ns

*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select tim ing oper ation clock

*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select tim ing oper ation clock

*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing oper a tion clo ck

*4: Only available with MB91F583AM/F584AM/F585AM

For details of *1, *2 and *3 above, see Hardware Manual.

Notes:



This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation cl ock us ed and other p ar a meter s.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 152 of 175

MB91580M/S Series

SCK output

SOT

(Normal Sync transfer)

SOT

(SPI compatible)

CSSI

SCS output

CSHI

CSDI

Master Mode

SCK input

SOT

(Normal Sync

transfer)

SOT

(SPI compatible)

CSSE

SCS input t

CSHE

CSDE

DSE

DEE

Slave Mode

Document Number: 002-04665 Rev *A Page 153 of 175

MB91580M/S Series

When the serial chip sele ct is used (SCSCR:CSEN=1)

 Serial clock output signal detect level "L" (SMR:SCINV=1)

 Serial chip sele ct ina ctiv e level "L" (SCSCR:CSLVL=0)

(TA: Recommended op er atin g cond itio ns, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

SCS ↑ ⇒ SCK ↑

setup time tCSSI SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Master mode

CL=50pF

tCSSU*1+0 tCSSU*1+50 ns

SCK ↓ ⇒ SCS ↓

hold time tCSHI tCSHD*2-50 tCSHD*2+0 ns

SC S des elect time tCSDI SCS1, SCS2*4, SCS3*4 -50+5tCPP

+tCSDS*3 +50+5tCPP

+tCSDS*3 ns

SCS ↑ ⇒ SCK ↑

setup time tCSSE SCK1, SCK2*4,

SCK3*4,

SCS1, SCS2*4,

SCS3*4 Slave mode

CL=50pF

3tCPP+30 - ns

SCK ↓ ⇒ SCS ↓

hold time tCSHE 0 - ns

SCS desel ect time tCSDE SCS1, SCS2*4, SCS3*4 3tCPP+30 - ns

SCS ↑ ⇒ SOT

delay time tDSE SCS1, SCS2*4, SCS3*4,

SOT1, SOT2*4,

SOT3*4

- 40 ns

SCS ↓ ⇒ SOT

delay time tDEE 0 - ns

*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select tim ing oper ation clock

*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select tim ing oper ation clock

*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing oper a tion clo ck

*4: Only available with MB91F583AM/F584AM/F585AM

For details of *1, *2 and *3 above, see Hardware Manual.

Notes:



This is the AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.

 The maximum baud rate is limited by the internal operation clock us ed and other parameters.

See Hardware Manual for details.

Document Number: 002-04665 Rev *A Page 154 of 175

MB91580M/S Series

SCK output

SOT

(Normal Sync transfer)

SOT

(SPI compatible)

CSSI

SCS output

CSHI

CSDI

Master Mode

SCK input

SOT

(Normal Sync

transfer)

SOT

(SPI compatible)

CSSE

SCS input

CSHE

CSDE

DSE

DEE

Slave Mode

Document Number: 002-04665 Rev *A Page 155 of 175

MB91580M/S Series

UART (Async Serial Interface) timing (SMR:MD2-0="000"b, "001"b)

When the external clock is selected (BGR:EXT=1)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock

"L" pulse width tSLSH

SCK0_0, SCK0_1*,

SCK1, SCK2*,

SCK3* CL=50pF

tCPP+10 - ns

Serial clock

"H" pulse width tSHSL tCPP+10 - ns

SCK fall time tF - 5 ns

SCK rise time tR - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

SCK

SHSL

SLSH

W hen the external clock is selected

LIN interface (v2.1)( LIN Communication Control Interface (v2.1)) timing (SMR:MD2-0="011"b)

When the external clock is selected (BGR:EXT=1)

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock

"L" pulse width tSLSH

SCK0_0, SCK0_1*,

SCK1, SCK2*,

SCK3* CL=50pF

tCPP+10 - ns

Serial clock

"H" pulse width tSHSL tCPP+10 - ns

SCK fall time tF - 5 ns

SCK rise time tR - 5 ns

*: Only available with MB91F583AM/F584AM/F585AM

SCK

SHSL

SLSH

W hen the external clock is selected

Document Number: 002-04665 Rev *A Page 156 of 175

MB91580M/S Series

I2C timing (SMR:MD2-0="100"b)

(TA: Recommended op er atin g cond itio ns, VCC=5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Standard

mode High-speed

mode*3 Unit Remarks

Min Max Min Max

SCL clock frequency fSCL

SCK0_0,

SCK0_1*5,

SCK2*5, SCK3*5

(SCL)

CL=50pF

R=(VP/IOL) *1

0 100 0 400 kHz

"Repeat START

condition" hold time

SDA ↓ → SCL ↓ tHDSTA

SCK0_0,

SCK0_1*5,

SCK2*5, SCK3*5

(SCL)

SOT0_0,

SOT0_1*5,

SOT2*5, SOT3*5

(SDA)

4.0 - 0.6 - µs

"L" width for SCL

clock tLOW SCK0_0,

SCK0_1*5,

SCK2*5, SCK3*5

(SCL)

4.7 - 1.3 - µs

"H" width for SCL

clock tHIGH 4.0 - 0.6 - µs

"Repeat START

condition" setup time

SCL ↑ → SDA ↓ tSUSTA SCK0_0,

SCK0_1*5,

SCK2*5, SCK3*5

(SCL)

SOT0_0,

SOT0_1*5,

SOT2*5, SOT3*5

(SDA)

4.7 - 0.6 - µs

Data hold time

SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45

*2 0 0.90

*3 µs

Data setup time

SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns

"STOP condition"

setup time

SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - µs

Bus free time

between "STOP

conditi on" and

"START condition"

tBUF - 4.7 - 1.3 - µs

Noise filt er tSP - 2tCPP

*4 - 2tCPP

*4 - ns

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. VP

shows that the power supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.

*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.

*3: A high-spee d mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies

the requirement of "tSUDAT ≥ 250 ns".

*4: tCPP is the peripheral clock cycle time. Adjust the clock of the peripheral bus to 8MHz or more when using I2C.

*5: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 157 of 175

MB91580M/S Series

SDA

SCL

HDSTA

LOW

HDDAT

SUDAT

HIGH

SUSTA

HDSTA

BUF

SUSTO

11.4.5 Timer Input Timing

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse

width tTIWH,

tTIWL

TIN0 to TIN3,

IN0 to IN3,

FRCK0 t o FRCK5,

TIOA1, TIOB0, TIOB1

- 4tCPP - ns

AIN0,AIN1,

BIN0,BIN1,

ZIN0,ZIN1 - 2tCPP - ns

 Timer input timing

TINx

INx

FRCKx

TIOAx,TIOBx

AINx,BINx,ZINx

TIWL

TIWH

11.4.6 Trigger Input Timing

(TA: Recommended operating conditions, VCC =5.0V±10% VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse

width tTRGH,

tTRGL

INT0 to INT6, INT7

ADTG0 to ADTG2,

RX0, RX1*,

TRG0, TRG1,

DTTI0

5tCPP - ns

1 - µs At Stop mode

*: Only available with MB91F583AM/F584AM/F585AM

Document Number: 002-04665 Rev *A Page 158 of 175

MB91580M/S Series

 Trigger input timing

TRGL

TRGH

INTx

ADTGx

RXx

TRGx

DTTIx

11.4.7 NMI Input Timing

(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse width tNMIL NMIX - 4tCPP - ns

 NMIX input timing

NMIX

NMIL

Document Number: 002-04665 Rev *A Page 159 of 175

MB91580M/S Series

11.4.8 Low-voltage Detection (External Low-voltage Detection)

(TA: Recommende d oper ati ng cond iti ons, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min

Typ

Max

Power supply

voltage range VDP5 VCC5 - 3.7 - 5.5 V

Detecti on voltage VDL VCC5 *1 -8% 3.9 +8% V

When power supply

voltage falls and

detection level is set

initially

Hysteresis width VHYS VCC5 - - 0.1 - V When power supply

voltage rises

Low-voltage

detection time Td - - - - 30 μs

Power supply

voltage fluct uation

rate - VCC5 - -2 - 2 V/ms *2

*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the

low-voltage detection time (Td), there is the possibility to generate or release after the power supply voltage has

exceeded the detection voltage range.

*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluc tuation of the

power supply within the limits of the power supply voltage fluctuation rate.

11.4.9 Low-voltage Detection (Internal Low-voltage Detection)

(TA: Recommend ed oper ati ng con diti on s, VSS=AVSS=0.0V)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Typ Max

Power supply

voltage range VRDP5 - - 1.1 - 1.3 V

Detecti on voltage VRDL - * 0.8 0.9 1.0 V When power supply

voltage falls

Hysteresis width VRHYS - - - 0.1 - V When power supply

voltage rises

Low-voltage

detection time - - - - - 30 μs

*: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to generate or

release after the power supply voltage has exceeded the detection voltage range.

Document Number: 002-04665 Rev *A Page 160 of 175

MB91580M/S Series

11.5 A/D Converter

11.5.1 Electrical Characteristics

(TA: Recommende d oper ati ng cond iti ons, VCC =5.0V±10%, AVCC=5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Resolution - - - - 12 bit

Non linearity error - - -4.0 - +4.0 LSB

Different i al lineari ty

error - - -1.9 - +1.9 LSB

Zero transition voltage

VOT AN0 to AN14, AN16 to

AN18*3, A N19, AN20,

AN21 to AN23*3

AVRL+

0.5LSB-20 - AVRL+

0.5LSB+20 mV 1LSB=

(VFST-VOT)/40

Full-scale transition

voltage VFST AN0 to AN14, AN16 to

AN18*3, A N19, AN20,

AN21 to AN23*3

AVRH-

1.5LSB-20 - AVRH-

1.5LSB+20 mV

Sampl ing time tSMP - 0.3 - 12 µs *1

Compare time tCMP - 0.7 - 28 µs *1

A/D conversion time tCNV - 1.0 - 40 µs *1

Analog port input

current IAIN AN0 to AN14, AN16 to

AN18*3, A N19, AN20,

AN21 to AN23*3 -1.0 - 1.0 µA VAVSS ≤ VAIN

≤VAVCC

Analog input voltage VAIN AN0 to AN14, AN16 to

AN18*3, A N19, AN20,

AN21 to AN23*3 AVSS - AVRH V

Reference voltage

AVRH AVRH0,

AVRH1 4.5 - 5.5 V Avcc ≥ AVRH

AVRL AVRL0,

AVRL1, - 0.0 - V

Power supply current

IA AVCC0,

AVCC1

- 1.5 2.1 mA 3 units

operating

IAH - - 25 µA 3 units

operating*2

IR AVRH0,

AVRH1

- 3 6 mA 3 units

operating

IRH - - 4.8 µA 3 units

operating*2

Variation between

channels - AN0 to AN14, AN16 to

AN18*3, A N19, AN20,

AN21 to AN23*3 - - 4 LSB Every 1 unit*4

*1: Time for each channel.

*2: The Power supply current (Vcc =AVcc=5.0V) is specified if the A/D converter is not operating and CPU is stopped.

*3: Only available with MB91F583AM/F584AM/F585AM

*4: Unit0 AN0 to AN7

Unit1 AN8 to AN14

Unit2 AN16 to AN23

Document Number: 002-04665 Rev *A Page 161 of 175

MB91580M/S Series

11.5.2 Definition of Terms

Resolution: Analog variation that is recognized by an A/D converter.

Linearity error : Deviation of the actual conversion characteristics from a straight line that connects the zero

transition point ("0000 0000 0000"←→"0000 0000 0001") to the full-scale transition point ("1111

1111 1110"←→"1111 1111 1111").

Differential linearity error: Deviation of the input voltage from the ideal value that is required to change the output

code by 1LSB.

Linearity error Differential linearity error

Linearity error of digital output N = V

- {1LSB×(N-1) + V

}[LSB]

1LSB

Differential linearity error of digital output N = V

(N + 1) T

- V

-1 LSB [LSB]

1LSB

1LSB = V

FST

- V

[V]

4094

: Voltage at which the digital output changes from "000

" to "001

FST

: Voltage at which the digital output changes from "FFE

" to "FFF

AVSS

(AVRL) AVRH AVRH

Actual conversion

characteristics

{1 LS B (N - 1) + V

}

AVSS

(AVRL)

FST

(Actually-measured value)

(N+1)T

Ideal characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Ideal characteristics

Digital output

(Ac tually- m eas ur ed v alue)

(Actually-

measured

value)

(Ac tually- m eas ur ed v alue)

Analog input Analog input

(Actually-measured

value)

Digital output

N - 1

N - 2

N + 1

FFF

FFE

FFD

004

003

002

001

11.5.3 Notes on Using A/D Converter

When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this case, it

is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.

Document Number: 002-04665 Rev *A Page 162 of 175

MB91580M/S Series

 Analog input circuit model

R C

12bit A/D 1.9kΩ (max) 8.3pF (max) (4.5V Avcc 5.5V)

Note: Listed values must be considered as reference values.

Sampling ON

Comparator

Analog input

Document Number: 002-04665 Rev *A Page 163 of 175

MB91580M/S Series

11.6 D/A Converter

(TA: Recommende d oper ati ng cond iti ons, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Resolution - - - - 10 bit

Different i al lineari ty error - - -4.0 - +4.0 LSB When the analog output

voltage is 0.5V to 4.5V

11.7 Flash memory

11.7.1 Electrical Characteristics

Parameter Value Unit Remarks

Min Typ Max

Sector erase time

- 200 800 ms 8 Kbyte sector

excluding internal preprogramm i ng time

- 300 1100 ms 8 Kbyte sector

including internal preprogramm i ng time

- 400 2000 ms 64 Kbyte sector

excluding internal preprogramm i ng time

- 700 3700 ms 64 Kbyte sector*1

including internal preprogramm i ng time

8-bit writing time - 9 288 µs Excluding overhead tim e at system level

16-bit writing time - 12 384 µs Excluding overhead tim e at system level*1

ECC writing time - 9 288 µs E xcludi ng overhead t ime at system level

Erase cycl e *2/

Data retention time

1,000 cycles/20 years,

10,000 cycles/10 years,

100,000 cycles/5 years

- - - Average tem perat ure TA=+85°C

*1: The guaranteed value for erase up to 100,000 cycles

*2: Number of erase cycles for each sector

*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measuremen t s into normaliz ed value at + 85°C).

Document Number: 002-04665 Rev *A Page 164 of 175

MB91580M/S Series

11.7.2 Notes

While the F las h mem ory is written or erased, shutdown of the external power (Vcc) is prohibited.

In the application system where Vcc might disappear while writing or erasing, be sure to turn the power off by using an

external low-v olt age dete ction function.

To put it concretely, after the external power supply voltage falls below the detection voltage (VDL*), hold Vcc at 2.7V or

more within the duration calculated by the following expression:

Td*[µs] + (PCLK cycle[µs] × 257) + 50[µs]

*: See "4. AC characteristics (8) Low-voltage detection (External low-voltage detection)."

Document Number: 002-04665 Rev *A Page 165 of 175

MB91580M/S Series

12. Example Characteristics

This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.

10.00

100.00

-50 050 100 150

ICC5[mA]

TA[ºC]

normal operati on

(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128M Hz, FlexRay=ON

(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40M Hz, FlexRay=ON

(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=ON

(VCC = 5.5V)

(1)

(2)

(3)

(4)

(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=ON

10.00

100.00

-50 050 100 150

ICC5[mA]

TA[ºC]

normal operati on

(VCC = 5.5V)

(1)

(2)

(3)

(4)

(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128M Hz, FlexRay=OFF

(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40M Hz, FlexRay=OFF

(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=OFF

(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=OFF

Document Number: 002-04665 Rev *A Page 166 of 175

MB91580M/S Series

10.000

100.000

-50 050 100 150

ICCS5/ICCBS5 [mA]

TA[ºC]

sleep mode

CPU Sleep(128MHz)

BUS Sleep (128MHz)

(VCC = 5.5V)

Document Number: 002-04665 Rev *A Page 167 of 175

MB91580M/S Series

0.001

0.010

0.100

1.000

10.000

-50 050 100 150

ICCT5 [mA]

TA[ºC]

Watc h mode

Main osc (4MHz)

External clock (4MHz)

(VCC = 5.5V)(VCC = 5.5V)

0.001

0.010

0.100

1.000

10.000

-50 050 100 150

H5 [mA]

[ºC]

Stop mode

= 5.5V)

Document Number: 002-04665 Rev *A Page 168 of 175

MB91580M/S Series

0.01

0.10

1.00

10.00

100.00

1000.00

-50 050 100 150

ICCT52 [µA]

TA[ºC]

Watc h mode(power off)

Main osc (4MHz)

External clock (4MHz)

(VCC = 5.5V)

0.01

0.10

1.00

10.00

100.00

1000.00

-50 050 100 150

H52 [µA]

[ºC]

Stop mode(power of f)

= 5.5V)

Document Number: 002-04665 Rev *A Page 169 of 175

MB91580M/S Series

13. Ordering Information

Part number Package*

MB91F583AMGPMC-GTE1

MB91F584AMGPMC-GTE1

MB91F585AMGPMC-GTE1

MB91F583AMHPMC-GTE1

MB91F584AMHPMC-GTE1

MB91F585AMHPMC-GTE1

MB91F583AMJPMC-GTE1

MB91F584AMJPMC-GTE1

MB91F585AMJPMC-GTE1

MB91F583AMKPMC-GTE1

MB91F584AMKPMC-GTE1

MB91F585AMKPMC-GTE1

100-pin plastic LQFP

(FPT-100P-M20)

MB91F583ASGPMC1-GTE1

MB91F584ASGPMC1-GTE1

MB91F585ASGPMC1-GTE1

MB91F583ASHPMC1-GTE1

MB91F584ASHPMC1-GTE1

MB91F585ASHPMC1-GTE1

MB91F583ASJPMC1-GTE1

MB91F584ASJPMC1-GTE1

MB91F585ASJPMC1-GTE1

MB91F583ASKPMC1-GTE1

MB91F584ASKPMC1-GTE1

MB91F585ASKPMC1-GTE1

64-pin plastic LQFP

(FPT-64P-M24)

*: For details of t he pack age, see Package Dimensions

Document Number: 002-04665 Rev *A Page 170 of 175

MB91580M/S Series

14. Package Dimensions

100-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 14.0 mm × 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm Max

Weight 0.65 g

Code

(Reference)P-LFQFP100-14×14-0.50

100-pin plastic LQFP

(FPT-100P-M20)

C2005 -2010 FUJIT SU SEMICONDUCTOR LIMITED F100031S-c-3-5

16.00±0.20(.630±.008)SQ

125

76 50

100

0.50(.020) 0.20±0.05

(.008±.002)

0.08(.003) 0.145±0.055

(.006±.002)

0.08(.003)

"A"

INDEX .059–.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0°~8°

0.50±0.20

(.020±.008)

(.024±.006)

0.60±0.15

0.25(.010)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

*14.00±0.10(.551±.004)SQ

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

Document Number: 002-04665 Rev *A Page 171 of 175

MB91580M/S Series

64-pin plastic LQFP Lead pitch 0.50 mm

Pac kage wi dth ×

pack age length 10.0 × 10.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm MAX

Weight 0.32 g

Code

(Reference)P-LFQFP64-10×10-0.50

64-pin plastic LQFP

(FPT-64P-M24)

LE AD No.

Details of "A" part

0.25(.010)

(Stand off)

0.10±0.10

0.60±0.15

(.024±.006)

0.50±0.20

(.020±.008)

1.50+0.20

–0.10

+.008

–.004

.059

0°~8°

"A"

0.08(.003)

0.145±0.055

(.006±.002)

0.08(.003)

(.008±.002)

0.20±0.05

0.50(.020)

12.00±0.20(.472±.008)SQ

INDEX

3348

161

2005-2010 FUJIT SU SEMICONDUCTOR LIMITED F64036S-c-1-3

(Mounting height)

*10.00±0.10(.394±.004)SQ

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

(.004±.004)

Document Number: 002-04665 Rev *A Page 172 of 175

MB91580M/S Series

15. Ma jor Changes

Spansion Publication Number: MB91F585AMG_DS705-00013

Page Section Change Results

Revision 1.0

- - Initi al releas e

Revision 2.0

- -

The product series name should be corrected.

MB91F585MG MB91F585AMG

MB91F585MH MB91F585AMH

MB91F585MJ MB91F585AMJ

MB91F585MK MB91F585AMK

MB91F584MG MB91F584AMG

MB91F584MH MB91F584AMH

MB91F584MJ MB91F584AMJ

MB91F584MK MB91F584AMK

MB91F583MG MB91F583AMG

MB91F583MH MB91F583AMH

MB91F583MJ MB91F583AMJ

MB91F583MK → MB91F583AMK

MB91F585SG MB91F585ASG

MB91F585SH MB91F585ASH

MB91F585SJ MB91F585ASJ

MB91F585SK MB91F585ASK

MB91F584SG MB91F584ASG

MB91F584SH MB91F584ASH

MB91F584SJ MB91F584ASJ

MB91F584SK MB91F584ASK

MB91F583SG MB91F583ASG

MB91F583SH MB91F583ASH

MB91F583SJ MB91F583ASJ

MB91F583SK MB91F583ASK

2 Features

The features of CR oscillation should be corrected.

Oscillation frequency: 100kHz, with frequency accuracy ± 10%

↓

Oscillation frequency: 100kHz, with frequency accuracy ± 50%

(pre-trimming)

22 I/O Circuit Type

The specification of "H" level input voltage and "L" level input

voltage of FlexRay should be corrected.

FlexRay input (0.65Vcc/0.35Vcc)

↓

FlexRay input (0.7Vcc/0.3Vcc)

Document Number: 002-04665 Rev *A Page 173 of 175

MB91580M/S Series

Page Section Change Results

33 Memory Map The memory map should be corrected.

The address of "Reset vector table" and "Interrupt vect or table"

should be added

54,85 I/O Map

Address:00150CH

The register name should be corrected.

STMCR00 → STMCR0

54,55,85

I/O Map

Address: 00150 EH, 001510H, 001511H,

001512H,

001513H

The registers should be deleted.

SCS CR0,S CSTR30 ,SCSTR20,SCST R10 ,SCSTR00

63,92 I/O Map

Address:00D310H

The initial values of MHDS should be corrected.

-0000000 -0000000 -0000000 10000000

↓

-0000000 -0000000 -0000000 00000000

104 Electrical Characteristics

DC Caharacteristics

The specification of " H" level input voltage of P021-P023,P025-P027

should be corrected.

Min:0.65 ×Vcc

↓

Min: 0.7 × Vcc

105 Electrical Characteristics

DC Caharacteristics

The specification of " L" level input voltage of P021-P023,P025-P027

should be corrected.

Max: 0.35 × Vcc

↓

Max: 0.3 × Vcc

111 Electrical Characteristics

AC Characteristics

Main Clock Timing The remarks of "CAN PLL jitter" should be deleted.

111 Electric al Characterist i cs

AC Characteristics

Main Clock Timing

The specifications of "The Built-in CR oscill ation frequency" should

be corrected.

Min: 90kHz,

Max: 110kHz

↓

Min:50kHz

Max:150kHz,

- - Company name and layout design change

NOTE: Please see “Document History” a bout later revised information.

Document Number: 002-04665 Rev *A Page 174 of 175

MB91580M/S Series

Document History

Document T itle: MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,

MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK, MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,

MB91580M/S Series FR81S, 32-bit Microc on troll er Datasheet

Document Number: 002-04665

Revision

ECN Orig. of

Change

Submission

Date Description of Change

** − KOJM 04/18/2014 Migrated to Cypress and assigned document number 002-04665.

No change to document contents or format.

*A 5139690 KOJM 03/29/2016 Updated to Cypress template

Document Number: 002-04665 Rev *A Page 175 of 175

MB91580M/S Series

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