THIS SPEC IS OBSOLETE
Spec No: 002-08364
Spec Title: MB39C015 2CH DC/DC CONVERTER IC WITH
PFM/PWM SYNCHRONOUS RECTIFICATION
Replaced by: NONE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-08364 Rev. *D Revised December 10, 2018
MB39C015
2 ch DC/DC Converter IC with
PFM/PWM Synchronous Rectification
Description
The MB39C015 is a current mode type 2-channel DC/DC converter IC built-in voltage detection, synchronous rectifier, and down
conversion support. The device is integrated with a switching FET, oscillator, error amplifier, PWM control circuit, reference voltage
source, and voltage detection circuit.
External inductor and decoupling capacitor are needed only for the external component.
As combining with external parts enables a DC/DC converter with a compact and high load response characteristic, this is suitable
as the built-in power supply for such as mobile phone/PDA, DVDs, and HDDs.
Features
■High efficiency : 96% (Max)
■Output current (DC/DC) : 800 mA/ch (Max)
■Input voltage range : 2.5 V to 5.5 V
■Operating frequency : 2.0 MHz (Typ)
■No flyback diode needed
■Low dropout operation : For 100% on duty
■Built-in high-precision reference voltage generator : 1.30 V ± 2%
■Consumption current in shutdown mode : 1 µA or less
■Built-in switching FET : P-ch MOS 0.3 Ω (Typ) N-ch MOS 0.2 Ω (Typ)
■High speed for input and load transient response in the current mode
■Over temperature protection
■Packaged in a compact package : QFN-24
Applications
■Flash ROMs
■MP3 players
■Electronic dictionary devices
■Surveillance cameras
■Portable GPS navigators
■DVD drives
■IP phones
■Network hubs
■Mobile phones etc.
Document Number: 002-08364 Rev. *D Page 2 of 35
MB39C015
Contents
Description ............................................................................. 1
Features .................................................................................. 1
Applications ........................................................................... 1
Contents ................................................................................. 2
1. Pin Assignment ................................................................ 3
2. Pin Descriptions ............................................................... 4
3. I/O Pin Equivalent Circuit Diagram ................................. 5
4. Block Diagram .................................................................. 6
5. Function of Each Block .................................................... 8
6. Absolute Maximum Ratings .......................................... 10
7. Recommended Operating Conditions .......................... 11
8. Electrical Characteristics ............................................... 12
9. Test Circuit For Measuring Typical Operating
Characteristics ................................................................. 14
10. Application Notes ......................................................... 15
10.1 Selection of Components ...................................... 15
10.2 Output Voltage Setting ......................................... 16
10.3 About Conversion Efficiency ................................. 16
10.4 Power Dissipation and Heat Considerations ......... 17
10.5 XPOR Threshold Voltage Setting [VPORH,
VPORL] ....................................................................... 18
10.6 Transient Response .............................................. 19
10.7 Board Layout, Design Example ............................. 20
11. Example Of Standard Operation Characteristics ...... 21
12. Application Circuit Examples ...................................... 29
13. Application Circuit Examples ...................................... 30
14. Usage Precautions ....................................................... 32
15. Ordering Information .................................................... 32
16. RoHS Compliance Information .................................... 32
17. Package Dimension ...................................................... 33
Document History ................................................................ 34
Sales, Solutions, and Legal Information ........................... 35
Document Number: 002-08364 Rev. *D Page 3 of 35
MB39C015
1. Pin Assignment
LX2 LX1DGND2 DGND2 DGND1 DGND1
CTLP
19
20
21
22
23
24
12
11
10
9
8
7
123456
18 17 16 15 14 13
VREFCTL2 CTL1 AGND AVDD
DVDD2
DVDD2
OUT2
MODE2
V
REFIN2
XPOR
DVDD1
DVDD1
OUT1
MODE1
VREFIN
1
VDET
(Top View)
(WNN024)
Document Number: 002-08364 Rev. *D Page 4 of 35
MB39C015
2. Pin Descriptions
Pin No. Pin Name I/O Description
1 CTLP I Voltage detection circuit block control input pin.
(L : Voltage detection function stop, H : Normal operation)
2/3 CTL2/CTL1 I DC/DC converter block control input pin.
(L : Shut down, H : Normal operation)
4 AGND – Control block ground pin.
5 AVDD – Control block power supply pin.
6 VREF O Reference voltage output pin.
7 VDET I Voltage detection input pin.
8/23 VREFIN1/VREFIN2 I Error amplifier (Error Amp) non-inverted input pin.
9/22 MODE1/MODE2 I Use pin at L level or leave open.
10/21 OUT1/OUT2 I Output voltage feedback pin.
11, 12/
19, 20
DVDD1/DVDD2 – Drive block power supply pin.
13/18 LX1/LX2 O Inductor connection output pin.
High impedance during shut down.
14, 15/
16, 17
DGND1/DGND2 – Drive block ground pin.
24 XPOR O VDET circuit output pin.
Connected to an N-ch MOS open drain circuit.
Document Number: 002-08364 Rev. *D Page 5 of 35
MB39C015
3. I/O Pin Equivalent Circuit Diagram
GND
VDD
LX1, LX2
∗
∗
GND
VDD
VREF
XPOR
∗
GND
MODE1,
MODE2
∗
GND
VDD
∗
∗
GND
VDD
CTL1, CTL2, CTLP
GND
VDD
∗
∗
VREFIN1,
VREFIN2,
VDET OUT1, OUT2
∗
∗
* : ESD Protection device
Document Number: 002-08364 Rev. *D Page 6 of 35
MB39C015
4. Block Diagram
×3−
+
−
+
VIN DVDD2
11, 12 19, 20
DVDD1
AVDD
VOUT1
VIN
XPOR
5
16, 17
DGND2
14, 15
DGND1AGND4
ON/OFF
ON/OFF
ON/OFF
CTL1
OUT1
3
10
8
VREFIN1
DAC
GND 9
1
7
MODE1
VDET
CTLP
CTL2
OUT2
VIN
DVDD1
IOUT
Comparator
ERR
Amplifier
ERR
Amplifier
PWM
Logic
Control
×3−
+
DVDD2
IOUT
Comparator
PWM
Logic
Control
LX1
13
VOUT2
LX2
18
24
1.30 V
VREF
VREF
VREFIN2
MODE2
GND
6
21
2
23
22
Document Number: 002-08364 Rev. *D Page 7 of 35
MB39C015
■Current Mode
❐Original voltage mode type :
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Reference triangular wave (VTRI)
❐Current mode type :
Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the
oscillator (rectangular wave generation circuit) and SW FET is used.
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in the oscillator (rectangular wave generation
circuit) and SW FET
V
IN
ton
toff
V
TRI
V
c
Vc
V
TRI
V
IN
toff
Vc
Vc
V
IDET
S
R
ton
SR-FF
V
IDET
Q
−
+−
+
Voltage mode type model Current mode type model
Oscillator
Note : The above models illustrate the general operation and an actual operation will be preferred in the IC.
Document Number: 002-08364 Rev. *D Page 8 of 35
MB39C015
5. Function of Each Block
■PWM Logic Control Circuit
The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency (2.0 MHz) oscillated
from the built-in oscillator (square wave oscillation circuit).
■IOUT Comparator Circuit
This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing VIDET obtained
through I-V conversion of peak current IPK of ILX with the Error Amp output, the built-in P-ch MOS FET is turned off via the PWM Logic
Control circuit.
■Error Amp Phase Compensation Circuit
This circuit compares the output voltage to reference voltages such as VREF. This IC has a built-in phase compensation circuit that
is designed to optimize the operation of this IC.This needs neither to be considered nor addition of a phase compensation circuit and
an external phase compensation device.
■VREF Circuit
A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.30 V (Typ).
■Voltage Detection (VDET) Circuit
The voltage detection circuit monitors the voltage at the VDET pin. Normally, use the XPOR pin through pull-up with an external
resistor. When the VDET pin voltage reaches 0.6 V, it reaches the H level.
Timing Chart Example : (XPOR Pin Pulled Up to VIN)
■Protection Circuit
This IC has a built-in over-temperature protection circuit. The over-temperature protection circuit turns off both N-ch and P-ch switching
FETs when the junction temperature reaches + 135 °C . When the junction temperature comes down to + 110 °C , the switching FET
is returned to the normal operation. Since the PWM control circuit of this IC is in the control method in current mode, the current peak
value is also monitored and controlled as required.
VIN
CTLP
VDET
POR
V
UVLO
V
THHP
V
THLP
VUVLO : UVLO threshold voltage
VTHHPR, VTHLPR : XPOR threshold voltage
Document Number: 002-08364 Rev. *D Page 9 of 35
MB39C015
■Function Table
MODE
Input Output
CTL1 CTL2 CTLP CH1 Function CH2 Function VDET
Function
VREF
Function
Shutdown mode L Stopped
Operating mode
H L L Operation Stopped Stopped
Outputs 1.3 V
L H L Stopped Operation Stopped
L L H Stopped Stopped Operation
H H L Operation Operation Stopped
L H H Stopped Operation Operation
H L H Operation Stopped Operation
HOperation
Document Number: 002-08364 Rev. *D Page 10 of 35
MB39C015
6. Absolute Maximum Ratings
*1 : Power dissipation value between + 25 °C and + 85 °C is obtained by connecting these two points with straight line.
*2 : When mounted on a four-layer epoxy board of 11.7 cm × 8.4 cm
*3 : Connection at exposure pad with thermal via. (Thermal via 9 holes)
*4 : Connection at exposure pad, without a thermal via.
Notes:
• The use of negative voltages below − 0.3 V to the AGND, DGND1, and DGND2 pin may create parasitic
transistors on LSI lines, which can cause abnormal operation.
• This device can be damaged if the LX1 pin and LX2 pin are short-circuited to AVDD and DVDD1/DVDD2,
or AGND and DGND1/DGND2.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VDD AVDD = DVDD1 = DVDD2 −0.3 +6.0 V
Signal input voltage VISIG OUT1/OUT2 pins −0.3 VDD + 0.3 V
CTLP, CTL1/CTL2,
MODE1/MODE2 pins
−0.3 VDD + 0.3
VREFIN1/VREFIN2 pins −0.3 VDD + 0.3
VDET pin −0.3 VDD + 0.3
XPOR pull-up voltage VIXPOR XPOR pin −0.3 +6.0 V
LX voltage VLX LX1/LX2 pins −0.3 VDD + 0.3 V
LX Peak current IPK ILX1/ILX2 – 1.8 A
Power dissipation PDTa ≤ +25 °C – 3125*1, *2, *3mW
– 1563*1, *2, *4
Ta = +85 °C – 1250*1, *2, *3mW
– 625*1, *2, *4
Operating ambient
temperature
Ta – −40 +85 °C
Storage temperature TSTG – −55 +125 °C
Document Number: 002-08364 Rev. *D Page 11 of 35
MB39C015
7. Recommended Operating Conditions
Note :
The output current from this device has a situation to decrease if the power supply voltage (VIN) and the DC/DC converter output
voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this device.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply voltage VDD AVDD = DVDD1 = DVDD2 2.5 3.7 5.5 V
VREFIN voltage VREFIN – 0.15 – 1.30 V
CTL voltage VCTL CTLP, CTL1, CTL2 0 – 5.0 V
LX current ILX ILX1/ILX2 – – 800 mA
VREF output current IROUT 2.5 V ≤ AVDD = DVDD1 = DVDD2 <
3.0 V
– – 0.5 mA
3.0 V ≤ AVDD = DVDD1 = DVDD2 ≤
5.5 V
– – 1
XPOR current IPOR – – – 1 mA
Inductor value L – – 2.2 – µH
Document Number: 002-08364 Rev. *D Page 12 of 35
MB39C015
8. Electrical Characteristics
(Ta = +25 °C , AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V)
* : Standard design value
Parameter Sym-
bol Pin No. Condition Value Unit
Min Typ Max
DC/DC
converter
block
Input current IREFIN 8, 23 VREFIN = 0.15 V to 1.3 V − 100 0 + 100 nA
Output voltage VOUT 10, 21 VREFIN = 0.833 V,
OUT = −100 mA
2.45 2.50 2.55 V
Input stability LINE 2.5 V ≤ AVDD = DVDD1 =
DVDD2 ≤ 5.5 V*1
– – 10 mV
Load stability LOAD −100 mA ≥ OUT ≥
−800 mA
– – 10 mV
OUT pin input
impedance
ROUT OUT = 2.0 V 0.6 1.0 1.5 MΩ
LX Peak current IPK 13, 18 Output shorted to GND 0.9 1.2 1.7 A
Oscillation
frequency
fosc – 1.6 2.0 2.4 MHz
Rise delay time tPG 2, 3,
10, 21
C1/C2 = 4.7 µF, OUT =
0 A, OUT1/OUT2 : 0 → 90%
VOUT
– 45 80 µs
SW NMOS-FET
OFF voltage
VNOFF 13, 18 – – − 10* – mV
SW PMOS-FET ON
resistance
RONP LX1/LX2 = −100 mA – 0.30 0.48 Ω
SW NMOS-F E T O N
resistance
RONN LX1/LX2 = −100 mA – 0.20 0.42 Ω
LX leak current ILEAKM 0 ≤ LX ≤ VDD*2 − 1.0 – + 8.0 µA
ILEAKH VDD = 5.5 V, 0 ≤ LX ≤ VDD*2 − 2.0 – + 16.0 µA
Protection
circuit block
Overheating
protection (Junction
Te mp.)
TOTPH – – + 120* + 135* + 160* °C
TOTPL + 95* + 110* + 125* °C
UVLO threshold
voltage
VTHHUV 5, 11,
12, 19, 20
– 2.17 2.30 2.43 V
VTHLUV 2.03 2.15 2.27 V
UVLO
hysteresis width
VHYSUV – 0.08 0.15 0.25 V
Voltage
detection
circuit block
XPOR threshold
voltage
VTHHPR 7 – 575 600 625 mV
VTHLPR 558 583 608 mV
XPOR
hysteresis width
VHYSPR – – 17 – mV
XPOR output
voltage
VOL 24 XPOR = 25 µA – – 0.1 V
XPOR output
current
IOH XPOR = 5.5 V – – 1.0 µA
Document Number: 002-08364 Rev. *D Page 13 of 35
MB39C015
(Ta = +25 °C , AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V)
*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher.
*2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.
*3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.
*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included
because the device is in full ON state (no switching operation). Also the load current is not included.
Parameter Symbol Pin No. Condition Value Unit
Min Typ Max
Control block
CTL threshold
voltage
VTHHCT 1, 2, 3 – 0.55 0.95 1.45 V
VTHLCT – 0.40 0.80 1.30 V
CTL pin
input current
IICTL 0 V ≤ CTLP/CTL1/CTL2 ≤
3.7 V
– – 1.0 µA
Reference
voltage block
VREF voltage VREF 6VREF = 0 mA 1.274 1.300 1.326 V
VREF Load
stability
LOADREF VREF = −1.0 mA – – 20 mV
General
Shut down
power supply
current
IVDD1
5, 11,
12, 19,
20
CTLP/CTL1/CTL2 = 0 V
State of all circuits OFF*3
– – 1.0 µA
IVDD1H CTLP/CTL1/CTL2 = 0 V,
VDD = 5.5 V
State of all circuits OFF*3
– – 1.0 µA
Power supply current
(DC/DC mode)
IVDD31 1. CTLP = 0 V, CTL1 = 3.7 V,
CTL2 = 0 V
2. CTLP = 0 V, CTL1 = 0 V,
CTL2 = 3.7 V
OUT = 0 A
– 3.5 10 mA
IVDD32 CTLP = 0 V, CTL1/CTL2 =
3.7 V, OUT = 0 A
– 7.0 20.0 mA
Power supply current
(voltage detection
mode)
IVDD5 CTLP = 3.7 V,
CTL1/CTL2 = 0 V,
– 15 24 µA
Power-on
invalid current
IVDD 1. CTL1 = 3.7 V, CTL2 = 0 V
2. CTL1 = 0 V, CTL2 = 3.7 V
VOUT1/VOUT2 = 90%
OUT = 0 A*4
– 1000 2000 µA
Document Number: 002-08364 Rev. *D Page 14 of 35
MB39C015
9. Test Circuit For Measuring Typical Operating Characteristics
Note : These components are recommended based on the operating tests authorized.
TDK : TDK Corporation
SSM : SUSUMU Co., Ltd
KOA : KOA Corporation
Component Specification Vendor Part Number Remarks
R1 1 MΩKOA RK73G1JTTD D 1 MΩ
R3-1
R3-2
20 kΩ
150 kΩ
SSM
SSM
RR0816-203-D
RR0816-154-D VOUT1/VOUT2 = 2.5 V
Setting
R4 300 kΩSSM RR0816-304-D
R5 510 kΩKOA RK73G1JTTD D 510 kΩ
R6 100 kΩSSM RR0816-104-D
C1 4.7 µF TDK C2012JB1A475K
C2 4.7 µF TDK C2012JB1A475K
C3 0.1 µF TDK C1608JB1E104K
C6 0.1 µF TDK C1608JB1H104K For adjusting slow start time
L1 2.2 µH TDK VLF4012AT-2R2M
VIN
VOUT1/
VOUT2
C1
4.7 μFI
OUT
C2
4.7 μF
SW CTL1/CTL2
MODE1/MODE2
VREF
VREFIN1/VREFIN2 AGND
OUT1/OUT2
AVDD
LX1/LX2
DVDD1/DVDD2
GND
R1
1 MΩ
V
DD
V
DD
MB39C015
DGND1/DGND2
VDET
R4
300 kΩ
R5
510 kΩ
R6
100 kΩ
C6
0.1 μF
C3
4.7 μF
R3-1
20 kΩ
R3-2
150 kΩ
L1
2.2 μH
Output voltage = VREFIN × 3.01
Document Number: 002-08364 Rev. *D Page 15 of 35
MB39C015
10. Application Notes
10.1 Selection of Components
■Selection of an External Inductor
Basically it dose not need to design inductor. This IC is designed to operate efficiently with a 2.2 µH inductor.
The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and
should have a minimal DC resistance. (100 mΩ or less is recommended.)
LX peak current value IPK is obtained by the following formula.
L : External inductor value
IOUT : Load current
VIN : Power supply voltage
VOUT : Output setting voltage
D : ON-duty to be switched ( = VOUT/VIN)
fosc : Switching frequency (2.0 MHz)
ex) When VIN = 3.7 V, VOUT = 2.5 V, IOUT = 0.8 A, L = 2.2 µH, fosc = 2.0 MHz
The maximum peak current value IPK;
■I/O Capacitor Selection
❐Select a low equivalent series resistance (ESR) for the VDD input capacitor to suppress dissipation from ripple currents.
❐Also select a low equivalent series resistance (ESR) for the output capacitor. The variation in the inductor current causes ripple
currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied by the
ESR value. The output capacitor value has a significant impact on the operating stability of the device when used as a DC/DC
converter. Therefore, Cypress generally recommends a 4.7 µF capacitor, or a larger capacitor value can be used if ripple voltages
are not suitable. If the VIN/VOUT voltage difference is within 0.6 V, the use of a 10 µF output capacitor value is recommended.
❐Types of capacitors
Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply functions
as a heat generator, therefore avoid to use capacitor with the F-temperature rating ( − 80% to + 20%).Cypress recommends
capacitors with the B-temperature rating ( ± 10% to ± 20%). Normal electrolytic capacitors are not recommended due to their
high ESR.Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when damaged.
If you insist on using a tantalum capacitor, Cypress recommends the type with an internal fuse.
IPK = IOUT + VIN − VOUT × D × 1 = IOUT + (VIN − VOUT) × VOUT
L fosc 2 2 × L × fosc × VIN
IPK = IOUT + (VIN − VOUT) × VOUT
= 0.8 A + (3.7 V − 2.5 V) × 2.5 V ≈ 0.89 A
2 × L × fosc × VIN 2 × 2.2 µH × 2.0 MHz × 3.7 V
Document Number: 002-08364 Rev. *D Page 16 of 35
MB39C015
10.2 Output Voltage Setting
The output voltage VOUT (VOUT1 or VOUT2) of this IC is defined by the voltage input to VREFIN (VREFIN1 or VREFIN2) . Supply the
voltage for inputting to VREFIN from an external power supply, or set the VREF output by dividing it with resistors.
The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is shown in the following formula.
Note :
Refer to “ Application Circuit Examples” for the an example of this circuit.
Although the output voltage is defined according to the dividing ratio of resistance, select the resistance value so that the current
flowing through the resistance does not exceed the VREF current rating (1 mA) .
10.3 About Conversion Efficiency
The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.
The total loss (PLOSS) of the DC/DC converter is roughly divided as follows :
PLOSS = PCONT + PSW + PC
PCONT : Control system circuit loss (The power used for this IC to operate, including the gate driving power for internal SW FETs)
PSW : Switching loss (The loss caused during switching of the IC's internal SW FETs)
PC : Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits )
VOUT = 3.01 × VREFIN, VREFIN = R2 × VREF
R1 + R2
(VREF = 1.30 V)
R2
R1
VREF
VREFIN
VREF
VREFIN
MB39C015
Document Number: 002-08364 Rev. *D Page 17 of 35
MB39C015
The IC's control circuit loss (PCONT) is extremely small, less than 100 mW (with no load).
As the IC contains FETs which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavy-
load operation than the control circuit loss (PCONT) and switching loss (PSW) .
Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series
resistance.
PC = IOUT2 × (RDC + D × RONP + (1 - D) × RONN)
D : Switching ON-duty cycle ( = VOUT / VIN)
RONP : Internal P-ch SW FET ON resistance
RONN : Internal N-ch SW FET ON resistance
RDC : External inductor series resistance
IOUT : Load current
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting
components.
10.4 Power Dissipation and Heat Considerations
The IC is so efficient that no consideration is required in most cases. However, if the IC is used at a low power supply voltage, heavy
load, high output voltage, or high temperature, it requires further consideration for higher efficiency.
The internal loss (P) is roughly obtained from the following formula :
P = IOUT2 × (D × RONP + (1 - D) × RONN)
D : Switching ON-duty cycle ( = VOUT / VIN)
RONP : Internal P-ch SW FET ON resistance
RONN : Internal N-ch SW FET ON resistance
IOUT : Output current
The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit
loss as well but they are so small compared to the continuity loss they can be ignored.
In this IC with RONP greater than RONN, the larger the on-duty cycle, the greater the loss.
When assuming VIN = 3.7 V, Ta = + 70 °C , for example, RONP = 0.36 Ω and RONN = 0.30 Ω according to the graph “MOS FET
ON resistance vs. Operating ambient temperature”. The IC's internal loss P is 123 mW at VOUT = 2.5 V and IOUT = 0.6 A. According
to the graph “Power dissipation vs. Operating ambient temperature”, the power dissipation at an operating ambient temperature Ta
of + 70 °C is 300 mW and the internal loss is smaller than the power dissipation.
Document Number: 002-08364 Rev. *D Page 18 of 35
MB39C015
10.5 XPOR Threshold Voltage Setting [VPORH, VPORL]
Set the detection voltage by applying voltage to the VDET pin via an external resistor calculated according to this formula.
VTHHPR = 0.600 V
VTHLPR = 0.583 V
Example for setting detection voltage to 3.7 V
R3 = 510 kΩ
R4 = 100 kΩ
VPORH = R3 + R4 × VTHHPR
R4
VPORL = R3 + R4 × VTHLPR
R4
VPORH = 510 kΩ + 100 kΩ
× 0.600 = 3.66 ≈ 3.7 [V]
100 kΩ
VPORL = 510 kΩ + 100 kΩ
× 0.583 = 3.56 ≈ 3.6 [V]
100 kΩ
R4
R3 1 MΩ
VIN
XPOR
AVDD
MB39C015
XPOR
VDET
Document Number: 002-08364 Rev. *D Page 19 of 35
MB39C015
10.6 Transient Response
Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and
overshoot/undershoot voltage is checked. As this IC has built-in Error Amp with an optimized design, it shows good transient response
characteristics. However, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor C6 (e.g.
0.1 µF). (Since this capacitor C6 changes the start time, check the start waveform as well.) This action is not required for DAC input.
R2
R1
VREF
VREFIN
VREF
VREFIN1/
VREFIN2
MB39C015
C6
Document Number: 002-08364 Rev. *D Page 20 of 35
MB39C015
10.7 Board Layout, Design Example
The board layout needs to be designed to ensure the stable operation of this IC.
Follow the procedure below for designing the layout.
• Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through hole (TH) near the pins
of this capacitor if the board has planes for power and GND.
• Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external inductor (L). Group
these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these
components on the same surface and arrange wiring without through hole wiring. Use thick, short, and straight routes to wire
the net (The layout by planes is recommended.).
• Arrange a bypass capacitor for AVDD as close as possible to both the AVDD and AGND pins. Make a through hole (TH) near
the pins of this capacitor if the board has planes for power and GND.
• The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (Co). The OUT pin
is extremely sensitive and should thus be kept wired away from the LX1 and pin LX2 pin of this IC as far as possible.
• If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the wiring can be kept
as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor is close to the IC's AGND pin.
Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current.
If installing a bypass capacitor for the VREFIN, put it close to the VREFIN pin.
• If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as
possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND pin. Further, provide a GND exclusively
for the control line so that the resistor can be connected via a path that does not carry current.
• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the QFN-24
package, Cypress recommends providing a thermal via in the footprint of the thermal pad.
■Example of Arranging IC SW System Parts
■Notes for Circuit Design
The switching operation of this IC works by monitoring and controlling the peak current which, incidentally, serves as a form of short-
circuit protection. However, do not leave the output short-circuited for long periods of time. If the output is short-circuited where VIN <
2.9 V, the current limit value (peak current to the inductor) tends to rise. Leaving in the short-circuit state, the temperature of this IC
will continue rising and activate the thermal protection.
Once the thermal protection stops the output, the temperature of the IC will go down and operation will be restarted, after which the
output will repeat the starting and stopping.
Although this effect will not destroy the IC, the thermal exposure to the IC over prolonged hours may affect the peripherals surrounding
it.
Cin VIN
GND
Cin
VIN
Co Co
GND VIN
1
pin
L
L
Feedback line Feedback line
AVDD bypass capacitor
Document Number: 002-08364 Rev. *D Page 21 of 35
MB39C015
11. Example Of Standard Operation Characteristics
(Shown below is an example of characteristics for connection according to “Test Circuit For Measuring Typical Operating
Characteristics”.)
■Characteristics CH1
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
Ta
= +
25
°C
V
OUT
=
1.2 V
VIN = 3.7 V
VIN = 3.0 V
VIN = 4.2 V
VIN = 5.0 V
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
VIN = 3.7 V
VIN = 4.2 V
VIN = 3.0 V
Ta
= +
25
°C
V
OUT
=
1.8 V
VIN = 5.0 V
0
10
20
30
40
50
60
70
80
90
100
1 10 100 100
0
Ta
= +
25
°C
V
OUT
=
3.3 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5.0 V
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
VIN = 3.7 V
VIN = 4.2 V
VIN = 3.0 V
Ta
= +
25
°C
V
OUT
=
2.5 V
VIN = 5.0 V
Load current IOUT (mA)
Conversion efficiency η (%)
Load current IOUT (mA)
Conversion efficiency η (%)
Load current IOUT (mA)
Conversion efficiency η (%)
Load current IOUT (mA)
Conversion efficiency η (%)
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current Conversion efficiency vs. Load current
Document Number: 002-08364 Rev. *D Page 22 of 35
MB39C015
2.40
2.0 3.0 4.0 5.0 6.0
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
I
OUT
=
0 A
I
OUT
=
100 mA
2.40
0 200 400 600 800
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
2.0 3.0 4.0 5.0 6.0
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
I
OUT
=
0 A
I
OUT
=
100 mA
V
OUT
=
2.5 V
Ta
= +
25
°C
−50 0 +50 +100
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
VOUT = 2.5 V
IOUT = 0 V
VIN = 3.7 V
Input voltage VIN (V)
Output voltage VOUT (V)
Load current IOUT (mA)
Output voltage VOUT (V)
Output voltage vs. Input voltage
Output voltage vs. Load current
Ta = +25 °C
VOUT = 2.5 V setting
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V setting
Reference voltage vs. Input voltage
Reference voltage VREF (V)
Reference voltage vs. Operating
ambient temperature
Reference voltage VREF (V)
Input voltage VIN (V) Operating ambient temperature Ta ( °C )
Document Number: 002-08364 Rev. *D Page 23 of 35
MB39C015
0
2.0 3.0 4.0 5.0 6.0
1
2
3
4
5
6
7
8
9
10
V
OUT
=
2.5 V
Ta
= +
25
°C
−
50 0+50 +100
0
1
2
3
4
5
6
7
8
9
10
V
OUT
=
2.5 V
V
IN
=
3.7 V
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.0 3.0 4.0 5.0 6.0
Ta = +25 °C
V
OUT
= 1.8 V
I
OUT
= 100 mA
1.6
1.8
1.7
1.9
2.0
2.1
2.2
2.3
2.4
−
50 0+50 +100
I
OUT
=
100 mA
V
OUT
=
2.5 V
V
IN
=
3.7 V
Input current vs. Operating ambient
temperature
Input current IIN (mA)
Input current vs. Input voltage
Input current IIN (mA)
Operating ambient temperature Ta ( °C )
Input voltage VIN (V)
Input voltage VIN (V)
Oscillation frequency fOSC (MHz)
Operating ambient temperature Ta ( °C )
Oscillation frequency fOSC (MHz)
Oscillation frequency vs. Input voltage Oscillation frequency vs. Operating
ambient temperature
Document Number: 002-08364 Rev. *D Page 24 of 35
MB39C015
2.0 3.0 4.0 5.0 6.0
0
0.1
0.2
0.3
0.4
0.5
0.6
Ta
= +
25
°C
P-ch
N-ch
−
50 0 +50 +100
0
0.1
0.2
0.3
0.4
0.5
0.6
VIN
=
3.7 V
VIN
=
5.5 V
−
50 0 +50 +100
0
0.1
0.2
0.3
0.4
0.5
0.6
V
IN
=
3.7 V
V
IN
=
5.5 V
Input voltage VIN (V)
MOS FET ON resistance RON (Ω)
Operating ambient temperature Ta ( °C )
P-ch MOS FET ON resistance RONP (Ω)
Operating ambient temperature Ta ( °C )
N-ch MOS FET ON resistance RONN (Ω)
MOS FET ON resistance vs.
Input voltage
P-ch MOS FET ON resistance vs.
Operating ambient temperature
N-ch MOS FET ON resistance vs.
Operating ambient temperature
Document Number: 002-08364 Rev. *D Page 25 of 35
MB39C015
2.0 3.0 4.0 5.0 6.0
0.0
0.4
0.2
0.6
0.8
1.0
1.2
1.4
Ta
= +
25
°C
V
OUT
=
2.5 V
V
THLCT
V
THHCT
0.0
1.0
2.0
3.0
4.0
5.0
6.0
2.0 3.0 4.0 5.0 6.0
Ta
= +
25
°C
VPORH = 3.7 V setting
V
XPORH
V
XPORL
−
50 0 +50
+85
+100
0
1000
500
1500 1250
3125
2000
2500
3000
3500
−
50 0 +50
+85
+100
0
1000
500
1500
625
1563
2000
2500
3000
3500
Operating ambient temperature Ta ( °C )
Power dissipation PD (mW)
Operating ambient temperature Ta ( °C )
Power dissipation PD (mW)
Power dissipation vs. Operating
ambient temperature
(with thermal via)
Power dissipation vs. Operating
ambient temperature
(without thermal via)
Input voltage VIN (V)
CTL threshold voltage VTH (V)
CTL threshold voltage VTH vs. Input voltage
VTHHCT : Circuit OFF → ON
VTHLCT : Circuit ON → OFF
Input voltage VIN (V)
XPOR output voltage VXPOR (V)
XPOR output voltage VXPOR vs. Input voltage
Document Number: 002-08364 Rev. *D Page 26 of 35
MB39C015
■Switching Waveforms
ILX : 500 mA/div
VLX : 2.0 V/div
VOUT : 20 mV/div
Ta = +25 °C
V
IN
= 3.7 V
V
OUT
= 2.5 V
I
OUT
= 800 mA
1 µs/div
Document Number: 002-08364 Rev. *D Page 27 of 35
MB39C015
■Startup Waveform
V
CTL
: 5.0 V/div
I
LX
: 500 mA/div
V
OUT
: 1.0 V/div
10 ms/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 A
VREFIN capacitor value =
0.1 µF
V
CTL
: 2.0 V/div
I
LX
: 500 mA/div
V
OUT
: 1.0 V/div
Ta = +25 °C
V
IN
= 3.7 V
V
OUT
= 2.5 V
I
OUT
= 0 A
10 μs/div
No VREFIN capacitor
Document Number: 002-08364 Rev. *D Page 28 of 35
MB39C015
■Output Waveforms at Sudden Load Changes (0 mA ↔ 800 mA)
■Output Waveforms at Sudden Load Changes (100 mA ↔ 800 mA)
V
OUT
: 100 mV/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5
V
IOUT = 0 mA IOUT = 0 mA
IOUT = 800 mA
10 μs/div
VREFIN capacitor value =
0.1 µF
Ta = +25 °C
VIN = 3.7 V
V
OUT
= 2.5
V
I
OUT
=
100 mA I
OUT
=
800 mA I
OUT
=
100 mA
V
OUT
:
100 mV/div
10
μs/div
VREFIN capacitor value =
0.1 µF
Document Number: 002-08364 Rev. *D Page 29 of 35
MB39C015
12. Application Circuit Examples
■Application Circuit Example 1
❐An external voltage is input to the reference voltage external input (VREFIN1, VREFIN2) , and the VOUT voltage is set to 3.01 times
the VOUT setting gain.
VIN
CPU
VOUT1
DAC1
L1
2.2 μH
L2
2.2 μH
4.7 μF
C1
4.7 μF
C2
MB39C015
C3
4.7 μF
4.7 μF
CTL1
MODE1
VREFIN1
OUT1
XPOR
LX1
DVDD1
R8
1 MΩ
R7
1 MΩ
CTL2
MODE2
VREF
VREFIN2
VDET
CTLP
DVDD2
DGND1
DGND2
C4
0.1 μF
C5
AVDD
AGND
OUT2
LX2
DAC2
APLI2
VOUT2
VOUT = 3.01 × VREFIN
3
8
2
23
9
22
6
7
124
21
18
10
13
4
5
16
17
19
20
14
15
11
12
APLI1
Document Number: 002-08364 Rev. *D Page 30 of 35
MB39C015
■Application Circuit Example 2
❐The voltage of VREF pin is input to the reference voltage external input (VREFIN1, VREFIN2) by dividing resistors. The VOUT1
voltage is set to 2.5 V and VOUT2 voltage is set to 1.8 V.
R8
1 MΩ
R6
300 kΩ
R2
R5
( 22 kΩ + 330 kΩ )
352 kΩ
R1
( 20 kΩ + 150 kΩ )
170 kΩ
300 kΩ
R7
1 MΩ
CPU
MB39C015
CTL1
VREF
VREFIN1
CTL2
MODE2
MODE1
VREFIN2
CTLP
3
8
2
23
6
9
22
1
VIN
C3
4.7 μF
4.7 μF
DVDD1
DVDD2
DGND1
DGND2
C4
0.1 μF
C5
AVDD
AGND 4
5
16
17
19
20
14
15
11
12
OUT1
XPOR
LX1
OUT2
LX2
VOUT1
L1
2.2 μH
L2
2.2 μH
4.7 μF
C1
4.7 μF
C2
APLI2
VOUT2
24
21
18
10
13
APLI1
VOUT1 = 3.01 × VREFIN1
(VREF = 1.30 V)
× VREFVREFIN1 = R2
R1 + R2
× 1.30 V = 2.5 VVOUT1 = 3.01 × 300 kΩ
170 kΩ + 300 kΩ
× 1.30 V = 1.8 VVOUT12 = 3.01 ×300 kΩ
352 kΩ + 300 kΩ
Document Number: 002-08364 Rev. *D Page 31 of 35
MB39C015
■Application Circuit Example Components List
TDK : TDK Corporation
FDK : FDK Corporation
KOA : KOA Corporation
Component Item Part Number Specification Package Vendor
L1 Inductor VLF4012AT-2R2M 2.2 µH, RDC = 76 mΩSMD TDK
MIPW3226D2R2M 2.2 µH, RDC = 100 mΩSMD FDK
L2 Inductor VLF4012AT-2R2M 2.2 µH, RDC = 76 mΩSMD TDK
MIPW3226D2R2M 2.2 µH, RDC = 100 mΩSMD FDK
C1 Ceramic capacitor C2012JB1A475K 4.7 µF (10 V) 2012 TDK
C2 Ceramic capacitor C2012JB1A475K 4.7 µF (10 V) 2012 TDK
C3 Ceramic capacitor C2012JB1A475K 4.7 µF (10 V) 2012 TDK
C4 Ceramic capacitor C2012JB1A475K 4.7 µF (10 V) 2012 TDK
C5 Ceramic capacitor C1608JB1E104K 0.1 µF (50 V) 2012 TDK
R1 Resistor RK73G1JTTD D 20 kΩ
RK73G1JTTD D 150 kΩ
20 kΩ
150 kΩ
1608
1608
KOA
KOA
R2 Resistor RK73G1JTTD D 300 kΩ300 kΩ1608 KOA
R5 Resistor RK73G1JTTD D 22 kΩ
RK73G1JTTD D 330 kΩ
22 kΩ
330 kΩ
1608
1608
KOA
KOA
R6 Resistor RK73G1JTTD D 300 kΩ300 kΩ1608 KOA
R7 Resistor RK73G1JTTD D 1 MΩ1 MΩ ± 0.5% 1608 KOA
R8 Resistor RK73G1JTTD D 1 MΩ 1 MΩ ± 0.5% 1608 KOA
Document Number: 002-08364 Rev. *D Page 32 of 35
MB39C015
13. Usage Precautions
1. Do not Configure the IC Over the Maximum Ratings
If the lC is used over the maximum ratings, the LSl may be permanently damaged.It is preferable for the device to normally operate
within the recommended usage conditions. Usage outside of these conditions adversely affect the reliability of the LSI.
2. Use the Devices Within Recommended Operating Conditions
The recommended operating conditions are the conditions under which the LSl is guaranteed to operate.The electrical ratings are
guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item.
3. Printed Circuit Board Ground Lines Should be Set up With Consideration for Common Impedance
4. Take Appropriate Static Electricity Measures
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
5. Do not Apply Negative Voltages
The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation.
14. Ordering Information
15. RoHS Compliance Information
The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury,
hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE).
A product whose part number has trailing characters “E1” is RoHS compliant.
Part Number Package Remarks
MB39C015WQN 24-pin plastic QFN
(WNN024) Exposed PAD
Document Number: 002-08364 Rev. *D Page 33 of 35
MB39C015
16. Package Dimension
DIMENSIONS
NOM.MIN.
b
E
2.60 BSC
4.00 BSC
D
A
1
A
4.00 BSC
0.00
SYMBOL
MAX.
0.80
0.05
0.50 BSC
L
0.20 0.25 0.30
E
D2
22.60 BSC
e
c0.35 REF
0.400.35 0.45
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
NOTE
10. JEDEC SPECIFICATION NO. REF : N/A
SIDE VIEW
BOTTOM VIEW
TOP VIEW
DA
E
B
0.10 C
2X
0.20 C
A
A1
0.05 C
C
SEATING PLANE
D2
E2
0.15 C A B
0.15 C A B
1
eb0.05 C A B
0.20 C
(ND-1)× e
INDEX MARK
8
4
5
9
L
9
0.10 C
2X
6
7
12
1813
24
19
Package Code: WNN024
002-15158 Rev. **
Document Number: 002-08364 Rev. *D Page 34 of 35
MB39C015
Document History
Document Title: MB39C015 2 ch DC/DC Converter IC with PFM/PWM Synchronous Rectification
Document Number: 002-08364
Revision ECN Orig. of
Change
Submission
Date Description of Change
** – TAOA 07/16/2008 Initial release
*A 5148534 TAOA 03/01/2016 Migrated Spansion Datasheet from DS04-27254-3E to Cypress format
*B 5633427 HIXT 02/17/2019
Updated Pin Assignment:
Change the package name from LCC-24P-M10 to WNN024
Updated Ordering Information:
Change the package name from LCC-24P-M10 to WNN024
Deleted “Marking Format (Lead Free Version)”
Deleted “Labeling Sample (Lead Free Version)”
Deleted “Evaluation Board Specification”
Deleted “EV Board Ordering Information”
Updated Package Dimension: Updated to Cypress format
*C 5763669 MASG 06/06/2017 Adapted Cypress new logo.
*D 6405849 YOST 12/10/2018 Obsoleted.
Document Number: 002-08364 Rev. *D Revised December 10, 2018 Page 35 of 35
© Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
MB39C015
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