16-bit FCT - Cypress Semiconductor

16 -bi t FCT w ith Balan ced Driv e

Cypress Semiconductor Corporation • 3 9 01 North First Stre et • Sa n Jo se • CA 95134 • 408-943-2600

September 1996

Cyp ress 16 -bit FCT Logi c P roducts Feature Balanced D rive

Introduction

This application note answers the basic questions about bal-

anced drive. Namely; what is it, which Cypress FCT products

have it, why have it and what benefits do es it provide to the

user, how is it specified, and how is it measured?

What i s Bal an ced Dri ve?

Balanced drive refers to the design of the output buffer such

that the current that the device sources or sinks are approxi-

mately equal. This implies that the source impedance (to VCC,

as well as to ground) is the same for a LOW to HIGH, or a

HIGH to LOW transition of the output. They could just as well

be called “balanced output impedance” devices.

Which 16-bit FCT Products Have It?

The Cypress FCT prod ucts that have ba lanced drive have the

number “2” following the number “16” in their part number.

They are ei ther of the f orm CY74FCT 162XXXT or o f the form

CY74FCT162HXXXT, where the “H” designates Bus Hold,

and XXX the industry standard logic function.

Balanced Drive Products; 14 Functions

The balanced drive products are, 240, 244, 245, 373, 374,

500, 501, 543, 646, 652, 823, 827, 841, and 952.

Balanced Drive with Bus Hold; 4 Function s

The balanced drive products with bus hold are 244, 245, 501,

and 952.

Why Have Balanced Drive?

In three words; to reduce noise.

The balanced drive output structure is designed to, (1) pro-

vide matched rise and fall times with edge rate control, (2)

present a constant source impedance of approximately 25

Ohms, (3) source or sink up to 60 mA of dynamic current, and

(4) source or sink a m inimum of 24 mA of s tatic current. Each

item will be discussed in d etail.

Matched Output Rise and Fall Times of

Approximately One Nanosecond

The controll ed edge rates over a lar ge range of load capaci-

tance (up to 300 pF) result in the generation of predictable

harmonics (noise), which can be filtered out by using the

proper high-frequency filter capacitor between VCC and

ground. This is in addition to any decouplin g capacitor.

When a Fourier analysis is performed on a train of pulses,

noise is generated at frequencies of one over Pi times the

period, one over Pi times the pulse width, and one over Pi

times the rise time. For rise times of one nanosecond, the

corresponding (highest ) frequency is 320 MHz. For this rea-

son, 100-pF to 500-pF chipcaps, w hose series resonant fre-

quency is greater than 320 MHz, are recommended to be

connected between VCC and ground.

Controlled e dge rates also reduce EMI and RFI emissions.

The one nanosecond (unloaded) rise and fall times of the

outputs mean that for strip line construction on G10 glass

epoxy PCBs, whose intrinsic characteristic impedance is ap-

proximately 50 Ohms, a tra ce whose length is ov er approxi-

mately two inches is a transmission line. A ramification of this

is that if high drive FCT products drive the line, it must be

terminated. However, if balanced drive FCT products drive

the line, they (internally) provide the termination and termina-

tion is not required at the load. Thus, the user saves the cost

of termination circuits, as well as the PCB area required to

mount them.

Constant Source Impedance

The constant source impedance insures that the reflection

coefficient betw een the line and the source will be the same

for either a LOW to HIGH or a HIGH to LOW output signal

transition.

A 25-Ohm source impedance will cause all but the most

heav ily lo aded lines to be “overdamped,” which will cause the

energy reflected back from the load to be absorbed by the

source. Thus, the ba lanced drive reduces noise by absorbing

reflected energy, b ut without the disa dvantage of the half-volt-

age level along the line that would occur if an external series

damping resistor were used.

Balanced drive FCT is recommended fo r all app lications with

the exception of heavily loaded (over 300 pF) backplanes.

The relatively low source impedance of 25 Ohms means a

smaller RC time constant for the rise time and the fall time at

the load, thus eliminati ng duty cy cl e degradati on and asym-

metry problems.

Dynamic Current

The balanced drive outputs are designed and guaranteed to

source or sink a minimum of 60 mA at 1.5V. Actually, the

specification should be 60 mA at the minimum TTL logical

one voltage level, which is two Volts. As will be shown, this

amount of instantaneous current is suf ficient to cause incident

wave switching in all but the most heavily loaded backplanes.

Dynamic Current Calculation VMEbus Example

For example, the VMEbus specifies a maximum I/O c apaci-

tance per slot of 20 pF. For a fully loaded backplane, con-

structed of m ulti- layer G10 glass epoxy, what instantaneous

current must the drivers be capable of supplying?

The assumptions are that the intr i n sic (unloaded) character-

istic i mpedance is 50 Ohms a nd the dielectric constant of the

G10 is 5 . The VMEbu s bac kplane leng th is 1 9 inches and the

maximum number of slots is 20. T he procedure is to list the

applicable equations, calculate the loaded line impedance,

and then calculate the inst antaneous curr ent by dividin g 2V

by the loaded line impedance.

The propagation delay of the line is given by t he formula:

Eq. 1

Tpd 1.017 εr

=nsft

⁄[]

16-bit FCT with Balanced Drive

Where Epsilon is the dielec tric constan t. For G10 glass epoxy

the propagation delay is 2.27ns per foot .

From transmission line theory , for a lossless line, the following

equations apply

Eq. 2

Eq. 3

Where L and C are the inductance and capacitance of the

line, per unit length. Finall y, the relatio nship between the in-

trinsi c line characteristic impedance, ZO, and the loaded line

impedance, ZOL is

Eq. 4

Where ZO is the intrinsic characteristic impedance, CD is the

sum of the lumped loads, l is the line length, and C is the

intrinsic line capacitance per unit length.

Solving Equation 4 for C yields

Su bstitutio n of Tpd = 2.27 ns/ft and Zo = 50 Ohms yields C =

45.4 pF/ft.

Substitution into Equation 3, with CD = 400p F, yield s a loade d

impedance of 19.51 Ohms. The instantaneous current re-

quired is i = 2V/19.51 = 100 mA.

Th e conc lu sion is that balanced drive devices cann ot be use d

to drive a fully loaded VMEbus.

The next logical questi on to be asked is, un der w hat lo adi ng

and line length conditions can balanced drive FCT be used?

Dynamic Current Limi t Conditions

The procedure is to reverse the preceding sequence of cal-

culations and det ermine the relati o nship between l ine length

and load that must be satisfied in order to reliably use bal-

anced drive devices. Solving Equati on 4 for

yields.

The operating conditions are;

ZO = 50 Ohms

ZOL = 2V/60mA = 33.3 Ohms

C = 3.78 pF/inch (equivalent to 45.4pF/ft.)

If the maximum instantaneous cu rrent is limited to 60 mA, the

loaded line impedance must limited t o a minimum of 2V/ 60

mA = 33.3 Ohms.

Substitution of these values yields;

Eq. 5

where CD is in pF and l i s in inches.

This equation is of the form XY = K, which is an equilateral

hyperbola. Where X = CD, and Y = 1/l The “negativ e values”

of X and Y (i.e., those in the third quadrant) have no physical

meaning, but those in the first quadrant represent, in this

case, the loci of all com binat ions of one over l and C D, such

that the loaded lin e impedance (of a 50 Ohm intrinsic line) is

33.3 Ohms. In other words, the curve illustrated in

Figure 1

re presents a constant 33.3 Ohm (minimum) lin e impedance.

Equation 5 is r ewri tten a s and plotted in

Figure 2

. The VME-

bus example is shown f or referenc e. Note how far outside the

balanced drive operating region it is. Analysis of Equation 4

reveals that as the line becomes longer, the loaded line im-

pedance approaches the intrinsic line characteristic imped-

ance . The line in

Figure 2

represents the minimum line length

for a given total lumped capacitance that results i n a lo aded

line impedance of 33.3 Ohms. All points to the left of the line

have load ed line impedances greater than 33.3 Ohms, which

balance d drive FCT can drive. All points to the right of the line

have lower impedances, which balanced drive FCT cannot

drive.

As a r ule of t humb, the input capacitance of each CMOS de-

vice is 10 pF. For example, if we are driving four loads, the

total capac itance i s 40 p F, and the minimum line length is .021

x 40 = 8.4 inches. It i s, perhaps, counter intui tive to increase

the line length, b ut in s ome cases i t must be don e to in crease

the loaded l ine im pedance. The person performi ng the PCB

layout m ust be aware of this.

ZoL

----

=Ohms[]

pd LC ZoC== nsft⁄[]

OL ZO

1CD

--------+

----------------------=Ohms[]

---------=

--------

-------- Zo

ZOL

---------- 21–=Ohms[] Figure 1. Balanced Drive Hyperbola

-------- 4.73=

1/l

ZOL = 33.3 Ω

operating region

l = K

16-bit FCT with Balanced Drive

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze

its product s for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Conditi ons for A Transmission Line

For a trace on a PCB or m odule to be a transmission line it

must be “long.” The definition of a long line is any line whose

leng th is greater than (or equa l to) the rise t ime divided by two

times the one way propagation delay per unit length of the

line. In equation form;

Eq. 6

The loaded propagat ion delay of the line is increased by the

same factor that the unloaded characteristic impedance is

decreased by. In equation form;

Eq. 7

It is good practice t o calculate the loaded propagation d elay

and to check t hat the line i s long, using Equati on 6.

Static Current

Static currents are guaranteed by the d ata sheet and are test-

ed, on a production basis, on each and every output of every

device manufactured b y Cypress. In m ost ap plications, FCT

outputs are either driving other FCT or CMOS inputs. If this is

the case, there is no appreciable static current. The only static

current is leakage current, which is guaranteed to be less

than one microampere, and is typically in the tens of nanoam-

pe res .

Howe ver , for those applications that require a guaranteed

minimum static cu rrent, Cypress guarantee s that the outputs

will sink a nd sour ce a minimum of 24 mA of st atic curr ent at

low VCC (4.5V). This tr anslates to 26.67 m A at Vcc=5V.

An example of an application wh ere static current mat ters is

illustrated in

Figure 3

. The pull-up/pulldown termination is

usually used for terminating clock lines, because it causes

less signal duty cycle distortion than either series termination

or AC termination.

Its disadvantage is that it has DC power dissip ation, and that

the driver must sink an amount of DC current equal to (VCC -

VOL)/R1 and source an amount of suf ficient to reach the min-

imum HIGH TTL level (2V) at th e junction of R1 and R2.

50 Ohm Line Calculations

For proper termination, R1=2Zo and R2= 2Zo. If Zo=50

Ohms, R1=R2=100 Ohms. However , the current that the driv-

er must sink is 5V-0.55V/100=40 mA, which is greater than

the 24 mA specification. The current that the driver must sup-

ply (source) is 2V/100=20 mA, which is within the 24 mA

specification. The conclusion is that balance d dr ive FCT ca n-

not drive 50 Ohm transmission lines with pull-up/pull-down

resistive terminations.

However , ad ding a small capacitor (22 -pF) in se ries with each

resistor converts the termination to an AC termination, and

there is no DC power dissipation.

100 Ohm Line Calculations

For a ZO= 100 Ohms, R1=R2=200 Ohms. The current that

the driver must sink is 20 mA, so the balan ced drive FCT can

drive 100 Ohm transmission lines.

Output Source Current Test

The output i s conditioned to be in the HIGH state, a voltage

of 2.4V i s applied to the output, and a minimum current of 24

mA is pulled out of the lead.

Output Sink Current Test

The output is conditioned to be in the LOW state, and a cur-

rent source of 24 mA is applied to the lead, and a ma ximum

voltage of 0.55V is measured between the le ad and ground.

Figure 2. Balanced Dri ve Hyper bola

l = 0.21 C D

inches

CDinpF

00 100 200 300 400 500

100

operating region

+VMEbus

ZOL =33.3Ω

Balanced Drive

operating region

High Drive

ZOL = 19.51

ltr

2Tpdl

-------------->

Tpd Tpd 1CD

--------+=

Figure 3. Pull;-up/Pull-down Terminated Line

VCC

ZOR1