Data Book The Programmable Logic Data Book Success made simple Click anywhere on this page to continue 1996 On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in Xilinx products and services. As the inventor of Field Programmable Gate Array technology and the world's leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you, our users, with the best possible integrated circuit components, development systems, and technical and sales support. Over the past year, we have substantially broadened our product line with the introduction of the XC4000E, XC4000EX, XC5000, XC6000, and XC8000 series of FPGAs and the XC9500 family of CPLDs. The recently-introduced XACTstep v6 and Foundation series products have set a new standard for functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation to continue, and even increase, as we maintain our leadership role in bringing leading-edge programmable logic solutions to the market. We look forward to satisfying all of your programmable logic needs. Sincerely, Wim Roelandts Chief Executive Officer Data Book Contents Table of Contents Introduction Development System Products CPLD Products (XC9500, XC7300, XC7200) SRAM-Based FPGA Products (XC4000, XC5200, XC6200, XC3000) OTP FPGA Products (XC8100) SPROM Products (XC1700) 3V Products HardWire Products Military Products Programming Support Packages and Thermal Characteristics Testing, Quality, and Reliability Technical Support Product Technical Information (Application Notes) Sales Offices, Sales Representatives, and Distributors Index R The Programmable Logic Data Book Technical Support Telephone Hotline: 1-800-255-7778 (North America) 1-408-879-5199 (USA, Xilinx headquarters) (44) 1932 820821 (United Kingdom) (33) 1 3463 0100 (France) (49) 89 991 54930 (Germany) (81) 3-3297-9163 (Japan) Technical Support Direct FAX: 1-408-879-4442 (USA, Xilinx headquarters) (44) 1932 828522 (United Kingdom) (33) 1 3463 0959 (France) (49) 89 904 4748 (Germany) (81) 3-3297-0067 (Japan) Technical Support Hotline E-mail: Xilinx BBS: XDOCS E-mail Document Server: XFACTS Automated FAX Server: Xilinx Home Page (WWW): hotline@xilinx.com (USA, Xilinx headquarters) ukhelp@xilinx.com (United Kingdom) frhelp@xilinx.com (France) dlhelp@xilinx.com (Germany) jhotline@xilinx.com (Japan) 1-408-559-9327 (USA, Xilinx headquarters) (44) 1932 333540 (United Kingdom) 8 data bits, no parity, 1 stop xdocs@xilinx.com send E-mail with help in the header 1-408-879-4400 http://www.xilinx.com/ 2100 Logic Drive San Jose, California 95124 United States of America Telephone: (408) 559-7778 Fax: (408) 559-7114 R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire, LCA, Logic Cell, LogiCore, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM, SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx devices and products are protected under one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363, RE 34,444, and RE 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. Copyright 1996 Xilinx, Inc. All Rights Reserved. 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Section Titles 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Table of Contents Introduction An Introduction to Xilinx Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Development System Products Development Systems Products Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Bundled Packages Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Individual Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 CPLD Products XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 In-System Programmable CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 XC95180 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 XC95432 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 XC95576 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 XC7300 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 XC7300 CMOS CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 XC7318 18-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81 XC7336/XC7336Q 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 XC7354 54-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 XC7372 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107 XC73108 108-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 XC73144 144-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 XC7300 Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135 XC7200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145 XC7236A 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147 XC7272A 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163 SRAM-Based FPGA Products XC4000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 XC5200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-179 XC5200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181 XC5200L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249 XC6200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251 XC6200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253 XC3000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287 XC3000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289 XC3000A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341 XC3000L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349 XC3100A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357 XC3100L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365 OTP FPGA Products XC8100 FPGA Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 SPROM Products XC1700D Family of Serial Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 3V Products 3.3 V and Mixed Voltage Compatible Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 HardWire Products Xilinx HardWireTM Array Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Military Products High-Reliability and Military Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Programming Support HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Packages and Thermal Characteristics Packages and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Testing, Quality, and Reliability Quality Assurance and Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Technical Support Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Product Technical Information Product Technical Information Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . . . . . . 14-35 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45 Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47 Boundary Scan in XC4000 and XC5000 Series Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Sales Offices, Sales Representatives, and Distributors Sales Offices, Sales Representatives, and Distributors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Table of Contents Introduction An Introduction to Xilinx Products About this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic vs. Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shortest Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Programmable Logic Devices (CPLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2 1-3 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-5 1-5 1-5 1-5 Development System Products Development Systems Products Overview XACTstep: Accelerating Your Productivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Six Powerful New Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Xilinx Design Manager--Simplifies the Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Flow Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extensive On-line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Software on CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support and Update Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Product Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Online Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support Hotline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Technical Bulletin Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Support FAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internet Electronic Mail Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Series Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Easy to Learn and Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABEL-HDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-3 2-3 2-4 2-5 2-5 2-5 2-5 2-6 2-6 2-6 2-6 2-6 2-6 2-7 2-7 2-7 1 Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Migration Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Series 8000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Individual Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-7 2-7 2-8 2-8 2-9 Development Systems: Bundled Packages Product Descriptions Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base System with VHDL Synthesis (PC) . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Standard System with VHDL (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: OrCAD - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: OrCAD - Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Extended System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Mentor V8 - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Synopsys - Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Cadence - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Third Party Alliance - Standard System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 Development Systems: Individual Product Descriptions FPGA Core Implementation - DS-502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPLD Core Implementation - DS-560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic and Simulator Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-BLOX - DS-380. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx ABEL Design Entry - DS-371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx ABEL Design Entry - DS-571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx-Synopsys Interface (XSI) - DS-401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XChecker Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demonstration Board - FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2-31 2-32 2-32 2-33 2-34 2-35 2-36 2-36 CPLD Products XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastCONNECT Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3-3 3-3 3-3 3-5 3-6 3-8 3-11 3-12 3-13 3-14 3-14 IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstepTM Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-14 3-15 3-15 3-16 3-16 3-16 XC9536 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-17 3-17 3-19 3-19 3-19 3-20 3-21 3-21 3-22 3-22 XC9572 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3-23 3-23 3-25 3-26 XC95108 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3-27 3-27 3-29 3-29 3-29 3-30 3-31 3-32 3-32 3-33 3-33 XC95144 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-35 3-35 3-37 3-38 3-39 XC95180 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95180 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3-41 3-41 3-43 3 XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95180 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3-47 3-47 3-49 3-49 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-55 XC95288 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 3-57 3-57 3-59 3-60 3-61 3-62 3-63 XC95432 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 XC95576 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 XC7300 Series Table of Contents XC7300 CMOS CPLD Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared and Private Product Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Lookahead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V or 5 V Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Characteristics/Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erasure Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3-71 3-71 3-72 3-74 3-74 3-74 3-74 3-75 3-75 3-76 3-76 3-77 3-77 3-77 3-77 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Volume Production Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstep Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 3-78 3-78 3-78 3-78 3-79 3-80 3-80 XC7318 18-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7318 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81 3-81 3-82 3-82 3-82 3-83 3-83 3-84 3-85 3-85 3-85 3-86 3-86 3-87 3-87 3-88 3-88 XC7336/XC7336Q 36-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7336 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 3-89 3-90 3-90 3-90 3-91 3-91 3-92 3-93 3-94 3-94 3-95 3-95 3-96 3-96 3-97 3-97 XC7354 54-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 3-99 3-99 3-101 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7354 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101 3-101 3-102 3-102 3-102 3-103 3-103 3-104 3-104 3-105 3-106 3-106 XC7372 72-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107 3-107 3-107 3-109 3-109 3-109 3-110 3-110 3-110 3-111 3-111 3-112 3-112 3-113 3-114 3-114 XC73108 108-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73108 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73108 Pinouts (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 3-115 3-115 3-117 3-117 3-117 3-118 3-118 3-118 3-119 3-119 3-120 3-120 3-121 3-122 3-123 3-123 XC73144 144-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate and Programmable Ground Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73144 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73144 Pinouts (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 3-125 3-127 3-127 3-127 3-128 3-128 3-128 3-129 3-129 3-130 3-130 3-131 3-132 3-133 3-134 3-134 XC7300 Characterization Data XC7200 Series Table of Contents XC7236A 36-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FBs and macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V or 5 V Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming and Using the XC7236A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147 3-147 3-147 3-148 3-149 3-150 3-150 3-150 3-151 3-152 3-152 3-152 3-153 3-154 3-154 3-155 3-156 3-156 3-161 3-162 3-162 XC7272A 72-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Blocks and Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163 3-163 3-163 3-165 3-166 3-167 3-167 7 Programming and Using the XC7272A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167 3-168 3-168 3-168 3-169 3-170 3-170 3-171 3-172 3-172 3-177 3-178 3-178 SRAM-Based FPGA Products XC4000 Series Table of Contents XC4000 Series Field Programmable Gate Arrays XC4000-Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4000EX/XL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E and XC4000EX Families Compared to the XC4000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in XC4000E and XC4000EX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Improvements in XC4000EX Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Function Generators as RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4-5 4-5 4-5 4-5 4-6 4-7 4-8 4-8 4-9 4-11 4-11 4-11 4-11 4-12 4-12 4-12 4-13 4-13 4-13 4-13 4-13 4-13 4-14 4-21 4-24 4-24 4-27 4-29 4-29 4-30 4-30 4-31 4-31 4-32 4-32 CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Lines (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal I/O Routing (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of Global Set/Reset After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4-35 4-35 4-35 4-36 4-37 4-37 4-38 4-40 4-41 4-41 4-43 4-46 4-46 4-50 4-50 4-50 4-53 4-53 4-53 4-54 4-54 4-54 4-54 4-54 4-55 4-55 4-56 4-56 4-57 4-59 4-59 4-59 4-60 4-60 4-60 4-62 4-63 4-63 4-63 4-64 4-64 4-65 4-65 4-65 4-65 4-65 4-65 4-66 4-66 4-68 4-70 4-72 4-74 4-74 4-74 9 Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76 Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79 Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79 Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79 XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 XC4000E Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81 XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81 XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . 4-83 XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84 XC4000E CLB Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . 4-85 XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines . . . . 4-86 XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines 4-87 XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . 4-88 XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89 XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs). . . . . . . . . . . . . . 4-90 XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs) . . . . . . . . . . . 4-91 XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92 XC4000E IOB Input Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . 4-93 XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94 XC4000E IOB Output Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . 4-95 XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . 4-96 XC4000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96 XC4000EX Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96 XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96 Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97 Pin Locations for XC4003E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97 Pin Locations for XC4005E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98 Pin Locations for XC4006E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100 Pin Locations for XC4008E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-102 Pin Locations for XC4010E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104 Pin Locations for XC4013E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107 Pin Locations for XC4020E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110 Pin Locations for XC4036EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-118 Pin Locations for XC4044EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-123 Pin Locations for XC4052XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-128 Package-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133 PC84 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133 PQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134 VQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-135 PG120 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136 TQ144 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-138 PG156 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-140 PQ160 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-142 TQ176 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144 PG191 Package Pinouts (see PG223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-145 PG223 and PG191 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-149 BG225 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152 PQ240, HQ240 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154 PG299 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-157 HQ304 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-160 BG352 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163 PG411 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-166 10 BG432 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-170 4-174 4-176 4-178 XC5200 Series Table of Contents XC5200 Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Family Compared to XC4000 and XC3000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block (CLB) Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Block (IOB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock: Abundant Local Routing Plus Versatile Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reset (GR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single- and Double-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unrestricted User-Programmable I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181 4-181 4-182 4-182 4-183 4-183 4-183 4-184 4-184 4-185 4-185 4-185 4-186 4-186 4-187 4-187 4-188 4-188 4-188 4-189 4-190 4-191 4-191 4-191 4-191 4-192 4-192 4-192 4-194 4-194 4-194 4-194 4-196 4-196 4-197 4-197 4-197 4-198 4-199 4-199 4-199 4-199 4-199 4-199 4-200 4-200 4-203 11 Power-On Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . XC5200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 CLB-to-Pad Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5202 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5204 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5206 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5210 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5215 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203 4-203 4-203 4-203 4-204 4-205 4-205 4-205 4-206 4-206 4-206 4-206 4-207 4-207 4-208 4-209 4-210 4-211 4-212 4-223 4-223 4-226 4-230 4-235 4-241 4-248 4-248 4-248 XC5200L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249 4-249 4-250 4-250 4-250 4-250 XC6200 Series Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253 XC6200 Field Programmable Gate Arrays Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical and Physical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cells, Blocks and Tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magic Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4-254 4-254 4-254 4-254 4-256 4-257 4-257 4-257 4-258 4-259 4-261 4-261 Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Design with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Map Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wildcard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Power-on/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Serial Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Cell Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . XC6200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Internal Routing Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - West Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - South Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - East Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - North Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261 4-263 4-265 4-265 4-265 4-267 4-267 4-268 4-268 4-268 4-268 4-270 4-271 4-272 4-273 4-274 4-275 4-275 4-275 4-275 4-276 4-276 4-276 4-276 4-277 4-277 4-278 4-278 4-282 4-282 4-283 4-284 4-285 4-286 XC3000 Series Table of Contents XC3000 Series Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of I/O Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289 4-289 4-290 4-291 4-291 4-292 4-293 4-294 4-295 4-296 4-296 4-300 4-302 4-303 4-304 4-304 4-306 13 Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Configuration Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Spike Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Readback Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General XC3000 Series Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unrestricted User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 44-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 64-Pin Plastic VQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 100-Pin QFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 144-Pin Plastic TQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 160-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 176-Pin TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 208-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3195A PQ208 and PG223 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307 4-307 4-307 4-307 4-307 4-308 4-308 4-308 4-308 4-308 4-308 4-309 4-309 4-309 4-309 4-309 4-310 4-310 4-312 4-314 4-316 4-318 4-319 4-320 4-321 4-321 4-322 4-322 4-323 4-323 4-323 4-324 4-325 4-326 4-327 4-328 4-329 4-330 4-331 4-332 4-333 4-334 4-335 4-336 4-337 4-338 4-339 4-340 XC3000A Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4-341 4-341 4-342 4-342 4-342 XC3000A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A CLB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . XC3000A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-343 4-343 4-344 4-345 4-346 4-347 4-348 4-348 XC3000L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L CLB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . XC3000L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349 4-349 4-350 4-350 4-350 4-351 4-351 4-352 4-353 4-354 4-355 4-356 4-356 XC3100A Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A CLB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . XC3100A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357 4-357 4-358 4-358 4-358 4-359 4-359 4-360 4-361 4-362 4-363 4-364 4-364 XC3100L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L CLB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . XC3100L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365 4-365 4-366 4-366 4-366 4-367 4-367 4-368 4-369 4-370 4-371 4-372 15 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-372 OTP FPGA Products XC8100 FPGA Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimating XC8100 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Cell (CLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Cell (IOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTEST/EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metastability Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstep Series 8000 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workstation General Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sun Sparcstation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HP PA series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS 6000 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBM Compatible PC's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Synthesis Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8101 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8103 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8106 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8109 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5-1 5-1 5-3 5-3 5-4 5-4 5-5 5-5 5-6 5-6 5-6 5-6 5-6 5-7 5-9 5-9 5-10 5-10 5-11 5-11 5-11 5-11 5-12 5-12 5-12 5-13 5-13 5-15 5-15 5-16 5-16 5-16 5-16 5-16 5-16 5-16 5-16 5-17 5-17 5-17 5-17 5-19 5-24 5-24 5-25 5-25 5-26 5-27 5-28 5-29 Package Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability (5/96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5-33 5-42 5-42 SPROM Products XC1700D Family of Serial Configuration PROMs Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 RESET/OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 CEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 VPP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Serial PROM Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type 6-2 Controlling Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 FPGA Master Serial Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Programming the FPGA With Counters Unchanged Upon Completion . . . . . . . . . . . . . . . . . . . 6-3 Cascading Serial Configuration PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Programming the XC1700 Family Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 XC1718D, XC1736D, XC1765D, XC17128D and XC17256D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 XC1718L, XC1765L, XC17128L and XC17256L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 AC Characteristics Over Operating Condition (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 3V Products 3.3 V and Mixed Voltage Compatible Products FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L, XC8100 . . . . . . . . . . . . . 3 V PCI-Compliant FPGA: XC3100L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL. . . . . . . . . . . . . . . . . . . . . High-Density FPGAs Without On-chip RAM: XC5200L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Compatible Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-Time-Programmable FPGAs: XC8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX . . . . . . . . . . . . . . . . CPLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-1 17 5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing Between 5 V and 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Devices Driving Inputs on 5 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Devices Driving Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E/EX is Fully Compatible With 3.3 V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-2 7-2 7-2 7-3 7-4 Hardwire Products Xilinx HardWireTM Array Overview Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advantages of Using Xilinx HardWire Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire versus Full ASIC Gate Array Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Coverage and Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging and Silicon Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for the Entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The HardWire Product Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-1 8-2 8-2 8-3 8-3 8-3 Military Products High-Reliability and Military Products Unmatched Hi-Rel Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Committed to the Hi-Rel Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Xilinx Hi-Rel Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Programming Support Programming Support HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programs All Xilinx Nonvolatile Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Socket Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Requirements and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Selector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-1 10-1 10-1 10-1 10-1 10-1 10-2 Packages and Thermal Characteristics Packages and Thermal Characteristics Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inches vs. Millimeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EIA Standard Board Layout of Soldered Pads for QFP Devices . . . . . . . . . . . . . . . . . . . . . . . . Cavity Up or Cavity Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clockwise or Counterclockwise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Method and Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11-1 11-3 11-4 11-5 11-5 11-5 11-6 11-6 11-6 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Junction-to-Reference General Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Junction-to-Case Measurement -- QJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Junction-to-Ambient Measurement -- QJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Data Acquisition and Package Thermal Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Application of Thermal Resistance Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Example 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Example 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 PQ/HQ Thermal Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 The Package Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Where and When Offered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Mass Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Thermal Data for the HQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Other Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Moisture Induced Cracking During Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Factory Floor Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Dry Bake Recommendation and Dry Bag Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Handling Parts in Sealed Bags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Expiration Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 Other Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Material and Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Cover Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Bar Code Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Shipping Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Standard Bar Code Label Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 Reflow Soldering Process Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Plastic DIP Packages -- PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 SOIC Packages -- SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 TSOP Packages -- VO8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 PLCC Packages -- PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 PQFP Packages -- PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 TQFP Packages -- TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . 11-38 VQFP Packages -- VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 BGA Packages -- BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 Ceramic DIP Packages -- DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 Ceramic PGA Packages -- PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299, PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 Ceramic Brazed QFP Packages -- CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . 11-61 CLCC Packages -- CC20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67 Plastic PGA Packages -- PP132, PP175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68 Windowed CLCC Packages -- WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-70 19 Metal Quad Packages -- MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-71 Testing, Quality, and Reliability Quality Assurance and Reliability Quality Assurance Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Integrity and Assembly Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cell Design in the FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Temperature Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 12-2 12-2 12-2 12-3 12-6 12-6 12-7 12-8 12-8 Technical Support Technical Support Technical Support Hotlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-TALX: The Xilinx Network of Electronic Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WebLINX World Wide Web Site (www.xilinx.com) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XDOCs E-mail Document Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XFACTS Document Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Technical Bulletin Board Service (408) 559-9327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-mail addresses for questions related to specific applications . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support E-mail addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AppLINX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCELL Newsletter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What You Will Learn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hands-On Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Course Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic-Based Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis-Based Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis-Based Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Update and Advanced Training Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Update Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13-2 13-2 13-2 13-2 13-3 13-3 13-3 13-3 13-3 13-3 13-3 13-3 13-4 13-4 13-5 13-5 13-5 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-7 13-7 13-7 13-7 13-7 13-8 13-8 Xilinx Headquarters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . North American Distributor Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer-Site Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Site Classes Provide Additional Benefits: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scheduling a Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tuition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Money-back Guarantee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enrollment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Training Registrar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13-8 13-8 13-8 13-8 13-8 13-9 13-9 13-9 13-9 13-9 Product Technical Information Product Technical Information Table of Contents Choosing a Xilinx Product Family Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM-Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200) . . . . . . . . . . . . . . . . . . . Overview of SRAM-Based FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) . . . . . . . . . . . . . . . Antifuse-Based FPGAs (XC8100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM- and FLASH-Based CPLDs (XC7300, XC9500) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of CPLD Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Appropriate Xilinx Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Features Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14-3 14-3 14-4 14-5 14-5 14-5 14-5 14-6 14-6 14-6 14-8 XC4000 Series Technical Information Voltage/Current Characteristics of XC4000-Family Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Output Delays When Driving Capacitive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Bounce in XC4000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpretation of the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Reducing Ground-Bounce Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground-Bounce vs Delay Trade-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 and XC4000E Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14-10 14-10 14-10 14-11 14-11 14-11 14-12 XC3000 Series Technical Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generator Avoids Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Bus Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14-13 14-13 14-14 14-15 14-15 14-16 14-17 14-17 14-17 14-17 21 Vertical Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal-Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Practical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Series Resonant or Parallel Resonant? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCLK Frequency Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCLK Low-Time Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Back-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Things to Remember . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Things to Watch Out For. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beware of a Slow-Rising XC3000 Series RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14-18 14-18 14-19 14-19 14-20 14-21 14-21 14-21 14-21 14-22 14-22 14-22 14-22 14-22 14-23 FPGA Configuration Guidelines Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Against Data or Format Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Best Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . When Configuration Fails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for all Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for the XC2000 and XC3000 Families . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for the XC4000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Mode-Specific Debugging Hints for All Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Up and Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Do Not Let the VPP Pin Float . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Debugging Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potential Length-Count Problem in Parallel or Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14-26 14-26 14-26 14-28 14-29 14-29 14-29 14-30 14-30 14-30 14-30 14-30 14-30 14-31 14-31 14-31 14-32 14-32 Configuring Mixed FPGA Daisy Chains Configuration Issues: Power-up, Volatility, Security, Battery Back-up Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity to VCC Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security when Configuration Data is Accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security by Hiding the Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Back-up and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Things to Remember: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Things to Watch Out for: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14-35 14-36 14-36 14-37 14-37 14-38 14-38 14-38 Dynamic Reconfiguration Important Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 22 Reconfiguration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initiating Reconfiguration in Different Xilinx Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC2000 and XC3000 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 Series and XC5200 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40 14-40 14-40 14-40 Metastable Recovery Metastability Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 Metastability Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 Set-up and Hold Times Overshoot and Undershoot Boundary Scan in XC4000 and XC5000 Series Devices Overview of XC4000/XC5000 Boundary-Scan Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deviations from the IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Boundary-Scan Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49 14-50 14-51 14-51 14-51 14-51 14-53 14-53 14-54 14-57 14-57 Index Index Sales Offices, Sales Representatives, and Distributors Sales Offices 23 24 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Introduction 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Introduction Table of Contents An Introduction to Xilinx Products About this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic vs. Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shortest Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Programmable Logic Devices (CPLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2 1-3 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-5 1-5 1-5 1-5 About this Book This Data Book provides a "snapshot in time" in its listing of IC devices and development system software available from Xilinx as of early 1996. New devices, speed grades, package types and development system products are continually being added to the Xilinx product portfolio. Users are encouraged to contact their local Xilinx sales representative and consult the WebLINX World Wide Web site (http:/ /www.xilinx.com) and the quarterly XCELL newsletter for the latest information regarding new product availability. The product specifications for several older Xilinx FPGA families are not included in this Data Book. This does not imply that these products are no longer available. However, for new designs, users are encouraged to use the newer products described in this book, which offer better performance at lower cost than the older technologies. Product specifications for the older products are available at WebLINX, the Xilinx site on the World Wide Web, or through your local Xilinx sales representative. These products include the following FPGA families: the XC2000, XC3000, XC3100, XC4000, XC4000A, XC4000D, and XC4000H families. Data Sheet Categories In order to provide the most up-to-date information, some component products included in this book may not have been fully characterized at the time of publication. In these cases, the AC and DC characteristics included in the data sheets will be marked as Advance or Preliminary information. (Not withstanding the definitions of such terms, all specifications are subject to change without notice.) These designations have the following meaning: * * * Advance -- Initial estimates based on simulation and/ or extrapolation from other speed grades, devices, or device families. Use as estimates, but not for final production. Preliminary -- Based on preliminary characterization. Changes are possible, but not expected. Final (unmarked) -- Specifications not identified as either Advance or Preliminary are to be considered final. Data Book Contents Chapter 1 is a general overview of the Xilinx product line, and is recommended reading for designers who are new to the field of high-density programmable logic. An Introduction to Xilinx Products Chapter 2 contains a discussion of the overall design methodology when using Xilinx programmable logic and descriptions of Xilinx development system products. This chapter is placed at the beginning of the book since these development tools are needed to design with any of the Xilinx programmable logic devices. Chapter 3 contains the product descriptions for the Xilinx Complex Programmable Logic Device (CPLD) products, including the XC7000 and XC9000 series. Chapter 4 includes the product descriptions for the Xilinx static-memory-based Field Programmable Gate Array (FPGA) products, including the XC3000, XC4000, XC5000, and XC6000 series. Chapter 5 contains the product descriptions for the onetime-programmable XC8000 FPGA series. Chapter 6 holds the product descriptions for the XC1700 family of Serial PROM devices. These Serial PROMs provide a convenient, low-cost means of storing configuration programs for the SRAM-based FPGAs described in Chapter 4. Chapter 7 is an overview of Xilinx components appropriate for 3.3 V and mixed-voltage systems. This chapter will refer you back to the appropriate product descriptions in the earlier chapters. Chapter 8 contains a brief overview of the HardWire product line. Detailed product specifications are available in separate Xilinx data sheets. Chapter 9 is an overview of Xilinx High-Reliability/Military products. Detailed product specifications are available in separate Xilinx data sheets. Chapter 10 describes the HW130 device programmer for the XC1700 series of Serial PROMs, the XC7000 and XC9000 series of CPLDs, and the XC8000 FPGA series. Chapter 11 contains a description of all the physical packages for the various IC products, including information about the thermal characteristics of those packages. Chapter 12 discusses the testing, quality, and reliability of Xilinx component products. Chapter 13 includes a listing of all the technical support facilities provided by Xilinx. Chapter 14 contains additional information about Xilinx components that is not provided in the product specifications of the earlier chapters. This includes some additional electrical parameters that are not in the product specifica- 1-1 An Introduction to Xilinx Products tions because they are not part of the manufacturing test program for the particular device, but may be of interest to the user. Also included in this chapter is a discussion of the JTAG boundary test scan logic found in several Xilinx component families. The final two sections contain an index to the topics included in this Data Book and a listing of Xilinx sales offices, sales representatives, and distributors. About the Company Xilinx, Inc., offers the industry's broadest selection of programmable logic devices. With 1995 revenues of over $500 million, Xilinx is the world's largest supplier of programmable logic, and the market leader in Field Programmable Gate Arrays (FPGAs). Xilinx was founded in 1984, based on the revolutionary idea of combining the logic density and versatility of gate arrays with the time-to-market advantages and convenience of user-programmable standard parts. One year later, Xilinx introduced the world's first Field Programmable Gate Array. Since then, through a combination of architectural and manufacturing process improvements, the company has continually increased device performance, in terms of capacity, speed, and ease-of-use, while lowering costs. In 1992, Xilinx expanded its product line to include advanced Complex Programmable Logic Devices (CPLDs, also known as EPLDs). For the user, CPLDs are an attrac- 1-2 tive complement to FPGAs, offering simpler design software and more predictable timing. As the market leader in one of the fastest growing segments of the semiconductor industry, Xilinx strategy is to focus its resources on creating new ICs and development system software, providing world-class technical support, developing markets, and building a diverse customer base across a broad range of geographic and end-use application segments. The company has avoided the large capital commitment and overhead burden associated with sole ownership and operation of a wafer fabrication facility. Instead, Xilinx has established alliances with several highvolume, state-of-the-art CMOS IC manufacturers. Using standard, high-volume processes assures low manufacturing costs, produces programmable logic devices with wellestablished reliability, and provides for early access to advances in CMOS processing technology. Xilinx headquarters are located in San Jose, California. The company markets its products worldwide through a network of direct sales offices, manufacturers' representatives, and distributors (as listed in the back of this book). The company has representatives and distributors in over 38 countries. Product Line Overview Shortest Time-to-Market Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) can be used in virtually any digital logic system. Over 35 million Xilinx components have been used in a wide variety of end-equipment applications, ranging from supercomputers to hand-held instruments, from central office switches to centrifuges, and from missile guidance systems to guitar synthesizers. When designing with Xilinx programmable logic, time-tomarket is measured in days or a few weeks, not the months often required when using gate arrays. A study by market research firm McKinsey & Co. concluded that a six-month delay in getting to market can cost a product one-third of its lifetime potential profit. With mask-programmed gate arrays, design iterations can easily add that much time, and more, to a product schedule. Xilinx achieved its leading position through a continuing commitment to provide a complete product solution. This encompasses a focus on all three critical areas of the highdensity programmable solution "triangle": components (silicon), software, and service (Figure 1). Programmable Logic vs. Gate Arrays Xilinx programmable logic devices provide the benefits of high integration levels without the risks or expenses of semi-custom and custom IC development. Some of the benefits of programmable logic as versus mask-programmed gate arrays are briefly discussed below. Faster Design and Verification Xilinx FPGAs and CPLDs can be designed and verified quickly while the same process requires several weeks with gate arrays. There are no non-recurring engineering (NRE) costs, no test vectors to generate, and no delay while waiting for prototypes to be manufactured. Design Changes without Penalty Because the devices are software-configured and userprogrammed, modifications are much less risky and can be made anytime - in a manner of minutes or hours, as opposed to the weeks it would take with a gate array. This results in significant cost savings in design and production. Once the decision has been made to use Xilinx programmable logic, a choice must be made from a number of product families, device options, and product types. The information in the product selection matrices that follow can help guide that selection; detailed product specifications are available in subsequent chapters of this book. Since many component products are available in common packages with common footprints, designs often can be migrated to higher or lower density devices, or even across some product families, without any printed circuit board changes. Design ideas, represented in text or schematic format, are converted into a configuration data file for an FPGA or CPLD device using the Xilinx XACTstep development software running on a PC or workstation. Component Products Xilinx offers the broadest line of programmable logic devices available today, with hundreds of products featuring various combinations of architectures, logic densities, package types, and speed grades in commercial, industrial, and military grades. This breadth of product offerings allows the selection of the programmable logic device that is best suited for the target application. Xilinx programmable logic offerings include several families of reprogrammable FPGAs, one-time-programmable * Optimized circuits/architectures * Powerful but easy N CO * Seamless integration into customer CAE system RE SI LI WA * Unmatched quality and reliability * Integrated across families FT * Deep submicron processes SO * Highest performance/densities S E RV I C E * Global world class sales/distribution support * Global world class technical support: FAEs/support center/on-line/internet * Global world class manufacturing: quality/capacity/delivery X5955 Figure 1: The Xilinx Programmable Solution Triangle 1-3 An Introduction to Xilinx Products FPGAs, EPROM-based CPLDs, and FLASH-memorybased CPLDs (Figure 2). HardWire devices are mask-programmed versions of the reprogrammable FPGAs, and provide a transparent, no-risk migration path to lower-cost devices for high-volume, stable designs. Additionally, a family of Serial PROM devices is available to store configuration programs for the reprogrammable FPGA devices. Many devices are available in military temperature range and/or MIL-STD-883B versions, for high-reliability and military applications. Field Programmable Gate Arrays (FPGAs) FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of I/O cells, as diagrammed in Figure 3. Segments of metal interconnect can be linked in an arbitrary manner by programmable switches to form the desired signal nets between the cells. CPLD ISP PAL Architecture Medium Density Simple Tools FPGA Programmable Gate Array Architecture High Density ASIC Tools Complex Programmable Logic Devices (CPLDs) Designers more comfortable with the speed, design simplicity, and predictability of PALs may prefer CPLD devices. Conceptually, CPLDs consist of multiple PAL-like function blocks that can be interconnected through a switch matrix (Figure 4). The Xilinx XC7000 CPLD series is based on EPROM technology. The new XC9000 CPLD series features 5V in-system programmable FLASH technology, and, like most of the FPGA families, includes built-in JTAG boundary scan test logic. HardWire devices ASIC Alternatives Gate Arrays Custom Highest Density ASIC Tools Xilinx Product Line FPGAs combine an abundance of logic gates, registers, and I/Os with fast system speed. Xilinx offers several families of reprogrammable, static-memory-based (SRAMbased) FPGAs, including the XC2000, XC3000, XC4000, XC5000, and XC6000 series. One Xilinx FPGA family, the XC8100 family, is based on the one-time-programmable MicroVia antifuse technology. HardWireTM Custom Transparent Conversion 100% Tested PAL Devices Programmable AND/OR Architecture Low Density Simple Tools HardWire devices are masked-programmed versions of the SRAM-based FPGAs. The HardWire products provide an easy, transparent migration path to a cost-reduced device without the engineering burden associated with conventional gate array re-design. The HardWire gate array is architecturally identical to its FPGA counterpart, but the programmable elements in the FPGA are replaced with fixed metal connections. The resulting die is considerably smaller, with a correspondingly lower cost. Using proprietary automatic test vector generation software and pat- X5957 Figure 2: Application-Specific IC Products PROGRAMMABLE INTERCONNECT I/O BLOCKS X1153 LOGIC BLOCKS Figure 3: FPGA Architecture 1-4 FB FB FB FB Interconnect Matrix I/O I/O FB FB FB FB X5956 Figure 4: CPLD Architecture ented test logic, Xilinx guarantees over 95% fault coverage, while eliminating the need for user-generated test vectors. The mask and test programs are generated automatically by Xilinx from the user's existing FPGA design file. Serial PROMs The XC1700 family features one-time programmable serial PROMs ranging in density from about 18,000 bits to over 260,000 bits. These serial PROMs are an easy-to-use, cost-effective method for storing configuration data for the SRAM-based FPGAs. High-Reliability Devices Xilinx was the first company to offer high-reliability FPGAs by introducing MIL-STD-883B qualified XC2000 and XC3000 series devices in 1989. MIL-STD-883B members of the XC4000 FPGA series also are available, and qualified versions of additional Xilinx families are in development. The product line also includes Standard Microcircuit Drawing (SMD) versions of several families. Some Xilinx devices are available in tested die form through arrangements with manufacturing partners. Development System Products Xilinx offers a complete software environment for the implementation of logic designs in Xilinx programmable logic devices. This environment, called XACTstep, combines powerful technology with a flexible, easy-to-use graphical interface to help users achieve the best possible designs, regardless of experience level. The user has a wide range of choices between a fully-automatic implementation and detailed involvement in the layout process. The XACTstep system provides all the implementation tools required to design with Xilinx logic devices, including the following: * * * * * * * libraries and interfaces for popular schematic editors, logic synthesis tools, and simulators design manager/flow engine module generator map, place, and route compilation software graphical floorplanner static timing analyzer hardware debugger Xilinx is committed to an "open system" approach to frontend design creation, synthesis, and verification. Xilinx devices are supported by the broadest number of EDA vendors and synthesis vendors in the industry. Supported platforms include the ubiquitous PC and several popular workstations. Service Providing global, world-class manufacturing, technical support, and sales/distribution support is an essential foundation of the Xilinx product strategy. Xilinx manufacturing facilities have earned ISO9002 certification, and Xilinx quality and reliability achievements are among the world's best - not just for programmable logic suppliers, but among all semiconductor companies. Comprehensive technical support facilities include training courses, extensive product documentation and application notes, a quarterly technical newsletter, automated document servers, a technical bulletin board, the WebLINX World Wide Web site, technical support hotlines, and a cadre of Field Application Engineers. Sales support is provided by a worldwide network of representatives and distributors. 1-5 An Introduction to Xilinx Products FEATURES DENSITY PERFORMANCE XC3190L XC3142L XC3195A XC3190A XC3164A XC3142A XC3130A XC3120A XC3090A/L XC3064A/L Low Cost/ Low Power Low Voltage (3.3 V) Highest Performance Highest Performance Max Logic Gates (K) 1.5 2 3 5 6 1.5 2 3 5 6 8 3 6 Max RAM Bits N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Typical Gate Range (K) 1-1.5 1.5-2 2-3 4-5 5-6 1-1.5 1-2 2-3 4-5 5-6 7-8 2-3 5-6 CLBs 64 100 144 224 320 64 100 144 224 320 484 144 320 Flip-Flops 928 256 360 480 688 928 256 360 480 688 928 1320 480 Output Drive (mA) 4 4 4 4 4 8 8 8 8 8 8 4 4 JTAG (IEEE 1149.1) N N N N N N N N N N N N N Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 1-6 XC3042A/L XC3030A/L KEY FEATURES XC3000 Series XC3020A/L DEVICES FPGA Product Selection Matrix N N N N N N N N N N N N N 0.5/ 0.02 0.5/ 0.02 0.5/ 0.02 0.5/ 0.02 0.5/ 0.02 8 8 8 8 8 8 1.5 1.5 -6/-8 -6/-8 -6/-8 -6/-8 -6/-8 -09 -09 -09 -09 -09 -09 -2 -2 Shift Register (MHz) 124/69 124/69 124/69 124/69 124/69 312 312 312 312 312 312 256 256 Small State Machine (MHz) 42/23 42/23 42/23 42/23 42/23 112 112 112 112 112 112 68 68 Large State Machine (MHz) 21/14 21/14 21/14 21/14 21/14 55 55 55 55 55 55 33 33 4-Bit Multiply-Accumulator (MHz) 20/12 20/12 20/12 20/12 20/12 51 51 51 51 51 51 33 33 16-Bit Accumulator (MHz) 25/15 25/15 25/15 25/15 25/15 58 58 58 58 58 58 41 41 Address Map Decoder (MHz) 52/27 52/27 52/27 52/27 52/27 127 127 127 127 127 127 84 84 Data Path (MHz) 147/86 147/86 147/86 147/86 147/86 335 335 335 335 335 335 84 84 Counter Timer (MHz) 37/23 37/23 81 81 81 81 81 81 56 56 16-Bit Non Loadable Counter (MHz) 135/81 135/81 135/81 135/81 135/81 370 370 370 370 370 370 323 323 16-Bit Loadable Binary Up Counter (MHz) 39/25 37/23 39/25 37/23 39/25 37/23 39/25 91 91 91 91 91 91 63 63 16-Bit Loadable Prescaled Counter (MHz) 100/59 100/59 100/59 100/59 100/59 39/25 228 228 228 228 228 228 154 154 RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Pad to Setup (ns) 14/12 14/12 14/12 14/12 14/12 2.5 2.5 2.5 2.5 2.5 2.5 4 4 Clock to Pad (ns) 7/18 7/18 7/18 7/18 7/18 4 4 4 4 4 4 5 5 Combinatorial Pad to Pad (ns) 14/25 14/25 14/25 14/25 14/25 6 6 6 6 6 6 8 8 Max RAM Bits (no Logic) 3 5 8 10 13 20 25 28 36 44 52 3200 6272 8192 10368 12800 18342 25088 32768 32768 41472 51200 61952 XC4013L XC4010L XC4005L XC4005H XC4003H XC4062XL XC4052XL XC4044EX XC4036EX XC4028EX XC4025E* XC4020E* XC4013E* XC4010E* XC4008E* 6 High I/O Low Voltage (3 V) 62 3 5 5 73728 3200 6272 6272 10 13 12800 18432 Typical Gate Range (Logic and RAM) (K) 2-5 3-9 4-12 6-15 7-20 10-30 13-40 15-45 18-50 22-65 27-80 33-100 40-130 2-5 3-9 3-9 7-20 CLBs 100 196 256 324 400 576 784 1024 1024 1296 1600 1936 2304 100 196 196 400 576 Flip-Flops 360 616 768 936 1120 1536 2016 2560 2560 3168 3840 4576 5376 200 392 616 1120 1536 Output Drive (mA) 12 12 12 12 12 12 12 12 12 12 12 12 12 24 24 4 4 4 JTAG (IEEE 1149.1) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 10-30 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Quiescent Current (mA) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 0.05 0.05 0.05 Fastest Speed Grade -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -5 -5 Shift Register (MHz) 190 190 190 190 190 190 190 190 190 190 190 190 190 105 105 69 69 69 69 69 69 69 69 69 69 69 48 48 43 43 43 43 43 43 43 43 43 43 43 43 37 37 4-Bit Multiply-Accumulator (MHz) 39 39 39 39 39 39 39 39 39 39 39 39 39 20 20 16-Bit Accumulator (MHz) 65 65 65 65 65 65 65 65 65 65 65 65 65 36 36 Address Map Decoder (MHz) 71 71 71 71 71 71 71 71 71 71 71 71 71 43 43 Data Path (MHz) 156 156 156 156 156 156 156 156 156 156 156 156 156 105 105 Counter Timer (MHz) 117 117 117 117 117 117 117 117 117 117 117 117 117 58 58 16-Bit Non Loadable Counter (MHz) 180 180 180 180 180 180 180 180 180 180 180 180 180 95 95 16-Bit Loadable Binary Up Counter (MHz) 87 87 87 87 87 87 87 87 87 87 87 87 87 42 42 16-Bit Loadable Prescaled Counter (MHz) 115 115 115 115 115 115 115 115 115 115 115 115 115 63 63 RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 50 50 Pad to Setup (ns) 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 7 7 Clock to Pad (ns) 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 10 10 Combinatorial Pad to Pad (ns) 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 5 5 XC8100 69 43 XC6264 69 Large State Machine (MHz) XC6236 Small State Machine (MHz) CONTACT FACTORY Dedicated Arithmetic XC6216 DENSITY FEATURES XC4006E* High Density High Performance Select-RAMTM Memory Max Logic Gates, (no RAM) (K) PERFORMANCE XC4005E* XC4000 Series XC4003E* KEY DEVICES FEATURES FPGA Product Selection Matrix (continued) XC8109 XC8106 XC8103 XC8101 XC6209 XC5215 XC5210 XC5206 3 6 10 16 23 13 24 55 100 1 2 8 13 20 Max RAM Bits N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Typical Gate Range (K) 2-3 4-6 6-10 10-16 15-23 9-13 16-24 36-55 64-100 0.6-1 1-2 3-8 6-13 9-20 CLBs/Logic Cells 64 120 196 324 484 2304 4096 9216 16384 192 384 1024 1728 2688 Flip-Flops 256 480 784 1296 1936 2304 4096 9216 16384 96 192 512 864 1344 Output Drive (mA) 8 8 8 8 8 8 8 8 8 24 24 24 24 24 JTAG (IEEE 1149.1) Y Y Y Y Y N N N N Y Y Y Y Y Dedicated Arithmetic Y Y Y Y Y N N N N N N N N N - - - - 10 Quiescent Current (mA) 15 15 15 15 15 5 5 10 10 Fastest Speed Grade -4 -4 -4 -4 -4 -1 -1 -1 -1 -1 Shift Register (MHz) 83 83 83 83 83 123 123 123 123 123 Small State Machine (MHz) 50 50 50 50 50 48 48 48 48 48 Large State Machine (MHz) 35 35 35 35 35 33 33 33 33 33 4-Bit Multiply-Accumulator (MHz) 24 24 24 24 24 N/A N/A N/A N/A N/A 16-Bit Accumulator (MHz) 60 60 60 60 60 Address Map Decoder (MHz) 69 69 69 69 69 Data Path (MHz) 83 83 83 83 83 Counter Timer (MHz) 59 59 59 59 59 16-Bit Non Loadable Counter (MHz) N/A N/A N/A N/A N/A 16-Bit Loadable Binary Up Counter (MHz) 58 58 58 58 58 16-Bit Loadable Prescaled Counter (MHz) 83 83 83 83 83 RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A Pad to Setup (ns) 6.6 6.6 6.6 6.6 6.6 Clock to Pad (ns) 14.2 14.2 14.2 14.2 15 15 15 15 Combinatorial Pad to Pad (ns) CONTACT FACTORY DENSITY FEATURES Single Chip Design Security ASIC Design Flow P Interface Fast Configuration High Density Low Cost Max Logic Gates (K) PERFORMANCE XC5204 XC5000, XC6000, XC8000 Series XC5202 KEY DEVICES FEATURES *Usable gates assume 20% of CLBs used as RAM 30 30 30 30 30 N/A N/A N/A N/A N/A 103 103 103 103 103 N/A N/A N/A N/A N/A 102 102 102 102 102 40 40 40 40 40 51 51 51 51 51 N/A N/A N/A N/A N/A 7.5 7.5 7.5 7.5 7.5 14.2 7 7 7 7 7 15 9.5 9.5 9.5 9.5 9.5 *Usable gates assume 20% of CLBs used as RAM 1-7 An Introduction to Xilinx Products XC95432 XC95576 XC95288 XC95216 XC95180 3.8 0.8 1.6 2.4 3.2 4.0 4.8 6.4 9.6 12.8 108 144 36 72 108 144 180 216 288 432 576 Flip-Flops 18 36 36 108 126 198 234 36 72 108 144 180 216 288 432 576 Output Drive (mA) 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 JTAG (IEEE 1149.1) N N N N N N N Y Y Y Y Y Y Y Y Y Dedicated Arithmetic N N N Y Y Y Y N N N N N N N N N 100% Routable 100% Utilization 5 ns TPD XC95144 XC95108 3.0 72 XC9572 1.9 54 XC9536 XC73144 1.5 36 XC7372 0.8 36 XC7354 XC73108 XC7336Q 0.8 18 XC7336 0.4 Macrocells XC7318 Gates (K) CPLD Families JTAG 5 V ISP 3 V or 5 V I/O Quiescent Current (mA) 90 126 50 140 187 227 250 - - 140 - - - - - - Fastest Speed Grade -5 -5 -10 -7 -7 -7 -7 -5 -7 -7 -7 -10 -10 -10 - - Shift Register (MHz) 125 125 95 95 95 95 Small State Machine (MHz) 108 108 95 95 95 95 Large State Machine (MHz) 102 102 95 95 95 95 4-Bit Multiply-Accumulator (MHz) 46 46 52 52 52 52 16-Bit Accumulator (MHz) 40 40 63 63 63 63 34 72 108 133 168 168 192 232 232 69 69 72 81 72 81 133 133 168 168 232 232 Address Map Decoder (MHz) 108 108 95 95 95 95 Data Path (MHz) 125 125 95 95 95 95 Counter Timer (MHz) 94 94 47 47 47 47 16-Bit Non Loadable Counter (MHz) 125 125 95 95 95 95 16-Bit Loadable Binary Up Counter (MHz) 125 125 95 95 95 95 16-Bit Loadable Prescaled Counter (MHz) 125 125 95 95 95 95 RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A Pad to Setup (ns) 3.5 3.5 4 4 4 4 Clock to Pad (ns) 4.5 4.5 7 7 7 7 5 5 7 7 7 7 84 120 156 Combinatorial Pad to Pad (ns) CONTACT FACTORY PERFORMANCE FEATURES DENSITY KEY DEVICES FEATURES CPLD Product Selection Matrix Number of Pins PACKAGE OPTIONS AND USER I/O Package (Code) MAX I/O 1-8 38 38 38 58 PLCC (PC) 44 38 38 38 38 PQFP (PQ) 44 38 38 38 CLCC (WC) 44 38 38 VQFP (VQ) 44 PLCC (PC) 68 58 57 CLCC (WC) 68 58 57 PLCC (PC) 84 72 72 CLCC (WC) 84 72 72 84 84 34 34 38 38 PGC (PG) 84 PQFP (PQ) 100 TQFP (TQ) 100 PGA (PG) 144 120 PQFP (PQ) 160 120 HQFP (HQ) 208 BGA (BG) 225 HQFP (HQ) 304 120 136 108 81 133 168 156 192 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Development System Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Development System Products Table of Contents Development Systems Products Overview XACTstep: Accelerating Your Productivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Six Powerful New Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Software on CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support and Update Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Series Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Individual Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-2 2-4 2-5 2-6 2-8 2-9 Bundled Packages Product Descriptions Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base System with VHDL Synthesis (PC) . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Standard System with VHDL (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: OrCAD - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: OrCAD - Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic Stand-alone - Extended System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Viewlogic - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Mentor V8 - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Synopsys - Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Cadence - Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Third Party Alliance - Standard System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 Individual Product Descriptions FPGA Core Implementation - DS-502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPLD Core Implementation - DS-560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic and Simulator Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-BLOX - DS-380. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx ABEL Design Entry - DS-371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx ABEL Design Entry - DS-571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx-Synopsys Interface (XSI) - DS-401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XChecker Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demonstration Board - FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2-31 2-32 2-32 2-33 2-34 2-35 2-36 2-36 Development Systems Products Overview June 1, 1996 (Version 1.0) XACTstep: Accelerating Your Productivity The newest version of the XACT development system, XACTstep, started shipping in the fourth quarter of 1995. XACTstep software features a revolutionary combination of power and ease-of-use to provide accelerated learning curves, short implementation cycles, and faster design debug. This high-productivity environment contains six new productivity tools that are easily accessible through graphical tool bars, icons and pop-up menus. They support the complete spectrum of programmable logic design methodology from fully automatic to hand-crafted. All the tools in XACTstep feature a new graphical user interface (GUI). On the PC, the GUI is fully Microsoft Windows compliant. With this new GUI, all programs are executed from tool bars and icons. Tool tips provide instant descriptions and on-line help is available for more in-depth information. Report browsers present message files with plain English titles and allow simultaneous viewing of multiple documents. Six Powerful New Tools * The new Design Manager provides a complete project management environment for a wide range of families. It provides version control, device re-targeting and design re-use. * The configurable Flow Engine lets designers choose the amount of control they want over the implementation process. They can choose a fully automatic flow or set break points that allow analysis and optimization of results before proceeding to the next step. * XACTstep contains the industry's first graphically-based hierarchical Floorplanner. This tool provides techniques that have proven to be extremely valuable to gate array and custom silicon designers. Using floorplanning, it is easy to achieve hand-crafted levels of performance and density without resorting to low-level manual techniques. Floorplanning is valuable for any design that has a high degree of structure or a large number of gates. It also allows optimization of specialized structures like Xilinx unique high-speed distributed RAM and three-state internal bus features. * The new interactive Timing Analyzer makes it easy to quickly determine a design's performance by generating custom timing reports. Using pop-up menus, June 1, 1996 (Version 1.0) it is quickly configured to show the delay along a specific path or group of paths. It also shows the delay along all paths of a certain type or those associated with a specific clock signal. In addition, the Timing Analyzer automatically compares the design's actual performance to XACT-Performance goals and shows the estimated maximum frequency for each clock in the design. * The Hardware Debugger allows verification of configuration data and viewing of internal signal activity. It takes advantage of the reprogrammability of SRAMbased devices by configuring the FPGA in-circuit using a cable connected to a host PC or workstation. After configuring the device, bitstream data is read back through the cable for automatic verification. While the device is running, an unlimited number of internal nodes can be probed and displayed in a waveform window. * The new PROM Formatter in XACTstep assists the designer in creating PROM programming files. This tool chooses the best PROM size or automatically splits the data into multiple files if multiple PROMs are required. It supports serial and byte-wide PROMs in four different formats. If the target system uses the daisy chain capability of the Xilinx FPGA, the PROM formatter graphically creates the load order and verifies the load sequence. The Xilinx Design Manager--Simplifies the Design Flow * * * * Source and revision control Permits running all Xilinx software from menus Automates design translation via XMake facility Provides on-line help for all menus, programs and options .Flow * * Engine Automatically invokes all implementation programs as required to compile a design into an FPGA or CPLD Supports hierarchically-structured designs Extensive On-line Help * The Design Manager contains on-line Help for Every menu Every program Every program option Design-flow suggestions 2-1 Development Systems Products Overview Figure 1: Design Manager Main Window Design Flow Overview This section describes the Xilinx Automated CAE Tools (XACT) design environment for Xilinx FPGA and CPLD devices. logic System's PROcapture schematic editor and PROsim simulator), but architecture-specific tools are needed for implementation. Design Entry High-density programmable logic has created unique requirements for CAE software; the tools must deliver the ease-of-design and fast time-to-market benefits that have popularized FPGA and CPLD technologies, must be capable of implementing high-density logic designs on an engineer's desktop system, and must be easy-to-use and compatible with the user's existing design environment. Schematic editors and synthesis are the most-popular methodologies for design entry. FPGA/CPLD symbol libraries and netlist interfaces are available for schematic editors from vendors such as Viewlogic, OrCAD, Mentor Graphics, and Cadence. These libraries reflect the wide variety of logic functions that can be implemented in FPGA/CPLD devices. In order to meet those needs, Xilinx offers a variety of development system products optimized to support the Xilinx FPGA and CPLD architectures. Available products include state-of-the-art design implementation software, libraries and interfaces to popular schematic editors, synthesis and timing simulators, and behavioral-based design entry tools. All Xilinx development system software is integrated under the Xilinx Design Manager, providing designers with a common user interface regardless of their choice of device architecture and tools. Behavioral-oriented design entry methods, including Boolean equations and state-machine descriptions, are supported by the Xilinx ABEL and LogiBloxs products, as well as a number of products from CAE vendors such as Data I/O, Logical Devices, MINC, and ISDATA. As with other logic technologies, the basic methodology for FPGA design consists of three interrelated steps: entry, implementation, and verification. (Figure 2 - Figure 4). The design process is iterative, returning to the design entry phase for correction and optimization. Popular generic tools are used for entry and simulation (for example, View- 2-2 As the density and complexity of FPGA and CPLD designs increase to 10,000 gates and beyond, gate-level entry tools often are cumbersome, and the use of logic synthesis and high-level description languages (HDLs), such as VHDL and Verilog, can raise designer productivity. The use of HDLs requires synthesis tools that effectively compile designs for the target architecture. Xilinx offers interfaces for synthesis tools from Synopsys. Other CAE vendors, such as Mentor Graphics, Cadence Design Systems, Viewlogic, and Exemplar Logic, also offer synthesis tools tailored for the Xilinx device architectures. June 1, 1996 (Version 1.0) Functional Simulation Design Entry Design Verification Timing Simulation (Back-annotation) Schematic Entry Text-based Entry Simulation In-circuit Verification Static Timing Analysis Design Implementation Partition, Place & Route FPGA Partition, Map & Interconnect CPLD X4351 Figure 2: FPGA/CPLD Design Flow Many engineers prefer visually oriented design-entry techniques over text-based HDLs. The benefits of HDLs are provided to these designers with tools that provide highlevel design constructs in a symbolic format compatible with graphics-based schematic editors. X-BLOX is a graphics-based high-level language that allows designers to use a schematic editor to enter designs as a set of generic modules. The X-BLOX compiler optimizes the modules for the target device architecture, automatically choosing the appropriate architectural resources for each function. The XACTstep design environment supports hierarchical design entry, with top-level drawings defining the major functional blocks, and lower-level descriptions defining the logic in each block. The implementation tools automatically combine the hierarchical elements of a design. Different hierarchical elements can be specified with different design entry tools, allowing the use of the most convenient entry method for each portion of the design. In this type of `mixedmode' design entry, designers can intermix schematic, text, gate-level and behavioral-level design, permitting the reuse of previously designed modules and easing the transition to higher-level design methodologies. Design Implementation After the design is entered, implementation tools map the logic into the resources of the target device architecture, determine an optimal placement of the logic, and select the routing channels that connect the logic and I/O blocks. Xilinx design implementation tools apply a very high degree of automation to these tasks. A design compilation utility automatically retrieves the design's input files and performs all the necessary steps to create the CPLD or FPGA configuration program. For demanding applications, the user can exercise various degrees of control over the automated implementation process using auto-interactive tools and techniques. Option- June 1, 1996 (Version 1.0) ally, user-designated partitioning, placement, and routing information can be specified as part of the design entry process (typically, right on the schematic). The implementation of highly structured designs can greatly benefit from the basic floorplanning techniques familiar to designers of large gate arrays. For Xilinx FPGAs, the automatic tools are complemented by an interactive, graphics-based editor that allows users to view and manipulate a model of the logic and routing resources inside the FPGA device, providing the user with visibility into the implementation of the design. Design Verification Verification of FPGA/CPLD designs typically involves a combination of in-circuit testing, simulation, and static timing analysis. The user-programmable nature of these devices allows designs to be tested immediately in the target application. For Xilinx FPGAs and in-system-programmable CPLDs, download cables are provided that allow for the direct downloading of a bitstream from a PC or workstation to an FPGA or CPLD device on a target board. Demonstration/prototyping boards are also available. The implementation tools include back-annotation to provide post-layout timing of implemented designs to support timing simulation. A static timing analyzer can be used to examine a design's logic and timing to calculate the performance along signal paths, identify possible race conditions, and detect set-up and hold-time violations. Timing analyzers do not require the user to generate input stimulus patterns or test vectors. Xilinx software is available both in bundled packages containing front end implementation tools and with integrated kits to enable plug and play with 3rd party EDA environments. New enhancements are constantly being developed, and update services are available to ensure timely access to the latest versions. 2-3 Development Systems Products Overview Xilinx Software on CD-ROM * Xilinx software and updates are now delivered on CD-ROM for the PC and workstations (Sun, HP700 and RS6000 Series). Here are some of the benefits: * * Faster Installation: No more wasted time, feeding floppy after floppy into the PC. No more waiting for workstation tapes to spin, looking for the proper data. Installing or updating Xilinx software is as easy as popping in one CD-ROM disk. Step 1 Design Entry Macro & MSI Libraries OrCAD Viewlogic Software Compatibility: New install utilities monitor the software configuration, ensure executable version compatibility, and update only the necessary files to keep the software up-to-date. Archiving old versions of XACT software is as easy as storing one CD-ROM disk. On-line documentation, tutorials, application notes, and product demonstrations. Mentor V8.x Alliance Partner HDL/VHDL Synopsys I/F Xilinx Logic Library & XNF Interface Xilinx ABEL State Machine Entry Logic Synthesis XNF Netlist DS-502 Step 2 File Merging Logic Reduction Design Rule Check X-BLOX (if present) Design Implementation Mapping into Blocks Place & Route LCA Netlist Interactive Design Editor LCA Netlist with Block and Net Timing Timing Annotated XNF Netlist Gate Level Simulation Logic & Timing Simulation Bit Stream Compiler MakeBits & MakePROM Logic Cell Array (FPGA) Step 3 Design Verification Serial Configuration PROM Programmer In-Circuit Design Verification Xilinx Serial PROMs X5978 Figure 3: Detailed FPGA Design Flow 2-4 June 1, 1996 (Version 1.0) Macro & MSI Libraries Step 1 Design Entry OrCAD Viewlogic Mentor V8.x Alliance Partner Xilinx Logic Library & XNF Interface Xilinx ABEL PLUSASM XNF Netlist Data I/O ABEL 6 Logical Devices-CUPL Step 2 File Merging Logic Reduction Design Rule Checking Design Implementation DS-560 Logic Optimization Device Fitting Step 3 Report Generation Programming Generation Design Reports Device Programming File Design Verification Device Programming HW-130 Timing Netlist Generation Timing Annotated XNF Netlist Gate Level Simulation Logic & Timing X5979 Figure 4: Detailed CPLD Design Flow Support and Update Services Software Updates A major focus of Xilinx engineering is continual improvement of the Xactstep Development System Software. This is accomplished by developing new features to improve your design productivity, and adding new technologies to give you access to the latest Xilinx products. If you are on maintenance, you will receive new revisions containing enhancements to the software products you have licensed from Xilinx. June 1, 1996 (Version 1.0) Base Product Updates The Xactstep Base packages do not come with a standard one-year update contract. When Xilinx releases a new version of software, customers will be notified and may purchase the new version update at the listed price. Online Documentation Xilinx continually updates documentation to reflect changes to the Development System Software. As part of the update service, you receive new online documentation with each update. 2-5 Development Systems Products Overview Technical Support Hotline The Technical Telephone Support Hotline provides you with toll-free telephone access to trained software technical support engineers. (See Chapter 13.) Expertise provided includes most major third-party interfaces including Viewlogic, OrCAD, Mentor Graphics, Xilinx ABEL, Synopsys, and Cadence. Additionally, Xilinx core expertise is available for both FPGA and CPLD product lines covering place and route, X-BLOX, XACT Performance, XDelay, configuration and component issues. This support service for problem resolution assistance is available between 8:00 am and 5:00 pm Pacific Standard Time, Monday through Friday (except holidays). For service outside USA, please contact your local representative. Xilinx Technical Bulletin Board The Xilinx Technical Bulletin Board allows electronic exchange of information with technical support engineers. With this service you can upload your design data making it available to support engineers during problem resolution. You can use the Technical Bulletin Board download capability to obtain various software utilities, the latest released revisions of speed and package files, detailed solutions for commonly encountered problems, and marketing updates. The Technical Bulletin Board number is 1-408-559-9327 and it is available 24 hours a day, 7 days a week. Customer Support FAX The technical support engineers can be reached directly via facsimile by using the "Technical Support only" fax line. This service is available to supply information to the support engineers to resolve a specific inquiry. Additionally, this service may be used in lieu of, or together with, the Technical Support Hotline. The fax number is 1-408-879-4442. Internet Electronic Mail Support Another alternative for technical support is via the Internet E-Mail address, hotline@xilinx.com. As with the other previously described methods, electronic mail allows full access to Xilinx Technical Support engineers. Software Series Overview The Xilinx Xactstep Software Series provides powerful, easy to use design tools for FPGA and CPLD devices. Three different series with several choices of configurations lets designers choose the exact system for their needs. * * * Foundation Series -- Complete shrink-wrapped design solutions Alliance Series -- Powerful systems that integrate into existing EDA environments SLI Series -- Value added options that enable system level integration. 2-6 * XC8000 Series -- Specifically designed for the XC8100 FPGA sea-of-gates architecture and ASIC design flow The Foundation Series provides entry-level designers with a complete solution in a shrink-wrapped, easy-to-use environment. This fully integrated set of tools, which is perfect for users that are new to PLD design, includes design entry simulation, VHDL synthesis, and design implementation tools. The Xilinx Alliance Series is for designers who want to integrate into their existing EDA tool environment. It supports the complete spectrum of design techniques with interfaces to over 45 EDA vendors and 80 different design tools. Optional Viewlogic front-end products are part of the Alliance Series. This is ideal for users who want a complete system that is extensible to board and system level design. The Foundation and Alliance Series support the industry's broadest array of PLD solutions including the XC2000, XC3000A, XC3100A, XC4000/E, XC5000, XC7300 and XC9500 families. This gives designers technology independence by letting them choose target devices late in the design cycle. Both series include the powerful XACTstep implementation system containing the popular Design Manager, Flow Engine, PROM File Formatter, Floorplanner and Hardware Debugger. The XC8000 Series is a standalone software package that is specifically designed for the sea-of-gates architecture. It features ASIC-like design flows and interfaces to many synthesis and schematic tools. All products in the Xilinx XACTstep Series use standardsbased design techniques that maximize design portability and reuse. EDA design tools that support EDIF, ABEL, Verilog, VHDL and LPM formats interface easily into the Xilinx design environment. PLD designs can use integrated ABEL design and synthesis or interfaces to any of the leading PLD design tools environments. Schematic designs can use the integrated capture tool in the Foundation Series or choose interfaces to any leading EDA environment. HDL designs enjoy standards-based design using integrated VHDL synthesis in the Foundation Series or interfaces to any leading VHDL or Verilog synthesis tool. This flexibility protects the user's investment in design tools and training and makes it easy to re-use designs even when EDA systems change. Foundation Series The Foundation Series provides everything required to design a programmable logic device in an easy-to-use, fully-integrated environment. This fully integrated solution makes PLD design easy by providing push button design June 1, 1996 (Version 1.0) flows, on-line training and the XACTstep windows-based graphical user interface. This series features broad support for standards based HDL design. All configurations interface with the popular ABEL language and fitters optimized for each target architecture. VHDL configurations include integrated VHDL synthesis with tutorials and wizards to turn new users into experts quickly and easily. Easy to Learn and Use The Foundation Series is a fully integrated tool set allowing users to access design entry, implementation and verification tools from a single graphical user interface. Every step in the design process is accomplished using graphical tool bars, icons and pop-up menus supported by interactive tutorials and comprehensive on-line help. VHDL Synthesis VHDL configurations of the Foundation Series contain integrated VHDL synthesis and wizards with the following features. * * * * On-line tutorial teaches the art of VHDL design. Intelligent HDL editor with color coding, syntax checking and single click error navigation makes it easy to read and debug VHDL designs. HDL Language Assistant provides libraries of common functions with optimized VHDL code. FPGA specific synthesis tools produce high-density, high-performance results. ABEL-HDL Synthesis ABEL configurations of the Foundation Series contain integrated synthesis and wizards with the following features. * * * Intelligent HDL editor with color coding, syntax checking and single click error navigation makes it easy to read and debug ABEL designs. HDL Language Assistant provides libraries of common functions with optimized ABEL code. FPGA/CPLD specific synthesis tools produce highdensity, high-performance results. Alliance Series The Alliance Series is for users who want powerful design tools that integrate into their existing EDA environment. With this series, designers can choose from a wide range of design techniques including schematic capture, modulebased design and HDL from over 45 EDA vendors. With standards based design interfaces including EDIF, ABEL, Verilog and VHDL, this series provides maximum flexibility, portability and design reuse. Advanced integration with Cadence, Mentor, OrCAD, Synopsys and Viewlogic provide tightly-coupled environments that make it easy to move through the design process. June 1, 1996 (Version 1.0) Other EDA vendors are supported through the Xilinx Alliance Program, insuring high quality tools and accurate results. Information on these vendors can be found on the Xilinx Alliance CD or through WebLINX on the world wide web at www.xilinx.com. The Alliance Series includes the complete XACTstep implementation tool set supporting the complete spectrum of design methodologies from fully-automatic to handcrafted. Viewlogic Standalone products are part of the Alliance Series and are for those users who want the integration of a complete solution with the power to access board and system level design tools. These products include Viewlogic Workview Office schematic capture, simulation and synthesis tools. Configurations The Xilinx Software Series are available in 3 configurations giving designers a cost effective way to match their tools to the gate densities they require. CPLD configurations provide support for Xilinx's XC9500 and XC7300 CPLD families. Base configurations provides push-button design flows and support designs up to 5,000 gates. Standard configurations combine push-button flows with powerful auto-interactive tools. These tools give designers more influence and control over implementation while maintaining the benefits of design automation. Standard configurations support designs up to 20,000 gates. Optional LogiCores give designers access to large fully verified functions that simplify design entry and provide dramatic savings in engineering resources. The initial LogiCore product set includes a complete PCI interface module. Migration Paths All tools in the Xilinx XACTstep Series use standardsbased design to protect the user's investment as design requirements change. For example, designers can use Foundation products to learn ABEL or VHDL and produce code optimized for device resources. If future requirements force the use of different design tools, users can upgrade to the Xilinx Alliance Series and reuse their code while gaining access to powerful system-level tools. The Foundation and Alliance Series use the same core implementation tools eliminating the need to re-learn the design process after an upgrade. Unified libraries and standard design file formats allow schematic designers to enjoy the same migration capabilities. 2-7 Development Systems Products Overview Series 8000 Individual Products XC8100 FPGAs use a stand-alone software package specifically designed for the sea-of-gates architecture and ASIC-like design flow. This package, called Series 8000, is both simple to use and powerful with features including incremental design, hierarchical netlist/naming, floorplanning, scripting and on-line help. Libraries and Interface - Contains schematic symbols or HDL libraries, simulation models with timing information, and translators to the XNF file format. The XC8100 family is architected from the ground up to be efficient with synthesis by providing predictable pre-layout timing, accurate backannotation and 1-1 mapping of netlist to logic. Although this series is designed specifically for the XC8100, it shares common design entry methodologies with the Foundation and Alliance series. Schematic libraries use the same symbol names and sizes and HDL code is portable between the systems. This lets designers easily retarget designs from one family to another. The Series 8000 includes CAE libraries and interfaces, place and route software and programming software for all devices in the XC8100 family. Core Implementation - Provides the software necessary to process an XNF file into a file which can be used to program a Xilinx FPGA or CPLD device. Includes tools for logic reduction, design rule checking, mapping, automatic placement and routing, bitstream generation and PROM file generation. X-BLOX Module Generator & Optimizer - Allows design entry as block diagrams using a familiar schematic editor. Using built-in expert knowledge, X-BLOX software automatically optimizes your design to take full advantage of the unique features of the XC3000A, XC3100A, XC4000, and XC5000 FPGA families. Xilinx ABEL - Supports CPLD and FPGA text-based design entry and netlist translation using ABEL high level description language. ABEL supports different design styles including Boolean equations, truth tables and encoded or symbolic state machines. XCheckerTM Cable - Supports downloading of bitstream and PROM files, and readback of configuration data and internal node values. This cable uses the serial port of IBM PCs & compatibles and supported workstations. FPGA Demoboard - Provides demonstration or prototype capability for XC2000, XC3000, XC3000A, XC3100, XC3100A devices in 68-pin PLCC packages, and XC4000 family devices in 84-pin PLCC. This board is designed to offer flexibility for learning and prototyping. 2-8 June 1, 1996 (Version 1.0) Order Codes Order codes for Development Systems products consist of a multiple-field part number. The first field indicates the product category. Additional fields indicate the third-party CAE vendor for interface tools, the package name or individual product number and the platform. For example, the following order code indicates the category as Development System, the interface CAE vendor as Viewlogic, the package as Standard, the platform as IBM PC or compatible, and the media as CD-ROM. DS-VL-STD-PC1-C The following table shows valid product category, CAE vendor, package type, platform and media type codes. June 1, 1996 (Version 1.0) Product Category Development System Support and Updates Base Update Re-instate Updates Product Upgrade Hardware Training Course Code DS SC BU SR DX HW TC Interface Vendor OrCAD Viewlogic Viewlogic Stand-alone Mentor, version 8 Synopsys Cadence Foundation Code OR VL VLS MN8 SY CDN FND Package Type Base System Standard System Extended System Advanced System Code BAS STD EXT ADV Platform IBM PC compatible Sun-4 HP700 IBM RS6000 Code PC1 SN2 HP7 RS6 Media Type CD-ROM Code C 2-9 Development Systems Products Overview 2-10 June 1, 1996 (Version 1.0) Development Systems: Bundled Packages Product Descriptions June 1, 1996 (Version 1.0) This section describes the following products: Foundation Series * * * * Foundation Base System (PC) Foundation Base System with VHDL Synthesis (PC) Foundation Standard System (PC) Foundation Standard System with VHDL Synthesis (PC) Alliance Series * * * * * * * * * * * * OrCAD - Base System (PC) OrCAD - Standard System (PC) Viewlogic - Base System (PC) Viewlogic - Standard System (PC) Viewlogic Stand-alone - Base System (PC) Viewlogic Stand-alone - Standard System (PC) Viewlogic Stand-alone - Extended System (PC) Viewlogic - Standard System (Workstation) Mentor - Standard System (Workstation) Synopsys - Standard System (Workstation) Cadence Standard System (Workstation) Third-Party Alliance - Standard System (PC and Workstation) June 1, 1996 (Version 1.0) 2-11 Development Systems: Bundled Packages Product Descriptions Foundation Series: Foundation Base System (PC) Base System Includes: * Schematic editor with library support for XC2000, XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and XC7300 and XC9500 CPLDs * Functional and Timing Simulator * Core implementation software for FPGAs with device support for XC2000, XC3000/A & XC3100/A up to XC3x42/A, XC4000/E up to XC4003/E, and XC5200 up to XC5204 * Core implementation software for CPLDs with device support for XC7300 and XC9500 * XChecker Diagnostic Cable Support and Updates Include: * Hotline Telephone Support * Access to Xilinx bulletin board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation Package Features - Foundation Base (PC) Feature Libraries and Interface Schematic Editor Simulator (Unlimited) CPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support FND Base 2 FND FND FND Std. BaseV Std. V 2 Notes: 1. XC2000, XC3000, up to XC3042/XC3142; XC4000/E up to XC4003/E; XC5200 up to XC5204 2. XDE Design Editor and Floorplanner not included Required Hardware Environment: * Fully compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 70 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel and two serial ports * 16 MB of RAM 2-12 June 1, 1996 (Version 1.0) Foundation Series: Foundation Base System with VHDL Synthesis (PC) Base System Includes: * Schematic editor with library support for XC2000, XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and XC7300 and XC9500 CPLDs * Functional and Timing Simulator * VHDL Synthesis capability with HDL * Wizard that makes HDL design entry easier and faster with Xilinx specific templates * VHDL multimedia tutorial * Core implementation software for FPGAs with device support for XC2000, XC3000/A & XC3100/A up to XC3x42/A, XC4000/E up to XC4003/E, and XC5200 up to XC5204 * Core implementation software for CPLDs with device support for XC7300 and XC9500 * XChecker Diagnostic Cable Package Features - Foundation (PC) Support and Updates Include: * Hotline Telephone Support * Access to Xilinx bulletin board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation Notes: 1. XC2000, XC3000, up to XC3042/XC3142; XC4000/E up to XC4003/E; XC5200 up to XC5204 2. XDE Design Editor and Floorplanner not included Feature Libraries and Interface Schematic Editor Simulator (Unlimited) CPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support FND Base 2 FND FND FND Std. BaseV Std. V 2 Required Hardware Environment: * Fully compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 70 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel and two serial ports * 16 MB of RAM June 1, 1996 (Version 1.0) 2-13 Development Systems: Bundled Packages Product Descriptions Foundation Series: Foundation Standard System (PC) Standard System Includes: * Schematic editor with library support for XC2000, XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and XC7300 and XC9500 CPLDs * Functional and Timing Simulator (unlimited gates) * Core implementation software for FPGAs with device support for XC2000, XC3000/A & XC3100/A, XC4000/E and XC5200 * Core implementation software for CPLDs with device support for XC7300 and XC9500 * XChecker Diagnostic Cable Support and Updates Include: * Hotline Telephone Support * Access to Xilinx bulletin board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation Package Features - Foundation (PC) Feature Libraries and Interface Schematic Editor Simulator (Unlimited) CPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support FND Base FND FND FND Std. BaseV Std. V Required Hardware Environment: * Fully compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 70 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel and two serial ports * 16 MB of RAM 2-14 June 1, 1996 (Version 1.0) Foundation Series: Foundation Standard System with VHDL (PC) Standard System Includes: * Schematic editor with library support for XC2000, XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and XC7300 and XC9500 CPLDs * Functional and Timing Simulator (unlimited gates) * VHDL Syntheses capability with HDL Wizard that makes HDL design entry easier and faster with Xilinx specific templates * VHDL multimedia tutorial * Core implementation software for FPGAs with device support for XC2000, XC3000/A & XC3100/A, XC4000/E and XC5200 * Core implementation software for CPLDs with device support for XC7300 and XC9500 * XChecker Diagnostic Cable Support and Updates Include: * Hotline Telephone Support * Access to Xilinx bulletin board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation Package Features - Foundation (PC) Feature Libraries and Interface Schematic Editor Simulator (Unlimited) CPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support FND Base FND FND FND Std. BaseV Std. V Required Hardware Environment: * Fully compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 70 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel and two serial ports * 16 MB of RAM June 1, 1996 (Version 1.0) 2-15 Development Systems: Bundled Packages Product Descriptions Alliance Series: OrCAD - Base System (PC) Base System Includes: * Schematic Interface for OrCAD SDT386+ with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E and XC5200 FPGAs and XC7000 and XC9500 Series CPLDs * Functional and Timing Simulation Interface for OrCAD VST386+ * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A and XC3100, XC3100A up to XC3x42, XC3x42A, XC4000/E up to XC4003/E, XC5200 up to XC5204, XC7300, and XC9500 Note: * * * * This package does not include the OrCAD SDT schematic capture or VST simulation tools. They must be purchased separately from OrCAD. XDE-Xilinx Design Editor is not included. This Base Package does not come with a standard one year update contract. Instead, when Xilinx releases a new version of software, customers will be notified and may purchase the Base Update at the listed price. The Base Update is only available to licensees of the DS-OR-BAS-PC1 on a one-for-one basis. Revision Updates Include: * Latest version software and online documentation * Only available to customers who have purchased a Base product before. Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 60 Mbyte hard-disk space * One 3.5" High-Density floppy disk drive * VGA display * One parallel and two serial ports * 16 Mbytes of RAM for all supported XC3000A and XC4000/E FPGAs * Mouse Package Features - OrCAD PC Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Base Std. 2 Notes: 1. XC2000, XC3000, up to XC3042/XC3142; XC4000/E up to XC4003/E; XC5200 up to XC5204 2. XDE Design Editor and Floorplanner not included 2-16 June 1, 1996 (Version 1.0) Alliance Series: OrCAD - Standard System (PC) Standard System Includes: * Schematic Interface for OrCAD SDT386+ with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E FPGAs and XC7000 and XC9500 Series CPLDs * Functional and Timing Simulation Interface for OrCAD VST386+ * X-BLOX Module Generator and Optimizer * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200, XC7300, and XC9500 * Software Support and Updates for first year Note: * This package does not include the OrCAD SDT schematic capture or VST simulation tools. They must be purchased separately from OrCAD. Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes June 1, 1996 (Version 1.0) Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 80 Mbyte hard-disk space * One ISO 9660 compatible CD-ROM drive * VGA display * One parallel and two serial ports * 16 Mbytes of RAM up to XC4008 * 24 Mbytes of RAM for XC3195, XC3195A, XC4010 * 32 Mbytes of RAM for XC4013 * Mouse Package Features - OrCAD PC Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Base Std. 2-17 Development Systems: Bundled Packages Product Descriptions Alliance Series: Viewlogic - Base System (PC) Base System Includes: * Viewlogic Schematic Interface library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs, and XC7000 and XC9500 CPLDs * Viewlogic Functional and Timing Simulation Interface * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A up to XC3x42/A, XC4000/E up to XC4003/E, XC5200 up to XC5204, XC7300, and XC9500 Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows version 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 60 Mbytes disk space * One CD-ROM drive * VGA display * 3-Button Serial Mouse * One parallel and two serial ports * 16 Mbytes of RAM Package Features - Viewlogic PC Note: * * * * * This package does not include Viewlogic schematic capture or simulation tools. They must be purchased separately from Viewlogic or Xilinx (see Stand-alone packages). Interface and libraries support Workview 6.1, Workview PRO and Office Series. XDE-Xilinx Design Editor - not included This Base Package does not come with a standard oneyear update contract. Instead, when Xilinx releases a new version of software, customers will be notified and may purchase the Base Update at the listed price. The Base Update is only available to licensees of the DS-VL-BAS-PC1 on a one-for-one basis. Revision Updates Include: * Latest version software and online documentation * Only available to customers who have purchased a base product before. 2-18 Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support VL VL VLS VLS VLS Base Std. Base Std. Ext. 2 2 1. XC2000, XC3000, up to XC3042/XC3142; XC4000/E up to XC4003/E; XC5200 up to XC5204 2. XDE Design Editor and Floorplanner not included June 1, 1996 (Version 1.0) Alliance Series: Viewlogic - Standard System (PC) Standard System Includes: * Viewlogic Schematic Interface with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7000 and XC9500 CPLDs * Viewlogic Functional and Timing Simulation Interface * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200, XC7300, and XC9500 * X-BLOX Module Generator and Optimizer * Software Support and Updates for the first year Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 90 Mbytes hard-disk space * One ISO 9660 compatible CD-ROM drive * VGA display * 3-Button Serial Mouse * One parallel and two serial ports * 16 Mbytes of RAM for devices up to XC4008 * 24 Mbytes of RAM for XC3195, XC4010 * 32 Mbytes of RAM for XC4013 Note: Package Features - Viewlogic PC * * This package does not include Viewlogic schematic capture or simulation tools. They must be purchased separately from Viewlogic or Xilinx (see Stand-alone packages). Interface and libraries support Workview PRO and Office Series. Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes June 1, 1996 (Version 1.0) Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support VL VL VLS VLS VLS Base Std. Base Std. Ext. 2-19 Development Systems: Bundled Packages Product Descriptions Alliance Series: Viewlogic Stand-alone - Base System (PC) Stand-alone Standard System Includes: * Workview Office Schematic Editor with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7000 and XC9500 CPLDs * Workview Office Functional and Timing Simulation for designs (limited gates) * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200, XC7300, and XC9500 Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows version 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 60 Mbytes disk space * One CD-ROM drive * VGA display * 3-Button Serial Mouse * One parallel and two serial ports * 16 Mbytes of RAM Package Features - Viewlogic PC Note: * * * XDE-Xilinx Design Editor - not included This Base Package does not come with a standard oneyear update contract. Instead, when Xilinx releases a new version of software, customers will be notified and may purchase the Base Update at the listed price. The Base Update is only available to licensees on a one-for-one basis. Revision Updates Include: * Latest version software and online documentation * Only available to customers who have purchased a base product before. Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support VL VL VLS VLS VLS Base Std. Base Std. Ext. 2 2 Notes: VL = Viewlogic, VLS = Viewlogic Stand-alone 1. XC2000, XC3000, up to XC3042/XC3142; XC4000/E up to XC4003/E; XC5200 up to XC5204 2. XDE Design Editor and Floorplanner not included 2-20 June 1, 1996 (Version 1.0) Alliance Series: Viewlogic Stand-alone - Standard System (PC) Stand-alone Standard System Includes: * Workview Office Schematic editor with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7000 and XC9500 CPLDs * Workview Office Functional and Timing Simulation for designs (unlimited gates) * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200, XC7300, and XC9500 * X-BLOX Module Generator and Optimizer * Software Support and Updates for the first year Support and Updates Include: * Hotline Telephone support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes June 1, 1996 (Version 1.0) Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 90 Mbytes hard-disk space * One ISO 9660 compatible CD-ROM drive * VGA display * 3-Button SP Mouse * One parallel and two serial ports * 16 Mbytes of RAM for devices up to XC4008 * 24 Mbytes of RAM for XC3195, XC4010 * 32 Mbytes of RAM for XC4013 Package Features - Viewlogic PC Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support VL VL VLS VLS VLS Base Std. Base Std. Ext. 2-21 Development Systems: Bundled Packages Product Descriptions Alliance Series: Viewlogic Stand-alone - Extended System (PC) Extended Stand-alone System Includes: * Workview Office Schematic editor with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7000 and XC9500 CPLDs * Workview Office Functional, Timing, and VHDL Simulation (unlimited gates) * ViewSynthesis - VHDL synthesis with X-BLOX integration and library synthesis support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E and XC5200 FPGAs * X-BLOX Module Generator and Optimizer * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000/ XC3100, XC4000/E, XC5200, XC7300, and XC9500 * Software Support and Updates if on maintenance Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes 2-22 Required Hardware Environment: * Fully IBM compatible PC386/486/Pentium * MS-Windows 3.1 (minimum) * MS-DOS version 5.0 (minimum) * Minimum 90 Mbytes hard-disk space * One ISO 9660 compatible CD-ROM drive * VGA display * 3-Button Serial Mouse * One parallel and two serial ports * 16 Mbytes of RAM for devices up to XC4008 * 24 Mbytes of RAM for XC3195, XC4010 * 32 Mbytes of RAM for XC4013 Package Features - Viewlogic PC Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support VL VL VLS VLS VLS Base Std. Base Std. Ext. June 1, 1996 (Version 1.0) Alliance Series: Viewlogic - Standard System (Workstation) Standard System Includes: * Schematic Interface for Draw with library support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7000 and XC9500 CPLDs * Functional and Timing Simulation Interface for ViewSim * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200, XC7300, and XC9500 * X-BLOX Module Generator and Optimizer * Software Support and Updates if on maintenance Required Hardware Environment: * 50 to 200 MB hard disk space allocated Xilinx designs. * 32 MB of RAM (minimum) * Color Monitor * Swap Space: 140 MB (minimum) * TCP/IP Software * CD ROM Drive Note: HP700 Series * * * * * This package does not include schematic capture or simulation tools. They must be purchased separately. Interface supports Workview Office and PRO Series Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes June 1, 1996 (Version 1.0) Sun-4 Sparcstation Series * * * Sun OS 4.1.X X-Windows (R3 or R4) Open Windows or Motif HPUX 9.0/9.1 X-Windows (R5) HP_VUE 3.0 Recommended Hardware Environment: * Additional RAM to increase performance Package Features - Viewlogic W/S Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Std. 2-23 Development Systems: Bundled Packages Product Descriptions Alliance Series: Mentor V8 - Standard System (Workstation) Standard System Includes: * Mentor V8 Interface (Mentor Design Architect/QuickSim II Libraries and Interface) * Core Implementation Software for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs and XC7300 and XC9500 CPLDs * X-BLOX Module Generator and Optimizer * Software Support and Updates if on maintenance Required Hardware Environment: * 50 to 200 MB hard disk space allocated Xilinx designs. * 32 MB of RAM (minimum) * Color Monitor * Swap Space: 140 MB (minimum) * TCP/IP Software * CD ROM Drive Note: * * * * * This package does not include Design Architect schematic capture, or QuickSim II simulation tools. Contact your local Mentor Graphics sales office to purchase these tools. AutoLogic synthesis program, libraries and interface are available from Mentor Graphics. Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes 2-24 Sun-4 Sparcstation Series Sun OS 4.1.X X-Windows (R3 or R4) Open Windows or Motif HP700 Series * * * HPUX 9.0/9.1 X-Windows (R5) HP_VUE 3.0 Recommended Hardware Environment: * Additional RAM to increase performance Package Features - Mentor W/S Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Std. June 1, 1996 (Version 1.0) Alliance Series: Synopsys - Standard System (Workstation) Standard System Includes: * XC3000, XC3000A, XC3100, XC3100A, XC4000/E and XC5200 synthesis library * Core Implementation Software for XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 FPGAs, and XC7300 and XC9500 CPLDs * X-BLOX Module Generator and Optimizer * Works with Synopsys Design Compiler and FPGA Compiler * Translator from Synopsys to Xilinx XNF * Software Support and Updates if on maintenance Note: * This package does not include Synopsys Design Compiler or FPGA Compiler. These must be purchased separately from Synopsys. Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes June 1, 1996 (Version 1.0) Required Hardware Environment: * 50 to 200 MB hard disk space allocated Xilinx designs. * 32 MB of RAM (minimum) * Color Monitor * Swap Space: 140 MB (minimum) * TCP/IP Software * CD ROM Drive Sun-4 Sparcstation Series * * * Sun OS 4.1.X X-Windows (R3 or R4) Open Windows or Motif HP700 Series * * * HPUX 9.0/9.1 X-Windows (R5) HP_VUE 3.0 Recommended Hardware Environment: * Additional RAM to increase performance Package Features - Synopsys W/S Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Std. 2-25 Development Systems: Bundled Packages Product Descriptions Alliance Series: Cadence - Standard System (Workstation) Standard System Includes: * Cadence Interface (Composer and Concept Schematic Libraries and Verilog and RapidSim simulation models and interfaces) * Core Implementation Software for XC2000, XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs, and XC7300 and XC9500 CPLDs * LogiBlox Module Generator and Optimizer * Software Support and Updates if on maintenance Note: * * This package does not include Composer/Concept schematic capture, or Verilog/RapidSim simulation tools. Contact your local Cadence sales office to purchase these tools FPGA designer (Synergy based top-down FPGA design tool) is available from Cadence. Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes 2-26 Required Hardware Environment: * 50 to 200 MB hard disk space allocated Xilinx designs. * 32 MB of RAM (minimum) * Color Monitor * Swap Space: 140 MB (minimum) * TCP/IP Software * CD ROM Drive Sun-4 Sparcstation Series * * * Sun OS 4.1.X X-Windows (R3 or R4) Open Windows or Motif HP700 Series * * * HPUX 9.0/9.1 X-Windows (R5) HP_VUE 3.0 Recommended Hardware Environment: * Additional RAM to increase performance Package Features - Synopsys W/S Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Std. June 1, 1996 (Version 1.0) Alliance Series: Third Party Alliance - Standard System Standard System Includes: * X-BLOX Module Generator & Optimizer * Core Implementation Software for CPLDs and FPGAs with device support for XC2000, XC3000/A, XC3100/A, XC4000/E, XC7300, and XC9500 * Software Support and Updates for the first year Note: Required Hardware Environment (Workstation): * 50 to 200 MB hard disk space allocated Xilinx designs. * 32 MB of RAM (minimum) * Color Monitor * Swap Space: 140 MB (minimum) * TCP/IP Software * CD-ROM Drive * Sun-4 Sparcstation Series Purchase schematic and simulation tools and interfaces and libraries from a Xilinx 3rd-Party Alliance Partner Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes Required Hardware Environment (PC): * Fully compatible PC386/486/Pentium * MS-DOS version 5.0 (minimum) * MS-Windows 3.1 (minimum) * Minimum 80 MB hard disk space * One ISO 9660-type CD-ROM drive * VGA display (higher resolutions supported) * One parallel and two serial ports * 16 MB of RAM for devices up to XC4008 * 24 MB of RAM for XC3195A, XC4010 * 32 MB of RAM for XC4013 * Mouse June 1, 1996 (Version 1.0) * * * Sun OS 4.1.X X-Windows (R3 or R4) Open Windows or Motif HP700 Series * * * HPUX 9.0/9.1 X-Windows (R5) HP_VUE 3.0 IBM RS6000 * * AIX 3.2 X-Windows Support Package Features - Third Party Alliance Feature Libraries and Interface Schematic Editor Simulator (Limited) Simulator (Unlimited) EPLD Devices FPGA Limited1 FPGA 2K, 3K, 4K, 5K Core Implementation Synthesis Tools X-BLOX XChecker Cable Hotline Support Std. 2-27 Development Systems: Bundled Packages Product Descriptions 2-28 June 1, 1996 (Version 1.0) Development Systems: Individual Product Descriptions June 1, 1996 (Version 1.0) This section describes the following products: * * * * * * * * * FPGA Core Implementation - DS-502 CPLD Core Implementation - DS-560 Schematic and Simulator Interfaces X-BLOX - DS-380 Xilinx ABEL Design Entry - DS-371 Xilinx ABEL Design Entry - DS-571 Xilinx-Synopsys Interface (XSI) - DS401 XChecker Cables Demonstration Boards June 1, 1996 (Version 1.0) 2-29 Development Systems: Individual Product Descriptions FPGA Core Implementation - DS-502 Core Implementation Includes: * Software to process an XNF file for an XC2000, XC3000, XC3000A, XC3100, XC3100A, XC4000/E, XC5200 device into a BIT or PROM file that can be downloaded * Automatic or interactive implementation * XACT PerformanceTM system-level timing-driven mapping, placement, and routing * Fast incremental design capability * Advanced logic reduction algorithms * Comprehensive design rule checker * Powerful design editor * Static timing analyzer * Bitstream and PROM file generators * Original hierarchical netlist-based back-annotation * Software Support and Updates if on maintenance Support and Updates Include: * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes 2-30 Hardware Requirements: PC * * * * * * * * * * Fully compatible PC386/486 MS-Windows 3.1 (minimum) MS-DOS version 5.0 (minimum) Minimum 50 Mbytes hard-disk space for Xilinx software One 3.5" High-Density floppy disk drive or ISO 9660 type CD-ROM drive VGA display One parallel and two serial ports 16 Mbytes of RAM for devices up to XC4008 32 Mbytes of RAM for XC3195, XC4010, and XC4013 Mouse Workstations * * 65 Mbytes hard-disk drive space for Xilinx software Other hardware requirements are same as for the Standard package June 1, 1996 (Version 1.0) CPLD Core Implementation - DS-560 CPLD Core Implementation Includes: * Fitter software to process XC7000 and XC9500 family designs * Automatic optimization and mapping * Automatic use of UIM resources * Automatic arithmetic functions * Complete optimization and collapsing * High speed compilation Support and Updates Include: * Documentation Updates * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX XACT-CPLD provides a complete, user-friendly, multi-platform design environment for implementing behavioral or schematic designs. XACT-CPLD allows users to easily create, verify, and implement logic designs targeting the entire range of Xilinx XC7000 and XC9500 series devices. Automatic Logic Mapping and Optimization The automatic partitioning and mapping capabilities of XACT-CPLD allow the designer to concentrate on design functionality without concern for physical implementation; all device resources are automatically mapped and interconnected with no user intervention required. In addition, automatic logic optimization insures the highest performance and the most efficient usage of device resources. Because of these automatic features, the user does not need a detailed knowledge of the device architecture. However, XACT-CPLD also allows the designer to fully control the physical mapping of logic and I/O resources when necessary. Required Hardware Environment * Fully compatible PC 486/Pentium * MS-Windows 3.1 * MS-DOS version 5.0 (minimum) * Minimum 26 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel port for EZTag download cable * One serial port for Windows compatible mouse * 16 MB of RAM June 1, 1996 (Version 1.0) Feature Summary * Advanced XACTstep v6.0 XC7000 implementation software with fully automatic device selection, multiple pass optimization, partitioning and mapping, and timing driven fitting. * XC9500 implementation software with advanced pinlocking capability. * EZTag download software supporting the programming of multiple Xilinx CPLDs anywhere in a JTAG chain. * Includes XC9500 Synopsys, Viewlogic, and OrCAD interfaces. * On-line tutorials and documentation * Static timing report * Schematic Design Entry -- XACT-CPLD, coupled with the appropriate external interface, provides a schematic library that includes familiar TTL and PAL components for use with industry-standard schematic editors such as those available from OrCAD, ViewLogic, Mentor Graphics, and Cadence Design Systems. * Simulation Support -- XACT-CPLD supports various third-party simulators such as ViewLogic PROsim, OrCAD VST, Mentor QuickSim, Cadence Verilog, and Cadence RapidSim. Both functional and timing simulation are supported. * Board-Level Simulation Support -- XACT-CPLD device models are available from Logic Modeling Corporation for board-level simulation on a variety of platforms. * High-Speed Compilation -- Design iterations are easily performed and the results are quickly reported. * Predictable Design Performance -- The PAL-like architecture of the Xilinx CPLDs provides fixed predictable delays independent of physical placement, routing, or device utilization. * Automatic Mapping and Logic Optimization -- Device resources are automatically mapped for optimal efficiency and high performance. Users can focus on design functionality without concern for the physical implementation in the device. * Complete Design Control -- Users have the option to override the automatic features of XACT-CPLD and selectively control any or all device resources. * Multiple Platform Support -- XACT-CPLD runs on Sun, HP, and PC (DOS) platforms 2-31 Development Systems: Individual Product Descriptions Schematic and Simulator Interfaces X-BLOX - DS-380 Interfaces and libraries for several popular schematic editors and timing simulators are available as individual products, for users that already own an editor and simulator. For designers looking for a design entry tool, Xilinx offers Xilinxspecific versions of Viewlogic's schematic editor, simulator, and ViewSynthesis VHDL synthesizer and VHDL simulator. X-BLOX Includes: * Parameter-based schematic and function-generation tool. Allows block-diagram design entry using generic function modules. * Works with many Schematic Entry Interfaces (Viewlogic, Mentor, OrCAD, Cadence and other Alliance Partners) * Expert system that automatically utilizes the advanced features of the XC5200 family, XC4000/E family and XC3000A and XC3100A families * Schematic library with more than 30 frequently-used generic modules (adders, counters, decoders, registers, MUXes, etc.) * Software Support and Updates for first year The following products are available for the platforms noted in parentheses: DS-390 Viewlogic schematic editor with Xilinx libraries and interface (PC) DS-290 Viewlogic simulator with Xilinx libraries and interface (PC) DS-391 Libraries and interfaces that support Viewlogic's Workview Office Series, PRO Series, and Powerview design entry and simulation tools (PC, Sun, HP700) DS-344 Libraries and interfaces for Mentor Graphics Design Architect schematic editor and QuickSim II simulator (HP700, Sun) DS-35 Libraries and interfaces for OrCAD 386+ schematic editor and VST 386+ simulator (PC) Note: * * XC5200, XC4000/E and XC3000A, XC3100A families are supported. XC2000, XC3000, and XC3100 are not supported. Additional Requirements: Five Mbytes hard-disk space for program and design files Features * Complete set of primitive and macro libraries for all FPGA and CPLD products * Full simulation models provides for accurate post-layout timing analysis * Unified libraries allow easy migration between all Xilinx architectures, including CPLDs * Converts schematic drawings to Xilinx Netlist Format (XNF) output * Converts XNF files to format compatible with logic and timing simulators * Supports unlimited levels of hierarchy * Includes one year of support and updates * All above products can be purchased with core implementation tools as a package, offering easier upgrading and reduced cost. 2-32 June 1, 1996 (Version 1.0) Xilinx ABEL Design Entry - DS-371 The Xilinx ABEL system gives designers the ability to enter Xilinx designs using the industry standard ABEL Hardware Description Language (ABEL-HDL). Designers can describe circuits with Boolean equations, state machines and truth tables. State machine and logic optimization software automatically generates efficient logic for Xilinx devices. Many designs contain portions of logic that are best described in a text-based format; some designs can be completely described in this way. In the Xilinx ABEL system, Xilinx designs can be created with Boolean equations, state machines, and truth tables. The ABEL HDL makes designing quick and simple. Intelligent state machine and logic optimization software automatically creates efficient, fast state machines. The ABEL simulator allows functional simulation of ABEL-HDL designs. CPLD designs may be entered entirely with ABEL-HDL. FPGA designs should be entered via a combination of XABEL and a schematic editor to take optimal advantage of the Xilinx architectures. The recommended design flow is to enter designs schematically with functional blocks that refer to logic described in ABEL-HDL. From inside the Xilinx ABEL environment, designers create and compile the logic in these functional blocks. The Xilinx XMake program then compiles the complete design to a bitstream that can be downloaded to a Xilinx device. XMake automatically calls the software that merges the various design files (schematics and ABEL-HDL), partitions, places and routes the design and creates the final bitstream. The design can then be verified with a simulator and a timing analyzer, as well as verified in-circuit. One-Hot Encoding For the flop-flop rich, fan-in limited Xilinx FPGA architecture, One-Hot Encoding (OHE) is the preferred technique for implementing high-performance state machines. OHE is also know as state-per-bit encoding, since it uses one flipflop per state. OHE takes advantage of the abundance of flip-flops in Xilinx FPGAs to reduce the levels of logic required to implement a state machine. This implementation significantly increases performance over fully encoded state machines, the traditional technique used in PLDs. Xilinx ABEL automatically uses OHE on symbolic state machines created in ABEL-HDL for FPGAs. Features * State machine and Boolean equation entry via DATA I/O's ABEL language * ABEL Functional Simulator * Xilinx-specific ABEL environment, compiler, and optimizer for FPGAs * Automatic symbolic One-Hot encoding or fully encoded state-machine implementation * Ability to integrate ABEL designs with other schematic elements * Software Support and Updates for the first year Support and Updates Include * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Software Updates if on maintenance * Online Documentation * World Wide Web Access * Technical Newsletter * Extensive Application Notes Additional Requirements * 10 Mbytes hard-disk space for program and design files June 1, 1996 (Version 1.0) 2-33 Development Systems: Individual Product Descriptions Xilinx ABEL Design Entry - DS-571 XABEL-CPLD is the new Xilinx development system designed for PAL and CPLD users. With this completely self contained system, customers can quickly and easily integrate their logic into Xilinx CPLDs using the industry-standard ABEL hardware description language. XABEL-CPLD Includes * Familiar Data I/O ABEL, Windows based environment for design entry, simulation and fitting * Hierarchical design entry and JEDEC file conversion * Functional simulation with graphical waveform viewer * Static timing report * Advanced XACTstep v6.0 XC7000 and XC9500 fitters with fully automatic device selection, multiple pass optimization, partitioning and mapping, and timing driven fitting * EZTag download software and cable * Online tutorial and online help reduces learning curve Support and Updates Include * Hotline Telephone Support * Access to Xilinx Technical Bulletin Board * Apps FAX and E-Mail * Online tutorial and help Feature Summary * Familiar Data I/O ABEL, Windows based environment for design entry, simulation and fitting provides a simple, single push button design flow * Industry-standard ABEL-HDL supports state machines, high level logic descriptions, truth tables and equation entry * Hierarchical design entry and JEDEC file conversion enables reuse of existing PAL codes, simplifying PAL integration into Xilinx CPLDs * Functional simulation with graphical waveform viewer and static timing reports facilitate rapid design verification * Advanced XACTstep v6.0 fitter's architecture specific knowledge let's the user focus on design functionality * Online tutorial leads users through the entire design process in minutes * Extensive online help system places all documentation just a mouse-click away Required Hardware Environment * Fully compatible PC 486/Pentium * MS-Windows 3.1 * MS-DOS version 5.0 (minimum) * Minimum 45 MB hard disk space * ISO 9660 type CD ROM drive * VGA display * One parallel port for EZTag download cable * One serial port for Windows compatible mouse * 16 MB of RAM 2-34 June 1, 1996 (Version 1.0) Xilinx-Synopsys Interface (XSI) - DS-401 This interface and library product supports VHDL and Verilog/HDL synthesis using either the Synopsys Design Compiler or FPGA Compiler products Features * Synthesis libraries for: XC3000/XC3100, XC4000/E and XC5000 family FPGAs XC7000 and XC9500 family CPLDs * X-BLOX synthetic library * Translator from Synopsys to Xilinx XNF * Ability to integrate models with other design * Available for Sun-4, and HP700, platforms DS-401 (XSI) lets the Synopsys FPGA Compiler and Design Compiler target the XC3000, XC3100, XC4000/E, and XC5000 FPGA families and XC7500 and XC9500 CPLD families. XSI consists of synthesis libraries, a translator from Synopsys to XNF, and a library of X-BLOX functions implemented using Synopsys DesignWare. Simulation Support Behavioral simulation before compilation using Synopsys VHDL System Simulator (VSS) is supported. In the future, gate-level simulation of designs after layout will be supported as well. Support and Updates * Software updates for one year * Documentation updates * Hotline Telephone Support for the first six months * Access to Xilinx bulletin board * Apps FAX Notes * * Language Support Either VHDL or Verilog/HDL entry is supported through the use of the appropriate Synopsys language compiler. Compiler Support FPGA Compiler is highly recommended for XC4000/E and XC5200 designs due to its specific XC4000/E algorithms. Design Compiler is sufficient for XC3000 and XC3100 designs. June 1, 1996 (Version 1.0) * This product does not support the Synopsys Test Compiler A Synopsys Standard package is available which combines XSI (DS-401) and FPGA core implementation tools (DS-502) in one product. Packages offer reduced prices over modules purchased separately. The X-BLOX library allows Synopsys software to automatically insert certain X-BLOX functions (adders, subtracters, and comparators) where possible for maximum performance. In-warranty XSI customer receive X-BLOX as an automatic upgrade. 2-35 Development Systems: Individual Product Descriptions XChecker Cables Demonstration Board - FPGA XChecker Cable Package Includes: * XChecker cable * Flying wire jumper * Flat header jumper * XChecker diagnostics fixture FPGA Demo Board Includes: * Three 7-segment displays (one for XC3000, XC3000A and two for XC4000/E) * Two, octal DIP switches for inputs to LCA devices (one for XC3000 and one for XC4000/E) * Test pins for access to all LCA I/O * XC4003A in 84-pin PLCC package * XC3020A in 68-pin PLCC package * Two 8-segment bar displays (one for XC3000A and one for XC4000/E) * Program, Reset, and Spare momentary contact switches XChecker Cable Features: * Provides bitstream and PROM-file download capability to FPGAs * Provides readback capability * Works with serial ports on IBM 386/486/Pentium and compatibles * Compatible with XACT XChecker diagnostics software and the XACT Probe utility * Flying-wire and flat-header jumpers provide easy access during prototyping 2-36 FPGA Demo Board Features * Operates from a 5-V power supply * Compatible with XChecker and parallel download cables * Supports Master-Serial configuration mode for interface to Xilinx serial PROMs * Two sockets, one can be used for any XC2000, XC3000 or XC3100 device in a 68-pin PLCC package, the other can be used for any XC4000/E device in an 84 pin PLCC package * Provides sockets for up to three daisy-chained serial PROMs * Includes 3 inch by 3 inch prototyping area * Daisy-chain configuration capability (XC4000/E must be first in the chain) June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products CPLD Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors CPLD Products Table of Contents CPLD Products XC9500 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 In-System Programmable CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 XC95180 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 XC95432 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 XC95576 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 XC7300 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 XC7300 CMOS CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 XC7318 18-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81 XC7336/XC7336Q 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 XC7354 54-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 XC7372 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107 XC73108 108-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 XC73144 144-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 XC7300 Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135 XC7200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145 XC7236A 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147 XC7272A 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163 XC9500 Series Table of Contents XC9500 In-System Programmable CPLD Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastCONNECT Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstepTM Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-3 3-3 3-5 3-6 3-8 3-11 3-12 3-13 3-14 3-14 3-14 3-14 3-15 3-15 3-16 3-16 3-16 XC9536 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-17 3-17 3-19 3-19 3-19 3-20 3-21 3-21 3-22 3-22 XC9572 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3-23 3-23 3-25 3-26 XC95108 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3-27 3-27 3-29 3-29 3-29 3-30 3-1 XC9500 Series Table of Contents XC95108 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3-32 3-32 3-33 3-33 XC95144 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-35 3-35 3-37 3-38 3-39 XC95180 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95180 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95180 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3-41 3-41 3-43 3-44 3-45 3-45 XC95216 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3-47 3-47 3-49 3-49 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-55 XC95288 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 3-57 3-57 3-59 3-60 3-61 3-62 3-63 XC95432 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 XC95576 In-System Programmable CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 3-2 XC9500 In-System Programmable CPLD Family June 1, 1996 (Version 1.0) Preliminary Product Information Features throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free reconfigurations and system field upgrades. * * * * * * * * * * * * * High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz Large density range - 36 to 576 macrocells with 800 to12,800 usable gates 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs with 3.3 V or 5 V I/O capability PCI compliant (-5, -7, -10 speed grades) Advanced 0.6m CMOS 5V FastFLASH technology Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be configured for 3.3 V or 5 V operation. All outputs provide 24 mA drive. Architecture Description Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1. Description The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members. As shown in Table 1, the nine devices of the XC9500 family range in logic density from 800 to over 12,800 usable gates with 36 to 576 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming June 1, 1996 (Version 1.0) 3-3 XC9500 In-System Programmable CPLD Family 3 JTAG Port JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 18 I/O/GSR I/O/GTS 2 or 4 Function Block N Macrocells 1 to 18 X5877 Figure 1: XC9500 Architecture Table 1: XC9500 Device Family Macrocells Usable Gates Registers tPD (ns) tSU (ns) tCO (ns) fCNT (MHz) fSYSTEM (MHz) XC9536 36 800 36 5 4.5 4.5 125 100 XC9572 72 1,600 72 7.5 5.5 5.5 125 83 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576 108 144 180 216 288 432 576 2,400 3,200 4,000 4,800 6,400 9600 12,800 108 144 180 216 288 432 576 7.5 7.5 10 10 10 10 12 5.5 5.5 6.5 6.5 6.5 6.5 9.5 5.5 5.5 6.5 6.5 6.5 6.5 9.5 125 125 111 111 111 111 100 83 83 67 67 67 67 67 Preliminary Note: fCNT = Operating frequency for 16-bit counters fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs. 3-4 June 1, 1996 (Version 1.0) Table 2: Available Packages and Device I/O Pins 44-Pin PLCC 44-Pin VQFP 84-Pin PLCC 100-Pin PQFP 100-Pin TQFP 160-Pin PQFP 208-Pin HQFP 304-Pin HQFP XC9536 34 34 XC9572 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576 69 72 72 69 81 81 108 81 133 133 168 133 168 168 192 232 232 Note: Does not include the dedicated JTAG pins. Function Block Each Function Block, as shown in Figure 2, is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB supports local feedback paths that allow any number of FB outputs to drive into its own programmable ANDarray without going outside the FB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and Macrocell 1 Programmable AND-Array From FastCONNECT Switch Matrix Product Term Allocators 18 To FastCONNECT Switch Matrix 36 18 OUT 18 PTOE To I/O Blocks Macrocell 18 1 Global Set/Reset 3 Global Clocks X5878 Figure 2: XC9500 Function Block June 1, 1996 (Version 1.0) 3-5 XC9500 In-System Programmable CPLD Family Macrocell Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure 3. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product 36 term allocator associated with each macrocell selects how the five direct terms are used. The macrocell register can be configured as a D-type or Ttype flip-flop, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user-defined preload state (default to 0 if unspecified). Global Set/Reset Global Clocks 3 Additional Product Terms (from other macrocells) Product Term Set 1 0 To FastCONNECT Switch Matrix S D/T Q Product Term Allocator Product Term Clock R Product Term Reset OUT Product Term OE PTOE To I/O Blocks Additional Product Terms (from other macrocells) X5879 Figure 3: XC9500 Macrocell Within Function Block 3-6 June 1, 1996 (Version 1.0) All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a product term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-defined state. Macrocell Product Term Set Product Term Clock S D/T R Product Term Reset I/O/GSR Global Set/Reset I/O/GCK1 Global Clock 1 I/O/GCK2 I/O/GCK3 Global Clock 2 Global Clock 3 X5880 Figure 4: Macrocell Clock and Set/Reset Capability June 1, 1996 (Version 1.0) 3-7 XC9500 In-System Programmable CPLD Family Product Term Allocator The product term allocator controls how the five direct product terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. terms can be available to a single macrocell with only a small incremental delay of tPTA, as shown in Figure 6. Product Term Allocator Product Term Allocator Macrocell Product Term Logic Product Term Allocator X5894 Figure 5: Macrocell Logic Using Direct Product Term The product term allocator can re-assign other product terms within the FB to increase the logic capacity of a macrocell beyond five direct terms. Any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the FB. Up to 15 product Macrocell Logic With 15 P-Terms Product Term Allocator X5895 Figure 6: Product Term Allocation With 15 Product Terms 3-8 June 1, 1996 (Version 1.0) The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in Figure 7. In this example, the incremental delay is only 2*tPTA. All 90 product terms are available to any macrocell, with a maximum incremental delay of 8*tPTA. Product Term Allocator Macrocell Logic With 2 Product Terms Product Term Allocator Product Term Allocator Macrocell Logic With 18 Product Terms Product Term Allocator X5896 Figure 7: Product Term Allocation Over Several Macrocells June 1, 1996 (Version 1.0) 3-9 XC9500 In-System Programmable CPLD Family The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell To Upper Macrocell Product Term Allocator Product Term Set Global Set/Reset 1 0 S D/T Q Global Clocks Product Term Clock R Product Term Reset Global Set/Reset Product Term OE From Lower Macrocell To Lower Macrocell X5881 Figure 8: Product Term Allocator Logic 3-10 June 1, 1996 (Version 1.0) FastCONNECT Switch Matrix The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be programmably selected to drive each FB with a uniform delay. FastCONNECT Switch Matrix The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fanin of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable. Function Block I/O Block (36) 18 D/T Q I/O Function Block I/O Block (36) 18 D/T Q I/O Wired-AND Capability X5882 Figure 9: FastCONNECT Switch Matrix June 1, 1996 (Version 1.0) 3-11 XC9500 In-System Programmable CPLD Family I/O Block The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 10 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary with the VCCIO voltage. The output enable may be generated from one of four options: a product term signal from the macrocell, any of the global OE signals, always "1", or always "0". There are two global output enables for devices with up to 144 macrocells, and four global output enables for devices with 180 or more macrocells. Both polarities of any of the global 3-state control (GTS) pins may be used within the device. To other Macrocells I/O Block VCCINT To FastCONNECT Switch Matrix Pull-up Resistor Macrocell I/O OUT (Inversion in AND-array) Product Term OE PTOE UserProgrammable Ground 1 0 Slew Rate Control I/O/GTS1 Global OE 1 I/O/GTS2 I/O/GTS3 I/O/GTS3 Global OE 2 Global OE 3 Available in XC95180, XC95216 and XC95288 Global OE 4 X5899 Figure 10: I/O Block and Output Enable Capability 3-12 June 1, 1996 (Version 1.0) Each output has independent slew rate control. Output edge rates may be programmably slowed down to reduce system noise (with an additional time delay of tSLEW). See Figure 11. voltage supply. Figure 12 shows how the XC9500 device can be used in 5 V only and mixed 3.3 V/5 V systems. Each IOB provides user programmable ground pin capability. This allows device I/O pins to be configured as additional ground pins. By tying strategically located programmable ground pins to the external ground connection, system noise generated from large numbers of simultaneous switching outputs may be reduced. The capability to lock the user defined pin assignments during design changes depends on the ability of the architecture to adapt to unexpected changes. The XC9500 devices have architectural features that enhance the ability to accept design changes while maintaining the same pinout. A control pull-up resistor (typically 10K ohms) is attached to each device I/O pin to prevent device pins from floating when the device is not in normal user operation. This resistor is active during device programming mode and system power-up. It is also activated for an erased device. The resistor is deactivated during normal operation. The output driver is capable of supplying 24 mA output drive. All output drivers in the device may be configured for either 5 V TTL levels or 3.3 V levels by connecting the device output voltage supply (VCCIO) to a 5 V or 3.3 V Pin-Locking Capability The XC9500 provides 100% routing within the FastCONNECT switch matrix, and incorporates a flexible Function Block that allows block-wide allocation of available p-terms. This provides a high level of confidence of maintaining both input and output pin assignments for unexpected design changes. For extensive design changes requiring higher logic capacity than is available in the initially chosen device, the new design may be able to fit into a larger pin-compatible device using the same pin assignments. Output Voltage Output Voltage Standard Slew-Rated Limited Slew-Rated Limited tSLEW tSLEW 1.5 V 1.5 V Standard Time 0 Time 0 (b) (a) X5900 Figure 11: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs 5V 5 V CMOS 5 V CMOS 5V 0V VCCIO VCCINT 5 V TTL or 0V 3.3 V VCCINT VCCIO 5 V TTL or 5 V TTL 3.6 V IN XC9500 CPLD 0V 3.3 V 5V 5V 3.3 V OUT IN 3.3 V GND 0V XC9500 CPLD 0V 0V or 3.3 V 3.6 V ~4V 3.3 V OUT 0V or 3.3 V GND 0V (a) (b) X5901 Figure 12: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems June 1, 1996 (Version 1.0) 3-13 XC9500 In-System Programmable CPLD Family In-System Programming XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure 13. In-system programming offers quick and efficient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. Refer to the application note on the XC9500 JTAG instruction set for additional information. Design Security XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 3 shows the four different security settings available. The system designer must ensure that the system is wellbehaved before the XC9500 device is programmed with a user pattern. During XC9500 programming, all I/Os are tristated and pulled-up. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. Erasing the entire device is the only way to reset the read security bit. XC9500 devices also can be programmed by third-party device programmers. The write security bits provide added protection against accidental device erasure or reprogramming by the user. Once set, the write-protection may be deactivated when the device needs to be reprogrammed with a valid pattern. All XC9500 CPLDs provide a minimum endurance level of 10,000 in-system program/erase cycles. Each device meets all functional, performance, and data retention specifications within this endurance limit. IEEE 1149.1 Boundary-Scan (JTAG) XC9500 devices fully support IEEE 1149.1 boundary-scan (JTAG). Extest, Sample/Preload, Bypass, Usercode, Intest, Idcode, and Highz instructions are supported in each device. All in-system programming, erase, and verify instructions are implemented as fully compliant extensions of the 1149.1 instruction set. Table 3: Data Security Options Read Security Default Write Security Endurance Set Read Allowed Read Inhibited Program/Erase Allowed Program/Erase Allowed Read Allowed Read Inhibited Program/Erase Inhibited Program/Erase Inhibited Default Set X5905 V CC GND (a) (b) X5902 Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable 3-14 June 1, 1996 (Version 1.0) Low Power Mode All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature allows the device power to be significantly reduced. Each individual macrocell may be programmed in lowpower mode by the user. Performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for lowpower operation to reduce the overall power dissipation. Macrocells programmed for low-power mode incur additional delay (tLP) in pin-to-pin combinatorial delay as well as register setup time. Product term clock to output and product term output enable delays are unaffected by the macrocell power-setting. Timing Model The uniformity of the XC9500 architecture allows a simplified timing model for the entire device. The basic timing model is shown in Figure 14. Detailed timing information on a design, including secondary parameters, can be easily obtained from the timing report in the XACTstep development system. The basic timing model is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. Table 4 shows how each of the key timing parameters is affected by the product term allocator (if needed), low-power setting, and slew-limited setting. The product term allocation time depends on the logic span of the macrocell function, which is defined as one less than the maximum number of allocators in the product term path. If only direct product terms are used, then the logic span is 0. The Figure 6 example shows that up to 15 product terms are available with a span of 1. In the case of Figure 7, the 18 product term function has a span of 2. tSU Combinatorial Logic Combinatorial Logic D/T Q tCO Setup Time = tSU Propagation Delay = tPD Clock to Out Time = tCO (b) (a) tPSU Combinatorial Logic D/T Q Combinatorial Logic P-Term Clock Path D/T Q tPCO Setup Time = tPSU Clock to Out Time = tPCO Internal System Cycle Time = tSYSTEM (c) (d) All resources within FB using local Feedback Combinatorial Logic Combinatorial Logic D/T Q Combinatorial Logic Internal Cycle Time = tCNT (e) Propagation Delay = tPD + tFBK With Feedback (f) Setup Time Combinatorial Logic Combinatorial Logic D/T Q tCO Setup Time = tSU + tFBK Clock to Out Time = tCO With Feedback (g) X5903 Figure 14: Basic Timing Model June 1, 1996 (Version 1.0) 3-15 XC9500 In-System Programmable CPLD Family Power-Up Characteristics The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until VCCINT supply voltage is at a safe level (approximately 3.8 V). During this time, all device pins and JTAG pins are disabled, and all device outputs are disabled with the IOB pull-up resistors (~ 10K ohms) enabled. See Table 5. When the supply voltage reaches a safe level, all user registers become initialized (within 100 s typical), and the device is immediately available for operation, as shown in Figure 15. If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with the IOB pull-up resistors enabled. The JTAG pins are enabled to allow the device to be programmed at any time. If the device is programmed, the device inputs and outputs take on their configured states for normal operation. The JTAG pins are enabled to allow device erasure or boundary-scan tests at any time. In mixed 3.3 V/5 V systems, it is recommended that VCCINT VCCIO at all times during the power-up sequence. XACTstepTM other HDL languages in a variety of software front-endtools. The XACTstep development system can be used to implement the design and generate a JEDEC bitmap which can be used to program the XC9500 device. The XACTstep development system includes JTAG download software that can be used to program the devices via a download cable. FastFLASH Technology An advanced 0.6 m CMOS Flash process is used to fabricate all XC9500 devices. Specifically developed for Xilinx in-system programmable CPLDs, the process provides high performance logic capability and endurance of 10,000 program/erase cycles. VCCINT 3.8 V (Typ) 0V No Power Development System The XC9500 CPLD family is fully supported by the Xilinx XACTstep development system. The designer can create the design using ABEL, schematics, equations, VHDL or Quiescent State User Operation Quiescent State Initialization of User Registers No Power X5904 Figure 15: Device Behavior During Power-up Table 4: Timing Model Parameters Description Parameter Product Term Allocator1 Propagation Delay Global Clock Setup Time Global Clock-to-output Product Term Clock Setup Time Product Term Clock-to-output Internal System Cycle Period Feedback Time tPD tSU tCO tPSU tPCO tSYSTEM tFBK + tPTA * S + tPTA * S - + tPTA * S Macrocell Low-Power Setting + tLP + tLP - + tLP Output Slew-Limited Setting + tSLEW - + tSLEW - - + tPTA * S + tPTA * S - + tLP + tLP + tSLEW - - Note: 1. S = the logic span of the function, as defined in the text. Table 5: XC9500 Device Characteristics Device Feature IOB Pull-up Resistors Device Outputs Device Inputs and Clocks Function Block JTAG Controller 3-16 Quiescent State Enabled Disabled Disabled Disabled Disabled Erased Device Operation Enabled Disabled Disabled Disabled Enabled Valid User Operation Disabled As Configured As Configured As Configured Enabled June 1, 1996 (Version 1.0) XC9536 In-System Programmable CPLD June 1, 1996 (Version 1.0) Preliminary Product Specification Features Power Management * 5 ns pin-to-pin logic delays on all pins * fCNT to 125 MHz * 36 macrocells with 800 usable gates * Up to 34 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-5, -7, -10 speed grades) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 44-pin PLCC and 44-pin VQFP packages Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview. June 1, 1996 (Version 1.0) ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device. ance (83) erform High P Typical ICC (mA) Description Operating current for each design can be approximated for specific operating conditions using the following equation: (50) (50) ower Low P (30) 0 50 Clock Frequency (MHz) 100 X5920 Figure 1: Typical ICC vs. Frequency For XC9536 3-17 XC9536 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 X5919 Figure 2: XC9536 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-18 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Warning: Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operating Conditions 1 Symbol VCCINT Parameter Supply voltage for internal logic and input buffer VCCIO Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Input signal transition time VIL VIH VO TIN Min 4.75 (4.5) 4.75 (4.5) 3.0 Max 5.25 (5.5) 5.25 (5.5) 3.6 Units V 0 2.0 0 0.80 VCCINT +0.5 VCCINT + 0.5 50 V V V ns V V Note 1. Numbers in parenthesis are for industrial-temperature range versions. DC Characteristics Over Recommended Operating Conditions Symbol VOH VOL IIL IIH CIN ICC Parameter Output high voltage for 5 V operation Test Conditions IOH = -4.0 mA VCC = Min Output high voltage for 3.3 V operation IOH = -3.2 mA VCC = Min Output low voltage for 5 V operation IOL = 24 mA VCC = Min Output low voltage for 3.3 V operation IOL = 10 mA VCC = Min Input leakage current VCC = Max VIN = GND or VCC I/O high-Z leakage current VCC = Max VIN = GND or VCC I/O capacitance VIN = GND f = 1.0 MHz Operating Supply Current VI = GND, No load (low power mode, active) f = 1.0 MHz June 1, 1996 (Version 1.0) Min 2.4 Max Units V V 2.4 0.5 V 0.4 V 10.0 A 10.0 A 10.0 pF 30 mA Typ 3-19 XC9536 In-System Programmable CPLD AC Characteristics Symbol Parameter tPD tSU tH tCO fCNT fSYSTEM 1 tPSU tPH tPCO tOE tOD tPOE tPOD tPTA tFBK tWLH fTOG tSLEW tLP I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB Internal Operating Frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output valid Product term OE to output disable Product term allocator delay Internal combinatorial feedback delay GCK pulse width (High or Low) Export Control Max. flip-flop toggle rate Slew rate time delay Low power time delay adder Note: XC9536-5 XC9536-7 XC9536-10 XC9536-15 Min Min Min Min Max 5.0 4.5 0 Max 7.5 5.5 0 4.5 125 100 0.5 4.0 6.5 0 5.5 125 83.0 0.5 5.0 7.5 6.0 6.0 10.5 10.5 1.5 NA 4.0 4.0 125 3.5 8.0 Max 10 Max 15 8.0 0 6.5 111.0 67.0 1.0 5.5 8.0 95.0 55.0 2.0 6.0 10.5 7.0 7.0 13.0 13.0 1.5 8.5 12.0 10.0 10.0 15.5 15.5 2.0 12.0 4.5 125 4.0 8.0 Preliminary 111 4.5 8.5 14.0 15.0 15.0 18.0 18.0 2.0 17.0 5.0 100 5.5 8.5 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns MHz ns ns 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X5906 Figure 3: AC Load Circuit 3-20 June 1, 1996 (Version 1.0) XC9536 I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Macrocell PC44 VQ44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 5 4 6 8 7 9 11 12 13 14 18 19 20 22 24 - 40 41 43 42 44 2 1 3 5 6 7 8 12 13 14 16 18 - BScan Notes Order 105 102 99 [1] 96 93 [1] 90 87 [1] 84 81 78 75 72 69 66 63 60 57 54 Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell PC44 VQ44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 44 42 43 40 39 38 37 36 35 34 33 29 28 27 26 25 - 39 38 36 37 34 33 32 31 30 29 28 27 23 22 21 20 19 - BScan Notes Order 51 48 45 [1] 42 39 [1] 36 [1] 33 30 27 24 21 18 15 12 9 6 3 0 [1] Global control pin XC9536 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects June 1, 1996 (Version 1.0) PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 23,10,31 -- VQ44 43 44 1 36 34 33 11 9 24 10 15,35 26 17,4,25 -- 3-21 XC9536 In-System Programmable CPLD Ordering Information XC9536 - 5 VQ 44 C Device Type Temperature Range Number of Pins Speed Package Type Speed Options 15 ns pin-to-pin delay -15 10 ns pin-to-pin delay -10 7.5 ns pin-to-pin delay -7 -5 5 ns pin-to-pin delay Temperature Options C Commercial I Industrial 0C to 70C -40C to 85C Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) VQ44 44-Pin Very Thin Quad Flat Pack (VQFP) X5952 Component Availability 100 Pins 44 84 Type Plastic Plastic PLCC VQFP Plastic PLCC Plastic PQFP PC84 PQ100 Code -15 -10 XC9536 -7 -5 PC44 VQ44 C(I) C(I) C C C(I) C(I) C C 160 208 Plastic TQFP Plastic PQFP Power QFP TQ100 PQ160 HQ208 X5907 3-22 June 1, 1996 (Version 1.0) XC9572 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 7.5 ns pin-to-pin logic delays on all pins * fCNT to 125 MHz * 72 macrocells with 1,600 usable gates * Up to 72 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-7, -10 speed grades) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 1 for the architecture overview. June 1, 1996 (Version 1.0) Power Management Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 3-23 XC9572 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 2 18 Function Block 4 Macrocells 1 to 18 X5921 Figure 1: XC9572 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-24 June 1, 1996 (Version 1.0) XC9572 I/O Pins Function Macrocell Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC84 PQ100 TQ100 4 1 6 7 2 3 11 5 9 13 10 18 20 12 14 23 15 24 63 69 67 68 70 71 76 72 74 75 77 79 80 81 83 82 84 - 18 15 20 22 16 17 27 19 24 30 25 35 38 29 31 41 32 42 89 96 93 95 97 98 5 99 1 3 6 8 10 11 13 12 14 94 16 13 18 20 14 15 25 17 22 28 23 33 36 27 29 39 30 40 87 94 91 93 95 96 3 97 99 1 4 6 8 9 11 10 12 92 BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 [1] [1] [1] [1] [1] [1] Function Macrocell Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC84 PQ100 TQ100 25 17 31 32 19 34 35 21 26 40 33 41 43 36 37 45 39 - 46 44 51 52 47 54 55 48 50 57 53 58 61 56 65 62 66 - 43 34 51 52 37 55 56 39 44 62 54 63 65 57 58 67 60 61 68 66 73 74 69 78 79 70 72 83 76 84 87 80 91 88 92 81 41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 65 58 59 66 64 71 72 67 76 77 68 70 81 74 82 85 78 89 86 90 79 BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 Notes: [1] Global control pin June 1, 1996 (Version 1.0) 3-25 XC9572 In-System Programmable CPLD XC9572 Global, JTAG and Power Pins 3-26 Pin Type PC84 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42,49,60 -- PQ100 TQ100 24 22 25 23 29 27 5 3 6 4 1 99 50 48 47 45 85 83 49 47 7,59,100 5,57,98 28,40,53,90 26,38,51,88 2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84 4,9,21,26,36,45,48,75,82 2,7,19,24,34,43,46,73,80 June 1, 1996 (Version 1.0) XC95108 In-System Programmable CPLD June 1, 1996 (Version 1.0) Preliminary Product Specification Features Power Management * 7.5 ns pin-to-pin logic delays on all pins * fCNT to 125 MHz * 108 macrocells with 2400 usable gates * Up to 108 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-7, -10 speed grades) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP and 160-pin PQFP packages Power dissipation can be reduced in the XC95108 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95108 device. 300 (250) ance rform igh Pe H Typical ICC (mA) Description Operating current for each design can be approximated for specific operating conditions using the following equation: 200 (180) (170) er w Pow Lo 100 0 50 Clock Frequency (MHz) 100 X5898 Figure 1: Typical ICC vs. Frequency for XC95108 June 1, 1996 (Version 1.0) 3-27 XC95108 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 36 18 Function Block 4 Macrocells 1 to 18 Function Block 5 Macrocells 1 to 18 Function Block 6 Macrocells 1 to 18 X5897 Figure 2: XC95108 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-28 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions 1 Symbol VCCINT Parameter Supply voltage for internal logic and input buffer VCCIO Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Input signal transition time VIL VIH VO TIN Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCINT + 0.5 50 Units V V V V V V ns Note: 1. Numbers in parenthesis are for industrial-temperature range versions. DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL Input leakage current IIH I/O high-Z leakage current CIN I/O capacitance ICC Operating Supply Current (low power mode, active) June 1, 1996 (Version 1.0) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min Max 2.4 Units V V 2.4 0.5 V 0.4 V 10.0 A 10.0 A 10.0 pF 100 mA Typ 3-29 XC95108 In-System Programmable CPLD AC Characteristics Symbol Parameter XC95108-7 XC95108-10 XC95108-15 XC95108-20 Units Min tPD tSU tH tCO fCNT fSYSTEM 1 tPSU tPH tPCO tOE tOD tPOE tPOD tPTA tFBK tWLH fTOG tSLEW tLP I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB Internal Operating Frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output valid Product term OE to output disable Product term allocator delay Internal combinatorial feedback delay GCK pulse width (High or Low) Export Control Max. flip-flop toggle rate Slew rate time delay Low power time delay adder Max Min 7.5 5.5 0 Max Min 10 5.5 8.0 0 10.5 7.0 7.0 13.0 13.0 1.5 8.5 4.0 4.5 125 4.0 8.0 Max 20 10.0 0 6.5 111 67.0 1.0 5.5 Min 15 6.5 0 125 83.0 0.5 5.0 Max 8.0 95.0 55.0 2.0 6.0 10.0 83.0 50.0 4.0 6.0 12.0 10.0 10.0 15.5 15.5 2.0 12.0 14.0 15.0 15.0 18.0 18.0 2.0 17.0 5.0 111 4.5 8.5 Preliminary 100 5.0 8.5 16.0 20.0 20.0 22.0 22.0 2.0 20.0 6.0 83 5.5 8.5 ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns MHz ns ns Note: 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X5906 Figure 3: AC Load Circuit 3-30 June 1, 1996 (Version 1.0) XC95108 I/O Pins Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 1 2 - 3 4 - 5 6 - 7 9 - 10 11 12 13 - - 71 72 - 74 75 - 76 77 - 79 80 - 81 82 83 84 - - 15 16 21 17 18 - 19 20 26 22 24 - 25 27 29 30 - - 98 99 4 1 3 - 5 6 9 8 10 - 11 12 13 14 - - 13 14 19 15 16 - 17 18 24 20 22 - 23 25 27 28 - - 96 97 2 99 1 - 3 4 7 6 8 - 9 10 11 12 - 25 21 22 29 23 24 27 26 28 36 30 33 34 35 37 42 44 43 158 154 156 4 159 2 9 6 8 12 11 13 14 15 17 18 19 16 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 [1] [1] [1] [1] [1] [1] 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 14 15 - 17 18 - 19 20 - 21 23 - 24 25 26 31 - - 57 58 - 61 62 - 63 65 - 66 67 - 68 69 - 70 - - 31 32 36 34 35 - 37 38 45 39 41 - 42 43 44 51 - - 83 84 82 87 88 - 89 91 - 92 93 - 95 96 94 97 - - 29 30 34 32 33 - 35 36 43 37 39 - 40 41 42 49 - - 81 82 80 85 86 - 87 89 - 90 91 - 93 94 92 95 - 45 47 49 57 54 56 50 58 59 69 60 62 52 63 64 68 77 74 123 134 135 133 138 139 128 140 142 147 143 144 153 146 148 145 152 155 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Notes: [1] Global control pin June 1, 1996 (Version 1.0) 3-31 XC95108 In-System Programmable CPLD XC95108 I/O Pins (continued) Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 32 33 - 34 35 - 36 37 - 39 40 - 41 43 - 44 - - 52 54 48 55 56 - 57 58 - 60 62 - 63 65 61 66 - - 50 52 46 53 54 - 55 56 - 58 60 - 61 63 59 64 - 76 79 82 72 86 88 78 90 92 84 95 97 87 98 101 96 102 89 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 45 46 - 47 48 - 50 51 - 52 53 - 54 55 - 56 - - 67 68 75 69 70 - 72 73 - 74 76 - 78 79 81 80 - - 65 66 73 67 68 - 70 71 - 72 74 - 76 77 79 78 - 91 103 104 116 106 108 105 111 113 107 115 117 112 122 124 129 126 114 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 XC95108 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND GND GND 3-32 PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42,49,60 - - PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71,77,86 - - TQ100 22 23 27 3 4 99 48 45 83 47 5,57,98 26,38,51,88 100,21,31,44,62,69,75,84 - - PQ160 33 35 42 6 8 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 20,31,40,51,70,80,99 100,110,120,127,137 160 June 1, 1996 (Version 1.0) Ordering Information XC95108 - 7 PQ 160 C Device Type Temperature Range Number of Pins Speed Package Type Speed Options -20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7 ns pin-to-pin delay Temperature Options C Commercial Industrial I 0C to 70C -40C to 85C Packaging Options PC84 84-Pin Plastic Leaded Chip Carrier (PLCC) PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Thin Quad Flat Pack (TQFP) PQ160 160-Pin Plastic Quad Flat Pack (PQFP) X5953 Component Availability Pins 44 84 160 208 Type Plastic Plastic PLCC VQFP Plastic PLCC Plastic PQFP Plastic TQFP Plastic PQFP Power QFP PC84 PQ100 TQ100 PQ160 HQ208 C(I) C(I) C(I) C C(I) C(I) C(I) C C(I) C(I) C(I) C C(I) C(I) C(I) C Code -20 -15 XC95108 -10 -7 PC44 VQ44 100 X5941 June 1, 1996 (Version 1.0) 3-33 XC95108 In-System Programmable CPLD 3-34 June 1, 1996 (Version 1.0) XC95144 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 7.5 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 144 macrocells with 3,200 usable gates * Up to 133 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-7, -10 speed grades) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 100-pin PQFP, and 160-pin PQFP packages The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 1 for the architecture overview. June 1, 1996 (Version 1.0) Power Management Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 3-35 XC95144 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 Function Block 4 Macrocells 1 to 18 Function Block 8 Macrocells 1 to 18 X5922 Figure 1: XC95144 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-36 June 1, 1996 (Version 1.0) XC95144 I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell PQ100 PQ160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 15 16 - 17 18 - 19 20 - 21 22 - 24 25 - 26 - - 4 - - 5 6 - 8 9 - 10 11 - 12 13 - 14 - 38 21 22 25 23 24 32 26 28 74 29 30 39 33 35 78 36 - 3 4 147 158 6 8 7 11 12 155 13 15 5 17 18 105 19 - BScan Notes Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 [1] 387 [1] 384 381 378 375 372 [1] 369 366 363 [1] 360 [1] 357 354 351 348 345 342 339 336 333 330 327 324 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ100 PQ160 - 27 - - 29 30 - 31 32 - 34 35 - 36 37 - 38 - - 92 - - 93 94 - 95 96 - 97 98 - 99 1 - 3 - 53 37 84 45 42 44 48 47 49 89 54 56 55 57 58 34 59 - 149 143 107 123 144 145 151 146 148 114 152 154 150 156 159 14 2 - BScan Notes Order 321 318 315 312 309 [1] 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 [1] 222 219 [1] 216 Notes: [1] Global control pin Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. June 1, 1996 (Version 1.0) 3-37 XC95144 In-System Programmable CPLD XC95144 I/O Pins (continued) Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 3-38 Macrocell PQ100 PQ160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 39 - - 41 42 - 43 44 - 45 48 - 51 52 - 54 - - 79 - - 80 81 - 82 83 - 84 87 - 88 89 - 91 - 65 60 27 76 62 63 67 64 68 93 69 72 66 77 79 52 82 - - 124 9 91 126 129 131 133 134 130 135 138 132 139 140 153 142 - BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell PQ100 PQ160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 55 - - 56 57 - 58 60 - 61 62 - 63 65 - 66 - - 67 - - 68 69 - 70 72 - 73 74 - 75 76 - 78 - - 86 50 43 88 90 83 92 95 109 96 97 85 98 101 87 102 - - 103 128 16 104 106 118 108 111 125 113 115 119 116 117 112 122 - BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 June 1, 1996 (Version 1.0) XC95144 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND PQ100 24 25 29 5 6 3 4 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71, 77,86 No Connects - June 1, 1996 (Version 1.0) PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 20,31,40,51,70,80, 99,100,110,120,127, 137,160 - 3-39 XC95144 In-System Programmable CPLD 3-40 June 1, 1996 (Version 1.0) XC95180 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 10 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 180 macrocells with 4,000 usable gates * Up to 168 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-10 speed grade) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 160-pin PQFP, and 208-pin HQFP packages The XC95180 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of ten 36V18 Function Blocks, providing 4,000 usable gates with propagation delays of 10 ns. See Figure 1 for the architecture overview. June 1, 1996 (Version 1.0) Power Management Power dissipation can be reduced in the XC95180 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 3-41 XC95180 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 Function Block 4 Macrocells 1 to 18 Function Block 10 Macrocells 1 to 18 X5923 Figure 1: XC95180 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-42 June 1, 1996 (Version 1.0) XC95180 I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ160 HQ208 - 22 23 24 25 26 - 27 28 29 30 32 - 33 34 35 36 - - 6 7 8 9 11 - 12 13 14 15 16 - 17 18 19 21 - 39 30 31 32 33 34 40 35 36 37 38 43 41 44 45 46 47 - 14 7 8 9 10 15 28 16 17 18 19 20 29 21 22 23 25 - BScan Notes Order 537 534 531 528 525 522 519 516 513 510 507 504 501 498 [1] 495 492 [1] 489 486 483 480 [1] 477 474 [1] 471 468 465 462 459 456 453 450 447 444 441 438 435 432 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ160 HQ208 - 37 38 39 42 43 - 44 45 47 48 49 - 50 52 53 56 - - 150 151 152 153 154 - 155 156 - 158 159 - 2 3 4 5 - 48 49 50 51 55 56 54 57 58 60 61 63 62 64 70 71 74 - 196 194 197 198 199 200 203 201 202 208 205 206 12 3 4 5 6 - BScan Notes Order 429 426 423 420 417 [1] 414 411 408 405 402 399 396 393 390 387 384 381 387 375 372 369 366 363 360 357 354 351 348 345 342 [1] 339 336 [1] 333 330 [1] 327 324 Notes: [1] Global control pin Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. June 1, 1996 (Version 1.0) 3-43 XC95180 In-System Programmable CPLD XC95180 I/O Pins (continued) Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 3-44 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ160 HQ208 - 54 55 57 58 59 - 60 62 - 63 64 - 65 66 67 68 - - 134 135 138 139 140 - 142 143 - 144 145 - 146 147 148 149 - 66 72 73 75 76 77 67 78 82 69 83 84 80 85 86 87 88 - 169 174 175 178 179 180 183 182 185 189 186 187 195 188 191 192 193 - BScan Notes Order 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ160 HQ208 - 69 72 74 76 77 - 78 79 - 82 83 - 84 85 86 87 - - 118 119 122 123 124 - 125 126 - 128 129 - 130 131 132 133 - 90 89 95 97 99 100 91 102 103 101 110 111 106 112 113 114 115 - 144 154 155 158 159 160 151 161 162 165 164 166 168 167 170 171 173 - BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 June 1, 1996 (Version 1.0) XC95180 I/O Pins (continued) Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Macrocell PQ160 HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 88 89 90 91 92 - 93 95 - 96 97 - 98 101 102 103 - - 116 117 118 121 122 107 123 125 109 126 127 119 128 131 133 134 - BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 Function Block 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PQ160 HQ208 - 104 105 106 107 108 - 109 111 - 112 113 - 114 115 116 117 - - 135 136 137 138 139 120 140 145 142 146 147 143 148 149 150 152 - BScan Notes Order 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 XC95180 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 GND 20,31,40,51,70,80, 99,100,110,120,127, 137,160 No Connects - June 1, 1996 (Version 1.0) HQ208 44 46 55 7 9 3 5 206 98 94 176 96 11,59,124,153,204 1,26,53,65,79,92,105, 132,157,172,181,184 2,13,24,27,42,52,68,81, 93,104,108,129,130, 141,156,163,177, 190,207 - 3-45 XC95180 In-System Programmable CPLD 3-46 June 1, 1996 (Version 1.0) XC95216 In-System Programmable CPLD June 1, 1996 (Version 1.0) Preliminary Product Specification Features Power Management * 10 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 216 macrocells with 4800 usable gates * Up to 168 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant (-10 speed grade) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in 160-pin PQFP and 208-pin HQFP packages Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twelve 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview. ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95216 device. 600 e rmanc erfo High P Typical ICC (mA) Description Operating current for each design can be approximated for specific operating conditions using the following equation: 400 (360) (500) (340) wer ow Po L 200 0 50 Clock Frequency (MHz) 100 X5918 Figure 1: Typical ICC vs. Frequency For XC95216 June 1, 1996 (Version 1.0) 3-47 XC95216 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 Function Block 4 Macrocells 1 to 18 Function Block 12 Macrocells 1 to 18 X5917 Figure 2: XC95216 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-48 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operating Conditions 1 Symbol VCCINT Parameter Supply voltage for internal logic and input buffer VCCIO Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Input signal transition time VIL VIH VO TIN Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCINT + 0.5 50 Note: 1. Numbers in parenthesis are for industrial-temperature range versions. DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL Input leakage current IIH I/O high-Z leakage current CIN I/O capacitance ICC Operating Supply Current (low power mode, active) June 1, 1996 (Version 1.0) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 V 0.4 V 10.0 A 10.0 A 10.0 pF 200 mA 3-49 XC95216 In-System Programmable CPLD AC Characteristics Symbol tPD tSU tH tCO fCNT fSYSTEM 1 tPSU tPH tPCO tOE tOD tPOE tPOD tPTA tFBK tWLH fTOG tSLEW Note: Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB Internal Operating Frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output valid Product term OE to output disable Product term allocator delay Internal combinatorial feedback delay GCK pulse width (High or Low) Export Control Max. flip-flop toggle rate Slew rate time delay XC95216-10 XC95216-15 XC95216-20 Min Min Min Max 10 6.5 0 Max 15 20 8.0 0 6.5 111 67.0 1.0 5.5 10.0 0 8.0 10.0 95.0 55.0 2.0 6.0 12.0 10.0 10.0 15.5 15.5 2.0 12.0 4.5 83.0 50.0 4.0 6.0 14.0 15.0 15.0 18.0 18.0 2.0 17.0 16.0 20.0 20.0 22.0 22.0 2.0 20.0 5.0 111 4.5 Units Max 6.0 100 5.0 Preliminary 83 5.5 ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns MHz ns 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X5906 Figure 3: AC Load Circuit 3-50 June 1, 1996 (Version 1.0) XC95216 I/O Pins Function Block Macrocell PQ160 HQ208 BScan Order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 18 19 - 21 22 - 23 24 - 25 26 - 27 28 29 30 - - 6 7 - 8 9 - 11 12 - 13 14 - 15 16 - 17 - - 22 23 28 25 30 - 31 32 12 33 34 - 35 36 37 38 - - 7 8 29 9 10 - 15 16 66 17 18 - 19 20 14 21 - 645 642 639 636 633 630 627 624 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 546 543 540 June 1, 1996 (Version 1.0) Notes [1] [1] Function Block Macrocell PQ160 HQ208 BScan Order 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 32 33 - 34 35 - 36 37 - 38 39 - 42 43 - 44 - - 152 153 - 154 155 - 156 158 - 159 2 - 3 4 - 5 - - 43 44 39 45 46 - 47 49 67 50 51 - 55 56 80 57 - - 198 199 196 200 201 - 202 205 69 206 3 - 4 5 203 6 - 537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432 Notes [1] [1] [1] [1] [1] [1] 3-51 XC95216 In-System Programmable CPLD XC95216 I/O Pins (continued) Function Block Macrocell PQ160 HQ208 BScan Order 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 45 47 - 48 49 - 50 52 - 53 54 - 55 56 - 57 - - 140 142 - 143 144 - 145 146 - 147 148 - 149 150 - 151 - - 58 60 41 61 63 - 64 70 109 71 72 - 73 74 40 75 - - 180 182 208 185 186 - 187 188 183 191 192 - 193 194 169 197 - 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 3-52 Notes Function Block Macrocell PQ160 HQ208 BScan Order 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 58 59 - 60 62 - 63 64 - 65 66 - 67 68 - 69 - - 126 128 - 129 130 - 131 132 - 133 134 - 135 138 - 139 - - 76 77 54 78 82 - 83 84 91 85 86 - 87 88 48 89 - - 162 164 143 166 167 - 170 171 195 173 174 - 175 178 189 179 - 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 Notes June 1, 1996 (Version 1.0) XC95216 I/O Pins (continued) Function Block Macrocell PQ160 HQ208 BScan Order 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 72 74 - 76 77 - 78 79 - 82 83 - 84 85 - 86 - - 113 114 - 115 116 - 117 118 - 119 122 - 123 124 - 125 - - 95 97 101 99 100 - 102 103 90 110 111 - 112 113 62 114 - - 147 148 144 149 150 - 152 154 168 155 158 - 159 160 165 161 - 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 June 1, 1996 (Version 1.0) Notes Function Block Macrocell PQ160 HQ208 BScan Order 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 87 88 - 89 90 - 91 92 - 93 95 - 96 97 - 98 - - 101 102 - 103 104 - 105 106 - 107 108 - 109 111 - 112 - - 115 116 119 117 118 - 121 122 107 123 125 - 126 127 120 128 - - 131 133 106 134 135 - 136 137 151 138 139 - 140 145 142 146 - 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 Notes 3-53 XC95216 In-System Programmable CPLD XC95216 Global, JTAG and Power Pins 3-54 Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 GND 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160 No Connects - HQ208 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204 1, 26, 53, 65, 79, 92, 105, 132, 157, 172, 181, 184 2, 13, 24, 27, 42, 52, 68, 81, 93, 104, 108, 129, 130, 141, 156, 163, 177, 190, 207 - June 1, 1996 (Version 1.0) Ordering Information XC95216 - 10 PQ 208 C Device Type Temperature Range Number of Pins Speed Package Type Speed Options -20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay Temperature Options C Commercial I Industrial 0C to 70C -40C to 85C Packaging Options PQ160 160-Pin Plastic Quad Flat Pack (PQFP) HQ208 208-Pin Power Quad Flat Pack (HQFP) X5088 Component Availability Pins 44 84 160 208 Type Plastic Plastic PLCC VQFP Plastic PLCC Plastic PQFP Plastic TQFP Plastic PQFP Power QFP PC84 PQ100 TQ100 PQ160 HQ208 C(I) C C C(I) C C Code -20 XC95216 -15 -10 PC44 VQ44 100 X5089 June 1, 1996 (Version 1.0) 3-55 XC95216 In-System Programmable CPLD 3-56 June 1, 1996 (Version 1.0) XC95288 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 10 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 288 macrocells with 6,400 usable gates * Up to 292 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * PCI compliant ( -10 speed grade) * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in a 208-pin and 304-pin HQFP packages The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen 36V18 Function Blocks, providing 6,400 usable gates with propagation delays of 10 ns. See Figure 1 for the architecture overview. June 1, 1996 (Version 1.0) Power Management Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 3-57 XC95288 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 Function Block 4 Macrocells 1 to 18 Function Block 16 Macrocells 1 to 18 X5924 Figure 1: XC95288 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks 3-58 June 1, 1996 (Version 1.0) XC95288 I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 28 29 - 30 31 - 32 - 33 - 34 - 35 36 - 37 - - 15 16 - 17 18 - 19 - 20 - 21 - 22 23 - 25 - BScan Notes Order 861 858 855 852 849 846 843 840 837 834 831 828 825 822 819 816 813 810 807 804 801 798 795 792 789 786 783 780 777 774 771 768 765 762 759 756 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 38 39 - 40 41 - 43 - 44 - 45 - 46 47 - 48 - - 3 4 - 5 6 - 7 - 8 - 9 - 10 12 - 14 - BScan Notes Order 753 750 747 744 741 738 735 732 729 726 [1] 723 720 717 714 [1] 711 708 705 702 699 696 [1] 693 690 687 [1] 684 681 678 [1] 675 672 669 666 [1] 663 660 657 654 651 648 Notes: [1] Global control pin Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. Consult factory for HQ304 pinouts. June 1, 1996 (Version 1.0) 3-59 XC95288 In-System Programmable CPLD XC95288 I/O Pins (continued) Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Note: 3-60 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 49 50 - 51 54 - 55 - 56 - 57 - 58 60 - 61 - - 197 198 - 199 200 - 201 - 202 - 203 - 205 206 - 208 - BScan Notes Order 645 642 639 636 633 630 627 624 [1] 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 [1] 546 543 540 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 62 63 - 64 66 - 67 - 69 - 70 - 71 72 - 73 - - 186 187 - 188 189 - 191 - 192 - 193 - 194 195 - 196 - BScan Notes Order 537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432 [1] Global control pin June 1, 1996 (Version 1.0) XC95288 I/O Pins (continued) Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 June 1, 1996 (Version 1.0) - 74 75 - 76 77 - 78 - 80 82 83 - 84 85 - 86 - - 170 171 - 173 174 - 175 - 178 179 180 - 182 183 - 185 - BScan Notes Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 Function Block 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 87 88 - 89 90 - 91 - 95 97 99 - 100 101 - 102 - - 158 159 - 160 161 - 162 - 164 165 166 - 167 168 - 169 - BScan Notes Order 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 3-61 XC95288 In-System Programmable CPLD XC95288 I/O Pins (continued) Function Block 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 3-62 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 103 106 - 107 109 - 110 - 111 112 113 - 114 115 - 116 - - 144 145 - 146 147 - 148 - 149 150 151 - 152 154 - 155 - BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Macrocell HQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 117 118 - 119 120 - 121 - 122 123 125 - 126 127 - 128 - - 131 133 - 134 135 - 136 - 137 138 139 - 140 142 - 143 - BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 June 1, 1996 (Version 1.0) XC95288 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects June 1, 1996 (Version 1.0) HQ208 44 46 55 7 9 3 5 206 98 94 176 96 11,59,124,153,204 1,26,53,65,79,92,105, 132,157,172,181,184 2,13,24,27,42,52,68,81, 93,104,108,129,130, 141,156,163,177, 190,207 - 3-63 XC95288 In-System Programmable CPLD 3-64 June 1, 1996 (Version 1.0) XC95432 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 10 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 432 macrocells with 9,600 usable gates * Up to 232 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in a 304-pin HQFP package The XC95432 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twentyfour 36V18 Function Blocks, providing 9,600 usable gates with propagation delays of 10 ns. June 1, 1996 (Version 1.0) 3-65 XC95432 In-System Programmable CPLD 3-66 June 1, 1996 (Version 1.0) XC95576 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description * 12 ns pin-to-pin logic delays on all pins * fCNT to 100 MHz * 576 macrocells with 12,800 usable gates * Up to 232 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs with 3.3 V or 5 V I/O capability * Advanced 0.6 m CMOS 5V FastFLASH technology * Available in a 304-pin HQFP package The XC95576 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of thirtytwo 36V18 Function Blocks, providing 12,800 usable gates with propagation delays of 12 ns. June 1, 1996 (Version 1.0) 3-67 XC95576 In-System Programmable CPLD 3-68 June 1, 1996 (Version 1.0) XC7300 Series Table of Contents XC7300 CMOS CPLD Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V or 5 V Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Characteristics/Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erasure Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Volume Production Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstep Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 3-77 3-77 3-77 3-77 3-77 3-78 3-78 3-78 3-78 XC7318 18-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7318 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81 3-82 3-82 3-83 3-83 3-84 3-85 3-85 3-85 3-86 3-87 3-88 XC7336/XC7336Q 36-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7336 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 3-90 3-90 3-91 3-91 3-92 3-93 3-94 3-94 3-95 3-96 3-97 XC7354 54-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 3-99 3-101 3-101 3-102 3-102 3-102 3-69 XC7300 Series Table of Contents Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7354 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103 3-103 3-104 3-104 3-105 3-106 XC7372 72-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107 3-107 3-109 3-109 3-110 3-110 3-110 3-111 3-111 3-112 3-112 3-113 3-114 XC73108 108-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73108 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 3-115 3-117 3-117 3-118 3-118 3-118 3-119 3-119 3-120 3-120 3-121 3-123 XC73144 144-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density Function Block (FB) Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC73144 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7300 Characterization Data 3-70 3-125 3-125 3-127 3-127 3-128 3-128 3-129 3-129 3-130 3-130 3-131 3-132 3-134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135 XC7300 CMOS CPLD Family June 1, 1996 (Version 1.0) Product Specification Features Description * The XC7300 family employs a unique Dual-Block architecture that provides high speed operations via Fast Function Blocks and/or high density capability via High Density Function Blocks. * * * * * * * * * * * * * High-performance Complex Programmable Logic Devices (CPLDs) - 5 / 7.5 ns pin-to-pin speeds on all fast inputs - Up to 167 MHz maximum clock frequency 100% PCI compliant High-drive 24 mA output I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 43 to 61 MHz 18-bit accumulators Multiple independent clocks Each input programmable as direct, latched, or registered Power management options Multiple security bits for design protection Supported by industry standard design and verification tools Advanced Dual-Block architecture - Fast Function Blocks - High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144) 0.8 CMOS EPROM technology Fast Function Blocks (FFBs) provide fast, pin-to-pin speed and logic throughput for critical decoding and ultra-fast state machine applications. High-Density Function Blocks (FBs) provide maximum logic density and system-level features to implement complex functions with predictable timing for adders and accumulators, wide functions and state machines requiring large numbers of product terms, and other forms of complex logic. See Figure 1. In addition, the XC7300 architecture employs the Universal Interconnect Matrix (UIM) which guarantees 100% interconnect of all internal functions. This interconnect scheme provides constant, short interconnect delays for all routing paths through the UIM. Constant interconnect delays simplify device timing and guarantee design performance, regardless of logic placement within the chip. The UIM provides an intrinsic wire-AND capability called SMARTswitch. Transferring functions into the UIM conserves macrocell logic. This increases the total logic capacity of the device. The wire-AND capability also significantly increases the signal fan-in of each function block. All Xilinxsupported CPLD design tools automatically implement SMARTswitch. The XC7300 Family Typical 22V10 Equivalent Number of Macrocells Number of Function Blocks Number of Flip-Flops Number of Fast Inputs Number of Signal Pins June 1, 1996 (Version 1.0) XC7318 1.5 - 2 18 2 18 12 38 XC7336 3-4 36 4 36 12 38 XC7354 6 54 6 108 12 58 XC7372 8 72 8 126 12 84 XC73108 12 108 12 198 12 120 XC73144 16 144 16 276 12 156 3-71 XC7300 CMOS CPLD Family Input Output FFB FB FFB UIM Output FB I/O Block I/O Block FB FB X3204 Figure 1: XC7300 Device Block Diagram All XC7300 Dual-Block CPLDs include programmable power management features to specify high-performance or low-power operation on an individual macrocell-by-macrocell basis. Unused macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while noncritical paths dissipate less power. Fast Function Blocks The FFB has 24 inputs that can be individually selected from the UIM, 12 fast input pins, or the nine macrocell feedbacks from the FFB. The programmable AND array in each FFB generates 45 product terms to drive the nine macrocells in each FFB. Each macrocell can be configured for registered or combinatorial logic. See Figure 2. Five product terms from the programmable AND array are allocated to each macrocell. Four of these product terms are ORed together and may be optionally inverted before driving the input of a programmable D-type flip-flop. The fifth product term drives the asynchronous active-High programmable Reset or Set Input to the macrocell flip-flop. The flip-flop can be configured as a D-type or Toggle flip-flop, or transparent for combinatorial outputs. Two FFB macrocell differences exist between the XC7318/ XC7336/XC73144 and the XC7354/XC7372/XC73108. In the XC7318, XC7336 and XC73144, five product terms from the programmable AND array are allocated to each macrocell. Four of these product terms are OR'd together and may be optionally inverted before driving the input of a 3-72 programmable D-type flip-flop. The fifth product term drives the asynchronous active High programmable Set or Reset input to the macrocell flip-flop. The flip-flop can be configured as a D-type or Toggle flip-flop, or transparent for combinatorial outputs. See Figure 2. In the XC7354, XC7372 and XC73108, five product terms from the programmable AND array are allocated to each macrocell. Four of these product terms are OR'd together, inverted and drive the input of a programmable D-type flipflop. The fifth product term drives the asynchronous active High programmable Set input to the macrocell flip-flop. The flip-flop can be configured as a D-type flip-flop or transparent for combinatorial outputs. See Figure 3. The programmable clock source is one of two global FastClock signals (FCLK0 or FCLK1) that are distributed with short delay and minimal skew over the entire chip. The FFB macrocells drive chip outputs directly through 3state output buffers. Each output buffer can be individually controlled by one of two dedicated Fast Output Enable inputs or permanently enabled or disabled. The macrocell output can also be routed back as an input to the FFB and the UIM. Each FFB output is capable of sinking 24 mA when VCCIO = 5 volts. These include all outputs on the XC7318 and XC7336 devices and all Fast Outputs (FOs) on the XC7354, XC7372, XC73108, and XC73144 devices. Unlike other I/Os, the FFB inputs do not have an input register. June 1, 1996 (Version 1.0) 2 Global Fast OE 2 12 from Fast Input Pins 12 24 Inputs from UIM AND Array 3 Sum-of-Products from Previous Macrocell 9 from FFB Macrocell Feedback Fast Clocks 0 1 5 1 of 9 Macrocells OE Control 9 5 Private P-Terms per Macrocell 0 I/O Pin D/T Q 1 Output Polarity S/R P-Term Assignment Control Input-Pad Register/Latch (optional) (XC73144 only) Register Transparent Control Feedback to UIM Sum-of-Products to Succeeding Macrocell Pin Feedback to UIM X5725 Figure 2: Fast Function Block and Macrocell Schematic for the XC7318, XC7336, and XC73144 2 Global Fast OE 2 12 from Fast Input Pins 12 24 Inputs from UIM AND Array 3 Sum-of-Products from Previous Macrocell 9 from FFB Macrocell Feedback Fast Clocks 0 1 5 1 of 9 Macrocells OE Control 9 5 Private P-Terms per Macrocell IOL = 24 mA 0 D 1 Pin Q S P-Term Assignment Control Register Transparent Control Input-Pad Register/Latch (optional) (XC7354 only) Feedback to UIM Sum-of-Products to Succeeding Macrocell Pin Feedback to UIM (XC7354 Only) X5761 Figure 3: Fast Function Block and Macrocell Schematic for the XC7354, XC7372, and XC73108 June 1, 1996 (Version 1.0) 3-73 XC7300 CMOS CPLD Family Product Term Assignment Each macrocell sum-of-product OR gates can be expanded using the FFB product term assignment scheme. Product term assignment transfers product terms in increments of four product terms from one macrocell to the neighboring macrocell (Figure 4). Complex logic functions requiring up to 36 product terms can be implemented using all nine macrocells within the FFB. When product terms are assigned to adjacent macrocells, the product term normally dedicated to the Set or Reset function becomes the input to the macrocell register. From Previous Macrocell Global Clocks Single-ProductTerm Assignment D/T configured for either registered or combinatorial logic. A detailed block diagram of the FB is shown in Figure 5. Each FB receives 21 signals and their complements from the UIM and an additional three inputs from the Fast Input (FI) pins. Shared and Private Product Terms Each macrocell contains five private product terms that can be used as the primary inputs for combinatorial functions implemented in the Arithmetic Logic Unit (ALU), or as individual Reset, Set, Output-Enable, and Clock logic functions for the flip-flop. Each FB also provides an additional 12 shared product terms, which are uncommitted product terms available for any of the nine macrocells within the FB. Four private product terms can be ORed together with up to four shared product terms to drive the D1 input to the ALU. The D2 input is driven by the OR of the fifth private product term and up to eight of the remaining shared product terms. The shared product terms add no logic delay, and each shared product term can be connected to one or all nine macrocells in the FB. Q 4 Output Polarity MCN Eight-ProductTerm Assignment S/R D/T Q 4 The functional versatility of each macrocell in the FB is enhanced through additional gating and control functions available in the ALU. A detailed block diagram of the XC7300 ALU is shown in Figure 6. The ALU has two programmable modes; logic and arithmetic. In logic mode, the ALU functions as a 2-input function generator using a 4-bit look-up table that can be programmed to generate any Boolean function of its D1 and D2 inputs as illustrated in Table 1. Output Polarity MCN+1 X5220 Figure 4: Fast Function Block Product Term Assignment High-Density Function Blocks The XC7354, XC7372, XC73108 and XC73144 devices contain multiple, High-Density FBs linked though the UIM. Each FB contains nine macrocells. Each macrocell can be 3-74 Arithmetic Logic Unit The function generator can OR its inputs, widening the OR function to a maximum of 17 inputs. It can AND them, which means that one sum-of-products can be used to mask the other. It can also XOR them, toggling the flip-flop or comparing the two sums of products. Either or both of the sumof-product inputs to the ALU can be inverted, and either or both can be ignored. June 1, 1996 (Version 1.0) AND Array 21 Inputs from UIM 3 from Fast Input Pins (FI) Arithmetic Carry-In from Previous Macrocell Feedback Enable Override Fast Clocks 0 1 5 12 Sharable P-Terms per Function Block CLOCK OE* SET RESET 5 Private P-Terms per Macrocell C in D1 4 F D2 C out I/O (see fig. 7) R S D Q Clock Select To 8 More Macrocells Shift-In from Previous MC Pin Input-Pad Register/Latch (optional) ALU Register Trasparent Control Feedback Polarity Local Feedback Shift-Out to Next MC Global Fast OE OE Control MUX 8 1 of 9 Macrocells Arithmetic Carry-Out to Next Macrocell * OE is forced high when P-term is not used Feedback to UIM Input to UIM X5485 Figure 5: High-Density Function Block and Macrocell Schematic Table 1: Function Generator Logic Operations Function D1:+: D2 D1:+: D2 D1 * D2 D1 * D2 D1 + D2 D1 + D2 D1 D2 D1 D2 D1 * D2 D1 * D2 D1 + D2 D1 + D2 In arithmetic mode, the ALU block can be programmed to generate the arithmetic sum or difference of the D1 and D2 inputs. Combined with the carry input from the next lower macrocell, the ALU operates as a 1-bit full adder generating a carry output to the next higher macrocell. The carry chain propagates between adjacent macrocells and also crosses the boundaries between FBs. This dedicated carry chain overcomes the inherent speed and density problems of the traditional CPLD architecture when trying to perform arithmetic functions. Carry Lookahead Carry Output Arithmetic Logic Unit (ALU) 0 1 D1 Sum-ofProducts D1 D2 Sum-ofProducts D2 Function Generator To Macrocell Flip-Flop Carry Input June 1, 1996 (Version 1.0) Each FB provides a carry lookahead generator capable of anticipating the carry across all nine macrocells. The carry lookahead generator reduces the ripple-carry delay of wide arithmetic functions such as add, subtract, and magnitude compare to that of the first nine bits, plus the carry lookahead delay of the higher-order FBs. Macrocell Flip-Flop Arithmetic Carry Control Figure 6: ALU Schematic Therefore, the ALU can implement one additional layer of logic without any speed penalty. X3206 The ALU block output drives the input of a programmable D-type flip-flop. The flip-flop is triggered by the rising edge of the clock input, but it can be configured as transparent, 3-75 XC7300 CMOS CPLD Family Each UIM input can be connected to any UIM output. The UIM delay is constant, regardless of the routing distance, fan-out, or fan-in. making the Q output identical to the D input, independent of the clock, or as a conventional flip-flop. The macrocell clock source is programmable and can be one of the private product terms or one of two global FastCLK signals (FCLK0 and FCLK1). Global FastCLK signals are distributed to every macrocell flip-flop with short delay and minimal skew. When multiple UIM inputs are connected to the same output, their wire-AND is formed by using internally available inversions. This AND logic can also be used to implement wide NAND, OR or NOR functions. This offers an additional level of logic without any speed penalty. The asynchronous Set and Reset product terms override the clocked operation. If both asynchronous inputs are active simultaneously, Reset overrides Set. A macrocell feedback signal that is disabled by the output enable product term represents a High input to the UIM. Programming several such macrocell outputs onto the same UIM output emulates a 3-state bus line. If one of the macrocell outputs is enabled, the UIM output assumes the enabled output's level. In addition to driving the chip output buffer, the macrocell output is routed back as an input to the UIM. One private product term can be configured to control the Output Enable of the output buffer and/or the feedback to the UIM. If it is configured to control UIM feedback, the Output Enable product term forces the UIM feedback line High when the macrocell output is disabled. Input/Output Blocks Macrocells drive chip outputs directly through 3-state output buffers, each individually controlled by the Output Enable product term mentioned above. The macrocell output can be inverted. An additional configuration option allows the output to be disabled permanently. Two dedicated FastOE inputs can also be configured to control any of the chip outputs instead of, or in conjunction with, the individual Output Enable product term. See Figure 7. Universal Interconnect Matrix The UIM receives inputs from each macrocell output, I/O pin, and dedicated input pin. Acting as fully connected crossbar switch, the UIM generates 21 output signals to each FB and 24 output signals to each FFB. Fast OE0 Fast OE1 MUX Macrocell From FB Macrocell Register I/O, FCLK/O, CKEN/O and FOE/O Pins Only Pin Driver From FB Macrocell Register I/O Pin Output Polarity Feedback to UIM MUX Q To UIM Input Polarity D EN CKEN0 CLK CKEN1 Q Q To Function Block AND-Array (on Fast Input Pins Only) D CLK D EN FastCLK0 FastCLK1 Input and I/O Pins Only FastCLK2 Global Select X5463 Figure 7: Input/Output Schematic (except XC7318/XC7336 which do not include I/O flip-flops) 3-76 June 1, 1996 (Version 1.0) Output buffers, except those connected to FFBs, can sink 12 mA when VCCIO = 5 V. FFB outputs can sink 24 mA when VCCIO = 5 V. is brought high after tWMR, but before tRESET, the outputs will become active after tRESET. It is essential that the MR pin remain static during power on reset (tRESET). Each signal input to the chip is connected to a programmable input structure that can be configured as direct, latched, or registered. The latch and flip-flop can use one of two FastCLK signals as latch enable or clock. The two FastCLK signals are FCLK0 and a global choice of either FCLK1 or FCLK2. Latches are transparent when FastCLK is High, and flip-flops clock on the rising edge of FastCLK. The flipflop includes an active-low clock enable, which when High, holds the present state of the flip-flop and inhibits response to the input signal. The clock enable source is one of two global Clock Enable signals (CE0 and CE1). An additional configuration option is polarity inversion for each input signal. During the initialization sequence, all input registers or latches are preloaded High and all FB and FFB macrocell registers are preloaded to a known state. For FFB macrocell registers where the Set/Reset product term is defined, the preload is accomplished by asserting the product term shortly before the end of the initialization sequence. When the Set/Reset product term is configured as Reset, the register preload value is Low. When the Set/Reset product term is configured as Set, the register preload value is High. For FFB macrocell registers where the Set/Reset product term is not used, the register preload value is High. 3.3 V or 5 V Interface Configuration XC7300 devices can be used in systems with two different supply voltages: 3.3 V and 5 V. Each XC7300 device has separate VCC connections to the internal logic and input buffers (VCCINT) and to the I/O drivers (VCCIO). VCCINT must always be connected to a nominal 5 V supply, while VCCIO may be connected to either 3.3 V or 5 V, depending on the output interface requirement. When VCCIO is connected to 5 V, the input thresholds are TTL levels, compatible with 3.3 V and 5 V logic. The output High levels are also TTL compatible. When VCCIO is connected to 3.3 V, the input thresholds are still TTL levels, and the outputs pull up to the 3.3 V rail. This makes the XC7300 family ideal for interfacing directly to 3.3 V components. In addition, the output structure is designed so the I/O can also safely interface to a mixed 3.3 V and 5 V bus. Power-On Characteristics/Master Reset Each XC7300 device undergoes a short internal initialization sequence upon device powerup. During this time (tRESET), the outputs remain 3-stated while the device is configured from its internal EPROM array and all registers are initialized. If the MR pin is tied to VCCINT, the initialization sequence is completely transparent to the user and is completed in tRESET after VCCINT has reached 4.75 V. If MR is held low while the device is powering up, the internal initialization sequence begins and outputs will remain 3-stated until the sequence is complete and MR is brought High. VCC rise must be monotonic to ensure the initialization sequence is performed correctly. For additional flexibility, the MR pin is provided so the device can be reinitialized after power is applied. On the falling edge of MR, all outputs become 3-stated and the initialization sequence begins. The outputs remain 3-stated until the internal initialization sequence is complete and MR is brought High. The minimum MR pulse with is tWMR. If MR June 1, 1996 (Version 1.0) For FB macrocell registers, the preload value is defined by a separate preload configuration bit, independent of the Set and Reset product terms. The value of this preload configuration bit may be determined by the user. If unspecified, the register preload value is Low. Power Management The XC7300 family features a power-management scheme permitting non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a small portion is speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To further reduce power dissipation, unused FBs are turned off and unused macrocells in used FBs are configured for low power operation. Erasure Characteristics In windowed packages, the EPROM array can be erased by exposure to UV light with wavelengths of approximately 4000 A. The recommended erasure time is approximately 1 hr. when the device is placed within 1 in. of an UV lamp with 12,000 W/cm2 power rating. To prevent unintentional exposure, place opaque labels over the device window. When the device is exposed to high intensity UV light for much longer periods, permanent damage can occur. The maximum integrated dose the XC7300 CPLDs can be exposed to without damage is 7000 W * s/cm2, or approximately one week at 12,000 W/cm2. Design Recommendations For proper operation, all unused input and I/O pins must be connected to a valid logic level (High or Low). The recommended decoupling for all VCC pins should total 1 F using high-speed (tantalum or ceramic) capacitors. 3-77 XC7300 CMOS CPLD Family Use electrostatic discharge (ESD) handling procedures with the XC7300 CPLDs to prevent damage to the device during programming, assembly, and test. Design Security Each member of the XC7300 family has a multibit security system that controls access to the configuration programmed into the device. This security scheme uses multiple EPROM bits at various locations within the EPROM array to offer a higher degree of design security than other EPROM and fused-based devices. Programmed data within EPROM cells is invisible-even when examined under a microscope-and cannot be selectively erased. The EPROM security bits, and the device configuration data, reset when the device is erased. High-Volume Production Programming The XC7300 family is available as a factory programmed product. For factory programming procedures, contact your local Xilinx representative. 3-78 XACTstep Development System The XC7300 CPLD family is fully supported by the Xilinx XACTstep development system. The designer can create the design using ABEL, schematics, equations, VHDL or other HDL languages in a variety of software front-end tools. The XACTstep development system can be used to implement the design and generate a bitmap which can be used to program the XC7300 devices. Timing Model Timing within the XC7300 family is accurately determined using external timing parameters from the device data sheet, a variety of CAE simulators, or with the timing model shown in Figure 8. The timing model is based on the fixed internal delays of the XC7300 architecture which consists of four basic parts: I/O Blocks, the UIM, FFBs and FBs. The timing model identifies the internal delay paths and their relationships to ac characteristics. Using this model and the ac characteristics, designers can calculate the timing information for a particular device. June 1, 1996 (Version 1.0) FOE tFOE High Density Function Block I, I/O FB Logic tLOGI tIN Input Register UIM Delay tSUIN tHIN tSUCEIN tHCEIN tCOIN CE Carry Delay tCARY8 tUIM tSUI tCOI tPDI tHI tAOI tOUT P-Term Clock tPCI P-Term OE tOEI High Density Function Block FAST INPUT FFB Logic tFOGI tIN P-Term Assignment tPTXI FFB Feedback tFFD tFSUI tFCOI tFPDI tFHI tFAOI tOUT tFCLKI FCLK X3208 Figure 8: XC7300 Timing Model Synchronous Switching Characteristics tCWF tCWF FCLK Pin tSUIN tSUCEIN tHIN tHCEIN Data/CE at Input I/O Register tCOIN tUIM Input, I/O Register to UIM tFCLKI Fast Clock Input Delay tIN tUIM Data at Input I/O Pin tLOGI tFLOGI tSUI tFSUI tHI tFHI Data at Input Register tCOI tFCOI tOUT tFOUT Register to Output Pin X3494 June 1, 1996 (Version 1.0) 3-79 XC7300 CMOS CPLD Family Combinational Switching Characteristics tIN Input, I/O Pin tUIM UIM Delay tLOGI tFLOGI Logic Delay tPTXI P-Term Assignment Delay tPDI tFPDI Transparent Register Delay tOUT tFOUT Output Buffer Output Pin X3339 Asynchronous Switching Characteristics t PCW t PCW INPUT, I/O Pin t IN INPUT, I/O DELAY t UIM UIM DELAY t LOGI CLOCK at REGISTER t SUI t HI DATA from LOGIC ARRAY t COI t UIM t AOI t UIM REGISTER to UIM t OUT t OUT REGISTER to OUTPUT Pin X3580 3-80 June 1, 1996 (Version 1.0) XC7318 18-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features General Description * The XC7318 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks interconnected by the 100%populated Universal Interconnect Matrix (UIMTM). See Figure 1 for the architecture overview. * * * * * * * * * Ultra high-performance Complex Programmable Logic Devices (CPLDs) - 5 ns pin-to-pin speeds on all fast inputs - Up to 167 MHz maximum clock frequency 100% PCI compliant High-drive 24 mA output I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch Multiple security bits for design protection Incorporates two PAL-like 24V9 Fast Function Blocks 0.8 CMOS EPROM technology Available in 44-pin PQFP and PLCC packages 17 11 PC44 7 PQ44 1 I/O 8 2 I/O 9 3 MC1-4 I/O 11 5 AND MC1-5 ARRAY MC1-6 I/O 12 6 I/O 13 7 MC1-7 I/O 14 8 I/FI MC1-8 I/O 15 9 20 I/FI MC1-9 I/O 16 10 22 28 I/FI 36 42 I/FI 29 23 43 MC2-9 I/O 37 I/FI MC2-8 I/O 30 24 38 44 I/FI MC2-7 I/O 33 27 11 17 I MC2-6 I/O 34 28 AND MC2-5 ARRAY MC2-4 I/O 35 29 I/O 36 30 MC2-3 I/O 37 31 PQ44 PC44 39 1 I/FI/MR 40 2 I/FI 41 3 I/FI 42 4 I/FI 12 18 I/FI 13 19 14 12 FFB1 12 3 9 MC1-1 I/O/FI MC1-2 MC1-3 9 UIM 12 FFB2 12 3 16 22 I 18 24 I 19 25 I MC2-2 I/O 38 32 20 26 I MC2-1 O 39 33 21 27 I FOE0 40 34 FCLK0 5 43 FCLK1 6 9 9 FOE1 44 X5455 Figure 1: XC7318 Architecture June 1, 1996 (Version 1.0) 3- 81 XC7318 18-Macrocell CMOS CPLD Power Estimation Figure 2 shows a typical power estimation for the XC7318 device, programmed as a 16-bit counter and operating at the indicated clock frequency. 200 Typical ICC (mA) 150 ance High Perform 100 Low Power 50 0 50 Clock Frequency (MHz) 100 X5693 Figure 2: Typical ICC vs. Frequency for XC7318 Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN 3- 82 Parameter Supply voltage relative to GND Commercial I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time o o TA = 0 C to 70 C Min Max Units 4.75 5.25 V 3.0 0 2.0 0 3.6 0.8 VCC +0.5 VCCIO 50.0 V V V V ns June 1, 1996 (Version 1.0) DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins CIN Input capacitance for global control pins (FCLK0, FCLK1, FOE0, FOE1) COUT1 ICC2 Output capacitance Supply current Min IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 24 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Max Units 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 6.0 pF 8.0 pF 10.0 pF 90 Typ mA Typ Max 80 160 Units ns s Notes: 1. Sample tested. 2. Measured with device programmed as a 16-bit counter. Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 tWMR MR tRESET Output Hi-Z X5349 Figure 3: Global Reset Waveform June 1, 1996 (Version 1.0) 3- 83 XC7318 18-Macrocell CMOS CPLD Fast Function Block (FFB) External AC Characteristics 1 Symbol tPD tSU tH tCO tFOE tFOD fMAX tWLH XC7318-5 Min Max 5.0 8.5 4.5 7.0 0 4.5 7.0 7.0 167.0 3.0 Parameter Fast input to output valid 2 I/O or input to output valid 2 Fast input setup time before FCLK I/O or input setup time before FCLK Fast, I/O or input hold time after FCLK FCLK input to output valid FOE input to output valid FOE input to output disable Max count frequency 2, 3 Fast Clock pulse width (High or Low) XC7318-7 Min Max 7.5 12.0 5.0 8.5 0 4.5 7.5 7.5 125.0 4.0 Units ns ns ns ns ns ns ns ns MHz ns Notes: 1. All appropriate ac specifications tested using Figure 5 as test load circuit. 2. Assumes four product terms per output. 3. Export Control Max. flip-flop toggle rate. Fast Input tSU FOE Pin tH tFOD tFOE FCLK Output tCO Output Input or I/O tSU tH tWH FCLK FCLK tCO tWL Output X5695 Figure 4: Switching Waveform VTEST R1 Device Output Test Point R2 CL Device Imput Rise and Fall Times < 3ns VCCIO Level VTEST R1 R1 CL 5V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X5222 Figure 5: AC Load Circuit 3- 84 June 1, 1996 (Version 1.0) FOE FAST INPUT I, I/O tFOE tIN Fast Function Block tIN UIM Delay FFB Logic tFLOGI tUIM P-Term Assignment tPTXI FFB Feedback tFFD FCLK tFSUI tFCOI tFPDI tFHI tFAOI tFCLKI tFOUT Pin X5221 Figure 6: XC7318 Timing Model Timing Model Timing within the XC7318 is accurately determined using external timing parameters from the device data sheet, using a variety of CAE simulators, or with the timing model shown in Figure 6. The timing model is based on the fixed internal delays of the XC7318 architecture that consists of three basic parts: I/O Blocks, the UIM and Fast Function Blocks. The timing model identifies the internal delay paths and their relationships to ac characteristics. Using this model and the ac characteristics, designers can easily calculate the timing information for the XC7318. Fast Function Block (FFB) Internal AC Characteristics Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD Note: Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay XC7318-5 Min Max 1.0 2.0 2.5 1.0 1.0 0.5 2.0 0.6 0.5 XC7318-7 Min Max 1.5 3.5 1.5 2.5 1.0 0.5 2.0 0.8 4.0 Units ns ns ns ns ns ns ns ns ns 1. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell. Internal AC Characteristics Symbol tIN tFOUT tUIM tFCLKI Parameter Input pad and buffer delay FFB output buffer and pad delay Universal Interconnect Matrix delay Fast clock buffer delay June 1, 1996 (Version 1.0) XC7318-5 Min Max 1.5 2.0 3.5 1.5 XC7318-7 Min Max 2.5 3.0 4.5 1.5 Units ns ns ns ns 3- 85 XC7318 18-Macrocell CMOS CPLD Combinational Switching Characteristics tIN Input, I/O Pin tUIM UIM Delay tLOGI tFLOGI Logic Delay tPTXI P-Term Assignment Delay tPDI tFPDI Transparent Register Delay tOUT tFOUT Output Buffer Output Pin X3339 Asynchronous Switching Characteristics t PCW t PCW INPUT, I/O Pin t IN INPUT, I/O DELAY t UIM UIM DELAY t LOGI CLOCK at REGISTER t SUI t HI DATA from LOGIC ARRAY t COI t UIM t AOI t UIM REGISTER to UIM t OUT t OUT REGISTER to OUTPUT Pin X3580 3- 86 June 1, 1996 (Version 1.0) Synchronous Switching Characteristics tCWF tCWF FCLK Pin tSUIN tSUCEIN tHIN tHCEIN Data/CE at Input I/O Register tCOIN tUIM Input, I/O Register to UIM tFCLKI Fast Clock Input Delay tIN tUIM Data at Input I/O Pin tLOGI tFLOGI tSUI tFSUI tHI tFHI Data at Input Register tCOI tFCOI tOUT tFOUT Register to Output Pin X3494 XC7318 Pinouts PQ44 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Input I/FI I/FI I/FI I/FI FCLK0 FCLK1 I/FO/FI I/FO I/FO XC7318 MR Output MC1-1 MC1-2 MC1-3 GND I/FO I/FO I/FO I/FO I/FO I/FO I I/FI I/FI I/FI MC1-4 MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 VCCINT I June 1, 1996 (Version 1.0) PQ44 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PC44 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Input XC7318 GND I I I I I/FI I/FO I/FO Output MC2-9 MC2-8 GND VCCIO I/FO I/FO I/FO I/FO I/FO I/FO FOE1/FO FOE0 MC2-7 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 VCCINT/VPP I/FI I/FI I/FI 3- 87 XC7318 18-Macrocell CMOS CPLD Ordering Information XC7318 - 5 PC 44 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -7 -5 7.5 ns pin-to-pin delay (commercial only) 5 ns pin-to-pin delay (commercial only) Packaging Options PC44 PQ44 44-Pin Plastic Leaded Chip Carrier 44-Pin Plastic Quad Flat Pack Temperature Options C Commercial 0oC to 70oC Component Availability Pins 44 Type Code XC7318 -7 -5 Plastic PLCC PC44 C C Plastic PQFP PQ44 C C C = Commercial = 0 to +70C 3- 88 June 1, 1996 (Version 1.0) XC7336/XC7336Q 36-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features General Description * The XC7336 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like 24V9 Fast Function Blocks interconnected by the 100%populated Universal Interconnect Matrix (UIMTM). See Figure 1 for the architecture overview. * * * * PQ44 PC44 22 28 I/FI The XC7336 is designed in 0.8 CMOS EPROM technology, in speed grades ranging from 5 to 15 ns. The XC7336Q is also available now, providing lower power consumption in -10, -12 and -15 ns speed grades. 19 34 I/FO/FI MC1-1 I/FO MC1-2 I/FO MC1-3 I/FO MC1-4 12 12 12 3 3 36 MC2-9 I/FO MC2-8 I/FO MC2-7 I/FO MC2-6 I/FO MC2-5 I/FO MC2-4 I/FO 29 30 33 34 35 36 37 38 39 23 24 27 28 29 30 31 32 33 40 43 44 1 2 3 4 5 6 34 37 38 39 40 41 42 43 44 MC1-5 I/FO MC1-6 I/FO MC1-7 I/FO MC1-8 MC2-2 I/FO I/FO MC1-9 MC2-1 FO/FOE1 9 9 I/FO MC4-2 I/FO MC4-3 I/FO MC4-4 I/FO MC4-5 I/FO/FI MC4-6 I/FO/FI MC4-7 I/FO/FI I/FO 12 AND ARRAY MC4-1 12 UIM I/FO 12 FFB3 12 12 3 3 9 9 AND ARRAY 12 I/FO MC2-3 9 FFB4 27 26 25 24 22 20 19 18 17 42 I/FO 9 21 20 19 18 16 14 13 12 11 I/FI FFB2 12 AND ARRAY 7 8 9 11 12 13 14 15 16 PQ44 12 FFB1 1 2 3 5 6 7 8 9 10 PC44 15 12 AND ARRAY * * * * * * Ultra high-performance Complex Programmable Logic Devices (CPLDs) - 5 ns pin-to-pin speeds on all fast inputs - Up to 167 MHz maximum clock frequency New low power XC7336Q 100% PCI compliant High-drive 24 mA output I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch Multiple security bits for design protection Incorporates four PAL-like 24V9 Fast Function Blocks 0.8 CMOS EPROM technology Available in 44-pin VQFP, PQFP and PLCC/CLCC packages MC3-9 FO/FOE0 MC3-8 I/FO/FI MC3-7 I/FO/FI MC3-6 I/FO/FI/MR MC3-5 I/FO/FI MC3-4 I/FO/FI MC3-3 I/FO/FI MC4-8 MC3-2 FO/FCLK0 MC4-9 MC3-1 FO/FCLK1 9 9 X5452 Figure 1: XC7336 Architecture June 1, 1996 (Version 1.0) 3- 89 XC7336/XC7336Q 36-Macrocell CMOS CPLD Power Estimation Figure 2 shows a typical power estimation for the XC7336 and the XC7336Q device, programmed as two 16-bit counters and operating at the indicated clock frequency. 200 ance High Perform Typical ICC (mA) 150 100 ce rforman High Pe s Q device 50 0 50 Clock Frequency (MHz) 100 X5085 Figure 2: Typical ICC vs. Frequency for XC7336 Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +250 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN 3- 90 Parameter Supply voltage relative to GND Commercial TA = 0oC to 70oC Supply voltage relative to GND Industrial TA = -40oC to 85oC I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.50 3.0 0 2.0 0 Max 5.25 5.50 3.60 0.80 VCC +0.5 VCCIO 50 Units V V V V V V ns June 1, 1996 (Version 1.0) DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 24 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins Input capacitance for global control pins (FCLK0, FCLK1, FOE0, FOE1) CIN Input capacitance for Fast Inputs COUT1 Output capacitance ICC2 Supply current CIN (Non Q) (Q) Min Max Units 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 6.0 pF 8.0 pF 12.0 pF 10.0 pF 126 Typ mA 55 Typ Notes: 1. Sample tested. 2. Measured with device programmed as two 16-bit counters. Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ Max 80 160 Units ns s tWMR MR tRESET Output Hi-Z X5349 Figure 3: Global Reset Waveform June 1, 1996 (Version 1.0) 3- 91 XC7336/XC7336Q 36-Macrocell CMOS CPLD Fast Function Block (FFB) External AC Characteristics 1 XC7336-5 Symbol Parameter tPD Fast input to output valid 2 I/O or input to output valid 2 tSU Fast input setup time before FCLK I/O or input setup time before FCLK tH Fast, I/O or input hold time after FCLK tCO FCLK input to output valid tFOE FOE input to output valid tFOD FOE input to output disable fMAX Max count frequency 2, 3 tWLH Fast Clock pulse width (High or Low) Min XC7336-7 Max 5.0 8.5 Min Max 7.5 12.0 XC7336-10 XC7336-12 XC7336-15 Min Min Min Max 10.0 15.0 Max 12.0 19.0 Max Units 15.0 ns 23.0 ns 4.5 5.0 5.0 6.0 7.0 ns 7.0 8.5 10.0 13.0 15.0 ns 0 0 0 0 0 ns 4.5 4.5 8.0 9.0 12.0 ns 7.0 7.5 10.0 12.0 15.0 ns 7.0 7.5 10.0 12.0 15.0 ns 167.0 125.0 100.0 80.0 66.7 MHz 3.0 4.0 5.0 5.5 6.0 ns XC7336Q-10 XC7336Q-12 XC7336Q-15 Symbol Parameter tPD Fast input to output valid 2 I/O or input to output valid 2 tSU Fast input setup time before FCLK I/O or input setup time before FCLK tH Fast, I/O or input hold time after FCLK tCO FCLK input to output valid tFOE FOE input to output valid tFOD FOE input to output disable fMAX Max count frequency 2, 3 tWLH Fast Clock pulse width (High or Low) Min Max 10.0 15.0 Min Max 12.0 19.0 Min Max Units 15.0 ns 23.0 ns 6.5 6.5 7.0 ns 11.5 13.5 15.0 ns 0 0 0 ns 6.5 8.5 12.0 ns 10.0 12.0 15.0 ns 10.0 12.0 15.0 ns 100.0 80.0 66.7 MHz 5.0 5.5 6.0 ns Notes: 1. All appropriate ac specifications tested using Figure 5 as test load circuit. 2. Assumes four product terms per output. 3. Export Control Max. flip-flop toggle rate. Fast Input tSU FOE Pin tH tFOD tFOE FCLK Output tCO Output Input or I/O tSU tH tWH FCLK tCO FCLK tWL Output X5695 Figure 4: Switching Waveform 3- 92 June 1, 1996 (Version 1.0) VTEST R1 Device Output Test Point CL R2 Device Imput Rise and Fall Times < 3ns VCCIO Level VTEST R1 R1 CL 5V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X5222 Figure 5: AC Load Circuit FOE FAST INPUT I, I/O tFOE tIN Fast Function Block tIN UIM Delay tUIM FFB Logic tFLOGI P-Term Assignment tPTXI FFB Feedback tFFD FCLK tFCLKI tFSUI tFCOI tFPDI tFHI tFAOI tFOUT Pin X5221 Figure 6: XC7336 Timing Model Timing Model Timing within the XC7336 is accurately determined using external timing parameters from the device data sheet, using a variety of CAE simulators, or with the timing model shown in Figure 6. The timing model is based on the fixed internal delays of the XC7336 architecture that consists of three basic parts: June 1, 1996 (Version 1.0) I/O Blocks, the UIM and Fast Function Blocks. The timing model identifies the internal delay paths and their relationships to ac characteristics. Using this model and the ac characteristics, designers can easily calculate the timing information for the XC7336. 3- 93 XC7336/XC7336Q 36-Macrocell CMOS CPLD Fast Function Block (FFB) Internal AC Characteristics XC7336-5 Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay Min Max 1.0 2.0 2.5 1.0 XC7336-7 Min Max 1.5 3.5 1.5 2.5 1.0 0.5 2.0 0.6 0.5 XC7336-10 XC7336-12 XC7336-15 Min Min Min Max 1.5 5.5 2.5 2.5 1.0 0.5 2.0 0.8 4.0 Max 2.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 4.0 3.0 1.0 1.0 3.0 1.2 6.5 Max Units 2.0 ns 8.0 ns ns ns 1.0 ns 1.0 ns 4.0 ns 1.5 ns 8.0 ns XC7336Q-10 XC7336Q-12 XC7336Q-15 Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD Note: Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay Min Max 3.0 5.5 2.5 2.5 Min Max 3.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 Min 4.0 3.0 1.0 1.0 3.0 1.2 6.5 Max Units 2.0 ns 8.0 ns ns ns 1.0 ns 1.0 ns 4.0 ns 1.5 ns 8.0 ns 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. Internal AC Characteristics XC7336-5 Symbol Parameter tIN Input pad and buffer delay tFOUT FFB output buffer and pad delay tUIM Universal Interconnect Matrix delay tFCLKI Fast clock buffer delay Min Max 1.5 2.0 3.5 1.5 XC7336-7 Min Max 2.5 3.0 4.5 1.5 XC7336-10 XC7336-12 XC7336-15 Min Min Min Max 3.5 4.5 5.0 2.5 Max 4.0 5.0 7.0 3.0 Max Units 5.0 ns 7.0 ns 8.0 ns 4.0 ns XC7336Q-10 XC7336Q-12 XC7336Q-15 Symbol Parameter tIN Input pad and buffer delay tFOUT FFB output buffer and pad delay tUIM Universal Interconnect Matrix delay tFCLKI Fast clock buffer delay 3- 94 Min Max 3.5 3.0 5.0 2.5 Min Max 4.0 4.5 7.0 3.0 Min Max Units 5.0 ns 7.0 ns 8.0 ns 4.0 ns June 1, 1996 (Version 1.0) Combinational Switching Characteristics tIN Input, I/O Pin tUIM UIM Delay tLOGI tFLOGI Logic Delay tPTXI P-Term Assignment Delay tPDI tFPDI Transparent Register Delay tOUT tFOUT Output Buffer Output Pin X3339 Asynchronous Switching Characteristics t PCW t PCW INPUT, I/O Pin t IN INPUT, I/O DELAY t UIM UIM DELAY t LOGI CLOCK at REGISTER t SUI t HI DATA from LOGIC ARRAY t COI t UIM t AOI t UIM REGISTER to UIM t OUT t OUT REGISTER to OUTPUT Pin X3580 June 1, 1996 (Version 1.0) 3- 95 XC7336/XC7336Q 36-Macrocell CMOS CPLD Synchronous Switching Characteristics tCWF tCWF FCLK Pin tSUIN tSUCEIN tHIN tHCEIN Data/CE at Input I/O Register tCOIN tUIM Input, I/O Register to UIM tFCLKI Fast Clock Input Delay tIN tUIM Data at Input I/O Pin tLOGI tFLOGI tSUI tFSUI tHI tFHI Data at Input Register tCOI tFCOI tOUT tFOUT Register to Output Pin X3494 XC7336 Pinouts VQ44/PQ44 PC44 Input XC7336 Output VQ44/PQ44 PC44 39 40 41 42 43 44 1 2 3 4 1 2 3 4 5 6 7 8 9 10 I/FO/FI I/FO/FI I/FO/FI I/FO/FI FO/FCLK0 FO/FCLK1 I/FO/FI I/FO I/FO MR MC3-6 MC3-5 MC3-4 MC3-3 MC3-2 MC3-1 MC1-1 MC1-2 MC1-3 17 18 19 20 21 22 23 24 25 26 23 24 25 26 27 28 29 30 31 32 5 6 7 8 9 10 11 12 13 11 12 13 14 15 16 17 18 19 I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI MC1-4 MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 MC4-9 MC4-8 MC4-7 27 28 29 30 31 32 33 34 35 33 34 35 36 37 38 39 40 41 I/FO I/FO I/FO I/FO I/FO I/FO FO/FOE1 FO/FOE0 14 15 20 21 I/FO/FI MC4-6 36 37 42 43 I/FI I/FO/FI MC3-8 16 22 I/FO MC4-5 38 44 I/FO/FI MC3-7 3- 96 GND VCCINT Input XC7336 Output GND I/FO I/FO I/FO I/FO I/FI I/FO I/FO MC4-4 MC4-3 MC4-2 MC4-1 MC2-9 MC2-8 GND VCCIO MC2-7 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 MC3-9 VCCINT/VPP June 1, 1996 (Version 1.0) Ordering Information XC7336 Q - 5 PC 44 C Device Type Temperature Range Power Option Speed Number of Pins Package Type Packaging Options Power Options Q Low Power -10, -12, -15 speeds Speed Options -15 -12 -10 -7 -5 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay (commercial only) 5 ns pin-to-pin delay (commercial only) PC44 44-Pin Plastic Leaded Chip Carrier WC44 44-Pin Windowed Ceramic Leaded Chip Carrier PQ44 44-Pin Plastic Quad Flat Pack VQ44 44-Pin Thin Quad Pack Temperature Options C I Commercial0C to 70C Industrial-40C to 85C Component Availability Pins Type 44 Code XC7336 XC7336Q -15 -12 -10 -7 -5 -15 -12 -10 Plastic PLCC PC44 CI CI CI C C CI CI C C = Commercial = 0 to +70C June 1, 1996 (Version 1.0) Ceramic CLCC WC44 CI CI CI C C CI CI C Plastic PQFP PQ44 CI C C C C C C C Plastic VQFP VQ44 C C C I = Industrial = -40 to 85C 3- 97 XC7336/XC7336Q 36-Macrocell CMOS CPLD 3- 98 June 1, 1996 (Version 1.0) XC7354 54-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: * * * * * * * * * * * * * * High-performance Complex Programmable Logic Devices (CPLDs) - 7.5 ns pin-to-pin speeds on all fast inputs - Up to 125 MHz maximum clock frequency 100% PCI compliant 18 outputs with 24 mA drive I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 61 MHz 18-bit accumulators Multiple independent clocks Up to 54 inputs programmable as direct, latched, or registered Power management options Multiple security bits for design protection 54 macrocells with programmable I/O architecture Advanced Dual-Block architecture - 2 Fast Function Blocks - 4 High-Density Function Blocks 0.8 CMOS EPROM technology Available in 44-pin and 68-pin PLCC and CLCC packages ICC (mA)=MCHP (3.0) + MCLP (2.6) + MC (0.006 mA/MHz) f Where: MCHP MCLP MC f = = = = Macrocells in high-performance mode Macrocells in low-power mode Total number of macrocells used Clock frequency (MHz) Figure 1 shows a typical power calculation for the XC7354 device, programmed as three 16-bit counters and operating at the indicated clock frequency. 200 ance High Perform 150 Typical ICC (mA) * Low Power 100 50 General Description The XC7354 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks and four High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIMTM). 0 50 Clock Frequency (MHz) 100 X5286 Figure 1: Typical ICC vs. Frequency for XC7354 Power Management The XC7354 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. June 1, 1996 (Version 1.0) 3- 99 XC7354 54-Macrocell CMOS CPLD PC44 PC68 43 42 28 67 65 43 PC68 PC44 I/FI I/FI I/FI I/FI/MR I/FI I/FI I/FI I/FI I/FI 6 12 MC1-1 MC2-9 I/FO I/FO MC1-2 MC2-8 I/FO I/FO MC1-3 MC2-7 I/FO I/FO MC1-4 MC2-6 I/FO I/FO MC1-5 MC2-5 I/FO I/FO MC1-6 MC2-4 I/FO I/FO MC1-7 MC2-3 I/FO I/FO MC1-8 MC2-2 I/FO I/FO MC1-9 MC2-1 I/FO 12 AND ARRAY 12 3 3 9 9 Carry Serial Shift O/FCLK0 MC6-3 O/FCLK1 MC6-4 O/FCLK2 MC6-5 I/O/FI MC6-6 I/O/FI MC6-7 I/O/FI MC6-8 I/O/FI MC6-9 UIM 21 21 I/O/FI MC3-8 I/O/FI MC3-7 I/O/FI MC3-6 O/FOE1 MC3-5 O/FOE0 MC3-4 O/CKEN1 MC3-3 O/CKEN0 MC3-1 FB4 MC5-1 MC4-9 I/O/FI I/O MC5-2 MC4-8 I/O/FI I/O MC5-3 MC4-7 I/O/FI I/O MC5-4 I/O MC5-5 I/O MC5-6 I/O/FI MC5-7 21 21 AND ARRAY I/O AND ARRAY 32 33 35 37 16 18 25 31 36 MC3-9 MC3-2 FB5 -- -- -- -- -- -- 17 22 24 27 26 25 -- -- -- -- -- -- FB3 AND ARRAY MC6-2 AND ARRAY I/O/FI 42 40 39 -- -- -- 54 53 38 18 Arithmetic FB6 MC6-1 -- -- -- -- 40 -- 39 18 18 I/O/FI 47 45 44 64 62 61 60 9 24 27 28 8 9 10 29 6 24 26 29 30 33 34 35 36 37 38 -- FFB2 9 18 19 5 6 -- 20 -- -- -- 46 48 51 52 55 56 57 58 66 12 I/FO AND ARRAY 4 12 13 15 17 19 21 22 23 44 1 2 3 4 7 6 12 FFB1 -- 8 9 11 12 13 14 15 16 68 1 2 3 5 11 MC4-6 MC4-5 MC4-4 MC4-3 I/O I/O/FI MC5-8 MC4-2 I/O I/O/FI MC5-9 MC4-1 I/O Serial Shift Arithmetic Carry X5458 Figure 2: XC7354 Architecture 3- 100 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO 50 Units V V V V V V V ns Max Units DC Characteristics Over Recommended Operating Conditions Symbol VOH VOL IIL IOZ CIN CIN COUT1 ICC2 Parameter Test Conditions IOH = -4.0 mA 5 V TTL High-level output voltage VCC = Min IOH = -3.2 mA 3.3 V High-level output voltage VCC = Min IOL = 24 mA (FO) 5 V TTL Low-level output voltage IOL = 12 mA (I/O) VCC = Min IOL = 10 mA 3.3 V Low-level output voltage VCC = Min VCC = Max Input leakage current VIN = GND or VCCIO VCC = Max Output high-Z leakage current VIN = GND or VCCIO VIN = GND Input capacitance for Input and I/O pins f = 1.0 MHz Input capacitance for global control pins (FCLK0, VIN = GND FCLK1, FCLK2, FOE0, FOE1) f = 1.0 MHz VIN = GND Output capacitance f = 1.0 MHz VIN = VCC or GND Supply current (low power mode) VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Min 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 8.0 pF 12.0 pF 10.0 pF 140 Typ mA Notes: 1. Sample tested. 2. Measured with device programmed as three 16-bit counters. June 1, 1996 (Version 1.0) 3- 101 XC7354 54-Macrocell CMOS CPLD Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ Max 80 160 Units ns s Fast Function Block (FFB) External AC Characteristics3 XC7354-7 (Com only) Parameter fCF Max count frequency 1, 2, 4 tSUF Fast input setup time before FCLK 1 tHF Fast input hold time after FCLK tCOF FCLK to output valid tPDFO Fast input to output valid 1, 2 tPDFU I/O to output valid 1, 2 tCWF Fast clock pulse width Symbol Min 125.0 4.0 0 Max XC7354-10 (Com/Ind only) Min 100.0 5.0 0 5.5 7.5 12.0 4.0 Max XC7354-12 Min 80.0 6.0 0 8.0 10.0 16.0 5.0 XC7354-15 Max Min 66.7 7.0 0 9.0 12.0 19.0 5.5 Max 12.0 15.0 23.0 6.0 Units MHz ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3. All appropriate AC specifications tested using Figure 3 as the test load circuit. 4. Export Control Max. flip-flop toggle rate. High-Density Function Block (FB) External AC Characteristics Symbol fC tSU tH tCO tPSU tPH tPCO tPD tCW tPCW Parameter Max count frequency 1, 2 I/O setup time before FCLK 1, 2 I/O hold time after FCLK FCLK to output valid I/O setup time before p-term clock 2 I/O hold time after p-term clock P-term clock to output valid I/O to output valid 1, 2 Fast clock pulse width P-term clock pulse width XC7354-7 (Com only) Min Max 95.2 10.5 0 XC7354-10 (Com/Ind only) Min Max 76.9 13.0 0 7.0 4.0 0 XC7354-15 Min Max 66.7 15.0 0 55.6 18.0 0 10.0 6.0 0 13.5 16.5 4.0 5.0 XC7354-12 Min Max 12.0 7.0 0 17.0 22.0 5.0 6.0 15.0 9.0 0 20.0 27.0 5.5 7.5 24.0 32.0 6.0 8.5 Units MHz ns ns ns ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3- 102 June 1, 1996 (Version 1.0) Fast Function Block (FFB) Internal AC Characteristics XC7354-7 (Com only) Symbol Parameter tFLOGI FFB logic array delay 1 tFLOGILP Low-power FFB logic array delay 1 tFSUI FFB register setup time tFHI FFB register hold time tFCOI FFB register clock-to-output delay tFPDI FFB register pass through delay tFAOI FFB register async. set delay tPTXI FFB p-term assignment delay tFFD FFB feedback delay Min Max 1.5 3.5 1.5 2.5 XC7354-10 (Com/Ind only) Min Max 1.5 5.5 2.5 2.5 1.0 0.5 2.0 0.8 4.0 XC7354-12 Min Max 2.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 XC7354-15 Min Max 2.0 8.0 4.0 3.0 1.0 1.0 3.0 1.2 6.5 1.0 1.0 4.0 1.5 8.0 Units ns ns ns ns ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. High-Density Function Block (FB) Internal AC Characteristics Symbol Parameter FB logic array delay 1 tLOGILP Low power FB logic delay 1 tSUI FB register setup time tHI FB register hold time tCOI FB register clock-to-output delay tPDI FB register pass through delay tAOI FB register async. set/reset delay tRA Set/reset recovery time before FCLK tHA Set/reset hold time after FCLK tPRA Set/reset recovery time before p-term clock tPHA Set/reset hold time after p-term clock tPCI FB p-term clock delay tOEI FB p-term output enable delay tCARY8 ALU carry delay within 1 FB 2 tCARYFB Carry lookahead delay per additional Functional Block 2 XC7354-7 (Com only) Min Max tLOGI XC7354-10 (Com/Ind only) Min Max 3.5 7.0 1.5 3.5 1.0 1.5 2.5 5.0 11.0 1.0 2.5 3.0 4.0 5.0 1.0 4.0 4.0 18.0 0 12.0 6.0 1.0 3.0 5.0 1.0 4.0 9.0 3.0 4.0 16.0 0 10.0 5.0 XC7354-15 Min Max 3.5 7.5 2.5 3.5 13.5 0 7.5 XC7354-12 Min Max 21.0 0 15.0 8.0 0 4.0 6.0 1.5 1.0 4.0 5.0 9.0 0 5.0 8.0 2.0 0 7.0 12.0 3.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with registered outputs. June 1, 1996 (Version 1.0) 3- 103 XC7354 54-Macrocell CMOS CPLD I/O Block External AC Characteristics Symbol Parameter XC7354-7 XC7354-10 (Com only) (Com/Ind only) Min Max fIN Max pipeline frequency (input register to FFB or 95.2 FB register) 1 4.0 tSUIN Input register/latch setup time before FCLK tHIN Input register/latch hold time after FCLK 0 tCOIN FCLK to input register/latch output tCESUIN Clock enable setup time before FCLK 5.0 tCEHIN Clock enable hold time after FCLK 0 tCWHIN FCLK pulse width high time 4.0 tCWLIN FCLK pulse width low time 4.0 XC7354-12 Min Max XC7354-15 Min Max Units 76.9 66.7 55.6 MHz 5.0 0 6.0 0 7.0 0 ns ns ns ns ns ns ns Min Max 2.5 3.5 4.0 7.0 0 5.0 5.0 8.0 0 5.5 5.5 5.0 10.0 0 6.0 6.0 Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. Internal AC Characteristics Symbol tIN tFOUT tOUT tUIM tFOE tFOD tFCLKI Parameter XC7354-7 XC7354-10 (Com only) (Com/Ind only) Min Max Input pad and buffer delay FFB output buffer and pad delay FB output buffer and pad delay Universal Interconnect Matrix delay FOE input to output valid FOE input to output disable Fast clock buffer delay Min 2.5 3.0 4.5 4.5 7.5 7.5 1.5 Max XC7354-12 Min Max XC7354-15 Min Max 3.5 4.5 6.5 6.0 10.0 10.0 2.5 4.0 5.0 8.0 7.0 12.0 12.0 3.0 5.0 7.0 10.0 8.0 15.0 15.0 4.0 Units ns ns ns ns ns ns ns VTEST R1 Device Output Test Point R2 CL Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL FO 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X3491 Figure 3: AC Load Circuit 3- 104 June 1, 1996 (Version 1.0) XC7354 Pinouts PC68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PC44 1 2 3 - 4 - - 5 6 - 7 8 9 10 11 - 12 - 13 - 14 15 16 - 17 - 18 19 20 21 22 - - 23 Input I/FI/ MR I/FI I/FI I/FO I/FI I/O/FI XC7354 Output MC1-1 MC6-7 GND O/FCLK0 O/FCLK1 O/FCLK2 I/FI I/FO I/FO MC6-3 MC6-4 MC6-5 MC1-2 MC1-3 GND I/FO I/O I/FO I/O I/FO MC1-4 MC5-5 MC1-5 MC5-6 MC1-6 VCCIO I/FO I/FO I/FO I/O/FI I/O/FI I/O/FI I/O/FI I/O/FI I/O/FI MC1-7 MC1-8 MC1-9 MC6-8 MC5-7 MC6-9 MC6-1 MC6-2 MC6-6 VCCINT I/O/FI I/O I/O June 1, 1996 (Version 1.0) MC5-8 MC5-1 MC5-2 GND PC68 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PC44 - 24 - - 25 26 - 27 28 - - 29 - 30 31 32 33 34 - - 35 36 37 38 - 39 - 40 41 - 42 - 43 44 Input I/O I/O/FI I/O I/O I/O/FI I/O/FI XC7354 Output MC5-3 MC5-9 MC5-4 MC4-1 MC4-7 MC4-8 GND I/O/FI I/FI I/O/FI I/O/FI I/FO I/O/FI I/FO MC4-9 MC3-7 MC3-8 MC2-9 MC3-9 MC2-8 GND VCCIO I/FO I/FO I/O I/O I/FO I/FO I/FO I/FO MC2-7 MC2-6 MC4-2 MC4-3 MC2-5 MC2-4 MC2-3 MC2-2 VCCINT O/CKEN0 O/CKEN1 O/FOE0 MC3-3 MC3-4 MC3-5 VCCINT/VPP O/FOE1 I/FI I/FO I/FI I/FI MC3-6 MC2-1 3- 105 XC7354 54-Macrocell CMOS CPLD Ordering Information XC7354 - 7 PC 68 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -15 -12 -10 -7 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay (commercial and industrial only) 7.5 ns pin-to-pin delay (commercial only) Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier WC44 44-Pin Windowed Ceramic Leaded Chip Carrier PC68 68-Pin Plastic Leaded Chip Carrier WC68 68-Pin Windowed Ceramic Leaded Chip Carrier Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case) Component Availability Pins 44 Type Code XC7354 -15 -12 -10 -7 C = Commercial = 0 to +70C 3- 106 Plastic PLCC PC44 CI CI CI C 68 Ceramic CLCC WC44 CI CI CI C I = Industrial = -40 to 85C Plastic PLCC PC68 CI CI CI C Ceramic CLCC WC68 CIM CIM CI C M = Military = -55C(A) to 125C (C) June 1, 1996 (Version 1.0) XC7372 72-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features tion Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. * * * * * * * * * * * * * * High-performance Complex Programmable Logic Devices (CPLDs) - 7.5 ns pin-to-pin speeds on all fast inputs - Up to 125 MHz maximum clock frequency 100% PCI compliant 18 outputs with 24 mA drive I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 61 MHz 18-bit accumulators Multiple independent clocks Up to 84 inputs programmable as direct, latched, or registered Power management options Multiple security bits for design protection 72 macrocells with programmable I/O architecture Advanced Dual-Block architecture - 2 Fast Function Blocks - 6 High-Density Function Blocks 0.8 CMOS EPROM technology Available in 68-pin and 84-pin PLCC/CLCC and 100-pin PQFP packages General Description The XC7372 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks and six High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIMTM). See Figure 2 for the architecture overview. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA)=MCHP (3.1) + MCLP (2.6) + MC (0.012 mA/MHz) f Where: MCHP MCLP MC f = = = = Macrocells in high-performance mode Macrocells in low-power mode Total number of macrocells used Clock frequency (MHz) Figure 1 shows a typical power calculation for the XC7372 device, programmed as four 16-bit counters and operating at the indicated clock frequency. 400 300 Typical ICC (mA) * High ce rman Perfo Low r Powe 200 100 0 50 Clock Frequency (MHz) 100 X5287 Figure 1: Typical ICC vs. Frequency for XC7372 Power Management The XC7372 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Func- June 1, 1996 (Version 1.0) 3- 107 XC7372 72-Macrocell CMOS CPLD PC68 PC84 PQ100 68 67 66 65 64 -- 84 83 82 81 80 79 14 13 12 11 10 8 I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI 6 12 FO MC1-1 MC2-9 FO FO MC1-2 MC2-8 FO FO MC1-3 MC2-7 FO FO MC1-4 MC2-6 FO FO MC1-5 MC2-5 FO FO MC1-6 MC2-4 FO FO MC1-7 MC2-3 FO FO MC1-8 MC2-2 FO FO MC1-9 MC2-1 FO 12 12 3 3 9 9 Carry Serial Shift MC8-2 O/FCLK0 MC8-3 O/FCLK1 MC8-4 O/FCLK2 MC8-5 O MC8-6 I/O/FI MC8-7 I/O/FI I/O/FI UIM 21 21 51 52 54 57 58 60 62 63 65 I/OFI MC3-6 O/FOE1 O/FOE0 O/CKEN1 O/CKEN0 MC8-8 MC3-2 O MC8-9 MC3-1 O MC4-9 I/O/FI MC7-2 MC4-8 I/O/FI I/O MC7-3 MC4-7 I/O/FI I/O MC7-4 MC4-6 I/O I/O MC7-5 MC4-5 I/O I/O MC7-6 MC4-4 I/O I/O/FI MC7-7 MC4-3 I/O I/O/FI MC7-8 MC4-2 I/O I/O/FI MC7-9 MC4-1 I/O 21 21 AND ARRAY MC7-1 I/O MC6-1 MC5-9 I/O/FI I/O MC6-2 MC5-8 I/O/FI I/O MC6-3 MC5-7 I/O/FI I/O MC6-4 MC5-6 I/O MC5-5 I/O MC5-4 I/O MC5-3 I/O MC6-5 94 82 9 6 5 3 1 81 75 -- -- -- 77 76 75 74 -- -- -- -- -- -- 62 61 60 -- -- 89 88 87 84 73 74 85 83 80 63 62 61 58 51 52 59 57 56 -- -- -- -- -- -- 48 47 46 79 78 76 72 70 69 68 67 66 55 54 53 50 48 47 46 45 44 45 44 43 42 40 39 38 37 36 FB5 I/O I/O 51 52 53 54 55 56 57 58 -- FB4 I/O AND ARRAY 31 32 33 36 37 39 40 41 43 I/O/FI MC3-7 MC3-3 FB6 25 26 27 28 29 31 32 33 35 I/O/FI MC3-8 MC3-4 21 21 AND ARRAY 41 42 43 55 56 44 47 49 50 MC3-9 MC3-5 AND ARRAY 23 24 25 34 35 26 28 29 30 65 66 67 68 69 70 71 72 -- FB3 FB7 -- -- -- -- -- 21 22 23 24 91 92 93 95 96 97 98 99 4 27 AND ARRAY MC8-1 O AND ARRAY O 2 3 4 5 6 -- 21 27 Arithmetic FB8 36 45 24 25 29 48 61 21 27 2 3 4 5 6 7 9 21 -- -- 9 10 12 -- -- -- 11 16 17 18 19 20 22 FFB2 9 -- -- 8 9 10 -- -- -- -- PC68 12 AND ARRAY 26 30 31 32 34 35 37 38 39 AND ARRAY -- 13 14 15 17 18 19 20 21 PC84 6 12 FFB1 -- 11 12 13 15 16 17 18 19 PQ100 I/O MC6-6 I/O/FI MC6-7 I/O/FI MC6-8 MC5-2 I/O I/O/FI MC6-9 MC5-1 I/O Serial Shift Arithmetic Carry X5464 Figure 2: XC7372 Architecture 3- 108 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT/ VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO 50 Units V V V V V V V ns Max Units DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins CIN Input capacitance for global control pins (FCLK0, FCLK1, FCLK2, FOE0, FOE1) COUT1 ICC2 Output capacitance Supply current (low power mode) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA (FO) IOL = 12 mA (I/O) VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Min 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 8.0 pF 12.0 pF 10.0 pF 187 Typ mA Notes: 1. Sample tested. 2. Measured with device programmed as four 16-bit counters. June 1, 1996 (Version 1.0) 3- 109 XC7372 72-Macrocell CMOS CPLD Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ Max 80 160 Units ns s Fast Function Block (FFB) External AC Characteristics3 XC7372-7 (Com only) Parameter fCF Max count frequency 1, 2, 4 tSUF Fast input setup time before FCLK 1 tHF Fast input hold time after FCLK tCOF FCLK to output valid tPDFO Fast input to output valid 1, 2 tPDFU I/O to output valid 1, 2 tCWF Fast clock pulse width (High or Low) Symbol Min 125.0 4.0 0 Max XC7372-10 (Com/Ind only) Min 100.0 5.0 0 5.5 7.5 14.0 4.0 Max XC7372-12 Min 80.0 6.0 0 8.0 10.0 17.0 5.0 XC7372-15 Max Min 66.7 7.0 0 9.0 12.0 20.0 5.5 Max 12.0 15.0 24.0 6.0 Units MHz ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3. All appropriate specifications tested using Figure 3 as the test load circuit. 4. Export Control Max. flip-flop toggle rate. High-Density Function Block (FB) External AC Characteristics Symbol fC tSU tH tCO tPSU tPH tPCO tPD tCW tPCW Parameter Max count frequency 1, 2 I/O setup time before FCLK 1, 2 I/O hold time after FCLK FCLK to output valid I/O setup time before p-term clock 2 I/O hold time after p-term clock P-term clock to output valid I/O to output valid 1, 2 Fast clock pulse width P-term clock pulse width XC7372-7 (Com only) Min Max 95.2 12.5 0 XC7372-10 (Com/Ind only) Min Max 71.4 14.0 0 7.0 6.0 0 XC7372-15 Min Max 62.5 16.0 0 52.6 19.0 0 10.0 6.0 0 13.5 18.5 4.0 5.0 XC7372-12 Min Max 12.0 7.0 0 18.0 23.0 5.0 6.0 15.0 9.0 0 21.0 28.0 5.5 7.5 25.0 33.0 6.0 8.5 Units MHz ns ns ns ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3- 110 June 1, 1996 (Version 1.0) Fast Function Block (FFB) Internal AC Characteristics XC7372-7 (Com only) Symbol Parameter tFLOGI FFB logic array delay 1 tFLOGILP Low-power FFB logic array delay 1 tFSUI FFB register setup time tFHI FFB register hold time tFCOI FFB register clock-to-output delay tFPDI FFB register pass through delay tFAOI FFB register async. set delay tPTXI FFB p-term assignment delay tFFD FFB feedback delay Min Max 1.5 3.5 1.5 2.5 XC7372-10 (Com/Ind only) Min Max 1.5 5.5 2.5 2.5 1.0 0.5 2.0 0.8 4.0 XC7372-12 Min Max 2.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 XC7372-15 Min Max 2.0 8.0 4.0 3.0 1.0 1.0 3.0 1.2 6.5 1.0 1.0 4.0 1.5 8.0 Units ns ns ns ns ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. High-Density Function Block (FB) Internal AC Characteristics Symbol Parameter FB logic array delay 1 tLOGILP Low power FB logic delay 1 tSUI FB register setup time tHI FB register hold time tCOI FB register clock-to-output delay tPDI FB register pass through delay tAOI FB register async. set/reset delay tRA Set/reset recovery time before FCLK tHA Set/reset hold time after FCLK tPRA Set/reset recovery time before p-term clock tPHA Set/reset hold time after p-term clock tPCI FB p-term clock delay tOEI FB p-term output enable delay tCARY8 ALU carry delay within 1 FB 2 tCARYFB Carry lookahead delay per additional Functional Block 2 XC7372-7 (Com only) Min Max tLOGI XC7372-10 (Com/Ind only) Min Max 3.5 7.0 1.5 3.5 1.0 1.5 2.5 5.0 11.0 1.0 2.5 3.0 4.0 5.0 1.0 4.0 4.0 19.0 0 12.0 6.0 1.0 3.0 5.0 1.0 4.0 9.0 3.0 4.0 17.0 0 10.0 5.0 XC7372-15 Min Max 3.5 7.5 2.5 3.5 13.5 0 7.5 XC7372-12 Min Max 22.0 0 15.0 8.0 0 4.0 6.0 1.5 1.0 4.0 5.0 9.0 0 5.0 8.0 2.0 0 7.0 12.0 3.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with registered outputs. June 1, 1996 (Version 1.0) 3- 111 XC7372 72-Macrocell CMOS CPLD I/O Block External AC Characteristics Symbol Parameter XC7372-7 XC7372-10 (Com only) (Com/Ind only) Min Max fIN Max pipeline frequency (input register to FFB or 95.2 FB register) 1 4.0 tSUIN Input register/latch setup time before FCLK tHIN Input register/latch hold time after FCLK 0 tCOIN FCLK to input register/latch output tCESUIN Clock enable setup time before FCLK 5.0 tCEHIN Clock enable hold time after FCLK 0 tCWHIN FCLK pulse width high time 4.0 tCWLIN FCLK pulse width low time 4.0 XC7372-12 Min Max XC7372-15 Min Max Units 71.4 62.5 52.6 MHz 5.0 0 6.0 0 7.0 0 ns ns ns ns ns ns ns Min Max 2.5 3.5 4.0 7.0 0 5.0 5.0 8.0 0 5.5 5.5 5.0 10.0 0 6.0 6.0 Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. Internal AC Characteristics Symbol tIN tFOUT tOUT tUIM tFOE tFOD tFCLKI Parameter XC7372-7 XC7372-10 (Com only) (Com/Ind only) Min Max Input pad and buffer delay FFB output buffer and pad delay FB output buffer and pad delay Universal Interconnect Matrix delay FOE input to output valid FOE input to output disable Fast clock buffer delay Min 2.5 3.0 4.5 6.5 7.5 7.5 1.5 Max XC7372-12 Min Max XC7372-15 Min Max 3.5 4.5 6.5 7.0 10.0 10.0 2.5 4.0 5.0 8.0 8.0 12.0 12.0 3.0 5.0 7.0 10.0 9.0 15.0 15.0 4.0 Units ns ns ns ns ns ns ns VTEST R1 Device Output Test Point CL R2 Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL FO 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X3491 Figure 3: AC Load Circuit 3- 112 June 1, 1996 (Version 1.0) XC7372 Pinouts PQ100 PC84 PC68 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 - 7 8 9 10 - 11 - 12 13 14 15 16 17 18 - 19 20 21 22 23 24 25 26 - 27 28 - 29 30 1 2 3 4 5 6 - - 7 8 9 - - - 10 11 12 13 14 15 16 - 17 18 19 20 - - - 21 - - 22 - 23 24 51 52 53 54 55 56 57 31 32 - 33 34 35 36 58 59 60 61 62 63 64 37 38 39 - 40 41 42 Input XC7372 Output MR I/FI I/FI I/FI I/FI I/FI I/O/FI I/FI MC8-8 GND O/FCLK0 O/FCLK1 FO I/O/FI MC8-3 MC8-4 MC1-1 MC8-9 VCCIO O/FCLK2 FO FO FO MC8-5 MC1-2 MC1-3 MC1-4 GND FO FO O FO FO FO MC1-5 MC1-6 MC8-1 MC1-7 MC1-8 MC1-9 VCCIO I/O I/O I/O I/O O MC7-1 MC7-2 MC7-3 MC7-6 MC8-2 GND I/O/FI O I/O/FI I/O/FI MC7-7 MC8-6 MC7-8 MC7-9 25 26 - 27 - - 28 I/O I/O MC6-1 MC6-2 29 30 31 - 32 33 34 I/O VCCIO I/O I/O I/O I/O MC6-3 MC7-4 MC7-5 MC6-4 MC6-5 VCCINT I/O I/O/FI I/O/FI I/O/FI June 1, 1996 (Version 1.0) MC6-6 MC8-7 MC6-7 MC6-8 GND PQ100 PC84 PC68 Input 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 43 44 45 46 47 48 49 50 51 52 - 53 - 54 55 56 - - 57 58 59 60 61 62 63 64 65 66 67 - 68 69 70 71 72 73 35 36 37 38 39 40 41 42 - - - 43 - 44 45 46 - - 47 - 48 49 - - - 50 51 52 53 - 54 55 56 57 58 59 I/O/FI I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 74 - 75 - 76 77 78 60 - 61 - 62 - 63 O/CKEN0 8 9 10 11 12 13 14 79 - 80 81 82 83 84 - - 64 65 66 67 68 I/FI I/O/FI I/FI I/FI I/FI I/FI I/FI XC7372 Output MC6-9 MC5-1 MC5-2 MC5-3 MC5-4 MC5-5 GND I/O I/O I/O O I/O/FI MC5-6 MC4-5 MC4-4 MC3-1 MC5-7 GND I/O/FI I/O/FI I/O O I/O/FI I/O I/O I/O MC5-8 MC5-9 MC4-1 MC3-2 MC3-8 MC4-2 MC4-6 MC4-3 GND I/O/FI I/O/FI I/O/FI MC4-7 MC4-8 MC4-9 VCCIO FO FO FO I/O/FI FO FO FO FO FO MC2-9 MC2-8 MC2-7 MC3-9 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 VCCINT MC3-3 GND O/CKEN1 FO O/FOE0 O/FOE1 MC3-4 MC2-1 MC3-5 MC3-6 VCCINT/ VPP MC3-7 3- 113 XC7372 72-Macrocell CMOS CPLD Ordering Information XC7372 - 7 PC 84 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -15 -12 -10 -7 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay (commercial and industrial only) 7.5 ns pin-to-pin delay (commercial only) Packaging Options PC68 68-Pin Plastic Leaded Chip Carrier WC68 68-Pin Windowed Ceramic Leaded Chip Carrier PC84 84-Pin Plastic Leaded Chip Carrier WC84 84-Pin Windowed Ceramic Leaded Chip Carrier PQ100 100-Pin Plastic Quad Flat Pack Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case) Component Availability Pins 68 Type Code XC7372 -15 -12 -10 -7 Plastic PLCC PC68 CI CI CI C C = Commercial = 0 to +70C 3- 114 84 Ceramic CLCC WC68 CIM CIM CI C Plastic PLCC PC84 CI CI CI C I = Industrial = -40 to 85C Ceramic CLCC WC84 CIM CI CI C 100 Plastic PQFP PQ100 CI CI CI C M = Military = -55C(A) to 125C (C) June 1, 1996 (Version 1.0) XC73108 108-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. * * * * * * * * * * * * * * High-performance Complex Programmable Logic Devices (CPLDs) - 7.5 ns pin-to-pin speeds on all fast inputs - Up to 125 MHz maximum clock frequency 100% PCI compliant 18 outputs with 24 mA drive I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 56 MHz 18-bit accumulators Multiple independent clocks Up to 120 inputs programmable as direct, latched, or registered Power management options Multiple security bits for design protection 108 macrocells with programmable I/O architecture Advanced Dual-Block architecture - 2 Fast Function Blocks - 10 High-Density Function Blocks 0.8 CMOS EPROM technology Available in 84-pin and 84-pin PLCC/CLCC, 144-pin PGA, 100-pin and 160-pin PQFP, and 225-pin BGA packages General Description The XC73108 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks and ten High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIMTM). Power Management The XC73108 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. June 1, 1996 (Version 1.0) Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA)=MCHP (2.4) + MCLP (2.1) + MC (0.015 mA/MHz) f Where: MCHP MCLP MC f = = = = Macrocells in high-performance mode Macrocells in low-power mode Total number of macrocells used Clock frequency (MHz) Figure 1 shows a typical power calculation for the XC73108 device, programmed as six 16-bit counters and operating at the indicated clock frequency. 400 300 Typical ICC (mA) * High ce rman Perfo 200 Low er Pow 100 0 50 Clock Frequency (MHz) 100 X5697 Figure 1: Typical ICC vs. Frequency for XC73108 3- 115 XC73108 108-Macrocell CMOS CPLD PC84 PQ100 BG225/ PG144 PQ160 84 83 82 81 80 79 14 13 12 11 10 8 H1 H2 G1 G3 E1 F3 19 18 17 15 13 11 -- 13 14 15 17 18 19 20 21 26 30 31 32 34 35 37 38 39 N3 P4 P5 N6 P7 R6 P8 R8 N8 36 44 47 49 54 56 58 59 60 PQ160 I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI 6 FO FO MC1-2 FO MC1-3 FO MC1-4 FO MC1-5 FO MC1-6 FO MC1-7 FO FO 12 FO MC2-8 FO MC2-7 FO MC2-6 FO MC2-5 FO MC2-4 FO MC2-3 FO MC1-8 MC2-2 FO MC1-9 MC2-1 FO 12 12 AND ARRAY AND ARRAY MC2-9 3 3 9 9 Serial Shift I/O/FI MC3-8 I/O/FI I/O MC12-3 MC3-7 I/O/FI I/O MC12-4 MC3-6 I/O I/O MC12-5 MC3-5 I/O I/O MC12-6 MC3-4 I/O I/O/FI MC12-7 MC3-3 I/O I/O/FI MC12-8 MC3-2 I/O I/O/FI MC12-9 MC3-1 I/O 21 21 MC11-1 MC4-9 I/O/FI I/O MC11-2 MC4-8 I/O/FI I/O MC11-3 MC4-7 I/O/FI I/O MC11-4 MC4-6 I/O I/O MC11-5 MC4-5 I/O I/O MC11-6 MC4-4 I/O I/O/FI MC11-7 MC4-3 I/O I/O/FI MC11-8 MC4-2 I/O I/O/FI MC11-9 MC4-1 I/O 21 21 UIM 25 27 33 35 42 34 32 29 37 O MC10-1 MC5-9 I/O/FI O MC10-2 MC5-8 I/O/FI O/FCLK0 MC10-3 MC5-7 I/O/FI O/FCLK1 MC10-4 O/FCLK2 MC10-5 O MC10-6 I/O/FI MC10-7 I/O/FI I/O/FI 21 21 R9 R10 P9 M14 N15 N10 R12 P12 P13 62 63 64 86 88 68 71 73 75 O/FOE0 O/CKEN1 MC5-3 O/CKEN0 MC10-8 MC5-2 O MC10-9 MC5-1 O I/O MC9-1 MC6-9 I/O/FI I/O MC9-2 MC6-8 I/O/FI I/O MC9-3 MC6-7 I/O/FI I/O MC9-4 MC6-6 I/O I/O MC9-5 MC6-5 I/O I/O MC9-6 MC6-4 I/O I/O/FI MC9-7 MC6-3 I/O I/O/FI MC9-8 MC6-2 I/O I/O/FI MC9-9 MC6-1 I/O N12 P14 N14 M15 K14 J13 J15 H14 G13 77 79 82 90 92 95 97 98 101 21 21 K15 L15 K13 L14 L13 P15 N13 R14 N11 61 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 72 69 57 67 55 50 48 45 43 R13 R11 R7 P10 N7 P6 R4 N5 R2 48 45 36 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16 14 12 8 6 2 159 9 7 F1 G2 F2 C1 D2 C2 B2 E2 E3 -- -- 9 6 5 3 1 -- -- -- -- -- 77 76 75 74 -- -- 140 139 138 135 113 115 136 134 126 C8 A8 B8 C9 C14 D13 A10 B9 A13 89 88 87 84 73 74 85 83 80 63 62 61 58 51 52 59 57 56 124 122 117 111 108 106 104 103 102 B12 B13 B14 D14 E14 F13 G14 F15 G15 79 78 76 72 70 69 68 67 66 55 54 53 50 48 47 46 45 44 FB7 I/O MC8-1 MC7-9 I/O/FI I/O MC8-2 MC7-8 I/O/FI I/O MC8-3 MC7-7 I/O/FI I/O MC8-4 MC7-6 I/O I/O MC8-5 MC7-5 I/O I/O MC8-6 MC7-4 I/O I/O/FI MC8-7 MC7-3 I/O I/O/FI MC8-8 MC7-2 I/O I/O/FI MC8-9 MC7-1 I/O AND ARRAY 51 52 54 57 58 60 62 63 65 96 93 91 89 87 84 78 76 74 FB6 FB8 31 32 33 36 37 39 40 41 43 O/FOE1 MC5-4 AND ARRAY 41 42 43 55 56 44 47 49 50 MC5-6 MC5-5 FB9 23 24 25 34 35 26 28 29 30 65 66 67 68 69 70 71 72 -- FB5 AND ARRAY K2 L1 N2 M3 P3 P1 L3 M1 P2 AND ARRAY -- -- 24 25 29 -- -- 21 27 AND ARRAY I/O FB10 -- -- 9 10 12 -- -- -- 11 91 92 93 95 96 97 98 99 4 FB4 AND ARRAY 130 147 151 153 155 158 129 133 145 AND ARRAY MC3-9 MC12-2 AND ARRAY MC12-1 I/O 21 21 Serial Shift AND ARRAY B10 A5 A4 B4 B3 C3 C10 A11 B6 A7 A6 B7 C6 B5 A3 C5 A2 B1 FB3 I/O AND ARRAY -- -- -- -- -- -- 81 82 94 142 143 144 146 148 152 154 156 4 45 Carry FB11 -- -- -- -- -- -- -- -- -- 2 3 4 5 6 7 39 Arithmetic FB12 105 107 109 112 114 123 125 128 116 16 17 18 19 20 22 9 45 F14 E15 D15 E13 B15 A14 C11 A12 C13 J1 K1 J2 K3 L2 N1 FFB2 39 -- -- -- -- -- -- -- -- 75 22 23 24 26 28 30 12 9 -- -- -- -- -- -- -- -- -- PC84 6 12 FFB1 MC1-1 BG225/ PG144 PQ100 X5454 Arithmetic Carry Figure 2: XC73108 Architecture 3- 116 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO 50 Units V V V V V V V ns Max Units DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins CIN Input capacitance for global control pins (FCLK0, FCLK1, FCLK2, FOE0, FOE1) COUT1 ICC2 Output capacitance Supply current (low power mode) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA (FO) IOL = 12 mA (I/O) VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Min 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 8.0 pF 12.0 pF 20.0 pF 227 Typ mA Notes: 1. Sample tested. 2. Measured with device programmed as six 16-bit counters. June 1, 1996 (Version 1.0) 3- 117 XC73108 108-Macrocell CMOS CPLD Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ Max 80 160 Units ns s Fast Function Block (FFB) External AC Characteristics3 Symbol fCF tSUF tHF tCOF tPDFO tPDFU tCWF Parameter Max count frequency 1, 2, 4 Fast input setup time before FCLK Fast input hold time after FCLK FCLK to output valid Fast input to output valid 1, 2 I/O to output valid 1, 2 Fast clock pulse width (High or Low) 1 XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min 125.0 4.0 0 Max Min 100.0 5.0 0 5.5 7.5 13.5 4.0 Max Min 80.0 6.0 0 8.0 10.0 19.0 5.0 Max 9.0 12.0 22.0 5.5 XC73108-15 Min Max 66.7 7.0 0 12.0 15.0 27.0 6.0 XC73108-20 Min Max 50.0 10.0 0 15.0 20.0 35.0 6.0 Units MHz ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3. All appropriate AC specifications tested using Figure 3 as the test load circuit. 4. Export Control Max. flip-flop toggle rate. High-Density Function Block (FB) External AC Characteristics Symbol fC tSU tH tCO tPSU tPH tPCO tPD tCW tPCW Parameter Max count frequency 1, 2 I/O setup time before FCLK 1, 2 I/O hold time after FCLK FCLK to output valid I/O setup time before p-term clock 2 I/O hold time after p-term clock P-term clock to output valid I/O to output valid 1, 2 Fast clock pulse width P-term clock pulse width XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min 83.3 12.0 0 Max Min 62.5 16.0 0 7.0 4.0 0 Min 55.6 18.0 0 10.0 6.0 0 15.0 18.0 4.0 5.0 Max 12.0 7.0 0 20.0 25.0 5.0 6.0 Max 23.0 30.0 5.5 7.5 XC73108-15 Min Max 45.5 22.0 0 15.0 9.0 0 28.0 36.0 6.0 8.5 XC73108-20 Min Max 35.7 28.0 0 20.0 12.0 0 36.0 45.0 6.0 12.0 Units MHz ns ns ns ns ns ns ns ns ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3- 118 June 1, 1996 (Version 1.0) Fast Function Block (FFB) Internal AC Characteristics Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min Max 1.5 3.5 1.5 2.5 Min Max 1.5 5.5 2.5 2.5 1.0 0.5 2.0 0.8 4.0 Min Max 2.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 1.0 1.0 3.0 1.2 6.5 XC73108-15 Min Max 2.0 8.0 4.0 3.0 1.0 1.0 4.0 1.5 8.0 XC73108-20 Min Max 3.0 11.0 6.0 4.0 1.0 2.0 6.0 2.0 10.0 Units ns ns ns ns ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. High-Density Function Block (FB) Internal AC Characteristics Symbol Parameter tLOGI FB logic array delay 1 Low power FB logic delay 1 FB register setup time FB register hold time FB register clock-to-output delay FB register pass through delay FB register async. set/reset delay Set/reset recovery time before FCLK Set/reset hold time after FCLK Set/reset recovery time before p-term clock Set/reset hold time after p-term clock FB p-term clock delay FB p-term output enable delay ALU carry delay within 1 FB 2 Carry lookahead delay per additional Functional Block 2 tLOGILP tSUI tHI tCOI tPDI tAOI tRA tHA tPRA tPHA tPCI tOEI tCARY8 tCARYFB XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min Max 3.5 7.0 1.5 3.5 Min Max 3.5 7.5 2.5 3.5 1.0 1.5 2.5 15.0 0 7.5 1.0 2.5 3.0 1.0 4.0 4.0 21.0 0 12.0 6.0 1.0 3.0 5.0 1.0 Max 4.0 9.0 3.0 4.0 19.0 0 10.0 5.0 Min 8.0 0 4.0 6.0 1.5 XC73108-15 Min Max 5.0 11.0 4.0 5.0 1.0 4.0 5.0 25.0 0 15.0 9.0 0 5.0 8.0 2.0 XC73108-20 Min Max 6.0 14.0 6.0 6.0 1.0 4.0 7.0 31.0 0 20.0 12.0 0 7.0 12.0 3.0 0 9.0 15.0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with registered outputs. June 1, 1996 (Version 1.0) 3- 119 XC73108 108-Macrocell CMOS CPLD I/O Block External AC Characteristics Symbol Parameter fIN Max pipeline frequency (input register to FFB or FB register) 1 tSUIN Input register/latch setup time before FCLK Input register/latch hold time after tHIN FCLK tCOIN FCLK to input register/latch output tCESUIN Clock enable setup time before FCLK tCEHIN Clock enable hold time after FCLK tCWHIN FCLK pulse width high time tCWLIN FCLK pulse width low time XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min 83.3 Max Min 62.5 Max Min 55.6 XC73108-15 Min Max 45.5 Max XC73108-20 Min Max 35.7 Units MHz 4.0 5.0 6.0 7.0 10.0 ns 0 0 0 0 0 ns 2.5 3.5 5.0 0 4.0 4.0 7.0 0 5.0 5.0 4.0 5.0 8.0 0 5.5 5.5 10.0 0 6.0 6.0 6.0 12.0 0 6.0 6.0 ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. Internal AC Characteristics Symbol tIN tFOUT tOUT tUIM tFOE tFOD tFCLKI Parameter XC73108-7 XC73108-10 XC73108-12 (Com only) (Com only) (Com/Ind only) Min Input pad and buffer delay FFB output buffer and pad delay FB output buffer and pad delay Universal Interconnect Matrix delay FOE input to output valid FOE input to output disable Fast clock buffer delay Max 2.5 3.0 4.5 6.0 7.5 7.5 1.5 Min Max 3.5 4.5 6.5 9.0 10.0 10.0 2.5 Min XC73108-15 Min Max 5.0 7.0 10.0 12.0 15.0 15.0 4.0 Max 4.0 5.0 8.0 10.0 12.0 12.0 3.0 XC73108-20 Min Max 6.0 9.0 14.0 15.0 20.0 20.0 5.0 Units ns ns ns ns ns ns ns VTEST R1 Device Output Test Point R2 CL Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL FO 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X3491 Figure 3: AC Load Circuit 3- 120 June 1, 1996 (Version 1.0) XC73108 Pinouts PQ160 PG144 BG225 PQ100 PC84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D3 C2 - B1 - D2 E3 C1 E2 D1 F3 F2 E1 G2 G3 F1 G1 H2 H1 H3 J3 J1 K1 J2 K2 K3 L1 L2 M1 N1 M2 L3 N2 P1 M3 N3 P2 - - R1 - 3 - 4 - 5 - 6 - 7 8 9 10 - 11 - 12 13 14 - 15 16 17 18 - 19 - 20 21 22 23 - 24 - 25 26 27 - - - - 75 - - - 76 - 77 - 78 79 - 80 - 81 - 82 83 84 - 1 2 3 4 - 5 6 - 7 8 - 9 - 10 - 11 - - - Input XC73108 Output VCCIO O/CKEN1 MC5-4 N/C FO MC2-1 N/C O/FOE0 O O/FOE1 O MC5-5 MC5-1 MC5-6 MC5-2 VCCINT/VPP I/FI I/O/FI I/FI I/O/FI I/FI I/O/FI I/FI I/FI I/FI MC5-7 MC5-8 MC5-9 GND MR I/FI I/FI I/FI O I/FI O I/FI I/O/FI I/FI MC10-1 MC10-2 MC10-8 GND I/O/FI O/FCLK0 O O/FCLK1 FO I/O/FI MC10-7 MC10-3 MC10-6 MC10-4 MC1-1 MC10-9 N/C N/C GND PQ160 PG144 BG225 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 N4 P3 R2 P4 N5 R3 P5 R4 N6 P6 R5 - - P7 N7 R6 R7 P8 R8 N8 N9 R9 R10 P9 - - P10 N10 R11 P11 R12 R13 P12 N11 P13 R14 N12 N13 P14 R15 PQ100 PC84 28 29 - 30 - - 31 - 32 - 33 - - 34 - 35 36 37 38 39 40 41 42 43 - - - 44 45 46 47 48 49 - 12 - 13 - - 14 - 15 - 16 - - 17 - 18 - 19 20 21 22 23 24 25 - - - 26 - 27 28 - 29 - 30 - 31 - 32 - 50 - 51 - 52 - Input XC73108 Output VCCIO O/FCLK2 I/O FO I/O MC10-5 MC4-1 MC1-2 MC4-2 VCCINT FO I/O FO I/O MC1-3 MC4-3 MC1-4 MC4-4 GND N/C N/C FO I/O FO I/O/FI FO FO FO MC1-5 MC4-5 MC1-6 MC4-7 MC1-7 MC1-8 MC1-9 VCCIO I/O I/O I/O MC9-1 MC9-2 MC9-3 N/C N/C I/O I/O I/O/FI MC4-6 MC9-6 MC4-8 GND I/O/FI I/O/FI I/O/FI I/O I/O/FI I/O I/O I/O I/O MC9-7 MC4-9 MC9-8 MC3-1 MC9-9 MC3-2 MC8-1 MC3-3 MC8-2 GND Note: With the XC73108 in the 225-pin ball grid array package, only 144 of the solder balls are connected, the remaining solder balls should be left unconnected. June 1, 1996 (Version 1.0) 3- 121 XC73108 108-Macrocell CMOS CPLD XC73108 Pinouts (continued) PQ160 PG144 BG225 PQ100 PC84 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 M13 N14 - P15 - M14 L13 N15 L14 M15 K13 K14 L15 J14 J13 K15 J15 H14 H15 H13 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 E13 C14 B15 D13 C13 B14 - - A15 53 54 - - - 55 - 56 - 57 - 58 - 59 60 61 62 63 - 64 65 66 67 68 - 69 - 70 - 71 72 - 73 - 74 75 76 - - 77 - 33 - - - 34 - 35 - 36 - 37 - 38 39 - 40 41 - 42 43 44 45 46 - 47 - 48 - 49 50 - 51 - 52 - 53 - - - 3- 122 Input XC73108 Output VCCIO I/O MC8-3 N/C I/O MC3-4 N/C I/O I/O I/O I/O I/O I/O/FI I/O I/O/FI MC9-4 MC3-5 MC9-5 MC3-6 MC8-4 MC3-7 MC8-5 MC3-8 VCCINT I/O I/O/FI I/O/FI I/O/FI MC8-6 MC3-9 MC8-7 MC8-8 GND GND I/O/FI I/O I/O I/O I/O I/O I/O I/O I/O MC8-9 MC7-1 MC7-2 MC7-3 MC12-1 MC7-4 MC12-2 MC7-5 MC12-3 GND I/O I/O I/O I/O I/O I/O/FI I/O/FI MC7-6 MC12-4 MC6-5 MC12-5 MC6-4 MC12-9 MC7-7 N/C N/C GND PQ160 PG144 BG225 PQ100 PC84 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 C12 B13 A14 B12 C11 A13 B11 A12 C10 B10 - - A11 B9 C9 A10 A9 B8 A8 C8 C7 A7 A6 B7 B6 C6 A5 B5 - - A4 A3 B4 C5 B3 A2 C4 C3 B2 A1 - 78 - 79 - 80 - - 81 - - - 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 96 - - - 97 - 98 - 99 100 - 1 2 - 54 - 55 - 56 - - - - - - - 57 58 59 60 61 62 63 64 65 66 67 - 68 - 69 - - - 70 - 71 - 72 73 - 74 - Input XC73108 Output VCCIO I/O/FI I/O I/O/FI I/O/FI I/O MC7-8 MC12-6 MC7-9 MC12-7 MC6-1 GND I/O/FI I/O/FI I/O MC12-8 MC11-7 MC11-1 N/C N/C I/O/FI I/O I/O I/O MC11-8 MC6-2 MC6-6 MC6-3 GND I/O/FI I/O/FI I/O/FI MC6-7 MC6-8 MC6-9 VCCIO FO FO FO I/O/FI FO I/O FO MC2-9 MC2-8 MC2-7 MC11-9 MC2-6 MC11-2 MC2-5 N/C N/C I/O FO I/O FO I/O FO MC11-3 MC2-4 MC11-4 MC2-3 MC11-5 MC2-2 VCCINT I/O O/CKEN0 MC11-6 MC5-3 GND June 1, 1996 (Version 1.0) Ordering Information XC73108 - 7 PC 84 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -20 -15 -12 -10 -7 20 ns pin-to-pin delay 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay (commercial and industrial only) 7.5 ns pin-to-pin delay (commercial only) Packaging Options PC84 84-Pin Plastic Leaded Chip Carrier WC84 84-Pin Windowed Ceramic Leaded Chip Carrier PQ100 100-Pin Plastic Quad Flat Pack PG144 144-Pin Windowed Pin-Grid-Array PQ160 160-Pin Plastic Quad Flat Pack BG225 225-Pin Plastic Ball-Grid-Array Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case) Component Availability Pins 84 Type Code XC73108 -20 -15 -12 -10 -7 Plastic PLCC PC84 CI CI CI C C C = Commercial = 0 to +70C June 1, 1996 (Version 1.0) Ceramic CLCC WC84 CI CI CI C C 100 Plastic PQFP PQ100 CI CI CI C C I = Industrial = -40 to 85C 144 Ceramic PGA PG144 CIM CIM CI C C 160 Plastic PQFP PQ160 CI CI CI C C 225 Plastic BGA BG225 CI CI CI C C M = Military = -55C(A) to 125C (C) 3- 123 XC73108 108-Macrocell CMOS CPLD 3- 124 June 1, 1996 (Version 1.0) XC73144 144-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. * * * * * * * * * * * * * * * * High-performance Complex Programmable Logic Devices (CPLDs) - 7.5 ns pin-to-pin speeds on all fast inputs - Up to 100 MHz maximum clock frequency 100% PCI compliant 18 outputs with 24 mA drive I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 43 MHz 16-bit accumulators Multiple independent clocks Up to 132 inputs programmable as direct, latched, or registered Power management options Multiple security bits for design protection 144 macrocells with programmable I/O architecture Advanced Dual-Block architecture - 4 Fast Function Blocks - 12 High-Density Function Blocks Programmable slew rate Programmable ground control 0.8 CMOS EPROM technology Available in 84-pin and 84-pin PLCC/CLCC, 144-pin PGA, 100-pin and 160-pin PQFP, and 225 BGA packages Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA)=MCHP (2.4) + MCLP (2.1) + MC (0.015 mA/MHz) f Where: MCHP MCLP MC f = = = = Macrocells in high-performance mode Macrocells in low-power mode Total number of macrocells used Clock frequency (MHz) Figure 1 shows a typical power calculation for the XC73144 device, programmed as eight 16-bit counters and operating at the indicated clock frequency. 500 400 Typical ICC (mA) * 300 nce rma erfo P High er Low Pow 200 100 General Description The XC73144 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like 24V9 Fast Function Blocks and twelve High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIMTM). 0 50 Clock Frequency (MHz) 100 X5768 Figure 1: Typical ICC vs. Frequency for XC73144 Power Management The XC73144 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral June 1, 1996 (Version 1.0) 3- 125 XC73144 144-Macrocell CMOS CPLD BG225 19 18 17 15 13 11 H1 H2 G1 G3 E1 F3 I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI 6 12 12 FFB1 N3 P4 P5 N6 P7 R6 P8 R8 N8 I/FO MC1-1 I/FO MC1-2 I/FO MC1-3 I/FO MC1-4 I/FO MC1-5 I/FO MC1-6 I/FO MC1-7 I/FO I/FO I/FO MC2-8 I/FO MC2-7 I/FO MC2-6 I/FO MC2-5 I/FO MC2-4 I/FO MC2-3 I/FO MC1-8 MC2-2 I/FO MC1-9 MC2-1 I/FO 12 12 3 3 9 9 9 I/FO MC3-7 I/FO MC3-6 I/FO MC3-5 I/FO MC3-4 I/FO MC3-3 I/FO MC4-8 MC3-2 I/FO MC4-9 MC3-1 I/FO MC4-2 I/FO MC4-3 I/FO MC4-4 I/FO MC4-5 I/FO MC4-6 I/FO MC4-7 I/FO I/FO 12 12 3 3 9 9 AND ARRAY I/FO MC3-8 MC4-1 I/FO 9 18 54 Arithmetic Shift I/O/FI MC5-8 I/O/FI I/O MC16-3 MC5-7 I/O/FI I/O MC16-4 MC5-6 I/O I/O MC16-5 MC5-5 I/O I/O MC16-6 MC5-4 I/O I/O/FI MC16-7 MC5-3 I/O I/O/FI MC16-8 MC5-2 I/O I/O/FI MC16-9 MC5-1 I/O 21 21 MC15-1 MC6-9 I/O/FI I/O MC15-2 MC6-8 I/O/FI I/O MC15-3 MC6-7 I/O/FI I/O MC15-4 MC6-6 I/O I/O MC15-5 MC6-5 I/O MC6-4 I/O MC6-3 I/O I/O 21 21 I/O MC15-6 I/O/FI MC15-7 I/O/FI MC15-8 MC6-2 I/O/FI MC15-9 MC6-1 I/O UIM O MC14-1 MC7-9 I/O/FI MC14-2 MC7-8 I/O/FI MC14-3 MC7-7 I/O/FI O/FCLK1 MC14-4 O/FCLK2 MC14-5 O MC14-6 I/O/FI MC14-7 I/O/FI MC14-8 I/O/FI MC14-9 21 21 O/FOE0 O/CKEN1 MC7-3 O/CKEN0 MC7-2 O MC7-1 O O MC13-1 MC8-9 I/O/FI O MC13-2 MC8-8 I/O/FI O MC13-3 MC8-7 I/O/FI O MC13-4 MC8-6 O O MC13-5 MC8-5 O MC8-4 O MC8-3 O AND ARRAY 21 21 O MC13-6 I/O/FI MC13-7 I/O/FI MC13-8 MC8-2 O I/O/FI MC13-9 MC8-1 O 72 69 57 67 55 50 48 45 43 F1 G2 F2 C1 D2 C2 B2 E2 E3 16 14 12 8 6 2 159 9 7 D7 D9 D12 E11 D10 E10 G12 F12 132 131 119 118 - - - - - C8 A8 B8 C9 C14 D13 A10 B9 A13 140 139 138 135 113 115 136 134 126 B12 B13 B14 D14 E14 F13 G14 F15 G15 124 122 117 111 108 106 104 103 102 FB9 MC12-1 MC9-9 I/O/FI I/O MC12-2 MC9-8 I/O/FI I/O MC12-3 MC9-7 I/O/FI I/O MC12-4 MC9-6 I/O I/O MC12-5 MC9-5 I/O I/O MC12-6 MC9-4 I/O I/O/FI MC12-7 MC9-3 I/O I/O/FI MC12-8 MC9-2 I/O I/O/FI MC12-9 MC9-1 I/O 21 21 AND ARRAY I/O FB10 MC11-1 MC10-9 I/O/FI I/O MC11-2 MC10-8 I/O/FI I/O MC11-3 MC10-7 I/O/FI I/O MC11-4 MC10-6 I/O I/O MC11-5 MC10-5 I/O I/O MC11-6 MC10-4 I/O I/O/FI MC11-7 MC10-3 I/O I/O/FI MC11-8 MC10-2 I/O I/O/FI MC11-9 MC10-1 I/O 21 21 AND ARRAY I/O AND ARRAY N12 P14 N14 M15 K14 J13 J15 H14 G13 R13 R11 R7 P10 N7 P6 R4 N5 R2 FB8 FB11 77 79 82 90 92 95 97 98 101 O/FOE1 MC7-4 AND ARRAY K9 R10 P9 M14 N15 N10 R12 P12 P13 MC7-6 MC7-5 FB12 62 63 64 86 88 68 71 73 75 AND ARRAY O O/FCLK0 AND ARRAY M10 L10 L12 K12 K11 L11 M11 J12 G12 96 93 91 89 87 84 78 76 74 FB7 FB13 - - - - - 65 66 83 85 AND ARRAY I/O AND ARRAY K2 L1 N2 M3 P3 P1 L3 M1 P2 K15 L15 K13 L14 L13 P15 N13 R14 N11 FB6 FB14 25 27 33 35 42 34 32 29 37 AND ARRAY MC5-9 MC16-2 AND ARRAY B10 A5 A4 B4 B3 C3 C10 A11 B6 149 - 150 - 3 - 5 - - FB5 MC16-1 I/O FB15 130 147 151 153 155 158 129 133 145 D5 D6 E5 E6 G4 E4 J4 F4 F5 42 I/O AND ARRAY F14 E15 D15 E13 B15 A14 C11 A12 C13 142 143 144 146 148 152 154 156 4 54 Carry Serial FB16 105 107 109 112 114 123 125 128 116 A7 A6 B7 C6 B5 A3 C5 A2 B1 9 18 42 22 23 24 26 28 30 FFB3 MC3-9 I/FO AND ARRAY N9 L4 M7 M5 L5 L6 M4 M6 M9 J1 K1 J2 K3 L2 N1 9 FFB4 53 - 52 - 39 - 38 - - PQ160 FFB2 MC2-9 AND ARRAY 36 44 47 49 54 56 58 59 60 BG225 6 12 AND ARRAY PQ160 Serial Shift Arithmetic Carry X5653 Figure 2: XC73144 Architecture 3- 126 June 1, 1996 (Version 1.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO 50 Units V V V V V V V ns Max Units DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins CIN Input capacitance for global control pins (FCLK0, FCLK1, FCLK2, FOE0, FOE1) COUT1 ICC2 Output capacitance Supply current (low power mode) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Min 2.4 V 2.4 V 0.5 V 0.4 V 10.0 A 10.0 A 8.0 pF 12.0 pF 10.0 pF 250 Typ mA Notes: 1. Sample tested. 2. Measured with device programmed as eight 16-bit counters. June 1, 1996 (Version 1.0) 3- 127 XC73144 144-Macrocell CMOS CPLD Power-up/Reset Timing Parameters Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ Max 80 160 Units ns s Slew Rate and Programmable Ground Control Due to the large number of high current drivers available on the XC73144, two programmable signal management features have been included - slew rate control (SRC) and ground control (GC). Slew rate control is primarily for external system benefit, to reduce ringing and other coupling phenomenon. SRC permits designers to select either 1 V/ns or 1.5 V/ns slew rate on a pin-by-pin basis for any output or I/O signal. This can be done with PLUSASM or schematically, as needed. The default slew rate is 1 V/ns. To assign the pins with equations (PLUSASM), the designer needs to only declare them as follows: FAST ON This will assign the signals in the list to have a 1.5 V/ns slew rate. Omitting the signal name list will globally set all signals to be 1.5 V/ns. Specific signals therefore can be declared with 1 V/ns slew rate as follows: FAST OFF Schematic control of SRC is also straightforward. Again, the default is 1 V/ns, but to assign specific pins fast, the designer need only attach the "FAST" attribute to the I/O or output buffer or the corresponding pin. Programmable ground control is useful for internal chip signal management. The output buffers of the Fast Function Blocks have an impedance of approximately 7 when switching high to low, where the High Density Function Blocks impedance is around 14 . Since this low impedance is negligible compared to the impedance of the pin inductance when output current transients occur, a reasonable ground connection can be made by driving unused output pins low and physically attaching them to external ground. The XC73144 architecture permits the automatic assignment of external ground signals to all macrocells that are not declared as primary outputs or I/Os. Note that the logical function of the buried macrocell is fully preserved, while its output driver is driving low and physically attached to ground. Should designers not wish to employ programmable ground control, they need only declare all such pins as primary I/Os whether they will be attached externally or not. Fast Function Block (FFB) External AC Characteristics3 Symbol fCF tSUF tHF tCOF tPDFO tPDFU tCWF Parameter Max count frequency 1, 2, 4 Fast input setup time before FCLK 1 Fast input hold time after FCLK FCLK to output valid Fast input to output valid 1, 2 I/O to output valid 1, 2 Fast clock pulse width (High or Low) XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min 105.0 4.0 0 Max Min 100.0 5.0 0 5.5 7.5 13.5 4.0 Max Min 80.0 6.0 0 7.0 9.0 17.0 5.0 Max 9.0 12.0 22.0 5.5 XC73144-15 Min Max Units 66.7 MHz 7.0 ns 0 ns 12.0 ns 15.0 ns 27.0 ns 6.0 ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3. All appropriate AC specifications tested using Figure 3 as the test load circuit. 4. Export Control Max. flip-flop toggle rate. 3- 128 June 1, 1996 (Version 1.0) High-Density Function Block (FB) External AC Characteristics Symbol fC tSU tH tCO tPSU tPH tPCO tPD tCW tPCW Parameter Max count frequency 1, 2 I/O setup time before FCLK 1, 2 I/O hold time after FCLK FCLK to output valid I/O setup time before p-term clock 2 I/O hold time after p-term clock P-term clock to output valid I/O to output valid 1, 2 Fast clock pulse width P-term clock pulse width XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min 83.3 12.0 0 Max Min 62.5 13.5 0 7.0 4.0 0 Max 9.0 6.0 0 15.0 18.0 4.0 5.0 Min 55.6 18.0 0 Max 12.0 7.0 0 19.0 22.0 5.0 6.0 23.0 30.0 5.5 7.5 XC73144-15 Min Max Units 45.5 MHz 22.0 ns 0 ns 15.0 ns 9.0 ns 0 ns 28.0 ns 36.0 ns 6.0 ns 8.5 ns Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. Fast Function Block (FFB) Internal AC Characteristics XC73144-7 XC73144-10 Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay (Com Only) (Com Only) Min Min Max 1.5 3.5 1.5 2.5 Max 1.5 5.5 2.5 2.5 1.0 0.5 2.0 0.8 4.0 XC73144-12 (Com/Ind Only) Min Max 2.0 7.0 3.0 3.0 1.0 0.5 2.5 1.0 5.0 1.0 1.0 3.0 1.2 6.5 XC73144-15 Min Max Units 2.0 ns 8.0 ns 4.0 ns 3.0 ns 1.0 ns 1.0 ns 4.0 ns 1.5 ns 8.0 ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. June 1, 1996 (Version 1.0) 3- 129 XC73144 144-Macrocell CMOS CPLD High-Density Function Block (FB) Internal AC Characteristics XC73144-7 XC73144-10 (Com Only) Symbol tLOGI tLOGILP tSUI tHI tCOI tPDI tAOI tRA tHA tPRA tPHA tPCI tOEI tCARY8 tCARYFB Min Parameter FB logic array delay 1 Low power FB logic delay 1 FB register setup time 1.5 FB register hold time 3.5 FB register clock-to-output delay FB register pass through delay FB register async. set/reset delay Set/reset recovery time before FCLK 15.0 Set/reset hold time after FCLK 0 Set/reset recovery time before p-term clock 7.5 Set/reset hold time after p-term clock 5.0 FB p-term clock delay FB p-term output enable delay ALU carry delay within 1 FB 2 Carry lookahead delay per additional Functional Block 2 Max 3.5 7.0 (Com Only) Min Max 3.5 7.5 2.5 3.5 1.0 1.5 2.5 XC73144-12 (Com/Ind Only) Min 3.0 4.0 1.0 2.5 3.0 19.0 0 10.0 6.0 1.0 3.0 5.0 1.0 Max 4.0 9.0 1.0 4.0 4.0 21.0 0 12.0 8.0 0 4.0 6.0 1.5 0 5.0 8.0 2.0 XC73144-15 Min Max Units 5.0 ns 11.0 ns 4.0 ns 5.0 ns 1.0 ns 4.0 ns 5.0 ns 25.0 ns 0 ns 15.0 ns 9.0 ns 0 ns 7.0 ns 12.0 ns 3.0 ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with registered outputs. I/O Block External AC Characteristics XC73144-7 XC73144-10 Symbol Parameter fIN Max pipeline frequency (input register to FFB or FB register) 1 tSUIN Input register/latch setup time before FCLK tHIN Input register/latch hold time after FCLK tCOIN FCLK to input register/latch output tCESUIN Clock enable setup time before FCLK tCEHIN Clock enable hold time after FCLK tCWHIN FCLK pulse width high time tCWLIN FCLK pulse width low time XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min 83.3 Min 62.5 Min 55.6 Max 4.0 0 5.0 0 2.5 5.0 0 4.0 4.0 Max 6.0 0 3.5 7.0 0 5.0 5.0 Max XC73144-15 Min Max Units 45.5 MHz 7.0 0 4.0 8.0 0 5.5 5.5 5.0 10.0 0 6.0 6.0 ns ns ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell. 3- 130 June 1, 1996 (Version 1.0) Internal AC Characteristics XC73144-7 XC73144-10 Symbol tIN tFOUT tOUT tUIM tFOE tFOD tFCLKI Parameter Input pad and buffer delay FFB output buffer and pad delay FB output buffer and pad delay Universal Interconnect Matrix delay FOE input to output valid FOE input to output disable Fast clock buffer delay (Com Only) (Com Only) Min Min Max 2.5 3.0 4.5 6.0 7.5 7.5 1.5 Max 3.5 4.5 6.5 9.0 10.0 10.0 2.5 XC73144-12 (Com/Ind Only) Min Max 4.0 5.0 8.0 10.0 12.0 12.0 3.0 XC73144-15 Min Max Units 5.0 ns 7.0 ns 10.0 ns 12.0 ns 15.0 ns 15.0 ns 4.0 ns VTEST R1 Device Output Test Point R2 CL Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL FO 5.0 V 5.0 V 160 120 35 pF 3.3 V 3.3 V 260 360 35 pF X3491 Figure 3: AC Load Circuit June 1, 1996 (Version 1.0) 3- 131 XC73144 144-Macrocell CMOS CPLD XC73144 Pinouts BG225 PQ160 Input XC73144 D3 1 VCCIO E4 I/FO F4 I/FO C2 2 O/CKEN1 F5 I/FO G4 3 I/FO B1 4 I/FO J4 5 I/FO D2 6 O/FOE0 E3 7 O C1 8 O/FOE1 E2 9 O D1 10 VCCINT/VPP F3 11 I/FI F2 12 I/O/FI E1 13 I/FI G2 14 I/O/FI G3 15 I/FI F1 16 I/O/FI G1 17 I/FI H2 18 I/FI H1 19 I/FI H3 20 GND J3 21 I/FI MR K5 VCCIO J1 22 I/FI K1 23 I/FI J2 24 I/FI K2 25 O K3 26 I/FI L1 27 O L2 28 I/FI M1 29 I/O/FI N1 30 I/FI M2 31 GND L3 32 I/O/FI N2 33 O/FCLK0 P1 34 O M3 35 O/FCLK1 N3 36 I/FO K4 I/FO L4 I/FO P2 37 I/O/FI M4 38 I/FO L5 39 I/FO R1 40 GND 3- 132 Output MC3-4 MC3-2 MC7-4 MC3-1 MC3-5 MC2-1 MC3-3 MC7-5 MC7-1 MC7-6 MC7-2 MC7-7 MC7-8 MC7-9 MC14-1 MC14-2 MC14-8 MC14-7 MC14-3 MC14-6 MC14-4 MC1-1 MC4-1 MC4-2 MC14-9 MC4-3 MC4-5 BG225 PQ160 Input N4 41 P3 42 O/FCLK2 R2 43 I/O P4 44 I/FO N5 45 I/O R3 46 M5 I/FO P5 47 I/FO R4 48 I/O L6 I/FO M6 I/FO N6 49 I/FO P6 50 I/O R5 51 M7 52 I/FO M9 53 I/FO P7 54 I/FO N7 55 I/O R6 56 I/FO R7 57 I/O/FI P8 58 I/FO R8 59 I/FO N8 60 I/FO N9 61 M10 O L10 O R9 62 I/O R10 63 I/O P9 64 I/O L11 65 O M11 66 I/O/FI M12 P10 67 I/O N10 68 I/O R11 69 I/O/FI P11 70 R12 71 I/O/FI R13 72 I/O/FI P12 73 I/O/FI N11 74 I/O P13 75 I/O/FI R14 76 I/O N12 77 I/O N13 78 I/O P14 79 I/O R15 80 XC73144 VCCIO Output MC14-5 MC6-1 MC1-2 MC6-2 VCCINT MC4-4 MC1-3 MC6-3 MC4-6 MC4-8 MC1-4 MC6-4 GND MC4-7 MC4-9 MC1-5 MC6-5 MC1-6 MC6-7 MC1-7 MC1-8 MC1-9 VCCIO MC13-1 MC13-2 MC12-1 MC12-2 MC12-3 MC13-6 MC13-7 GND MC6-6 MC12-6 MC6-8 GND MC12-7 MC6-9 MC12-8 MC5-1 MC12-9 MC5-2 MC11-1 MC5-3 MC11-2 GND June 1, 1996 (Version 1.0) XC73144 Pinouts (continued) BG225 PQ160 M13 81 L12 K12 N14 82 K11 J12 83 P15 84 G12 85 M14 86 L13 87 N15 88 L14 89 M15 90 K13 91 K14 92 L15 93 J14 94 J13 95 K15 96 J15 97 H14 98 H15 99 H13 100 F11 G13 101 G15 102 F15 103 G14 104 F14 105 F13 106 E15 107 E14 108 D15 109 C15 110 D14 111 E13 112 C14 113 B15 114 D13 115 C13 116 F12 E12 B14 117 E11 118 D12 119 A15 120 Input XC73144 VCCIO O O I/O O I/O/FI I/O I/O/FI I/O I/O I/O I/O I/O I/O/FI I/O I/O/FI Output MC13-3 MC13-4 MC11-3 MC13-5 MC13-8 MC5-4 MC13-9 MC12-4 MC5-5 MC12-5 MC5-6 MC11-4 MC5-7 MC11-5 MC5-8 VCCINT I/O I/O/FI I/O/FI I/O/FI MC11-6 MC5-9 MC11-7 MC11-8 GND GND VCCINT I/O I/O I/O I/O I/O I/O I/O I/O I/O MC11-9 MC10-1 MC10-2 MC10-3 MC16-1 MC10-4 MC16-2 MC10-5 MC16-3 GND I/O I/O I/O I/O I/O I/OFI O O I/O/FI O I/O/FI June 1, 1996 (Version 1.0) MC10-6 MC16-4 MC9-5 MC16-5 MC9-4 MC16-9 MC8-1 MC8-2 MC10-7 MC8-6 MC8-7 GND BG225 PQ160 Input C12 121 B13 122 I/O/FI A14 123 I/O B12 124 I/O/FI C11 125 I/O/FI A13 126 I/O D11 O B11 127 A12 128 I/O/FI E10 O D10 O C10 129 I/O/FI B10 130 I/O D9 131 I/O/FI D7 132 I/O/FI A11 133 I/O/FI B9 134 I/O C9 135 I/O A10 136 I/O A9 137 B8 138 I/O/FI A8 139 I/O/FI C8 140 I/O/FI C7 141 A7 142 I/FO A6 143 I/FO B7 144 I/FO B6 145 I/O/FI C6 146 I/FO D6 I/FO E6 I/FO A5 147 I/O B5 148 I/FO D5 149 I/FO E5 150 I/FO A4 151 I/O A3 152 I/FO B4 153 I/O C5 154 I/FO D4 B3 155 I/O A2 156 I/FO C4 157 C3 158 I/O B2 159 O/CKEN0 A1 160 XC73144 VCCIO Output MC10-8 MC16-6 MC10-9 MC16-7 MC9-1 MC8-3 GND MC16-8 MC8-4 MC8-5 MC15-7 MC15-1 MC8-8 MC8-9 MC15-8 MC9-2 MC9-6 MC9-3 GND MC9-7 MC9-8 MC9-9 VCCIO MC2-9 MC2-8 MC2-7 MC15-9 MC2-6 MC3-8 MC3-6 MC15-2 MC2-5 MC3-9 MC3-7 MC15-3 MC2-4 MC15-4 MC2-3 GND MC15-5 MC2-2 VCCINT MC15-6 MC7-3 GND 3- 133 XC73144 144-Macrocell CMOS CPLD Ordering Information XC73144 - 7 PQ 160 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -15 -12 -10 -7 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay (commercial and industrial only) 7.5 ns pin-to-pin delay (commercial only) Packaging Options PQ160 160-Pin Plastic Quad Flat Pack BG225 225-Pin Plastic Ball-Grid-Array Temperature Options C Commercial 0C to 70C I Industrial -40C to 85C Component Availability Pins Type Code XC73144 -15 -12 -10 -7 C = Commercial = 0 to +70C 3- 134 160 Plastic PQFP PQ160 CI CI C C 225 Plastic BGA BG225 CI CI C C I = Industrial = -40 to 85C June 1, 1996 (Version 1.0) XC7300 Characterization Data June 1, 1996 (Version 1.0) Though this set of characterization data does not include explicit information on the XC7318, XC7336 and XC73144, all XC7300 products are designed using the same circuit configurations, design rules and process technology. Therefore, the XC7318, XC7336 and XC73144 timing parameters are also safely guardbanded with respect to their published data sheet limits. t CO vs Voltage XC7354-7 @ 25C 1 Output Switching 5 Time (ns) The following section includes typical characterization data for the XC7354, XC7372 and XC73108. Frequently consulted timing parameters were characterized under variations in temperature, voltage and number of simultaneously switching outputs. As demonstrated by the graphical data presented, all products are well within published data sheet limits for commercial temperature and voltage ranges. 4.75 4.5 4.25 4 4.75 V 5.00 V 5.25 V Voltage X7011 XC7354 t CO vs Temperature XC7354-7 @ 5 V 1 Output Switching t SU vs Voltage XC7354-7 @ 25C 6 Time(ns) Time (ns) 10 9 8 4 3 7 4.75 V 5.00 V Voltage 0 5.25 V 25 Temperature 70 X7012 X7009 t CO vs # Outputs Switching XC7354-7 @ 25C t SU vs Temperature XC7354-7 @ 5 V 6 11 Time(ns) 10 Time (ns) 5 9 5 8 4 7 0 25 Temperature June 1, 1996 (Version 1.0) 70 X7010 4 8 12 Outputs 16 20 X7013 3-135 XC7300 Characterization Data XC7354 (continued) t COF vs Voltage XC7354-7 @ 25C 1 Output Switching t RA vs Temperature XC7354-7 @ 5 V 1 Output Switching 4.75 12 Time(ns) 13 Time (ns) 5 4.5 4.25 11 10 9 4 4.75 V 8 5.00 V Voltage 5.25 V 0 X7014 70 X7018 t HA vs Voltage XC7354-7 @ 25C t COF vs Temperature XC7354-7 @ 5 V 1 Output Switching -7 6 25 Temperature Time (ns) Time (ns) -8 5 4 -9 -10 -11 -12 -13 3 -14 0 25 Temperature 70 4.75 V X7015 5.00 V Voltage 5.25 V X7019 t HA vs Temperature XC7354 @ 5 V 1 Output Switching t COF vs # Outputs Switching XC7354-7 @ 25C 6 -8 Time (ns) Time (ns) -9 5 -10 -11 -12 4 -13 4 8 12 Outputs 16 20 0 X7016 4.75 V 3-136 70 X7020 t PD vs Voltage XC7354-7 @25C 1 Output Switching 11 10.5 10 9.5 9 8.5 8 7.5 7 15 14 Time (ns) Time (ns) t RA vs Voltage XC7354-7 @ 25C 25 Temperature 13 12 11 5.00 V Voltage 5.25 V X7017 10 4.75 V 5.00 V Voltage 5.25 V X7021 June 1, 1996 (Version 1.0) XC7354 (continued) t PD vs Temperature XC7354-7 @5 V 1 Output Switching t PDFO vs # Outputs Switching XC7354-7 @25C 5 V 15 5 Time (ns) Time (ns) 14 13 12 4 11 3 10 0 25 Temperature 4 70 16 13 15 12 14 16 20 X7026 11 10 13 9 12 4 8 12 # Outputs 16 8 4.75 V 20 5.00 V Voltage X7023 t PDFO vs Voltage XC7354-7 @25C 1 Output Switching 5.25 V X7027 t PDFU vs Temperature XC7354-7 @5 V 1 Output Switching 11 5 10 Time (ns) 6 4 9 8 3 4.75 V 5.00 V Voltage 0 5.25 V 25 Temperature X7024 t PDFO vs Temperature XC7354-7 @5 V 1 Output Switching 70 X7028 t PDFU vs # Outputs Switching XC7354-7 @25C 5 V 5 10 4 Time (ns) Time (ns) 12 # Outputs t PDFU vs Voltage XC7354-7 @25C 1 Output Switching Time (ns) Time (ns) t PD vs # Outputs Switching XC7354-7 @25C 5 V Time (ns) 8 X7022 3 2 9 8 0 June 1, 1996 (Version 1.0) 25 Temperature 70 X7025 4 8 12 # Outputs 16 20 X7029 3-137 XC7300 Characterization Data XC7372 t SU vs Voltage XC7372-7 @ 25C t CO vs #Outputs Switching XC7372-7 @ 25C 7 Time (ns) Time (ns) 7 6 5 4.75 V 5.00 V Voltage 6 5 4 5.25 V 1 X7030 4 7 7 Time (ns) Time (ns) 8 6 5 5 4.75 V 70 5.00 V Voltage X7031 6 6 Time (ns) Time (ns) 7 5 X7035 5 4 4.75 V 5.25 V 5.00 V Voltage X7032 5.25 V X7036 t COF vs #Outputs Switching XC7372-7 @ 25C t CO vs Temperature XC7372-7 @ 5 V 1 Output Switching 7 7 6 6 Time (ns) Time (ns) 5.25V t COF vs Voltage XC7372-7 @25C 1 Output Switching 7 5.00 V Voltage 20 X7034 6 t CO vs Voltage XC7372-7 @25C 1 Output Switching 4 4.75 V 16 t SUF vs Voltage XC7372-15 @ 25C 8 25 Temperature 12 # Outputs t SU vs Temperature XC7372-7 @ 5 V 0 8 5 4 5 4 0 3-138 25 Temperature 70 X7033 1 4 8 12 # Outputs 16 20 X7037 June 1, 1996 (Version 1.0) XC7372 (continued) 12 17 11 16 Time (ns) Time (ns) t RA vs Voltage XC7372-7 @25C 10 9 t PD vs Voltage XC7372-7 @25C 1 Output Switching 15 14 13 8 7 4.75 V 5.00 V Voltage 12 4.75 5.25 V t RA vs Temperature XC7372-7 @ 5 V 1 Output 13 17 12 16 Time (ns) Time (ns) 5.00 Voltage X7038 11 10 t PD vs Temperature XC7372-7 @5 V 1 Output Switching 14 13 12 8 0 25 Temperature 0 70 25 Temperature 70 X7001 X7039 t HA vs Voltage XC7372-7 @25C -7 20 -8 19 -9 18 Time (ns) Time (ns) X7002 15 9 -10 -11 -12 t PD vs # Outputs XC7372-7 @25C 5V 17 16 15 -13 14 -14 4.75 V 5.00 V Voltage 4 5.25 V X7040 t HA vs Temperature XC7372-7 @ 5V 1 Output Switching 8 12 # Outputs 16 20 X7000 t PDFO vs Voltage XC7372-7 @25C 1 Output Switching -8 10 -9 9 Time (ns) Time (ns) 5.25 -10 -11 8 7 -12 6 -13 5 4.75 V 0 June 1, 1996 (Version 1.0) 25 Temperature 70 X7041 5.00 V Volts 5.25 V X7003 3-139 XC7300 Characterization Data XC7372 (continued) t PDFO vs Temperature XC7372-7 @5 V 1 Output Switching t PDFU vs Temperature XC7372-10 @5V 1 Output Switching 15 Time (ns) Time (ns) 14 7.04 6.02 13 12 11 10 -40 5 0 25 Temp 70 0 X7004 25 Temperature 70 80 X7007 t PDFU vs # Outputs XC7372-10 @25C 5V t PDFO vs # Outputs XC7372-7 @25C 5V 15 8 Time (ns) Time (ns) 14 7 6 13 12 11 10 5 4 8 12 # Outputs 16 20 X7005 4 8 12 # Outputs 16 20 X7008 t PDFU vs Voltage XC7372-10 @25C 1 Output Switching 15 Time (ns) 14 13 12 11 10 4.50 V 4.75 V 5.00 V Volts 3-140 5.25 V X7006 June 1, 1996 (Version 1.0) XC73108 t SU vs Voltage XC73108-7 @ 25C 5 Time (ns) Time (ns) 9 t CO vs #Outputs Switching XC73108-7 @ 25C 8 4 7 4.75 V 5.00 V Voltage 4 5.25 V X7042 t SU vs Temperature XC73108-7 @ 5 V Time (ns) 16 20 X7046 8 Time (ns) 9 8 0 25 Temperature 7 6 4.75 V 7 70 X7043 t CO vs Voltage XC73108-7 @25C 1 Output Switching 5.00 V Voltage 5.25 V X7047 t COF vs Voltage XC73108-7 @25C 1 Output Switching 4.25 4.25 4 Time (ns) 4.5 Time (ns) 12 # Outputs t SUF vs Voltage XC73108-7 @ 25C 10 4 3.75 3.5 3.75 3.25 3.5 4.75 V 5.00 V Voltage 4.75 V 5.25 V X7044 5.00 V Voltage 5.25 V X7048 t COF vs Temperature XC73108-7 @ 5 V 1 Output t CO vs Temperature XC73108-7 @ 5 V 1 Output Switching 6 5 5 Time (ns) Time (ns) 8 4 3 4 3 0 June 1, 1996 (Version 1.0) 25 Temperature 70 X7045 0 25 Temperature 70 X7049 3-141 XC7300 Characterization Data XC73108 (continued) t HA vs Temperature XC73108-7 @ 5 V 1 Output Switching t COF vs #Outputs Switching XC73108-7 @ 25C -9 5.5 Time (ns) Time (ns) -10 4.5 -11 -12 -13 3.5 -14 4 8 12 # Outputs 16 20 0 25 Temperature X7050 t RA vs Voltage XC73108-7 @25C 70 X7054 t PD vs Voltage XC73108-7 @25C 1 Output Switching 11.5 17 11 Time (ns) Time (ns) 10.5 10 9.5 9 16 15 14 8.5 8 4.75 V 5.00 V 5.25 V Voltage X7051 13 4.75 V t RA vs Temperature XC73108-7 @ 5 V 1 Output 17 Time (ns) 12 11 16 15 14 13 10 12 9 0 25 Temperature 0 70 25 Temperature X7052 t HA vs Voltage XC73108-7 @25C -8 18 -9 -10 17 -11 -12 -13 -14 16 15 -15 4.75 V 70 X7056 t PD vs # Outputs XC73108-7 @25C 5 V Time (ns) Time (ns) X7055 18 13 3-142 5.25 V t PD vs Temperature XC73108-7 @5 V 1 Output Switching 14 Time (ns) 5.00 V Voltage 14 5.00 V Voltage 5.25 V X7053 4 8 12 # Outputs 16 20 X7057 June 1, 1996 (Version 1.0) XC73108 (continued) t PDFU vs Voltage XC73108-7 @25C 1 Output Switching t PDFO vs Voltage XC73108-7 @25C 1 Output Switching 7 13 Time (ns) Time (ns) 12 6 5 11 10 9 4 4.75 V 5.00 V Voltage 8 4.75 V 5.25 V t PDFO vs Temperature XC73108-7 @5 V 1 Output Switching 7 13 6 12 5 4 X7061 11 10 3 9 0 25 Temperature 70 0 25 Temperature X7059 t PDFO vs # Outputs XC73108-7 @25C 5 V 70 X7062 t PDFU vs # Outputs Switching XC73108-7 @25C 5 V 13 Time (ns) 7 Time (ns) 5.25 V t PDFU vs Temperature XC73108-7 @5 V 1 Output Switching Time (ns) Time (ns) 5.00 V Voltage X7058 6 12 11 10 5 9 8 12 16 # Outputs June 1, 1996 (Version 1.0) 20 X7060 4 8 12 # Outputs 16 20 X7063 3-143 XC7300 Characterization Data 3-144 June 1, 1996 (Version 1.0) XC7200 Series Table of Contents XC7236A 36-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FBs and macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V or 5 V Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming and Using the XC7236A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147 3-147 3-147 3-148 3-149 3-150 3-150 3-150 3-151 3-152 3-152 3-152 3-153 3-154 3-154 3-155 3-156 3-156 3-161 3-162 3-162 XC7272A 72-Macrocell CMOS CPLD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Blocks and Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming and Using the XC7272A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163 3-163 3-163 3-165 3-166 3-167 3-167 3-167 3-168 3-168 3-168 3-169 3-170 3-170 3-171 3-172 3-172 3-177 3-178 3-178 3-145 XC7200 Series Table of Contents 3-146 XC7236A 36-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features This additional ALU in each macrocell can generate any combinatorial function of two sums of products, and it can generate and propagate arithmetic-carry signals between adjacent macrocells and FBs. * * * * * * * * * * * * Second-Generation High Density Programmable Logic Device UV-erasable CMOS EPROM technology 36 macrocells, grouped into four Function Blocks(FBs), interconnected by a programmable Universal Interconnect Matrix Each FB contains a programmable AND-array with 24 complementary inputs, providing up to 17 product terms per macrocell Enhanced logic features: - 2-input Arithmetic Logic Unit in each macrocell - Dedicated fast carry network between macrocells - Wide AND capability in the Universal Interconnect Matrix Identical timing for all interconnect paths and for all macrocell logic paths 36 signal pins - 30 I/Os, 2 inputs, 4 outputs Each input is programmable - Direct, latched, or registered I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V Three high-speed, low-skew global clock inputs Available in 44-pin PLCC and CLCC packages General Description The XC7236A combines the classical features of the PALlike CPLD architecture with innovative systems-oriented logic enhancements. This favors the implementation of fast state machines, large synchronous counters and fast arithmetic, as well as multi-level general-purpose logic. Performance, measured in achievable system clock rate and critical delays, is not only predictable, but independent of physical logic mapping, interconnect routing, and resource utilization. Performance, therefore, remains invariant between design iterations. The propagation delay through interconnect and logic is constant for any function implemented in any one of the output macrocells. The Universal Interconnect Matrix (UIM) facilitates unrestricted, fixed-delay interconnects from all device inputs and macrocell outputs to any FB AND-array input. The UIM can also perform a logical AND across any number of its incoming signals on the way to any FB, adding another level of logic without additional delay. This supports bidirectional loadable synchronous counters of any size up to 36 bits, operating at the specified maximum device frequency As a result of these logic enhancements, the XC7236A can deliver high performance even in designs that combine large numbers of product terms per output, or need more layers of logic than AND-OR, or need a wide AND function in some of the product terms, or perform wide arithmetic functions. Architectural Overview Figure 1 shows the XC7236A structure. Four Function Blocks(FBs) are all interconnected by a central UIM. Each FB receives 21 signals from the UIM and each FB produces nine signals back into the UIM. All device inputs are also routed via the UIM to all FBs. Each FB contains nine output macrocells that draw from a programmable AND array driven by the 21 signals from the UIM. Most macrocells drive a 3-state chip output. All feed back into the UIM. The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit (ALU) in each macrocell. Dedicated fast arithmetic carry lines running directly between adjacent macrocells and FBs support fast adders, subtractors and comparators of any length up to 36 bits. June 1, 1996 (Version 1.0) 3- 147 XC7236A 36-Macrocell CMOS CPLD 15 17 18 44 LCC 18 Arithmetic Carry Serial Shift FB2 FB3 MC2-1 MC3-9 I/O/FI I MC2-2 MC3-8 I/O/FI I MC2-3 MC3-7 I/O/FI I/O MC2-4 MC3-6 I/O MC3-5 I/O MC3-4 I/O MC3-3 I/O 21 21 AND ARRAY I/O AND ARRAY 2 3 4 5 6 8 9 10 11 44 LCC I/O MC2-5 I/O MC2-6 FCLK0/O MC2-7 FCLK1/O MC2-8 MC3-2 I/O FCLK2/O MC2-9 MC3-1 I/O 35 36 37 38 40 41 42 43 44 UIM FB1 FB4 MC1-1 MC4-9 I/O/FI I/O MC1-2 MC4-8 I/O/FI I/O MC1-3 MC4-7 I/O/FI I/O MC1-4 MC4-6 I/O MC4-5 I/O MC4-4 I/O I/O MC1-5 I/O MC1-6 I/O/FI MC1-7 I/O/FI MC1-8 I/O/FI MC1-9 21 21 AND ARRAY I/O AND ARRAY 13 14 15 16 18 19 20 21 22 MC4-3 I/O MC4-2 FOE/O MC4-1 I/O 24 25 26 27 28 30 31 32 33 Serial Shift Arithmetic Carry X3492 Figure 1: XC7236A Architecture FBs and macrocells The XC7236A contains 36 macrocells with identical structure, grouped into four FBs of nine macrocells each. Figure 2 shows the macrocell structure. Each macrocell is driven by product terms derived from a programmable AND array in the FB. The AND array in each FB receives 21 signals and their complements from the UIM. In three FBs, the AND array receives three additional inputs and their complements directly from FastInput (FI) pins, thus offering faster logic paths. Five product terms are private to each macrocell; an additional 12 product terms are shared among the nine macrocells in each FB. Four of the private product terms can be selectively ORed together with up to four of the shared product terms, and drive the D1 input to the ALU. The other input, D2, to the ALU is driven by the OR of the fifth private product term and up to eight of the remaining shared product terms. As a programmable option, four of the private product terms can be used for other purposes. One of the private product terms can be used as a dedicated clock for the flipflop in the macrocell. (See the subsequent description of other clocking options.) Another one of the private product terms can be the asynchronous active-High Reset of the macrocell flip-flop, another one can be the asynchronous active-High Set of the macrocell flip-flop, and another one can be the Output Enable signal. As a configuration option, the macrocell output can be fed back and ORed into the D2 input to the ALU after being 3- 148 ANDed with three of the shared product terms to implement counters and toggle flip-flops. The ALU has two programmable modes. In the logic mode, it is a 2-input function generator, a 4-bit look-up table, that can be programmed to generate any Boolean function of its two inputs. It can OR them, widening the OR function to 17 inputs; it can AND them, which means that one sum of products can be used to mask the other; it can XOR them, toggling the flip-flop or comparing the two sums of products. Either or both of the sum-of-product inputs to the ALU can be inverted and either or both can be ignored. The ALU can implement one additional layer of logic without any speed penalty. In the arithmetic mode, the ALU block in each macrocell can be programmed to generate the arithmetic sum or difference of two operands, combined with a carry signal coming from the next lower macrocell. It also feeds a carry output to the next higher macrocell. This carry propagation chain crosses the boundaries between FBs. This dedicated carry chain overcomes the inherent speed and density problems of the traditional CPLD architecture when trying to perform arithmetic functions. The ALU output drives the D input of the macrocell flip-flop. Each flip-flop has several programmable options. One option is to eliminate the flip-flop by making it transparent, which makes the Q output identical with the D input, independent of the clock. Otherwise, the flip-flop operates in the June 1, 1996 (Version 1.0) AND Array 21 Inputs from UIM 3 from Fast Input Pins (FI) Arithmetic Carry-In from Previous Macrocell 5 1 of 9 Macrocells CLOCK OE* SET RESET 12 Sharable 5 Private P-Terms per P-Terms per Function Block Macrocell Cin D1 4 F D2 C out Clock Select To 8 More Macrocells Shift-In from Previous MC Pin Input-Pad Register/Latch (optional) Register Trasparent Control Feedback Polarity Local Feedback * OE is forced high when P-term is not used I/O (see fig.3) R S D Q ALU Shift-Out to Next MC Global Fast OE OE Control MUX 8 Feedback Enable Override Fast Clocks 0 1 Arithmetic Carry-Out to Next Macrocell Feedback to UIM Input to UIM X1829 Figure 2: FB and macrocell Schematic conventional manner, triggered by the rising edge on its clock input. input pins. Acting as an unrestricted crossbar switch, the UIM generates 84 output signals, 21 to each FB. The clock source is programmable and is either the dedicated product term mentioned earlier, or one of two global FastCLK signals (FLCK0 or FLCK1) that are distributed with short delay and minimal skew over the whole chip. Any one of the 68 inputs can be programmed to be connected to any number of the 84 outputs. The delay through the array is constant, independent of the apparent routing distance, the fan-out, fan-in, or routing complexity. The asynchronous Set and Reset (Clear) inputs override the clocked operation. If both asynchronous inputs are active simultaneously, Reset overrides Set. Upon powerup, each macrocell flip-flop can be preloaded with either 0 or 1. Routability is not an issue in that any UIM input can drive any UIM output or multiple outputs without additional delay. In addition to driving a chip output pin, the macrocell output is also routed back as an input to the UIM. One private product term can be configured to control the Output Enable of the output pin driver and/or the feedback to the UIM. If configured to control UIM feedback, when the OE product-term is de-asserted, the UIM feedback line is forced High and thus disabled. Universal Interconnect Matrix The UIM receives 68 inputs: 36 from the macrocell feedbacks, 30 from bidirectional I/O pins, and 2 from dedicated June 1, 1996 (Version 1.0) When multiple inputs are programmed to be connected to the same output, this output becomes the AND of the input signals if the levels are interpreted as active High. By choosing the appropriate signal inversion at the input pin, macrocell outputs and FB AND-array input, this AND-logic can also be used to implement a NAND, OR, or NOR function. This offers an additional level of logic without any speed penalty. A macrocell feedback signal that is disabled by the output enable product term represents a High input to the UIM. Several such macrocell outputs programmed onto the same UIM output emulate a 3-state bus line. If one of the macrocell outputs is enabled, the UIM output assumes that same level. 3- 149 XC7236A 36-Macrocell CMOS CPLD Outputs Thirty-four of the 36 macrocell drive chip outputs directly through individually programmable inverters followed by 3state output buffers; each can be individually controlled by the Output Enable product term mentioned above. An additional configuration option disables the output permanently. One dedicated FastOE input also can be configured to control any of the chip outputs instead of, or in conjunction with, the individual OE product term. Inputs Each signal input to the chip is programmable as either direct, latched, or registered in a flip flop. The latch and flipflop can be programmed with either of two FastCLK signals as latch enable or clock. The two FastCLK signals are FCLK0 and a global choice of either FCLK1 or FCLK2. Latches are transparent when FastCLK is High, and flipflops clock on the rising edge of FastCLK. Registered inputs allow high system clock rates by pipelining the inputs before they incur the combinatorial delay in the device, provided the one-clock-period pipeline latency is acceptable. The direct, latched, or registered inputs then drive the UIM. There is no propagation-delay difference between pure inputs and I/O inputs. 3.3 V or 5 V Interface configuration The XC7236A can be used in systems with two different supply voltages, 5 V and 3.3 V. The device has separate VCC connections to the internal logic and input buffers (VCCINT) and to the I/O output drivers (VCCIO). VCCINT is always connected to a nominal +5 V supply, but VCCIO may be connected to either +5 V or +3.3 V, depending on the output interface requirement. When VCCIO is connected to +5 V, the input thresholds are TTL levels, and thus compatible with 5 V or 3.3 V logic, and the output high levels are compatible with 5 V systems. When VCCIO is connected to 3.3 V, the input thresholds are still TTL levels, and the outputs pull up to the 3.3 V rail. This makes the XC7236A ideal for interfacing directly to 3.3 V components. In addition, the output structure is designed such that the I/O can also safely interface to a mixed 3.3-V and 5-V bus. Global Fast OE Pin Macrocell MUX OE P-Term I/O. FCLK/O and FOE/O Pins Only Pin Driver From Macrocell Register I/O Pin Output Polarity MUX Feedback to UIM To UIM Input Polarity Q CLK Q To Function Block AND-Array (on Fast Input Pins Only) D D EN FastCLK0 FastCLK1 Input and I/O Pins Only FastCLK2 Global Select X5338 Figure 3: Input/Output Schematic 3- 150 June 1, 1996 (Version 1.0) Programming and Using the XC7236A The user can specify a security bit that prevents any reading of the programming bit map after the device has been programmed and verified. The device is programmed in a manner similar to an EPROM (ultra-violet light erasable read-only memory) using the Intel Hex format. Programming support is available from a number of programmer manufacturers. The UIM connections and FB AND-array connections are made directly by non-volatile EPROM cells. Other control bits are read out of the EPROM array and stored into latches just after power-up. This method, common among EPLD devices, requires application of a master-reset signal delayed at least until VCC has reached the required operating voltage. This can be achieved using a simple capacitor and pull-up resistor on the MR pin (the RC product should be larger than twice the VCC rise time). The power-up or reset signal initiates a self-timed configuration period lasting about 350 s (tRESET), during which all device outputs remain disabled and programmed preload state values are loaded into the macrocell registers. June 1, 1996 (Version 1.0) 150 Supply Current (mA) The features and capabilities described above are used by the Xilinx development software to program the device according to the specification given either through schematic entry, or through a behavioral description expressed in Boolean equations. TA = -55C TA = 25C TA = 125C 125 100 75 50 25 0 5 10 15 20 25 30 Frequency (MHz) 35 40 X3255 Figure 4: Typical ICC vs. Frequency for XC7236A configured as sixteen 4-bit counters (VCC = +5.0 V, VIN = VCC or GND, all outputs open) Unused input and I/O pins should be tied to ground or Vcc or some valid logic level. This is common practice for all CMOS devices to avoid dissipating excess current through the input pad circuitry. The recommended decoupling capacitance on the three VCC pins should total 1 F using high-speed (tantalum or ceramic) capacitors. 3- 151 XC7236A 36-Macrocell CMOS CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT/ VCCIO VCCIO VIL VIH VO Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C I/O supply voltage 3.3 V Low-level input voltage High-level input voltage Output voltage Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO Units V V V V V V V Max Units DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage ICC Supply current IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance (sample tested) 3- 152 Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 24 mA VCC = Min VIN = 0 V VCC = Max f = 0 MHz VCC = Max VIN = GND or VCCIO VCC = Max VO = GND or VCCIO VIN = GND f = 1.0 MHz Min 2.4 V 2.4 V 0.5 V 0.4 V 126 Typ mA -10 +10 A -100 +100 A 10 pF June 1, 1996 (Version 1.0) AC Timing Requirements Parameter Max sequential toggle frequency (with feedback) using FastCLK Max sequential toggle frequency (with feedback) using a Product-Term Clock Max macrocell toggle frequency using local feedback and FastCLK Max macrocell register transmission frequency (without feedback) using FastCLK Max macrocell register transmission frequency (without feedback) using a Product-Term Clock Max input register transmission frequency (without feedback) using FastCLK Max input register to macrocell register pipeline frequency using FastCLK FastCLK pulse width (HIgh/Low) Export Control Max. flip-flop toggle rate Product-term clock pulse width (active/inactive) Input to macrocell register set-up time before FastCLK Input to macrocell register hold time tH after FastCLK Input to macrocell register set-up time tSU1 (Note 1) before Product-term clock Input to macrocell register hold time tH1 after Product-term clock Input to register/latch set-up time tSU2 before FastLCK Input to register/latch hold time tH2 after FastLCK FastInput to macrocell register set-up time tSU5 before FastCLK FastInput to macrocell register hold time tH5 after FastCLK Set/Reset pulse width (active) tWA tRA Set/Reset input recovery set-up time before FastCLK Set/Reset input hold time tHA after FastCLK Set/Reset input recovery set-up time tRA1 before Product-term clock Set/Reset input hold time tHA1 after Product-term clock tHRS Product-term clock width (active/inactive) Symbol fCYC (Note 1) fCYC1 (Note 1) fCYC4 (Note 2) fCLK (Note 2) fCLK1 (Note 2) fCLK2 (Note 2) fCLK3 (Note 1) tW fTOG tW1 tSU XC7236A-16 (Com/Ind only) XC7236A-25 XC7236A-20 Fig. 6 Min 40 Min 50 6 40 50 60 MHz 50 50 60 MHz 45 50 60 MHz 42 50 60 MHz 50 50 60 MHz 7 33 40 60 MHz 11 10 Max Max 8 Min 60 Max Units MHz 11 9 12 29 9 24 7 18 ns MHz ns ns 9 -7 -4 -4 ns 8 16 14 10 ns 8 0 0 0 ns 10 8 8 6 ns 10 0 0 0 ns 20 18 15 ns 0 0 0 ns 11 11 12 30 12 25 10 20 ns ns 11 -5 0 0 ns 11 15 15 12 ns 11 9 9 8 ns 10 10 8 ns 50 6 62 83 Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU. 2. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements. June 1, 1996 (Version 1.0) 3- 153 XC7236A 36-Macrocell CMOS CPLD Propagation Delays Symbol tCO tCO1 tAO tPD (Note 1) tOE tOD tPD5 tOE5 tOD5 tFOE tFOD Parameter FastCLK input to registered output delay P-term clock input to registered output delay Set/Reset input to registered output delay Input to non-registered output delay Input to output enable Input to output disable FastInput to non-registered macrocell output delay FastInput to output enable FastInput to output disable FOE input to output enable FOD input to output disable XC7236A-16 (Com/Ind only) XC7236A-25 XC7236A-20 Fig. 11 11 11 11 Min 5 10 10 10 Max 14 30 40 40 Min 3 5 5 5 Max 13 24 32 32 Min 3 5 5 5 Max 10 20 25 25 Units 11 11 10 10 10 32 32 31 5 5 5 25 25 25 5 5 5 20 20 20 ns ns ns 5 5 5 5 23 23 15 15 3 3 3 3 20 20 14 14 3 3 3 3 15 15 12 12 ns ns ns ns ns ns ns ns Note: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU. Incremental Parameters Symbol tPDT1 (Note 2) tPDT8 (Note 2) tPDT9 (Note 2) tCOF1 tCOF2 (Note 3) tPDF (Note 1) tAOF tOEF tODF tIN + tOUT (Note 4) Parameter Fig. Arithmetic carry delay 12 between adjacent macrocells Arithmetic carry delay through 9 adjacent 12 macrocells in a FB Arithmetic carry delay through 10 macrocells 12 from macrocell #n to macrocell #n in next FB Incremental delay from UIM-input (for P-term 13 clock) to registered macrocell feedback Incremental delay from FastCLK net to 13 latched/registered UIM-input Incremental delay from UIM-input to 13 non-registered macrocell feedback Incremental delay from UIM-input (Set/Reset) to 13 registered macrocell feedback Incremental delay from UIM-input (used as out13 put-enable/disable) to macrocell feedback Propagation delay 13 through unregistered input pad (to UIM) plus output pad driver (from macrocell) XC7236A-25 XC7236A-20 Min Min Max 1.2 Max 1.2 XC7236A-16 (Com/Ind only) Min Max 1 Units ns 6 5 3 ns 9 6 4 ns 12 7 5 ns 1 1 1 ns 22 14 10 ns 22 14 10 ns 14 7 5 ns 18 18 15 ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for an adder with registered outputs. 3. Parameter tCOF2 is derived as the difference between the clock period for pipelining input-to-macrocell registers (1/fCLK3) and the non-registered input set-up time (tSU). 4. Parameter tIN represents the delay from an input or I/O pin to a UIM-input (or from a FastCLK pin to the Fast CLK net); tOUT represents the delay from a macrocell output (feedback point) to an output or I/O pin. Only the sum of tIN + tOUT can be derived from measurements, e.g., tIN + tOUT = tSU + tCO - 1/fCYC. 3- 154 June 1, 1996 (Version 1.0) Power-up/Reset Timing Parameters Symbol tWMR trVCC tRESET Parameter Master Reset input Low pulse width VCC rise time (if MR not used for power-up) Configuration completion time (to outputs operational) Min 100 Typ Max 350 5 1000 Units ns s s Note: Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, VCC rise must be monotonic. Following reset, the Clock, Reset and Set inputs must not be asserted until all applicable input and feedback set-up times are met. VTEST R1 Device Output Test Point CL R2 Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL O 5.0 V 5.0 V 310 195 35 pF 3.3 V 3.3 V 260 360 35 pF X3489 Figure 5: AC Load Circuit June 1, 1996 (Version 1.0) 3- 155 XC7236A 36-Macrocell CMOS CPLD Timing and Delay Path Specifications The delay path consists of three blocks that can be connected in series: Figure 8 defines the set-up and hold times from the data inputs to the product-term clock used by the output register. * * * Figure 9 defines the set-up and hold times from the data inputs to the FastCLK used by the output register. Input Buffer and associated latch or register Logic Resource (UIM, AND-array and macrocell) Three-state Output Buffer All inputs have the same delay, regardless of fan-out or location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input method (direct, latched or registered) and the number of times a signal passes through the combinatorial logic. Timing and Delay Path Descriptions Figure 6 defines the maximum clock frequency (with feedback). Any macrocell output can be fed back to the UIM as an input for the next clock cycle. Figure 6 shows the relevant delay path. The parameters fCYC and fCYC1 specify the maximum operating frequency for FastCLK and product-term clock operation respectively. Figure 7 specifies the max operating frequency (fCLK3) for pipelined operation between the input registers and the macrocell registers, using FastCLK. UIM Figure 11 shows the waveforms for the macrocell and control paths Figure 12 defines the carry propagation delays between macrocells and between FBs. The parameters describe the delay from the C , D1 and D2 inputs of a macrocell ALU to IN the CIN input of the adjacent macrocell ALU. These delays must be added to the standard macrocell delay path (tPD or tSU) to determine the performance of an arithmetic function. Figure 13 defines the incremental parameters for the standard macrocell logic paths. These incremental parameters are used in conjunction with pin-to-pin parameters when calculating compound logic path timing. Incremental parameters are derived indirectly from other pin-to-pin measurement. Function Block AND-Array, ALU Logic Input or I/O Pin Figure 10 defines the set-up and hold times from the data input to the FastCLK used in an input register. Macrocell Register D Q Output Driver Output or I/O Pin FASTCLK or P-Term Clock 1/fCYC, 1/fCYC1 FASTCLK or Product Term Clock Macrocell Register Output X3279 Figure 6: Delay Path Specification for fCYC and fCYC1 3- 156 June 1, 1996 (Version 1.0) UIM Function Block Input-Pad Register D Q Input or I/O Pin Macrocell Register D Q AND-Array, ALU Logic Output Driver Output or I/O Pin FASTCLK Pin 1/fCLK3 FASTCLK Input-Pad Register Output X3280 Figure 7: Delay Path Specification for fCLK3 UIM Function Block AND-Array, ALU Logic Input or I/O Pin Macrocell Register D Q Output Driver Output or I/O Pin Input or I/O Pin Clock Output tSU1 Input or I/O Pin tH1 Data X3281 Figure 8: Delay Path Specification for fSU1 and fH1 June 1, 1996 (Version 1.0) 3- 157 XC7236A 36-Macrocell CMOS CPLD UIM Function Block Macrocell Register D Q AND-Array, ALU Logic Input or I/O Pin Output Driver Output or I/O Pin FASTCLK Pin FASTCLK Input tSU - tH Input or I/O Pin Data X3282 Figure 9: Delay Path Specification for fSU and fH UIM Input or I/O Pin Input-Pad Register D Q FASTCLK Pin FASTCLK Pin tSU2 Input or I/O Pin tH2 Data X3283 Figure 10: Delay Path Specification for fSU2 and fH2 3- 158 June 1, 1996 (Version 1.0) * tSU2 and tH2 are measured with respect to the high-going Registered Inputs tSU2* FastCLK tH2* tSU2* tWL tWH Active Inactive edge of FastCLK for registered inputs, and with respect to the low-going edge of FastCLK for latched inputs. Only the high going edge is used for clocking the macrocell registers. tH2* Active tHA Input Used as Clock tW1 tW1 Active Inactive tSU tSU1 Active tHA1 tH tH1 Unlatched Inputs Inactive Active tRA Inactive Active tRA1 tWA Valid Disable Valid Enable Valid Reset/Set Reset/Set De-Asserted tOE tPD tOD Non-Registered Outputs tCO tAO tCO1 Registered Outputs X3284 Figure 11: Principal Pin-to-Pin Measurements tPDF tOUT tIN UIM Function Block MC1 ALU Cin A0 F D1, D2 tPDT1 F D1, D2 AND/OR S0 MC2 ALU Cin A1 Cout Macrocell Register Cout Macrocell Register S1 tPDT1 ALU tPDT8 A8 Cin MC9 F D1, D2 Cout Macrocell Register S8 Function Block ALU AND/OR A9 tPDT9 MC1 Cin D1, D2 F Macrocell Register S9 X3287 Figure 12: Arithmetic Timing Parameters June 1, 1996 (Version 1.0) 3- 159 XC7236A 36-Macrocell CMOS CPLD UIM Function Block tOUT tTPDF tIN Output or I/O Pin AND-Array ALU Logic Input or I/O Pin Macrocell Register tIN tAOF AND-Array ALU Logic Input or I/O Pin tOUT R S D Output or I/O Pin Q tCOF1 tOUT tIN Input or I/O Pin D Q C/E tIN AND-Array ALU Logic D Output or I/O Pin Q tCOF tCOF2 FASTCLK Pin X3288 Figure 13: Incremental Timing Parameters 3- 160 June 1, 1996 (Version 1.0) XC7372 Pinouts Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Input Master Reset Input Input Input Input Input Output VPP MC2-1 MC2-4 MC2-5 GND Input FastCLK0 FastCLK1 FastCLK2 MC2-6 MC2-7 MC2-8 MC2-9 VCCIO Input Input Input Input MC1-1 MC1-2 MC1-3 MC1-4 GND Input Input Input/FI Input/FI Input/FI June 1, 1996 (Version 1.0) MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Input Output VCCIO Input/FI Input/FI Input/FI Input Input MC4-9 MC4-8 MC4-7 MC4-6 MC4-5 GND Input Input FastOE Input MC4-4 MC4-3 MC4-2 MC4-1 VCCINT Input/FI Input/FI Input/FI Input MC3-9 MC3-8 MC3-7 MC3-6 GND Input Input Input Input Input MC3-5 MC3-4 MC3-3 MC3-2 MC3-1 3- 161 XC7236A 36-Macrocell CMOS CPLD Ordering Information XC7236A - 16 PC 44 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -25 25 ns (40 MHz) sequential cycle time -20 20 ns (50 MHz) sequential cycle time -16 16 ns (60 MHz) sequential cycle time (commercial/industrial only) Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier WC44 44-Pin Windowed Ceramic Leaded Chip Carrier Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case) Component Availability Pins 44 Type Code Plastic PLCC PC44 CI CI CI XC7236A -25 -20 -16 C = Commercial = 0 to +70C I = Industrial = -40 to 85C 3- 162 Ceramic CLCC WC44 CIM CIM CI M = Military = -55C(A) to 125C (C) June 1, 1996 (Version 1.0) XC7272A 72-Macrocell CMOS CPLD June 1, 1996 (Version 1.0) Product Specification Features This additional ALU in each macrocell can generate any combinatorial function of two sums of products, and it can generate and propagate arithmetic-carry signals between adjacent macrocells and Functional Blocks. * * * * * * * * * * * Second-Generation High Density Programmable Logic Device UV-erasable CMOS EPROM technology 72 macrocells, grouped into eight Function Blocks (FBs), interconnected by a programmable Universal Interconnect Matrix Each FB contains a programmable AND-array with 21 complementary inputs, providing up to 16 product terms per macrocell Enhanced logic features: - 2-input Arithmetic Logic Unit in each macrocell - Dedicated fast carry network between macrocells - Wide AND capability in the Universal Interconnect Matrix Identical timing for all interconnect paths and for all macrocell logic paths 72 signal pins in the 84-pin packages - 42 I/Os, 12 inputs, 18 outputs Each input is programmable - Direct, latched, or registered I/O-pin is usable as input when macrocell is buried Two high-speed, low-skew global clock inputs Available in 68-pin and 84-pin PLCC/CLCC, 84-pin PGA packages General Description The XC7272A combines the classical features of the PALlike CPLD architecture with innovative systems-oriented logic enhancements. This favors the implementation of fast state machines, large synchronous counters and fast arithmetic, as well as multi-level general-purpose logic. Performance, measured in achievable system clock rate and critical delays, is not only predictable, but independent of physical logic mapping, interconnect routing, and resource utilization. Performance, therefore, remains invariant between design iterations. The propagation delay through interconnect and logic is constant for any function implemented in any one of the output macrocells. The Universal Interconnect Matrix (UIM) facilitates unrestricted, fixed-delay interconnects from all device inputs and macrocell outputs to any Function Block AND-array input. The UIM can also perform a logical AND across any number of its incoming signals on the way to any Functional Block, adding another level of logic without additional delay. This supports bidirectional loadable synchronous counters of any size up to 72 bits, operating at the specified maximum device frequency As a result of these logic enhancements, the XC7272A can deliver high performance even in designs that combine large numbers of product terms per output, or need more layers of logic than AND-OR, or need a wide AND function in some of the product terms, or perform wide arithmetic functions. Architectural Overview Figure 1 shows the XC7272A structure. Eight Function Blocks(FBs) are all interconnected by a central UIM. Each FB receives 21 signals from the UIM and each FB produces nine signals back into the UIM. All device inputs are also routed via the UIM to all FBs. Each FB contains nine output macrocells that draw from a programmable AND array driven by the 21 signals from the UIM. Most Macro-cells drive a 3-state chip output. All feed back into the UIM. The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit (ALU) in each macrocell. Dedicated fast arithmetic carry lines running directly between adjacent macrocells and FBs support fast adders, subtractors and comparators of any length up to 72 bits. June 1, 1996 (Version 1.0) 3- 163 I I I I I I I I I I I I 7 6 5 4 3 2 84 83 82 81 80 79 [5] [4] [3] * * [2] * * [68] [67] [66] [65] XC7272A 72-Macrocell CMOS CPLD 12 20 22 36 68 84 LCC LCC 36 Arithmetic Carry FB4 FB5 I/O MC4-1 MC5-9 I/O MC4-2 MC5-8 FCLK/O MC4-3 MC5-7 FCLK/O MC4-4 MC4-5 MC4-6 21 21 AND ARRAY 12 11 10 9 AND ARRAY [10] [9] [8] [7] 84 68 LCC LCC MC5-6 MC5-5 MC5-4 I/O MC5-3 I/O MC4-8 MC5-2 I/O MC4-9 MC5-1 I/O MC4-7 74 75 76 77 [60] [61] [62] [63] 65 66 67 68 70 71 72 73 [55] [56] [57] [58] * * * * 54 55 56 57 58 60 61 62 63 [44] [45] [46] [47] [48] [50] [51] [52] [53] 44 45 46 47 48 50 51 52 53 * * [36] [37] [38] [40] [41] [42] [43] UIM FB3 O MC3-1 MC6-9 O MC3-2 MC6-8 O O MC3-3 MC6-7 O O MC3-4 MC6-6 O O MC3-5 MC6-5 O O MC3-6 MC6-4 O O MC3-7 MC6-3 O O MC3-8 MC6-2 O MC3-9 MC6-1 O 21 21 FB2 AND ARRAY 21 20 19 18 16 15 14 13 AND ARRAY * * * * [14] [13] [12] [11] FB6 FB7 I/O MC2-1 MC7-9 I/O I/O MC2-2 MC7-8 I/O I/O MC2-3 MC7-7 I/O I/O MC2-4 MC7-6 I/O MC7-5 I/O MC7-4 I/O MC7-3 I/O * * [34] [33] [32] [30] [29] [28] [27] 42 41 40 39 38 36 35 34 33 21 21 AND ARRAY 32 31 30 29 28 26 25 24 23 AND ARRAY [26] [25] [24] [23] [22] [20] [19] [18] [17] I/O MC2-5 I/O MC2-6 I/O MC2-7 I/O MC2-8 MC7-2 I/O I/O MC2-9 MC7-1 I/O I/O MC1-1 MC8-9 I/O I/O MC1-2 MC8-8 I/O I/O MC1-3 MC8-7 I/O I/O MC1-4 MC8-6 I/O I/O MC1-5 MC8-5 I/O I/O MC1-6 MC8-4 I/O I/O MC1-7 MC8-3 I/O I/O MC1-8 MC8-2 I/O I/O MC1-9 MC8-1 I/O FB8 21 21 AND ARRAY AND ARRAY FB1 Arithmetic Carry * = Pin not present on 68 LCC X3493 Figure 1: XC7272A Architecture 3- 164 June 1, 1996 (Version 1.0) The ALU has two programmable modes. In the logic mode, it is a 2-input function generator, a 4-bit look-up table, that can be programmed to generate any Boolean function of its two inputs. It can OR them, widening the OR function to 16 inputs; it can AND them, which means that one sum of products can be used to mask the other; it can XOR them, toggling the flip-flop or comparing the two sums of products. Either or both of the sum-of-product inputs to the ALU can be inverted, and either or both can be ignored. The ALU can implement one additional layer of logic without any speed penalty. Function Blocks and Macrocells The XC7272A contains 72 identical macrocells, grouped into eight FBs of nine macrocells each. Each macrocell is driven by product terms derived from the 21 inputs from the UIM into the Function Block. Figure 2 shows the macrocell structure. Five product terms are private to each macrocell; an additional 12 product terms are shared among the nine macrocells in any Function Block. One private product term is a dedicated clock for the flip-flop in the macrocell. In the arithmetic mode, the ALU block can be programmed to generate the arithmetic sum or difference of two operands, combined with a carry signal coming from the lower macrocell; it also feeds a carry output to the next higher macrocell. This carry propagation chain crosses the boundaries between FBs, but it can also be configured as a 0 or 1 when it enters a Function Block. The remaining four private product terms can be selectively ORed together with up to three of the shared product terms, to drive one input to an Arithmetic Logic Unit (ALU). The other input to the ALU is driven by the OR of up-to-nine product terms from the remaining shared product terms. As a programmable option, two of the private product terms can be used for other purposes. One is the asynchronous active-High Reset of the macrocell flip-flop, the other can be either an asynchronous active-High Set of the macrocell flip-flop, or provide an active-High Output-Enable signal from any one of the Function Block inputs. This dedicated carry chain overcomes the inherent speed and density problems of the traditional CPLD architecture, when trying to perform arithmetic functions like add, subtract, and magnitude compare. One Function Block AND Array Arithmetic Carry-In from Previous Macrocell 1 of 9 Macrocells 5 Private P-Terms per Macrocell 3 9 I/O Pad CLOCK OE* SET RESET MUX 5 12 Sharable P-Terms per Function Block Fast Clocks 0 1 C in D1 F D2 C out R S D Q MUX 21 Inputs from UIM Input-Pad Register/Latch (optional) ALU Clock Select To 8 More Macrocells * OE is forced high when P-term is not used Pin Register Trasparent Control Arithmetic Carry-Out to Next Macrocell Feedback to UIM Input to UIM X5490 Figure 2: Function Block and Macrocell Schematic June 1, 1996 (Version 1.0) 3- 165 XC7272A 72-Macrocell CMOS CPLD The ALU output drives the D input of the macrocell flip-flop. Universal Interconnect Matrix Each flip-flop has several programmable options: The UIM receives 126 inputs: 72 from the 72 macrocells, 42 from bidirectional I/O pins, and 12 from dedicated input pins. Acting as an unrestricted crossbar switch, the UIM generates 168 output signals, 21 to each Function Block. One option is to eliminate the flip-flop by making it transparent, which makes the Q output identical with the D input, independent of the clock. If this option is not programmed, the flip-flop operates in the conventional manner, triggered by the rising edge on its clock input. The clock source is programmable: It is either the dedicated product term mentioned above, or it is one of the two global FastCLK signals that are distributed with short delay and minimal skew over the whole chip. The asynchronous Set and Reset (Clear) inputs override the clocked operation. If both asynchronous inputs are active simultaneously, Reset overrides Set. Upon powerup, each macrocell flip-flop can be preloaded with either 0 or 1. In addition to driving the chip output buffer, the macrocell output is also routed back as an input to the UIM. When the Output Enable product term mentioned above is not active, this feedback line is forced High and thus disabled. Any one of the 126 inputs can be programmed to be connected to any number of the 168 outputs. The delay through the array is constant, independent of the apparent routing distance, the fan-out, fan-in, or routing complexity. Routability is not an issue: Any UIM input can drive any UIM output, even multiple outputs, and the delay is constant. When multiple inputs are programmed to be connected to the same output, this output becomes the AND of the input signals if the levels are interpreted as active High. By choosing the appropriate signal inversion in the macrocell outputs and the Function Block AND-array input, this ANDlogic can also be used to implement a NAND, OR, or NOR function, thus offering an additional level of logic without any speed penalty. A macrocell feedback signal that is disabled by the output enable product term represents a High input to the UIM. Several such macrocell outputs programmed onto the same UIM output emulate a 3-state bus line. If one of the macrocell outputs is enabled, the UIM output assumes that same level. Macrocell Output I/O and FCLK/O Pins Only MUX OE P-Term Pin Driver From Macrocell Register I/O Pin MUX Feedback to UIM To UIM Q D CLK Q D EN FastCLK1 FastCLK0 Input and I/O Pins Only X5339 Figure 3: Input/Output Schematic 3- 166 June 1, 1996 (Version 1.0) Outputs schematic entry, or through a behavioral description expressed in Boolean equations. Sixty of the 72 macrocells drive chip outputs directly through 3-state output buffers, each individually controlled by the Output Enable product term mentioned above. For bidirectional I/O pins, an additional programmable cell can optionally disable the output permanently. The buried flipflop is then still available for internal feedback, and the pin can still be used as a separate input The user can specify a security bit that prevents any reading of the programming bit map after the device has been programmed and verified. The device is programmed in a manner similar to an EPROM (ultra-violet light erasable read-only memory) using the Intel Hex or JEDEC format. Programming support is available from a number of programmer manufacturers. The UIM connections and Function Block AND-array connections are made directly by non-volatile EPROM cells. Other control bits are read out of the EPROM array and stored into latches just after power-up. This method, common among CPLD devices, requires either a very fast VCC rise time (<5 s) or the application of a master-reset signal delayed at least until VCC has reached the required operating voltage. The latter can be achieved using a simple capacitor and pull-up resistor on the MR pin (the RC product should be larger than twice the VCC rise time). The power-up or reset signal initiates a self-timed configuration period lasting about 350 s (tRESET), during which all device outputs remain disabled and programmed preload state values are loaded into the macrocell registers. Inputs Each signal input to the chip is programmable as either direct, latched, or registered in a flip-flop. The latch and flipflop can be programmed with either of the two FastCLK signals as latch enable or clock. The latch is transparent when FastCLK is High, and the flip-flop clocks on the rising edge of FastCLK. Registered inputs allow high system clock rates by pipelining the inputs before they incur the combinatorial delay in the device, in cases where a pipeline cycle is acceptable. The direct, latched, or registered inputs then drive the UIM. There is no propagation-delay difference between pure inputs and I/O inputs. Programming and Using the XC7272A Unused input and I/O pins should be tied to ground or Vcc or some valid logic level. This is common practice for all CMOS devices to avoid dissipating excess current through the input-pad circuitry. The features and capabilities described above are used by the Xilinx XACTstep development software to program the device according to the specification given either through The recommended decoupling capacitance on the three VCC pins should total 1 F using high-speed (tantalum or ceramic) capacitors. 350 TA = -55C TA = 25C 300 Supply Current (mA) TA = 125C 250 200 150 100 50 0 5 10 15 20 25 30 Count Frequency (MHz) 35 40 X3254 Figure 4: Typical ICC vs. Frequency for XC7272A configured as sixteen 4-bit counters (VCC = +5.0 V, VIN = VCC or GND, all outputs open) June 1, 1996 (Version 1.0) 3- 167 XC7272A 72-Macrocell CMOS CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to VCC +0.5 -0.5 to VCC +0.5 -0.5 to 7.0 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCCINT/ VCCIO VIH VIL Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = -40C to 85C Supply voltage relative to GND Military TA = -55C to TC + 125C High-level input voltage Low-level input voltage Min 4.75 4.5 4.5 2.0 0 Max 5.25 5.5 5.5 VCC +0.5 0.8 Units V V V V V Max Units DC Characteristics Over Recommended Operating Conditions Symbol Parameter VOH TTL High-level output voltage VOL TTL Low-level output voltage ICC Supply current IIL IOZ CIN Input leakage current Output high-Z leakage current Input capacitance (sample tested) 3- 168 Test Conditions IOH = -4.0 mA VCC = Min IOL = 8 mA VCC = Min VIN = 0 V VCC = Max f = 0 MHz Min 2.4 V 0.5 222 Typ -10 -100 +10 +100 10 V mA A A pF June 1, 1996 (Version 1.0) AC Timing Requirements Parameter Max sequential toggle frequency (with feedback) using FastCLK Max sequential toggle frequency (with feedback) using a Product-Term Clock Max macrocell register transmission frequency (without feedback) using FastCLK Max macrocell register transmission frequency (without feedback) using a Product-Term Clock Max input register transmission frequency (without feedback) using FastCLK Max input register to macrocell register pipeline frequency using FastCLK FastCLK Low pulse width FastCLK High pulse width Export Control Max. flip-flop toggle rate Product-term clock pulse width (active/inactive) Input to macrocell register set-up time before FastCLK Input to macrocell register hold time tH after FastCLK Input to macrocell register set-up time tSU1 (Note 1) before Product-term clock Input to macrocell register hold time tH1 after Product-term clock Input to register/latch set-up time tSU2 before FastLCK Input to register/latch hold time tH2 after FastLCK Set/Reset pulse width tWA tRA Set/Reset input recovery set-up time before FastCLK Set/Reset input hold time tHA after FastCLK Set/Reset input recovery set-up time tRA1 before Product-term clock Set/Reset input hold time tHA1 after Product-term clock tHRS Set/Reset input hold time after Reset/Set inactive Symbol fCYC (Note 1) fCYC1 (Note 1) fCLK (Note 2) fCLK1 (Note 2) fCLK2 (Note 2) fCLK3 (Note 1) tWL tWH fTOG tW1 tSU Fig. XC7272A-25 XC7272A-20 Min 40 Min 50 Max Max XC7272A-16 (Com/Ind only) Min 55 Max Units MHz 40 50 55 MHz 40 50 55 MHz 40 50 55 MHz 67 67 67 MHz 7 40 50 60 MHz 11 11 7.5 7.5 7.5 7.5 6 6 11 9 10 24 9 19 7 15 ns ns MHz ns ns 9 -7 -4 -4 ns 8 10 8 6 ns 8 0 0 0 ns 10 8 8 6 ns 10 0 0 0 ns 11 11 12 20 10 20 8 16 ns ns 11 -5 -3 -3 ns 11 6 5 4 ns 11 9 8 6 ns 10 8 6 ns 67 67 83 Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU. 2. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements. June 1, 1996 (Version 1.0) 3- 169 XC7272A 72-Macrocell CMOS CPLD Propagation Delays Symbol tCO tCO1 tAO tPDD (Note 1) tOE tOD Note: Parameter FastCLK input to registered output delay P-term clock input to registered output delay Set/Reset input to registered output delay Input to non-registered output delay Input to output enable Input to output disable XC7272A-16 (Com/Ind only) XC7272A-25 XC7272A-20 Fig. 11 11 11 11 Min 5 10 13 13 Max 16 30 40 40 Min 3 6 8 8 Max 14 25 32 32 Min 3 6 8 8 Max 12 21 25 25 Units 11 11 11 32 32 7 7 25 25 7 7 22 22 ns ns ns ns ns ns 1. Specifications account for logic paths which use the maximum number of available product terms and the ALU. Incremental Parameters Symbol tPDT1 (Note 2) tPDT8 (Note 2) tPDT9 (Note 2) tCOF tCOF1 tCOF2 (Note 3) tPDF (Note 1) tAOF tOEF tODF tIN + tOUT (Note 4) Parameter Fig. Arithmetic carry delay 12 between adjacent macrocells Arithmetic carry delay through 9 adjacent 12 macrocells in a FB Arithmetic carry delay through 10 macrocells 12 from macrocell #n to macrocell #n in next FB Incremental delay from FastCLK net to registered 13 output feedback Incremental delay from UIM-input (for P-term 13 clock) to registered macrocell feedback Incremental delay from FastCLK net to 13 latched/registered UIM-input Incremental delay from UIM-input to 13 non-registered macrocell feedback Incremental delay from UIM-input (Set/Reset) to 13 registered macrocell feedback Incremental delay from UIM-input (used as out13 put-enable/disable) to macrocell feedback Propagation delay 13 through unregistered input pad (to UIM) plus output pad driver (from macrocell) XC7272A-25 XC7272A-20 Min Min Max 1.6 Max 1.2 XC7272A-16 (Com/Ind only) Min Max 1 Units ns 10 8 6 ns 14 12 10 ns 1 1 1 ns 1.5 12 10 ns 1 1 1 ns 25 19 14 ns 25 19 14 ns 17 12 11 ns 15 13 11 ns Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU. 2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for an adder with registered outputs. 3. Parameter tCOF2 is derived as the difference between the clock period for pipelining input-to-macrocell registers (1/fCLK3) and the non-registered input set-up time (tSU). 4. Parameter tIN represents the delay from an input or I/O pin to a UIM-input (or from a FastCLK pin to the Fast CLK net); tOUT represents the delay from a macrocell output (feedback point) to an output or I/O pin. Only the sum of tIN + tOUT can be derived from measurements, e.g., tIN + tOUT = tSU + tCO - 1/fCYC. 3- 170 June 1, 1996 (Version 1.0) Power-up/Reset Timing Parameters Symbol tWMR trVCC tRESET Parameter Master Reset input Low pulse width VCC rise time (if MR not used for power-up) Configuration completion time (to outputs operational) Min 100 Typ Max 350 5 1000 Units ns s s VTEST R1 Device Output Test Point CL R2 Device Imput Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL O 5.0 V 5.0 V 450 245 35 pF X3490 Figure 5: AC Load Circuit June 1, 1996 (Version 1.0) 3- 171 XC7272A 72-Macrocell CMOS CPLD Timing and Delay Path Specifications The delay path consists of three blocks that can be connected in series: Figure 8 defines the set-up and hold times from the data inputs to the product-term clock used by the output register. * * * Figure 9 defines the set-up and hold times from the data inputs to the FastCLK used by the output register. Input Buffer and associated latch or register Logic Resource (UIM, AND-array and macrocell) Three-state Output Buffer All inputs have the same delay, regardless of fan-out or location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input method (direct, latched or registered) and the number of times a signal passes through the combinatorial logic. Timing and Delay Path Descriptions Figure 6 defines the maximum clock frequency (with feedback). Any macrocell output can be fed back to the UIM as an input for the next clock cycle. Figure 6 shows the relevant delay path. The parameters fCYC and fCYC1 specify the maximum operating frequency for FastCLK and product-term clock operation respectively. Figure 7 specifies the max operating frequency (fCLK3) for pipelined operation between the input registers and the macrocell registers, using FastCLK. UIM Figure 11 shows the waveforms for the macrocell and control paths Figure 12 defines the carry propagation delays between macrocells and between FBs. The parameters describe the delay from the C , D1 and D2 inputs of a macrocell ALU to IN the CIN input of the adjacent macrocell ALU. These delays must be added to the standard macrocell delay path (tPD or tSU) to determine the performance of an arithmetic function. Figure 13 defines the incremental parameters for the standard macrocell logic paths. These incremental parameters are used in conjunction with pin-to-pin parameters when calculating compound logic path timing. Incremental parameters are derived indirectly from other pin-to-pin measurement. Function Block AND-Array, ALU Logic Input or I/O Pin Figure 10 defines the set-up and hold times from the data input to the FastCLK used in an input register. Macrocell Register D Q Output Driver Output or I/O Pin FASTCLK or P-Term Clock 1/fCYC, 1/fCYC1 FASTCLK or Product Term Clock Macrocell Register Output X3279 Figure 6: Delay Path Specification for fCYC and fCYC1 3- 172 June 1, 1996 (Version 1.0) UIM Function Block Input-Pad Register D Q Input or I/O Pin Macrocell Register D Q AND-Array, ALU Logic Output Driver Output or I/O Pin FASTCLK Pin 1/fCLK3 FASTCLK Input-Pad Register Output X3280 Figure 7: Delay Path Specification for fCLK3 UIM Function Block AND-Array, ALU Logic Input or I/O Pin Macrocell Register D Q Output Driver Output or I/O Pin Input or I/O Pin Clock Output tSU1 Input or I/O Pin tH1 Data X3281 Figure 8: Delay Path Specification for fSU1 and fH1 June 1, 1996 (Version 1.0) 3- 173 XC7272A 72-Macrocell CMOS CPLD UIM Function Block Macrocell Register D Q AND-Array, ALU Logic Input or I/O Pin Output Driver Output or I/O Pin FASTCLK Pin FASTCLK Input tSU - tH Input or I/O Pin Data X3282 Figure 9: Delay Path Specification for fSU and fH UIM Input or I/O Pin Input-Pad Register D Q FASTCLK Pin FASTCLK Pin tSU2 Input or I/O Pin tH2 Data X3283 Figure 10: Delay Path Specification for fSU2 and fH2 3- 174 June 1, 1996 (Version 1.0) * tSU2 and tH2 are measured with respect to the high-going Registered Inputs tSU2* FastCLK tH2* tSU2* tWL tWH Active Inactive edge of FastCLK for registered inputs, and with respect to the low-going edge of FastCLK for latched inputs. Only the high going edge is used for clocking the macrocell registers. tH2* Active tHA Input Used as Clock tW1 tW1 Active Inactive tSU tSU1 Active tHA1 tH tH1 Unlatched Inputs Inactive Active tRA Inactive Active tRA1 tWA Valid Disable Valid Enable Valid Reset/Set Reset/Set De-Asserted tOE tPD tOD Non-Registered Outputs tCO tAO tCO1 Registered Outputs X3284 Figure 11: Principal Pin-to-Pin Measurements tPDF tOUT tIN UIM Function Block MC1 ALU Cin A0 F D1, D2 tPDT1 F D1, D2 AND/OR S0 MC2 ALU Cin A1 Cout Macrocell Register Cout Macrocell Register S1 tPDT1 ALU tPDT8 A8 Cin MC9 F D1, D2 Cout Macrocell Register S8 Function Block ALU AND/OR A9 tPDT9 MC1 Cin D1, D2 F Macrocell Register S9 X3287 Figure 12: Arithmetic Timing Parameters June 1, 1996 (Version 1.0) 3- 175 XC7272A 72-Macrocell CMOS CPLD UIM Function Block tOUT tTPDF tIN Output or I/O Pin AND-Array ALU Logic Input or I/O Pin Macrocell Register tIN tAOF AND-Array ALU Logic Input or I/O Pin tOUT R S D Output or I/O Pin Q tCOF1 tOUT tIN Input or I/O Pin D Q C/E tIN AND-Array ALU Logic D Output or I/O Pin Q tCOF tCOF2 FASTCLK Pin X3288 Figure 13: Incremental Timing Parameters 3- 176 June 1, 1996 (Version 1.0) XC7372 Pinouts PC68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 - in XC7272A Master Reset Input Input Input Input Input Input GND Fast CLK0 Fast CLK1 Input Input out MC4-4 MC4-3 MC4-2 MC4-1 MC3-8 MC3-7 MC3-6 MC3-5 GND MC3-4 MC3-3 MC3-2 MC3-1 Vcc Input Input Input Input MC2-9 MC2-8 MC2-7 MC2-6 GND Input Input Input Input Input Input Input Input Input MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 MC1-9 MC1-8 MC1-7 MC1-6 GND Input Input Input Input Input June 1, 1996 (Version 1.0) MC1-5 MC1-4 MC1-3 MC1-2 MC1-1 PC84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 PG84 F-9 F-11 E-11 E-10 E-9 D-11 D-10 C-11 B-11 C-10 A-11 B-10 B-9 A-10 A-9 B-8 A-8 B-6 B-7 A-7 C-7 C-6 A-6 A-5 B-5 C-5 A-4 B-4 A-3 A-2 B-3 A-1 B-2 C-2 B-1 C-1 D-2 D-1 E-3 E-2 E-1 F-2 PC68 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 - in XC7272A Vcc Input Input Input Input Input out MC8-9 MC8-8 MC8-7 MC8-6 MC8-5 GND Input Input Input Input Input Input Input Input Input MC8-4 MC8-3 MC8-2 MC8-1 MC7-9 MC7-8 MC7-7 MC7-6 MC7-5 GND Input Input Input Input MC7-4 MC7-3 MC7-2 MC7-1 Vcc MC6-8 MC6-7 MC6-6 MC6-5 GND MC6-4 MC6-3 MC6-2 MC6-1 MC5-4 MC5-3 MC5-2 MC5-1 Input Input Input Input GND Input Input Input Input Input Input PC84 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PG84 F-3 G-3 G-1 G-2 F-1 H-1 H-2 J-1 K-1 J-2 L-1 K-2 K-3 L-2 L-3 K-4 L-4 J-5 K-5 L-5 K-6 J-6 J-7 L-7 K-7 L-6 L-8 K-8 L-9 L-10 K-9 L-11 K-10 J-10 K-11 J-11 H-10 H-11 F-10 G-10 G-11 G-9 3- 177 XC7272A 72-Macrocell CMOS CPLD Ordering Information XC7272A - 16 PC 84 C Device Type Temperature Range Speed Number of Pins Package Type Speed Options -25 25 ns (40 MHz) sequential cycle time -20 20 ns (50 MHz) sequential cycle time -16 16 ns (60 MHz) sequential cycle time (commercial/industrial only) Packaging Options PC68 68-Pin Plastic Leaded Chip Carrier WC68 68-Pin Windowed Ceramic Leaded Chip Carrier PC84 84-Pin Plastic Leaded Chip Carrier WC84 84-Pin Windowed Ceramic Leaded Chip Carrier PG84 84-Pin Ceramic Windowed Pin Grid Array Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case) Component Availability Pins 68 Type Code XC7272A -25 -20 -16 Plastic PLCC PC68 CI CI CI C = Commercial = 0 to +70C 3- 178 Ceramic CLCC WC68 CI CI CI Plastic PLCC PC84 CI CI CI I = Industrial = -40 to 85C 84 Ceramic CLCC WC84 CIM CIM CI Ceramic PGA PG84 CI CI CI M = Military = -55C(A) to 125C (C) June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products SRAM-Based FPGA Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors SRAM-Based FPGA Products Table of Contents SRAM-Based FPGA Products XC4000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 XC5200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-179 XC5200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181 XC5200L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249 XC6200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251 XC6200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253 XC3000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287 XC3000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289 XC3000A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341 XC3000L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349 XC3100A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357 XC3100L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365 XC4000 Series Table of Contents XC4000 Series Field Programmable Gate Arrays XC4000-Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4000EX/XL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E and XC4000EX Families Compared to the XC4000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in XC4000E and XC4000EX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Improvements in XC4000EX Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Function Generators as RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Lines (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal I/O Routing (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-5 4-5 4-5 4-6 4-7 4-8 4-8 4-9 4-11 4-11 4-11 4-11 4-12 4-12 4-12 4-13 4-13 4-13 4-13 4-13 4-13 4-14 4-21 4-24 4-24 4-27 4-29 4-29 4-30 4-30 4-31 4-31 4-32 4-32 4-32 4-35 4-35 4-35 4-36 4-37 4-37 4-38 4-40 4-41 4-41 4-43 4-46 4-1 XC4000 Series Table of Contents Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of Global Set/Reset After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-46 4-50 4-50 4-50 4-53 4-53 4-53 4-54 4-54 4-54 4-54 4-54 4-55 4-55 4-56 4-56 4-57 4-59 4-59 4-59 4-60 4-60 4-60 4-62 4-63 4-63 4-63 4-64 4-64 4-65 4-65 4-65 4-65 4-65 4-65 4-66 4-66 4-68 4-70 4-72 4-74 4-74 4-74 4-76 4-79 4-79 4-79 4-80 4-80 4-80 4-80 4-81 4-81 4-82 4-83 4-84 XC4000E CLB Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines . . . . XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs). . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs) . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . XC4000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4003E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4005E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4006E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4008E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4010E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4013E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4020E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4036EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4044EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4052XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC84 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG120 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQ144 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG156 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ160 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQ176 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG191 Package Pinouts (see PG223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG223 and PG191 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BG225 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQ240, HQ240 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG299 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HQ304 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BG352 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG411 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BG432 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85 4-86 4-87 4-88 4-89 4-90 4-91 4-92 4-93 4-94 4-95 4-96 4-96 4-96 4-96 4-97 4-97 4-98 4-100 4-102 4-104 4-107 4-110 4-118 4-123 4-128 4-133 4-133 4-134 4-135 4-136 4-138 4-140 4-142 4-144 4-145 4-149 4-152 4-154 4-157 4-160 4-163 4-166 4-170 4-174 4-176 4-178 4-3 XC4000 Series Table of Contents 4-4 XC4000 Series Field Programmable Gate Arrays June 1, 1996 (Version 1.02) Product Specification XC4000-Series Features Additional XC4000EX/XL Features Note: XC4000-Series devices described in this data sheet include the XC4000E, XC4000EX, XC4000L, and XC4000XL. This information does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D or XC4000H. For information on these devices, see the Xilinx WEBLINX at http://www.xilinx.com. * * * * * * * * * * Third Generation Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Fully PCI compliant (speed grades -3 and faster) - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance to 66 MHz Flexible Array Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output (4 mA per XC4000L output) Configured by Loading Binary File - Unlimited reprogrammability Readback Capability Backward Compatible with XC4000 Devices XACTstep Development System runs on '386/'486/ Pentium-type PC, Sun-4, and Hewlett-Packard 700 series - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization - RAM/ROM compiler * * * * * * * * Highest Capacity -- Over 130,000 Usable Gates Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Configurable Logic Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility Flexible New High-Speed Clock Network - 8 additional Early Buffers for shorter clock delays - 4 additional FastCLKTM buffers for fastest clock input - Virtually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs High-Speed Parallel ExpressTM Configuration Mode Improved I/O Setup and Clock-to-Output with FastCLK and Global Early Buffers 4 Additional Address Bits in Master Parallel Configuration Mode Introduction XC4000-Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of eleven years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. The XC4000 Series currently has 19 members, as shown in Table 1. Low-Voltage Versions Available * * * Low-Voltage Devices Function at 3.0 - 3.6 Volts XC4000L: Low-Voltage Versions of XC4000E devices XC4000XL: Low-Voltage Versions of XC4000EX devices June 1, 1996 (Version 1.02) 4-5 XC4000 Series Field Programmable Gate Arrays Table 1: XC4000-Series Field Programmable Gate Arrays Device XC4003E XC4005E/L XC4006E XC4008E XC4010E/L XC4013E/L XC4020E XC4025E XC4028EX/XL XC4036EX/XL XC4044EX/XL XC4052XL XC4062XL Max Logic Max. RAM Typical Total Number Gates Bits Gate Range CLB Logic of (No RAM) (No Logic) (Logic and RAM)* Matrix Blocks Flip-Flops 3,000 3,200 2,000 - 5,000 10 x 10 100 360 5,000 6,272 3,000 - 9,000 14 x 14 196 616 6,000 8,192 4,000 - 12,000 16 x 16 256 768 8,000 10,368 6,000 - 15,000 18 x 18 324 936 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 Larger Devices Available in the First Half of 1997 Max. Decode Inputs per side 30 42 48 54 60 72 84 96 96 108 120 132 144 Max. User I/O 80 112 128 144 160 192 224 256 256 288 320 352 384 * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. Note: Throughout the functional descriptions in this document, references to the XC4000E device family include the XC4000L, and references to the XC4000EX device family include the XC4000XL, unless explicitly stated otherwise. References to the XC4000 Series include the XC4000E, XC4000EX, XC4000L, and XC4000XL families. All functionality in low-voltage families is the same as in the corresponding 5-Volt family, except where numerical references are made to timing, power, or current-sinking capability. Description XC4000-Series devices are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal memory cells. The FPGA can either actively read its configuration data from an external serial or byteparallel PROM (master modes), or the configuration data 4-6 can be written into the FPGA from an external device (slave, peripheral and Express modes). XC4000-Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, floorplanning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of the configuration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month. For lowest high-volume unit cost, a design can first be implemented in the XC4000E or XC4000EX, then migrated to one of Xilinx' compatible HardWire mask-programmed devices. Table 2 shows density and performance for a few common circuit functions that can be implemented in XC4000-Series devices. June 1, 1996 (Version 1.02) Table 2: Density and Performance for Several Common Circuit Functions in XC4000E1 Design Class Memory Logic Note: Function 256 x 8 Single Port (read/modify/write) 32 x 16 bit FIFO simultaneous read/write MUXed read/write 9 bit Shift Register (with enable) 16 bit Pre-Scaled Counter 16 bit Loadable Counter 16 bit Accumulator 8 bit, 16 tap FIR Filter sample rate parallel serial 8 x 8 Parallel Multiplier single stage, register to register 16 bit Address Decoder (internal decode) 9 bit Parity Checker CLBs Used 72 XC4000E-3 63 XC4000E-2 80 Units MHz 48 32 5 8 8 9 63 63 170 142 65 65 80 80 200 170 76 76 MHz MHz MHz MHz MHz MHz 400 68 55 8.1 65 10 MHz MHz 73 3 1 37 4.7 4.3 30 3.9 2.7 ns ns ns 1. Most functions are faster in XC4000EX due to faster carry logic, direct connects, and other additional interconnect. Taking Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be recon- June 1, 1996 (Version 1.02) figured dynamically to perform different functions at different times. Reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product time-to-market. 4-7 XC4000 Series Field Programmable Gate Arrays XC4000E and XC4000EX Families Compared to the XC4000 For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000-Series devices are listed in this section. The biggest advantages of XC4000E and XC4000EX devices are significantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000EX devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. Most XC4000EX devices have no corresponding XC4000 devices, because of the larger CLB arrays. The XC4028EX has the same array size as the XC4025 and XC4025E, but is not bitstream-compatible. However, the XC4025, XC4025E, and XC4028EX are all pinout-compatible. Improvements in XC4000E and XC4000EX Increased System Speed Delays in FPGA-based designs are layout dependent. There is a rule of thumb designers can consider--the system clock rate should not exceed one third to one half of the specified toggle rate. Critical portions of a design, such as shift registers and simple counters, can run faster--approximately two thirds of the specified toggle rate. XC4000E and XC4000EX devices can run at synchronous system clock rates of up to 66 MHz, and internal performance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000Series devices use a sub-micron triple-layer metal process. In addition, many architectural improvements have been made, as described below. Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes The RAM in any CLB can be configured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write. Dual-Port RAM A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be configured as either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, or as combinatorial logic. Configurable RAM Content The RAM content can now be loaded at configuration time, so that the RAM starts up with user-defined data. H Function Generator In XC4000-Series devices, the H function generator is more versatile than in the XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function generator can thus be totally or partially independent of the other two function generators, increasing the maximum capacity of the device. IOB Clock Enable The two flip-flops in each IOB have a common clock enable input, which through configuration can be activated individually for the input or output flip-flop or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the IOBs more versatile, and avoids the need for clock gating. Output Drivers XC4000-Series -3 and faster speed grades are fully PCI compliant. XC4000E and XC4000EX devices can be used to implement a one-chip PCI solution. The output pull-up structure defaults to a TTL-like totempole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 outputs. Alternatively, XC4000-Series devices can be globally configured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also, the configurable pullup resistor in the XC4000 Series is a p-channel transistor that pulls to Vcc, whereas in the XC4000 it is an n-channel transistor that pulls to a voltage one transistor threshold below Vcc. Carry Logic Input Thresholds The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry chain through a single CLB (TBYP), have improved by as much as 50% from XC4000 values. See "Fast Carry Logic" on page 21 for more information. The input thresholds can be globally configured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two global adjustments of input threshold and output level are independent of each other. PCI Compliance 4-8 June 1, 1996 (Version 1.02) Global Signal Access to Logic Faster Input and Output There is additional access from global clocks to the F and G function generator inputs. A fast, dedicated early clock sourced by global clock buffers is available for the IOBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the early clock is available. The input data can be initially loaded into the Fast Capture latch with the early clock, then transferred to the input flip-flop or latch with the low-skew global clock. A programmable delay on the input can be used to avoid hold-time requirements. See "IOB Input Signals" on page 24 for more information. Configuration Pin Pull-Up Resistors During configuration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually configured with or without weak pull-up or pull-down resistors after configuration. The PROGRAM input pin has a permanent weak pull-up. Soft Start-up Like the XC3000A, XC4000-Series devices have "Soft Start-up." When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual configuration option. XC4000 and XC4000A Compatibility Existing XC4000 bitstreams can be used to configure an XC4000E device. XC4000A bitstreams must be recompiled for use with the XC4000E due to improved routing resources, although the devices are pin-for-pin compatible. Additional Improvements in XC4000EX Only Increased Routing New interconnect in the XC4000EX includes twenty-two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs. The twelve "Quad Lines" in each CLB row and column include optional repowering buffers for maximum speed. Additional highperformance routing near the IOBs enhances pin flexibility. June 1, 1996 (Version 1.02) Latch Capability in CLBs Storage elements in the XC4000EX CLB can be configured as either flip-flops or latches. This capability makes the FPGA highly synthesis-compatible. IOB Output MUX From Output Clock A multiplexer in the IOB allows the output clock to select either the output data or the IOB clock enable as the output to the pad. Thus, two different data signals can share a single output pad, effectively doubling the number of device outputs without requiring a larger, more expensive package. This multiplexer can also be configured as an ANDgate to implement a very fast pin-to-pin path. See "IOB Output Signals" on page 27 for more information. Express Configuration Mode A new slave configuration mode accepts parallel data input. Data is processed in parallel, rather than serialized internally. Therefore, the data rate is eight times that of the six conventional configuration modes. Additional Address Bits Larger devices require more bits of configuration data. A daisy chain of several large XC4000EX devices may require a PROM that cannot be addressed by the eighteen address bits supported in the XC4000E. The XC4000EX family therefore extends the addressing in Master Parallel configuration mode to 22 bits. 4-9 XC4000 Series Field Programmable Gate Arrays Table 3: CLB Count of Selected XC4000-Series Soft Macros 7400 Equivalents CLBs `138 5 `139 2 `147 5 `148 6 `150 5 `151 3 `152 3 `153 2 `154 16 `157 2 `158 2 `160 5 `161 6 `162 8 `163 8 `164 4 `165s 9 `166 5 `168 7 `174 3 `194 5 `195 3 `280 3 `283 8 `298 2 `352 2 `390 3 `518 3 `521 3 Explanation of RAM nomenclature s = single-port edge-triggered d = dual-port edge-triggered no extension = level-sensitive 4-10 Barrel Shifters brlshft4 brlshft8 4-Bit Counters cd4cd cd4cle cd4rle cb4ce cb4cle cb4re 8- and 16-Bit Counters cb8ce cb8re cc16ce cc16cle cc16cled Identity Comparators comp4 comp8 comp16 Magnitude Comparators compm4 compm8 compm16 RAMs ram16x4 ram16x4s ram16x4d CLBs Multiplexers CLBs 4 m2-1e 1 13 m4-1e 1 m8-1e 3 m16-1e 5 3 Registers 5 rd4r 2 6 rd8r 4 3 rd16r 8 6 5 Shift Registers 6 sr8ce 4 10 sr16re 8 9 Decoders 9 d2-4e 2 21 d3-8e 4 d4-16e 16 1 2 5 Explanation of counter nomenclature cb = binary counter 4 cd = BCD counter 9 cc = cascadable binary counter 20 d = bidirectional l = loadable e = clock enable r = synchronous reset c = asynchronous clear 2 2 4 June 1, 1996 (Version 1.02) Detailed Functional Description XC4000-Series devices achieve high speed through advanced semiconductor technology and improved architecture. The XC4000E and XC4000EX support system clock rates of up to 66 MHz and internal performance in excess of 150 MHz. Compared to older Xilinx FPGA families, XC4000-Series devices are more powerful. They offer on-chip edge-triggered and dual-port RAM, clock enables on I/O flip-flops, and wide-input decoders. They are more versatile in many applications, especially those involving RAM. Design cycles are faster due to a combination of increased routing resources and more sophisticated software. Basic Building Blocks Xilinx user-programmable gate arrays include two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * * CLBs provide the functional elements for constructing the user's logic. IOBs provide the interface between the package pins and internal signal lines. Three other types of circuits are also available: * * * 3-State buffers (TBUFs) driving horizontal longlines are associated with each CLB. Wide edge decoders are available around the periphery of each device. An on-chip oscillator is provided. Programmable interconnect resources provide routing paths to connect the inputs and outputs of these configurable elements to the appropriate networks. The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. Each of these available circuits is described in this section. Configurable Logic Blocks (CLBs) Configurable Logic Blocks implement most of the logic in an FPGA. The principal CLB elements are shown in Figure 1. The number of CLBs needed to implement selected soft macros is shown in Table 3. Two 4-input function generators (F and G) offer unrestricted versatility. Most combinatorial logic functions need four or fewer inputs. However, a third function generator (H) is provided. The H function generator has three inputs. Either zero, one, or both of these inputs can be the outputs of F and G; the other input(s) are from outside the CLB. The CLB can, therefore, implement certain functions of up to nine variables, like parity check or expandable-identity comparison of two sets of four inputs. Each CLB contains two storage elements that can be used to store the function generator outputs. However, the storage elements and function generators can also be used independently. These storage elements can be configured as flip-flops in both XC4000E and XC4000EX devices; in the XC4000EX they can optionally be configured as latches. DIN can be used as a direct input to either of the two storage elements. H1 can drive the other through the H function generator. Function generator outputs can also drive two outputs independent of the storage element outputs. This versatility increases logic capacity and simplifies routing. Thirteen CLB inputs and four CLB outputs provide access to the function generators and storage elements. These inputs and outputs connect to the programmable interconnect resources outside the block. Function Generators Four independent inputs are provided to each of two function generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F' and G', are each capable of implementing any arbitrarily defined Boolean function of four inputs. The function generators are implemented as memory look-up tables. The propagation delay is therefore independent of the function implemented. A third function generator, labeled H', can implement any Boolean function of its three inputs. Two of these inputs can optionally be the F' and G' functional generator outputs. Alternatively, one or both of these inputs can come from outside the CLB (H2, H0). The third input must come from outside the block (H1). Signals from the function generators can exit the CLB on two outputs. F' or H' can be connected to the X output. G' or H' can be connected to the Y output. A CLB can be used to implement any of the following functions: * any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables1 * any single function of five variables * any function of four variables together with some functions of six variables * some functions of up to nine variables. 1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB. June 1, 1996 (Version 1.02) 4-11 XC4000 Series Field Programmable Gate Arrays C1 * * * C4 4 H1 D IN /H 2 EC SR/H 0 G4 G3 G2 S/R CONTROL Bypass DIN F' G' H' LOGIC FUNCTION G' OF G1-G4 YQ SD D Q G1 LOGIC FUNCTION OF H' F', G', AND H1 EC RD G' H' 1 Y F4 F3 F2 Bypass S/R CONTROL DIN F' G' H' LOGIC FUNCTION F' OF F1-F4 XQ SD D Q F1 EC RD K (CLOCK) 1 H' F' X Multiplexer Controlled by Configuration Program X6692 Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown) Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This flexibility improves cell usage. Flip-Flops The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial results or other incoming data in one or two flip-flops, and connect their outputs to the interconnect network as well. The two edge-triggered D-type flip-flops have common clock (K) and clock enable (EC) inputs. Either or both clock inputs can also be permanently enabled. Storage element functionality is described in Table 4. Table 4: CLB Storage Element Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Latch Both Legend: X __/ SR 0* 1* K EC SR D Q X X X X SR X __/ 0 1 0 X X 1* X 1* 1* 0 1 0* 0* 0* 0* 0* X D X X D X SR D Q Q D Q Don't care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) Latches (XC4000EX only) The CLB storage elements can also be configured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Storage element functionality is described in Table 4. 4-12 Clock Input Each flip-flop can be triggered on either the rising or falling clock edge. The clock pin is shared by both storage elements. However, the clock is individually invertible for each storage element. Any inverter placed on the clock input is automatically absorbed into the CLB. June 1, 1996 (Version 1.02) Clock Enable Data Inputs and Outputs The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state. EC is not invertible within the CLB. The source of a storage element data input is programmable. It is driven by any of the functions F', G', and H', or by the Direct In (DIN) block input. The flip-flops or latches drive the XQ and YQ CLB outputs. Set/Reset Two fast feed-through paths are available, as shown in Figure 1. A two-to-one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs. This bypass is sometimes used by the automated router to repower internal signals. An asynchronous storage element input (SR) can be configured as either set or reset. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a Global Set/Reset pulse during normal operation, and the effect of a pulse on the SR pin of the CLB. All three set/ reset functions for any single flip-flop are controlled by the same configuration data bit. The set/reset state can be independently specified for each flip-flop. This input can also be independently disabled for either flip-flop. The set/reset state is specified by using the INIT attribute, or by placing the appropriate set or reset flip-flop library symbol. Control Signals Multiplexers in the CLB map the four control inputs (C1 - C4 in Figure 1) into the four internal control signals (H1, DIN/ H2, SR/H0, and EC). Any of these inputs can drive any of the four internal control signals. When the logic function is enabled, the four inputs are: * * EC -- Enable Clock SR/H0 -- Asynchronous Set/Reset or H function generator Input 0 DIN/H2 -- Direct In or H function generator Input 2 H1 -- H function generator Input 1. SR is active High. It is not invertible within the CLB. * * Global Set/Reset When the memory function is enabled, the four inputs are: A separate Global Set/Reset line (not shown in Figure 1) sets or clears each storage element during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. * * * * Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. Therefore, if a flip-flop is set by SR, it is also set by GSR. Similarly, a reset flip-flop is reset by both SR and GSR. Using FPGA Flip-Flops and Latches GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 2.) A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Set/ Reset signal. Alternatively, GSR can be driven from any internal node. STARTUP PAD IBUF GSR GTS Q2 Q3 Q1Q4 CLK DONEIN EC -- Enable Clock WE -- Write Enable D0 -- Data Input to F and/or G function generator D1 -- Data input to G function generator (16x1 and 16x2 modes) or 5th Address bit (32x1 mode). The abundance of flip-flops in the XC4000 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline flip-flops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB flip-flop, place the appropriate library symbol. For example, FDCE is a D-type flip-flop with clock enable and asynchronous clear. The corresponding latch symbol (for the XC4000EX only) is called LDCE. In XC4000-Series devices, the flip flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices. The CLB setup time is specified between the function generator inputs and the clock input K. Therefore, the specified CLB flip-flop setup time includes the delay through the function generator. X5260 Figure 2: Schematic Symbols for Global Set/Reset June 1, 1996 (Version 1.02) 4-13 XC4000 Series Field Programmable Gate Arrays Using Function Generators as RAM RAM Configuration Options Optional modes for each CLB make the memory look-up tables in the F' and G' function generators usable as an array of Read/Write memory cells. Available modes are level-sensitive (similar to the XC4000/A/H families), edgetriggered, and dual-port edge-triggered. Depending on the selected mode, a single CLB can be configured as either a 16x2, 32x1, or 16x1 bit array. The function generators in any CLB can be configured as RAM arrays in the following sizes: Supported CLB memory configurations and timing modes for single- and dual-port modes are shown in Table 5. XC4000-Series devices are the first programmable logic devices with edge-triggered (synchronous) and dual-port RAM accessible to the user. Edge-triggered RAM simplifies system timing. Dual-port RAM doubles the effective throughput of FIFO applications. These features can be individually programmed in any XC4000-Series CLB. * * One F or G function generator can be configured as a 16x1 RAM while the other function generators are used to implement any function of up to 5 inputs. Additionally, the XC4000-Series RAM may have either of two timing modes: * * Advantages of On-Chip and Edge-Triggered RAM The on-chip RAM is extremely fast. The read access time is the same as the logic delay. The write access time is slightly slower. Both access times are much faster than any off-chip solution, because they avoid I/O delays. Edge-triggered RAM, also called synchronous RAM, is a feature never before available in a Field Programmable Gate Array. The simplicity of designing with edge-triggered RAM, and the markedly higher achievable performance, add up to a significant improvement over existing devices with on-chip RAM. Three application notes are available from Xilinx that discuss edge-triggered RAM: "XC4000E Edge-Triggered and Dual-Port RAM Capability," "Implementing FIFOs in XC4000E RAM," and "Synchronous and Asynchronous FIFO Designs." All three application notes apply to both XC4000E and XC4000EX RAM. Table 5: Supported RAM Modes Single-Port Dual-Port 16 x 1 16 x 2 32 x 1 EdgeTriggered Timing LevelSensitive Timing Two 16x1 RAMs: two data inputs and two data outputs with identical or, if preferred, different addressing for each RAM One 32x1 RAM: one data input and one data output. Edge-Triggered (Synchronous): data written by the designated edge of the CLB clock. WE acts as a true clock enable. Level-Sensitive (Asynchronous): an external WE signal acts as the write strobe. The selected timing mode applies to both function generators within a CLB when both are configured as RAM. The number of read ports is also programmable: * * Single Port: each function generator has a common read and write port Dual Port: both function generators are configured together as a single 16x1 dual-port RAM with one write port and two read ports. Simultaneous read and write operations to the same or different addresses are supported. RAM configuration options are selected by placing the appropriate library symbol. Choosing a RAM Configuration Mode The appropriate choice of RAM mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 6. The difference between level-sensitive, edge-triggered, and dual-port RAM is only in the write operation. Read operation and timing is identical for all modes of operation. Table 6: RAM Mode Selection Use for New Designs? Size (16x1, Registered) Simultaneous Read/Write Relative Performance 4-14 LevelSensitive EdgeTriggered Dual-Port EdgeTriggered No Yes Yes 1/2 CLB 1/2 CLB 1 CLB No No Yes X 2X 2X (4X effective) June 1, 1996 (Version 1.02) C1 * * * C4 4 D1 WE EC D0 DIN WRITE DECODER 4 G1 * * * G4 16-LATCH ARRAY MUX G' 4 1 of 16 LATCH ENABLE READ ADDRESS WRITE PULSE DIN WRITE DECODER 4 F1 * * * F4 16-LATCH ARRAY MUX F' 4 1 of 16 LATCH ENABLE K (CLOCK) WRITE PULSE READ ADDRESS X6752 Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM C1 * * * C4 4 EC WE D1/A4 EC D0 DIN WRITE DECODER G1 * * * G4 F1 * * * F4 4 16-LATCH ARRAY MUX G' 4 1 of 16 LATCH ENABLE WRITE PULSE READ ADDRESS H' DIN WRITE DECODER 4 16-LATCH ARRAY MUX F' 4 1 of 16 K (CLOCK) LATCH ENABLE WRITE PULSE READ ADDRESS X6754 Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical) June 1, 1996 (Version 1.02) 4-15 XC4000 Series Field Programmable Gate Arrays RAM Inputs and Outputs TWPS The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. WCLK (K) The functionality of the CLB control signals changes when the function generators are configured as RAM. The DIN/ H2, H1, and SR/H0 lines become the two data inputs (D0, D1) and the Write Enable (WE) input for the 16x2 memory. When the 32x1 configuration is selected, D1 acts as the fifth address bit and D0 is the data input. The contents of the memory cell(s) being addressed are available at the F' and G' function-generator outputs. They can exit the CLB through its X and Y outputs, or can be captured in the CLB flip-flop(s). Configuring the CLB function generators as Read/Write memory does not affect the functionality of the other portions of the CLB, with the exception of the redefinition of the control signals. In 16x2 and 16x1 modes, the H' function generator can be used to implement Boolean functions of F', G', and D1, and the D flip-flops can latch the F', G', H', or D0 signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) RAM simplifies timing requirements. XC4000-Series edge-triggered RAM timing operates like writing to a data register. Data and address are presented. The register is enabled for writing by a logic High on the write enable input, WE. Then a rising or falling clock edge loads the data into the register, as shown in Figure 5. Complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. The active edge of WCLK latches the address, input data, and WE signals. An internal write pulse is generated that performs the write. See Figure 3 and Figure 4 for block diagrams of a CLB configured as 16x2 and 32x1 edge-triggered, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port, edge-triggered mode are shown in Table 7. The Write Clock input (WCLK) can be configured as active on either the rising edge (default) or the falling edge. It uses the same CLB pin (K) used to clock the CLB flip-flops, but it can be independently inverted. Consequently, the RAM output can optionally be registered within the same 4-16 TWHS TWSS WE TDSS TDHS TASS TAHS DATA IN ADDRESS TILO TWOS DATA OUT OLD TILO NEW X6461 Figure 5: Edge-Triggered RAM Write Timing CLB either by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to both function generators in the CLB when both are configured as RAM. The WE pin is active-High and is not invertible within the CLB. Note: The pulse following the active edge of WCLK (TWPS in Figure 5) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are configured as edge-triggered RAM. Table 7: Single-Port Edge-Triggered RAM Signals RAM Signal D A[3:0] A[4] WE WCLK SPO (Data Out) CLB Pin D0 or D1 (16x2, 16x1) D0 (32x1) F1-F4 or G1-G4 D1 (32x1) WE K F' or G' Function Data In Address Address Write Enable Clock Single Port Out (Data Out) June 1, 1996 (Version 1.02) Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously at two independent addresses. Simultaneous read and write operations at the same address are also supported. Dual-port mode always has edge-triggered write timing, as shown in Figure 5. Figure 6 shows a simple model of an XC4000-Series CLB configured as dual-port RAM. One address port, labeled A[3:0], supplies both the read and write address for the F function generator. This function generator behaves the same as a 16x1 single-port edge-triggered RAM array. The RAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reflects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the G function generator. The write address for the G function generator, however, comes from the address A[3:0]. The output from this 16x1 RAM array, Dual Port Out (DPO), appears at the G function generator output. DPO, therefore, reflects the data at address DPRA[3:0]. RAM16X1D Primitive Therefore, by using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effective throughput of the FIFO. The relationships between CLB pins and RAM inputs and outputs for dual-port, edge-triggered mode are shown in Table 8. See Figure 7 for a block diagram of a CLB configured in this mode. Note: The pulse following the active edge of WCLK (TWPS in Figure 5) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are configured as edge-triggered RAM. Table 8: Dual-Port Edge-Triggered RAM Signals RAM Signal CLB Pin D D0 A[3:0] F1-F4 DPRA[3:0] WE WCLK SPO G1-G4 WE K F' DPO G' DPO (Dual Port Out) WE D DPRA[3:0] WE D D Q Registered DPO AR[3:0] AW[3:0] Function Data In Read Address for F, Write Address for F and G Read Address for G Write Enable Clock Single Port Out (addressed by A[3:0]) Dual Port Out (addressed by DPRA[3:0]) G Function Generator SPO (Single Port Out) WE D A[3:0] D Q Registered SPO AR[3:0] AW[3:0] F Function Generator WCLK X6755 Figure 6: XC4000-Series Dual-Port RAM, Simple Model June 1, 1996 (Version 1.02) 4-17 XC4000 Series Field Programmable Gate Arrays C1 * * * C4 4 D1 WE EC D0 DIN WRITE DECODER 16-LATCH ARRAY G' MUX 4 1 of 16 LATCH ENABLE G1 * * * G4 WRITE PULSE 4 READ ADDRESS DIN WRITE DECODER F1 * * * F4 4 K (CLOCK) 16-LATCH ARRAY F' MUX 4 1 of 16 LATCH ENABLE WRITE PULSE READ ADDRESS X6748 Figure 7: 16x1 Edge-Triggered Dual-Port RAM 4-18 June 1, 1996 (Version 1.02) Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000-Series backward-compatibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be complicated in execution. Data and address signals are presented, then a positive pulse on the write enable pin (WE) performs a write into the RAM at the designated address. As indicated by the "level-sensitive" label, this RAM acts like a latch. During the WE High pulse, changing the data lines results in new data written to the old address. Changing the address lines while WE is High results in spurious data written to the new address--and possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. The user must generate a carefully timed WE signal. The delay on the WE signal and the address lines must be carefully verified to ensure that WE does not become active until after the address lines have settled, and that WE goes inactive before the address lines change again. The data must be stable before and after the falling edge of WE. In practical terms, WE is usually generated by a 2X clock. If a 2X clock is not available, the falling edge of the system clock can be used. However, there are inherent risks in this approach, since the WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several older application notes are available from Xilinx that discuss the design of level-sensitive RAMs. These application notes include XAPP031, "Using the XC4000 RAM Capability," and XAPP042, "High-Speed RAM Design in XC4000." However, the edge-triggered RAM available in the XC4000 Series is superior to level-sensitive RAM for almost every application. Figure 8 shows the write timing for level-sensitive, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port level-sensitive mode are shown in Table 9. Figure 9 and Figure 10 show block diagrams of a CLB configured as 16x2 and 32x1 level-sensitive, single-port RAM. Initializing RAM at Configuration Both RAM and ROM implementations of the XC4000Series devices are initialized during configuration. The initial contents are defined via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. If not defined, all RAM contents are initialized to all zeros, by default. RAM initialization occurs only during configuration. The RAM content is not affected by Global Set/Reset. Table 9: Single-Port Level-Sensitive RAM Signals RAM Signal D A[3:0] WE O CLB Pin D0 or D1 F1-F4 or G1-G4 WE F' or G' Function Data In Address Write Enable Data Out T WC ADDRESS TAS T WP T AH WRITE ENABLE T DS DATA IN T DH REQUIRED X6462 Figure 8: Level-Sensitive RAM Write Timing June 1, 1996 (Version 1.02) 4-19 XC4000 Series Field Programmable Gate Arrays C1 * * * C4 4 WE D1 EC D0 DIN Enable 16-LATCH ARRAY WRITE DECODER 4 G1 * * * G4 G' MUX 1 of 16 4 READ ADDRESS DIN Enable WRITE DECODER 4 F1 * * * F4 16-LATCH ARRAY F' MUX 1 of 16 4 READ ADDRESS X6746 Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM C1 * * * C4 4 WE D1/A4 D0 EC DIN Enable G1 * * * G4 F1 * * * F4 4 WRITE DECODER 16-LATCH ARRAY MUX G' 1 of 16 4 READ ADDRESS H' DIN Enable 4 WRITE DECODER 16-LATCH ARRAY MUX F' 1 of 16 4 READ ADDRESS X6749 Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical) 4-20 June 1, 1996 (Version 1.02) Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of normal routing resources. Dedicated fast carry logic greatly increases the efficiency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be configured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efficient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benefit at the 32-bit level. The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: "Using the Dedicated Carry Logic in XC4000." This discussion also applies to XC4000E devices, and to XC4000EX devices when the minor logic changes are taken into account. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols. CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB This fast carry logic is one of the more significant features of the XC4000 Series, speeding up arithmetic and counting into the 70 MHz range. The carry chain in XC4000E devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right. (See Figure 11.) In order to improve speed in the high-capacity XC4000EX devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in Figure 12. This restriction should have little impact, because the smallest XC4000EX device, the XC4028EX, can accommodate a 64-bit carry chain in a single column. Additionally, standard interconnect can be used to route a carry signal in the downward direction. Figure 13 on page 22 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000EX is similar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 13, the carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 14 and Figure 15 on page 23 show the details of the carry logic for the XC4000E and the XC4000EX respectively. These diagrams show the contents of the box labeled "CARRY LOGIC" in Figure 13. As shown, the XC4000EX carry logic eliminated a multiplexer to reduce delay on the pass-through carry chain. Additionally, the multiplexer on the G4 path now has a memory-programmable input, which permits G4 to directly connect to COUT. G4 thus becomes an additional high-speed initialization path for carry-in. June 1, 1996 (Version 1.02) X6687 Figure 11: Available XC4000E Carry Propagation Paths CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB X6610 Figure 12: Available XC4000EX Carry Propagation Paths (dotted lines use general interconnect) 4-21 XC4000 Series Field Programmable Gate Arrays CARRY LOGIC C OUT D IN C IN DOWN G Y H G CARRY G4 G3 G DIN G2 S/R H D G F Q YQ Q XQ G1 EC COUT0 H H1 DIN S/R H F CARRY D G F EC F4 F3 F F2 H F1 X F CIN UP C OUT K S/R EC X6699 Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX) 4-22 June 1, 1996 (Version 1.02) C OUT M G1 M 1 0 1 G2 0 I G4 G3 C OUT0 TO FUNCTION GENERATORS M F2 M 1 0 F1 M 0 1 0 M F4 1 3 M 1 F3 M 0 M M M 1 0 C IN UP X2000 C IN DOWN Figure 14: Detail of XC4000E Dedicated Carry Logic COUT M G1 M 1 0 M 1 G2 0 G4 G3 COUT0 TO FUNCTION GENERATORS M F2 M 1 0 F1 M M M F3 M 0 1 0 F4 1 3 1 M 0 C IN UP M X6701 Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic) June 1, 1996 (Version 1.02) 4-23 XC4000 Series Field Programmable Gate Arrays Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals. Figure 16 shows a simplified block diagram of the XC4000E IOB. A more complete diagram of the XC4000E IOB can be found in Figure 42 on page 51, in the "Boundary Scan" section. Figure 42 includes the boundary scan logic in the IOB. Figure 17 shows a simplified block diagram of the XC4000EX IOB. The XC4000EX IOB contains some special features not included in the XC4000E IOB. These features are highlighted in Figure 17, and discussed throughout this section. When XC4000EX special features are discussed, they are clearly identified in the text. Any feature not so identified is present in both XC4000E and XC4000EX devices. IOB Input Signals Two paths, labeled I1 and I2 in Figure 16 and Figure 17, bring input signals into the array. Inputs also connect to an input register that can be programmed as either an edgetriggered flip-flop or a level-sensitive latch. The choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are available, and some combinations of latches and flip-flops can be implemented in a single IOB, as described in the XACT Libraries Guide. The inputs can be globally configured for either TTL (1.2V, default) or CMOS thresholds, using an option in the MakeBits program. There is a slight hysteresis of about 300mV. The output levels are also configurable; the two global adjustments of input threshold and output level are independent. Inputs of the low-voltage devices must be configured as CMOS at all times. They can be driven by the outputs of all 5-Volt XC4000-Series devices, provided that the 5-Volt outputs are in TTL mode. They can also be driven by any TTL output that does not exceed 3.7 V. 5-Volt XC3000-family device outputs, for example, are TTL-compatible, but since the output voltage can exceed 3.7 V, they cannot be used to drive an XC4000L or XC4000XL input. Table 10: Supported Sources for XC4000-Series Device Inputs XC4000-Series Inputs 3.3 V, 5 V, 5 V, CMOS TTL CMOS Source Any device, Vcc = 3.3 V, CMOS outputs XC4000-Series, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, TTL outputs (Voh 3.7 V) Any device, Vcc = 5 V, CMOS outputs Danger1 Unreliable Data 1. Acceptable for XC4000XL if the designated 5-Volt supply pad (VTT) is tied to 5V. Registered Inputs The I1 and I2 signals that exit the block can each carry either the direct or registered input signal. The input and output storage elements in each IOB have a common clock enable input, which, through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC pin on the XC4000-Series CLB. It cannot be inverted within the IOB. The storage element behavior is shown in Table 11. Table 11: Input Register Functionality (active rising edge is shown) Mode Clock Power-Up or GSR Flip-Flop X Clock Enable X __/ 0 1 0 X 1* X 1* 1* 0 Latch Both Legend: X __/ SR 0* 1* D Q X SR D X X D X D Q Q D Q Don't care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) The inputs of XC4000-Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC4000-Series device inputs are shown in Table 10. 4-24 June 1, 1996 (Version 1.02) Passive Pull-Up/ Pull-Down Slew Rate Control T Flip-Flop D Q Out Output Buffer CE Pad Output Clock I1 I2 Clock Enable Input Buffer FlipFlop/ Latch Q D Delay CE Input Clock X6704 Figure 16: Simplified Block Diagram of XC4000E IOB Slew Rate Control T Passive Pull-Up/ Pull-Down Output MUX 0 1 Flip-Flop Out D Q Output Buffer CE Pad Input Buffer Output Clock I1 I2 Clock Enable Flip-Flop/ Latch Q CE Delay D Fast Capture Latch Delay Q D Latch G Input Clock X5984 Figure 17: Simplified Block Diagram of XC4000EX IOB (shaded areas indicate differences from XC4000E) June 1, 1996 (Version 1.02) 4-25 XC4000 Series Field Programmable Gate Arrays Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input flip-flop setup time is defined between the data measured at the device I/O pin and the clock input at the IOB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the IOB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the default. The XC4000E IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC4000E global clock buffers. (See "Global Nets and Buffers (XC4000E only)" on page 41 for a description of the global clock buffers in the XC4000E.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the flip-flop. The XC4000EX IOB has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The attributes or properties used to select the desired delay are shown in Table 12. The choices are no added attribute, MEDDELAY, and NODELAY. The default setting, with no added attribute, ensures no hold time with respect to any of the XC4000EX clock buffers, including the Global LowSkew buffers. MEDDELAY ensures no hold time with respect to the Global Early and FastCLK buffers. Inputs with NODELAY may have a positive hold time with respect to all clock buffers, including the FastCLK buffers. For a description of each of these buffers, see "Global Nets and Buffers (XC4000EX only)" on page 43. Additional Input Latch for Fast Capture (XC4000EX only) The XC4000EX IOB has an additional optional latch on the input. This latch, as shown in Figure 17, is clocked by the output clock -- the clock used for the output flip-flop -- rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the IOB flip-flop or latch. To use this Fast Capture technique, drive the output clock pin (the Fast Capture latching signal) from the output of one of the Global Early or FastCLK buffers supplied in the XC4000EX. The second storage element should be clocked by a Global Low-Skew buffer, to synchronize the incoming data to the internal logic. (See Figure 18.) These special buffers are described in "Global Nets and Buffers (XC4000EX only)" on page 43. The Fast Capture latch is designed primarily for use with a Global Early buffer. For Fast Capture, a single clock signal is routed through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) The Fast Capture latch is clocked by the Global Early buffer, and the standard IOB flip-flop or latch is clocked by the Global Low-Skew buffer. This mode is the safest way to use the Fast Capture latch, because the clock buffers on both storage elements are driven by the same pad. There is no external skew between clock pads to create potential problems. Alternatively, a FastCLK buffer can be used to minimize the setup time of device inputs, if a positive hold time is acceptable. Use the FastCLK buffer to clock the Fast Capture latch, and a slower clock buffer to clock the standard IOB flip-flop or latch. Either the Global Early buffer or the Global Low-Skew buffer can be used for the second storage ele- ILDFFDX IPAD NODELAY When to Use Zero Hold with respect to Global LowSkew Buffer, Global Early Buffer, or FastCLK Buffer Zero Hold with respect to Global Early Buffer or FastCLK Buffer Short Setup, positive Hold time Q to internal logic Q to internal logic GF BUFGE CE G IPAD BUFGLS Table 12: XC4000EX IOB Input Delay Element Value full delay (default, no attribute added) MEDDELAY D ILDFFDX IPAD D GF IPAD BUFFCLK CE G NODELAY IPAD BUFGLS X6705 Figure 18: Examples Using XC4000EX Fast Capture Latch 4-26 June 1, 1996 (Version 1.02) ment, but whichever one is used should be the same clock as the related internal logic. Since the FastCLK pads are different from the Global Early and Global Low-Skew pads, care must be taken to ensure that skew external to the device does not create internal timing difficulties. To place the Fast Capture latch in a design, use one of the special library symbols, ILDFFDX or ILDFLDX. ILDFFDX is a transparent-Low Fast Capture latch followed by an active-High input flip-flop. ILDFLDX is a transparent-Low Fast Capture latch followed by a transparent-High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB. If a single BUFG output is used to drive both clock inputs, the software automatically runs the clock through both a Global Low-Skew buffer and a Global Early buffer, and clocks the Fast Capture latch appropriately. Figure 17 on page 25 also shows a two-tap delay on the input. By default, if the Fast Capture latch is used, the Xilinx software assumes a Global Early buffer is driving the clock, and selects MEDDELAY to ensure a zero hold time. This default can be overridden to remove the delay, if FastClk is used, by attaching a NODELAY attribute or property to the ILDFFD or ILDFLD latch. Select the desired delay based on the discussion in the previous subsection. IOB Output Signals Output signals can be optionally inverted within the IOB, and can pass directly to the pad or be stored in an edgetriggered flip-flop. The functionality of this flip-flop is shown in Table 13. An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB. The 4-mA maximum output current specification of many FPGAs often forces the user to add external buffers, which are especially cumbersome on bidirectional I/O lines. The XC4000E and XC4000EX devices solve many of these problems by providing a guaranteed output sink current of 12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. (XC4000L and XC4000XL outputs can sink up to 4 mA, and two adjacent XC4000L and XC4000XL outputs can sink up to 8 mA.) The XC4000E and XC4000EX FPGAs can thus directly drive buses on a printed circuit board. June 1, 1996 (Version 1.02) Table 13: Output Flip-Flop Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Legend: X __/ SR 0* 1* Z Clock X Clock Enable X T 0* D X Q SR X __/ X 0 0 1* X X 0* 0* 1 0* X D X X Q D Z Q Don't care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 3-state By default, the output pull-up structure is configured as a TTL-like totem-pole. The High driver is an n-channel pullup transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally configured as CMOS drivers, with p-channel pull-up transistors pulling to Vcc. This MakeBits option applies to all outputs on the device. It is not individually programmable. Outputs of low-voltage devices must be configured as CMOS at all times. They can drive the inputs of any 5-Volt device with TTL-compatible thresholds. Any XC4000-Series 5-Volt device with its outputs configured in TTL mode can drive the inputs of any typical 3.3Volt device. Supported destinations for XC4000-Series device outputs are shown in Table 14. Table 14: Supported Destinations for XC4000-Series Outputs XC4000-Series Outputs Destination 3.3 V, 5 V, 5 V, CMOS TTL CMOS Any typical device, Vcc = 3.3 V, some1 CMOS-threshold inputs Any device, Vcc = 5 V, TTL-threshold inputs Unreliable Any device, Vcc = 5 V, Data CMOS-threshold inputs 1. Only if destination device has 5-V tolerant inputs 4-27 XC4000 Series Field Programmable Gate Arrays OPAD OBUFT X6702 Figure 19: Open-Drain Output An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 19.) Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For XC4000EX devices, additional internal Power/ Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000EX devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000-Series devices have a feature called "Soft Startup," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 16 or Figure 17) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network. 4-28 GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to GSR. See Figure 2 on page 13 for details. Alternatively, GTS can be driven from any internal node. Output Multiplexer/2-Input Function Generator (XC4000EX only) As shown in Figure 17 on page 25, the output path in the XC4000EX IOB contains an additional multiplexer not available in the XC4000E IOB. The multiplexer can also be configured as a 2-input function generator, implementing a pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 17. When configured as a multiplexer, this feature allows two output signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package. When the MUX is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with either a FastCLK or Global Early buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a FastCLK buffer, as shown in Figure 20. The critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. (This value may not be achievable in XC4000XL devices.) As shown in Figure 17, the IOB input pins Out, Output Clock, and Clock Enable have different delays and different flexibilities regarding polarity. Additionally, Output Clock sources are more limited than the other inputs. Therefore, the Xilinx software does not move logic into the IOB function generators unless explicitly directed to do so. IPAD BUFFCLK F from internal logic OAND2 OPAD FAST X6698 Figure 20: Fast Pin-to-Pin Path in XC4000E June 1, 1996 (Version 1.02) D0 are independent, except that in the XC4000EX, the Fast Capture latch shares an IOB input with the output clock pin. OMUX2 O F Early Clock for IOBs (XC4000EX only) D1 OAND2 X6598 S0 X6599 Figure 21: Output AND and MUX Symbols in XC4000EX IOB The user can specify that the IOB function generator be used, by placing special library symbols beginning with the letter "O." For example, a 2-input AND-gate in the IOB function generator is called OAND2. Use the symbol input pin labelled "F" for the signal on the critical path. This signal is placed on the OK pin -- the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 21. Other IOB Options There are a number of other programmable options in the XC4000-Series IOB. Pull-up and Pull-down Resistors Programmable pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to Vcc. The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is 50 k - 100 k. This high value makes them unsuitable as wired-AND pull-up resistors. The pull-up resistors for most user-programmable IOBs are active during the configuration process. See Table 24 on page 78 for a list of pins with pull-ups active before and during configuration. After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Independent Clocks Separate clock signals are provided for the input and output flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating either falling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB June 1, 1996 (Version 1.02) Special early clocks are available for IOBs. These clocks are sourced by the same sources as the Global Low-Skew buffers, but are separately buffered. They have fewer loads and therefore less delay. The early clock can drive either the IOB output clock or the IOB input clock, or both. The early clock allows fast capture of input data, and fast clockto-output on output data. The Global Early buffers that drive these clocks are described in "Global Nets and Buffers (XC4000EX only)" on page 43. Fast Clock for IOBs (XC4000EX only) Very fast clocks driven by FastCLK buffers are also available for IOBs. These clocks are sourced by semi-dedicated pads--the pads can be used as general I/O if not used to drive FastCLK buffers. There are two FastCLK buffers on the left edge, and two on the right edge of the device. They provide the fastest method of reaching the IOB clock pins. The FastCLK buffer can drive either the IOB output clock or the IOB input clock, or both. These buffers allow the fastest possible setup times and clock-to-output times. The FastCLK buffers are described in "Global Nets and Buffers (XC4000EX only)" on page 43. Global Set/Reset As with the CLB registers, the Global Set/Reset signal (GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-controlled set/reset signal is available to the I/O flip-flops. The choice of set or clear applies to both the initial state of the flip-flop and the response to the Global Set/Reset pulse. See "Global Set/Reset" on page 13 for a description of how to use GSR. JTAG Support Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, permitting easy chip and board-level testing. More information is provided in "Boundary Scan" on page 50. Three-State Buffers A pair of 3-state buffers is associated with each CLB in the array. (See Figure 27 on page 34.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programmable pull-up resistors attached to these longlines help to implement a wide wired-AND function. 4-29 XC4000 Series Field Programmable Gate Arrays The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 15. WAND4, WAND8, and WAND16 are also available. See the XACT Libraries Guide for further information. Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. (See Figure 33 on page 39.) The T pin is internally tied to the I pin. Connect the input to the I pin and the output to the O pin. Connect the outputs of all the WAND1s together and attach a PULLUP symbol. The horizontal longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. Wired OR-AND The buffer can be configured as a Wired OR-AND. A High level on either input turns off the output. Use the WOR2AND library symbol, which is essentially an opendrain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the I0 and I1 pins and tie the output to the O pin. Tie the outputs of all the WOR2ANDs together and attach a PULLUP symbol. Special longlines running along the perimeter of the array can be used to wire-AND signals coming from nearby IOBs or from internal longlines. These longlines form the wide edge decoders discussed in "Wide Edge Decoders" on page 31. Three-State Buffer Examples Three-State Buffer Modes Figure 22 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs are High, the pull-up resistor(s) provide the High output. The 3-state buffers can be configured in three modes: * * * Standard 3-state buffer Wired-AND with input on the I pin Wired OR-AND Figure 23 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Standard 3-State Buffer Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 15. All three pins are used. Place the library element BUFT. Connect the input to the I pin and the output to the O pin. The T pin is an active-High 3-state (i.e. an active-Low enable). Tie the T pin to Ground to implement a standard buffer. Table 15: Three-State Buffer Functionality IN X IN Wired-AND with Input on the I Pin The buffer can be used as a Wired-AND. Use the WAND1 library symbol, which is essentially an open-drain buffer. Z=D D A D WAND1 A D B (D C T 1 0 P U L L +D ) (D +D ) D E F D C D B WAND1 OUT Z IN U P D E D D F W0R2AND W0R2AND X6465 Figure 22: Open-Drain Buffers Implement a Wired-AND Function Z = DA * A + D B * B + D C * C + D N * N ~100 k DA DB BUFT A DC BUFT B DN BUFT C BUFT N X6466 "Weak Keeper" Figure 23: 3-State Buffers Implement a Multiplexer 4-30 June 1, 1996 (Version 1.02) Wide Edge Decoders INTERCONNECT Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000-Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. IOB IOB .I1 A .I1 C B ( An XC4000-Series FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the IOB I1 signals on that edge plus one local interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 24. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to a product term in typical PAL devices. Each of these wired-AND gates is capable of accepting up to 42 inputs on the XC4005E and 72 on the XC4013E. There are up to 96 inputs for each decoder on the XC4028EX and 132 on the XC4052EX. The decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. The decoder outputs can drive CLB inputs, so they can be combined with other logic to form a PAL-like AND/OR structure. The decoder outputs can also be routed directly to the chip outputs. For fastest speed, the output should be on the same chip edge as the decoder. Very large PALs can be emulated by ORing the decoder outputs in a CLB. This decoding feature covers what has long been considered a weakness of older FPGAs. Users often resorted to external PALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000-Series device can implement these functions fast and efficiently. To use the wide edge decoders, place one or more of the WAND library symbols (WAND1, WAND4, WAND8, WAND16). Attach a DECODE attribute or property to each WAND symbol. Tie the outputs together and attach a PULLUP symbol. Location attributes or properties such as L (left edge) or TR (right half of top edge) should also be used to ensure the correct placement of the decoder inputs. C) ..... (A * B * C) ..... (A * B * C) ..... (A * B * C) ..... X2627 Figure 24: XC4000-Series Edge Decoding Example On-Chip Oscillator XC4000-Series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK in Master configuration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 and 10 MHz. (The oscillator operates more slowly at lower voltages. The output frequency may be reduced by as much as 10% for low-voltage devices.) The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code (see Figure 25). The oscillator is automatically disabled after configuration if the OSC4 symbol is not used in the design. OSC4 F8M F500K F16K F490 F15 X6703 Figure 25: XC4000-Series Oscillator Symbol June 1, 1996 (Version 1.02) 4-31 XC4000 Series Field Programmable Gate Arrays Programmable Interconnect CLB Routing Connections All internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efficient automated routing. A high-level diagram of the routing resources associated with one CLB is shown in Figure 26. The shaded arrows represent routing present only in XC4000EX devices. The XC4000E and XC4000EX share a basic interconnect structure. XC4000EX devices, however, have additional routing not available in the XC4000E. The extra routing resources allow high utilization in high-capacity devices. All XC4000EX-specific routing resources are clearly identified throughout this section. Any resources not identified as XC4000EX-specific are present in all XC4000-Series devices. This section describes the varied routing resources available in XC4000-Series devices. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design. Interconnect Overview There are several types of interconnect. * * * CLB routing is associated with each row and column of the CLB array. IOB routing forms a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the internal logic blocks. Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals. Five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (XC4000EX only), and longlines. In the XC4000EX, direct connects allow fast data flow between adjacent CLBs, and between IOBs and CLBs. Extra routing is included in the IOB pad ring. The XC4000EX also includes a ring of octal interconnect lines near the IOBs to improve pin-swapping and routing to locked pins. Table 16 shows how much routing of each type is available in XC4000E and XC4000EX CLB arrays. Clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the XC4000EX. Smaller XC4000E designs, typically requiring significantly less interconnect, do not require the additional routing. Figure 27 on page 34 is a detailed diagram of both the XC4000E and the XC4000EX CLB, with associated routing. The shaded square is the programmable switch matrix, present in both the XC4000E and the XC4000EX. The L-shaped shaded area is present only in XC4000EX devices. As shown in the figure, the XC4000EX block is essentially an XC4000E block with additional routing. CLB inputs and outputs are distributed on all four sides, providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. Table 16: Routing per CLB in XC4000-Series Devices Singles Doubles Quads Longlines Direct Connects Globals Carry Logic Total XC4000E XC4000EX Vertical Horizontal Vertical Horizontal 8 8 8 8 4 4 4 4 0 0 12 12 6 6 10 6 0 0 2 2 4 2 24 0 0 18 8 1 45 0 0 32 XC4000E devices include two types of global buffers, while XC4000EX devices have three different types. These global buffers have different properties, and are intended for different purposes. They are discussed in detail later in this section. 4-32 June 1, 1996 (Version 1.02) Quad Single Double Long CLB Direct Connect Long Quad Long Global Clock Long Double Single Global Clock Carry Direct Chain Connect x5994 Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only) June 1, 1996 (Version 1.02) 4-33 XC4000 Series Field Programmable Gate Arrays QUAD DOUBLE SINGLE DOUBLE LONG F4 C4 G4 YQ DIRECT Y G1 C1 F1 CLB G3 FEEDBACK C3 F3 K X XQ F2 C2 G2 LONG LO U AD G D LO G N Q LO G L U BL E O SI U N G LE G LO D O N BA N G BL E D IR LO BA L EC T FE ED BA C K Common to XC4000E and XC4000EX XC4000EX only Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB 4-34 June 1, 1996 (Version 1.02) Single-Length Lines e ou D gl in S bl es e bl ou D Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switching matrices that are located in every row and a column of CLBs. Double Singles Six Pass Transistors Per Switch Matrix Interconnect Point Double X6600 Figure 28: Programmable Switch Matrix (PSM) Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to establish connections between the lines (see Figure 28). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix. CLB Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 29. Routing connectivity is shown in Figure 27. Single-length lines incur a delay whenever they go through a switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one. Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a switch matrix. Double-length lines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix at every other row or column of CLBs (see Figure 29). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Double-length lines are connected by way of the programmable switch matrices. Routing connectivity is shown in Figure 27. CLB CLB Doubles PSM Singles PSM Doubles CLB CLB PSM CLB CLB PSM CLB CLB X6601 Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs) June 1, 1996 (Version 1.02) 4-35 XC4000 Series Field Programmable Gate Arrays Quad Lines (XC4000EX only) XC4000EX devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected via buffered switch matrices (shown as diamonds in Figure 27 on page 34). Quad lines run past four CLBs before entering a buffered switch matrix. They are grouped in fours, with the buffered switch matrices staggered, so that each line goes through a buffered switch matrix at every fourth CLB location in that row or column. (See Figure 30.) The buffered switch matrixes have four pins, one on each edge. All of the pins are bidirectional. Any pin can drive any or all of the other pins. Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch matrix shown in Figure 28, with the addition of a programmable buffer. There can be up to two independent inputs and up to two independent outputs. Only one of the independent inputs can be buffered. The place and route software automatically uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. A heavily loaded signal is typically buffered, while a lightly loaded one is not. One scenario is to alternate buffers and pass transistors. This allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. Due to the buffered switch matrices, quad lines are very fast. They provide the fastest available method of routing heavily loaded signals for long distances across the device. CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB X6602 Figure 30: Quad Lines (XC4000EX only) 4-36 June 1, 1996 (Version 1.02) Longlines Direct Interconnect (XC4000EX only) Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000EX devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fanout nets. The XC4000EX offers two direct, efficient and fast connections between adjacent CLBs. These nets facilitate a data flow from the left to the right side of the device, or from the top to the bottom, as shown in Figure 31. Signals routed on the direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources. IOB CLB CLB IOB ~ ~ ~ ~ ~ ~ ~ ~ IOB IOB CLB IOB IOB IOB IOB IOB ~ ~ ~ ~ CLB CLB IOB IOB IOB IOB IOB IOB IOB June 1, 1996 (Version 1.02) CLB ~ ~ ~ ~ Routing connectivity of the longlines is shown in Figure 27 on page 34. IOB IOB Each XC4000EX longline not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. Due to the buffering, XC4000EX longline performance does not deteriorate with the larger array sizes. If the longline is split, the resulting partial longlines are independent. IOB Each XC4000E longline has a programmable splitter switch at its center, as does each XC4000EX longline driven by TBUFs. This switch can separate the line into two independent routing channels, each running half the width or height of the array. The place and route software uses direct interconnect whenever possible, to maximize routing resources and minimize interconnect delays. IOB Each horizontal longline driven by TBUFs has either two (XC4000E) or eight (XC4000EX) pull-up resistors. To activate these resistors, attach a PULLUP symbol to the longline net. The software automatically activates the appropriate number of pull-ups. There is also a weak keeper at each end of these two horizontal longlines. This circuit prevents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. The direct interconnect is also present between CLBs and adjacent IOBs. Each IOB on the left and top device edges has a direct path to the nearest CLB. Each CLB on the right and bottom edges of the array has a direct path to the nearest two IOBs, since there are two IOBs for each row or column of CLBs. ~ ~ ~ ~ Two horizontal longlines per CLB can be driven by 3-state or open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide multiplexers, or wired-AND functions. (See "Three-State Buffers" on page 29 for more details.) X6603 Figure 31: XC4000EX Direct Interconnect 4-37 XC4000 Series Field Programmable Gate Arrays I/O Routing XC4000-Series devices have additional routing around the IOB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines spanning two CLBs (four IOBs), and four longlines. Global lines and Wide Edge Decoder lines are provided. XC4000EX devices also include eight octal lines. Figure 33 is a detailed diagram of the XC4000E and XC4000EX VersaRing. The area shown includes two IOBs. There are two IOBs per CLB row or column, therefore this diagram corresponds to the CLB routing diagram shown in Figure 27 on page 34. The shaded areas represent routing and routing connections present only in XC4000EX devices. A high-level diagram of the VersaRing is shown in Figure 32. The shaded arrows represent routing present only in XC4000EX devices. IOB WED Quad WED Single Double INTERCONNECT Long Direct Connect Long IOB WED Direct Connect Edge Double Long Global Octal Decode Clock X5995 Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000EX only) 4-38 June 1, 1996 (Version 1.02) QUAD T O DOUBLE SINGLE C L B DOUBLE LONG DECODER IOB I1 IK OK DECODER T I2 CE O DIRECT A R R A Y DECODER IOB O T OK CE IK I1 I2 LONG E L TA C O L BA LO G G E BL U O E G OD ED EC D N LO D Common to XC4000E and XC4000EX XC4000EX only Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series IOB (Left Edge) June 1, 1996 (Version 1.02) 4-39 XC4000 Series Field Programmable Gate Arrays Octal I/O Routing (XC4000EX only) Between the XC4000EX CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and fixed pinout flexibility. (See Figure 34.) These routing tracks are called octals, because they can be broken every eight CLBs (sixteen IOBs) by a programmable buffer that also functions as a splitter switch. The buffers are staggered, so each line goes through a buffer at every eighth CLB location around the device edge. The octal lines bend around the corners of the device. The lines cross at the corners in such a way that the segment IOB most recently buffered before the turn has the farthest distance to travel before the next buffer, as shown in Figure 34. IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and double-length lines, quads, and longlines within the CLB array. Segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device. IOB IOB IOB Segment with nearest buffer connects to segment with furthest buffer IOB IOB IOB IOB X6607 Figure 34: XC4000EX Octal I/O Routing 4-40 June 1, 1996 (Version 1.02) Global Nets and Buffers Both the XC4000E and the XC4000EX have dedicated global networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in detail in the following sections. The text descriptions and diagrams are summarized in Table 17. The table shows which CLB and IOB clock pins can be sourced by which global buffers. In both XC4000E and XC4000EX devices, placement of a library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing requirements of the design. The detailed information in these sections is included only for reference. Global Nets and Buffers (XC4000E only) Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of two types of global buffers. The clock pins of every CLB and IOB can also be sourced from local interconnect. Two different types of clock buffers are available in the XC4000E: * * Primary Global Buffers (BUFGP) Secondary Global Buffers (BUFGS) Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semidedicated pads. The Secondary Global buffers can be sourced by either semi-dedicated pads or internal nets. Each CLB column has four dedicated vertical Global lines. Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 35. Each corner of the device has one Primary buffer and one Secondary buffer. IOBs along the left and right edges have four vertical global longlines. Top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. A global buffer should be specified for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=L attribute or property to a BUFGS symbol to direct that a buffer be placed in one of the two Secondary Global buffers on the left edge of the device, or a LOC=BL to indicate the Secondary Global buffer on the bottom edge of the device, on the left. Table 17: Clock Pin Access XC4000E All CLBs in Quadrant All CLBs in Device IOBs on Adjacent Vertical Half Edge IOBs on Adjacent Vertical Full Edge IOBs on Adjacent Horizontal Half Edge (Direct) IOBs on Adjacent Horizontal Half Edge (through CLB globals) IOBs on Adjacent Horizontal Full Edge (through CLB globals) BUFGP BUFGS BUFGLS XC4000EX L&R T&B BUFGE BUFGE BUFFCL K Local Interconnect L = Left, R = Right, T = Top, B = Bottom June 1, 1996 (Version 1.02) 4-41 XC4000 Series Field Programmable Gate Arrays IOB locals locals locals BUFGS IOB locals IOB IOB BUFGP PGCK1 SGCK4 PGCK4 SGCK1 4 4 BUFGS BUFGP 4 locals 4 locals CLB CLB IOB IOB locals Any BUFGS X4 locals X4 Any BUFGS X4 One BUFGP per Global Line IOB locals X4 locals One BUFGP per Global Line CLB locals CLB IOB locals BUFGP BUFGS SGCK3 IOB IOB IOB PGCK3 locals locals locals BUFGP locals PGCK2 SGCK2 BUFGS IOB X6604 Figure 35: XC4000E Global Net Distribution IOB BUFGLS GCK1 IOB IOB IOB BUFGLS GCK8 GCK7 BUFFCLK CLB X4 FCLK1 BUFGLS 8 locals locals BUFGE locals locals BUFGLS BUFFCLK X8 8 locals 8 locals 8 CLB CLOCKS (PER COLUMN) CLB CLOCKS (PER COLUMN) IOB IOB CLOCKS locals locals locals IOB CLOCKS IOB locals locals 8 locals 8 BUFGLS locals BUFGLS 8 8 BUFGLS X8 X8 BUFFCLK FCLK3 X8 BUFFCLK locals CLB locals locals CLB locals X4 IOB 8 4 BUFGLS 8 FCLK2 BUFGE GCK2 IOB CLOCKS CLB CLOCKS (PER COLUMN) CLB CLOCKS (PER COLUMN) 8 BUFGE FCLK4 8 BUFGLS 8 IOB CLOCKS locals X8 BUFGLS 4 IOB BUFGLS BUFGE CLB X8 locals BUFGLS 8 locals BUFGLS BUFGE BUFGLS BUFGE GCK4 GCK3 BUFGLS GCK6 BUFGE BUFGE IOB IOB IOB IOB BUFGLS GCK5 X6694 Figure 36: XC4000EX Global Net Distribution 4-42 June 1, 1996 (Version 1.02) Global Nets and Buffers (XC4000EX only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The global lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. Each half-column global line has its own buffered multiplexer, as shown in Figure 36. The top and bottom global lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. The top and bottom halves of the global lines must be separately driven -- although they can be driven by the same global buffer. The eight global lines in each CLB column can be driven by either of two types of global buffers. They can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. Consequently, the number of different clocks that can be used simultaneously in an XC4000EX device is very large. There are four global lines feeding the IOBs at the left edge of the device. IOBs along the right edge have eight global lines. There is a single global line along the top and bottom edges with access to the IOBs. All IOB global lines are broken at the center. They cannot be connected across the center of the device, as this connection might introduce unacceptable skew. IOB global lines can be driven from any of three types of global buffers, or from local interconnect. Alternatively, top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. Three different types of clock buffers are available in the XC4000EX: * * * Global Low-Skew Buffers (BUFGLS) Global Early Buffers (BUFGE) FastCLK Buffers (BUFFCLK) Global Low-Skew Buffers are the standard clock buffers. They should be used for most internal clocking, whenever a large portion of the device must be driven. Global Early Buffers are designed to provide a faster clock access, but CLB access is limited to one-fourth of the device. They also facilitate a faster I/O interface. FastCLK buffers are specifically designed to provide the fastest possible I/O clock. They have only the standard input access to CLBs, through local interconnect. Figure 36 is a conceptual diagram of the global net structure in the XC4000EX. Global Early buffers and Global Low-Skew buffers share a single pad. Therefore, the same IPAD symbol can drive one buffer of each type, in parallel. This configuration is particularly useful when using the Fast Capture latches, as described in "IOB Input Signals" on page 24. Paired Global June 1, 1996 (Version 1.02) Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals. Choosing an XC4000EX Clock Buffer The clocking structure of the XC4000EX provides a large variety of features. However, it can be simple to use, without understanding all the details. The software automatically handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. In fact, if a buffer symbol called BUFG is placed, rather than a specific type of buffer, the software even chooses the buffer most appropriate for the design. The detailed information in this section is provided for those users who want a finer level of control over their designs. If fine control is desired, use the following summary and Table 17 on page 41 to choose an appropriate clock buffer. * * * * The simplest thing to do is to use a Global Low-Skew buffer. If a faster clock path is needed, try a BUFG. The software will first try to use a Global Low-Skew Buffer. If timing requirements are not met, a faster buffer will automatically be used. If a single quadrant of the chip is sufficient for the clocked logic, and the timing requires a faster clock than the Global Low-Skew buffer, use a Global Early buffer. In special cases, where both external and internal timing have been carefully studied, a FastCLK buffer can be used, for the fastest possible I/O clock path. Global Low-Skew Buffers Each corner of the XC4000EX device has two Global LowSkew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any of the four vertical lines accessing the IOBs on the left edge of the device, and any of the eight vertical lines accessing the IOBs on the right edge of the device. (See Figure 37 on page 44.) IOBs at the top and bottom edges of the device are accessed through the vertical Global lines in the CLB array, as in the XC4000E. Any Global Low-Skew buffer can, therefore, access every IOB and CLB in the device. The Global Low-Skew buffers can be driven by either semidedicated pads or internal logic. To use a Global Low-Skew buffer, place a BUFGLS element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGLS be placed in one of the two Global Low-Skew buffers on the top edge of the device, or a LOC=TR to indicate the Global Low-Skew buffer on the top edge of the device, on the right. 4-43 XC4000 Series Field Programmable Gate Arrays 8 7 IOB 8 IOB 1 6 I O B 2 IOB 1 6 CLB I O B I O B CLB CLB I O B CLB CLB I O B I O B CLB CLB I O B IOB IOB IOB IOB CLB I O B 7 IOB 3 5 2 3 4 5 4 X6751 X6753 Figure 37: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Figure 38: Left and Right BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant or Edge (GCK1 is shown. GCK2, GCK3 and GCK4 are similar.) Global Early Buffers Each corner of the XC4000EX device has two Global Early buffers. The primary purpose of the Global Early buffers is to provide an earlier clock access than the potentially heavily-loaded Global Low-Skew buffers. A clock source applied to both buffers will result in the Global Early clock edge occurring several nanoseconds earlier than the Global Low-Skew buffer clock edge, due to the lighter loading. Global Early buffers also facilitate the fast capture of device inputs, using the Fast Capture latches described in "IOB Input Signals" on page 24. For Fast Capture, take a single clock signal, and route it through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) Use the Global Early buffer to clock the Fast Capture latch, and the Global Low-Skew buffer to clock the normal input flip-flop or latch, as shown in Figure 18 on page 26. The Global Early buffers can also be used to provide a fast Clock-to-Out on device output pins. However, an early clock in the output flip-flop IOB must be taken into consideration when calculating the internal clock speed for the design. The left-side Global Early buffers can each drive two of the four vertical lines accessing the IOBs on the entire left edge of the device. The right-side Global Early buffers can each drive two of the eight vertical lines accessing the IOBs on the entire right edge of the device. (See Figure 38.) Each left and right Global Early buffer can also drive half of the IOBs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the Global Early buffers. The top and bottom Global Early buffers can drive half of the IOBs along either the left or right edge of the device, as shown in Figure 39. They can only access the top and bottom IOBs via the CLB global lines. 8 4-44 IOB 1 The Global Early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. Refer to Figure 38, Figure 39, and Figure 36 on page 42 while reading the following explanation. Each Global Early buffer can access the eight vertical Global lines for all CLBs in the quadrant. Therefore, only onefourth of the CLB clock pins can be accessed. This restriction is in large part responsible for the faster speed of the buffers, relative to the Global Low-Skew buffers. 7 IOB 6 I O B CLB CLB I O B I O B CLB CLB I O B IOB IOB 2 3 5 4 X6747 Figure 39: Top and Bottom BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant (GCK8 is shown. GCK3, GCK4 and GCK7 are similar.) June 1, 1996 (Version 1.02) The Global Early buffers can be driven by either semi-dedicated pads or internal logic. They share pads with the Global Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGE be placed in one of the two Global Early buffers on the top edge of the device, or a LOC=TR to indicate the Global Early buffer on the top edge of the device, on the right. IOB IOB 1 I O B CLB CLB I O B 4 2 I O B CLB CLB I O B 3 IOB IOB FastCLK Buffers The fastest way to bring a clock into the XC4000EX device is through a FastCLK buffer. Two FastCLK buffers are present on the left edge, and two on the right edge, of the XC4000EX die. There are no FastCLK buffers on the top or bottom edges. One purpose of the FastCLK buffers is to create a very fast pin-to-pin path by using the IOB 2-input function generator in conjunction with the FastCLK. Drive the F input of the IOB function generator with the FastCLK buffer output, as described in "IOB Output Signals" on page 27. Alternatively, a FastCLK buffer can be used to minimize the setup time of device inputs, if a positive hold time is acceptable. Use the FastCLK buffer to clock the Fast Capture latch, and a slower clock buffer to clock the standard IOB flip-flop or latch. Either the Global Early buffer or the Global Low-Skew buffer can be used for the second storage element, but whichever one is used should be the same clock as the related internal logic. Since the FastCLK pads are different from the Global Early and Global Low-Skew pads, care must be taken to ensure that skew external to the device does not create internal timing difficulties. The FastCLK buffers can also be used to provide a fast Clock-to-Out on device output pins. However, a fast clock in the output flip-flop IOB must be taken into consideration when calculating the internal clock speed for the design. June 1, 1996 (Version 1.02) X6745 Figure 40: Each BUFFCLK Can Drive Any or All Clock Inputs in Same Half-Edge (FCLK1 is shown. FCLK2, FCLK3 and FCLK4 are similar.) The FastCLK buffers are limited to accessing IOBs on onehalf of the die edge only, as shown in Figure 40 and Figure 36 on page 42. They can each drive two of the four vertical lines accessing the IOBs on the left edge of the device, or two of the eight vertical lines accessing the IOBs on the right edge of the device. They can only access the CLB array through single- and double-length lines. The FastCLK buffers must be driven by the semi-dedicated IOBs. They are not accessible from internal nets. Other than the FastCLK feature, these IOBs are identical to all other IOBs. To use a FastCLK buffer, place a BUFFCLK element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=LB attribute or property to direct that a BUFFCLK be placed on the left edge of the device at the bottom, or use LOC=L to indicate either of the buffers on the left edge. The input to the BUFFCLK symbol must be driven by a input pad symbol, such as IPAD, or by an input flip-flop or latch, such as INFF, ILD, ILDFFDX, or ILDFLDX. 4-45 XC4000 Series Field Programmable Gate Arrays Power Distribution Pin Descriptions Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 41. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. There are three types of pins in the XC4000-Series devices: This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 F capacitor connected near the Vcc and Ground pins of the package will provide adequate decoupling. Output buffers capable of driving/sinking the specified 12 mA (XC4000E) or 24 mA (XC4000EX) loads under specified worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical. GND * * * Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins. Before and during configuration, all outputs not used for the configuration process are 3-stated with a 50 k - 100 k pull-up resistor. After configuration, if an IOB is unused it is configured as an input with a 50 k - 100 k pull-up resistor. XC4000-Series devices have no dedicated Reset input. Any user I/O can be configured to drive the Global Set/ Reset net, GSR. See "Global Set/Reset" on page 13 for more information on GSR. XC4000-Series devices have no Powerdown control input, as the XC3000 and XC2000 families do. The XC3000/ XC2000 Powerdown control also 3-stated all of the device I/ O pins. For XC4000-Series devices, use the global 3-state net, GTS, instead. This net 3-states all outputs, but does not place the device in low-power mode. See "IOB Output Signals" on page 27 for more information on GTS. Device pins for XC4000-Series devices are described in Table 18. Pin functions during configuration for each of the seven configuration modes are summarized in Table 24 on page 78, in the "Configuration Timing" section. Ground and Vcc Ring for I/O Drivers Vcc Vcc Logic Power Grid GND X5422 Figure 41: XC4000-Series Power Distribution 4-46 June 1, 1996 (Version 1.02) Table 18: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Pin Description Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Eight or more (depending on package type) connections to Ground. All must be conGND I I nected. During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and CCLK I or O I can be selected as the Readback Clock. There is no CCLK High time restriction on XC4000-Series devices, except during Readback. See "Violating the Maximum High and Low Time Specification for the Readback Clock" on page 65 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE can be configured to delay the global logic initialization and the enabling of outDONE I/O O puts. The optional pull-up resistor is selected as an option in MakeBits, the XACTstep program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it PROGRAM I I goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. User I/O Pins That Can Have Special Functions During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in AsynRDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable I/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for XC4000EX) is preceded by a rising edge on RCLK, a redundant output signal. RCLK O I/O RCLK is useful for clocked PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. As Mode inputs, these pins are sampled after INIT goes High to determine the configuration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1 can be used as a 3-state output. These three pins have no associated input or output registers. I (M0), During configuration, these pins have weak pull-up resistors. For the most popular conM0, M1, M2 I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down resistors. A pull-down resistor value of 4.7 k is recommended. These pins can only be used as inputs or outputs when called out by special schematic definitions. To use these pins, place the library components MD0, MD1, and MD2 instead of the usual pad symbols. Input or output buffers must still be used. VCC I June 1, 1996 (Version 1.02) I 4-47 XC4000 Series Field Programmable Gate Arrays Table 18: Pin Descriptions (Continued) Pin Name I/O I/O During After Config. Config. TDO O O TDI, TCK, TMS I I/O or I (JTAG) HDC O I/O LDC O I/O INIT I/O I/O PGCK1 PGCK4 (XC4000E only) Weak Pull-up I or I/O SGCK1 SGCK4 (XC4000E only) Weak Pull-up I or I/O GCK1 GCK8 (XC4000EX only) Weak Pull-up I or I/O FCLK1 FCLK4 (XC4000EX only) Weak Pull-up I or I/O 4-48 Pin Description If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used. If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O. In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O. The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins. Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins. Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Global Early buffer. Each pair of global buffers can also be driven from internal logic, but must share an input signal. If not used to drive a global buffer, any of these pins is a user-programmable I/O. Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol is automatically placed on one of these pins. Four FCLK inputs can each drive a FastCLK buffer. The FastCLK buffers cannot be driven from internal logic. If not used to drive a global buffer, any of these pins is a userprogrammable I/O. Any input pad symbol connected directly to the input of a BUFFCLK symbol is automatically placed on one of these pins. June 1, 1996 (Version 1.02) Table 18: Pin Descriptions (Continued) Pin Name I/O I/O During After Config. Config. Pin Description These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low CS0, CS1, on Read Strobe (RS) changes D7 into a status output -- High if Ready, Low if Busy -- I I/O WS, RS and drives D0 - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. During Master Parallel configuration, these 18 output pins address the configuration A0 - A17 O I/O EPROM. After configuration, they are user-programmable I/O pins. A18 - A21 During Master Parallel configuration with an XC4000EX master, these 4 output pins add (XC4000EX O I/O 4 more bits to address the configuration EPROM. After configuration, they are user-proonly) grammable I/O pins. During Master Parallel and Peripheral configuration, these eight input pins receive conD0 - D7 I I/O figuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DOUT O I/O DIN input. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor (50 k - 100 k) that defines the logic level as High. June 1, 1996 (Version 1.02) 4-49 XC4000 Series Field Programmable Gate Arrays Boundary Scan Data Registers The `bed of nails' has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan configuration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this section. By exercising these input signals, the user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note XAPP 017: "Boundary Scan in XC4000 Devices." Figure 42 shows a simplified block diagram of the XC4000E Input/Output Block with boundary scan implemented. XC4000EX boundary scan logic is identical. Figure 43 on page 52 is a diagram of the XC4000-Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. XC4000-Series devices can also be configured through the boundary scan logic. See "Configuration Through the Boundary Scan Pins" on page 64. 4-50 The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE). Instruction Set The XC4000-Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 19. Table 19: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 Test TDO Source Selected EXTEST DR SAMPLE/ DR PRELOAD USER 1 BSCAN. TDO1 USER 2 BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved -- BYPASS Bypass Register I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled -- -- June 1, 1996 (Version 1.02) EXTEST TS INV M SLEW RATE PULL DOWN PULL UP TS/OE 3-State TS Boundary Scan VCC TS - capture TS - update OUTPUT INVERT OUTPUT M sd D Ouput Data O Q EC M INVERT PAD M Ouput Clock OK rd M OUT SEL S/R M Clock Enable Boundary Scan O - capture Q - capture O - update M I - capture Boundary Scan Input Data 1 I1 I - update M M sd Q D M M Input Data 2 I2 EC DELAY M INVERT QL M FLIP-FLOP/LATCH Input Clock IK rd M S/R INPUT GLOBAL S/R X5792 Figure 42: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown). XC4000EX Boundary Scan Logic is Identical. June 1, 1996 (Version 1.02) 4-51 XC4000 Series Field Programmable Gate Arrays DATA IN 1 0 sd D Q D Q LE 1 0 IOB.Q IOB.T 0 1 0 IOB IOB IOB IOB sd D Q D Q 1 LE IOB IOB IOB IOB IOB 1 sd D Q D Q 0 LE IOB IOB IOB IOB 1 IOB.I 0 1 IOB IOB IOB IOB IOB IOB BYPASS REGISTER 0 sd D Q D Q LE 1 0 IOB.Q IOB.T 0 M TDO U X INSTRUCTION REGISTER TDI 1 0 sd D Q D Q 1 LE M U TDO X TDI INSTRUCTION REGISTER 1 BYPASS REGISTER IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB 0 sd D Q D Q LE 1 IOB.I 0 1 0 sd D Q D Q LE 0 1 IOB.O DATAOUT IOB IOB IOB IOB IOB SHIFT/ CAPTURE UPDATE EXTEST CLOCK DATA REGISTER X1523 Figure 43: XC4000-Series Boundary Scan Logic 4-52 June 1, 1996 (Version 1.02) Bit Sequence The bit sequence within each IOB is: In, Out, 3-State. The input-only M0 and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the outputonly M1 pin contributes all three bits. The first two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 44. The device-specific pinout tables for the XC4000 Series include the boundary scan locations for each IOB pin. BSDL (Boundary Scan Description Language) files for XC4000-Series devices are available on the Xilinx BBS. Including Boundary Scan in a Schematic If boundary scan is only to be used during configuration, no special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after configuration. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK. Avoiding Inadvertent Boundary Scan Activation If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process. To prevent activation of boundary scan during configuration, do either of the following: * * TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Low--don't toggle this clock input. For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017.001, "Boundary Scan in XC4000E Devices." To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 45. Optional Bit 0 ( TDO end) Bit 1 Bit 2 TDO.T TDO.O To User Logic IBUF BSCAN Top-edge IOBs (Right to Left) TDI TDI Left-edge IOBs (Top to Bottom) TMS TMS MD1.T MD1.O MD1.I MD0.I MD2.I TCK TCK IDLE TDO1 SEL1 TDO2 SEL2 From User Logic TDO TDO DRCK To User Logic X2675 Bottom-edge IOBs (Left to Right) Figure 45: Boundary Scan Schematic Example Right-edge IOBs (Bottom to Top) (TDI end) B SCANT.UPD X6075 Figure 44: Boundary Scan Bit Sequence June 1, 1996 (Version 1.02) 4-53 XC4000 Series Field Programmable Gate Arrays Configuration Table 20: Configuration Modes Configuration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC4000-Series devices use several hundred bits of configuration data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format. Mode Master Serial Slave Serial Master Parallel Up M2 0 1 1 M1 0 1 0 M0 0 1 0 CCLK output input output Master Parallel Down 1 1 0 output Peripheral Synchronous* Peripheral Asynchronous Express (XC4000EX only) Reserved 0 1 1 input Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide 1 0 1 output Byte-Wide 0 1 0 input Byte-Wide 0 0 1 -- -- Special Purpose Pins Three configuration mode pins (M2, M1, M0) are sampled prior to configuration to determine the configuration mode. After configuration, these pins can be used as auxiliary connections. M2 and M0 can be used as inputs, and M1 can be used as an output. The XACTstep development system does not use these resources unless they are explicitly specified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol. In XC4000-Series devices, the mode pins have weak pullup resistors during configuration. With all three mode pins High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) After configuration, these pins can individually have weak pull-up or pull-down resistors, as specified in the design. A pull-down resistor value of 4.7 k is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired. Configuration Modes XC4000E devices have six configuration modes. XC4000EX devices have the same six modes, plus an additional configuration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel configuration of the high-capacity XC4000EX devices. The coding for mode selection is shown in Table 20. 4-54 Note: * Peripheral Synchronous can be considered bytewide Slave Parallel A detailed description of each configuration mode, with timing information, is included later in this data sheet. During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during configuration are shown in Table 24 on page 78. Master Modes The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the configuration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, for compatibility with different microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the configuration data in serial form from a Xilinx serial-configuration PROM. CCLK speed is selectable as either 1 MHz (default) or 8 MHz (up to 10% lower for low-voltage devices). Configuration always starts at the default slow frequency, then can switch to the higher frequency during the first frame. Frequency tolerance is -50% to +25%. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the syn- June 1, 1996 (Version 1.02) chronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode In Slave Serial mode, the FPGA receives serial configuration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously. Serial Daisy Chain Multiple devices with different configurations can be connected together in a "daisy chain," and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 55 on page 68. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the length count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last configuration bit is received. Figure 49 on page 61 shows the startup timing for an XC4000-Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The MakePROM program must be used to combine the bitstreams for a daisychained configuration. CCLK pulses until it reaches its finish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really finish its configuration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC4000Series device, not reaching F means that readback cannot be initiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the finish point F is reached. Timing is controlled using MakeBits options. XC3000 Master with an XC4000-Series Slave Some designers want to use an inexpensive lead device in peripheral mode and have the more precious I/O pins of the XC4000-Series devices all available for user I/O. Figure 46 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be configured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC4000-Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse. Express Mode (XC4000EX only) Express mode is similar to Slave Serial mode, except the data is presented in parallel format, and is clocked into the target device a byte at a time rather than a bit at a time. The data is loaded in parallel into eight different columns: it is not internally serialized. Eight bits of configuration data are loaded with every CCLK cycle, therefore this configuration Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, and XC4000 Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. The lead device must belong to the highest family in the chain. If the chain contains XC4000-Series devices, the master normally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 49 on page 61. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 49. The master device then generates additional June 1, 1996 (Version 1.02) OE/T Reset 0 0 1 0 1 1 0 1 0 1 . etc . . . Output Connected to CCLK Active Low Output Active High Output X5223 Figure 46: CCLK Generation for XC3000 Master Driving an XC4000-Series Slave 4-55 XC4000 Series Field Programmable Gate Arrays mode runs at eight times the data rate of the other six modes. A length count is not used in Express mode. Express mode must be specified as an option to the MakeBits program, which generates the bitstream. The Express mode bitstream is not compatible with the other six configuration modes. Multiple slave devices with identical configurations can be wired with parallel D0-D7 inputs. In this way, multiple devices can be configured simultaneously. Pseudo Daisy Chain Multiple devices with different configurations can be connected together in a pseudo daisy chain, provided that all of the devices are in Express mode. A single combined bitstream is used to configure the chain of Express mode devices, but the input data bus must drive D0-D7 of each device. Tie High the CS1 pin of the first device to be configured. Connect the DOUT pin of each FPGA to the CS1 pin of the next device in the chain. The D0-D7 inputs are wired to each device in parallel. The DONE pins are wired together, with one or more internal DONE pull-ups activated. Alternatively, a 4.7 k external resistor can be used, if desired. (See Figure 63 on page 76.) The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All XC4000EX devices in Express mode are synchronized to the DONE pin. User I/O for each device become active after the DONE pin for that device goes High. (The exact timing is determined by MakeBits options.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device in the chain has completed its configuration cycle. Because only XC4000EX and XC5200 devices support Express mode, only these devices can be used to form an Express mode daisy chain. XC5200 devices used in a combined daisy chain with XC4000EX devices should be configured as synchronized to DONE (MakeBits option CCLK_SYNC or UCLK_SYNC), and their DONE pins wired together with those of the XC4000EX devices. Setting CCLK Frequency For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz (up to 10% lower for lowvoltage devices). In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz (up to 10% lower for low-voltage devices). The frequency is selected by an option when running MakeBits, the bitstream generation software tool. If an XC4000-Series Master is driving an XC3000- or XC2000family slave, slow CCLK mode must be used. Slow mode is the default. 4-56 Data Stream Format The data stream ("bitstream") format is identical for all configuration modes, with the exception of Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream formats are shown in Table 21. Express mode data is shown with D0 at the left and D7 at the right. For all other modes, bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bit in each byte assigned to D0. The configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones (or 24 fill bits, in Express mode). This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 22 and Table 23). Each frame begins with a start field and ends with an error check. In all modes except Express mode, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are don't-cares; these bytes are not included in bitstreams created by the Xilinx software. Table 21: XC4000-Series Data Stream Formats Data Type Fill Byte Preamble Code Length Count Fill Bits Start Field Data Frame CRC or Constant Field Check Extend Write Cycle Postamble Start-Up Bytes Express Mode (D0-D7) 11111111b 11110010b FFFFFFh -- 11010010b DATA(n-1:0) 11010010b FFFFFFFFFFh -- xxxxxxxxh All Other Modes (D0...) 11111111b 0010b COUNT(23:0) 1111b 0b DATA(n-1:0) xxxx (CRC) or 0110b -- 01111111b xxh LEGEND: Unshaded Once per bitstream Light Dark Once per data frame Once per device June 1, 1996 (Version 1.02) Table 22: XC4000E Program Data Device Max Logic Gates CLBs (Row x Col.) IOBs Flip-Flops Horizontal Longlines TBUFs per Longline Bits per Frame Frames Program Data PROM Size (bits) XC4003E XC4005E/L XC4006E 3,000 5,000 6,000 100 196 256 (10 x 10) (14 x 14) (16 x 16) 80 112 128 360 616 768 20 28 32 XC4008E XC4010E/L XC4013E/L XC4020E 8,000 10,000 13,000 20,000 324 400 576 784 (18 x 18) (20 x 20) (24 x 24) (28 x 28) 144 160 192 224 936 1,120 1,536 2,016 36 40 48 56 XC4025E 25,000 1,024 (32 x 32) 256 2,560 64 12 16 18 20 22 26 30 34 126 428 53,936 53,976 166 572 94,960 95,000 186 644 119,792 119,832 206 716 147,504 147,544 226 788 178,096 178,136 266 932 247,920 247,960 306 1,076 329,264 329,304 346 1,220 422,128 422,168 Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra leading ones at the beginning of the header. The MakeBits software creates the configuration bitstream. In Express mode, only non-CRC error checking is supported. In all other modes, MakeBits allows a selection of CRC or non-CRC error checking. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, MakeBits calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vcc. Cyclic Redundancy Check (CRC) for Configuration and Readback The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system June 1, 1996 (Version 1.02) performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the configuration bitstream has four error bits at the end, as shown in Table 21. If a frame data error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 47. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Read Capture MakeBits option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. 4-57 XC4000 Series Field Programmable Gate Arrays Table 23: XC4000EX Program Data Device Max Logic Gates CLBs (Row x Col.) IOBs Flip-Flops Horizontal Longlines TBUFs per Longline Bits per Frame Frames Program Data PROM Size (bits) XC4028EX/XL 28,000 1,024 (32 x 32) 256 2,560 192 34 421 1587 668,127 668,167 XC4036EX/XL 36,000 1,296 (36 x 36) 288 3,168 216 38 469 1775 832,483 832,523 XC4044EX/XL 44,000 1,600 (40 x 40) 320 3,840 240 42 517 1963 1,014,879 1,014,919 XC4052XL 52,000 1,936 (44 x 44) 352 4,576 264 46 565 2151 1,215,323 1,215,363 XC4062XL 62,000 2,304 (48 x 48) 384 5,376 288 50 613 2,339 1,433,807 1,433,847 Notes: 1. Bits per Frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits Number of Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra leading ones at the beginning of the header. 3. Express mode bitfiles are slightly larger (see Table 21). X2 X15 X16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SERIAL DATA IN Polynomial: X16 + X15 + X2 + 1 1 1 1 1 0 15 14 13 12 11 10 9 START BIT 1 LAST DATA FRAME 8 7 6 5 CRC - CHECKSUM Readback Data Stream X1789 Figure 47: Circuit for Generating CRC-16 4-58 June 1, 1996 (Version 1.02) Configuration Sequence Configuration Memory Clear Initialization Configuration Start-Up No Yes Test M0 Generate One Time-Out Pulse of 16 or 64 ms PROGRAM = Low The full process is illustrated in Figure 48. Yes Configuration Memory Clear When power is first applied or is reapplied to an FPGA, an internal circuit forces initialization of the configuration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltage devices. The delay is four times as long when in Master Modes (M0 Low), to allow ample time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin Low. During this time delay, or as long as the PROGRAM input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory frames are consecutively initialized, using the internal oscillator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the configuration frames and then tests the INIT input. Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) INIT High? if Master Yes No Master Waits 50 to 250 s Before Sampling Mode Lines Sample Mode Lines Master CCLK Goes Active Load One Configuration Data Frame Frame Error Yes Pull INIT Low and Stop No SAMPLE/PRELOAD BYPASS Configuration memory Full No Yes Initialization Pass Configuration Data to DOUT During initialization and configuration, user pins HDC, LDC, INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 s (up to 10% longer for low-voltage devices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized as High, the FPGA samples the three mode lines to determine the configuration mode. The appropriate interface lines become active and the configuration preamble and data can be loaded. ~1.3 s per Frame LDC Output = L, HDC Output = H * * * * VCC >3.5 V Boundary Scan Instructions Available: CCLK Count Equals Length Count No Yes Start-Up Sequence F EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK Operational I/O Active There are four major steps in the XC4000-Series power-up configuration sequence. If Boundary Scan is Selected X6076 Figure 48: Power-up Configuration Sequence June 1, 1996 (Version 1.02) 4-59 XC4000 Series Field Programmable Gate Arrays Configuration The 0010 preamble code, included for all modes except Express mode, indicates that the following 24 bits represent the length count. The length count is the total number of configuration clocks needed to load the complete configuration data. (Four additional configuration clocks are required to complete the configuration process, as discussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. In Express mode, the length count bits are ignored, and DOUT is held Low, to disable the next device in the pseudo daisy chain. A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. In Express mode, when the first device is fully programmed, DOUT goes High to enable the next device in the chain. Delaying Configuration After Power-Up There are two methods of delaying configuration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 48 on page 59.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration memory. When PROGRAM goes High, the configuration memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The XC4000-Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration causes the FPGA to wait after completing the configuration memory clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configuration process. A master device waits up to an additional 250 s 4-60 to make sure that any slaves in the optional daisy chain have seen that INIT is High. Start-Up Start-up is the transition from the configuration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic `wakes up' gracefully, that the outputs become active without causing contention with the configuration signals, and that the internal flip-flops are released from the global Reset or Set at the right time. Figure 49 describes start-up timing for the three Xilinx families in detail. Express mode configuration always uses either CCLK_SYNC or UCLK_SYNC timing, the other configuration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a fixed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some flexibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000 Series offers additional flexibility. The three events -- DONE going High, the internal Set/Reset being de-activated, and the user I/O going active -- can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of software options in MakeBits, the bitstream generation software. The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os become active one clock later. Reset/Set is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 49, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. June 1, 1996 (Version 1.02) Length Count Match CCLK Period CCLK F DONE XC2000 I/O Global Reset F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F F XC3000 DONE I/O Heavy lines describe default timing Global Reset F DONE C1 XC4000E/EX C2 C3 C4 C2 C3 C4 C2 C3 C4 I/O CCLK_NOSYNC GSR Active DONE IN F DONE C1, C2 or C3 XC4000E/EX I/O CCLK_SYNC Di Di+1 GSR Active Di Di+1 F DONE C1 XC4000E/EX U2 U3 U4 U2 U3 U4 U2 U3 U4 I/O UCLK_NOSYNC GSR Active DONE IN F DONE C1 XC4000E/EX U2 I/O UCLK_SYNC Di Di+1 Di+2 Di+1 Di+2 GSR Active Synchronization Uncertainty Di UCLK Period X6700 Figure 49: Start-up Timing June 1, 1996 (Version 1.02) 4-61 XC4000 Series Field Programmable Gate Arrays The XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a configuration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active. If either of these two options is selected, and no user clock is specified in the design or attached to the device, the chip could reach a point where the configuration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the configuration memory is full, and the total number of configuration clocks received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a flip-flop Q0, shown in Figure 50. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. * * * The release of the open-drain DONE output The change of configuration-related pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called "Start-up Timing Synchronous to Done In" and is selected by the CCLK_SYNC and UCLK_SYNC MakeBits options. When DONE is not used as an input, the operation is called "Start-up Timing Not Synchronous to DONE In," and is selected by the CCLK_NOSYNC and UCLK_NOSYNC MakeBits options. As a configuration option, the start-up control register beyond Q0 can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. 4-62 Start-up from CCLK If CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 49 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options. Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence. DONE Goes High to Signal End of Configuration In all configuration modes except Express mode, XC4000Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration. Two conditions have to be met in order for the DONE pin to go high: * * the chip's internal memory must be full, and the configuration length count must be met, exactly. This is important because the counter that determines when the length count is met begins with the very first CCLK, not the first one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the first CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of configuration, the configuration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] -- which is sometimes interpreted as the device not configuring at all. If it is not possible to have the data ready at the time of the first CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. The XACT User Guide includes detailed information about manually altering the length count. In Express mode, there is no length count. The DONE pin for each device goes High when the device has received its quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all are fully configured. June 1, 1996 (Version 1.02) Q3 STARTUP Q1/Q4 DONE IN Q2 * IOBs OPERATIONAL PER CONFIGURATION * GLOBAL SET/RESET OF ALL CLB AND IOB FLIP-FLOP 1 0 GSR ENABLE GSR INVERT STARTUP.GSR CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE) STARTUP.GTS GTS INVERT GTS ENABLE 0 GLOBAL 3-STATE OF ALL IOBs 1 Q S R * DONE 1 1 0 0 Q0 FULL LENGTH COUNT Q1 Q2 Q3 " FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR Q4 1 S Q D Q D Q 0 D Q D Q M K K K * K K CLEAR MEMORY CCLK 0 STARTUP.CLK USER NET 1 M * * CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS" X1528 Figure 50: Start-up Logic Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by MakeBits, the bitstream generation software. Release of User I/O After DONE Goes High By default, the user I/O are released one CCLK cycle after the DONE pin goes High. If CCLK is not clocked after DONE goes High, the outputs remain in their initial state -- 3-stated, with a 50 k - 100 k pull-up. The delay from DONE High to active user I/O is controlled by a MakeBits option. June 1, 1996 (Version 1.02) Release of Global Set/Reset After DONE Goes High By default, Global Set/Reset (GSR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all flip-flops are held in their initial set or reset state. The delay from DONE High to GSR inactive is controlled by a MakeBits option. Configuration Complete After DONE Goes High Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 49 on page 61. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used. 4-63 XC4000 Series Field Programmable Gate Arrays Configuration Through the Boundary Scan Pins XC4000-Series devices can be configured through the boundary scan pins. The basic procedure is as follows: * Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after configuration if a resistor is used to hold INIT Low. * Issue the CONFIG command to the TMS input * Wait for INIT to go High * Sequence the boundary scan Test Access Port to the SHIFT-DR state * Toggle TCK to clock data into TDI pin. The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note XAPP017, "Boundary Scan in XC4000 Devices." This application note also applies to XC4000E and XC4000EX devices. Readback The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs and IOBs, as well as the content of function generators used as RAMs. Note that in XC4000-Series devices, configuration data is not inverted with respect to configuration as it is in XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble the original bitstream, because the bitstream format differs from other modes. XC4000-Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 51. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with five dummy bits (all High) followed by the Start bit (Low) of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low. IF UNCONNECTED, DEFAULT IS CCLK DATA CLK MD0 READ_TRIGGER TRIG IBUF READBACK RIP READ_DATA MD1 OBUF X1786 Figure 51: Readback Schematic Example 4-64 June 1, 1996 (Version 1.02) Readback Options Readback options are: Read Capture, Read Abort, and Clock Select. They are set with MakeBits, the bitstream generation software. I/O I/O PROGRAMMABLE INTERCONNECT When the Read Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table configuration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 52. Read Abort When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress. rdbk I When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output flip-flops and the input signals I1 and I2. Note that while the bits describing configuration (interconnect, function generators, and RAM content) are not inverted, the CLB and IOB output signals are inverted. TRIG DATA RIP Read Capture I/O I/O I/O rdclk X1787 Figure 52: READBACK Symbol in Graphical Editor Violating the Maximum High and Low Time Specification for the Readback Clock The readback clock has a maximum High and Low time specification. In some cases, this specification cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Clock Select Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 21, Table 22 and Table 23. RDBK.CLK is located in the lower right chip corner, as shown in Figure 52. Readback with the XChecker Cable The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verification. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator. June 1, 1996 (Version 1.02) 4-65 XC4000 Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble data--and all data that overflows the lead device--on its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In MakeBits, the user can specify Fast ConfigRate, which, starting several bits into the first frame, increases the CCLK frequency by a factor of eight. The value increases from between 0.5 and 1.25 MHz, to a value between 4 and 10 MHz. (For low-voltage devices, the frequency can be up to 10% lower.) Be sure that the serial PROM and slaves are fast enough to support this data rate. XC2000, XC3000/A, and XC3100A devices do not support the Fast ConfigRate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but LDC is then restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Master Serial mode is selected by a <000> on the mode pins (M2, M1, M0). NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O VCC N/C 4.7 K 4.7 K 4.7 K 4.7 K 4.7 K 4.7 K M0 M1 M2 N/C DOUT XC4000E/EX MASTER SERIAL DIN M0 M1 M2 DOUT CCLK VCC XC1700D 4.7 K CCLK M0 M1 M2 CLK DIN DATA PROGRAM LDC CE DONE INIT RESET/OE +5 V DIN DOUT CCLK XC4000E/EX, XC5200 XC3100A SLAVE SLAVE VPP CEO PWRDN PROGRAM DONE RESET INIT D/P INIT (Low Reset Option Used) PROGRAM X6608 Figure 53: Master Serial Mode Circuit Diagram 4-66 June 1, 1996 (Version 1.02) CCLK (Output) 2 TCKDS 1 Serial Data In Serial DOUT (Output) TDSCK n n-3 n+1 n-2 n+2 n-1 n X3223 CCLK Description DIN setup DIN hold 1 2 Symbol TDSCK TCKDS Min 20 0 Max Units ns ns Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode. Figure 54: Master Serial Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-67 XC4000 Series Field Programmable Gate Arrays Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble data--and all data that overflows the lead device--on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resistors during configuration. NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O VCC N/C 4.7 K 4.7 K 4.7 K 4.7 K 4.7 K 4.7 K M0 M1 M2 N/C DOUT XC4000E/EX MASTER SERIAL DIN M0 M1 M2 DOUT CCLK VCC XC1700D 4.7 K CCLK M0 M1 M2 CLK DIN DATA PROGRAM LDC CE DONE INIT RESET/OE +5 V DIN DOUT CCLK XC4000E/EX, XC5200 XC3100A SLAVE SLAVE VPP CEO PWRDN PROGRAM DONE RESET INIT D/P INIT (Low Reset Option Used) PROGRAM X6608 Figure 55: Slave Serial Mode Circuit Diagram 4-68 June 1, 1996 (Version 1.02) DIN Bit n 1 TDCC Bit n + 1 2 TCCD 5 TCCL CCLK 4 TCCH DOUT (Output) 3 TCCO Bit n - 1 Bit n X5379 CCLK Note: Description DIN setup DIN hold DIN to DOUT High time Low time Frequency 1 2 3 4 5 Symbol TDCC TCCD TCCO TCCH TCCL FCC Min 20 0 Max 30 45 45 10 Units ns ns ns ns ns MHz Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 56: Slave Serial Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-69 XC4000 Series Field Programmable Gate Arrays Master Parallel Modes In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decrementing the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble data--and all data that overflows the lead device--on its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. 4.7K M0 The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and can load its configuration bitstream from either end of the memory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, M0). The EPROM addresses start at 00000 and increment. Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement. TO DIN OF OPTIONAL DAISY-CHAINED FPGAS HIGH or LOW N/C M1 M2 N/C TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS CCLK NOTE:M0 can be shorted to Ground if not used as I/O. DOUT VCC 4.7K INIT A17 ... A16 ... A15 ... A14 ... A13 ... M0 M1 DIN EPROM (8K x 8) (OR LARGER) A12 A11 A11 A10 A10 PROGRAM A9 A9 D7 A8 A8 D6 A7 A7 D7 D5 A6 A6 D6 D4 A5 A5 D5 D3 A4 A4 D4 D2 A3 A3 D3 D1 A2 A2 D2 D0 A1 A1 D1 A0 A0 D0 DONE OE DOUT CCLK USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS A12 M2 XC4000E/EX SLAVE PROGRAM DONE INIT CE DATA BUS 8 PROGRAM X6697 Figure 57: Master Parallel Mode Circuit Diagram 4-70 June 1, 1996 (Version 1.02) A0-A17 (output) Address for Byte n Address for Byte n + 1 1 TRAC D0-D7 Byte 3 TRCD 2 TDRC RCLK (output) 7 CCLKs CCLK CCLK (output) DOUT (output) D6 D7 Byte n - 1 RCLK Description Delay to Address valid Data setup time Data hold time 1 2 3 Symbol TRAC TDRC TRCD Min 0 60 0 X6078 Max 200 Units ns ns ns Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge). This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 58: Master Parallel Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-71 XC4000 Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisychained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, M0). NOTE: M2 can be shorted to Ground if not used as I/O N/C M0 M1 N/C 4.7 k M2 M0 M1 CCLK CLOCK OPTIONAL DAISY-CHAINED FPGAs 8 DATA BUS D0-7 DOUT VCC 4.7 k M2 CCLK XC4000E/EX SYNCHRONOUS PERIPHERAL DIN DOUT XC4000E/EX SLAVE RDY/BUSY CONTROL SIGNALS INIT DONE DONE INIT 4.7 k PROGRAM PROGRAM PROGRAM X5996 Figure 59: Synchronous Peripheral Mode Circuit Diagram 4-72 June 1, 1996 (Version 1.02) CCLK INIT BYTE 0 BYTE 1 BYTE 0 OUT DOUT 0 1 2 3 4 BYTE 1 OUT 5 6 7 0 1 RDY/BUSY X6096 CCLK Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency Symbol TIC TDC TCD TCCH TCCL FCC Min 5 60 0 50 60 Max 8 Units s ns ns ns ns MHz Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal. 4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded. Figure 60: Synchronous Peripheral Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-73 XC4000 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods. Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. Status Read The logic AND condition of the CS0, CS1and RS inputs puts the device status on the Data bus. * * * The lead FPGA presents the preamble data (and all data that overflows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. D7 High indicates Ready D7 Low indicates Busy D0 through D6 go unconditionally High It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the final byte transfer. If this transfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 49 on page 61). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by MakeBits and MakePROM, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, M0). Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered. N/C N/C N/C 4.7 k M0 8 DATA BUS D0-7 M1 CCLK DOUT 4.7 k ... 4.7 k M1 M2 CCLK OPTIONAL DAISY-CHAINED FPGAs VCC ADDRESS BUS M0 M2 ADDRESS DECODE LOGIC DOUT DIN CS0 XC4000E/EX ASYNCHRONOUS PERIPHERAL XC4000E/EX SLAVE CS1 RS WS CONTROL SIGNALS RDY/BUSY REPROGRAM INIT INIT DONE DONE PROGRAM PROGRAM 4.7 k X6696 Figure 61: 4-74 Asynchronous Peripheral Mode Circuit Diagram June 1, 1996 (Version 1.02) Write to LCA Read Status RS, CS0 WS/CS0 RS, CS1 WS, CS1 1 TCA 2 3 TDC TCD 4 7 READY BUSY D0-D7 D7 CCLK TWTRB 4 6 TBUSY RDY/BUSY Previous Byte D6 DOUT D7 D0 D1 D2 X6097 Write RDY Description Effective Write time (CS0, WS=Low; RS, CS1=High) DIN setup time DIN hold time RDY/BUSY delay after end of Write or Read RDY/BUSY active after beginning of Read RDY/BUSY Low output (Note 4) 1 2 3 4 Symbol TCA TDC TCD TWTRB Min 100 60 0 7 6 TBUSY Max 2 Units ns 60 ns ns ns 60 ns 9 CCLK periods Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-75 XC4000 Series Field Programmable Gate Arrays Express Mode (XC4000EX only) nized as High, and remains Low until the device's configuration memory is full. DOUT is then pulled High to signal the next device in the chain to accept the configuration data on the D0-D7 bus. Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the configuration data shift registers. A CCLK frequency of 1 MHz is equivalent to a 8 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not support CRC error checking, but does support constant-field error checking. The DONE pins of all devices in the chain should be tied together, with one or more active internal pull-ups. If a large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is activated by default. It can be deactivated using a MakeBits option. In Express mode, an external signal drives the CCLK input of the FPGA device. The first byte of parallel configuration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. XC4000EX devices in Express mode are always synchronized to DONE. The device becomes active after DONE goes High. DONE is an open-drain output. With the DONE pins tied together, therefore, the external DONE signal stays low until all devices are configured, then all devices in the daisy chain become active simultaneously. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been configured. XC5200 devices in the chain should be configured as synchronized to DONE (MakeBits option CCLK_SYNC or UCLK_SYNC), and their DONE pins wired together with those of the XC4000EX devices. Express mode is only supported by the XC4000EX and XC5200 families. It may not be used, therefore, when an XC4000EX or XC5200 device is daisy-chained with devices from other Xilinx families. If the first device is configured in Express mode, additional devices may be daisy-chained only if every device in the chain is also configured in Express mode. CCLK pins are tied together and D0-D7 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). Frame data is accepted only when CS1 is High and the device's configuration memory is not already full. The status pin DOUT is pulled Low two internal-oscillator cycles after INIT is recog- Express mode must be specified as an option to the MakeBits program, which generates the bitstream. The Express mode bitstream is not compatible with the other six configuration modes. Express mode is selected by a <010> on the mode pins (M2, M1, M0). VCC NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O 4.7K 8 M0 M1 CS1 DATA BUS 8 M2 8 XC4000EX/ XC5200 4.7K PROGRAM PROGRAM INIT INIT CCLK M1 CS1 DOUT D0-D7 VCC M0 M2 To Additional Optional Daisy-Chained Devices DOUT D0-D7 Optional Daisy-Chained XC4000EX/ XC5200 PROGRAM DONE INIT DONE CCLK To Additional Optional Daisy-Chained Devices CCLK X6611 Figure 63: Express Mode Circuit Diagram 4-76 June 1, 1996 (Version 1.02) CCLK Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency Symbol TIC TDC TCD TCCH TCCL FCC Min 0 - Max - Units s ns ns ns ns MHz Preliminary CCLK 1 TIC INIT TCD 3 2 T DC D0-D7 BYTE 0 BYTE 1 BYTE 2 BYTE 3 DOUT FPGA Filled Internal INIT RDY/BUSY CS1 X6710 Note: If not driven by the preceding DOUT, CS1 must remain High until the device is fully configured. Figure 64: Express Mode Programming Switching Characteristics June 1, 1996 (Version 1.02) 4-77 XC4000 Series Field Programmable Gate Arrays Table 24: Pin Functions During Configuration SLAVE SERIAL <1:1:1> M2(HIGH) (I) M1(HIGH) (I) M0(HIGH) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (I) DIN (I) DOUT TDI TCK TMS TDO CONFIGURATION MODE SYNCH. ASYNCH. MASTER MASTER MASTER PERIPHPERIPHPARALLEL PARALLEL UP EXPRESS SERIAL ERAL ERAL DOWN <1:0:0> <0:1:0> <0:0:0> <0:1:1> <1:0:1> <1:1:0> M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) M2(LOW) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) M0(HIGH) (I) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) INIT INIT INIT INIT INIT INIT DONE DONE DONE DONE DONE DONE PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I) RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) RS (I) CS0 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DOUT DOUT DOUT DOUT DOUT DOUT TDI TDI TDI TDI TDI TDI TCK TCK TCK TCK TCK TCK TMS TMS TMS TMS TMS TMS TDO TDO TDO TDO TDO TDO WS (I) A0 A0 A1 A1 CS1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9 A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 A18* A18* A19* A19* A20* A20* A21* A21* USER OPERATION (I) (O) (I) I/O I/O I/O DONE PROGRAM CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK4-GCK5-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) I/O PGCK4-GCK6-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK1-GCK7-I/O PGCK1-GCK8-I/O I/O I/O I/O I/O I/O ALL OTHERS * XC4000EX only Notes 1. A shaded table cell represents a 50 k - 100 k pull-up before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration. 4-78 June 1, 1996 (Version 1.02) Configuration Switching Characteristics T POR Vcc RE-PROGRAM >300 ns PROGRAM T PI INIT T ICCK TCCLK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) DONE RESPONSE VALID X1532 <300 ns I/O Master Modes Description M0 = High M0 = Low Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast Symbol TPOR TPOR TPI Min 10 40 30 Max 40 130 200 TICCK TCCLK TCCLK 40 640 80 250 2000 250 Symbol TPOR TPI Min 10 30 Max 33 200 TICCK TCCLK 4 100 Units ms ms s per CLB column s ns ns Slave and Peripheral Modes Description Power-On Reset Program Latency CCLK (input) Delay (required) CCLK (input) Period (required) June 1, 1996 (Version 1.02) Units ms s per CLB column s ns 4-79 XC4000 Series Field Programmable Gate Arrays XC4000E Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1 XC4000E Operating Conditions Symbol VCC VIH Description Supply voltage relative to GND, TJ = -0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TC = -55C to +125C High-level input voltage VIL Low-level input voltage TIN Input signal transition time (Note 2) Commercial Industrial Military TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.5 4.5 2.0 70% 0 0 Max 5.25 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V V VCC V VCC ns Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Typical value only. Not tested or characterized. XC4000E DC Characteristics Over Operating Conditions Symbol VOH VOL Description High-level output voltage @ IOH = -4.0mA, VCC min High-level output voltage @ IOH = -1.0mA, VCC min Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) ICCO Quiescent FPGA supply current (Note 2) IL CIN Input or output leakage current Input capacitance (sample tested) IRIN IRLL Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Note 1: Note 2: TTL outputs CMOS outputs TTL outputs CMOS outputs TTL input levels CMOS input levels Min 2.4 VCC-0.5 -10 PQFP and MQFP packages Other packages 0.02 0.2 Max 0.4 0.4 10 1 +10 10 Units V V V V mA mA A pF 16 0.25 2.5 pF mA mA With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with a MakeBits Tie option. 1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. 4-80 June 1, 1996 (Version 1.02) XC4000E Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note 1: Note 2: Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150 +125 Units V V V C C C C Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. Description From pad through Primary buffer, to any clock K From pad through Secondary buffer, to any clock K June 1, 1996 (Version 1.02) Symbol TPG TSG Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E -4 -3 Max Max 7.0 4.7 7.0 4.7 7.5 5.3 8.0 6.1 11.0 6.3 11.5 6.8 12.0 7.0 12.5 7.2 7.5 5.2 7.5 5.2 8.0 5.8 8.5 6.6 11.5 6.8 12.0 7.3 12.5 7.5 13.0 7.7 PRELIMINARY -2 Max 4.0 4.0 4.5 5.2 5.4 5.8 6.2 6.3 4.4 4.4 4.9 5.6 5.8 6.2 6.6 6.8 ADVANCE Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4-81 XC4000 Series Field Programmable Gate Arrays XC4000E Wide Decoder Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. Description Full length, both pull-ups, inputs from IOB I-pins Full length, both pull-ups, inputs from internal logic Half length, one pull-up, inputs from IOB I-pins Half length, one pull-up, inputs from internal logic Note 1: Note 2: 4-82 Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAFL XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAO XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E TWAOL XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Symbol TWAF -4 -3 Max Max 9.2 5.0 9.5 6.0 12.0 7.0 12.5 8.0 15.0 9.0 16.0 11.0 17.0 13.9 18.0 16.9 12.0 7.0 12.5 8.0 14.0 9.0 16.0 10.0 18.0 11.0 19.0 13.0 20.0 15.5 21.0 18.9 10.5 6.0 10.5 7.0 13.5 8.0 14.0 9.0 16.0 10.0 17.0 12.0 18.0 15.0 19.0 17.6 12.0 8.0 12.5 9.0 14.0 10.0 16.0 11.0 18.0 12.0 19.0 14.0 20.0 16.8 21.0 19.6 PRELIMINARY -2 Max 4.3 5.1 6.2 7.0 8.1 9.9 12.5 15.2 6.0 6.8 7.9 8.8 9.7 11.7 14.0 17.0 5.1 6.0 6.8 7.9 8.8 10.8 13.5 15.8 6.8 7.7 8.5 9.4 10.2 11.9 14.3 16.7 ADVANCE Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID) and output delay (TOPF or TOPS), as listed under "IOB Switching Characteristic Guidelines." June 1, 1996 (Version 1.02) XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. Description TBUF driving a Horizontal Longline (LL): I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1) I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. Speed Grade Symbol Device XC4003E TIO1 TIO2 (Note1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. TON (Note1) T going High to TBUF going inactive, not driving LL T going High to LL going from Low to High, pulled up by a single resistor. TOFF TPUS (Note 2) T going High to LL going from Low to High, pulled up by two resistors. (Note1) TPUF -4 Max -3 Max -2 Max Units XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices 5.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 5.0 6.0 7.8 8.1 10.5 11.0 12.0 12.0 5.5 7.0 7.5 8.0 8.5 8.7 11.0 11.0 1.8 4.2 5.0 5.9 6.3 6.4 7.2 8.2 9.1 4.2 5.3 6.4 6.8 6.9 7.7 8.7 9.6 4.6 6.0 6.7 7.1 7.3 7.5 8.4 8.4 1.5 3.4 4.0 4.7 5.0 5.1 5.7 6.6 7.3 3.6 4.5 5.4 5.8 5.9 6.5 7.4 8.2 3.9 5.4 5.7 6.0 6.2 6.4 7.1 7.1 1.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 20.0 23.0 25.0 27.0 29.0 32.0 35.0 42.0 9.0 10.0 11.5 12.5 13.5 15.0 16.0 18.0 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 7.0 8.0 9.0 10.0 11.0 13.0 14.8 16.5 11.9 13.6 15.3 17.0 18.7 22.1 27.6 33.2 6.0 6.8 7.7 8.5 9.4 11.0 12.6 14.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PRELIMINARY Note 1: Note 2: ADVANCE These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. This value includes a minimum load. The value reported by LCA2XNF -S is increased to allow for potentially heavy loading, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. June 1, 1996 (Version 1.02) 4-83 XC4000 Series Field Programmable Gate Arrays XC4000E CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs C inputs via SR through H' to X/Y outputs C inputs via H' to X/Y outputs C inputs via DIN through H' to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H' C inputs via H0 through H' C inputs via H1 through H' C inputs via H2 through H' C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F'/G' CIN input via F'/G' and H' -4 Symbol Min -3 Max Min Min Max TILO TIHO THH0O THH1O THH2O 2.7 4.7 4.1 3.7 4.5 2.0 4.3 3.3 3.6 3.6 1.6 2.7 2.4 2.2 2.6 TOPCY TASCY TINCY TSUM 3.2 5.5 1.7 3.8 2.6 4.4 1.7 3.3 2.1 3.7 1.4 2.6 TBYP 1.0 0.7 0.6 TCKO 3.7 2.8 2.8 TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 PRELIMINARY 4-84 -2 Max 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 ADVANCE June 1, 1996 (Version 1.02) XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Hold Time after Clock K F/G inputs TCKI F/G inputs via H' TCKIH C inputs via H0 through H' TCKHH0 C inputs via H1 through H' TCKHH1 C inputs via H2 through H' TCKHH2 C inputs via DIN TCKDI C inputs via EC TCKEC C inputs via SR, going Low (inactive) TCKR Clock Clock High time TCH Clock Low time TCL Set/Reset Direct Width (High) TRPW Delay from C inputs via S/R, TRIO going High to Q Master Set/Reset (Note 1) Width (High or Low) TMRW TMRQ Delay from Global Set/Reset net to Q TMRK Global Set/Reset inactive to first active clock K edge FTOG Toggle Frequency2 (MHz) -4 Min -3 Max Min -2 Max Min 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.5 4.5 4.0 4.0 4.0 4.0 5.5 4.0 6.5 13.0 4.0 4.0 11.5 23.0 111 PRELIMINARY Max 4.0 11.5 18.7 17.4 125 125 ADVANCE Notes: 1. Timing is based on the XC4005E. For other devices see the XACT timing calculator. 2. Export Control Max. flip-flop toggle rate. June 1, 1996 (Version 1.02) 4-85 XC4000 Series Field Programmable Gate Arrays XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Description Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Note 1: Note 2: Speed Grade Size Symbol 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS -4 Min 15.0 15.0 7.5 7.5 2.8 2.8 0 0 3.5 2.5 0 0 2.2 2.2 0 0 -3 Max 1 ms 1 ms Min 14.4 14.4 7.2 7.2 2.4 2.4 0 0 3.2 1.9 0 0 2.0 2.0 0 0 10.3 11.6 PRELIMINARY -2 Max 1 ms 1 ms 8.8 10.3 Min 11.6 11.6 5.8 5.8 2.0 2.0 0 0 2.7 1.7 0 0 1.6 1.6 0 0 Max 1 ms 1 ms 6.3 7.4 ADVANCE Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Level-Sensitive Read timing. TWPS WCLK (K) TWHS TWSS WE TDSS TDHS TASS TAHS DATA IN ADDRESS TILO DATA OUT TWOS OLD TILO NEW X6461 4-86 June 1, 1996 (Version 1.02) XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Description Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Note: Speed Grade Size Symbol Min -4 16x1 TWCDS 15.0 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS 7.5 2.8 0 2.2 0 2.2 0.3 -3 Max Min -2 Max 14.4 1 ms 7.2 2.5 0 1.9 0 2.0 0 10.0 PRELIMINARY Min Max 11.6 1 ms 7.8 5.8 2.1 0 1.6 0 1.6 0 1 ms 6.2 ADVANCE Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing. TWPDS WCLK (K) TWSDS TWHDS TDSDS TDHDS TASDS TAHDS WE DATA IN ADDRESS TILO TILO TWODS DATA OUT OLD NEW X6474 June 1, 1996 (Version 1.02) 4-87 XC4000 Series Field Programmable Gate Arrays XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Description Write Operation Address write cycle time Speed Grade Size Symbol -4 Min -3 Max Min -2 Max Min 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT 8.0 8.0 4.0 4.0 2.0 2.0 2.5 2.0 4.0 5.0 2.0 2.0 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 2.2 2.2 2.0 2.0 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 0.8 0.8 2.0 2.0 16x2 32x1 Data valid after address 16x2 change (no Write Enable) 32x1 Read Operation, Clocking Data into Flip-Flop Address setup time 16x2 before clock K 32x1 Read During Write Data valid after WE goes 16x2 active (DIN stable 32x1 before WE) Data valid after DIN 16x2 (DIN changes during WE) 32x1 Read During Write, Clocking Data into Flip-Flop WE setup time 16x2 before clock K 32x1 Data setup time 16x2 before clock K 32x1 TRC TRCT TILO TIHO 4.5 6.5 3.1 5.5 2.6 3.8 TICK TIHCK 4.0 6.1 Write Enable pulse width (High) Address setup time before WE Address hold time after end of WE DIN setup time before end of WE DIN hold time after end of WE Read Operation Address read cycle time Note: 4-88 2.7 4.7 2.0 4.3 3.0 4.6 Max 1.6 2.7 2.4 3.9 TWO TWOT 10.0 12.0 6.0 7.3 4.9 5.6 TDO TDOT 9.0 11.0 6.6 7.6 5.8 6.2 TWCK TWCKT TDCK TDCKT 8.0 9.6 7.0 8.0 6.0 6.8 5.2 6.2 PRELIMINARY 5.1 5.8 4.4 5.3 ADVANCE Timing for the 16x1 RAM option is identical to 16x2 RAM timing. June 1, 1996 (Version 1.02) XC4000E CLB Level-Sensitive RAM Timing Characteristics T WC ADDRESS WRITE TAS T WP T AH WRITE ENABLE T DS DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS T DH T ILO VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP T ICK T CH CLOCK T CKO VALID (OLD) XQ, YQ OUTPUTS VALID (NEW) READ DURING WRITE T WP WRITE ENABLE T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID DATA IN (changing during WE) OLD VALID NEW T DO T WO X, Y OUTPUTS VALID (PREVIOUS) VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP T WP WRITE ENABLE T WCK T DCK DATA IN CLOCK T CKO XQ, YQ OUTPUTS X2640 June 1, 1996 (Version 1.02) 4-89 XC4000 Series Field Programmable Gate Arrays XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs) All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy between the two methods, the values listed below should be used, and the derived values must be ignored. All values are expressed in units of nanoseconds. Speed Grade Symbol Device XC4003E TICKOF Description Global Clock to Output (fast) using OFF TPG . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Global Clock to Output (slew-limited) using OFF TPG TICKO . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Input Setup Time, using IFF (no delay) D Input Set - Up & Hold Time TPSUF (Min) IFF TPG X3201 Input Hold Time, using IFF (no delay) TPHF D Input Set - Up & Hold Time (Min) IFF TPG X3201 Input Setup Time, using IFF (with delay) D Input Set - Up & Hold Time TPSU (Min) IFF TPG X3201 Input Hold Time, using IFF (with delay) TPH D Input Set - Up & Hold Time (Min) IFF TPG X3201 OFF = Output Flip-Flop 4-90 -4 -3 -2 XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 12.5 14.0 14.5 15.0 16.0 16.5 17.0 17.0 10.2 10.7 10.7 10.8 10.9 11.0 11.0 12.6 8.7 9.1 9.1 9.2 9.3 9.4 9.4 10.7 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 16.5 18.0 18.5 19.0 20.0 20.5 21.0 21.0 14.0 14.7 14.7 14.8 14.9 15.0 15.1 15.3 11.5 12.0 12.0 12.1 12.2 12.8 12.8 13.0 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 2.5 2.0 1.9 1.4 1.0 0.5 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 4.0 4.6 5.0 6.0 6.0 7.0 7.5 8.0 4.0 4.5 4.7 5.1 5.5 6.5 6.7 7.0 4.0 4.5 4.7 5.1 5.5 5.5 5.7 5.9 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 8.5 8.5 8.5 8.5 8.5 8.5 9.5 9.5 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.6 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.5 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFF = Input Flip-Flop or Latch PRELIMINARY ADVANCE June 1, 1996 (Version 1.02) XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs) All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy between the two methods, the values listed below should be used, and the derived values must be ignored. All values are expressed in units of nanoseconds. Speed Grade Symbol Device XC4003E TCICKOF Description Global Clock to Output (fast) using OFF TPG . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Global Clock to Output (slew-limited) using OFF TPG TCICKO . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Input Setup Time, using IFF (no delay) D Input Set - Up & Hold Time TCPSUF (Min) IFF TPG X3201 Input Hold Time, using IFF (no delay) TCPHF D Input Set - Up & Hold Time (Min) IFF TPG X3201 Input Setup Time, using IFF (with delay) D Input Set - Up & Hold Time TCPSU (Min) IFF TPG X3201 Input Hold Time, using IFF (with delay) TCPH D Input Set - Up & Hold Time (Min) IFF TPG X3201 OFF = Output Flip-Flop June 1, 1996 (Version 1.02) -4 -3 -2 XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E IFF = Input Flip-Flop or Latch PRELIMINARY ADVANCE 4-91 XC4000 Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Description Propagation Delays (TTL Inputs) Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay (CMOS Inputs) Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay Speed Grade Symbol Device Note 2: 4-92 -3 Max Min -2 Max Min Max TPID All devices 3.0 2.5 2.0 TPLI TPDLI All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 4.8 10.4 10.8 10.8 10.8 11.0 11.4 13.8 13.8 3.6 9.3 9.6 10.2 10.6 10.8 11.2 12.4 13.7 3.6 7.0 7.3 7.8 8.1 8.2 8.5 9.5 9.5 TPIDC All devices 5.5 4.1 3.7 TPLIC TPDLIC All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 8.8 16.5 16.5 16.8 17.3 17.5 18.0 20.8 20.8 6.8 12.4 13.2 13.4 13.8 14.0 14.4 15.6 15.6 6.2 11.0 11.9 12.1 12.4 12.6 13.0 14.0 14.0 All devices 5.6 2.8 2.8 All devices 6.2 4.0 3.9 (TTL or CMOS) Clock (IK) to I1, I2 (flip-flop) TIKRI Clock (IK) to I1, I2 (latch enable, active Low) TIKLI Hold Times (Note 1) Pad to Clock (IK), no delay TIKPI with delay TIKPID Clock Enable (EC) to Clock (IK), no delay TIKEC with delay TIKECD Note 1: -4 Min All devices All devices 0 0 All devices All devices 1.5 0 0 0 1.5 0 PRELIMINARY 0 0 0.9 0 ADVANCE Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. June 1, 1996 (Version 1.02) XC4000E IOB Input Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Device Setup Times (TTL Inputs) Pad to Clock (IK), no delay TPICK All devices with delay TPICKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E (CMOS Inputs) Pad to Clock (IK), no delay TPICKC All devices with delay TPICKDC XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E (TTL or CMOS) Clock Enable (EC) to Clock (IK), no delay TECIK All devices with delay TECIKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Global Set/Reset (Note 3) Delay from GSR net TRRI through Q to I1, I2 GSR width TMRW GSR inactive to first active TMRI Clock (IK) edge -4 Min -3 Max Min Note 2: Note 3: Min 4.0 10.9 10.9 10.9 11.1 11.3 11.8 14.0 14.0 2.6 8.2 8.7 9.2 9.6 9.8 10.2 11.4 11.4 1.7 5.5 5.5 6.6 6.9 7.0 7.3 8.2 8.2 6.0 12.0 12.0 12.3 12.8 13.0 13.5 16.0 16.0 3.3 8.8 9.7 9.9 10.3 10.5 10.9 12.1 12.1 2.4 6.2 6.2 7.3 7.6 7.7 8.0 8.9 8.9 3.5 10.4 10.4 10.4 10.4 10.7 11.1 14.0 14.0 2.5 8.1 8.5 9.1 9.5 9.7 10.1 11.3 11.3 2.0 5.6 5.6 6.9 7.2 7.3 7.6 8.5 8.5 12.0 13.0 7.8 11.5 PRELIMINARY Note 1: -2 Max Max 6.8 11.5 ADVANCE Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator. June 1, 1996 (Version 1.02) 4-93 XC4000 Series Field Programmable Gate Arrays XC4000E IOB Output Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast TOKPOF slew-rate limited TOKPOS Output (O) to Pad, fast TOPF slew-rate limited TOPS 3-state to Pad hi-Z TTSHZ (slew-rate independent) 3-state to Pad active and valid, fast TTSONF slew-rate limited TTSONS Propagation Delays (CMOS Output Levels) Clock (OK) to Pad, fast TOKPOFC slew-rate limited TOKPOSC Output (O) to Pad, fast TOPFC slew-rate limited TOPSC 3-state to Pad hi-Z TTSHZC (slew-rate independent) 3-state to Pad active and valid, fast TTSONFC slew-rate limited TTSONSC Note 1: Note 2: 4-94 -4 Min -3 Max Min -2 Max Min Max 7.5 11.5 8.0 12.0 5.0 6.5 9.5 5.5 8.5 4.2 4.5 7.0 4.8 7.3 3.8 9.7 13.7 8.1 11.1 7.3 9.8 9.5 13.5 10.0 14.0 5.2 7.8 11.6 9.7 13.4 4.3 7.0 10.4 8.7 12.1 3.9 9.1 13.1 PRELIMINARY 7.6 11.4 6.8 10.2 ADVANCE Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. June 1, 1996 (Version 1.02) XC4000E IOB Output Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Output (O) to clock (OK) TOOK setup time Output (O) to clock (OK) TOKO hold time Clock Enable (EC) to TECOK clock (OK) setup Clock Enable (EC) to TOKEC clock (OK) hold Clock Clock High TCH Clock Low TCL Global Set/Reset (Note 3) Delay from GSR net to Pad TRPO GSR width TMRW GSR inactive to first active TMRO clock (OK) edge -4 Min -3 Max Min Note 2: Note 3: Min 5.0 4.6 3.8 0 0 0 4.8 3.5 2.5 1.2 1.2 0.5 4.5 4.5 4.0 4.0 4.0 4.0 15.0 13.0 11.8 11.5 PRELIMINARY Note 1: -2 Max Max 8.7 11.5 ADVANCE Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator. June 1, 1996 (Version 1.02) 4-95 XC4000 Series Field Programmable Gate Arrays XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Input (TDI) to clock (TCK) TTDITCK setup time Input (TDI) to clock (TCK) TTCKTDI hold time Input (TMS) to clock (TCK) TTMSTCK setup time Input (TMS) to clock (TCK) TTCKTMS hold time Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH Clock (TCK) Low TTCKL Power-On Reset JTAG operation after valid TRJTAG Vcc -4 Min -3 Max Min PRELIMINARY Note 1: Note 2: Note 3: -2 Max Min Max ADVANCE Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. XC4000L Switching Characteristics XC4000L timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http://www.xilinx.com for the latest available information. XC4000EX Switching Characteristics XC4000EX timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http://www.xilinx.com for the latest available information. XC4000XL Switching Characteristics XC4000XL timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http://www.xilinx.com for the latest available information. 4-96 June 1, 1996 (Version 1.02) Device-Specific Pinout Tables Pin Locations for XC4003E Devices XC4003E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O PC 84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 PQ 100 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 June 1, 1996 (Version 1.02) VQ 100 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 PG 120 G3 G1 F1 E1 F2 F3 D1 C1 D2 C2 D3 C3 C4 B2 B3 C5 B4 B5 A4 C6 A5 B6 A6 B7 C7 A7 A8 A9 B8 C8 A10 B9 A11 C9 A12 B11 C10 C11 D11 B12 C12 A13 D12 C13 E12 D13 F11 E13 F12 F13 G12 G11 G13 H13 J13 H12 H11 Bndry Scan 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 126 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 XC4003E Pad Name I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 4/2/96 PC 84 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 PQ 100 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 VQ 100 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 PG 120 K13 J12 L13 M13 L12 K11 L11 L10 M12 M11 N13 M10 N11 M9 N10 L8 N9 M8 N8 M7 L7 N7 N6 N5 M6 L6 N4 M5 N3 Bndry Scan 172 175 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 P71 P72 P75 P76 P72 P73 N2 M3 241 244 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 L4 L3 M2 K3 L2 N1 K2 L1 J2 K1 H3 J1 H2 H1 G2 0 2 5 8 11 14 17 20 23 26 29 - Additional No Connect (N.C.) Connections on PG120 Package PG120 A1 A2 A3 B1 B10 PG120 B13 E2 E3 E11 J3 PG120 J11 K12 L5 L9 M1 PG120 M4 N12 2/28/96 4-97 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4005E/L Devices XC4005 E/L Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O 4-98 PC 84 PQ 100 TQ 144 PG 156 PQ 160 PQ Bndry 208 Scan P2 P92 P128 P3 P93 P129 P4 P94 P130 P95 P131 P96 P132 P5 P97 P133 P6 P98 P134 P135 P136 P137 P7 P99 P138 P8 P100 P139 P140 P141 P9 P1 P142 P10 P2 P143 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 E3 C1 C2 D3 B1 B2 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P154 P155 P156 P157 P158 P159 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P199 P200 P201 P202 P203 P204 44 47 50 53 56 59 62 65 68 71 74 77 80 83 P11 P12 P13 P3 P4 P5 P144 P1 P2 C3 C4 B3 P160 P205 P1 P2 P2 P4 86 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 - P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 - P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 P3 P4 P5 P6 P7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 P5 P6 P7 P8 P9 P14 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 XC4005 E/L Pad Name GND I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND PC 84 PQ 100 TQ 144 PG 156 PQ 160 PQ Bndry 208 Scan P27 P28 P29 P21 P22 P23 P24 P27 P28 P29 P30 P31 P32 P33 C11 B12 A13 A14 C12 B13 B14 P29 P32 P33 P34 P35 P36 P37 P37 P42 P43 P44 P45 P46 P47 152 155 158 161 164 167 P30 P31 P32 P33 P34 P35 P25 P26 P27 P28 P29 P30 P34 P35 P36 P37 P38 P39 A15 C13 A16 C14 B15 B16 P38 P39 P40 P41 P42 P43 P48 P49 P50 P55 P56 P57 170 173 174 175 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P40 D14 P44 P58 P41 C15 P45 P59 P42 D15 P46 P60 P43 E14 P47 P61 P44 C16 P48 P62 P45 F14 P51 P67 P46 F15 P52 P68 P47 E16 P53 P69 P48 F16 P54 P70 P49 G14 P55 P71 P50 G15 P56 P74 P51 G16 P57 P75 P52 H16 P58 P76 P53 H15 P59 P77 P54 H14 P60 P78 P55 J14 P61 P79 P56 J15 P62 P80 P57 J16 P63 P81 P58 K16 P64 P82 P59 K15 P65 P83 P60 K14 P66 P86 P61 L16 P67 P87 P62 M16 P68 P88 P63 L15 P69 P89 P64 L14 P70 P90 P65 P16 P73 P95 P66 M14 P74 P96 P67 N15 P75 P97 P68 P15 P76 P98 P69 N14 P77 P99 P70 R16 P78 P100 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 P52 P52 P71 P14 P79 P101 - June 1, 1996 (Version 1.02) XC4005 E/L Pad Name DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) PC 84 PQ 100 TQ 144 PG 156 PQ 160 P53 P54 P55 P53 P54 P55 P72 P73 P74 R15 P13 R14 P80 P103 P81 P106 P82 P108 - P56 P57 P56 P57 P75 P76 T16 T15 P83 P109 P84 P110 259 262 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P77 P78 P58 P79 P59 P80 P81 P82 P83 P60 P84 P61 P85 P62 P86 P63 P87 P64 P88 P65 P89 P66 P90 P67 P91 P68 P92 P69 P93 P70 P94 P95 P71 P96 P72 P97 P98 P99 P100 P73 P101 P74 P102 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 R6 T4 P6 T3 P5 P85 P86 P87 P88 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P113 P114 P111 P112 P113 P114 P119 P120 P121 P122 P123 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P138 P139 P140 P141 P142 P147 P148 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 P71 P103 P104 P75 P105 R4 R3 P4 P115 P149 P116 P150 P117 P151 331 334 337 P72 P76 P106 T2 P118 P152 340 P73 P74 P75 P76 P77 P77 P78 P79 P80 P81 R2 P3 T1 N3 R1 P119 P120 P121 P122 P123 P107 P108 P109 P110 P111 June 1, 1996 (Version 1.02) PQ Bndry 208 Scan P153 P154 P159 P160 P161 XC4005 E/L Pad Name I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND PC 84 PQ 100 TQ 144 P78 P82 P112 P124 P162 5 P79 P113 N2 P125 P163 P114 M3 P126 P164 P83 P115 P1 P127 P165 8 11 14 P80 P81 P82 P83 P84 P1 P84 P85 P86 P87 P88 P89 P90 P91 17 20 23 26 29 32 35 38 41 - P116 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 PG 156 P2 N1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 PQ 160 P128 P131 P132 P133 P134 P135 P137 P138 P139 P140 P141 PQ Bndry 208 Scan P166 P171 P172 P173 P174 P175 P178 P179 P180 P181 P182 4/2/96 Additional No Connect (N.C.) Connections on TQ144, PG156, PQ160 & PQ208 Packages TQ144 PG156 PQ160 PQ208 P117 A4 A12 D1 D2 D16 E15 M1 M2 M15 N16 R5 R12 T12 P8 P9 P30 P31 P49 P50 P71 P72 P89 P90 P111 P112 P129 P130 P136 P152 P153 P1 P3 P10-P13 P19-P20 P31-P32 P38-P41 P51-P54 P63-P66 P72-P73 P84-P85 P91-P94 P102 P104-P105 P107 P115-P118 P124-P125 P136-P137 P143-P146 P155-P158 P167-P170 P176-P177 P188-P189 P195-P198 P206-P208 0 2 3/12/96 4-99 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4006E Devices XC4006E Pad Name PC 84 TQ 144 PG 156 PQ 160 PQ 208 Bndry Scan VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 - P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 - H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 A4 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 A12 - P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P14 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 P37 P40 P41 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 4-100 XC4006E Pad Name I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM PC 84 TQ 144 PG 156 PQ 160 PQ 208 Bndry Scan P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P67 P68 P69 P70 P71 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P86 P87 P88 P89 P90 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 176 179 182 185 188 191 194 197 198 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 - June 1, 1996 (Version 1.02) XC4006E Pad Name I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O PC 84 TQ 144 PG 156 PQ 160 PQ 208 Bndry Scan P56 P57 P58 P59 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 T16 T15 R13 P12 T14 T13 R12 T12 P11 R11 T11 T10 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P109 P110 P111 P112 P113 P114 P115 P116 P119 P120 P121 P122 295 298 301 304 307 310 313 316 319 322 325 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 R6 T4 P6 R5 T3 P5 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P123 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P138 P139 P140 P141 P142 P145 P146 P147 P148 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 376 P71 P72 P103 P104 P105 P106 R4 R3 P4 T2 P115 P116 P117 P118 P149 P150 P151 P152 379 382 385 388 P73 P74 P75 P76 P77 P78 P79 P80 - P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P171 P172 0 2 5 8 11 14 17 20 23 26 June 1, 1996 (Version 1.02) XC4006E Pad Name I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND PC 84 TQ 144 PG 156 PQ 160 PQ 208 Bndry Scan P81 P82 P83 P84 P1 P120 P121 P122 P123 P124 P125 P126 P127 L1 K3 K2 K1 J1 J2 J3 H2 P133 P134 P135 P137 P138 P139 P140 P141 P173 P174 P175 P178 P179 P180 P181 P182 29 32 35 38 41 44 47 - 4/2/96 Additional No Connect (N.C.) Connections on PQ160 & PQ208 Packages PQ160 PQ208 P136 P1 P3 P12-P13 P19-20 P31-P32 P38-P39 P51-P54 P65-P66 P72-P73 P84-P85 P91-P92 P102 P104-P105 P107 P117-P118 P124-P125 P136-P137 P143-P144 P155-P158 P169-P170 P176-P177 P188-P189 P195-P196 P206-P208 2/28/96 4-101 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4008E Devices XC4008E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O 4-102 PC 84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 PG 191 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 B11 PQ 208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 XC4008E Pad Name Bndry Scan 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O PC 84 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 PQ 160 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 PG 191 A12 B12 A13 C12 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 G16 E18 F18 G17 G18 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 T18 P17 N16 PQ 208 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P93 P94 P95 Bndry Scan 185 188 191 194 197 200 203 206 209 212 215 218 221 222 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 June 1, 1996 (Version 1.02) XC4008E Pad Name I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC PC 84 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 PQ 160 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 PG 191 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 T12 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 U5 T6 V3 V2 PQ 208 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P145 P146 P147 P148 Bndry Scan 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 P71 P72 P73 P74 P115 P116 P117 P118 P119 P120 U4 T5 U3 T4 V1 R4 P149 P150 P151 P152 P153 P154 427 430 433 436 - June 1, 1996 (Version 1.02) XC4008E Pad Name O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND PC 84 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 PQ 160 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 PG 191 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 M3 P1 N1 M2 M1 L3 L2 L1 K1 K2 K3 K4 PQ 208 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 Bndry Scan 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 - 4/2/96 Additional No Connect (N.C.) Connections on PG191 & PQ208 Packages PG191 A14 B5 B6 B13 D1 D18 F2 F17 N2 N17 R1 R18 V4 V5 V14 V15 PQ208 P1 P3 P12 P13 P38 P39 P51 P52 P53 P54 P65 P66 P91 P92 P102 P104 PQ208 P107 P117 P118 P143 P144 P155 P156 P157 P158 P169 P170 P195 P196 P206 P207 P208 P105 2/28/96 4-103 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4010E/L Devices XC4010E/L PC Pad Name 84 VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O 4-104 P2 P3 P4 P5 P6 P7 P8 P9 P10 PQ 160 TQ 176 PG 191 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 F2 D1 C1 E2 F3 D2 B1 E3 C2 B2 PQ/ BG Bndry HQ 225 Scan 208 P183 D8 P184 E8 62 P185 B7 65 P186 A7 68 P187 C7 71 P188 D7 74 P189 E7 77 P190 A6 80 P191 B6 83 P192 A5 86 P193 B5 89 P194 GND* P195 D6 92 P196 C5 95 P197 A4 98 P198 E6 101 P199 B4 104 P200 D5 107 P201 B3 110 P202 F6 113 P203 A2 116 P204 C3 119 P11 P160 P176 D3 P205 P12 P1 P1 D4 P2 P13 P2 P2 C3 P4 P14 P15 P16 P17 P18 - P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 C4 B3 C5 A2 B4 C6 A3 B5 B6 C7 A4 A5 B7 A6 C8 A7 B8 A8 B2 A1 D4 P5 B1 P6 C2 P7 E5 P8 D3 P9 C1 P10 D2 P11 G6 P12 E4 P13 D1 P14 GND* P15 F5 P16 E1 P17 F4 P18 F3 P19 G4 P20 G3 P21 G2 P22 G1 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 XC4010E/L PC Pad Name 84 PQ 160 TQ 176 PG 191 I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 - P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 B11 A12 B12 A13 C12 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 G16 E18 F18 G17 G18 H16 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 - PQ/ BG Bndry HQ 225 Scan 208 P23 G5 176 P24 H3 179 P25 H2 P26 H1 P27 H4 182 P28 H5 185 P29 J2 188 P30 J1 191 P31 J3 194 P32 J4 197 P33 K2 200 P34 K3 203 P35 J6 206 P36 L1 209 P37 GND* P38 L3 212 P39 M1 215 P40 K5 218 P41 M2 221 P42 L4 224 P43 N1 227 P44 M3 230 P45 N2 233 P46 K6 236 P47 P1 239 P48 N3 242 P49 GND* P50 P2 245 P55 R1 P56 M4 246 P57 R2 247 P58 P3 250 P59 L5 253 P60 N4 256 P61 R3 259 P62 P4 262 P63 K7 265 P64 M5 268 P65 R4 271 P66 N5 274 P67 GND* P68 R5 277 P69 M6 280 P70 N6 283 P71 P6 286 P72 R6 289 June 1, 1996 (Version 1.02) XC4010E/L PC Pad Name 84 PQ 160 TQ 176 PG 191 I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O (D5) P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 V15 V14 T12 U13 V13 U12 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 June 1, 1996 (Version 1.02) PQ/ HQ 208 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 BG Bndry 225 Scan M7 R7 L7 N8 P8 R8 M8 L8 P9 R9 N9 M9 L9 N10 K9 R11 P11 GND* R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 GND* P14 R15 M12 P15 N14 L11 M13 J10 L12 M15 L13 L14 K11 GND* K13 K14 K15 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 XC4010E/L PC Pad Name 84 I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 PQ 160 TQ 176 PG 191 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 V5 V4 U5 T6 V3 V2 PQ/ HQ 208 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 BG Bndry 225 Scan J12 J13 J14 J15 J11 H13 H14 H15 GND* H12 H11 G14 G15 G13 G12 G11 F15 F14 F13 GND* E13 D15 F11 D14 E12 C15 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 - P115 P127 U4 P149 D13 - P116 P128 T5 P150 C14 P71 P117 P129 U3 P151 F10 475 478 481 P72 P118 P130 T4 P152 B15 484 P73 P74 P75 P76 P77 P119 P120 P121 P122 P123 P131 P132 P133 P134 P135 V1 R4 U2 R3 T3 P153 P154 P159 P160 P161 C13 B14 A15 D12 A14 0 2 P78 P124 P136 U1 P162 B13 5 - P125 P137 P3 P163 E11 - P126 P138 R2 P164 C12 P79 P127 P139 T2 P165 A13 8 11 14 P80 P128 P140 N3 P166 B12 17 4-105 XC4000 Series Field Programmable Gate Arrays XC4010E/L PC Pad Name 84 I/O I/O I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND P81 P82 P83 P84 P1 PQ 160 TQ 176 PG 191 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P2 T1 R1 N2 M3 P1 N1 M2 M1 L3 L2 L1 K1 K2 K3 K4 PQ/ HQ 208 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 BG Bndry 225 Scan A12 C11 B11 E10 GND* A11 D10 A10 D9 C9 B9 A9 E9 C8 B8 A8 Additional No Connect (N.C.) Connections on PQ/ HQ208 & BG225 Packages PQ/HQ208 P1 P3 P51 P52 P53 P54 P102 P104 P105 P107 P155 P156 P157 P158 P206 P207 P208 20 23 26 29 32 35 38 41 44 47 50 53 56 59 - 4/2/96 * Pads labelled GND* are internally bonded to a Ground plane within the BG225 package. They have no direct connection to any package pin. Additional Ground (GND) Connections on BG225 Package GND F8 G7 G8 G9 H6 H7 H8 H9 H10 J7 J8 J9 K8 BG225 A3 B10 C4 C6 C10 D11 E2 E3 E14 E15 F1 F2 F7 F9 F12 G10 J5 K1 K4 K12 L2 L6 L15 M10 M14 N7 N11 N15 P5 P7 P10 R10 3/12/96 2/28/96 Note: The package pins in this table are bonded to an internal Ground plane within the BG225 package. They should all be externally connected to Ground. 4-106 June 1, 1996 (Version 1.02) Pin Locations for XC4013E/L Devices XC4013E/L Pad Name PQ 160 PQ/ HQ 208 VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D8 E8 B7 A7 C7 D7 E7 A6 B6 VCC* C6 F7 A5 B5 GND* D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 P160 P1 P2 P205 P2 P4 D3 D4 C3 B2 A1 D4 P240 P1 P2 146 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 - P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 - C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 - B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND* F5 E1 F4 F3 VCC* P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 - June 1, 1996 (Version 1.02) PG 223 BG 225 PQ/ HQ 240 Bndry Scan XC4013E/L Pad Name PQ 160 PQ/ HQ 208 PG 223 BG 225 PQ/ HQ 240 Bndry Scan I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 - P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F2 F1 G4 G3 G2 G1 G5 H3 H2 H1 H4 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND* P2 R1 M4 R2 P3 L5 N4 R3 P4 K7 M5 R4 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 294 295 298 301 304 307 310 313 316 319 4-107 XC4000 Series Field Programmable Gate Arrays XC4013E/L Pad Name PQ 160 PQ/ HQ 208 PG 223 BG 225 PQ/ HQ 240 Bndry Scan I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 P7 R7 L7 N8 P8 R8 M8 L8 P9 R9 N9 M9 L9 R10 P10 VCC* N10 K9 R11 P11 GND* M10 N11 R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 GND* P14 R15 M12 P15 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 4-108 XC4013E/L Pad Name PQ 160 PQ/ HQ 208 PG 223 BG 225 PQ/ HQ 240 Bndry Scan I/O, PGCK3 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND* L15 K12 K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 H15 GND* H12 H11 G14 G15 G13 G12 G11 F15 VCC* F14 F13 G10 E15 GND* E14 F12 E13 D15 F11 D14 E12 C15 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 P115 P149 U4 D13 P175 571 June 1, 1996 (Version 1.02) XC4013E/L Pad Name PQ 160 PQ/ HQ 208 PG 223 BG 225 PQ/ HQ 240 Bndry Scan I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND P116 P117 P150 P151 T5 U3 C14 F10 P176 P177 574 577 P118 P152 T4 B15 P178 580 P119 P120 P121 P122 P123 P153 P154 P159 P160 P161 V1 R4 U2 R3 T3 C13 B14 A15 D12 A14 P179 P180 P181 P182 P183 0 2 P124 P162 U1 B13 P184 5 P125 P126 P163 P164 P3 R2 E11 C12 P185 P186 8 11 P127 P165 T2 A13 P187 14 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 B12 F9 D11 A12 C11 B11 E10 GND* A11 D10 C10 B10 VCC* A10 D9 C9 B9 A9 E9 C8 B8 A8 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 - 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the BG225 package. They have no direct connection to any package pin. Additional Ground (GND) Connections on BG225 Packages BG225 BG225 K8 J7 J8 J9 H6 H7 H8 H9 H10 G7 G8 G9 F8 3/11/96 The BG225 package pins in this table are bonded to an internal Ground plane on the XC4013E/L die. They must all be externally connected to Ground. Additional No Connect (N.C.) Connections on PQ/ HQ208 & PQ/HQ240 Packages PQ/HQ208 PQ/HQ240 P1 P3 P51 P52 P53 P54 P102 P104 P105 P107 P155 P156 P157 P158 P206 P207 P208 P22 P37 P83 P98 P143 P158 P195 P204 P219 3/20/96 Pins marked with this symbol are reserved for Ground connections on future revisions of the device. These pins do not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible. Pads labelled VCC* are internally bonded to a Vcc plane within the BG225 package. They have no direct connection to any package pin. June 1, 1996 (Version 1.02) 4-109 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4020E Devices XC4020E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 4-110 HQ 208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 PG 223 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 A5 HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 XC4020E Pad Name Bndry Scan 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) HQ 208 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 PG 223 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 HQ 240 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 Bndry Scan 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 338 341 342 343 346 June 1, 1996 (Version 1.02) XC4020E Pad Name I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HQ 208 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 June 1, 1996 (Version 1.02) PG 223 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 HQ 240 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 Bndry Scan 349 352 355 358 361 364 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 XC4020E Pad Name I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O HQ 208 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 - PG 223 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 - HQ 240 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 - Bndry Scan 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 4-111 XC4000 Series Field Programmable Gate Arrays XC4020E Pad Name I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O 4-112 HQ 208 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 - PG 223 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 HQ 240 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 Bndry Scan 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 XC4020E Pad Name I/O VCC I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND HQ 208 P174 P175 P176 P177 P178 P179 P180 P181 P182 PG 223 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 HQ 240 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 Bndry Scan 53 56 59 62 65 68 71 74 77 80 83 - 4/2/96 Additional No Connect (N.C.) Connections on HQ208 & HQ240 Packages HQ208 HQ240 P1 P3 P51 P52 P53 P54 P102 P104 P105 P107 P155 P156 P157 P158 P206 P207 P208 P22 P37 P83 P98 P143 P158 P195 P204 P219 3/20/96 Pins marked with this symbol are reserved for Ground connections on future revisions of the device. These pins do not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible. June 1, 1996 (Version 1.02) Pin Locations for XC4025E, XC4028EX, & XC4028XL Devices XC4025E, /28EX/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O (A14) I/O, SGCK1, GCK8 (A15) VCC GND I/O, PGCK1, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O HQ 208 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan P183 P184 P185 P186 P187 P188 P189 P190 P191 - J4 J3 J2 J1 H1 H2 H3 G1 G2 - P212 P213 P214 P215 P216 P217 P218 P220 P221 - K1 K2 K3 K5 K4 J1 J2 H1 J3 J4 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 VCC* D14 C14 A15 B15 C15 D15 A16 B16 GND* C16 98 101 104 107 110 113 116 119 122 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 J5 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 C2 F5 E4 D3 C3 P28 P27 P26 P25 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P10 P9 P8 P7 P6 P5 P4 P3 P2 B17 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 GND* VCC* D20 A23 D21 C22 B24 C23 D22 C24 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 P205 P2 P4 D3 D4 C3 P240 P1 P2 A2 B1 D4 P1 VCC* P304 GND* P303 D23 194 P5 P6 P7 P8 P9 - C4 B3 C5 A2 B4 - P3 P4 P5 P6 P7 - B2 B3 E6 D5 C4 A3 P302 P301 P300 P299 P298 P297 197 200 203 206 209 212 June 1, 1996 (Version 1.02) C25 D24 E23 C26 E24 F24 XC4025E, /28EX/XL Pad Name I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O, FCLK1 I/O I/O, TMS I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O, FCLK2 GND HQ 208 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 C6 A3 B5 B6 D5 D6 C7 A4 A5 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 E9 A7 D9 B8 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 C12 D12 E12 B13 A16 A14 C13 B14 D13 A15 P296 P295 P294 P293 P292 P291 P290 P289 P288 P287 P286 P285 P284 P283 P282 P280 P279 P278 P277 P276 P275 P274 P273 P272 P271 P270 P269 P268 P267 P266 P265 P264 P263 P262 P261 P260 P259 P258 P257 P256 P255 P253 P252 P251 P250 P249 P248 E25 VCC* GND* D26 G24 F25 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* K24 J25 L24 K25 GND* L25 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 GND* T26 T25 T23 V26 VCC* U24 V25 V24 U23 GND* 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 - 4-113 XC4000 Series Field Programmable Gate Arrays XC4025E, /28EX/XL Pad Name I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O 4-114 HQ 208 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 P247 P246 P245 P244 P243 P242 P241 P240 P239 P238 P237 P236 P235 P234 P233 P232 Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383 P48 P49 P50 P55 P56 P57 C15 D15 A18 D16 C16 B17 P58 P59 P60 P61 P62 P63 A20 A19 C18 B20 D17 B19 P231 P230 P229 P228 P227 P226 AB23 GND* AD24 VCC* AC23 AE24 386 389 390 391 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 C19 F16 E17 D18 C20 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 F20 J16 G20 P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 AD23 AC22 AF24 AD22 AE23 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 XC4025E, HQ /28EX/XL 208 Pad Name I/O I/O GND I/O I/O I/O I/O I/O P74 I/O P75 I/O P76 I/O (INIT) P77 VCC P78 GND P79 I/O P80 I/O P81 I/O P82 I/O P83 I/O P84 I/O P85 I/O I/O GND I/O I/O I/O I/O VCC I/O P86 I/O P87 I/O P88 I/O P89 GND P90 I/O I/O I/O I/O I/O P91 I/O P92 I/O P93 I/O P94 GND VCC I/O I/O I/O P95 I/O P96 I/O P97 I/O P98 I/O P99 I/O, SGCK3, P100 GCK4 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 J17 H19 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19 N20 M18 M17 M16 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20 R17 T18 U19 V19 R16 T17 U18 X20 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166 P165 P164 P163 P162 P161 P160 P159 P158 P157 P156 P155 AE17 AE16 GND* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 GND* AE11 AD11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 GND* VCC* AD6 AC7 AF4 AF3 AD5 AE3 AD4 AC5 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 June 1, 1996 (Version 1.02) XC4025E, /28EX/XL Pad Name GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3, GCK5 I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, FCLK3 I/O VCC I/O (D5) I/O (CS0) GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O HQ 208 PG 223 HQ 240 PG 299 P101 P103 P106 P108 P109 P110 R16 U17 R15 V18 T15 U16 P119 P120 P121 P122 P123 P124 W20 V18 X19 U17 W19 W18 P154 GND* P153 AD3 P152 VCC* P151 AC4 P150 AD2 P149 AC3 583 586 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 U12 W13 X13 V12 W12 T11 X12 U11 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9 P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 679 682 685 688 691 694 June 1, 1996 (Version 1.02) HQ 304 BG 352 AB4 AD1 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 U2 T2 GND* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 Bndry Scan XC4025E, /28EX/XL Pad Name I/O I/O GND I/O I/O I/O (D2) I/O VCC I/O I/O, FCLK4 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4, GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O HQ 208 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 X8 V9 U9 T9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 P107 P106 P105 P104 P103 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 M4 L1 GND* L2 L3 J1 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754 P149 P150 P151 U4 T5 U3 P175 P176 P177 W4 W3 T6 U5 V4 P84 P83 P82 P81 P80 D2 F4 E3 C2 D3 757 760 763 766 769 P152 T4 P178 X1 P79 E4 772 P153 P154 P159 P160 P161 P162 V1 R4 U2 R3 T3 U1 P179 P180 P181 P182 P183 P184 V3 W1 U4 X2 W2 V2 P78 C3 P77 VCC* P76 D4 P75 GND* P74 B3 P73 C4 0 2 5 P163 P164 P165 P3 R2 T2 P185 P186 P187 R5 T4 U3 P72 P71 P70 8 11 14 P166 - N3 P4 P188 P189 V1 R4 P5 U2 P69 C6 P68 B5 P67 A4 VCC* GND* P66 C7 D5 A3 D6 17 20 23 26 4-115 XC4000 Series Field Programmable Gate Arrays XC4025E, /28EX/XL Pad Name I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND HQ 208 PG 223 HQ 240 PG 299 HQ 304 BG 352 Bndry Scan P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 L3 L2 L1 K1 K2 K3 K4 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 T3 U1 P4 R3 N5 T2 R2 T1 N4 P3 P2 N3 R1 M5 P1 M4 N2 N1 M3 M2 L5 M1 L4 L3 L2 L1 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* A9 D11 B11 A11 GND* D12 C12 B12 A12 C13 B13 A13 B14 GND* 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 - 4/2/96 Additional No Connect (N.C.) Connections on HQ208 Package N.C. P1 P3 P51 P52 P53 P54 P102 P104 P105 N.C. P107 P155 P156 P157 P158 P206 P207 P208 3/15/96 Additional Ground (GND) Connections on HQ240 Package GND P204 P219 3/21/96 The Ground (GND) package pins in the above table should be externally connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices. Additional No Connect (N.C.) Connections on HQ304 Package Pads labelled GND* are internally bonded to a Ground plane within the BG352 package. They have no direct connection to any package pin. N.C. P11 P24 P53 P100 P128 P176 P205 Pads labelled VCC* are internally bonded to a Vcc plane within the BG352 package. They have no direct connection to any package pin. Pads labelled GND should be connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices. P254 P281 3/21/96 Note: In XC4025 (no extension) devices in the HQ304 package, P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E/L and XC4028EX/XL devices. Where necessary for compatibility, this pin can be left unconnected. 4-116 June 1, 1996 (Version 1.02) Additional No Connect, Vcc & Ground Connections on BG352 Package N.C. A18 A24 B4 B10 B23 C1 C5 C8 C11 D1 D16 D25 F23 J26 K2 L4 L23 T3 T4 T24 U25 AB3 AC2 AC6 AC11 VCC A10 A17 B2 B25 D7 D13 D19 G23 H4 K1 K26 N23 P4 U1 U26 W23 Y4 AC8 AC14 AC20 AE2 AE25 AF10 AF17 AC16 AC21 AC25 AD16 AD21 AD26 AE4 AE10 GND A1 A2 A5 A8 A14 A19 A22 A25 A26 B1 B26 E1 E26 H1 H26 N1 P26 W1 W26 AB1 AB26 AE1 AE26 AF1 AF2 AF5 AF8 AF13 AF19 AF22 AF25 AF26 3/21/96 June 1, 1996 (Version 1.02) 4-117 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4036EX/XL Devices XC4036EX/XL Pad Name GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O, FCLK1 I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC 4-118 HQ304 PG411 BG432 P304 P303 P302 P301 P300 P299 P298 P297 P296 P295 P294 P293 P292 P291 P290 P289 P288 P287 P286 P285 P284 P283 P282 P280 P279 P278 P277 P276 P275 P274 P273 P272 P271 P270 P269 P268 P267 GND* H8 F6 B4 D4 B2 G9 F8 C5 A7 A5 VCC* GND* B8 C9 E9 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* B16 D16 D18 A17 E19 B18 C17 C19 GND* VCC* GND* D29 C30 E28 E29 D30 D31 E30 E31 G28 G29 VCC* GND* H28 H29 G30 H30 J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 M29 M31 N31 N28 GND* VCC* P30 P28 P29 R31 R30 R28 R29 T31 GND* VCC* Bndry Scan 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 - XC4036EX/XL Pad Name I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O, FCLK2 GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) HQ304 PG411 BG432 P266 P265 P264 P263 P262 P261 P260 P259 P258 P257 P256 P255 P253 P252 P251 P250 P249 P248 P247 P246 P245 P244 P243 P242 P241 P240 P239 P238 P237 P236 P235 P234 P233 P232 P231 P230 P229 P228 P227 F20 B20 C21 B22 E21 D22 A23 B24 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 T30 T29 U31 U30 U28 U29 V30 V29 VCC* GND* W30 W29 Y30 Y29 Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AG31 AF28 AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 Bndry Scan 326 329 332 335 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383 386 389 392 395 398 401 404 407 410 413 416 419 422 425 428 431 434 437 438 June 1, 1996 (Version 1.02) XC4036EX/XL Pad Name I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O HQ304 PG411 BG432 P226 P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 June 1, 1996 (Version 1.02) D36 C37 F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 V38 W37 VCC* GND* Y34 AC37 AB38 AK29 AH27 AK28 AJ27 AL28 AH26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 AJ16 AK16 VCC* GND* AL16 AH15 AK15 Bndry Scan 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 XC4036EX/XL Pad Name I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O HQ304 PG411 BG432 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166 P165 P164 P163 P162 P161 P160 P159 P158 P157 P156 P155 P154 P153 P152 P151 P150 P149 P148 P147 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 Bndry Scan 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 4-119 XC4000 Series Field Programmable Gate Arrays XC4036EX/XL Pad Name I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, FCLK3 I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O 4-120 HQ304 PG411 BG432 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 P107 AV36 AR33 AP32 AU35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AH1 AF4 AF3 AG2 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 Y4 Y3 W4 W3 GND* VCC* V4 V3 U1 U2 U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 R3 P2 P3 Bndry Scan 667 670 673 676 679 682 685 688 691 694 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754 757 760 763 766 769 772 775 778 781 XC4036EX/XL Pad Name I/O VCC GND I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O, FCLK4 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1, A2) P106 P105 P104 P103 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 AP18 VCC* GND* AR17 AT16 AV14 AW13 AR15 AP16 VCC* AV12 AR13 AU11 AT12 GND* AP14 AR11 AV10 AT8 AT10 AP10 AP12 AR9 GND* VCC* AU7 AW7 P4 VCC* GND* N3 N4 M1 M2 L2 L3 VCC* K1 K2 K3 K4 GND* J2 J3 J4 H1 H2 H3 H4 G2 GND* VCC* G4 F2 Bndry Scan 784 787 790 793 796 799 802 805 808 811 814 817 820 823 826 829 832 835 838 841 844 P84 P83 P82 P81 P80 P79 P78 P77 P76 P75 P74 P73 P72 P71 P70 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 F3 E1 E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 847 850 853 856 859 862 865 868 0 2 5 8 11 14 17 20 HQ304 PG411 BG432 June 1, 1996 (Version 1.02) XC4036EX/XL Pad Name I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND HQ304 PG411 BG432 P69 P68 P67 P66 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 - June 1, 1996 (Version 1.02) AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AA3 Y6 GND* VCC* W3 Y2 V4 T2 U1 V6 U3 R1 VCC* GND* D7 B6 A6 VCC* GND* D8 C7 B7 D9 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 B16 A16 GND* VCC* D17 A17 C18 D18 B18 A19 B19 C19 VCC* GND* Bndry Scan 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 - XC4036EX/XL Pad Name I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC HQ304 PG411 BG432 P29 P28 P27 P26 P25 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 U5 T4 P2 N1 R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 J3 H2 H4 G3 GND* VCC* K6 G1 E1 E3 J7 H6 C3 D2 E5 G7 VCC* D19 A20 B20 C20 C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 C27 B28 D27 B29 C28 D28 VCC* Bndry Scan 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 - 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the associated package. They have no direct connection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the associated package. They have no direct connection to any package pin. 4-121 XC4000 Series Field Programmable Gate Arrays Additional No Connect (N.C.) Connections on HQ304 Package N.C. P11 P24 P53 P100 P128 N.C. P176 P205 P254 P281 3/22/96 Additional No Connect, Vcc & Ground Connections on PG411 Package N.C. A13 B6 B34 C7 C15 C23 C25 C33 D8 D12 D30 D32 E7 E23 E37 F2 F18 F22 G5 H34 J5 K36 K38 L5 L35 N3 P38 R3 V2 W5 W35 Y38 3/26/96 N.C. AA37 AB2 AC3 AC39 AF2 AF38 AJ5 AK2 AK38 AL35 AN1 AN5 AP8 AP30 AP38 AR37 AT2 AT30 AU5 AU9 AU13 AU15 AU17 AU25 AU37 AV8 AV26 AV34 AW15 AW23 AW25 AW35 VCC A3 A11 A21 A31 C39 D6 F36 J1 L39 W1 AA39 AJ1 AL39 AP4 AT34 AU1 AW9 AW19 AW29 AW37 GND A9 A19 A29 A37 C1 D14 D20 D26 D34 F4 J39 L1 P4 P36 W39 Y4 Y36 AA1 AF4 AF36 AJ39 AL1 AP36 AT6 AT14 AT20 AT26 AU39 AW3 AW11 AW21 AW31 Additional No Connect, Vcc & Ground Connections on BG432 Package N.C. A4 A8 A15 A28 B8 B12 B17 B21 B25 C8 C16 C17 D6 D13 D20 D23 D26 E2 F1 F4 F28 F29 F30 F31 G3 M3 M4 M28 M30 N1 N2 N29 N30 V2 V28 W1 W2 W28 W31 Y1 Y31 AC4 AD2 AD30 AD31 AE4 AF29 AF30 N.C. AG1 AH6 AH9 AH19 AH23 AJ5 AJ8 AJ12 AJ15 AJ20 AJ26 AK11 AK17 AK24 AK27 AL15 AL17 VCC A1 A11 A21 A31 C3 C29 D11 D21 L1 L4 L28 L31 AA1 AA4 AA28 AA31 AH11 AH21 AJ3 AJ29 AL1 AL11 AL21 AL31 GND A2 A3 A7 A9 A14 A18 A23 A25 A29 A30 B1 B2 B30 B31 C1 C31 D16 G1 G31 J1 J31 P1 P31 T4 T28 V1 V31 AC1 AC31 AE1 AE31 AH16 AJ1 AJ31 AK1 AK2 AK30 AK31 AL2 AL3 AL7 AL9 AL14 AL18 AL23 AL25 AL29 AL30 3/22/96 4-122 June 1, 1996 (Version 1.02) Pin Locations for XC4044EX/XL Devices XC4044EX/XL Pad Name GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O, FCLK1 I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O PG411 BG432 Bndry Scan GND* H8 F6 B4 D4 B2 G9 F8 C5 A7 A5 VCC* GND* C7 D8 B8 C9 E9 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* F18 C15 B16 D16 D18 A17 E19 B18 C17 C19 GND* VCC* F20 GND* D29 C30 E28 E29 D30 D31 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 R30 R28 R29 T31 GND* VCC* T30 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 338 341 344 347 350 353 356 359 362 June 1, 1996 (Version 1.02) XC4044EX/XL Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O, FCLK2 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) PG411 BG432 Bndry Scan B20 C21 B22 E21 D22 A23 B24 C23 F22 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 D30 D32 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 D36 C37 T29 U31 U30 U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 Y30 Y29 Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AG31 AF28 AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 365 368 371 374 377 380 383 386 389 392 395 398 401 404 407 410 413 416 419 422 425 428 431 434 437 440 443 446 449 452 455 458 461 464 467 470 473 476 479 482 485 486 487 490 4-123 XC4000 Series Field Programmable Gate Arrays XC4044EX/XL Pad Name I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O 4-124 PG411 BG432 Bndry Scan F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 K36 K38 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 W35 AC39 V38 W37 VCC* GND* Y34 AC37 Y38 AA37 AB38 AD36 AK28 AJ27 AL28 AH26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 AK15 AJ14 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 619 622 XC4044EX/XL Pad Name I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O PG411 BG432 Bndry Scan AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK38 AP38 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 AP32 AU35 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 AF3 AG2 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 679 682 685 688 691 694 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 June 1, 1996 (Version 1.02) XC4044EX/XL Pad Name I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, FCLK3 I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O I/O I/O VCC GND PG411 BG432 Bndry Scan AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AP30 AT30 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AW25 AW23 AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AP18 AU17 AW15 VCC* GND* AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 Y4 Y3 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 R3 P2 P3 P4 N1 N2 VCC* GND* 751 754 757 760 763 766 769 772 775 778 781 784 787 790 793 796 799 802 805 808 811 814 817 820 823 826 829 832 835 838 841 844 847 850 853 856 859 862 865 868 871 874 - June 1, 1996 (Version 1.02) XC4044EX/XL Pad Name I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O, FCLK4 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND PG411 BG432 Bndry Scan AR17 AT16 AV14 AW13 AR15 AP16 VCC* AV12 AR13 AU11 AT12 GND* AP14 AR11 AV10 AT8 AT10 AP10 AP12 AR9 AU9 AV8 GND* VCC* AU7 AW7 N3 N4 M1 M2 L2 L3 VCC* K1 K2 K3 K4 GND* J2 J3 J4 H1 H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 877 880 883 886 889 892 895 898 901 904 907 910 913 916 919 922 925 928 931 934 937 940 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 F3 E1 E3 D1 E4 D2 C2 D3 943 946 949 952 955 958 961 964 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 D7 B6 A6 VCC* GND* 0 2 5 8 11 14 17 20 23 26 29 - 4-125 XC4000 Series Field Programmable Gate Arrays XC4044EX/XL Pad Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O 4-126 PG411 BG432 Bndry Scan AL3 AH6 AP2 AK4 AN1 AK2 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AB2 AC3 AA3 Y6 GND* VCC* W3 Y2 V2 W5 V4 T2 U1 V6 U3 R1 VCC* GND* U5 T4 P2 N1 D8 C7 B7 D9 B8 A8 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 A15 C16 B16 A16 GND* VCC* D17 A17 C17 B17 C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 XC4044EX/XL Pad Name I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC PG411 BG432 Bndry Scan R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 L5 J5 J3 H2 H4 G3 GND* VCC* K6 G1 E1 E3 J7 H6 C3 D2 E5 G7 VCC* C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 C27 B28 D27 B29 C28 D28 VCC* 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 - 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the associated package. They have no direct connection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the associated package. They have no direct connection to any package pin. June 1, 1996 (Version 1.02) Additional No Connect, Vcc & Ground Connections on PG411 Package N.C. A13 B6 B34 C25 C33 D12 E7 E23 E37 F2 G5 H34 L35 N3 P38 R3 AF2 AF38 AJ5 AL35 AN5 VCC A3 A11 A21 A31 C39 D6 F36 J1 L39 W1 AA39 AJ1 AL39 AP4 AT34 AU1 AW9 AW19 AW29 AW37 AP8 AR37 AT2 AU5 AU13 AU15 AU25 AU37 AV26 AV34 AW35 Additional No Connect, Vcc & Ground Connections on BG432 Package N.C. A4 A28 B12 B21 C8 D6 D13 D20 D26 E2 F4 F28 F29 M3 M4 M28 M30 W1 W28 Y1 Y31 AE4 AF29 AF30 AG1 AH6 AH19 AJ5 AJ12 AJ20 AJ26 AK11 AK27 GND A9 A19 A29 A37 C1 D14 D20 D26 D34 F4 J39 L1 P4 P36 W39 Y4 Y36 AA1 AF4 AF36 AJ39 AL1 AP36 AT6 AT14 AT20 AT26 AU39 AW3 AW11 AW21 AW31 3/22/96 VCC A1 A11 A21 A31 C3 C29 D11 D21 L1 L4 L28 L31 AA1 AA4 AA28 AA31 AH11 AH21 AJ3 AJ29 AL1 AL11 AL21 AL31 GND A2 A3 A7 A9 A14 A18 A23 A25 A29 A30 B1 B2 B30 B31 C1 C31 D16 G1 G31 J1 J31 P1 P31 T4 T28 V1 V31 AC1 AC31 AE1 AE31 AH16 AJ1 AJ31 AK1 AK2 AK30 AK31 AL2 AL3 AL7 AL9 AL14 AL18 AL23 AL25 AL29 AL30 3/26/96 June 1, 1996 (Version 1.02) 4-127 XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4052XL Devices XC4052XL Pad Name GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O, FCLK1 I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND 4-128 BG432 GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* Bndry Scan 266 269 272 275 278 281 284 287 290 293 296 299 302 305 308 311 314 317 320 323 326 329 332 335 338 341 344 347 350 353 356 359 362 365 368 371 374 377 380 383 - XC4052XL Pad Name I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O, FCLK2 GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O BG432 R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 Bndry Scan 386 389 392 395 398 401 404 407 410 413 416 419 422 425 428 431 434 437 440 443 446 449 452 455 458 461 464 467 470 473 476 479 482 485 488 491 494 497 500 503 506 June 1, 1996 (Version 1.02) XC4052XL Pad Name I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O June 1, 1996 (Version 1.02) BG432 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 Bndry Scan 509 512 515 518 521 524 527 530 533 534 535 538 541 544 547 550 553 556 559 562 565 568 571 574 577 580 583 586 589 592 595 598 601 604 607 610 613 616 619 622 625 628 XC4052XL Pad Name I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O BG432 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 Bndry Scan 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 679 682 685 688 691 694 697 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 4-129 XC4000 Series Field Programmable Gate Arrays XC4052XL Pad Name I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O 4-130 BG432 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 Bndry Scan 754 757 760 763 766 769 772 775 778 781 784 787 790 793 796 799 802 805 808 811 814 817 820 823 826 829 832 835 838 841 844 847 850 853 856 859 862 865 868 871 XC4052XL Pad Name I/O, FCLK3 I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC I/O I/O, FCLK4 BG432 AB1 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC* K1 K2 Bndry Scan 874 877 880 883 886 889 892 895 898 901 904 907 910 913 916 919 922 925 928 931 934 937 940 943 946 949 952 955 958 961 964 967 970 973 976 979 982 985 988 991 June 1, 1996 (Version 1.02) XC4052XL Pad Name I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O June 1, 1996 (Version 1.02) BG432 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 Bndry Scan 994 997 1000 1003 1006 1009 1012 1015 1018 1021 1024 1027 1030 1033 1036 1039 1042 1045 1048 1051 1054 1057 1060 1063 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 XC4052XL Pad Name I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O BG432 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND* VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 Bndry Scan 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 4-131 XC4000 Series Field Programmable Gate Arrays XC4052XL Pad Name I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC BG432 B20 C20 B21 D20 GND* C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* Bndry Scan 170 173 176 179 182 185 188 191 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 - Additional No Connect, Vcc & Ground Connections on BG432 Package N.C. C8 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the associated package. They have no direct connection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the associated package. They have no direct connection to any package pin. VCC A1 A11 A21 A31 C3 C29 D11 D21 L1 L4 L28 L31 AA1 AA4 AA28 AA31 AH11 AH21 AJ3 AJ29 AL1 AL11 AL21 AL31 GND A2 A3 A7 A9 A14 A18 A23 A25 A29 A30 B1 B2 B30 B31 C1 C31 D16 G1 G31 J1 J31 P1 P31 T4 T28 V1 V31 AC1 AC31 AE1 AE31 AH16 AJ1 AJ31 AK1 AK2 AK30 AK31 AL2 AL3 AL7 AL9 AL14 AL18 AL23 AL25 AL29 AL30 3/22/96 4-132 June 1, 1996 (Version 1.02) Package-Specific Pinout Tables PC84 Package Pinouts Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 XC4005E XC4006E XC4008E XC4005L GND GND GND GND VCC VCC VCC VCC I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O, I/O, I/O, I/O, SGCK1 SGCK1 SGCK1 SGCK1 (A15) (A15) (A15) (A15) VCC VCC VCC VCC GND GND GND GND I/O, I/O, I/O, I/O, PGCK1 PGCK1 PGCK1 PGCK1 (A16) (A16) (A16) (A16) I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, SCGK2 SCGK2 SCGK2 SCGK2 O (M1) O (M1) O (M1) O (M1) GND GND GND GND I (M0) I (M0) I (M0) I (M0) VCC VCC VCC VCC I (M2) I (M2) I (M2) I (M2) I/O, I/O, I/O, I/O, PGCK2 PGCK2 PGCK2 PGCK2 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) VCC VCC VCC VCC GND GND GND GND I/O I/O I/O I/O XC4003E June 1, 1996 (Version 1.02) XC4010E XC4010L GND VCC I/O (A8) I/O (A9) I/O (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O (LDC) I/O I/O I/O I/O (INIT) VCC GND I/O Pin XC4003E P45 P46 P47 P48 P49 P50 P51 I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O (D5) I/O (CS0) I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O (A6) I/O (A7) P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 XC4005E XC4005L I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O (D5) I/O (CS0) I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O (A6) I/O (A7) XC4006E XC4008E I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O (D5) I/O (CS0) I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O (A6) I/O (A7) I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O (D5) I/O (CS0) I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O (A6) I/O (A7) XC4010E XC4010L I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O (D5) I/O (CS0) I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O (A6) I/O (A7) 2/28/96 4-133 XC4000 Series Field Programmable Gate Arrays PQ100 Package Pinouts PQ100 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 4-134 XC4003E I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 XC4005E I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 PQ100 Pin XC4003E XC4005E P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 2/28/96 June 1, 1996 (Version 1.02) VQ100 Package Pinouts VQ100 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 June 1, 1996 (Version 1.02) XC4003E GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC VQ100 Pin P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 XC4003E PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) I/O, SGCK1 (A15) VCC 2/28/96 4-135 XC4000 Series Field Programmable Gate Arrays PG120 Package Pinouts PG120 Pin N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 K13 K12 K11 K3 K2 K1 J13 4-136 XC4003E I/O, PGCK3 N.C. I/O I/O (CS0) I/O I/O I/O (D3) I/O (RS) I/O I/O I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, PGCK4 (A1) I/O PROGRAM I/O (D7) I/O (D6) I/O (D5) I/O (D4) VCC I/O I/O (D1) N.C. I/O, SGCK4 (DOUT) O, TDO N.C. I/O I/O, SGCK3 DONE VCC N.C. I/O GND I/O (D2) N.C. CCLK VCC I/O (A0, WS) I/O (A3) I/O N.C. GND GND I/O (CS1, A2) I/O (A5) I/O PG120 Pin J12 J11 J3 J2 J1 H13 H12 H11 H3 H2 H1 G13 G12 G11 G3 G2 G1 F13 F12 F11 F3 F2 F1 E13 E12 E11 E3 E2 E1 D13 D12 D11 D3 D2 D1 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 XC4003E I/O N.C. N.C. I/O (A4) I/O I/O I/O I/O I/O I/O (A6) I/O (A7) I/O VCC GND VCC GND I/O (A8) I/O (INIT) I/O I/O I/O (A10) I/O I/O (A9) I/O I/O N.C. N.C. N.C. I/O I/O I/O VCC I/O, SGCK1 (A15) I/O (A13) I/O (A11) I/O (LDC) I/O, PGCK2 I (M0) GND I/O I/O VCC I/O I/O, TDI GND VCC I/O (A14) I/O (A12) June 1, 1996 (Version 1.02) PG120 Pin B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A13 A12 A11 June 1, 1996 (Version 1.02) XC4003E N.C. I (M2) O (M1) N.C. I/O I/O GND I/O I/O, TMS I/O, TCK I/O (A17) I/O, PGCK1 (A16) N.C. I/O (HDC) I/O, SCGK2 I/O PG120 Pin A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 XC4003E I/O I/O I/O I/O I/O I/O I/O N.C. N.C. N.C. 3/13/96 Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-137 XC4000 Series Field Programmable Gate Arrays TQ144 Package Pinouts TQ144 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 4-138 XC4005E GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O XC4006E GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O TQ144 Pin P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 XC4005E I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O XC4006E I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O June 1, 1996 (Version 1.02) TQ144 Pin P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 XC4005E XC4006E I/O I/O I/O (D2) I/O (D2) I/O I/O I/O I/O I/O I/O GND GND I/O (D1) I/O (D1) I/O (RCLK, I/O (RCLK, RDY/BUSY) RDY/BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O (D0, DIN) I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT) CCLK CCLK VCC VCC O, TDO O, TDO GND GND I/O (A0, WS) I/O (A0, WS) I/O, PGCK4 (A1) I/O, PGCK4 (A1) I/O I/O I/O I/O I/O (CS1, A2) I/O (CS1, A2) I/O (A3) I/O (A3) N.C. I/O GND GND I/O I/O I/O I/O I/O (A4) I/O (A4) I/O (A5) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A6) I/O (A7) I/O (A7) GND GND VCC VCC I/O (A8) I/O (A8) I/O (A9) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A10) I/O (A11) I/O (A11) I/O I/O I/O I/O GND GND I/O (A12) I/O (A12) I/O (A13) I/O (A13) I/O I/O I/O I/O June 1, 1996 (Version 1.02) TQ144 Pin P142 P143 P144 XC4005E I/O (A14) I/O, SGCK1 (A15) VCC XC4006E I/O (A14) I/O, SGCK1 (A15) VCC 2/28/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. 4-139 XC4000 Series Field Programmable Gate Arrays PG156 Package Pinouts PG156 Pin T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 4-140 XC4005E XC4006E O, TDO O, TDO I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT) I/O (D1) I/O (D1) I/O I/O I/O I/O I/O I/O I/O (RS) I/O (RS) I/O (D3) I/O (D3) I/O I/O I/O (D5) I/O (D5) I/O I/O N.C. I/O I/O I/O I/O (D6) I/O (D6) I/O, PGCK3 I/O, PGCK3 I/O (D7) I/O (D7) I/O (A0, WS) I/O (A0, WS) CCLK CCLK I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O VCC VCC I/O (D4) I/O (D4) I/O I/O I/O I/O N.C. I/O I/O I/O PROGRAM PROGRAM DONE DONE I/O, SGCK3 I/O, SGCK3 I/O (CS1, A2) I/O (CS1, A2) I/O, PGCK4 (A1) I/O, PGCK4 (A1) VCC VCC I/O (D0, DIN) I/O (D0, DIN) I/O (RCLK, I/O (RCLK, RDY/BUSY) RDY/BUSY) GND GND I/O (D2) I/O (D2) GND GND I/O I/O I/O (CS0) I/O (CS0) GND GND I/O I/O VCC VCC PG156 Pin P14 P15 P16 N1 N2 N3 N14 N15 N16 M1 M2 M3 M14 M15 M16 L1 L2 L3 L14 L15 L16 K1 K2 K3 K14 K15 K16 J1 J2 J3 J14 J15 J16 H1 H2 H3 H14 H15 H16 G1 G2 G3 G14 G15 G16 F1 F2 F3 XC4005E GND I/O I/O I/O (A3) I/O GND I/O I/O N.C. N.C. N.C. I/O I/O N.C. I/O I/O I/O GND GND I/O I/O I/O I/O (A5) I/O (A4) I/O I/O I/O I/O I/O (A6) I/O (A7) GND I/O I/O I/O (A8) GND VCC VCC I/O (INIT) I/O I/O (A9) I/O I/O I/O I/O I/O I/O (A10) I/O (A11) GND XC4006E GND I/O I/O I/O (A3) I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O (A5) I/O (A4) I/O I/O I/O I/O I/O (A6) I/O (A7) GND I/O I/O I/O (A8) GND VCC VCC I/O (INIT) I/O I/O (A9) I/O I/O I/O I/O I/O I/O (A10) I/O (A11) GND June 1, 1996 (Version 1.02) PG156 Pin F14 F15 F16 E1 E2 E3 E14 E15 E16 D1 D2 D3 D14 D15 D16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 A1 XC4005E GND I/O I/O I/O I/O I/O (A12) I/O N.C. I/O N.C. N.C. I/O I/O (HDC) I/O N.C. I/O (A13) I/O VCC GND I/O GND I/O GND I/O I/O GND I/O GND VCC I/O I/O (LDC) I/O (A14) I/O, SGCK1 (A15) I/O, PGCK1 (A16) I/O, TDI I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O, SCGK2 I (M2) I/O, PGCK2 I/O (A17) June 1, 1996 (Version 1.02) XC4006E GND I/O I/O I/O I/O I/O (A12) I/O I/O I/O I/O I/O I/O I/O (HDC) I/O I/O I/O (A13) I/O VCC GND I/O GND I/O GND I/O I/O GND I/O GND VCC I/O I/O (LDC) I/O (A14) I/O, SGCK1 (A15) I/O, PGCK1 (A16) I/O, TDI I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O, SCGK2 I (M2) I/O, PGCK2 I/O (A17) PG156 Pin A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 XC4005E I/O I/O, TCK N.C. I/O, TMS I/O I/O I/O I/O I/O I/O N.C. I/O I/O O (M1) I (M0) XC4006E I/O I/O, TCK I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O O (M1) I (M0) 2/28/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-141 XC4000 Series Field Programmable Gate Arrays PQ160 Package Pinouts PQ 160 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 4-142 XC4005E XC4006E XC4008E XC4010E XC4013E GND GND GND GND GND I/O, I/O, I/O, I/O, I/O, PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 (A16) (A16) (A16) (A16) (A16) I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND VCC VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, I/O, SCGK2 SCGK2 SCGK2 SCGK2 SCGK2 O (M1) O (M1) O (M1) O (M1) O (M1) GND GND GND GND GND I (M0) I (M0) I (M0) I (M0) I (M0) VCC VCC VCC VCC VCC I (M2) I (M2) I (M2) I (M2) I (M2) I/O, I/O, I/O, I/O, I/O, PGCK2 PGCK2 PGCK2 PGCK2 PGCK2 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PQ 160 Pin P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 XC4005E XC4006E XC4008E XC4010E XC4013E I/O I/O I/O I/O I/O I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) VCC VCC VCC VCC VCC GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, I/O, SGCK3 SGCK3 SGCK3 SGCK3 SGCK3 GND GND GND GND GND DONE DONE DONE DONE DONE VCC VCC VCC VCC VCC PROPROPROPROPROGRAM GRAM GRAM GRAM GRAM I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O, I/O, I/O, I/O, I/O, PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) June 1, 1996 (Version 1.02) PQ 160 XC4005E XC4006E Pin P96 I/O I/O P97 I/O I/O P98 I/O (D4) I/O (D4) P99 I/O I/O P100 VCC VCC P101 GND GND P102 I/O (D3) I/O (D3) P103 I/O (RS) I/O (RS) P104 I/O I/O P105 I/O I/O P106 I/O (D2) I/O (D2) P107 I/O I/O P108 I/O I/O P109 I/O I/O P110 GND GND P111 N.C. I/O P112 N.C. I/O P113 I/O (D1) I/O (D1) P114 I/O (RCLK, I/O (RCLK, RDY/ RDY/ BUSY) BUSY) P115 I/O I/O P116 I/O I/O P117 I/O I/O (D0, DIN) (D0, DIN) P118 I/O, I/O, SGCK4 SGCK4 (DOUT) (DOUT) P119 CCLK CCLK P120 VCC VCC P121 O, TDO O, TDO P122 GND GND I/O P123 I/O (A0, WS) (A0, WS) P124 I/O, I/O, PGCK4 PGCK4 (A1) (A1) P125 I/O I/O P126 I/O I/O P127 I/O I/O (CS1, A2) (CS1, A2) P128 I/O (A3) I/O (A3) P129 N.C. I/O P130 N.C. I/O P131 GND GND P132 I/O I/O P133 I/O I/O P134 I/O (A4) I/O (A4) P135 I/O (A5) I/O (A5) P136 N.C. N.C. P137 I/O I/O P138 I/O I/O P139 I/O (A6) I/O (A6) XC4008E XC4010E XC4013E I/O I/O I/O I/O I/O I/O I/O (D4) I/O (D4) I/O (D4) I/O I/O I/O VCC VCC VCC GND GND GND I/O (D3) I/O (D3) I/O (D3) I/O (RS) I/O (RS) I/O (RS) I/O I/O I/O I/O I/O I/O I/O (D2) I/O (D2) I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (D1) I/O (D1) I/O (RCLK, I/O (RCLK, I/O (RCLK, RDY/ RDY/ RDY/ BUSY) BUSY) BUSY) I/O I/O I/O I/O I/O I/O I/O I/O I/O (D0, DIN) (D0, DIN) (D0, DIN) June 1, 1996 (Version 1.02) I/O, I/O, I/O, SGCK4 SGCK4 SGCK4 (DOUT) (DOUT) (DOUT) CCLK CCLK CCLK VCC VCC VCC O, TDO O, TDO O, TDO GND GND GND I/O I/O I/O (A0, WS) (A0, WS) (A0, WS) I/O, I/O, I/O, PGCK4 PGCK4 PGCK4 (A1) (A1) (A1) I/O I/O I/O I/O I/O I/O I/O I/O I/O (CS1, A2) (CS1, A2) (CS1, A2) I/O (A3) I/O (A3) I/O (A3) I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O (A4) I/O (A4) I/O (A4) I/O (A5) I/O (A5) I/O (A5) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A6) I/O (A6) I/O (A6) PQ 160 XC4005E XC4006E XC4008E XC4010E XC4013E Pin P140 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) P141 GND GND GND GND GND P142 VCC VCC VCC VCC VCC P143 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) P144 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) P145 I/O I/O I/O I/O I/O P146 I/O I/O I/O I/O I/O P147 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10) P148 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11) P149 I/O I/O I/O I/O I/O P150 I/O I/O I/O I/O I/O P151 GND GND GND GND GND P152 N.C. I/O I/O I/O I/O P153 N.C. I/O I/O I/O I/O P154 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12) P155 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13) P156 I/O I/O I/O I/O I/O P157 I/O I/O I/O I/O I/O P158 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14) P159 I/O, I/O, I/O, I/O, I/O, SGCK1 SGCK1 SGCK1 SGCK1 SGCK1 (A15) (A15) (A15) (A15) (A15) P160 VCC VCC VCC VCC VCC 2/28/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. 4-143 XC4000 Series Field Programmable Gate Arrays TQ176 Package Pinouts TQ176 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 4-144 XC4010L GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SCGK2 O (M1) GND I (M0) VCC I (M2) TQ176 Pin P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 XC4010L I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O June 1, 1996 (Version 1.02) TQ176 Pin P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 June 1, 1996 (Version 1.02) XC4010L I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O TQ176 Pin P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 XC4010L GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC 3/15/96 PG191 Package Pinouts (see PG223) The PG191 package pinout has been combined with the PG223 in a single table, because of their physical compatibility. The PG191 has the same dimensions as the PG223, but has 32 fewer pins on the inner ring. 4-145 XC4000 Series Field Programmable Gate Arrays PQ208, HQ208 Package Pinouts PQ 208 Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 4-146 XC XC XC XC XC XC XC 4005 4006 4008 4010 4013 4020 4028 E/L E E E/L E/L E EX/XL N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND GND GND GND GND GND GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. I/O, I/O, I/O, I/O, I/O, I/O, I/O, PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 GCK1 (A16) (A16) (A16) (A16) (A16) (A16) (A16) I/O I/O I/O I/O I/O I/O I/O (A17) (A17) (A17) (A17) (A17) (A17) (A17) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, I/O, I/O, I/O, I/O, I/O, I/O, TCK TCK TCK TCK TCK TCK TCK N.C. I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O, FCLK1 I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, I/O, I/O, I/O, TMS TMS TMS TMS TMS TMS TMS I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, FCLK2 GND GND GND GND GND GND GND N.C. N.C. N.C. I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PQ 208 Pin P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 XC 4005 E/L I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) N.C. N.C. N.C. N.C. GND I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O GND N.C. XC 4006 E I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O N.C. N.C. GND I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O GND N.C. XC 4008 E I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O N.C. N.C. GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND N.C. XC 4010 E/L I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O XC 4013 E/L I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O XC 4020 E I/O I/O I/O, SGCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O XC 4028 EX/XL I/O I/O I/O, GCK2 O (M1) GND I (M0) N.C. N.C. N.C. N.C. VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O June 1, 1996 (Version 1.02) PQ 208 Pin P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 XC XC XC XC XC XC XC 4005 4006 4008 4010 4013 4020 4028 E/L E E E/L E/L E EX/XL N.C. N.C. N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, I/O, I/O, I/O, SGCK3 SGCK3 SGCK3 SGCK3 SGCK3 SGCK3 GCK4 GND GND GND GND GND GND GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. DONE DONE DONE DONE DONE DONE DONE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC VCC VCC VCC VCC VCC VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. PRO- PRO- PRO- PRO- PRO- PRO- PROGRAM GRAM GRAM GRAM GRAM GRAM GRAM I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O, I/O, I/O, I/O, I/O, I/O, I/O, PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 GCK5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O, FCLK3 I/O I/O I/O I/O I/O I/O I/O I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O I/O I/O I/O I/O I/O I/O (CS0) (CS0) (CS0) (CS0) (CS0) (CS0) (CS0) N.C. N.C. I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O I/O I/O I/O I/O I/O I/O VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O I/O I/O I/O I/O I/O I/O (RS) (RS) (RS) (RS) (RS) (RS) (RS) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O June 1, 1996 (Version 1.02) PQ XC XC XC XC XC XC XC 208 4005 4006 4008 4010 4013 4020 4028 Pin E/L E E E/L E/L E EX/XL P138 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) P139 I/O I/O I/O I/O I/O I/O I/O P140 I/O I/O I/O I/O I/O I/O I/O P141 I/O I/O I/O I/O I/O I/O I/O, FCLK4 P142 GND GND GND GND GND GND GND P143 N.C. N.C. N.C. I/O I/O I/O I/O P144 N.C. N.C. N.C. I/O I/O I/O I/O P145 N.C. I/O I/O I/O I/O I/O I/O P146 N.C. I/O I/O I/O I/O I/O I/O P147 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O I/O I/O I/O I/O I/O P148 I/O (RCLK, (RCLK, (RCLK, (RCLK, (RCLK, (RCLK, (RCLK, RDY/ RDY/ RDY/ RDY/ RDY/ RDY/ RDY/ BUSY) BUSY) BUSY) BUSY) BUSY) BUSY) BUSY) P149 I/O I/O I/O I/O I/O I/O I/O P150 I/O I/O I/O I/O I/O I/O I/O P151 I/O I/O I/O I/O I/O I/O I/O (D0, (D0, (D0, (D0, (D0, (D0, (D0, DIN) DIN) DIN) DIN) DIN) DIN) DIN) P152 I/O, I/O, I/O, I/O, I/O, I/O, I/O, SGCK SGCK4 SGCK4 SGCK4 SGCK4 SGCK4 GCK6 (DOUT) (DOUT) (DOUT) (DOUT) (DOUT) (DOUT) (DOUT) P153 CCLK CCLK CCLK CCLK CCLK CCLK CCLK P154 VCC VCC VCC VCC VCC VCC VCC P155 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P156 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P157 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P158 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P159 O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO P160 GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O P161 I/O (A0, (A0, (A0, (A0, (A0, (A0, (A0, WS) WS) WS) WS) WS) WS) WS) P162 I/O, I/O, I/O, I/O, I/O, I/O, I/O, PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 GCK7 (A1) (A1) (A1) (A1) (A1) (A1) (A1) P163 I/O I/O I/O I/O I/O I/O I/O P164 I/O I/O I/O I/O I/O I/O I/O P165 I/O I/O I/O I/O I/O I/O I/O (CS1, (CS1, (CS1, (CS1, (CS1, (CS1, (CS1, A2) A2) A2) A2) A2) A2) A2) P166 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) P167 N.C. I/O I/O I/O I/O I/O I/O P168 N.C. I/O I/O I/O I/O I/O I/O P169 N.C. N.C. N.C. I/O I/O I/O I/O P170 N.C. N.C. N.C. I/O I/O I/O I/O P171 GND GND GND GND GND GND GND P172 I/O I/O I/O I/O I/O I/O I/O P173 I/O I/O I/O I/O I/O I/O I/O P174 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) P175 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) P176 N.C. N.C. I/O I/O I/O I/O I/O P177 N.C. N.C. I/O I/O I/O I/O I/O 4-147 XC4000 Series Field Programmable Gate Arrays PQ 208 Pin P178 XC 4005 E/L I/O XC 4006 E I/O XC 4008 E I/O XC 4010 E/L I/O XC 4013 E/L I/O XC 4020 E I/O P179 I/O I/O I/O I/O I/O I/O P180 P181 P182 P183 P184 P185 P186 I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O P187 I/O I/O I/O I/O I/O I/O P188 P189 P190 N.C. N.C. I/O (A10) I/O (A11) I/O I/O GND N.C. N.C. N.C. I/O (A10) I/O (A11) I/O I/O GND N.C. I/O I/O I/O (A10) I/O (A11) I/O I/O GND N.C. I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O P191 P192 P193 P194 P195 4-148 XC 4028 EX/XL I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O PQ 208 Pin P196 P197 P198 P199 P200 P201 P202 P203 P204 XC 4005 E/L N.C. N.C. N.C. I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) XC 4006 E N.C. I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) XC 4008 E N.C. I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC N.C. N.C. N.C. VCC N.C. N.C. N.C. VCC N.C. N.C. N.C. P205 P206 P207 P208 XC 4010 E/L I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC N.C. N.C. N.C. XC 4013 E/L I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC N.C. N.C. N.C. XC 4020 E I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC N.C. N.C. N.C. XC 4028 EX/XL I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, GCK8 (A15) VCC N.C. N.C. N.C. 3/13/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. June 1, 1996 (Version 1.02) PG223 and PG191 Package Pinouts These two packages have been combined into a single table because of their physical compatibility. The PG191 has the same dimensions as the PG223, but has 32 fewer pins on the inner ring. PG 223 Pin V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 T1 T2 PG XC4008E 191 PG191 Pin V1 CCLK V2 I/O (RCLK, RDY/ BUSY) V3 I/O (D1) V4 N.C. V5 N.C. V6 I/O V7 I/O (D2) V8 I/O V9 I/O V10 I/O V11 I/O V12 I/O (CS0) V13 I/O V14 N.C. V15 N.C. V16 I/O V17 I/O (D6) V18 PROGRAM U1 I/O, PGCK4 (A1) U2 O, TDO U3 I/O (D0, DIN) U4 I/O U5 I/O U6 I/O U7 I/O U8 I/O U9 I/O (RS) U10 I/O (D4) U11 I/O U12 I/O (D5) U13 I/O U14 I/O U15 I/O U16 I/O, PGCK3 U17 DONE U18 I/O T1 I/O T2 I/O (CS1,A2) XC4010E XC4013E XC4020E XC4025E PG191 PG223 PG223 PG223 CCLK I/O (RCLK, RDY/ BUSY) I/O (D1) I/O I/O I/O I/O (D2) I/O I/O I/O I/O I/O (CS0) I/O I/O I/O I/O I/O (D6) PROGRAM I/O, PGCK4 (A1) O, TDO I/O (D0, DIN) I/O I/O I/O I/O I/O I/O (RS) I/O (D4) I/O I/O (D5) I/O I/O I/O I/O, PGCK3 DONE I/O I/O I/O (CS1,A2) June 1, 1996 (Version 1.02) CCLK I/O (RCLK, RDY/ BUSY) I/O (D1) I/O I/O I/O I/O (D2) I/O I/O I/O I/O I/O (CS0) I/O I/O I/O I/O I/O (D6) PROGRAM I/O, PGCK4 (A1) O, TDO I/O (D0, DIN) I/O I/O I/O I/O I/O I/O (RS) I/O (D4) I/O I/O (D5) I/O I/O I/O I/O, PGCK3 DONE I/O I/O I/O (CS1,A2) CCLK I/O (RCLK, RDY/ BUSY) I/O (D1) I/O I/O I/O I/O (D2) I/O I/O I/O I/O I/O (CS0) I/O I/O I/O I/O I/O (D6) PROGRAM I/O, PGCK4 (A1) O, TDO I/O (D0, DIN) I/O I/O I/O I/O I/O I/O (RS) I/O (D4) I/O I/O (D5) I/O I/O I/O I/O, PGCK3 DONE I/O I/O I/O (CS1,A2) CCLK I/O (RCLK, RDY/ BUSY) I/O (D1) I/O I/O I/O I/O (D2) I/O I/O I/O I/O I/O (CS0) I/O I/O I/O I/O I/O (D6) PROGRAM I/O, PGCK4 (A1) O, TDO I/O (D0, DIN) I/O I/O I/O I/O I/O I/O (RS) I/O (D4) I/O I/O (D5) I/O I/O I/O I/O, PGCK3 DONE I/O I/O I/O (CS1,A2) PG 223 Pin T3 T5 T6 T7 T8 T9 T10 T11 T12 T13 PG XC4008E 191 PG191 Pin T3 I/O (A0, WS) T4 I/O, SGCK4 (DOUT) T5 I/O T6 I/O T7 GND T8 I/O T9 I/O (D3) T10 I/O T11 I/O T12 GND T13 I/O T14 T15 T16 T14 T15 T16 T17 T18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 P1 P2 P3 P4 P15 P16 P17 P18 N1 N2 N3 N4 N15 N16 T17 T18 R1 R2 R3 R4 I/O I/O (D7) I/O, SGCK3 I/O I/O N.C. I/O GND VCC R9 R10 GND VCC GND VCC R15 R16 R17 R18 P1 P2 P3 VCC GND I/O N.C. I/O I/O I/O VCC GND I/O I/O I/O I/O I/O P16 P17 P18 N1 N2 N3 I/O I/O I/O I/O N.C. I/O (A3) I/O I/O I/O I/O I/O I/O (A3) N16 I/O I/O T4 XC4010E XC4013E XC4020E XC4025E PG191 PG223 PG223 PG223 I/O I/O I/O (A0, WS) (A0, WS) (A0, WS) I/O, I/O, I/O, SGCK4 SGCK4 SGCK4 (DOUT) (DOUT) (DOUT) I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (D3) I/O (D3) I/O (D3) I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (A0, WS) I/O, SGCK4 (DOUT) I/O I/O GND I/O I/O (D3) I/O I/O GND I/O I/O I/O (D7) I/O, SGCK3 I/O I/O I/O I/O GND VCC I/O I/O (D7) I/O, SGCK3 I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A3) I/O I/O I/O I/O I/O (D7) I/O, SGCK3 I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A3) I/O I/O I/O I/O I/O (D7) I/O, SGCK3 I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A3) I/O I/O I/O 4-149 XC4000 Series Field Programmable Gate Arrays PG 223 Pin N17 N18 M1 M2 M3 M4 M15 M16 M17 M18 L1 L2 L3 L4 L15 L16 L17 L18 K1 K2 K3 K4 K15 K16 K17 K18 J1 J2 J3 J4 J15 J16 J17 J18 H1 H2 H3 H4 H15 H16 H17 H18 G1 G2 G3 G4 G15 G16 G17 G18 F1 4-150 PG XC4008E XC4010E XC4013E XC4020E 191 PG191 PG191 PG223 PG223 Pin N17 N.C. I/O I/O I/O N18 I/O I/O I/O I/O M1 I/O (A5) I/O (A5) I/O (A5) I/O (A5) M2 I/O (A4) I/O (A4) I/O (A4) I/O (A4) M3 GND GND GND GND I/O I/O I/O I/O M16 GND GND GND GND M17 I/O I/O I/O I/O M18 I/O I/O I/O I/O L1 I/O I/O I/O I/O L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O I/O I/O I/O I/O L16 I/O I/O I/O I/O L17 I/O I/O I/O I/O L18 I/O I/O I/O I/O K1 I/O I/O I/O I/O K2 I/O (A6) I/O (A6) I/O (A6) I/O (A6) K3 I/O (A7) I/O (A7) I/O (A7) I/O (A7) K4 GND GND GND GND K15 GND GND GND GND K16 I/O I/O I/O I/O K17 I/O I/O I/O I/O K18 I/O I/O I/O I/O J1 I/O I/O I/O I/O J2 I/O (A9) I/O (A9) I/O (A9) I/O (A9) J3 I/O (A8) I/O (A8) I/O (A8) I/O (A8) J4 VCC VCC VCC VCC J15 VCC VCC VCC VCC J16 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) J17 I/O I/O I/O I/O J18 I/O I/O I/O I/O H1 I/O I/O I/O I/O H2 I/O I/O I/O I/O H3 I/O I/O I/O I/O I/O I/O I/O I/O H16 I/O I/O I/O I/O H17 I/O I/O I/O I/O H18 I/O I/O I/O I/O G1 I/O (A10) I/O (A10) I/O (A10) I/O (A10) G2 I/O (A11) I/O (A11) I/O (A11) I/O (A11) G3 GND GND GND GND I/O I/O I/O I/O G16 GND GND GND GND G17 I/O I/O I/O I/O G18 I/O I/O I/O I/O F1 I/O I/O I/O I/O XC4025E PG223 I/O I/O I/O (A5) I/O (A4) GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A6) I/O (A7) GND GND I/O I/O I/O I/O I/O (A9) I/O (A8) VCC VCC I/O (INIT) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A10) I/O (A11) GND I/O I/O GND I/O I/O I/O PG 223 Pin F2 F3 F4 F15 F16 F17 F18 E1 E2 E3 E4 E15 E16 E17 E18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 PG XC4008E XC4010E XC4013E XC4020E 191 PG191 PG191 PG223 PG223 Pin F2 N.C. I/O I/O I/O F3 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O I/O I/O I/O F16 I/O I/O I/O I/O F17 N.C. I/O I/O I/O F18 I/O I/O I/O I/O E1 I/O I/O I/O I/O E2 I/O I/O I/O I/O E3 I/O I/O I/O I/O I/O I/O I/O I/O E16 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) E17 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) E18 I/O I/O I/O I/O D1 N.C. I/O I/O I/O D2 I/O (A13) I/O (A13) I/O (A13) I/O (A13) D3 VCC VCC VCC VCC D4 GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O D9 GND GND GND GND D10 VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O D15 GND GND GND GND D16 VCC VCC VCC VCC D17 I/O I/O I/O I/O D18 N.C. I/O I/O I/O C1 I/O I/O I/O I/O C2 I/O (A14) I/O (A14) I/O (A14) I/O (A14) C3 I/O, I/O, I/O, I/O, PGCK1 PGCK1 PGCK1 PGCK1 (A16) (A16) (A16) (A16) C4 I/O (A17) I/O (A17) I/O (A17) I/O (A17) C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 GND GND GND GND C8 I/O I/O I/O I/O C9 I/O I/O I/O I/O C10 I/O I/O I/O I/O C11 I/O I/O I/O I/O C12 GND GND GND GND C13 I/O I/O I/O I/O C14 I/O I/O I/O I/O C15 O (M1) O (M1) O (M1) O (M1) C16 I (M2) I (M2) I (M2) I (M2) XC4025E PG223 I/O I/O (A12) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (HDC) I/O (LDC) I/O I/O I/O (A13) VCC GND I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND VCC I/O I/O I/O I/O (A14) I/O, PGCK1 (A16) I/O (A17) I/O I/O GND I/O I/O I/O I/O GND I/O I/O O (M1) I (M2) June 1, 1996 (Version 1.02) PG PG XC4008E 223 191 PG191 Pin Pin C17 C17 I/O C18 C18 I/O B1 B1 I/O B2 B2 I/O, SGCK1 (A15) B3 B3 I/O B4 B4 I/O, TCK B5 N.C. B5 B6 B6 N.C. B7 B7 I/O, TMS B8 B8 I/O B9 B9 I/O B10 B10 I/O B11 B11 I/O B12 B12 I/O B13 B13 N.C. B14 B14 I/O B15 B15 I/O B16 B16 I/O, SCGK2 B17 B17 I/O, PGCK2 B18 B18 I/O A2 A2 I/O, TDI A3 A3 I/O A4 A4 I/O A5 A5 I/O A6 A6 I/O A7 A7 I/O A8 A8 I/O A9 A9 I/O A10 A10 I/O A11 A11 I/O A12 A12 I/O A13 A13 I/O N.C. A14 A14 A15 A15 I/O A16 A16 I/O A17 A17 I/O A18 A18 I (M0) XC4010E XC4013E XC4020E XC4025E PG191 PG223 PG223 PG223 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, SGCK1 SGCK1 SGCK1 SGCK1 (A15) (A15) (A15) (A15) I/O I/O I/O I/O I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, I/O, I/O, SCGK2 SCGK2 SCGK2 SCGK2 I/O, I/O, I/O, I/O, PGCK2 PGCK2 PGCK2 PGCK2 I/O I/O I/O I/O I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I (M0) I (M0) I (M0) I (M0) Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 2/28/96 June 1, 1996 (Version 1.02) 4-151 XC4000 Series Field Programmable Gate Arrays BG225 Package Pinouts BG225 Pin R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 4-152 XC4010E VCC I/O, PGCK2 I/O I/O I/O I/O I/O VCC I/O N.C. I/O I/O I/O I/O VCC I/O, SCGK2 I (M0) I/O (HDC) I/O (LDC) N.C. I/O N.C. I/O (INIT) I/O N.C. I/O I/O I/O DONE I/O (D7) I/O I/O O (M1) I/O I/O I/O N.C. I/O I/O I/O N.C. I/O I/O, SGCK3 I/O, PGCK3 N.C. I/O I/O I/O I (M2) I/O I/O I/O GND I/O N.C. I/O PROGRAM I/O XC4013E/L VCC I/O, PGCK2 I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC I/O, SCGK2 I (M0) I/O (HDC) I/O (LDC) I/O I/O I/O I/O (INIT) I/O I/O I/O I/O I/O DONE I/O (D7) I/O I/O O (M1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 I/O, PGCK3 I/O I/O I/O I/O I (M2) I/O I/O I/O GND I/O I/O I/O PROGRAM I/O BG225 Pin M14 M15 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 XC4010E N.C. I/O I/O N.C. I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O N.C. I/O I/O I/O GND I/O I/O I/O N.C. I/O I/O I/O (D5) I/O I/O I/O I/O N.C. I/O GND GND GND I/O (D6) I/O I/O (CS0) I/O I/O I/O VCC GND I/O I/O I/O GND GND GND GND GND I/O (RS) I/O (D3) I/O (D4) XC4013E/L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D5) I/O I/O I/O I/O I/O I/O GND GND GND I/O (D6) I/O I/O (CS0) I/O I/O I/O VCC GND I/O I/O I/O GND GND GND GND GND I/O (RS) I/O (D3) I/O (D4) June 1, 1996 (Version 1.02) BG225 Pin H14 H15 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 XC4010E I/O VCC I/O I/O I/O I/O I/O I/O GND GND GND N.C. I/O (D2) I/O I/O I/O I/O N.C. N.C. I/O I/O, TMS I/O I/O N.C. GND N.C. I/O (D0, DIN) I/O N.C. I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O (A8) I/O I/O I/O I/O (D1) I/O N.C. N.C. I/O I/O I/O, TDI I/O, PGCK1 (A16) I/O (A13) I/O I/O VCC I/O (A5) I/O N.C. GND I/O June 1, 1996 (Version 1.02) XC4013E/L I/O VCC I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O, TMS I/O I/O I/O GND I/O I/O (D0, DIN) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A8) I/O I/O I/O I/O (D1) I/O I/O I/O I/O I/O I/O, TDI I/O, PGCK1 (A16) I/O (A13) I/O I/O VCC I/O (A5) I/O I/O GND I/O BG225 Pin D14 D15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 XC4010E XC4013E/L I/O I/O I/O I/O I/O, TCK I/O, TCK I/O I/O I/O, SGCK1 (A15) I/O, SGCK1 (A15) N.C. I/O I/O I/O N.C. I/O I/O I/O I/O (A6) I/O (A6) I/O I/O N.C. I/O I/O I/O I/O I/O CCLK CCLK I/O I/O I/O (RCLK, I/O (RCLK, RDY/BUSY) RDY/BUSY) I/O (A17) I/O (A17) VCC VCC I/O I/O I/O (A12) I/O (A12) I/O I/O I/O (A11) I/O (A11) I/O (A9) I/O (A9) I/O (A7) I/O (A7) I/O I/O N.C. I/O I/O I/O I/O (A3) I/O (A3) I/O, PGCK4 (A1) I/O, PGCK4 (A1) VCC VCC I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT) GND GND I/O (A14) I/O (A14) N.C. I/O I/O I/O I/O I/O I/O (A10) I/O (A10) I/O I/O GND GND I/O I/O I/O (A4) I/O (A4) I/O I/O I/O I/O I/O (CS1, A2) I/O (CS1, A2) I/O (A0, WS) I/O (A0, WS) O, TDO O, TDO 2/28/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-153 XC4000 Series Field Programmable Gate Arrays PQ240, HQ240 Package Pinouts PQ240/ XC4013E XC4020E HQ240 Pin XC4013L P1 GND GND P2 I/O, I/O, PGCK1 PGCK1 (A16) (A16) P3 I/O (A17) I/O (A17) P4 I/O I/O P5 I/O I/O P6 I/O, TDI I/O, TDI P7 I/O, TCK I/O, TCK P8 I/O I/O P9 I/O I/O P10 I/O I/O P11 I/O I/O P12 I/O I/O P13 I/O I/O P14 GND GND P15 I/O I/O P16 I/O I/O P17 I/O, TMS I/O, TMS P18 I/O I/O P19 VCC VCC P20 I/O I/O P21 I/O I/O P22 N.C. N.C. P23 I/O I/O P24 I/O I/O P25 I/O I/O P26 I/O I/O P27 I/O I/O P28 I/O I/O P29 GND GND P30 VCC VCC P31 I/O I/O P32 I/O I/O P33 I/O I/O P34 I/O I/O P35 I/O I/O P36 I/O I/O P37 N.C. N.C. P38 I/O I/O P39 I/O I/O P40 VCC VCC P41 I/O I/O P42 I/O I/O P43 I/O I/O P44 I/O I/O 4-154 XC4025E GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O N.C. I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O N.C. I/O I/O VCC I/O I/O I/O I/O XC4028EX XC4028XL GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O, FCLK1 I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O, FCLK2 PQ240/ XC4013E XC4020E HQ240 Pin XC4013L P45 GND GND P46 I/O I/O P47 I/O I/O P48 I/O I/O P49 I/O I/O P50 I/O I/O P51 I/O I/O P52 I/O I/O P53 I/O I/O P54 I/O I/O P55 I/O I/O P56 I/O I/O P57 I/O, I/O, SGCK2 SGCK2 P58 O (M1) O (M1) P59 GND GND P60 I (M0) I (M0) P61 VCC VCC P62 I (M2) I (M2) P63 I/O, I/O, PGCK2 PGCK2 P64 I/O (HDC) I/O (HDC) P65 I/O I/O P66 I/O I/O P67 I/O I/O P68 I/O (LDC) I/O (LDC) P69 I/O I/O P70 I/O I/O P71 I/O I/O P72 I/O I/O P73 I/O I/O P74 I/O I/O P75 GND GND P76 I/O I/O P77 I/O I/O P78 I/O I/O P79 I/O I/O P80 VCC VCC P81 I/O I/O P82 I/O I/O P83 N.C. N.C. P84 I/O I/O P85 I/O I/O P86 I/O I/O P87 I/O I/O P88 I/O I/O P89 I/O (INIT) I/O (INIT) XC4028EX XC4028XL GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, SGCK2 GCK2 O (M1) O (M1) GND GND I (M0) I (M0) VCC VCC I (M2) I (M2) I/O, I/O, PGCK2 GCK3 I/O (HDC) I/O (HDC) I/O I/O I/O I/O I/O I/O I/O (LDC) I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O N.C. GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) I/O (INIT) XC4025E June 1, 1996 (Version 1.02) PQ240/ XC4013E XC4020E HQ240 Pin XC4013L P90 VCC VCC P91 GND GND P92 I/O I/O P93 I/O I/O P94 I/O I/O P95 I/O I/O P96 I/O I/O P97 I/O I/O P98 N.C. N.C. P99 I/O I/O P100 I/O I/O P101 VCC VCC P102 I/O I/O P103 I/O I/O P104 I/O I/O P105 I/O I/O P106 GND GND P107 I/O I/O P108 I/O I/O P109 I/O I/O P110 I/O I/O P111 I/O I/O P112 I/O I/O P113 I/O I/O P114 I/O I/O P115 I/O I/O P116 I/O I/O P117 I/O I/O P118 I/O, I/O, SGCK3 SGCK3 P119 GND GND P120 DONE DONE P121 VCC VCC P122 PROPROGRAM GRAM P123 I/O (D7) I/O (D7) P124 I/O, I/O, PGCK3 PGCK3 P125 I/O I/O P126 I/O I/O P127 I/O I/O P128 I/O I/O P129 I/O (D6) I/O (D6) P130 I/O I/O P131 I/O I/O P132 I/O I/O P133 I/O I/O June 1, 1996 (Version 1.02) XC4028EX XC4028XL VCC VCC GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. GND I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, I/O, SGCK3 GCK4 GND GND DONE DONE VCC VCC PROPROGRAM GRAM I/O (D7) I/O (D7) I/O, I/O, PGCK3 GCK5 I/O I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O (D6) I/O I/O I/O I/O I/O I/O I/O I/O XC4025E PQ240/ HQ240 Pin P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 XC4013E XC4013L I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) N.C. I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O N.C. I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O XC4020E XC4025E I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) N.C. I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O N.C. I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) N.C. I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O N.C. I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O XC4028EX XC4028XL I/O GND I/O I/O I/O, FCLK3 I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O (D2) I/O VCC I/O I/O, FCLK4 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O 4-155 XC4000 Series Field Programmable Gate Arrays PQ240/ XC4013E XC4020E HQ240 Pin XC4013L P177 I/O I/O (D0, DIN) (D0, DIN) P178 I/O, I/O, SGCK4 SGCK4 (DOUT) (DOUT) P179 CCLK CCLK P180 VCC VCC P181 O, TDO O, TDO P182 GND GND P183 I/O I/O (A0, WS) (A0, WS) P184 I/O, I/O, PGCK4 PGCK4 (A1) (A1) P185 I/O I/O P186 I/O I/O P187 I/O (CS1, I/O (CS1, A2) A2) P188 I/O (A3) I/O (A3) P189 I/O I/O P190 I/O I/O P191 I/O I/O P192 I/O I/O P193 I/O I/O P194 I/O I/O P195 N.C. N.C. P196 GND GND P197 I/O I/O P198 I/O I/O P199 I/O I/O P200 I/O I/O P201 VCC VCC P202 I/O (A4) I/O (A4) P203 I/O (A5) I/O (A5) P204 N.C. N.C. P205 I/O I/O P206 I/O I/O P207 I/O I/O P208 I/O I/O P209 I/O (A6) I/O (A6) P210 I/O (A7) I/O (A7) P211 GND GND P212 VCC VCC P213 I/O (A8) I/O (A8) P214 I/O (A9) I/O (A9) P215 I/O I/O P216 I/O I/O P217 I/O I/O 4-156 XC4025E I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) N.C. I/O I/O I/O I/O I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O I/O I/O XC4028EX XC4028XL I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) GND I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O PQ240/ HQ240 Pin P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 XC4013E XC4013L I/O N.C. I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC XC4020E XC4025E I/O N.C. I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC I/O N.C. I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC XC4028EX XC4028XL I/O GND I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC 3/11/96 Pins labelled GND should be connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices. Pins labelled N.C. are reserved for Ground connections on future revisions of the device. These pins do not physically connect to anything on the current device revision. However, they should be externally connected to Ground if possible. Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. June 1, 1996 (Version 1.02) PG299 Package Pinouts PG299 Pin X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 XC4025E I/O, SGCK4 (DOUT) GND I/O I/O VCC GND I/O I/O I/O VCC GND I/O I/O I/O (CS0) VCC GND I/O I/O VCC I/O, SGCK3 VCC I/O (A0, WS) I/O I/O I/O I/O I/O I/O (D2) I/O I/O (D3) I/O I/O I/O I/O I/O I/O I/O (D6) I/O, PGCK3 I/O (D7) GND I/O (A3) I/O, PGCK4 (A1) CCLK I/O (D0, DIN) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (RS) June 1, 1996 (Version 1.02) XC4028EX/XL I/O, GCK6 (DOUT) GND I/O I/O VCC GND I/O I/O I/O VCC GND I/O I/O I/O (CS0) VCC GND I/O I/O VCC I/O, GCK4 VCC I/O (A0, WS) I/O I/O I/O I/O I/O, FCLK4 I/O (D2) I/O I/O (D3) I/O I/O I/O I/O, FCLK3 I/O I/O I/O (D6) I/O, GCK5 I/O (D7) GND I/O (A3) I/O, GCK7 (A1) CCLK I/O (D0, DIN) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O (RS) PG299 Pin V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 R1 R2 XC4025E I/O (D4) I/O I/O I/O I/O I/O I/O DONE I/O I/O I/O I/O I/O (CS1, A2) O, TDO I/O I/O (D1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROGRAM I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D5) I/O I/O I/O VCC I/O I/O I/O VCC VCC I/O XC4028EX/XL I/O (D4) I/O I/O I/O I/O I/O I/O DONE I/O I/O I/O I/O I/O (CS1, A2) O, TDO I/O I/O (D1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROGRAM I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D5) I/O I/O I/O VCC I/O I/O I/O VCC VCC I/O 4-157 XC4000 Series Field Programmable Gate Arrays PG299 Pin R3 R4 R5 R16 R17 R18 R19 R20 P1 P2 P3 P4 P5 P16 P17 P18 P19 P20 N1 N2 N3 N4 N5 N16 N17 N18 N19 N20 M1 M2 M3 M4 M5 M16 M17 M18 M19 M20 L1 L2 L3 L4 L5 L16 L17 L18 L19 L20 K1 K2 K3 K4 4-158 XC4025E I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A4) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A5) I/O I/O I/O I/O I/O I/O I/O GND I/O (A7) I/O (A6) I/O I/O I/O I/O I/O I/O VCC VCC I/O (A8) I/O (A9) I/O XC4028EX/XL I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A4) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A21) I/O I/O (A5) I/O I/O I/O I/O I/O I/O I/O GND I/O (A7) I/O (A6) I/O (A20) I/O I/O I/O I/O I/O VCC VCC I/O (A8) I/O (A9) I/O (A18) PG299 Pin K5 K16 K17 K18 K19 K20 J1 J2 J3 J4 J5 J16 J17 J18 J19 J20 H1 H2 H3 H4 H5 H16 H17 H18 H19 H20 G1 G2 G3 G4 G5 G16 G17 G18 G19 G20 F1 F2 F3 F4 F5 F16 F17 F18 F19 F20 E1 E2 E3 E4 E5 E6 XC4025E I/O I/O I/O I/O I/O (INIT) GND I/O I/O I/O (A11) I/O I/O I/O I/O I/O I/O I/O I/O (A10) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A12) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O VCC I/O XC4028EX/XL I/O (A19) I/O I/O I/O I/O (INIT) GND I/O I/O I/O (A11) I/O I/O I/O I/O I/O I/O I/O I/O (A10) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A12) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O VCC I/O June 1, 1996 (Version 1.02) PG299 Pin E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 XC4025E I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O (A14) I/O, PGCK1 (A16) I/O, TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I (M2) I/O I/O I/O I/O (A13) I/O I/O, SGCK1 (A15) I/O, TCK I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 I (M0) June 1, 1996 (Version 1.02) XC4028EX/XL I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O (A14) I/O, GCK1 (A16) I/O, TDI I/O I/O I/O I/O I/O I/O I/O I/O, FCLK2 I/O I/O I/O I (M2) I/O I/O I/O I/O (A13) I/O I/O, GCK8 (A15) I/O, TCK I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 I (M0) PG299 Pin C19 C20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 XC4025E I/O (HDC) I/O (LDC) GND I/O (A17) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, PGCK2 VCC VCC I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O GND O (M1) XC4028EX/XL I/O (HDC) I/O (LDC) GND I/O (A17) I/O I/O I/O I/O, FCLK1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK3 VCC VCC I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O GND O (M1) 3/18/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-159 XC4000 Series Field Programmable Gate Arrays HQ304 Package Pinouts HQ304 XC4025E Pin P1 VCC P2 I/O, SGCK1 (A15) P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 4-160 I/O (A14) I/O I/O I/O I/O I/O I/O I/O (A13) N.C. I/O (A12) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O (A11) I/O (A10) I/O I/O I/O I/O I/O (A9) I/O (A8) VCC GND I/O (A7) I/O (A6) I/O I/O I/O I/O I/O (A5) I/O (A4) I/O I/O I/O XC4028EX XC4028XL VCC I/O, GCK8 (A15) I/O (A14) I/O I/O I/O I/O I/O I/O I/O (A13) N.C. I/O (A12) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O (A11) I/O (A10) I/O I/O I/O (A18) I/O (A19) I/O (A9) I/O (A8) VCC GND I/O (A7) I/O (A6) I/O (A20) I/O (A21) I/O I/O I/O (A5) I/O (A4) I/O I/O I/O XC4036EX XC4036XL VCC I/O, GCK8 (A15) I/O (A14) I/O I/O I/O I/O I/O I/O I/O (A13) N.C. I/O (A12) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O (A11) I/O (A10) I/O I/O I/O (A18) I/O (A19) I/O (A9) I/O (A8) VCC GND I/O (A7) I/O (A6) I/O (A20) I/O (A21) I/O I/O I/O (A5) I/O (A4) I/O I/O I/O HQ304 XC4025E Pin P51 I/O P52 VCC P53 N.C. P54 I/O P55 I/O P56 I/O P57 I/O P58 GND P59 I/O P60 I/O P61 I/O P62 I/O P63 I/O P64 I/O P65 I/O P66 I/O P67 I/O P68 I/O P69 I/O (A3) P70 I/O (CS1, A2) P71 I/O P72 I/O P73 I/O, PGCK4 (A1) P74 I/O (A0, WS) P75 GND P76 O, TDO P77 VCC P78 CCLK P79 I/O, SGCK4 (DOUT) P80 I/O (D0, DIN) P81 I/O P82 I/O P83 I/O P84 I/O P85 I/O (RCLK, RDY/BUSY) P86 I/O (D1) P87 I/O P88 I/O P89 I/O P90 I/O P91 I/O P92 I/O P93 I/O P94 I/O P95 GND P96 I/O P97 I/O P98 I/O P99 I/O P100 N.C. P101 VCC XC4028EX XC4028XL I/O VCC N.C. I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A3) I/O (CS1, A2) I/O I/O I/O, GCK7 (A1) I/O (A0, WS) GND O, TDO VCC CCLK I/O, GCK6 (DOUT) I/O (D0, DIN) I/O I/O I/O I/O I/O (RCLK, RDY/BUSY) I/O (D1) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, FCLK4 I/O N.C. VCC XC4036EX XC4036XL I/O VCC N.C. I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A3) I/O (CS1, A2) I/O I/O I/O, GCK7 (A1) I/O (A0, WS) GND O, TDO VCC CCLK I/O, GCK6 (DOUT) I/O (D0, DIN) I/O I/O I/O I/O I/O (RCLK, RDY/BUSY) I/O (D1) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, FCLK4 I/O N.C. VCC June 1, 1996 (Version 1.02) HQ304 Pin P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 XC4025E I/O I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O (RS) I/O (D3) GND VCC I/O I/O (D4) I/O I/O I/O I/O I/O I/O I/O I/O I/O (CS0) I/O (D5) N.C. VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O, PGCK3 I/O (D7) PROGRAM VCC DONE GND June 1, 1996 (Version 1.02) XC4028EX XC4028XL I/O I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O (RS) I/O (D3) GND VCC I/O I/O (D4) I/O I/O I/O I/O I/O I/O I/O I/O I/O (CS0) I/O (D5) N.C. VCC I/O I/O, FCLK3 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O, GCK5 I/O (D7) PROGRAM VCC DONE GND XC4036EX XC4036XL I/O I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O (RS) I/O (D3) GND VCC I/O I/O (D4) I/O I/O I/O I/O I/O I/O I/O I/O I/O (CS0) I/O (D5) N.C. VCC I/O I/O, FCLK3 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O, GCK5 I/O (D7) PROGRAM VCC DONE GND HQ304 Pin P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207 XC4025E I/O, SGCK3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (INIT) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC N.C. I/O I/O XC4028EX XC4028XL I/O, GCK4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (INIT) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC N.C. I/O I/O XC4036EX XC4036XL I/O, GCK4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O N.C. VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (INIT) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC N.C. I/O I/O 4-161 XC4000 Series Field Programmable Gate Arrays HQ304 Pin P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P241 P242 P243 P244 P245 P246 P247 P248 P249 P250 P251 P252 P253 P254 P255 P256 P257 P258 P259 P260 4-162 XC4025E I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (LDC) I/O I/O I/O I/O (HDC) I/O, PGCK2 I (M2) VCC I (M0) GND O (M1) I/O, SGCK2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC N.C. I/O I/O I/O I/O I/O I/O XC4028EX XC4028XL I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (LDC) I/O I/O I/O I/O (HDC) I/O, GCK3 I (M2) VCC I (M0) GND O (M1) I/O, GCK2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O, FCLK2 I/O I/O I/O VCC N.C. I/O I/O I/O I/O I/O I/O XC4036EX XC4036XL I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (LDC) I/O I/O I/O I/O (HDC) I/O, GCK3 I (M2) VCC I (M0) GND O (M1) I/O, GCK2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O, FCLK2 I/O I/O I/O VCC N.C. I/O I/O I/O I/O I/O I/O HQ304 Pin P261 P262 P263 P264 P265 P266 P267 P268 P269 P270 P271 P272 P273 P274 P275 P276 P277 P278 P279 P280 P281 P282 P283 P284 P285 P286 P287 P288 P289 P290 P291 P292 P293 P294 P295 P296 P297 P298 P299 P300 P301 P302 P303 P304 XC4025E I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. VCC I/O I/O, TMS I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TCK I/O, TDI I/O I/O I/O (A17) I/O, PGCK1 (A16) GND XC4028EX XC4028XL I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. VCC I/O I/O, TMS I/O I/O, FCLK1 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TCK I/O, TDI I/O I/O I/O (A17) I/O, GCK1 (A16) GND XC4036EX XC4036XL I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. VCC I/O I/O, TMS I/O I/O, FCLK1 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, TCK I/O, TDI I/O I/O I/O (A17) I/O, GCK1 (A16) GND 3/20/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. June 1, 1996 (Version 1.02) BG352 Package Pinouts BG352 Pin AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AD1 AD2 AD3 AD4 AD5 AD6 June 1, 1996 (Version 1.02) XC4028EX/XL GND GND I/O I/O GND I/O I/O GND I/O VCC I/O I/O GND I/O (INIT) I/O I/O VCC I/O GND I/O I/O GND I/O I/O GND GND GND VCC I/O N.C. I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (LDC) I/O, GCK3 VCC GND I/O I/O (D7) DONE I/O I/O I/O BG352 Pin AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 AA1 AA2 AA3 AA4 AA23 AA24 XC4028EX/XL I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O N.C. I/O I/O (HDC) I (M0) I/O N.C. I/O N.C. I/O, GCK5 PROGRAM I/O, GCK4 N.C. I/O VCC I/O I/O N.C. I/O I/O VCC I/O N.C. I/O I/O I/O VCC N.C. I/O I (M2) I/O, GCK2 N.C. I/O GND I/O N.C. I/O O (M1) I/O I/O GND I/O I/O I/O I/O I/O I/O 4-163 XC4000 Series Field Programmable Gate Arrays BG352 Pin AA25 AA26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 W1 W2 W3 W4 W23 W24 W25 W26 V1 V2 V3 V4 V23 V24 V25 V26 U1 U2 U3 U4 U23 U24 U25 U26 T1 T2 T3 T4 T23 T24 T25 T26 R1 R2 R3 R4 R23 R24 R25 R26 P1 P2 P3 P4 P23 P24 P25 P26 N1 N2 4-164 XC4028EX/XL I/O I/O I/O I/O I/O (D6) VCC I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O GND I/O (CS0) I/O (D5) I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O, FCLK3 I/O, FCLK2 I/O N.C. VCC I/O I/O N.C. N.C. I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC I/O I/O I/O GND GND I/O (D3) BG352 Pin N3 N4 N23 N24 N25 N26 M1 M2 M3 M4 M23 M24 M25 M26 L1 L2 L3 L4 L23 L24 L25 L26 K1 K2 K3 K4 K23 K24 K25 K26 J1 J2 J3 J4 J23 J24 J25 J26 H1 H2 H3 H4 H23 H24 H25 H26 G1 G2 G3 G4 G23 G24 G25 G26 F1 F2 F3 F4 F23 F24 XC4028EX/XL I/O I/O (RS) VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O VCC N.C. I/O I/O I/O I/O I/O VCC I/O (D2) I/O I/O, FCLK4 I/O I/O, FCLK1 I/O I/O N.C. GND I/O I/O VCC I/O I/O I/O, TMS GND I/O I/O I/O I/O (RCLK, RDY/BUSY) VCC I/O I/O I/O I/O I/O I/O (D1) I/O N.C. I/O June 1, 1996 (Version 1.02) BG352 Pin F25 F26 E1 E2 E3 E4 E23 E24 E25 E26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 June 1, 1996 (Version 1.02) XC4028EX/XL I/O I/O GND I/O I/O I/O, GCK6 (DOUT) I/O I/O, TCK I/O GND N.C. I/O I/O (D0, DIN) O (TDO) I/O I/O (CS1, A2) VCC I/O I/O I/O I/O I/O (A4) VCC I/O (A8) I/O N.C. I/O I/O VCC I/O I/O I/O (A14) I/O, GCK1 (A16) I/O N.C. I/O N.C. I/O CCLK I/O, GCK7 (A1) N.C. I/O (A3) I/O N.C. I/O I/O N.C. I/O (A5) I/O (A21) I/O (A9) I/O I/O I/O I/O I/O I/O I/O (A13) I/O I/O I/O, GCK8 (A15) BG352 Pin C25 C26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 XC4028EX/XL I/O (A17) I/O, TDI GND VCC I/O (A0, WS) N.C. I/O I/O I/O I/O I/O N.C. I/O I/O I/O (A20) I/O (A7) I/O (A18) I/O (A11) I/O I/O I/O I/O I/O I/O (A12) N.C. I/O VCC GND GND GND I/O I/O GND I/O I/O GND I/O VCC I/O I/O I/O (A6) GND I/O (A19) I/O (A10) VCC N.C. GND I/O I/O GND I/O N.C. GND GND 2/28/96 Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-165 XC4000 Series Field Programmable Gate Arrays PG411 Package Pinouts PG411 Pin AW1 AW3 AW5 AW7 AW9 AW11 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 AW29 AW31 AW33 AW35 AW37 AW39 AV2 AV4 AV6 AV8 AV10 AV12 AV14 AV16 AV18 AV20 AV22 AV24 AV26 AV28 AV30 AV32 AV34 AV36 AV38 AU1 AU3 AU5 AU7 AU9 AU11 AU13 AU15 AU17 AU19 AU21 AU23 4-166 XC4036EX/XL I/O GND I/O I/O (RCLK, RDY/BUSY) VCC GND I/O N.C. I/O VCC GND N.C. N.C. I/O VCC GND I/O N.C. VCC I/O I/O, GCK7 (A1) I/O I/O N.C. I/O I/O I/O I/O I/O I/O (RS) I/O I/O N.C. I/O I/O I/O (D6) N.C. I/O I/O VCC I/O, GCK6 (DOUT) N.C. I/O (D1) N.C. I/O N.C. N.C. N.C. I/O (D3) I/O I/O XC4044EX/XL I/O GND I/O I/O (RCLK, RDY/BUSY) VCC GND I/O I/O I/O VCC GND I/O I/O I/O VCC GND I/O N.C. VCC I/O I/O, GCK7 (A1) I/O I/O I/O I/O I/O I/O I/O I/O I/O (RS) I/O I/O N.C. I/O I/O I/O (D6) N.C. I/O I/O VCC I/O, GCK6 (DOUT) N.C. I/O (D1) I/O I/O N.C. N.C. I/O I/O (D3) I/O I/O PG411 Pin AU25 AU27 AU29 AU31 AU33 AU35 AU37 AU39 AT2 AT4 AT6 AT8 AT10 AT12 AT14 AT16 AT18 AT20 AT22 AT24 AT26 AT28 AT30 AT32 AT34 AT36 AT38 AR1 AR3 AR5 AR7 AR9 AR11 AR13 AR15 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31 AR33 AR35 AR37 AR39 AP2 AP4 AP6 AP8 AP10 AP12 XC4036EX/XL N.C. I/O (CS0) I/O I/O I/O I/O N.C. GND N.C. I/O (A0, WS) GND I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O, FCLK3 N.C. I/O VCC I/O, GCK4 I/O I/O I/O CCLK I/O I/O I/O I/O, FCLK4 I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O DONE N.C. I/O I/O VCC I/O (D0, DIN) N.C. I/O I/O XC4044EX/XL N.C. I/O (CS0) I/O I/O I/O I/O N.C. GND N.C. I/O (A0, WS) GND I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O, FCLK3 I/O I/O VCC I/O, GCK4 I/O I/O I/O CCLK I/O I/O I/O I/O, FCLK4 I/O (D2) I/O I/O I/O I/O I/O I/O I/O I/O I/O DONE N.C. I/O I/O VCC I/O (D0, DIN) N.C. I/O I/O June 1, 1996 (Version 1.02) PG411 Pin AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP30 AP32 AP34 AP36 AP38 AN1 AN3 AN5 AN7 AN9 AN31 AN33 AN35 AN37 AN39 AM2 AM4 AM6 AM8 AM32 AM34 AM36 AM38 AL1 AL3 AL5 AL7 AL33 AL35 AL37 AL39 AK2 AK4 AK6 AK34 AK36 AK38 AJ1 AJ3 AJ5 AJ35 AJ37 AJ39 AH2 AH4 XC4036EX/XL I/O I/O I/O I/O (D4) I/O I/O (D5) I/O I/O N.C. I/O I/O, GCK5 GND N.C. N.C. I/O (A3) N.C. O, TDO I/O I/O PROGRAM I/O I/O I/O I/O I/O I/O I/O I/O (D7) I/O I/O I/O GND I/O I/O I/O I/O N.C. I/O VCC N.C. I/O I/O (CS1, A2) I/O I/O N.C. VCC I/O N.C. I/O I/O GND I/O I/O June 1, 1996 (Version 1.02) XC4044EX/XL I/O I/O I/O I/O (D4) I/O I/O (D5) I/O I/O I/O I/O I/O, GCK5 GND I/O I/O I/O (A3) N.C. O, TDO I/O I/O PROGRAM I/O I/O I/O I/O I/O I/O I/O I/O (D7) I/O I/O I/O GND I/O I/O I/O I/O N.C. I/O VCC I/O I/O I/O (CS1, A2) I/O I/O I/O VCC I/O N.C. I/O I/O GND I/O I/O PG411 Pin AH6 AH34 AH36 AH38 AG1 AG3 AG5 AG35 AG37 AG39 AF2 AF4 AF6 AF34 AF36 AF38 AE1 AE3 AE5 AE35 AE37 AE39 AD2 AD4 AD6 AD34 AD36 AD38 AC1 AC3 AC5 AC35 AC37 AC39 AB2 AB4 AB6 AB34 AB36 AB38 AA1 AA3 AA5 AA35 AA37 AA39 Y2 Y4 Y6 Y34 Y36 Y38 W1 XC4036EX/XL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. GND I/O I/O GND N.C. I/O I/O I/O I/O I/O I/O I/O (A4) I/O (A21) I/O I/O I/O I/O I/O N.C. I/O I/O I/O N.C. N.C. I/O (A5) I/O I/O I/O I/O GND I/O (A6) I/O (A20) I/O N.C. VCC I/O (A9) GND I/O (A7) I/O GND N.C. VCC XC4044EX/XL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. GND I/O I/O GND N.C. I/O I/O I/O I/O I/O I/O I/O (A4) I/O (A21) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A5) I/O I/O I/O I/O GND I/O (A6) I/O (A20) I/O I/O VCC I/O (A9) GND I/O (A7) I/O GND I/O VCC 4-167 XC4000 Series Field Programmable Gate Arrays PG411 Pin W3 W5 W35 W37 W39 V2 V4 V6 V34 V36 V38 U1 U3 U5 U35 U37 U39 T2 T4 T6 T34 T36 T38 R1 R3 R5 R35 R37 R39 P2 P4 P6 P34 P36 P38 N1 N3 N5 N35 N37 N39 M2 M4 M6 M34 M36 M38 L1 L3 L5 L35 L37 L39 4-168 XC4036EX/XL I/O (A8) N.C. N.C. I/O (INIT) GND N.C. I/O (A19) I/O I/O I/O I/O I/O I/O (A10) I/O I/O I/O I/O I/O (A18) I/O I/O I/O I/O I/O I/O (A11) N.C. I/O I/O I/O I/O I/O GND I/O I/O GND N.C. I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O N.C. N.C. I/O VCC XC4044EX/XL I/O (A8) I/O I/O I/O (INIT) GND I/O I/O (A19) I/O I/O I/O I/O I/O I/O (A10) I/O I/O I/O I/O I/O (A18) I/O I/O I/O I/O I/O I/O (A11) N.C. I/O I/O I/O I/O I/O GND I/O I/O GND N.C. I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O N.C. I/O VCC PG411 Pin K2 K4 K6 K34 K36 K38 J1 J3 J5 J7 J33 J35 J37 J39 H2 H4 H6 H8 H32 H34 H36 H38 G1 G3 G5 G7 G9 G31 G33 G35 G37 G39 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 F36 F38 E1 E3 XC4036EX/XL I/O I/O I/O I/O N.C. N.C. VCC I/O N.C. I/O I/O I/O I/O GND I/O I/O (A12) I/O I/O, GCK1 (A16) I/O N.C. I/O I/O I/O I/O (A13) N.C. I/O, GCK8 (A15) I/O, TCK I/O I (M2) I/O (LDC) I/O I/O N.C. GND I/O (A17) I/O I/O I/O I/O I/O N.C. I/O N.C. I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O XC4044EX/XL I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O (A12) I/O I/O, GCK1 (A16) I/O N.C. I/O I/O I/O I/O (A13) N.C. I/O, GCK8 (A15) I/O, TCK I/O I (M2) I/O (LDC) I/O I/O N.C. GND i/O (A17) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O June 1, 1996 (Version 1.02) PG411 Pin E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 E39 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 D38 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 XC4036EX/XL I/O (A14) N.C. I/O I/O, TMS I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I (M0) N.C. I/O I/O I/O VCC N.C. I/O N.C. GND I/O I/O GND I/O I/O GND I/O N.C. N.C. GND I/O, GCK3 I/O GND I/O I/O N.C. I/O I/O, FCLK1 I/O N.C. I/O I/O I/O N.C. N.C. I/O I/O, FCLK2 I/O June 1, 1996 (Version 1.02) XC4044EX/XL I/O (A14) N.C. I/O I/O, TMS I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I (M0) N.C. I/O I/O I/O VCC I/O I/O N.C. GND I/O I/O GND I/O I/O GND I/O I/O I/O GND I/O, GCK3 I/O GND I/O I/O I/O I/O I/O, FCLK1 I/O I/O I/O I/O I/O I/O N.C. I/O I/O, FCLK2 I/O PG411 Pin C33 C35 C37 C39 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 B38 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 XC4036EX/XL N.C. I/O I/O (HDC) VCC I/O, TDI I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O, GCK2 I/O VCC I/O I/O GND VCC N.C. I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O GND O (M1) XC4044EX/XL N.C. I/O I/O (HDC) VCC I/O, TDI I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O, GCK2 I/O VCC I/O I/O GND VCC N.C. I/O I/O GND VCC I/O I/O I/O GND VCC I/O I/O GND O (M1) 3/26/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-169 XC4000 Series Field Programmable Gate Arrays BG432 Package Pinouts BG432 Pin AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 4-170 XC4036EX XC4036XL VCC GND GND I/O I/O I/O GND I/O GND I/O VCC I/O I/O GND N.C. I/O N.C. GND I/O I/O VCC I/O GND I/O GND I/O I/O I/O GND GND VCC GND GND I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/0 I/O I/O (INIT) N.C. I/O I/O I/O I/O I/O I/O XC4044EX XC4044XL VCC GND GND I/O I/O I/O GND I/O GND I/O VCC I/O I/O GND I/O I/O I/O GND I/O I/O VCC I/O GND I/O GND I/O I/O I/O GND GND VCC GND GND I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O (INIT) I/O I/O I/O I/O I/O I/O I/O BG432 Pin XC4052XL VCC GND GND I/O I/O I/O GND I/O GND I/O VCC I/O I/O GND I/O I/O I/O GND I/O I/O VCC I/O GND I/O GND I/O I/O I/O GND GND VCC GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) I/O I/O I/O I/O I/O I/O I/O AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 XC4036EX XC4036XL N.C. I/O I/O N.C. I/O I/O, GCK3 GND GND GND I/O (D7) VCC I/O, GCK4 N.C. I/O I/O N.C. I/O I/O I/O N.C. I/O I/O N.C. I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O N.C. I/O I (M2) VCC I/O, GCK2 GND I/O I/O PROGRAM DONE I/O N.C. I/O I/O N.C. I/O VCC I/O I/O I/O I/O GND I/O XC4044EX XC4044XL I/O I/O I/O N.C. I/O I/O, GCK3 GND GND GND I/O (D7) VCC I/O, GCK4 N.C. I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O N.C. I/O I (M2) VCC I/O, GCK2 GND I/O I/O PROGRAM DONE I/O N.C. I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O XC4052XL I/O I/O I/O I/O I/O I/O, GCK3 GND GND GND I/O (D7) VCC I/O, GCK4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I (M2) VCC I/O, GCK2 GND I/O I/O PROGRAM DONE I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O June 1, 1996 (Version 1.02) BG432 Pin AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AG1 AG2 AG3 AG4 AG28 AG29 AG30 AG31 AF1 AF2 AF3 AF4 AF28 AF29 AF30 AF31 AE1 AE2 AE3 AE4 AE28 AE29 AE30 AE31 AD1 AD2 AD3 AD4 AD28 AD29 AD30 AD31 AC1 AC2 AC3 AC4 AC28 AC29 AC30 AC31 AB1 AB2 XC4036EX XC4036XL I/O N.C. I/O VCC I/O N.C. I/O I/O I/O (LDC) I/O (HDC) I (M0) O (M1) I/O I/O N.C. I/O I/O I/O, GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O N.C. N.C. I/O GND I/O I/O N.C. I/O I/O I/O GND I/O N.C. I/O I/O I/O I/O N.C. N.C. GND I/O I/O N.C. I/O I/O I/O GND I/O, FCLK3 I/O June 1, 1996 (Version 1.02) XC4044EX XC4044XL I/O N.C. I/O VCC I/O I/O I/O I/O I/O (LDC) I/O (HDC) I (M0) O (M1) I/O I/O N.C. I/O I/O I/O, GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O N.C. N.C. I/O GND I/O I/O N.C. I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O, FCLK3 I/O XC4052XL BG432 Pin I/O I/O I/O VCC I/O I/O I/O I/O I/O (LDC) I/O (HDC) I (M0) O (M1) I/O I/O I/O I/O I/O I/O, GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O, FCLK3 I/O AB3 AB4 AB28 AB29 AB30 AB31 AA1 AA2 AA3 AA4 AA28 AA29 AA30 AA31 Y1 Y2 Y3 Y4 Y28 Y29 Y30 Y31 W1 W2 W3 W4 W28 W29 W30 W31 V1 V2 V3 V4 V28 V29 V30 V31 U1 U2 U3 U4 U28 U29 U30 U31 T1 T2 T3 T4 T28 T29 T30 T31 R1 R2 XC4036EX XC4036XL I/O I/O I/O I/O, FCLK2 I/O I/O VCC I/O (D5) I/O VCC VCC I/O I/O VCC N.C. I/O (CS0) I/O I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O N.C. I/O I/O N.C. GND N.C. I/O I/O N.C. I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O I/O (D3) GND GND I/O I/O I/O I/O (RS) I/O XC4044EX XC4044XL I/O I/O I/O I/O, FCLK2 I/O I/O VCC I/O (D5) I/O VCC VCC I/O I/O VCC N.C. I/O (CS0) I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O N.C. I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O I/O (D3) GND GND I/O I/O I/O I/O (RS) I/O XC4052XL I/O I/O I/O I/O, FCLK2 I/O I/O VCC I/O (D5) I/O VCC VCC I/O I/O VCC I/O I/O (CS0) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O I/O (D3) GND GND I/O I/O I/O I/O (RS) I/O 4-171 XC4000 Series Field Programmable Gate Arrays BG432 Pin R3 R4 R28 R29 R30 R31 P1 P2 P3 P4 P28 P29 P30 P31 N1 N2 N3 N4 N28 N29 N30 N31 M1 M2 M3 M4 M28 M29 M30 M31 L1 L2 L3 L4 L28 L29 L30 L31 K1 K2 K3 K4 K28 K29 K30 K31 J1 J2 J3 J4 J28 J29 J30 J31 H1 H2 4-172 XC4036EX XC4036XL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND N.C. N.C. I/O I/O I/O N.C. N.C. I/O I/O I/O N.C. N.C. N.C. I/O N.C. I/O VCC I/O (D2) I/O VCC VCC I/O I/O VCC I/O I/O, FCLK4 I/O I/O I/O, FCLK1 I/O I/O, TMS I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O XC4044EX XC4044XL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. N.C. I/O N.C. I/O VCC I/O (D2) I/O VCC VCC I/O I/O VCC I/O I/O, FCLK4 I/O I/O I/O, FCLK1 I/O I/O, TMS I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O XC4052XL BG432 Pin I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O (D2) I/O VCC VCC I/O I/O VCC I/O I/O, FCLK4 I/O I/O I/O, FCLK1 I/O I/O, TMS I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O H3 H4 H28 H29 H30 H31 G1 G2 G3 G4 G28 G29 G30 G31 F1 F2 F3 F4 F28 F29 F30 F31 E1 E2 E3 E4 E28 E29 E30 E31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 XC4036EX XC4036XL I/O I/O I/O I/O I/O I/O GND I/O N.C. I/O (D1) I/O I/O I/O GND N.C. I/O (RCLK, RDY/BUSY) I/O N.C. N.C. N.C. N.C. N.C. I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK6 (DOUT) CCLK I/O, GCK7 (A1) N.C. I/O (A3) I/O I/O I/O VCC I/O N.C. I/O I/O GND I/O (A8) I/O (A18) I/O N.C. VCC I/O N.C. I/O (A12) XC4044EX XC4044XL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D1) I/O I/O I/O GND I/O I/O (RCLK, RDY/BUSY) I/O N.C. N.C. N.C. I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK6 (DOUT) CCLK I/O, GCK7 (A1) N.C. I/O (A3) I/O I/O I/O VCC I/O N.C. I/O I/O GND I/O (A8) I/O (A18) I/O N.C. VCC I/O I/O I/O (A12) XC4052XL I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D1) I/O I/O I/O GND I/O I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK6 (DOUT) CCLK I/O, GCK7 (A1) I/O I/O (A3) I/O I/O I/O VCC I/O I/O I/O I/O GND I/O (A8) I/O (A18) I/O I/O VCC I/O I/O I/O (A12) June 1, 1996 (Version 1.02) BG432 Pin D25 D26 D27 D28 D29 D30 D31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 XC4036EX XC4044EX XC4052XL XC4036XL XC4044XL I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, TDI I/O, TDI I/O, TDI I/O, TCK I/O, TCK I/O, TCK GND GND GND I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN) VCC VCC VCC O, TDO O, TDO O, TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A4) I/O (A4) I/O (A4) I/O (A21) I/O (A21) I/O (A21) N.C. I/O I/O N.C. I/O I/O I/O (A19) I/O (A19) I/O (A19) I/O (A11) I/O (A11) I/O (A11) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O (A14) I/O (A14) VCC VCC VCC I/O (A17) I/O (A17) I/O (A17) GND GND GND GND GND GND GND GND GND I/O (A0, WS) I/O (A0, WS) I/O (A0, WS) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N.C. N.C. I/O I/O I/O I/O I/O I/O I/O I/O (A20) I/O (A20) I/O (A20) I/O (A6) I/O (A6) I/O (A6) N.C. I/O I/O I/O I/O I/O June 1, 1996 (Version 1.02) BG432 Pin B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 XC4036EX XC4036XL I/O (A10) I/O N.C. I/O I/O I/O N.C. I/O (A13) I/O I/O I/O GND GND VCC GND GND N.C. I/O (CS1, A2) I/O GND N.C. GND I/O VCC I/O I/O (A5) GND N.C. I/O (A7) I/O (A9) GND I/O I/O VCC I/O GND I/O GND I/O I/O N.C. GND GND VCC XC4044EX XC4044XL I/O (A10) I/O N.C. I/O I/O I/O I/O I/O (A13) I/O I/O I/O GND GND VCC GND GND N.C. I/O (CS1, A2) I/O GND I/O GND I/O VCC I/O I/O (A5) GND I/O I/O (A7) I/O (A9) GND I/O I/O VCC I/O GND I/O GND I/O I/O N.C. GND GND VCC XC4052XL I/O (A10) I/O I/O I/O I/O I/O I/O I/O (A13) I/O I/O I/O GND GND VCC GND GND I/O I/O (CS1, A2) I/O GND I/O GND I/O VCC I/O I/O (A5) GND I/O I/O (A7) I/O (A9) GND I/O I/O VCC I/O GND I/O GND I/O I/O I/O GND GND VCC 3/26/96 Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. 4-173 XC4000 Series Field Programmable Gate Arrays Product Availability Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the specifications. Table 25: Component Availability Chart for XC4000E FPGAs XC 4003E XC 4005E XC 4006E XC 4008E XC 4010E XC 4013E XC 4020E XC 4025E Speed Grade -4 -3 -2 -4 -3 -2 -4 -3 -2 -4 -3 -2 -4 -3 -2 -4 PC PQ VQ PG TQ PG 84 100 100 120 144 156 CI CI CI CI C C C C C C C C CI CI CI CI MB C C C C C C C C CI CI CI C C C C C C CI C C CI C C -3 -2 -4 -3 -2 -4 -3 -2 PQ CB PG CB PQ HQ PG BG CB PQ HQ PG HQ 160 164 191 196 208 208 223 225 228 240 240 299 304 CI MB CI C C CI C C CI C C CI C C CI C C CI C C CI CI CI C C CI C C CI C C CI MB CI C C CI C C CI C C C I MB MB C C C C CI MB C C C C CI CI C C C C CI C C C C C C MB CI C C CI C C CI C C CI CI MB C C C C C = Commercial, TJ = 0 to +85 C I = Industrial, TJ = -40 to +100 C M = Mil Temp, TC = -55 to +125 C B = MIL-STD-883C Class B, TC = -55 to +125 C Shaded device/package combinations are not supported. 4-174 June 1, 1996 (Version 1.02) Table 26: Component Availability Chart for XC4000EX FPGAs XC4028EX Speed Grade -4 -3 XC4036EX -4 -3 XC4044EX -4 -3 HQ208 HQ240 PG299 HQ304 BG352 CI C CI C CI C CI C CI C CI C PG411 BG432 CI C CI C CI C CI C C = Commercial, TJ = 0 to +85 C I = Industrial, TJ = -40 to +100 C M = Mil Temp, TC = -55 to +125 C B = MIL-STD-883C Class B, TC = -55 to +125 C Shaded device/package combinations are not supported. Table 27: Component Availability Chart for XC4000L and XC4000XL FPGAs Speed Grade -6 XC4005L -5 -4 -6 XC4010L -5 -4 -6 XC4013L -5 -4 PC 84 C C TQ 176 PQ 208 C C C C C C C C HQ 208 C C BG 225 PQ 240 C C C C C HQ 240 PG 299 HQ 304 BG 352 C C C C PG 411 BG 432 C C C C C C PG 475 XC4028XL C XC4036XL XC4044XL XC4052XL C XC4062XL C = Commercial, TJ = 0 to +85 C I = Industrial, TJ = -40 to +100 C M = Mil Temp, TC = -55 to +125 C B = MIL-STD-883C Class B, TC = -55 to +125 C Shaded device/package combinations are not supported. Speed grades for the XC4000XL have not yet been determined. June 1, 1996 (Version 1.02) 4-175 XC4000 Series Field Programmable Gate Arrays User I/O Per Package Maximum available user I/O for each device/package combination is shown in Table 28 - Table 30. Pinout tables for XC4000-Series devices follow. Pinout data is offered in two forms, as device-specific and package-specific tables. Device-specific tables include all packages for each XC4000-Series device. They follow the pad locations around the die, and include boundary scan register locations. Package-specific tables include all XC4000-Series devices available in a given package. These tables are especially useful in determining which pads should be avoided, in case of a future transition to a different device in the same package. All pinouts defined at the time of publication are included in these tables. Additional information may be available. Call your local sales office or see the Xilinx WEBLINX at http://www.xilinx.com for the latest information. Table 28: Maximum User I/O for XC4000E Device/Package Combinations No. of Package Pins (Code) Maximum User I/O 84 PLCC (PC) 100 PQFP (PQ) VQFP (VQ) 120 PGA (PG) 144 TQFP (TQ) 156 PGA (PG) 160 PQFP (PQ) 164 CBFP (CB) 191 PGA (PG) 196 CBFP (CB) 208 PQFP (PQ) HQFP (HQ) 223 PGA (PG) 225 BGA (BG) 228 CBFP (CB) 240 PQFP (PQ) HQFP (HQ) 299 PGA (PG) 304 HQFP (HQ) Note: 4-176 XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 80 61 77 77 80 112 61 77 128 61 144 61 160 61 192 224 256 112 112 112 112 113 125 128 129 129 129 144 160 160 160 160 160 192 192 112 128 144 160 160 160 192 192 192 192 192 192 193 193 256 256 This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) June 1, 1996 (Version 1.02) Table 29: Maximum User I/O for XC4000EX Device/Package Combinations No. of Pins Package (Code) Maximum User I/O 208 HQFP (HQ) 240 HQFP (HQ) 299 PGA (PG) 304 HQFP (HQ) 352 BGA (BG) 411 PGA (PG) 432 BGA (BG) Note: XC4028EX 256 160 193 256 256 256 XC4036EX 288 XC4044EX 320 256 288 288 320 320 This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) Table 30: Maximum User I/O for XC4000L and XC4000XL Device/Package Combinations No. of Package XC4005L XC4010L XC4013L XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL Pins (Code) Maximum User I/O 112 160 192 256 288 320 352 384 84 PLCC (PC) 61 61 176 TQFP (TQ) 153 208 PQFP (PQ) 112 160 160 208 HQFP (HQ) 160 225 BGA (BG) 192 240 PQFP (PQ) 192 240 HQFP (HQ) 193 299 PGA (PG) 256 304 HQFP (HQ) 256 256 352 BGA (BG) 256 411 PGA (PG) 288 320 352 432 BGA (BG) 288 320 352 475 PGA (PG) 384 Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) June 1, 1996 (Version 1.02) 4-177 XC4000 Series Field Programmable Gate Arrays Ordering Information Example: XC4013E-3HQ240C Device Type Temperature Range C = Commercial (TJ = 0 to +85C) I = Industrial (TJ = -40 to +100C) M = Military (TC = -55 to+125C) Speed Grade -6 -5 -4 -3 -2 Number of Pins Package Type PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack VQ = Very Thin Quad Flat Pack TQ = Thin Quad Flat Pack BG = Ball Grid Array PG = Ceramic Pin Grid Array HQ = High Heat Dissipation Quad Flat Pack MQ = Metal Quad Flat Pack CB = Top Brazed Ceramic Quad Flat Pack X6750 4-178 June 1, 1996 (Version 1.02) XC5200 Series Table of Contents XC5200 Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Family Compared to XC4000 and XC3000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block (CLB) Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Block (IOB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock: Abundant Local Routing Plus Versatile Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reset (GR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaBlock Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single- and Double-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VersaRing Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unrestricted User-Programmable I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Express Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181 4-181 4-182 4-182 4-183 4-183 4-183 4-184 4-184 4-185 4-185 4-185 4-186 4-186 4-187 4-187 4-188 4-188 4-188 4-189 4-190 4-191 4-191 4-191 4-191 4-192 4-192 4-192 4-194 4-194 4-194 4-194 4-196 4-196 4-197 4-197 4-197 4-198 4-199 4-199 4-199 4-199 4-199 4-199 4-200 4-200 4-203 4-203 4-179 XC5200 Series Table of Contents Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . XC5200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 CLB-to-Pad Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5202 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5204 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5206 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5210 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC5215 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203 4-203 4-203 4-204 4-205 4-205 4-205 4-206 4-206 4-206 4-206 4-207 4-207 4-208 4-209 4-210 4-211 4-212 4-223 4-223 4-226 4-230 4-235 4-241 4-248 4-248 4-248 XC5200L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-180 4-249 4-249 4-250 4-250 4-250 4-250 XC5200 Field Programmable Gate Arrays June 1, 1996 (Version 4.0) Preliminary Product Specification Features * Fully supported by XACTstepTM Development System - Includes complete support for XACT-PerformanceTM, X-BLOXTM, Unified Libraries, Relationally Placed Macros (RPMs), XDelay, and XCheckerTM - Wide selection of PC and workstation platforms - Interfaces to more than 100 third-party CAE tools * High-density family of Field-Programmable Gate Arrays (FPGAs) * Design- and process-optimized for low cost - 0.6-m three-layer metal (TLM) process * System performance up to 50 MHz * SRAM-based, in-system reprogrammable architecture * Flexible architecture with abundant routing resources - VersaBlockTM logic module - VersaRingTM I/O interface - Dedicated cell-feedthrough path - Hierarchical interconnect structure - Extensive registers/latches - Dedicated carry logic for arithmetic functions - Cascade chain for wide input functions - Dedicated IEEE 1149.1 boundary-scan logic - Internal 3-state bussing capability - Four global low-skew clock or signal distribution nets - Globally selectable CMOS or TTL input thresholds - Output slew-rate control - 8-mA sink current per output * Configured by loading binary file - Unlimited reprogrammability - Seven programming modes, including high-speed ExpressTM mode * 100% factory tested * 100% footprint compatibility for common packages Description The XC5200 Field-Programmable Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200 architecture for three-layer metal (TLM) technology and a 0.6-m CMOS SRAM process, dramatic advances have been made in silicon efficiency. These advances position the XC5200 family as a cost-effective, high-volume alternative to gate arrays. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to high-density programmable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-tomarket. Complete support for the XC5200 family is delivered through the familiar XACTstep software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and synthesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices. Table 1: Initial XC5200 Field-Programmable Gate Array Family Members Device XC5202 XC5204 XC5206 XC5210 XC5215 3,000 6,000 10,000 16,000 23,000 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22 Number of CLBs 64 120 196 324 484 Number of Flip-Flops 256 480 784 1,296 1,936 Number of I/Os 84 124 148 196 244 TBUFs per Horizontal Longline 10 14 16 20 24 Max Logic Gates Typical Gate Range June 1, 1996 (Version 4.0) 10,000 - 16,000 15,000 - 23,000 4-181 XC5200 Field Programmable Gate Arrays XC5200 Family Compared to XC4000 and XC3000 Series The registers in each XC5200 LC are optionally configurable as edge-triggered D-type flip-flops or as transparent level-sensitive latches. For readers already familiar with the XC4000 and XC3000 gate array series, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000 and XC3000 devices. The XC5200 CLB includes dedicated carry logic that provides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions. Configurable Logic Block (CLB) Resources Each XC5200 CLB contains four independent 4-input function generators and four registers, which are configured as four independent Logic CellsTM (LCs). The output from the function generator in each LC can be brought out as a CLB output and/or drive the D input of the register. A pair of LCs can be combined to form a 5-input function generator. There are four direct feedthrough paths for each XC5200 CLB, one per LC. These paths provide extra data input lines or serve as additional local routes without consuming any logic resources. XC4000 family: XC5200 devices have no wide edge decoders. XC4000 family: XC5200 dedicated carry logic differs from that of the XC4000 family in that the sum is generated in an additional function generator in the adjacent column. An XC5200 device thus uses twice as many function generators for adders, subtracters, accumulators, and some counters. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC4000 family: XC5200 lookup tables cannot be used as RAM. Table 2: Four Generations of Xilinx Field-Programmable Gate Array Families Parameter XC5200 XC4000 XC3000A/XC3100A XC2000 Function generators per CLB 4 3 2 2 Logic inputs per CLB 20 9 5 4 Logic outputs per CLB 12 4 2 2 Low-skew global buffers 4 8 2 2 Single-length lines 10 8 5 4 Double-length lines 4 4 0 0 Longlines 8 6 3 2 Direct connects 8 0 2 2 VersaRing yes no no no User RAM no yes no no Dedicated decoders no yes no no Cascade chain yes no no no Fast carry logic yes yes no no Internal 3-state drivers yes yes yes no IEEE boundary scan yes yes no no Output slew-rate control yes yes yes no Power-down option no no yes yes Crystal oscillator circuit no no yes yes 4-182 June 1, 1996 (Version 4.0) Input/Output Block (IOB) Resources The XC5200 family maintains footprint compatibility with the XC4000 family, but not with the XC3000 family. The XC5200 IOB does not include flip-flops or latches. The XC5200 family provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers. The XC5200 IOB provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems. Each XC5200 IOB is capable of 8-mA source and sink currents. IEEE 1149.1-type boundary scan is supported in each XC5200 IOB. XC3000 family: Each XC5200 IOB has access to tristatable Longlines by means of its own 3-state buffer (TBUF). Routing Resources The XC5200 family provides a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring VersaBlocks. Each XC5200 VersaBlock element has complete intra-CLB routing, the LIM, and offers four direct routing connections to each of the four neighboring CLBs. Any function generator or flip-flop thus has unrestricted connectivity to 19 other function generators or flip-flops: three in its own CLB, and 16 in the adjacent CLBs. These direct connects do not compete with the general routing resources (see Table 2). There is a special routing resource, the VersaRing, between the outer edge of the core CLB array and the ring of IOBs, providing added routability to the I/O. This feature is particularly important for designs that require a fixed pinout prior to completion. Each XC5200 TBUF can drive up to two horizontal Longlines. There are no internal pull-ups for XC5200 Longlines. Configuration and Readback XC4000 family: The XC5200 family provides a global reset but not a global set. XC5200 devices use a different configuration process than that of the XC3000 family, but use the same process as the XC4000 family. The rest of this discussion compares XC5200 features with those of the XC3000 family only. Although their configuration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices. The XC5200 PROGRAM pin is a single-function input pin that overrides all other inputs. The XC5200 INIT pin also acts as a Configuration Error output. XC5200 devices support two additional programming modes: Peripheral Synchronous and the new high-speed Express mode. XC5200 start-up can be synchronized to any user clock by means of a configuration option. The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flipflops. The XC5200 family does not provide an on-chip crystal oscillator amplifier, but it does provide an internal oscillator from which a variety of frequencies up to 16 MHz are available. Readback in the XC5200 family either ignores the flip-flop content, thereby avoiding the need for masking, or it takes a snapshot of all flip-flops at the start of Readback. Readback in the XC5200 family has the same polarity as Configuration, and can be aborted. The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source. June 1, 1996 (Version 4.0) 4-183 XC5200 Field Programmable Gate Arrays Architectural Overview Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, programmable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks. General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM). VersaBlock: Abundant Local Routing Plus Versatile Logic The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 2. Each LC contains a 4-input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for FPGAs. The storage device is configurable as either a D flip-flop or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions. Input/Output Blocks (IOBs) VersaRing VersaRing VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock GRM VersaBlock VersaRing GRM The XC5200 CLB consists of four LCs, as shown in Figure 3. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement 5-input functions. The challenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect -- the Local Interconnect Matrix (LIM) and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 4. The LIM provides 100% connectivity of the inputs and outputs of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes. The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a "sea of logic cells." Each VersaBlock has four 3-state buffers that share a common enable line and directly drive horizontal Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of logic functions, effectively implementing user designs in a hierarchical fashion. These resources also minimize local routing congestion and improve the efficiency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both fine-grain and coarsegrain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions. CO DO DI D GRM VersaBlock GRM VersaBlock F4 GRM Q FD F3 VersaBlock F2 F F1 VersaRing X CI CE CK CLR X4955 Figure 1: XC5200 Architectural Overview 4-184 X4956 Figure 2: XC5200 Logic Cell (Four LCs per CLB) June 1, 1996 (Version 4.0) VersaRing I/O Interface CO LC3 DO DI D Q F4 FD F3 F2 F F1 X LC2 DO DI D Q F4 FD F3 F2 F F1 X LC1 DO DI D Q F4 General Routing Matrix FD F3 F2 F F1 X LC0 DO DI D Q F4 FD F3 F2 F F1 X CI CE CK The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level testability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the I/O-to-gate ratio and decreasing the cost per I/O. A "freeway" of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manufactured concurrent with the logic design. CLR X4957 Figure 3: Configurable Logic Block The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight coupling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the development of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family contains six levels of interconnect hierarchy -- a series of single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each VersaBlock. Throughout the XC5200 interconnect, an efficient multiplexing scheme, in combination with three layer metal (TLM), was used to improve the overall efficiency of silicon usage. Performance Overview GRM 4 The XC5200 family has been benchmarked with many designs running synchronous clock rates up to 50 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the interconnect routing. Table 3 shows some performance numbers for representative circuits. A rough estimate of timing can be made by assuming 6 ns per logic level, which includes direct-connect routing delays. More accurate estimations can be made using the information in the Switching Characteristic Guideline section. 4 24 24 TS CLB LC3 4 LC2 4 4 4 4 LC1 LC0 LIM 4 4 Direct Connects X5707 Figure 4: VersaBlock June 1, 1996 (Version 4.0) 4-185 XC5200 Field Programmable Gate Arrays Table 3: Performance for Several Common Circuit Functions Function 16-bit Decoder from Input Pad 24-bit Accumulator 16-to-1 Multiplexer 16-bit Unidirectional Loadable Counter 16-bit U/D Counter 16-bit Adder 24-bit Loadable U/D Counter -6 9 ns 32 MHz 16 ns 40 MHz 40 MHz 24 ns 36 MHz XC5200 Speed Grade -5 -4 8 ns 7 ns 39 MHz 45 MHz 13 ns 11 ns 50 MHz 59 MHz 50 MHz 59 MHz 20 ns 17 ns 42 MHz 48 MHz Preliminary -3 6 ns 50 MHz 9 ns 65 MHz 65 MHz 15 ns 52 MHz Advance Development System The powerful features of the XC5200 device family require an equally powerful, yet easy-to-use, set of development tools. Xilinx provides an enhanced version of the Xilinx Automatic CAE Tools (XACTstep), optimized for the XC5200 family. As with other logic technologies, the basic methodology for XC5200 FPGA design consists of three interrelated steps: design entry, implementation, and verification. Popular generic tools are used for entry and simulation (for example, Viewlogic Systems's Viewdraw schematic editor and Viewsim simulator), but architecture-specific tools are needed for implementation. Several advanced features of the XACTstep system facilitate XC5200 FPGA design. RPMs -- schematic-based macros with relative location constraints to guide their placement within the FPGA -- help to ensure an optimized implementation for common logic functions. An abundance of local routing permits RPMs to be contained within a single VersaBlock or to span across multiple VersaBlocks. XACT-Performance allows designers to enter the exact performance requirements during design entry, at the schematic level, to guide PPR. Design Entry Designs can be entered graphically, using schematic-capture software, or in any of several text-based formats (such as Boolean equations, state-machine descriptions, and high-level design languages). Xilinx and third-party CAE vendors have developed library and interface products compatible with a wide variety of design-entry and simulation environments. A standard interface-file specification, Xilinx Netlist File (XNF), is provided to simplify file transfers into and out of the XACTstep development system. Xilinx offers XACTstep development system interfaces to the following design environments: * Xilinx Foundation Series * Viewlogic Systems (Viewdraw, Viewsim) 4-186 * Mentor Graphics V8 (NETED, QuickSim, Design Architect, QuickSim II) * OrCAD (SDT, VST) * Synopsys (Design Compiler, FPGA Compiler) * Xilinx-ABEL (State Machine module generator) * X-BLOX (Graphical Mode Generator) Many other environments are supported by third-party vendors. Currently, more than 100 packages are supported. The unified schematic library for the XC5200 FPGA reflects the wide variety of logic functions that can be implemented in these versatile devices. The library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. Designing with macros is as easy as designing with standard SSI/MSI functions. The "soft macro" library contains detailed descriptions of common logic functions, but does not contain any partitioning or routing information. The performance of these macros depends, therefore, on how the PPR software processes the design. RPMs, on the other hand, do contain predetermined partitioning and relative placement information, resulting in an optimized implementation for these functions. Users can create their own library elements -- either soft macros or RPMs -- based on the macros and primitives of the standard library. The X-BLOX design language is a graphics-based highlevel description language (HDL) that allows designers to use a schematic editor to enter designs as a set of generic modules. The X-BLOX compiler synthesizes and optimizes the modules for the target device architecture, automatically choosing the appropriate architectural resources for each function. The XACTstep design environment supports hierarchical design entry, with top-level drawings defining the major functional blocks, and lower-level descriptions defining the logic in each block. The implementation tools automatically combine the hierarchical elements of a design. Different June 1, 1996 (Version 4.0) hierarchical elements can be specified with different design entry tools, allowing the use of the most convenient entry method for each portion of the design. Design Implementation The design implementation tools satisfy the requirements for an automated design process. Logic partitioning, block placement, and signal routing are performed by the PPR program. The partitioner takes the logic from the entered design and maps the logic into the architectural resources of the FPGA (such as the logic blocks, I/O blocks, and 3state buffers). The placer then determines the best locations for the blocks, depending on their connectivity and the required performance. The router finally connects the placed blocks together. The PPR algorithms support fully automatic implementation of most designs. However, for demanding applications, the user may exercise various degrees of control over the automated implementation process. Optionally, user-designated partitioning, placement, and routing information can be specified as part of the design-entry process. The implementation of highly structured designs can benefit greatly from the basic floorplanning techniques familiar to designers of large gate arrays. The PPR program includes XACT-Performance, a feature that allows designers to specify the timing requirements along entire paths during design entry. Timing path analysis routines in PPR then recognize and accommodate the user-specified requirements. Timing requirements can be entered on the schematic in a form directly relating to the system requirements (such as the targeted minimum clock frequency, or the maximum allowable delay on the data path between two registers). So, while the timing of each individual net is not predictable, the overall performance of the system along entire signal paths is automatically tailored to match user-generated specifications. June 1, 1996 (Version 4.0) Design Verification The high development cost associated with common maskprogrammed gate arrays necessitates extensive simulation to verify a design. Due to the custom nature of masked gate arrays, mistakes or last-minute design changes cannot be tolerated. A gate-array designer must simulate and test all logic using simulation software. Simulation describes what happens in a system under worst-case situations. However, simulation can be tedious and slow, and simulation vectors must be generated. A few seconds of system time can take weeks to simulate. Programmable-gate-array users, however, can use in-circuit debugging techniques in addition to simulation. Because Xilinx devices are reprogrammable, designs can be verified in real time without the need for extensive simulation vectors. The XACTstep development system supports both simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database. This data can then be sent to the simulator to verify timing-critical portions of the design database using XDELAY, the Xilinx static timing analyzer tool. Back-annotation -- the process of mapping the timing information back into the signal names and symbols of the schematic -- eases the debugging effort. For in-circuit debugging, the XACTstep development system includes a serial download and readback cable (XChecker) that connects the FPGA in the system to the PC or workstation through an RS232 serial port. The engineer can download a design or a design revision into the system for testing. The designer can also single-step the logic, read the contents of the numerous flip-flops on the device, and observe internal logic levels. Simple modifications can be downloaded into the system in a matter of minutes. 4-187 XC5200 Field Programmable Gate Arrays Detailed Functional Description CLB Logic Figure 3 shows the logic in the XC5200 CLB, which consists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a DType flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are: * * * * High-speed carry propagate logic. High-speed pattern decoding. High-speed direct connection to flip-flop D-inputs. Each flip-flop can be programmed individually as either a transparent, level-sensitive latch or a D flip-flop. * Four 3-state buffers with a shared Output Enable. * Two 4-input LUTs can be combined to form an independent 5-input LUT. 5-Input Functions Figure 5 illustrates how the outputs from the LUTs from LC0 and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined. CO DO DI Q D FD I1 I2 I3 I4 F4 F3 F2 F1 F X LC1 F5_MUX DO I5 DI D Q out Qout FD F4 F3 F2 F1 F X CI CE CK 5-Input Function CLR LC0 X5710 Figure 5: Two LUTs in Parallel Combined to Create a 5-input Function 4-188 June 1, 1996 (Version 4.0) Carry Function The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) symbol on a schematic is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit high-speed carry propagate per logic cell (four bits per CLB). While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic function. Figure 6 represents an example of an adder function. The carry propagate is performed on the CLB shown, which also generates the half-sum for the four-bit adder. An adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The XC5200 library contains a set of RPMs and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement customized RPMs, freeing the designer from the need to become an expert on architectures. carry out A3 or B3 A3 and B3 to any two CO DO DI D F4 F3 F2 F1 carry3 DO XOR X half sum3 F4 F3 F2 F1 FD XOR X LC3 A2 or B2 A2 and B2 to any two D F4 F3 F2 F1 DO DI Q D FD CY_MUX XOR X half sum2 F4 F3 F2 F1 XOR X A1 and B1 to any two D F4 F3 F2 F1 D FD CY_MUX DO DI Q XOR X half sum1 F4 F3 F2 F1 A0 and B0 to any two DO DI XOR X F4 F3 F2 F1 XOR X CI LC1 DO DI CE CK CLR Q D FD CY_MUX sum1 carry0 Q D Q FD LC1 A0 or B0 sum2 LC2 DO carry1 DI Q FD LC2 A1 or B1 sum3 LC3 DO carry2 DI Q D FD CY_MUX CO DI Q half sum0 LC0 F4 F3 F2 F1 FD XOR X CI CE CK CLR sum0 LC0 carry in 0 CY_MUX F=0 Initialization of carry chain (One Logic Cell) X5709 Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate June 1, 1996 (Version 4.0) 4-189 XC5200 Field Programmable Gate Arrays Cascade Function Each CY_MUX can be connected to the CY_MUX in the adjacent LC to provide cascadable decode logic. Figure 7 illustrates how the 4-input function generators can be configured to take advantage of these four cascaded CY_MUXes. Note that AND and OR cascading are specific cases of a general decode. In AND cascading all bits are decoded equal to logic one, while in OR cascading all bits are decoded equal to logic zero. The flexibility of the LUT achieves this result. cascade out CO DO DI A15 F4 A14 F3 A13 F2 A12 F1 out Q D FD CY_MUX AND X LC3 DO DI D A11 A10 A9 A8 F4 F3 F2 F1 Q FD CY_MUX AND X LC2 DO DI D A7 F4 A6 F3 A5 F2 A4 F1 Q FD CY_MUX AND X LC1 DO DI Q D A3 F4 A2 F3 A1 F2 A0 F1 FD CY_MUX AND X CE CK CI CLR LC0 cascade in CY_MUX F=0 Initialization of carry chain (One Logic Cell) X5708 Figure 7: XC5200 CY_MUX Used for Decoder Cascade Logic 4-190 June 1, 1996 (Version 4.0) 3-State Buffers Global Reset (GR) The XC5200 family has four dedicated TBUFs per CLB. The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLB's output enable (TS) control signal drives the enable to all four buffers (see Figure 8). Each TBUF can drive up to two horizontal Longlines. On start-up, all XC5200 internal flip-flops are reset, using a global reset (GR) signal. The user can assign the pin location for the GR signal and use it to reset asynchronously all of the flip-flops in the design without using general routing resources. The user can also assign a positive or negative polarity to GR. Oscillator The XC5200 oscillator (OSC52) divides the internal 16MHz clock or a user clock that is connected to the "C" pin. The user then has the choice of dividing by 4, 16, 64, or 256 for the "OSC1" output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the "OSC2" output. The division is specified via a "DIVIDEn_BY=x" attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specified (see Figure 9). Boundary Scan XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. Boundary-scan operation is independent of individual IOB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after configuration provides flexibility for interconnect testing. TS Also, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This technique partially compensates for the lack of INTEST support. CLB CLB LC3 The public boundary-scan instructions are always available prior to configuration. After configuration, the public instructions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. LC2 LC1 LC0 In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA device, and to read back the configuration data. Horizontal Longlines X5706 Figure 8: XC5200 3-State Buffer OSC5 All of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the User Register are provided (Reset, Update, and Shift), representing the decoding of the corresponding state of the boundary-scan internal state machine. OSC1 OSC2 CK_DIV CLK OSC1 OSC2 Figure 9: XC5200 Oscillator Macros June 1, 1996 (Version 4.0) 4-191 XC5200 Field Programmable Gate Arrays VersaBlock Routing Local Interconnect Matrix The GRM connects to the VersaBlock via 24 bidirectional ports (M0-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these 24 ports. Four 3-statable unidirectional signals (TQ0-TQ3) drive out of the VersaBlock directly onto the horizontal Longlines. Two horizontal global nets (GH0 and GH1) and two vertical global nets (GV0 and GV1) connect directly to every CLB clock pin; they can connect to other CLB inputs via the GRM. Each CLB also has four unidirectional direct connects to each of its four neighboring CLBs. These direct connects can also feed directly back to the CLB (see Figure 10). In addition, each CLB has 16 direct inputs, four direct connections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM. The 13 CLB outputs (12 LC outputs plus a Vcc/GND signal) connect to the eight VersaBlock outputs via the output multiplexers, which consist of eight fully populated 13-to-1 multiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feedback path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight multiplexer outputs can connect to the GRM through the bidirectional M0-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB. 4-192 CLB inputs have several possible sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers (GH0, GH1, GV0, and GV1), and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The flexibility of LUT input swapping and LUT mapping compensates for this limitation. For example, if a 2input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT. Direct Connects The unidirectional direct-connect segments are connected to the logic input/output pins through the CLB's input and output multiplexer array, and thus bypass the programmable routing matrix altogether. These lines are intended to increase the routing channel utilization where possible, while simultaneously reducing the delay incurred in speedcritical connections. The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce set-up time, clock-to-out, and combinational propagation delay. The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro performance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths. June 1, 1996 (Version 4.0) To GRM M0-M23 24 TS 4 Global Nets 8 COUT North 4 South 4 East 4 West 4 4 4 To Longlines and GRM TQ0-TQ3 4 Direct to East CLB 5 Input Multiplexers LC3 5 LC2 5 LC1 5 LC0 3 3 VCC /GND 3 Output Multiplexers 8 4 3 Direct North CLK 4 Feedback 4 Direct West CE CLR CIN 4 4 Direct South X5724 Figure 10: VersaBlock Details June 1, 1996 (Version 4.0) 4-193 XC5200 Field Programmable Gate Arrays General Routing Matrix The General Routing Matrix, shown in Figure 11, provides flexible bidirectional connections to the Local Interconnect Matrix through a hierarchy of different-length metal segments in both the horizontal and vertical directions. A programmable interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a memory element, provides bidirectional (in some cases, unidirectional) connection between two adjoining wires. A collection of PIPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and associated routing segments combine to provide a powerful interconnect hierarchy: * Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions. * Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (nonneighboring) CLBs in four directions. * Eight horizontal and eight vertical bidirectional Longline segments span the width and height of the chip, respectively. * Two low-skew horizontal and vertical unidirectional global-line segments span each row and column of the chip, respectively. Single- and Double-Length Lines The single- and double-length bidirectional line segments make up the bulk of the routing channels. The doublelength lines hop across every other CLB to reduce the propagation delays in speed-critical nets. Regenerating the signal strength is recommended after traversing three or four such segments. XACTstep place-and-route software automatically connects buffers in the path of the signal as necessary. Single- and double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto single- and double-length lines. As a general rule, Longline and global-line connections to the programmable routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. Longlines Longlines are used for high-fan-out signals, 3-state busses, low-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the 4-194 total number of Longlines by electrically dividing them into two separated half-lines. The horizontal Longlines are driven by the 3-state buffers in each CLB, and are driven by similar buffers at the periphery of the array from the VersaRing I/O Interface. Bus-oriented microprocessor designs are accommodated by using horizontal Longlines in conjunction with the 3-state buffers in the CLB and in the VersaRing. Additionally, programmable keeper cells at the periphery can be enabled to retain the last valid logic level on the Longlines when all buffers are in 3-state mode. Longlines connect to the single-length or double-length lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PIPs in the General Routing Matrix is not possible. Again, as a general rule, long- and global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix. The XC5200 family has no pull-ups on the ends of the Longlines sourced by TBUFs. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing functions requiring pull-ups for undefined states (i.e., bus applications) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. In the case of 3-state bus applications, the user must insure that all states of the multiplexing function are defined. This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated. Global Lines Global buffers in Xilinx FPGAs are special buffers that drive a dedicated routing network called Global Lines, as shown in Figure 12. This network is intended for high-fan-out clocks or other control signals, to maximize speed and minimize skewing while distributing the signal to many loads. The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the FPGA. June 1, 1996 (Version 4.0) GRM GRM VersaBlock GRM GRM VersaBlock VersaBlock GRM VersaBlock 1 GRM VersaBlock VersaBlock 2 GRM GRM VersaBlock GRM VersaBlock VersaBlock 3 4 Six Levels of Routing Hierarchy 1 Single-length Lines 2 Double-length Lines 3 Direct Connects GRM 4 4 24 24 TS CLB LC3 4 4 4 4 Longlines and Global Lines LC2 4 4 LC1 6 LC0 5 LIM 6 Local Interconnect Matrix Logic Cell Feedthrough Path (Contained within each Logic Cell) LIM 4 5 4 Direct Connects X4963 Figure 11: XC5200 Interconnect Structure June 1, 1996 (Version 4.0) 4-195 XC5200 Field Programmable Gate Arrays The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals. Four clock input pads at the corners of the chip, as shown in Figure 12, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic. PIPs from several routing channels within the VersaRing can also be configured to drive the global-line buffers. The input buffer has globally selected CMOS and TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip setup and hold times. Minimum ESD protection is 3 KV using the Human Body Model. VersaRing 8 VersaRing Input/Output Interface 8 2 2 The VersaRing, shown in Figure 13, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The VersaRing decouples the pad ring's pitch from the core's pitch. Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on the other side. Depending on placement and pad-cell pitch, any number of pad cells to a maximum of four can be connected to a VersaRing cell. Pad 2 GRM Pad 10 Interconnect Pad 4 4 VersaBlock Pad 8 Input/Output Pad 8 2 The I/O pad, shown in Figure 14, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. Pad 2 GRM Pad 10 Interconnect Pad 4 VersaBlock GCK1 2 8 4 Pad 2 GCK4 8 8 2 X5705 Figure 13: VersaRing I/O Interface Vcc I PAD GCK2 GCK3 O X5704 OE Figure 12: Global Lines X4964 Figure 14: XC5200 I/O Block 4-196 June 1, 1996 (Version 4.0) Pin Descriptions Permanently Dedicated Pins Vcc Eight or more (depending on package type) connections to the nominal +5-V supply voltage. All must be connected. GND M0, M1, M2 As mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. After configuration, M0, M1, and M2 become user-programmable I/O. Eight or more (depending on package type) connections to ground. All must be connected. TDO CCLK If boundary scan is not used, this pin becomes user-programmable I/O. During configuration, Configuration Clock is an output of the FPGA in master modes or Asynchronous Peripheral mode, but is an input to the FPGA in Slave Serial mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and can be selected as Readback Clock. DONE This is a bidirectional signal with optional pull-up resistor. As an output, it indicates the completion of the configuration process. The configuration program determines the exact timing, the clock source for the Low-to-High transition, and enable of the pull-up resistor. If boundary scan is used, this is the Test Data Output. TDI, TCK, TMS If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs, respectively, coming directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the boundary scan option is not selected, all boundary scan functions are inhibited once configuration is completed. These pins become user-programmable I/O. HDC As an input, a Low level on DONE can be configured to delay the global logic initialization or the enabling of outputs. High During Configuration is driven High until configuration is completed. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin. PROGRAM LDC This is an active-Low input, held Low during configuration, that forces the FPGA to clear its configuration memory. Low During Configuration is driven Low until configuration completes. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin. When PROGRAM goes High, the FPGA executes a complete clear cycle, before it goes into a WAIT state and releases INIT. After configuration, it has an optional pull-up resistor. User I/O Pins That Can Have Special Functions RDY/BUSY During peripheral modes, this pin indicates when it is appropriate to write another byte of data into the FPGA device. The same status is also available on D7 in Asynchronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, this is a user-programmable I/O pin. INIT Before and during configuration, this is a bidirectional signal. An external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA device in the internal WAIT state before the start of configuration. Master-mode devices stay in a WAIT state an additional 50 to 250 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After configuration, this is a user-programmable I/O pin. RCLK GCK1 - GCK4 During Master Parallel configuration, each change on the A0-17 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration, this is a userprogrammable I/O pin. Four Global Inputs each drive a dedicated internal global net with short delay and minimal skew. If not used for this purpose, any of these pins is a user-programmable I/O pin. June 1, 1996 (Version 4.0) 4-197 XC5200 Field Programmable Gate Arrays CS0, CS1, WS, RS DIN These four inputs are used in peripheral modes. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer; a Low on Read Strobe (RS) changes D7 into a status output: High if Ready, Low if Busy, and D0...D6 are active High. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. In Express mode, CS1 is also used as a serial-enable signal for daisy chaining. During Slave Serial or Master Serial configuration modes, this is the serial configuration data input receiving data on the rising edge of CCLK. A0 - A17 During Master Parallel mode, these 18 output pins address the configuration EPROM. After configuration, these are user-programmable I/O pins. D0 - D7 During Master Parallel, peripheral, and Express configuration modes, these eight input pins receive configuration data. After configuration, they are user-programmable I/O pins. 4-198 During parallel configuration modes, this is the D0 input. After configuration, DIN is a user-programmable I/O pin. DOUT During configuration in any non-Express mode, this is the serial configuration data output that can drive the DIN of daisy-chained slave FPGA devices. DOUT data changes on the falling edge of CCLK. After configuration, DOUT is a user-programmable I/O pin. In Express mode, this is the enable output that can drive CS1 of daisy-chained FPGA devices. Unrestricted User-Programmable I/O Pins I/O A pin that can be configured to be input and/or output after configuration is completed. Before configuration is completed, these pins have an internal high-impedance pull-up resistor that defines the logical level as High. June 1, 1996 (Version 4.0) Configuration Configuration is the process of loading design-specific programming data into one or more FPGA devices to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Each configuration bit defines the state of a static memory cell that controls either a function LUT bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist file. It automatically partitions, places, and routes the logic and generates the configuration data in PROM format. Modes The XC5200 family has seven modes of configuration, selected by a 3-bit input code applied to the FPGA mode pins (M0, M1, and M2). There are three self-clocking Master modes, two Peripheral modes, a Slave serial mode, and a new high-speed Slave parallel mode called the Express. See Table 4. Brief descriptions of the seven modes are provided below. Master Modes The Master modes use an internal oscillator to generate CCLK for driving potential slave devices, and to generate address and timing for external PROM(s) containing the configuration data. Master Parallel (up or down) modes generate the CCLK signal and PROM addresses, and receive byte parallel data, which is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing con- ventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from a Xilinx serial-configuration PROM. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A READY/BUSY status is available as a handshake signal. In the asynchronous mode, the internal oscillator generates a CCLK burst signal that serializes the byte-wide data. In the synchronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode In the Slave Serial mode, the FPGA device receives serialconfiguration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs so that the devices can be configured simultaneously. Daisy Chaining Multiple devices may be daisy-chained together so that they may be programmed using a single bitstream. The first device in the chain may be set to operate in any mode; all other devices in the chain must be set to operate in Slave Serial mode. Express-mode daisy chains are the only exception: every device in such a chain must be set to operate in Express mode. All CCLK pins are tied together, and the data chain passes from DOUT to DIN of successive devices along the chain. Table 4: Configuration Modes Mode Master Serial Slave Serial Master Parallel up Master Parallel down Peripheral Synchronous * Peripheral Asynchronous Express Reserved M2 0 1 1 1 0 1 0 0 M1 0 1 0 1 1 0 1 0 M0 0 1 0 0 1 1 0 1 CCLK output input output output input output input -- Data Bit-Serial Bit-Serial Byte-Wide, 00000 Byte-Wide, 3FFFF Byte-Wide Byte-Wide Byte-Wide -- * Peripheral Synchronous can be considered byte-wide Slave Parallel June 1, 1996 (Version 4.0) 4-199 XC5200 Field Programmable Gate Arrays +5V 8 M0 M1 CS1 DATA BUS 8 M2 8 XC5200 5K PROGRAM INIT M1 CS1 DOUT D0-D7 +5V M0 To Additional Optional Daisy-Chained Devices DOUT D0-D7 Optional Daisy-Chained XC5200 PROGRAM PROGRAM INIT INIT CCLK M2 CCLK CCLK X5086 To Additional Optional Daisy-Chained Devices Figure 15: Express Mode Express Mode The Express mode (see Figure 15) is similar to the Slave serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK while byte-wide data is loaded directly into the configuration data shift registers. In this mode the XC5200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to an 80MHz serial rate, because eight bits of configuration data are being loaded per CCLK cycle. An XC5210 in the Express mode, for instance, can be configured in about 2 ms. The Express mode does not support CRC error checking, but does support constant-field error checking. In the Express configuration mode, an external signal drives the CCLK input(s) of the FPGA device(s). The first byte of parallel configuration data must be available at the D inputs of the FPGA devices a short set-up time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 16. Bitstream generation currently generates a bitstream sufficient to program in all configuration modes except Express. Extra CCLK cycles are necessary to complete the configuration, since in this mode data is read at a rate of eight bits per CCLK cycle instead of one bit per cycle. Normally the entire start-up sequence requires a number of bits that is equal to the number of CCLK cycles needed. An additional 4-200 five CCLKs (equivalent to 40 extra bits) will guarantee completion of configuration, regardless of the start-up options chosen. The Express mode is supported by the XC5200 and XC4000EX families. It may be used, if XC5200 and XC4000EX devices are daisy-chained. If the first device is configured in the Express mode, additional devices may be daisy-chained only if every device in the chain is also configured in the Express mode. CCLK pins are tied together and D7-D0 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pull-up). The status pin DOUT is pulled LOW two internal-oscillator cycles (nominally 1 MHz) after INIT is recognized as High, and remains Low until the device's configuration memory is full. Then DOUT is pulled High to signal the next device in the chain to accept the configuration data on the D7-D0 bus. All devices receive and recognize the six bytes of preamble and length count, irrespective of the level on CS1; but subsequent frame data is accepted only when CS1 is High and the device's configuration memory is not already full. Format Table 5 describes the XC5200 configuration data stream. Table 6 describes the internal configuration data structure. June 1, 1996 (Version 4.0) CCLK 1 TIC INIT TCD 3 2 T DC D0-D7 BYTE 0 BYTE 1 BYTE 2 BYTE 3 Serial Data Out (DOUT) FPGA Filled Internal INIT RDY/BUSY CS1 X5087 Figure 16: Express Mode Programming Switching Characteristics CCLK Description INIT (High) Setup time required DIN Setup time required DIN Hold time required CCLK High time CCLK Low time CCLK Frequency June 1, 1996 (Version 4.0) 1 2 3 Symbol TIC TDC TCD TCCH TCCL FCC Min 5 30 0 30 30 Max 10 Units s ns ns ns ns MHz 4-201 XC5200 Field Programmable Gate Arrays Table 5: XC5200 Bitstream Format Occurrences 11111111 11110010 COUNT(23:0) 11111111 11111110 DATA(N-1:0) CRC(3:0) or 0110 1111 FFFFFF 11111110 FFFF...FF FF Once per bitstream VCC 3V Boundary Scan Instructions Available: Yes Generate One Time-Out Pulse of 4 ms XC5202 XC5204 XC5206 XC5210 XC5215 VersaBlock Array 8x8 10 x 12 14 x 14 18 x 18 22 x 22 PROM Size (bits) 42,416 70,704 106,288 165,488 237,744 EXTEST* SAMPLE/PRELOAD* BYPASS CONFIGURE* Completely Clear Configuration Memory ~1.3 s per Frame (*only when PROGRAM = High) INIT High? if Master Yes Once per device Once per bitstream Xilinx Serial Prom Needed XC1765D XC17128D XC17128D XC17256D XC17256D Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill bits * + 24 extended write bits = (34 x number of Rows) + 100 * In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4 Number of Frames = (12 x number of Columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit = (12 x number of Columns) + 16 Program Data = (Bits per Frame x Number of Frames) + 48 header bits + 8 postamble bits + 240 fill bits + 8 start-up bits = (Bits per Frame x Number of Frames) + 304 PROM Size = Program Data 4-202 PROGRAM = Low Yes Once per data frame No Sample Mode Lines Master CCLK Goes Active after 50 to 250 s Load One Configuration Data Frame Table 6: Internal Configuration Data Structure Device No Frame Error Yes Pull INIT Low and Stop LDC Output = L, HDC Output = H Fill Byte Preamble Length Counter Fill Byte Start Byte Data Frame * Cyclic Redundancy Check or Constant Field Check Fill Nibble Extend Write Cycle Postamble Fill Bytes (30) Start-Up Byte Value No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes No Pass Configuration Data to DOUT CCLK Count Equals Length Count Yes No Start-Up Sequence F EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK Operational If Boundary Scan is Selected I/O Active Data Type X6037 Figure 17: Configuration Sequence June 1, 1996 (Version 4.0) Configuration Sequence Configuration Figure 17 illustrates the XC5200 configuration sequence. This section describes the configuration sequence in detail. The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream. Configuration will not begin until the internal configuration logic reset is released, which happens two cycles after INIT goes High. A master device's configuration is delayed from 32 to 256 s to ensure proper operation with any slave devices driven by the master device. Power-On Time-Out An internal power-on reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA begin to operate (i.e., performs a write-andread test of a sample pair of configuration memory bits), the programmable I/O buffers are 3-stated with active highimpedance pull-up resistors. A time-out delay -- nominally 4 ms -- is initiated to allow the power-supply voltage to stabilize. For correct operation the power supply must reach VCC(min) by the end of the time-out, and must not dip below it thereafter. There is no distinction between master and slave modes with regard to the time-out delay. Instead, the INIT line is used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For proper operation with XC3000 devices, the RESET signal, which is used in XC3000 to delay configuration, should be connected to INIT. If the time-out delay is insufficient, configuration should be delayed by holding the INIT pin Low until the power supply has reached operating levels. During all three phases -- Power-on, Initialization, and Configuration -- DONE is held Low; HDC, LDC, and INIT are active; DOUT is driven; and all I/O buffers are disabled. Initialization This phase clears the configuration memory and establishes the configuration mode. The configuration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the configuration memory is completely cleared. The device then tests for the absence of an external active-low level on INIT. The mode lines are sampled two internal clock cycles later (nominally 2 s). The master device waits an additional 32 s to 256 s (nominally 64-128 s) to provide adequate time for all of the slave devices to recognize the release of INIT as well. Then the master device enters the Configuration phase. June 1, 1996 (Version 4.0) A preamble field at the beginning of the configuration data stream indicates that the next 24 bits represent the length count. The length count equals the total number of configuration bits needed to load the complete configuration data to all daisy-chained devices. Once the preamble and length-count values have been passed through to the next device in the daisy-chain, DOUT is held High to prevent start bits from reaching any daisy-chained devices. After fully configuring itself, the device passes serial data to downstream daisy-chained devices via DOUT until the full length count is reached. Errors in the configuration bitstream are checked at the end of a frame of data. The device does not check the preamble or length count for errors. In a daisy-chained configuration, configuration data for downstream devices are not checked for errors. If an error is detected after reading a frame, the ERR pin (also known as INIT) is immediately pulled Low and all configuration activity ceases. However, a master or Peripheral Asynchronous device will continue outputting a configuration clock and incrementing the PROM address indefinitely even though it will never complete configuration. A reprogram or power-on must be applied to remove the device from this state. Start-Up and Operation The XC5200 start-up sequence is identical to that of the XC4000 family. Each of these events may occur in any order: (a) DONE is pulled High; and/or (b) user I/Os become active; and/or (c) Internal Reset is deactivated. As a configuration option, the three events may be triggered by a user clock rather than by CCLK, or the start-up sequence may be delayed by externally holding the DONE pin Low. In any mode, the clock cycles of the start-up sequence are not included in the length count. The length of the bitstream is greater than the length count. 4-203 XC5200 Field Programmable Gate Arrays Pin Functions During Configuration CONFIGURATION MODE: SLAVE <1:1:1> MASTER-SER <0:0:0> ASYN.PERIPH MASTER-HIGH MASTER-LOW <1:0:1> <1:1:0> <1:0:0> A16 A17 TDI TCK TMS TDI TCK TMS TDI TCK TMS TDI TCK TMS M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) M1 (HIGH) (I) M0 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT-ERROR * HDC (HIGH) LDC (LOW) INIT-ERROR * HDC (HIGH) LDC (LOW) INIT-ERROR * DONE PROGRAM (I) DONE PROGRAM (I) DONE PROGRAM (I) DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DIN (I) DOUT CCLK (I) TDO DIN (I) DOUT CCLK (O) TDO SYN.PERIPH <0:1:1> DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK (I) TDO * INIT is an open-drain output during configuration EXPRESS <0:1:0> USER OPERATION A16 A17 TDI TCK TMS GCK1-I/O I/O TDI TDI TDI-I/O TCK TCK TCK-I/O TMS TMS TMS-I/O I/O M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) I/O M0 (HIGH) (I) M0 (LOW) (I) M0 (LOW) (I) M0 (LOW) (I) I/O M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (LOW) (I) I/O GCK2-I/O HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O INIT-ERROR * INIT-ERROR * INIT-ERROR * INIT-ERROR * I/O I/O DONE DONE DONE DONE DONE PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O GCK3-I/O DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/O DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/O I/O CSO (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/O DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/O I/O RS (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/O DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O RDY/BUSY RCLK RCLK I/O DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O DOUT DOUT DOUT DOUT I/O CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I) TDO TDO TDO TDO TDO-I/O A0 A0 I/O WS (I) A1 A1 GCK4-I/O CS1 (I) A2 A2 CS1 (I) I/O A3 A3 I/O A4 A4 I/O A5 A5 I/O A6 A6 I/O A7 A7 I/O A8 A8 I/O A9 A9 I/O A10 A10 I/O A11 A11 I/O A12 A12 I/O A13 A13 I/O A14 A14 I/O A15 A15 I/O ALL OTHERS (I) Represents an input (O) Represents an output Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 100-kW pull-up resistor. 4-204 June 1, 1996 (Version 4.0) Configuration Switching Characteristics T POR Vcc RE-PROGRAM >300 ns PROGRAM T PI INIT T ICCK TCCLK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) DONE RESPONSE VALID X1532 <300 ns I/O Master Modes Description Power-On-Reset Program Latency CCLK (output) Delay period (slow) period (fast) Symbol TPOR TPI TICCK TCCLK TCCLK Min 2 6 40 640 100 Max 15 70 375 3000 375 Units ms s per CLB column s ns ns Symbol Min Max Units Slave and Peripheral Modes Description Power-On-Reset TPOR 2 15 ms Program Latency TPI 6 70 s per CLB column CCLK (input) Delay (required) TICCK 5 s period (required) TCCLK 100 ns Note: At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until VCC is valid. June 1, 1996 (Version 4.0) 4-205 XC5200 Field Programmable Gate Arrays XC5200 Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1 XC5200 Operating Conditions Symbol Description VCC Supply voltage relative to GNDCommercial:0C to 85C junction Supply voltage relative to GNDIndustrial:-40C to 100C junction High-level input voltage -- TTL configuration VIHT VILT Low-level input voltage -- TTL configuration VIHC High-level input voltage -- CMOS configuration VILC Low-level input voltage -- CMOS configuration TIN Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns Min 3.86 Max Units V V mA A pF mA XC5200 DC Characteristics Over Operating Conditions Symbol VOH VOL ICCO IIL CIN IRIN Note: Description High-level output voltage @ IOH = -8.0 mA, VCC min Low-level output voltage @ IOL = 8.0 mA, VCC max (Note 1) Quiescent FPGA supply current (Note 1) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) -10 0.02 0.4 15 +10 15 0.25 1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a MakeBits tie option. 1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. 4-206 June 1, 1996 (Version 4.0) XC5200 Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Description Units Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature in plastic packages Junction temperature in ceramic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 V V V C C C C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC5200 Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Global Signal Distribution From pad through global buffer, to any clock (CK) -6 -5 -4 -3 Max (ns) Max (ns) Max (ns) 8.5 8.7 8.8 8.8 9.9 8.5 8.3 Symbol Device Max (ns) TBUFG XC5202 XC5204 XC5206 XC5210 XC5215 9.1 9.3 9.4 9.4 10.5 PRELIMINARY ADVANCE Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. June 1, 1996 (Version 4.0) 4-207 XC5200 Field Programmable Gate Arrays XC5200 Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description -6 -5 -4 -3 Max (ns) Max (ns) Max (ns) 3.8 4.1 4.2 4.2 4.6 5.6 5.9 6.0 6.0 6.3 2.8 3.3 3.2 5.0 4.7 Symbol Device Max (ns) TIO XC5202 XC5204 XC5206 XC5210 XC5215 XC5202 XC5204 XC5206 XC5210 XC5215 XC52xx 6.0 6.4 6.6 6.6 7.3 7.8 8.3 8.4 8.4 8.9 3.0 TBUF driving a Longline TS I O TBUF I to Longline, while TS is Low; i.e., buffer is constantly active TS going Low to Longline going from floating High or Low to active Low or High TS going High to TBUF going inactive, not driving Longline TON TOFF PRELIMINARY ADVANCE Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. 4-208 June 1, 1996 (Version 4.0) XC5200 CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Combinatorial Delays F inputs to X output DI inputs to DO output (Logic-Cell Feedthrough) F inputs via F5_MUX to DO output Carry Delays Incremental delay per bit Carry-in overhead from DI Carry-in overhead from F Carry-out overhead to DO Sequential Delays Clock (CK) to out (Q) (Flip-Flop) Gate (Latch enable) going active to out (Q) Set-up Time Before Clock (CK) F inputs F inputs via F5_MUX DI input CE input Hold Times After Clock (CK) F inputs F inputs via F5_MUX DI input CE input Clock Widths Clock High Time Clock Low Time Export Control Max. flip-flop toggle rate (MHz) Reset Delays Width (High) Delay from CLR to Q (Flip-Flop) Delay from CLR to Q (Latch) Global Reset Delays (see Note 2) Width (High) Delay from internal GCLR to Q Symbol -6 Min (ns) -5 Max (ns) Min (ns) -4 Max (ns) Min (ns) -3 Max (ns) Min (ns) Max (ns) TILO TIDO 5.6 4.3 4.6 3.5 3.8 2.8 3.0 2.2 TIMO 7.2 5.8 5.0 4.2 TCY TCYDI TCYL TCYO 0.7 1.8 3.7 4.0 0.6 1.6 3.2 3.2 0.5 1.5 2.9 2.5 0.5 1.3 2.3 2.0 TCKO TGO 5.8 9.2 4.9 7.4 4.0 5.9 3.5 4.7 TICK TMICK TDICK TEICK 2.3 3.8 0.8 1.6 1.8 3.0 0.5 1.2 1.4 2.5 0.4 0.9 1.0 2.1 0.3 0.7 TCKI TCKMI TCKDI TCKEI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCH TCL FTOG 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 TCLRW TCLR TCLRL 6.0 TGCLRW TGCLR 6.0 83 83 6.0 7.7 6.5 6.0 6.3 5.2 6.0 14.7 83 83 6.0 5.1 4.2 4.0 3.2 9.1 6.0 8.0 6.0 12.1 PRELIMINARY ADVANCE Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold-time requirement (TCKDI) of any CLB on the same die. 2. Timing is based upon the XC5215 device. For other devices, see XACTstep Timing Calculator. June 1, 1996 (Version 4.0) 4-209 XC5200 Field Programmable Gate Arrays XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the Global Buffer specifications. The XACTstep delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. Speed Grade Description Global Clock to Output Pad (fast) CLB TBUFG Direct Connect IOB Global Clock-to-Output Delay CLB TBUFG Direct Connect Global Clock-to-Output Delay Input Set-up Time (no delay) to CLB Flip-Flop Direct IOB CLB Connect Input Set-up & Hold Time FD Connect Input Set-up & Hold Time FD Connect Input Set-up & Hold Time FD Connect Input Set-up & Hold Time FD 14.2 13.0 17.3 17.0 1.2 0.8 2.8 2.6 6.0 5.0 0 0 21.4 21.6 21.7 21.7 24.3 18.7 18.9 19.0 19.0 21.2 XC5202 XC5204 XC5206 XC5210 XC5215 2.5 2.3 2.2 2.2 0.5 1.8 1.6 1.5 1.5 0 XC5202 XC5204 XC5206 XC5210 XC5215 3.2 3.4 3.5 3.5 4.4 2.7 2.9 3.0 3.0 3.9 XC5202 XC5204 XC5206 XC5210 XC5215 8.8 8.6 8.5 8.5 6.8 7.7 7.5 7.4 7.4 5.7 XC52xx 0 0 (Max) TPSUF (Min) TPHF (Min) TPSU (Min) TBUFG Input Hold Time (with delay) to CLB Flip-Flop Direct IOB CLB Max (ns) XC5202 XC5204 XC5206 XC5210 XC5215 TBUFG Input Set-up Time (with delay) to CLB Flip-Flop Direct IOB CLB Max (ns) XC5202 XC5204 XC5206 XC5210 XC5215 TBUFG Input Hold Time (no delay) to CLB Flip-Flop Direct IOB CLB Max (ns) 15.1 15.3 15.4 15.4 17.0 TICKOF . . . . FD -3 Max (ns) 16.9 17.1 17.2 17.2 19.0 TICKO IOB -4 Device (Max) Global Clock to Output Pad (slew-limited) -5 Symbol . . . . FD -6 TPH (Min) TBUFG PRELIMINARY ADVANCE Note: 1. These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be used to assure that direct connects are used. 2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. 3. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. 4-210 June 1, 1996 (Version 4.0) XC5200 IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade Description Symbol Input Propagation Delays from CMOS or TTL Levels Pad to I (no delay) TPI Pad to I (with delay) TPID Output Propagation Delays to CMOS or TTL Levels Output (O) to Pad (fast) TOPF Output (O) to Pad (slew-limited) TOPS From clock (CK) to output pad (fast), using direct connect between Q TOKPOF and output (O) From clock (CK) to output pad (slew-limited), using direct connect be- TOKPOS tween Q and output (O) 3-state to Pad active (fast) TTSONF 3-state to Pad active (slew-limited) TTSONS Internal GTS to Pad active (see Note 3) TGTS -6 -5 -4 -3 Max (ns) Max (ns) Max (ns) Max (ns) 5.7 11.4 5.0 10.2 4.8 10.2 4.0 9.4 4.6 9.5 10.1 4.5 8.4 9.3 4.5 8.0 8.3 4.2 7.5 7.1 14.9 13.1 11.8 11.0 5.6 10.4 17.7 5.2 9.0 15.9 4.9 8.3 14.7 4.0 7.8 14.0 PRELIMINARY ADVANCE Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book. 2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors. 3. Timing is based upon the XC5210 device. For other devices, see XACTstep Timing Calculator. June 1, 1996 (Version 4.0) 4-211 XC5200 Field Programmable Gate Arrays XC5200 CLB-to-Pad Diagrams Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R2C1 R2C8 R3C1 R3C8 R4C1 R4C8 R5C1 R5C8 R6C1 R6C8 R7C1 R7C8 Left Right R8C1 R8C2 R8C3 R8C4 R8C5 R8C6 R8C7 R8C8 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 18: XC5202 CLB-to-Pad Relationship 4-212 June 1, 1996 (Version 4.0) Left Bottom R1C1 33 34 13 14 15 Right R8C1 R1C8 R2C1 35 36 37 R8C2 R2C8 16 17 18 R3C1 38 39 40 R8C3 R3C8 19 20 21 R4C1 41 42 43 R8C4 R4C8 22 23 24 R5C1 44 45 46 R8C5 R5C8 25 26 27 R6C1 47 48 49 R8C6 R6C8 28 29 30 R7C1 50 51 R8C7 R7C8 R8C1 52 53 R8C8 R8C8 11 12 31 32 Top R1C1 10 9 R1C2 8 7 R1C3 6 5 4 R1C4 3 2 1 R1C5 84 83 82 61 60 59 R1C6 81 80 79 58 57 56 R1C7 78 77 76 73 72 71 70 69 68 67 66 65 64 63 62 55 54 75 R1C8 74 Note: Pad numbers (1, 2, ..., 84) refer to die pads, not external device pins. See the XC5202 pinout table beginning on page 223. Figure 19: XC5202 CLB-to-Pad Relationship (Detail) June 1, 1996 (Version 4.0) 4-213 XC5200 Field Programmable Gate Arrays Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R2C1 R2C12 R3C1 R3C12 R4C1 R4C12 R5C1 R5C12 R6C1 R6C12 R7C1 R7C12 R8C1 R8C12 R9C1 R9C12 Left Right R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10 R10C11 R10C12 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 20: XC5204 CLB-to-Pad Relationship 4-214 June 1, 1996 (Version 4.0) Left 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Bottom R1C1 47 48 Right Top 16 15 R10C1 R1C12 R2C1 49 50 51 R10C2 R2C12 105 104 103 R1C2 R3C1 52 53 54 R10C3 R3C12 102 101 100 R1C3 R4C1 55 56 57 R10C4 R4C12 99 98 97 R1C4 R5C1 58 59 60 R10C5 R5C12 96 95 94 R1C5 R6C1 61 62 63 R10C6 R6C12 93 92 91 R1C6 R10C7 R7C12 90 89 88 R1C7 124 123 122 R7C1 64 65 107 106 R1C1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R8C1 66 67 68 R10C8 R8C12 87 86 85 R1C8 121 120 119 R9C1 69 70 71 R10C9 R9C12 84 83 82 R1C9 118 117 116 R10C1 72 73 74 R10C10 R10C12 R1C10 115 114 113 75 76 77 R10C11 R1C11 112 111 110 R10C12 R1C12 78 79 81 80 109 108 Note: Pad numbers (1, 2, ..., 124) refer to die pads, not external device pins. See the XC5204 pinout table beginning on page 226. Figure 21: XC5204 CLB-to-Pad Relationship (Detail) June 1, 1996 (Version 4.0) 4-215 XC5200 Field Programmable Gate Arrays Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R2C1 R2C14 R3C1 R3C14 R4C1 R4C14 R5C1 R5C14 R6C1 R6C14 R7C1 R7C14 R8C1 R8C14 R9C1 R9C14 R10C1 R10C14 R11C1 R11C14 R12C1 R12C14 R13C1 R13C14 Left Right R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 22: XC5206 CLB-to-Pad Relationship 4-216 June 1, 1996 (Version 4.0) Left 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Bottom R1C1 R2C1 R3C1 57 58 59 60 61 62 63 Right Top R14C1 R1C14 R14C2 R2C14 127 126 125 R1C2 R14C3 R3C14 124 123 122 R1C3 129 128 R1C1 18 17 16 15 14 13 12 11 10 R4C1 64 65 66 R14C4 R4C14 121 120 119 R1C4 R5C1 67 68 69 R14C5 R5C14 118 117 116 R1C5 9 8 7 R6C1 70 71 72 R14C6 R6C14 R1C6 6 5 4 R7C1 73 74 75 R14C7 R7C14 R1C7 3 2 1 R8C1 76 77 78 R14C8 R8C14 R1C8 148 147 146 R9C1 79 80 81 R14C9 R9C14 109 108 107 R1C9 145 144 143 R10C1 82 83 84 R14C10 R10C14 106 105 104 R1C10 142 141 140 R14C11 R11C14 R14C12 R12C14 101 100 99 R1C12 R14C13 R13C14 98 97 96 R1C13 R14C14 R14C14 R11C1 R12C1 R13C1 R14C1 85 86 87 88 89 90 91 92 93 115 114 113 112 111 110 103 102 R1C11 139 138 137 136 135 134 133 132 131 95 94 R1C14 130 Note: Pad numbers (1, 2, ..., 148) refer to die pads, not external device pins. See the XC5206 pinout table beginning on page 230. Figure 23: XC5206 CLB-to-Pad Relationship (Detail) June 1, 1996 (Version 4.0) 4-217 XC5200 Field Programmable Gate Arrays Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 R1C18 R2C1 R2C18 R3C1 R3C18 R4C1 R4C18 R5C1 R5C18 R6C1 R6C18 R7C1 R7C18 R8C1 R8C18 R9C1 R9C18 R10C1 R10C18 R11C1 R11C18 R12C1 R12C18 R13C1 R13C18 R14C1 R14C18 R15C1 R15C18 R16C1 R16C18 R17C1 R17C18 Left Right R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 24: XC5210 CLB-to-Pad Relationship 4-218 June 1, 1996 (Version 4.0) Left 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Bottom R1C1 R2C1 R3C1 R4C1 R5C1 R6C1 R7C1 45 46 R8C1 47 48 R9C1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R10C1 R11C1 R12C1 75 76 Right R1C18 77 78 79 R18C2 R2C18 80 81 82 169 168 167 R18C3 R3C18 83 84 85 166 165 164 R18C4 R4C18 86 87 88 163 162 161 R18C5 R5C18 160 159 158 R18C6 R6C18 91 92 93 157 156 155 R18C7 R7C18 94 95 96 154 153 152 R18C8 R8C18 97 98 99 R18C9 R9C18 100 101 102 R18C10 R10C18 103 104 105 R18C11 R11C18 106 107 108 145 144 143 R18C12 R12C18 142 141 140 139 138 137 89 90 109 110 R18C13 R13C18 R14C1 111 112 R18C14 R14C18 113 114 115 R18C15 R15C18 64 65 66 R15C1 67 68 69 R16C1 116 117 118 R18C16 R16C18 70 71 72 R17C1 119 120 121 R18C17 R17C18 R18C18 R18C18 73 74 Note: 171 170 R18C1 R13C1 R18C1 Top 122 123 151 150 R1C1 R1C2 R1C3 R1C4 11 10 R1C7 R1C8 R1C10 128 127 126 125 124 16 15 14 R1C6 147 146 131 130 129 19 18 17 13 12 R1C9 134 133 132 22 21 20 R1C5 149 148 136 135 24 23 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 9 8 7 6 5 4 3 2 1 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 R1C18 172 Pad numbers (1, 2, ..., 196) refer to die pads, not external device pins. See the XC5210 pinout table beginning on page 235. Figure 25: XC5210 CLB-to-Pad Relationship (Detail) June 1, 1996 (Version 4.0) 4-219 XC5200 Field Programmable Gate Arrays Top R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C15 R1C16 R1C17 R1C18 R1C19 R1C20 R1C21 R1C22 R2C1 R2C22 R3C1 R3C22 R4C1 R4C22 R5C1 R5C22 R6C1 R6C22 R7C1 R7C22 R8C1 R8C22 Left Right R15C1 R15C22 R16C1 R16C22 R17C1 R17C22 R18C1 R18C22 R19C1 R19C22 R20C1 R20C22 R21C1 R21C22 R22C1 R22C2 R22C3 R22C4 R22C5 R22C6 R22C7 R22C8 R22C15 R22C16 R22C17 R22C18 R22C19 R22C20 R22C21 R22C22 Bottom KEY: I/O Pad R#C# CLB, identified by R#C# = row and column numbers Figure 26: XC5215 CLB-to-Pad Relationship 4-220 June 1, 1996 (Version 4.0) Left 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 R1C1 R2C1 R3C1 R4C1 R5C1 R6C1 R7C1 R8C1 R9C1 R10C1 R11C1 Bottom 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 R12C1 93 94 R22C1 124 125 R22C12 R13C1 95 96 97 R22C2 126 127 128 R22C13 R14C1 98 99 100 R22C3 129 130 131 R22C14 R15C1 101 102 103 R22C4 132 133 134 R22C15 R16C1 104 105 106 R22C5 135 136 137 R22C16 R17C1 107 108 109 R22C6 138 139 140 R22C17 R18C1 110 111 112 R22C7 141 142 143 R22C18 R19C1 113 114 115 R22C8 144 145 146 R22C19 R20C1 116 117 118 R22C9 R21C1 119 120 121 R22C10 R22C1 122 123 R22C11 147 148 149 150 151 152 153 R22C20 R22C21 R22C22 Note: Pad numbers (31, 32, ..., 153) refer to die pads, not external device pins. See the XC5215 pinout table beginning on page 241. Figure 27: XC5215 CLB-to-Pad Relationship (Left/Bottom Detail) June 1, 1996 (Version 4.0) 4-221 XC5200 Field Programmable Gate Arrays Right R1C22 R2C22 213 212 211 210 209 R3C22 Top R12C22 183 182 R1C1 R13C22 181 180 179 R1C2 R14C22 178 177 176 R1C3 208 207 30 29 28 27 26 25 24 23 22 21 R1C12 R1C13 R1C14 244 243 242 241 240 239 238 237 236 235 234 R4C22 206 205 204 R15C22 175 174 173 R1C4 R5C22 203 202 201 R16C22 172 171 170 R1C5 20 19 18 R1C16 233 232 231 R6C22 200 199 198 R17C22 169 168 167 R1C6 17 16 15 R1C17 230 229 228 R7C22 197 196 195 R18C22 166 165 164 R1C7 14 13 12 R1C18 227 226 225 R8C22 194 193 192 R19C22 163 162 161 R1C8 11 10 9 R1C19 224 223 222 R9C22 191 190 189 R20C22 R1C9 8 7 6 R1C20 221 220 219 188 187 186 R21C22 R1C10 5 4 3 R1C21 218 217 216 R10C22 R11C22 160 159 158 157 156 R22C22 185 184 155 154 R1C11 2 1 R1C15 215 R1C22 214 Note: Pad numbers (1, 2, ..., 244) refer to die pads, not external device pins. See the XC5215 pinout table beginning on page 241. Figure 28: XC5215 CLB-to-Pad Relationship (Right/Top Detail) 4-222 June 1, 1996 (Version 4.0) Device-Specific Pinout Tables Pin Locations for XC5202 Devices Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. Description PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) GND I/O (A12) I/O (A13) I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O (TDI) I/O (TCK) GND I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 128 129 130 131 132 133 134 135* 136* 137 138 139 140* 141* 142 143 144 1 2 3 4* 5* 6 7 8 9* 10* 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25* 26* 27 28 29 30* 31* 32 H3 H1 G1 G2 G3 F1 F2 F3 E3 C1 B1 B2 C3 C4 B3 A1 B4 A3 C6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 C11 B12 A13 B13 51 54 57 63 66 69 78 81 90 93 102 105 111 114 117 123 126 129 135 138 141 147 150 153 159 162 165 171 174 June 1, 1996 (Version 4.0) 4-223 XC5200 Field Programmable Gate Arrays Pin Locations for XC5202 Devices Pin 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 4-224 Description I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O (D6) I/O GND - PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 - 33 34 35 36 37 38 39 40 41* 42* 43 44 45 46* 47* 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62* 63* 64 65 66 67* 68* 69 70 71 72 73 74 75 76 77* 78* 79 80 81 82* B14 A15 C13 A16 C14 B15 B16 D14 E14 C16 F14 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 L14 P16 M14 N14 R16 P14 R15 P13 R14 T16 T15 T14 T13 P11 - 177 186 189 192 195 204 207 210 216 219 222 228 231 234 240 243 246 252 255 258 264 267 276 279 288 291 300 303 - June 1, 1996 (Version 4.0) Pin Locations for XC5202 Devices Pin 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. Description PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O GND I/O (D1) I/O (RCLK-BUSY/ RDY) I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O (A2, CS1) I/O (A3) GND I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 59 60 61 62 63 64 65 66 67 68 69 70 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 83* 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98* 99* 100 101 102 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 P6 T3 P5 306 312 315 318 324 327 336 339 342 348 351 360 363 366 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 103* 104* 105 106 107 108 109 110 111 112 113* 114* 115 116 117* 118 119* 120* 121 122 123 124 125 126 127 P4 T2 R2 P3 T1 N3 R1 P2 P1 N1 L3 K3 K2 K1 J1 J2 J3 H2 372 375 0 9 15 18 21 27 30 33 39 42 45 - Notes: * Indicates unconnected package pins. leading numbers refer to bonded pad, shown in Figure 18 or Figure 19. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD June 1, 1996 (Version 4.0) 4-225 XC5200 Field Programmable Gate Arrays Pin Locations for XC5204 Devices Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 4-226 Description VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND - PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 - 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 - 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 - H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 - 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8* 9* 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30* 31* 78 81 87 90 93 99 102 105 111 114 117 123 126 129 138 141 150 153 159 162 165 171 174 177 180 183 186 189 195 198 201 207 210 213 219 222 225 231 - June 1, 1996 (Version 4.0) Pin Locations for XC5204 Devices Pin 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. Description I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG June 1, 1996 (Version 4.0) PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 234 237 240 243 246 249 258 261 264 267 276 279 282 288 291 294 300 303 306 312 315 318 324 327 330 336 339 348 351 354 360 363 366 372 375 378 384 387 390 396 399 - 4-227 XC5200 Field Programmable Gate Arrays Pin Locations for XC5204 Devices Pin 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 4-228 Description PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 - 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 - 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 - 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 R6 T4 P6 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 L1 83 84 85 86 87 88 89* 90* 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111* 112* 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 408 411 420 423 426 432 435 438 444 447 450 456 459 462 468 471 474 480 483 486 492 495 498 504 507 510 516 519 0 9 15 18 21 27 30 33 39 42 45 June 1, 1996 (Version 4.0) Pin Locations for XC5204 Devices Pin 119. 120. 121. 122. 123. 124. Description I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order 81 82 83 84 1 85 86 87 88 89 90 91 82 83 84 85 86 87 88 121 122 123 124 125 126 127 K3 K2 K1 J1 J2 J3 H2 134 135 136* 137 138 139 140 141 51 54 57 63 66 69 - Notes: * Indicates unconnected package pins. leading numbers refer to bonded pad, shown in Figure 20 or Figure 21. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD June 1, 1996 (Version 4.0) 4-229 XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 4-230 Description PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O GND I/O I/O I/O (TMS) I/O I/O I/O I/O I/O I/O I/O 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 155 156 157 158 159 160 161 162 163 164 165 166 167* 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 C1 E2 F3 D2 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 183 184 185 186 187 188 189 190 191 192 193 194 195* 196* 197 198 199 200 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 8 9 10 11 12* 13* 14 15 16 17 18 19 20 21 22 23 24 87 90 93 99 102 105 111 114 117 123 126 129 138 141 150 153 162 165 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 246 249 June 1, 1996 (Version 4.0) Pin Locations for XC5206 Devices Pin 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. Description GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O June 1, 1996 (Version 4.0) PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 - 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 D9 D10 C10 B10 A9 A10 A11 C11 B11 A12 B12 A13 C12 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 G16 E18 F18 G17 G18 H16 H17 H18 J18 25 26 27 28 29 30 31 32 33 34 35 36 37 38* 39* 40 41 42 43 44 45 46 47 48 49 50 51* 52* 53* 54* 55 56 57 58 59 60 61 62 63 64 65* 66* 67 68 69 70 71 72 73 74 75 255 258 261 267 270 273 279 282 285 291 294 297 303 306 309 315 318 321 330 333 336 339 348 351 354 360 363 372 375 378 384 387 390 396 399 402 408 4-231 XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin Description 74. 75. I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 4-232 PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 V17 V16 T13 U14 T12 U13 V13 U12 V12 T11 U11 V11 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91* 92* 93 94 95 96 97 98 99 100 101 102* 103 104* 105* 106 107* 108 109 110 111 112 113 114 115 116 117* 118* 119 120 121 122 123 124 125 126 411 414 420 423 426 432 435 438 444 447 450 456 459 468 471 480 483 486 492 495 504 507 516 519 522 528 531 534 540 543 552 555 558 564 567 June 1, 1996 (Version 4.0) Pin Locations for XC5206 Devices Pin 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. Description I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLKBUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O June 1, 1996 (Version 4.0) PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 61 62 63 64 65 66 67 68 69 70 63 64 65 66 67 68 69 70 71 72 73 74 60 61 62 63 64 65 66 67 68 69 70 71 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7 U5 T6 V3 V2 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143* 144* 145 146 147 148 570 576 579 588 591 600 603 612 615 618 624 627 630 636 639 642 648 71 72 73 74 75 76 77 78 79 80 81 82 - 75 76 77 78 79 80 81 82 83 84 85 86 - 72 73 74 75 76 77 78 79 80 81 82 83 - 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 - 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 - 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 M3 P1 N1 M2 M1 L3 149 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 164 165 166 167 168 169* 170* 171 172 173 174 175 176 651 654 660 663 9 15 18 21 27 30 33 42 45 51 54 57 63 4-233 XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin 144. 145. 146. 147. 148. Description I/O I/O I/O I/O (A6) I/O (A7) GND PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order 83 84 1 87 88 89 90 91 84 85 86 87 88 123 124 125 126 127 136 137 138 139 140 141 149 150 151 152 153 154 L2 L1 K1 K2 K3 K4 177 178 179 180 181 182 66 69 75 78 81 - Notes: * Indicates unconnected package pins. leading numbers refer to bonded pad, shown in Figure 22 or Figure 23. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD 4-234 June 1, 1996 (Version 4.0) Pin Locations for XC5210 Devices Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. Description VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) I/O I/O I/O I/O I/O I/O GND I/O June 1, 1996 (Version 4.0) PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 1 2 3 4 5 6 7 8 9 10 11 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 8 9 10 11 12 13 14 15 J4 J3 J2 J1 H1 H2 H3 G1 G2 H4 G4 F1 E1 G3 F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 D3 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 C7 A4 D8 E8 B7 A7 C7 D7 E7 A6 B6 VCC** C6 F7 A5 B5 GND** D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC** GND** D4 B1 C2 E5 D3 C1 D2 G6 E4 D1 E3 E2 GND** F5 212 213 214 215 216 217 218 219* 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 111 114 117 123 126 129 135 138 141 150 153 162 165 171 174 177 183 186 189 195 198 201 210 213 222 225 231 234 237 243 246 249 255 258 261 267 270 4-235 XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 4-236 Description I/O I/O (TMS) I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51* 52* 53* 54* 55 A5 B7 A6 D7 D8 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 D11 D12 B11 A12 B12 A13 C12 D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 E1 F4 F3 VCC** F2 F1 G4 G3 G2 G1 G5 H3 GND** VCC** H4 H5 J2 J1 J3 J4 J5 K1 VCC** K2 K3 J6 L1 GND** L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND** P2 VCC** 16 17 18 19 20 21 22* 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37* 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 273 279 282 285 291 294 297 306 309 318 321 327 330 333 339 342 345 351 354 357 363 366 369 375 378 381 387 390 393 399 402 405 411 414 417 426 429 - June 1, 1996 (Version 4.0) Pin Locations for XC5210 Devices Pin 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. Description M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O June 1, 1996 (Version 4.0) PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 34 35 36 37 38 39 40 41 42 43 44 45 46 47 - 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 - 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 G16 E18 F18 G17 G18 H16 H17 G15 H15 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 L15 M15 M18 M17 N18 P18 M16 N15 P15 N17 R18 T18 M4 R2 P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND** R5 M6 N6 P6 VCC** R6 M7 N7 P7 R7 L7 N8 P8 VCC** GND** L8 P9 R9 N9 M9 L9 R10 P10 VCC** N10 K9 R11 P11 GND** M10 N11 R12 L10 P12 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83* 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 432 435 444 447 450 456 459 462 468 471 474 480 483 486 492 495 504 507 510 516 519 522 528 531 534 540 543 546 552 555 558 564 567 570 576 579 588 591 600 603 606 612 4-237 XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 4-238 Description I/O I/O I/O I/O I/O I/O I/O GND DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 - 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 - 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 94 95 96 97 98 99 100 101 102* 103 104* 105* 106 107* 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 T12 R12 R11 U13 V13 U12 V12 T11 U11 V11 V10 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 M11 R13 N12 P13 K10 R14 N13 GND** P14 VCC** M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND** L15 K12 K13 K14 VCC** K15 J12 J13 J14 J15 J11 H13 H14 VCC** GND** H12 H11 G14 G15 G13 G12 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143* 144 145 146 147 148 149 150 151 152 153 154 155 156 157 615 618 624 627 630 636 639 648 651 660 663 666 672 675 678 684 687 690 696 699 708 711 714 720 723 726 732 735 738 744 747 756 759 768 771 780 783 June 1, 1996 (Version 4.0) Pin Locations for XC5210 Devices Pin 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. Description I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (A4) I/O (A5) June 1, 1996 (Version 4.0) PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 V7 U7 V6 U6 R8 R7 T7 R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P4 N4 P2 T1 R1 N2 M3 P1 N1 M4 L4 M2 M1 G11 F15 VCC** F14 F13 G10 E15 GND** E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC** A15 GND** A14 B13 E11 C12 A13 B12 F9 D11 A12 C11 B11 E10 GND** A11 D10 C10 B10 VCC** A10 D9 158* 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195* 196 197 198 199 200 201 202 203 786 792 795 798 804 807 810 816 819 822 828 831 834 840 843 846 855 858 9 15 18 21 27 30 33 39 42 45 51 54 57 66 69 75 78 81 4-239 XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin 191. 192. 193. 194. 195. 196. Description I/O I/O I/O I/O I/O (A6) I/O (A7) GND PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan Order 83 84 1 123 124 125 126 127 136 137 138 139 140 141 148 149 150 151 152 153 154 176 177 178 179 180 181 182 L3 L2 L1 K1 K2 K3 K4 C9 B9 A9 E9 C8 B8 GND** 204* 205 206 207 208 209 210 211 87 90 93 99 102 105 - Notes: * Indicates unconnected package pins. leading numbers refer to bonded pad, shown in Figure 24 or Figure 25. ** Pins labeled VCC** are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, D8, H15, R8, B14, E1, and R15. Pins labeled GND** are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD 4-240 June 1, 1996 (Version 4.0) Pin Locations for XC5215 Devices Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. Description VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O I/O I/O (A14) I/O (A15) VCC GND GCK1 (A16, I/O) I/O (A17) I/O I/O I/O (TDI) June 1, 1996 (Version 4.0) PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206* 207* 208* 1* 2 3* 4 5 6 7 8 212 213 214 215 216 217 218 219* 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 1 2 3 4 5 6 K1 K2 K3 K5 K4 J1 J2 H1 J3 H2 G1 E1 H3 G2 H4 F2 F1 H5 G3 D1 G4 E2 F3 G5 C1 F4 E3 D2 C2 F5 E4 D3 C3 A2 B1 D4 B2 B3 E6 D5 38 37 36 35 34 33 32 31 30 29* 28* 27 26 25 24* 23 22 21 20 19 18 17 16 15 14 13 12 11* 10 9 8 7 6 5 4 3 2 1 304 303 302 301 300 299 VCC** E8 B7 A7 C7 D7 E7 A6 B6 VCC** C6 F7 A5 B5 GND** D6 C5 A4 E6 B4 D5 A3 C4 B3 F6 A2 C3 VCC** GND** D4 B1 C2 E5 D3 VCC** D14 C14 A15 B15 C15 D15 A16 B16 C17 B18 VCC** C18 D17 A20 B19 GND** C19 D18 A21 B20 C20 B21 B22 C21 D20 A23 D21 C22 B24 C23 D22 C24 VCC** GND** D23 C25 D24 E23 C26 138 141 147 150 153 159 162 165 171 174 177 183 186 189 195 198 201 207 210 213 219 222 225 234 237 243 246 249 258 261 270 273 279 282 285 4-241 XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices Pin 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 4-242 Description I/O (TCK) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22* 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37* 38 39 40 41 42 43 C4 A3 D6 E7 B4 C5 A4 D7 C6 E8 B5 A5 B6 D8 C7 B7 A6 C8 E9 B8 A8 C9 B9 E10 A9 D10 C10 A10 A11 B10 B11 C11 E11 D11 A12 B12 A13 E12 B13 A16 A14 C13 B14 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281* 280 279 278* 277* 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258* 257* 256 255 254* 253 252 251 250 C1 D2 G6 E4 D1 E3 E2 GND** F5 E1 F4 F3 VCC** F2 F1 G4 G3 G2 G1 G5 H3 GND** VCC** H4 H5 J2 J1 J3 J4 J5 K1 VCC** K2 K3 J6 E24 F24 E25 D26 G24 F25 F26 H23 H24 G25 G26 GND** J23 J24 H25 K23 VCC** L24 K25 L25 L26 M23 M24 M25 M26 N24 N25 GND** VCC** N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 VCC** U24 V25 V24 294 297 303 306 309 315 318 321 327 330 333 339 342 345 351 354 357 363 366 369 375 378 381 390 393 399 402 405 411 414 417 423 426 429 435 438 441 447 June 1, 1996 (Version 4.0) Pin Locations for XC5215 Devices Pin 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. Description I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1 (I/O) GND M0 (I/O) VCC M2 (I/O) GCK2 (I/O) I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O June 1, 1996 (Version 4.0) PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 - 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51* 52* 53* 54* 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 D13 A15 B15 E13 C14 A17 D14 B16 C15 E14 A18 D15 C16 B17 B18 E15 D16 C17 A20 A19 C18 B20 D17 B19 C19 F16 E17 D18 C20 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 F20 J16 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205* 204 203 L1 GND** L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1 N3 GND** P2 VCC** M4 R2 P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND** R5 M6 N6 P6 VCC** R6 U23 GND** Y26 W25 W24 V23 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 AA23 AB24 AD25 AC24 AB23 GND** AD24 VCC** AC23 AE24 AD23 AC22 AF24 AD22 AE23 AE22 AF23 AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND** AD18 AE19 AC17 AD17 VCC** AE17 450 453 459 462 465 471 474 477 483 486 489 495 498 501 507 510 513 522 525 528 531 540 543 546 552 555 558 564 567 570 576 579 582 588 591 594 600 603 606 612 615 4-243 XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices Pin 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 4-244 Description I/O I/O I/O I/O I/O I/O I/O I/O I/O (ERR, INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 82 83* 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 G20 H20 J18 J19 K16 J20 K17 K18 K19 L20 K20 L19 L18 L16 L17 M20 M19 N20 M18 N19 P20 T20 N18 P19 N17 R19 R20 N16 P18 U20 P17 T19 R18 P16 V20 R17 T18 U19 V19 R16 T17 U18 X20 W20 202 201* 200* 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181* 180* 179 178 177 176* 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 M7 N7 P7 R7 L7 N8 P8 VCC** GND** L8 P9 R9 N9 M9 L9 R10 P10 VCC** N10 K9 R11 P11 GND** M10 N11 R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 GND** AE16 AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC** GND** AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AD11 VCC** AE9 AD9 AC10 AF7 GND** AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 AD6 AC7 AF4 AF3 AD5 AE3 AD4 AC5 GND** 618 624 627 630 636 639 642 648 651 660 663 672 675 678 684 687 690 696 699 702 708 711 714 720 723 726 732 735 738 744 747 750 756 759 768 771 774 780 783 - June 1, 1996 (Version 4.0) Pin Locations for XC5215 Devices Pin 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. Description DONE VCC PROG I/O (D7) GCK3 (I/O) I/O I/O I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O June 1, 1996 (Version 4.0) PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 - 102* 103 104* 105* 106 107* 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143* 144 145 146 147 148 149 150 151 152 153 154 155 156 157 V18 X19 U17 W19 W18 T15 U16 V17 X18 U15 T14 W17 V16 X17 U14 V15 T13 W16 W15 X16 U13 V14 W14 V13 X15 T12 X14 X13 V12 W12 T11 X12 U11 V11 W11 X10 X11 W10 V10 T10 U10 X9 W9 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128* 127 126 125* 124* 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 P14 VCC** M12 P15 N14 L11 M13 N15 M14 J10 L12 M15 L13 L14 K11 GND** L15 K12 K13 K14 VCC** K15 J12 J13 J14 J15 J11 H13 H14 VCC** GND** H12 H11 G14 G15 G13 G12 AD3 VCC** AC4 AD2 AC3 AB4 AD1 AA4 AA3 AB2 AC1 Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND** V3 W2 U4 U3 VCC** V2 V1 T1 R4 R3 R2 R1 P3 P2 P1 VCC** GND** N2 N4 N3 M1 M2 M3 792 795 804 807 810 816 819 828 831 834 840 843 846 852 855 858 864 867 870 876 879 882 888 891 894 900 903 906 912 915 924 927 936 939 942 948 4-245 XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices Pin Description PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 190. 191. I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK-BUSY/RDY) I/O I/O I/O I/O I/O (D0, DIN) I/O (DOUT) CCLK VCC I/O (TDO) GND I/O (A0, WS) GCK4 (A1, I/O) I/O I/O I/O (A2, CS1) I/O (A3) I/O I/O I/O I/O I/O I/O I/O 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 - 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155* 156* 157* 158* 159 160 161 162 163 164 165 166 167 168 169 158* 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 X8 V9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 W4 W3 T6 U5 V4 X1 V3 W1 U4 X2 W2 V2 R5 T4 U3 V1 R4 P5 U2 T3 U1 P4 R3 107 106 105* 104* 103 102 101 100* 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 G11 F15 VCC** F14 F13 G10 E15 GND** E14 F12 E13 D15 F11 D14 E12 C15 D13 C14 F10 B15 C13 VCC** A15 GND** A14 B13 E11 C12 A13 B12 F9 D11 A12 C11 B11 M4 L1 J1 K3 VCC** J2 J3 K4 G1 GND** H2 H3 J4 F1 G2 G3 F2 E2 F3 G4 D2 F4 E3 C2 D3 E4 C3 VCC** D4 GND** B3 C4 D5 A3 D6 C6 B5 A4 C7 B6 A6 D8 B7 951 954 960 963 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. 208. 209. 210. 211. 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. 224. 225. 226. 227. 4-246 966 972 975 978 984 987 990 996 999 1002 1008 1011 1014 1020 1023 1032 1035 1038 1044 1047 0 9 15 18 21 27 30 33 39 42 45 51 54 57 June 1, 1996 (Version 4.0) Pin Locations for XC5215 Devices Pin 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. 239. 240. 241. 242. 243. 244. Description I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O (A4) I/O (A5) I/O I/O I/O I/O I/O (A6) I/O (A7) GND PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order 131 132 133 134 135 136 137 138 139 140 141 170 171 172 173 174 175 176 177 178 179 180 181 182 194 195 196 197 198 199 200 201 202 203 204* 205 206 207 208 209 210 211 N5 T2 R2 T1 N4 P3 P2 N3 R1 M5 P1 N1 M3 M2 L5 M1 L4 L3 L2 L1 61 60 59 58 57 56 55 54 53* 52 51 50 49* 48* 47 46 45 44 43 42 41 40 39 E10 GND** A11 D10 C10 B10 VCC** A10 D9 C9 B9 A9 E9 C8 B8 GND** A7 D9 C9 GND** B8 D10 C10 B9 VCC** B11 A11 D12 C12 B12 A12 C13 B13 A13 B14 GND** 63 66 69 75 78 81 87 90 93 99 102 105 111 114 117 126 129 - Notes: * Indicates unconnected package pins. leading numbers refer to bonded pad, shown in Figure 26, Figure 27 or Figure 28. ** Pins labeled VCC** are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the BG225 are: B2, D8, H15, R8, B14, E1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17. Pins labeled GND** are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the BG225 are: A1, D12, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are: A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD June 1, 1996 (Version 4.0) 4-247 XC5200 Field Programmable Gate Arrays Product Availability PINS 84 100 100 144 156 160 176 191 208 208 223 225 240 240 299 304 352 TYPE Plast. PLCC Plast. PQFP Plast. VQFP Plast. TQFP Ceram. PGA Plast. PQFP Plast. TQFP Ceram. PGA HighPerf. QFP Plast. PQFP Ceram. PGA Plast. BGA HighPerf. QFP Plast. PQFP Ceram. PGA HighPerf. QFP Plast. BGA PC84 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 HQ304 BG352 CI CI CI CI CI CI CODE XC5202 XC5204 XC5206 XC5210 XC5215 -6 -5 CI CI CI CI CI -4 (CI) (CI) (CI) (CI) (CI) -3 (CI) (CI) (CI) (CI) (CI) -6 CI CI CI CI CI -5 CI CI CI CI CI CI -4 (CI) (CI) (CI) (CI) (CI) (CI) -3 (CI) (CI) (CI) (CI) (CI) (CI) -6 CI CI CI CI CI CI CI -5 CI CI CI CI CI CI CI CI -4 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI) -3 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI) -6 CI CI CI CI CI CI CI -5 CI CI CI CI CI CI CI CI -4 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI) -3 (CI) (CI) (CI) (CI) (CI) (CI) (CI) CI CI CI (CI) -6 CI CI CI CI CI CI -5 CI CI CI CI CI CI CI -4 (CI) (C) (CI) (CI) (CI) (CI) (CI) (CI) (C) (CI) (CI) (CI) (CI) (CI) -3 Notes: Parentheses indicate future product plans C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C User I/O Per Package Package Type Max I/O PC84 PQ100 VQ100 XC5202 84 65 81 81 84 84 XC5204 124 65 81 81 117 124 XC5206 148 65 81 81 117 XC5210 196 65 117 XC5215 244 Device TQ144 PG156 PQ160 TQ176 PG191 133 148 148 133 149 HQ208 PQ208 PG223 BG225 196 196 HQ240 PQ240 PG299 HQ304 BG352 244 244 244 124 133 148 164 164 196 196 197 Ordering Information Example: Device Type Speed Grade 4-248 XC5210-6PQ208C Temperature Range Number of Pins Package Type June 1, 1996 (Version 4.0) s XC5200L Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Advance Product Specification Features * * * * * * * * * * * High-density family of Field-Programmable Gate Arrays (FPGAs) JEDEC-compliant 3.3 V version of XC5200 FPGA family Design- and process-optimized for low cost - 0.5-m three-layer metal (TLM) process SRAM-based, in-system reprogrammable architecture Flexible architecture with abundant routing resources - VersaBlockTM logic module - VersaRingTM I/O interface - Dedicated cell-feedthrough path - Hierarchical interconnect structure - Extensive registers/latches - Dedicated carry logic for arithmetic functions - Cascade chain for wide input functions - Dedicated IEEE 1149.1 boundary-scan logic - Internal 3-state bussing capability - Four global low-skew clock or signal distribution nets - Output slew-rate control - 4-mA sink current per output Configured by loading binary file - Unlimited reprogrammability - Seven programming modes, including high-speed ExpressTM mode 100% factory tested 100% architecture, pin-out and bit-stream compatible with XC5200 families 100% footprint compatibility for common packages 5 V tolerant inputs Fully supported by XACTstepTM Development System - Includes complete support for XACT-PerformanceTM, X-BLOXTM, Unified Libraries, Relationally Placed Macros (RPMs), XDelay, and XCheckerTM - Wide selection of PC and workstation platforms - Interfaces to more than 100 third-party CAE tools Description The XC5200L Field-Programmable Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200L architecture for three-layer metal technology and 0.5-m CMOS SRAM process, dramatic advances have been made in silicon efficiency. These advances position the XC5200L family as a costeffective, high-volume alternative to gate arrays. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200L family brings a robust feature set to high-density programmable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-tomarket. Complete support for the XC5200L family is delivered through the familiar XACTstep software environment. The XC5200L family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and synthesis. Designers utilizing logic synthesis can use their existing Synopsys, Viewlogic, Mentor, and Exemplar tools to design with the XC5200L devices. Table 1: Initial XC5200L Field-Programmable Gate Array Family Members Device XC5202L XC5206L XC5215L 3,000 10,000 23,000 2,000 - 3,000 6,000 - 10,000 15,000 - 23,000 VersaBlock Array 8x8 14 x 14 22 x 22 Number of CLBs 64 196 484 Number of Flip-Flops 256 784 1,936 Number of I/Os 84 148 244 TBUFs per Horizontal Longline 10 16 24 Max Logic Gates Typical Gate Range June 1, 1996 (Version 1.0) 4- 249 XC5200L Field Programmable Gate Arrays XC5200L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC5200L Operating Conditions Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial: TJ=0C to 85C junction High-level input voltage--CMOS configuration Low-level input voltage--CMOS configuration Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 5.0 0.8 250 Units V V V ns Min 2.4 Max Units V V mA A pF mA XC5200L DC Characteristics Over Operating Conditions Symbol VOH VOL ICCO IIL CIN IRIN Description High-level output voltage @ IOH = -4 mA, VCC min Low-level output voltage @ IOL = 4 mA, VCC max (Note 1) Quiescent FPGA supply current (Note 2) Leakage current Input capacitance (sample tested) Pad pull-up (when selected) @ VIN = 0V (sample tested) -10 0.02 0.4 N/A +10 15 0.25 Notes: 1. With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. 2. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a MakeBits tie option. XC5200L Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: 4- 250 Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature in plastic packages Junction temperature in ceramic packages -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. June 1, 1996 (Version 1.0) XC6200 Series Table of Contents XC6200 Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical and Physical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cells, Blocks and Tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magic Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Design with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Map Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wildcard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Power-on/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Serial Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Cell Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . XC6200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Internal Routing Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6200 Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - West Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - South Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - East Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC6216 Pinouts - North Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253 4-254 4-254 4-254 4-254 4-256 4-257 4-257 4-257 4-258 4-259 4-261 4-261 4-261 4-263 4-265 4-265 4-265 4-267 4-267 4-268 4-268 4-268 4-268 4-270 4-271 4-272 4-273 4-274 4-275 4-275 4-275 4-275 4-276 4-276 4-276 4-276 4-277 4-277 4-278 4-278 4-282 4-282 4-283 4-284 4-285 4-286 4-251 XC6200 Series Table of Contents 4-252 XC6200 Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Advance Product Specification Features * * * * * * Advanced Processor-Compatible Architecture - FastMAPTM interface allows direct processor read/ write access to all internal registers in user design with no logic overhead - All user registers and SRAM control store memory mapped onto processor address space - Programmable data bus width (8, 16, 32-bits) - Easily interfaced to most microcontrollers and microprocessors High-Performance Sea-of-Gates FPGA - Up to 16K configurable cells - Abundant registers, gates and routing resources - Extremely high gate count for structured logic or datapath designs High Capacity Distributed RAM - High speed SRAM control store - 2 bytes of synchronous RAM per cell High Speed Flexible Interconnect Architecture - Low delay hierarchical routing scheme gives large number of fast `longlines' (Fastlanes) - Any cell can be connected to any other - Suited to both structured synchronous cell data path type designs or irregular random logic - Completely flexible clocks and clears for registers - 4 Global low-skew signals >110MHz flip-flop toggle rates * * * * Extremely Flexible Cell Architecture - Over 50 distinct logic functions per cell - One register and gate/multiplexer possible for every cell Advanced Dynamic Reconfiguration Capability - High speed reconfiguration via parallel CPU interface - Unlimited reprogrammability - Full or partial reconfiguration/context switching possible - Ideal for custom computing applications Flexible Pin Configuration - All User I/O's programmable as in, out, bidirect, tristate or open drain. - Configurable pull-up/down resistors - CMOS or TTL logic levels - 8, 16, 32-bit CPU interface Testability - Pre-tested volume part - JTAG capability with library macrocells XACTstep Series 6000 Development System - Implement designs using familiar tools like Viewlogic and Synopsys - Use PC or Unix workstation platforms - Fully automatic mapping, placement and routing - Interactive Physical Editor for design optimization - Large Xilinx parts library for schematic capture - VHDL synthesis Table 1: The XC6200 Family of Field-Programmable Gate Arrays Device Max Logic Gates Typical Gate Range Number of Cells Max. No. Registers Number IOB's Cell Rows x Columns Max. RAM (bits) XC6209 1 13,000 9,000 - 13,000 2304 2304 192 48x48 36K XC6216 24,000 16,000 - 24,000 4096 4096 256 64x64 65K XC6236 1 55,000 36,000 - 55,000 9216 9216 384 96x96 147K XC6264 1 100,000 64,000 - 100,000 16384 16384 512 128x128 262K Notes: 1. Planned Product June 1, 1996 (Version 1.0) 4- 253 XC6200 Field Programmable Gate Arrays Description The XC6200 family is a new type of high performance Field Programmable Gate Array (FPGA) from Xilinx. The XC6200 series is a family of fine-grain, sea-of-gates FPGAs. These devices are designed to operate in close cooperation with a microprocessor or microcontroller to provide an implementation of functions normally placed on an ASIC. These include interfaces to external hardware and peripherals, glue logic and custom coprocessors, including bit level and systolic operations unsuited for standard processors. XC6200 FPGAs can provide extremely high gate counts for data path or regular array type designs. In these cases the actual gate count may be considerably higher than those given in Table 1. An XC6200 part is composed of a large array of simple, configurable cells. Each basic cell contains a computation unit capable of simultaneously implementing one of a set of logic level functions and a routing area through which intercell communication can take place. The structure is simple, symmetrical, hierarchical and regular, allowing novice users to quickly make efficient use of the resources available. The nearest-neighbor interconnect of the cells is supplemented with wires of length 4, 16 and chip-length (CL) cells, called FastLane-4, 16 and CL respectively, which provide low-delay paths for longer connections. In addition there are four global input signals which provide a low-skew distribution path for critical high-fan-out nets such as clocks and initialization signals. An XC6200 part is configured by the content of an integral, highly stable six-transistor SRAM control store. This allows XC6200 parts to be quickly reconfigured an unlimited number of times. The SRAM control store can be mapped into the address space of a host processor and additional support logic is provided to allow rapid reconfiguration of all or part of the device. In addition, the outputs of function units within the device can be read by a processor through the RAM interface. A host processor can read or write registers within logic implemented on the device. Data transfers can be 8, 16 or 32 bits wide, even when register bits are distributed over a column of cells. These capabilities allow XC6200 FPGAs to support virtualised hardware in which circuits running on the FPGA can be saved (swapped out') to allow the FPGA resources to be assigned to a different task, then restored (swapped in') at a later time with the correct internal state in their registers. Sections of the device can be reconfigured without disturbing circuits running in other sections. Thus an XC6200 FPGA in a coprocessor application can be time-shared by several processes running on the host computer. 4- 254 Design entry and verification are carried out with Xilinx XACTstep Series 6000 software using industry-standard schematic capture, synthesis and simulation packages such as Viewlogic, Synopsys and Mentor Graphics. A comprehensive library of parts, ranging from simple gate primitives to complex macro-functions, exists to make this an easy task. Below the top level design tools, the XC6200 product family is supported by a number of CAD tools ranging from simple symbolic editors to sophisticated cell-compilation tools. These tools will ensure that the captured design is laid out efficiently with no user intervention. Node delays can then be back-annotated to the top level logic simulator. The tools also allow for manual intervention in the layout process, if desired. Incremental design is also supported: if a design is laid out and subsequently changed, only the modified block has to be re-laid out. The functions available within each cell provide a good target for logic synthesis programs. The simple cell architecture allows arbitrary user logic designs to be mapped onto a number of cells, rather than having to split the design up into medium-complexity mini-functions for mapping to a larger configurable logic block. Because each cell can be configured as a register, designs containing far more registers than would be possible with a larger configurable block are achievable. Detailed Functional Description Logical and Physical Organization The XC6200 architecture may be viewed as a hierarchy. At the lowest level lies a large array of basic cells (Figure 1). This is the `sea-of-gates'. Each cell is individually programmable to implement a D-type register and a 2-input logic function such as a multiplexer or gate. Any cell may also be configured to implement a purely combinatorial function, with no register. This is illustrated in Figure 7. Cells, Blocks and Tiles First generation fine-grain architectures implemented only nearest-neighbor interconnection and had no hierarchical routing (Figure 1). The XC6200 architecture is a second generation fine-grain architecture, employing a hierarchical cellular array structure. Neighbor-connected cells are grouped into Blocks of 4x4 cells (Figure 2) that themselves form a cellular array, communicating with neighboring 4x4 cell Blocks. A 4x4 array of these 4x4 Blocks forms a 16x16 cell Tile (Figure 3). In the XC6216 part, a 4x4 array of these 16x16 Tiles forms the central 64x64 cell array which is then surrounded by I/O pads (Figure 4). June 1, 1996 (Version 1.0) Length 4 Fastlanes Cell Cell Cell E4 Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell S4 Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell W4 N4 Figure 1: Nearest-Neighbor Interconnect Array Structure Figure 2: XC6200 4x4 Cell Block Each Arrow = Sixteen Chip-Length Fastlanes Four Length 16 Fastlanes S16 (Remainder hidden for clarity) (Only 1 shown for clarity) E16 4x4 4x4 4x4 4x4 4x4 4x4 4x4 4x4 4x4 4x4 4x4 4x4 16x16 16x16 16x16 16x16 16x16 16x16 16x16 4x4 16x16 16x16 16x16 16x16 4x4 16x16 16x16 16x16 16x16 W16 N16 Figure 3: XC6200 16x16 Cell Tile June 1, 1996 (Version 1.0) 64 User IOBs (1 per border cells) Figure 4: XC6216 Device 4- 255 XC6200 Field Programmable Gate Arrays Routing Resources Each level of hierarchy (basic cells, 4x4 cell Blocks, 16x16 cell Tiles, 64x64, etc.) has its own associated routing resources. Basic cells can route to their nearest neighbors or through the neighbor cell to its neighbor. Note that cells used for interconnect in this manner can still be used to provide a logic function. Wires of length four are provided to allow 4x4 cell blocks to route across themselves without using basic cell resources. Similarly 16x16 cell tiles provide additional wires of length 16 cells and the 64x64 array provides wires of length 64. Larger XC6200 products extend this process to 256x256 cell blocks and so on, scaling by a factor of 4 at each hierarchical level as required. Intermediate array sizes (e.g. 96x96) are created by adding more 16x16 tiles. Switches at the edge of the blocks and tiles provide for connections between the various levels of interconnect at the same position in the array (e.g. connecting length 4 wires to neighbor wires). The longer wires provided at each hierarchical level are termed `Fastlanes' because it is convenient to visualize the structure in three dimensions with routing at each hierarchical level being conceptually above that in lower hierarchical levels, with the cellular array as the base layer. The length- 4 Fastlanes are driven by special routing multiplexers within the cells at 4x4 block boundaries. All routing wires are directional. They are always labelled according to the signal travel direction. For example, S4 is a length-4 Fastlane heading from North to South. In Figures 2, 3 and 4 each individual cell has a length 4, 16 and CL Fastlane above it. However only a small number are shown for clarity. The benefit of the additional wiring resources provided at each level of the hierarchy is that wiring delays in the XC6200 architecture scale logarithmically with distance in cell units rather than linearly as is the case with the first generation neighbor interconnect architectures. Since 4x4 cell block boundaries lie on unit cell boundaries, the switching function provided at 4x4 cell boundaries is a superset of that provided at unit cell boundaries. i.e it provides for neighbor interconnect between the adjacent cells as well as additional switching options using the length 4 wires. Similarly, the switching unit on 16x16 cell tile boundaries provides a superset of the permutations available from that on the 4x4 cell block boundaries. Further switching units are also provided on the 64x64 cell boundaries to provide the length CL Fastlanes. CLK S4 S Clr E4 N S E W N4 S4E4W4 Nout E X3 N S E W N4 S4 E4 W4 Wout Function Unit X1 N S W F F S E W F N E W F N S E W N4 S4 E4 W4 X2 N S E F Eout W X2 X3 W4 Sout Clk MAGIC N N4 CLR Figure 5: XC6200 Basic Cell 4- 256 June 1, 1996 (Version 1.0) X1 X2 Y2 1 0 CS Mux RP Mux X3 F Y3 D Q Clk Clr Figure 6: XC6200 Function Unit Magic Wires The majority of interconnections are routed using the nearest-neighbor and Fastlane wires described above. Each cell has a further output (labelled `Magic') which provides an additional routing resource. A cell's Magic output is not always available for routing. Its availability is dependent on the logic function implemented inside the cell. More information on the physical nature of the Magic wires is given in the section "Function Unit" on page 257. Each cell's Magic output is routed to two distinct 4x4 block boundary switches. The Magic wire can be driven by N, S, E or W from adjacent cells or from the N4, S4, E4 or W4 Fastlanes passing over the cell. This makes it particularly useful for corner-turning (all other routing resources are straight). The Magic wires are illustrated in Figure 8. Global Wires The XC6200 architecture permits registers within a user design to be clocked by different clocks and cleared by different asynchronous clears. Clocks and Clears may be provided by any user I/O pin or generated from user logic internally. In line with good synchronous digital design practices, it is recommended that a single global Clock and Clear are used. This minimizes the likelihood of timing problems and gives more reliable simulations. Four Global wires (G1, G2, GClk and GClr) are provided for low skew, low delay signals. These wires are intended for global Clock and Clear or other high fan-out signals and are distributed throughout the array in a low skew pattern. A global signal can reach the function block inputs of any cell June 1, 1996 (Version 1.0) on the array passing through very few routing switches. The four Globals are very similar. It would be possible to use GClk as a global Clear signal, however for minimum delay, it is recommended that GClk be used for global clocks and GClr for global clears. GClk and GClr can reach the inputs of any register in the array, passing through only a single routing switch. G1 and G2 may be used for secondary global clocks or clears. G1 and G2 have a slightly larger delay than GClk and GClr. Function Unit Figure 5 shows the basic XC6200 cell in detail. The inputs from neighboring cells are labelled N, S, E, W and those from length 4 wires N4, S4, E4, W4 according to their signal direction. Additional inputs include Clock and Asynchronous Clear for the Function Unit D-type register. The output from the cell function unit, which implements the gates and registers required by the user's design, is labelled F. The Magic output is used for routing as described earlier. The multiplexers within the cell are controlled by bits within the configuration memory. As can be seen from Figure 5, the basic cells in the array have inputs from the length 4 wires associated with 4x4 cell blocks as well as their nearest neighbor cells. The function unit design allows the cells to efficiently support D-type registers with Asynchronous Clear and 2:1 multiplexers, as well as all Boolean functions of two variables (A and B) chosen from the inputs to the cell (N,S,E,W,N4,S4,E4,W4) (Table 2). Figure 7 shows the schematic representations of the basic cell functions possible. The Magic routing output can only be used if the signal to be routed can be placed on X2 or X3. 4- 257 XC6200 Field Programmable Gate Arrays A ZERO A B B OR2 M2_1 ONE SEL A A BUF B INV A OR2B1 A A B M2_1B1A B A SEL NOR2 B AND2 A A A B B M2_1B1B NOR2B1 B SEL AND2B1 A A A B XOR2 B B NAND2 M2_1B2 SEL A A B B NAND2B1 XNOR2 A A B D SEL Q CLK F A D SEL CLR Q F F D Q SEL CLK CLK CLR F A B SEL CLR Figure 7: Cell Logic Functions Figure 6 shows the implementation of the XC6200 function unit. The design uses the fact that any function of two Boolean variables can be computed by a 2:1 multiplexer if suitable values chosen from the input variables and their complements are placed on its inputs. The Y2 and Y3 multiplexers provide for this conditional inversion of the inputs. The CS multiplexer selects a combinatorial or sequential output. The RP multiplexer allows the contents of the register to be `protected'. If register protection is enabled then only the programming interface can write to the register. It will not change when the X inputs to the function unit change, even if it is clocked or cleared. This feature is useful in designs containing control registers which are only to be written by an external microprocessor. The control inputs of all the multiplexers, except the one switched by X1, come from configuration memory bits. Cell Logic Functions Each cell can be configured as any two-input gate function, any flavor of 2:1 multiplexer, constant 0 or 1, single input functions (buffer or inverter) or any of these in addition to a D-type register. This is illustrated in Figure 7. The gate names given correspond to standard Xilinx library part names for these primitives. Although three inputs are shown entering the combinatorial `cloud', dual and single input functions are also possible (e.g. inverter + register or 4- 258 register alone.) The buffer symbol is available in the CAD libraries, however the place and route software will generally optimize this out as there is no requirement for the designer to buffer signals with this architecture. This is because signals are regularly buffered by routing multiplexers. Symmetrical functions are also possible but not shown in Figure 7; e.g. A*B (AND2B1) is shown but A*B (AND2B2) is not. This is because A and B are assigned to user signals by the logic mapping software to provide the required function. Thus, a multiplexer with inversion on the SEL input is unnecessary because the mapping software can simply swap the signal assignments for A and B. The sources of the X1, X2 and X3 input multiplexers are set automatically by CAD software during the logic mapping phase. Table 2 shows the assignments for all the cell multiplexers to compute the various logic gate functions. A NAND2B1 is equivalent to an OR2B1 with the inputs swapped and a NOR2B1 is equivalent to an AND2B1 with the inputs swapped; therefore, these gates are not listed in Table 2. If the register within a cell is not used in the design then a special `fast' version of most gates can be configured, using the register to provide a constant 1 or 0. For example a fast AND gate (A*B) can be configured by setting the register to 0 during configuration and assigning Q to Y3. A is routed to X1 and B to X2. X2 is assigned to Y2. When A changes to June 1, 1996 (Version 1.0) Table 2: Function Derivation Function 0 (Fast) 0 1 (Fast) 1 BUF (Fast) BUF INV (Fast) INV A*B (Fast) A*B A*B (Fast) A*B A*B (Fast) A*B A+B (Fast) A+B A+B (Fast) A+B A+B (Fast) A+B AB AB M2_1 M2_1B1A M2_1B1B M2_1B2 X1 X A X A A X A X A A A A A A A A A A A A A A SEL SEL SEL SEL X2 X A X A X A X A B B X A B B X A B B X A B B A A A A X3 X A X A X A X A X A B B X A B B X A B B B B B B B B 0, Y3 is selected and F is forced low as soon as the X1-controlled multiplexer switches. In the normal AND gate, there would be an additional delay as A propagated through the Y3 multiplexer. Fast or normal gates may be specified by the designer but, for optimal layout density, this is best left to the logic mapping software. The multiplexer functions have a straightforward mapping with fixed assignments to X1,X2 and X3, and Y2 and Y3 providing input inversions as required. Routing Switches As described earlier, each cell within a 4x4 block is able to drive its output to its nearest neighbors to the N,S,E and W. In addition to this, cells at 4x4 block boundaries are also able to drive their outputs onto length-4 Fastlanes. Special switch units are provided around each 4x4 block boundary to facilitate these connections. This is illustrated in Figure 8. These switches also allow higher levels of hierarchical routing (e.g. length - 16 and CL Fastlanes) to be connected to length-4 Fastlanes. June 1, 1996 (Version 1.0) Y2 X X2 X X2 Q X2 Q X2 X2 X2 Q X2 X2 X2 Q X2 X2 X2 Q X2 X2 X2 X2 X2 X2 X2 Y3 X X3 X X3 Q X3 Q X3 Q X3 X3 X3 Q X3 X3 X3 Q X3 X3 X3 X3 X3 X3 X3 X3 X3 RP Q X Q X Q X Q X Q X Q X Q X Q X Q X Q X X X X X X X CS S C S C C C C C C C C C C C C C C C C C C C C C C C Q 0 X 1 X 1 X 0 X 0 X 0 X 1 X 1 X 1 X 0 X X X X X X X Figure 8 also shows the connections for each cell's Magic output. Each Magic output is routed to two destinations for increased routing flexibility. The two connections are labelled M and MA. The Magic wires allow cell outputs to jump to the edge of the 4x4 block and hence onto Fastlanes or into the next 4x4 block. They are also a particularly efficient way of making large busses turn corners. N,S,E and W switches are similar, however the N switches contain additional multiplexers to drive the register Clock lines. The contents of the boundary switches are shown in Figure 9 through Figure 12. The multiplexers driving the NOut, SOut, EOut and WOut lines are actually implemented within the cell adjacent to the switch. These multiplexers take the place of the neighbor multiplexers found in the basic cell (see Figure 5). Boundary cells contain additional RAM bits to control the larger multiplexers. An additional output is available from these multiplexers. This output reflects the output that would have come from the cell's neighbor multiplexer had it been a basic non-boundary cell. To distinguish this from the output of the boundary switch (NOut, SOut, EOut or WOut), it is suffixed with a `C' (Cell); e.g. NC for an Nswitch. NC will be one of NIn, E, W, 4- 259 XC6200 Field Programmable Gate Arrays or F depending on the least-significant two bits of the NOut multiplexer select lines. Hence NC will be identical to NOut if NOut is one of F, NIn, E or W. If NOut is one of N4In, N16, PS4 or MN then NC will be one of F, NIn, E or W depending on which signal is routed to NOut. The `C' signal will be one of the upper four inputs to the 8:1 multiplexers shown in Figure 9 through Figure 12, the actual value being selected by the two least-significant multiplexer select lines. Similar `C' signals are generated in the Sswitch, Eswitch, and WSwitch. The S4 input to the NOut multiplexer in the Nswitch is actually the S4 input to the adjacent Sswitch in the 4x4 block immediately to the North of this block. This should not be confused with the S4Out signal from that block's Sswitch. This is also true of some of the other inputs to the multiplexers in other boundary switches. To avoid confusion, these inputs are prefixed with the letter `P' (for Previous). e.g. PS4. This feature allows Fastlane wires to perform U-turns. Nswitch Nswitch Nswitch Nswitch Wswitch Cell Cell Cell Cell Eswitch Wswitch Cell Cell Cell Cell Eswitch Wswitch Cell Cell Cell Cell Eswitch Wswitch Cell Cell Cell Cell Eswitch SCIn NCL N16 NCOut ClkIn N4In MNA PS16 SCL MN MS N4Out GClr NCL G1 G2 F NIn E W N4In N16 PS4 MN ClkIn NOut GClk NCOut NOut ClkOut Nswitch Figure 9: Contents of Nswitch MN NCL PN16 S4In S16 MS MSA SCL SCOut NCIn S4Out F E W SIn S16 PN4 S4In MS SCOut SOut Sswitch Figure 10: Contents of Sswitch Sswitch Sswitch Sswitch Sswitch MA nets MW MEA PW16 WCL WCIn ECOut E4In ME E16 ECL E4Out F N EIn S PW4 ME E16 E4In ECOut EOut Eswitch M nets Figure 8: Routing Switches at 4x4 Block Boundary Figure 11: Contents of Eswitch ECL W4In WCL MWA MW PE16 WCOut ME W16 ECIn W4Out F WIn N S PE4 W16 MW W4In WCOut WOut Wswitch Figure 12: Contents of Wswitch 4- 260 June 1, 1996 (Version 1.0) Clock Distribution As described previously, register clock inputs may be driven from any source but it is recommended that the GClk signal is used. GClk also has the advantage that it can be stopped by writing to the Device Configuration Register. The Global wires enter the part through dedicated input pins and are distributed in a special low-skew `H' pattern (Figure 13). Each vertically aligned (South to North) group faster clock) or sourced directly from the device programmable I/O pins. Where a fast clock is required by only a small fraction of the logic on the device it may be preferable to employ user interconnect resources rather than a Global or Chip-Length Fastlane, since limiting fast clock distribution to the area of the device where it is required will reduce power consumption. Clear Distribution 16x16 16x16 16x16 16x16 16x16 16x16 16x16 16x16 Register Clear inputs are routed in a similar manner to Clock inputs. In this case vertical groups of 16 cells, within a 16x16 tile, share a common Clear. Clear lines run in a Southerly direction and are sourced from the Sswitch unit of 4x4 blocks which also lie on a 16x16 boundary. All of the boundary switches at 16x16 boundaries contain additional switching multiplexers. These are illustrated in Figure 14. 16x16 ClrOut drives the Clr inputs to each of the sixteen cells in the group. The S and SCL connections allow the output of a cell to provide a user-generated local Clear signal. 16x16 16x16 16x16 North Boundary 16x16 16x16 16x16 16x16 Global Input Figure 13: Low Skew `H' Distribution Of Global Signals (XC6216) of four cells within a 4x4 block is clocked by its own clock source. This is driven from a multiplexer in the Nswitch immediately to the South of the group of cells. The connections for this multiplexer are shown in Figure 9. ClkOut drives the Clk inputs to each of the four cells in the group. As can be seen from Figure 9, the register clock for each group of four cells can be driven by ClkIn, NOut, GClk, GClr, G1, G2 or NCL. ClkIn is the ClkOut from the 4x4 block to the South, allowing vertical daisy-chaining of clock signals. NOut is the N output from the cell associated with the Nswitch. This can be used to provide local user-generated or gated clock signals if required. GClk is the Global Clock signal direct from the device GClk input. Clearly this signal only has to pass through one 4:1 multiplexer whereas GClr, G1 and G2 have to pass through two. This is one reason why there is less delay on GClk. It is also possible to route North chip-length Fastlanes onto the Clock lines. This allows up to 64 (for a XC6216 device) locally used clocks to be provided that can still run the entire length of the chip with minimal skew. These local clock signals may be generated internally (e.g. by dividing a June 1, 1996 (Version 1.0) East Boundary West Boundary NCL SCL N16In N4In PS4 NCOut WCL ECL E16In N16Out PW4 E4In WCIn WCL ECL W16In E16Out W4In PE4 WCOut SCIn MN ECOut ME ECIn MW NCL SCL S16In PN4 S4In NCIn SCOut MS South Boundary S16Out GClr ClrIn SCL G2 GClk 0 W16Out ClrOut SOut G1 Figure 14: Additional Switches at 16x16 Boundaries Input/Output Blocks (IOBs) User-configurable Input/Output Blocks (IOBs) provide the interface between external package pins and the internal logic. One IOB is provided for every cell position around the array border. IOBs are connected to fixed pad locations. There are more IOBs than available pads, hence some IOBs are `padless'. However it is still possible to route signals from padless IOBs to device pins. Figure 15 is a simplified diagram of an IOB and its associated IO pad. The IOB is located at the array border and the pad is located close to its device pin. The pad may be located some distance from its associated IOB. The map- 4- 261 XC6200 Field Programmable Gate Arrays IOB IO PAD ControlEnable PUp ArrayEnable V DD Slew ArrayDToPad ControlDToPad Enable 0 1 Data DToPad Neighbor Data Array Data DelData PIN DFromPad DELAY Fastlane Data Signals From Array PDn Control Data V SS L16 Output From Array Figure 15: Input/Output Architecture The `Control' signals are routed to the internal XC6200 control circuitry. If control signals are not required all the time then these IOBs can be used to route other user signals into the array. For example if only eight data bus bits were continuously required, the remaining twenty-four IOBs associated with the data bus could be used to route user signals to/from the array. ControlEnable comes either from the internal XC6200 control circuitry if there is a bidirectional control signal or output signal on that IOB, or it is tied inactive. 4- 262 Enable ArrayEnable ArrayDToPad ArrayData DToPad DFromPad NORMAL IOB Control Data ControlDToPad ControlEnable DFromPadB DToPadB EnToPadB Enable Each IOB has an array data input and a control data input, labelled ArrayDToPad and ControlDToPad in Figure 15. Associated with these inputs are two enable signals - ArrayEnable and ControlEnable. These signals control whether the pad associated with this IOB is in the input or output mode. Each IOB also supplies ArrayData and ControlData when acting as an input. `PADLESS' IOB ArrayDToPad DToPad As an example of the power of this feature, an XC6200 design could include an address decoder which decoded microprocessor read/write cycles and produced appropriately retimed signals for all the parts on a board including itself, thereby removing the need for address decoding PAL's or discrete logic. ArrayEnable ArrayData The XC6200 IOB architecture incorporates a novel and very powerful feature: every IOB has the capability of routing either an array signal or a control logic signal to/from the device pin. Every signal, including all the control signals (e.g. CS, RdWr, Address Bus, Data Bus, etc.), passes through an IOB. This means that all the control signals can be routed into the logic array for use in user designs. Similarly, user logic can control the XC6200 internal control circuitry. For example a user signal could be used to drive the internal CS signal rather than the CS pin. There are less real control signals than IOBs, hence the three control signals on some IOBs are not connected to the device control logic. These spare control signals are used to route data to and from the padless IOBs mentioned above. The control signals on the padless IOB are not used. This is illustrated in Figure 16. DFromPad ping of IOBs to device pins is given in the pinout tables starting on page 282. IO PAD Figure 16: `Padless' IOB Configuration June 1, 1996 (Version 1.0) The `Control' signals are also referred to as `B' signals later in this data sheet. ControlDToPad = DToPadB, ControlEnable = EnToPadB and Control Data = DFromPadB. Also the L16 output from the array, which can be routed onto Control Data, is referred to as DForPadB. ers and may be activated at any time. Only when OE is active and there is a valid ID pattern in the ID register, do the pull-up and pull-down RAM control bits determine the IO-pad resistor configuration. Three configuration RAM bits within each IOB control the programmable aspects of its IO pad. These RAM bits have no effect for padless IOBs. `PUp' and `PDn' enable the pullup and pull-down resistors. The resistors may be used to tie floating logic inputs to a known value. `Slew' slows the output transition time to reduce supply noise and groundbounce. The default condition is pull-up off, pull-down off and slew on. The array signals to and from the IOBs are generally just the signals which would have passed between two cells in the array. The ArrayDToPad signal in Figure 15 is actually the neighbor output from the border cell associated with the IOB. The Array Enable signal is the length-4 Fastlane output from the same cell. The Array Enable, Array Data and Control Data multiplexers are also controlled by configuration RAM bits. A fixed delay may be optionally applied to Array Data inputs. This allows the input data hold time specification to be removed. The ArrayEnable and ArrayDToPad signals can be configured to constant 0 or 1 values within the logic array. The constant values are particularly useful for the enable signal when the pin is to function as an input or output rather than a bidirectional pin. Constant values on the data signal and a computed value on the enable signal produce open drain pull-up (DToPad=1) or pull-down (DToPad=0) pins. During reset, all the output drivers are disabled and the pull-up resistors are enabled. The pull-up and pull-down RAM control bits have no effect. After a reset the output drivers remain in this state. For the output drivers to be enabled, the global OE signal must be asserted (low) and a valid configuration must be present in the device ID register. The ID register is usually the last thing to be written during configuration and acts as a check that the programming interface is operating correctly. More details of this are given in the `Programming' section on page 268. The OE signal provides a quick way of disabling all the output driv- June 1, 1996 (Version 1.0) I/O Routing `0' ECLOut PW4In WCLIn WCIn MWIn PW4In ECLOut PW16In WCIn E16Out MWIn WrEn RdEn DataBit ControlDToPad DelData DelData ECLOut WCLIn PW16In WCIn E4Out DFromPad EOut MWIn ControlDToPad PW4In Control Enable DelData Figure 17: Array Data Sources In West IOBs 4- 263 XC6200 Field Programmable Gate Arrays The Array Data multiplexer in Figure 15 is actually a collection of multiplexers that source the neighbor, length-4, length-16 and chip-length wires into the array. South IOBs (IOBs at the South edge of the array) also source the local clock signals into the array. North IOBs source the local clear signals. This is illustrated for a West IOB in Figure 17. These multiplexers also allow a number of other internal control signals to be routed into the array: WrEn and RdEn are signals which are active during state register accesses. `DataBit' is the state register output value for this row during a state access. Details of the timing of these signals are given in the "Parallel Programming Interface" on page 268. Note that in order to provide a minimal delay signal path into the core array, the neighbor data output from the IOB cannot select the delayed version of DFromPad. Only the un-delayed DFromPad and the Previous Length-4 Input can be routed onto the neighbor data output. Therefore the neighbor data output is unaffected by the value of the configuration memory which controls the DelData multiplexer in Figure 15. The length-4 and length-16 routing multiplexers at the array border also expect some inputs which are not available. For example at the West edge, MEIn, ECIn, PE4In and PE16In are non-existent. These inputs are tied to ground thereby providing an abundant source of constant zeros and ones at the array border. These can be used to provide constant values to drive the Array Enable inputs to IOBs. 4- 264 FastMAP Interface CS RdWr A(15:0) D(31:0) OE Reset I/O G1 G2 GClk GClr Figure 18: XC6216 Logic Symbol June 1, 1996 (Version 1.0) Automatic Mapping, Place and Route Front End Design Entry Data M2_1 XOR2 En FDC D In-System Verification Clk Out Data M2_1 CLR EDIFNetlist En Cell1 ARCHITECTURE rtl OF counter IS...... Data NodeDelays CLK Load ENTITY counter IS PORT (data : IN std_ulogic; en : IN std_ulogic; ........ out : OUT std_ulogic);...... Load FDC Out D XOR2 CLK Load Logic Simulation CLR Cell2 En Binary Config File Out 00010 10011 00011 10011 00100 Failed Simulation Manual Place and Route using Physical Editor (optional) XOR2 Failed Test M2_1 FDC Figure 19: XC6200 Logic Design Flow Designing with XC6200 The designing of XC6200 FPGAs into systems may be partitioned into three distinct activities: board design, logic design, and software design. Board Design with XC6200 An XC6200 part may be used on a board design as a microprocessor peripheral part, as an ASIC-type device or as both. In the first instance the XC6200 part will have conventional SRAM data, address and control signals. In other cases, it may only require the user defined I/O signals of an ASIC. Packaging information for the part is shown in Table 6. The number of user I/O signals will depend on the exact package used. Several XC6200 devices may be tiled together on a board to form a larger array. The regular array structure of XC6200 devices makes this particularly easy. The configuration RAM bits in the IOBs allow for a number of different programmable options to make interfacing to other ICs easier. Logic Design with XC6200 This can be approached as an ASIC type design using the function and routing architecture defined in the previous sections. An example design flow is illustrated in Figure 19. The design may be carried out in a variety of different ways. Hardware description languages such as VHDL may be June 1, 1996 (Version 1.0) used with the synthesized design targeted to the XC6200 architecture. Alternatively, schematic capture, using the extensive Xilinx Unified Library, with commonly used front end design tools (e.g. ViewLogic PROcapture/ViewDraw) may be used. These tools produce an EDIF netlist which is subsequently passed to the underlying XC6200 place and route software. This automatically maps the user's design to the XC6200 architecture in an efficient way and provides individual node delays which can be passed back to the high level simulation tools such as Viewlogic PROsim/ ViewSim for accurate simulation. Simulation may be carried out prior to placement to check the logical correctness of the design using nominal delays. The place and route software also has optimization capability to carry out tasks such as redundant gate removal. A binary configuration file that can be written to the XC6200 device via the programming interface is also produced automatically. The underlying CAD software is highly integrated with the high level CAD tools, providing user-friendly pull-down menus and dialog boxes to carry out all tasks. These methods allow designers with little or no knowledge of the XC6200 architecture to quickly produce large and complex designs. Some designers may wish to carry out detailed hand placement and routing to produce ultra-optimized very high-speed/small area sections in their designs. Others may wish to generate large regular structures such as systolic arrays or perform floor-planning for extra efficiency. For these cases, a sophisticated physical editor is available that allows designers to graphically modify the 4- 265 XC6200 Field Programmable Gate Arrays automatic placement of gates/registers into cells and modify the routing as much as required. Alternatively this software may simply be used to see how the automatic placement and routing software has optimized a design. If a modification is subsequently made, then only the modified part of the design needs to be re-laid out. This incremental design process provides a very rapid change cycle during debugging. it is annotated with the instance names of the mapped primitives. The primary inputs and outputs are not shown in this example. MUX1 M2_1 D0 All the design tasks may be carried out on PC or Unix workstation platforms. O IN D1 COUT CIN S0 FDC1 As an example, the simple accumulator circuit of Figure 20 is mapped onto the XC6200 architecture. Figure 21 shows the resulting layout as displayed by the Physical Editor running under Microsoft Windows in this case. The Physical Editor tools are also available for Unix workstations. The boundaries of basic cells within the array are denoted by the squares, with larger rectangles representing the switch units on 4 cell boundaries. The wiring resources used by the design mapped onto the array are indicated by solid black lines. When a cell function unit is used by the design XOR2 FDC XOR1 D Q SUM XOR2 XOR2 C CLR CLK CLR Figure 20: Accumulator Schematic Figure 21: Accumulator Physical Editor View 4- 266 June 1, 1996 (Version 1.0) The inputs and outputs to the function unit are connected to the edges of the cell box. The CAD plot shows all the routing resources available. To the left of each cell the six wires running in a Southerly direction are: SCL, S16, Clr, S4, Magic and S. The signal direction is indicated with arrow heads. S, S4 and Clr are shown entering the cells on the left edge of the cell boxes. The two outputs on the left edge of the cell box are Magic and SOut. The inputs and outputs on the remaining three cell box edges follow a similar pattern. The Clk input on the right hand cell box edge is denoted with a clock `<' symbol. The Physical Editor allows cells to be selected and moved. The inter-cell routing rubber-bands and adapts automatically to the new placement. The routing may also be manually modified if desired. 64 64 I/O North 57 64 I/O W E S T Row D e c o d e 64x64 Cell Array Column Decode Control Software Design with XC6200 Register Access The XC6200 architecture supports direct accesses from the processor to nodes within the user's circuit: the output of any cell's function unit can be read and the flip-flop within any cell can be written. During state reads a number of cell outputs are routed onto the CPU data bus. The signal which is actually read is the inverse of F in Figure 6 (= Q or D). These accesses are carried out through the control store interface and involve no additional wiring within the user's design. The CPU interface signals involved in addressing the cell state can be routed into the configurable array so that user circuits can detect that an access has been made and take appropriate action: for example, calculate a new value for an output register or process a value placed in an input register. In many applications this access to internal nodes will be the main path through which data is transferred to the processor and in some coprocessor type applications it may be the only external I/O method: user programmable I/O pads may not be required at all. To allow high bandwidth transfers between the processor and internal nodes it is necessary to be able to transfer a complete processor data word of up to 32 bits in one memory cycle. For this reason, access bits are mapped into a separate region of the device address space from configuration bits so that all the bits in a word contain access bits. June 1, 1996 (Version 1.0) 57 Global I/O 64 Figure 22: XC6216 Block Diagram Figure 22 is a block diagram of the XC6216 part, showing the row and column address decoders. Figure 23 shows the mapping of this area of the address space: there are 64 I/O signals from each column of cells and a 6-bit column address selects a particular column of cells to access. This row and column addressing scheme puts a constraint on the placement of registers within the user's design that are to be accessed word-wide: they must be on the same column of cells within the array. (63,63) (0,63) SELECT This is the design of a program for the host processor which interacts with a design running on the XC6200 FPGA. Here various registers within the XC6200 design appear as locations within the processor's memory map. In addition, the configuration memory of the device appears within the memory map and portions of the device can be reconfigured as required. Predefined device drivers and an efficient run-time library are available to make optimal use of the high speed reconfiguration capabilities with minimal development time. 64 I/O South 64 I/O E A S T Row (63:0) D(8,16 or 31:0) (0,0) (63,0) Column Address CA(5:0) Figure 23: Memory Mapped I/O 4- 267 XC6200 Field Programmable Gate Arrays Map Register The XC6200 architecture also provides a mechanism for mapping the 64 possible cell outputs onto the 8,16 or 32-bit external data bus, selecting only those cells that implement bits of the register to be accessed. Without this unit the processor would have to implement a complex sequence of shift and mask operations to discard those bits corresponding to cells not within the register, or the user would have to constrain the layout so that the register bits were in adjacent cells. The mechanism provided takes the form of a 64bit map register, one bit for each row I/O signal from the array. This map register can be read and written through the control store interface and is set up prior to state accesses. A logic 0 in the map register indicates that the cell in the corresponding row is part of the register to be accessed. The unit maps rows from the cell array onto external data lines starting with the least significant bit: thus the first row with a 0 in the map register will connect to external data bus bit 0, the second row with a 0 in the map register to data bus bit 1 and so on. This technique puts a further constraint on the user's layout: the cells implementing the bits of the register must be ordered so that less significant bits occur below more significant bits. However, there are no constraints about the relative separations of the cells. In practice these two placement constraints: cells occurring in the same column and in order vertically are easy to meet in datapath type designs. Normally, the map register will be set once to indicate the placement of the user I/O register that will then be accessed many times. Therefore the two write operations required with a 32-bit bus to set up the map register represent a small overhead. In data path type designs where several registers are required, for example two input operand registers and a result register, it is easy to ensure that the corresponding bits of the registers occur on the same row but different columns of the array so that the same map register value can be used with different column addresses to access the various registers. If more `0's exist in the map register than there are valid data bus bits then a form of wildcarding occurs during writes. The data bus bits are allocated to the rows of the array with a `0' in their map register bit. Once all of the data bus bits have been allocated, Bit 0 of the data bus is allocated to the next row whose map register bit is a `0', Bit 1 of the data bus to the next row and so on. This feature means that an entire column of state registers can be written with a single 8-bit write. For example, if the map register contains all `0's and the CPU writes FFh to a particular column. All the state registers in that column will be written with a `1'. The default state of the map register is all `0's. During reads, if there are more `0' bits in the map register than data bus bits, the first rows with `0' bits are mapped onto the bus. 4- 268 If there are less `0's in the map register than data bus bits, the upper data bus bits, which are not mapped, will be read as `1's during CPU reads and ignored during CPU writes. An example of map register operation is shown in Figure 24. The position of the user-defined register within the cell array is defined by the `0's in the 64-bit map register. Similar registers could be defined for every column in the array if desired. There is a delay after a write to the map register before the change takes effect. No state accesses should be carried out during this time. Mask Register A mask unit controlled by a 32-bit register is placed between the external data bus and the internal data connections. When the external data bus is 8 or 16 bits wide only the bottom 8 or 16 bits of this register are significant. A logic `1' in a bit of this register indicates that the corresponding bit of the internal data bus is not relevant. Bit locations corresponding to `1's in the Mask Register will retain their values when written. On a write operation the corresponding bit line will not be enabled and the state information for that bit will not be changed. When the device is reset the Mask Register will contain all logic 0's corresponding to all data bus bits valid. During CPU reads, valid register bits which are disabled will be read as `0'. Invalid bits (bits which do not physically exist for the register being read) may be read as `0' or `1'. The mask register does not affect state register accesses. In this case the map register can be used to prevent certain bits being modified. Programming The binary data for configuring an XC6200 device, generated by CAD software from the textual description of a user design, must be downloaded into the part itself. This may be performed in several ways. Generally, the fastest and most efficient way is by writing directly to the control store, mapped into the address space of a host processor. If a microprocessor or other parallel data source is not available, then the serial programming interface may be used. Parallel Programming Interface The XC6200 FPGA has a conventional programming interface for static RAM, based on Chip Select (CS) and Read/ Write (RdWr) control signals. The CS signal can be used to address a single part within an array of devices and allows data to be read or written. Timing for these signals is illustrated in Figures 28 and 29. These figures show that the programming interface is synchronous. The GClk input is used to sample all the interface signals. GClk is also used when accessing user registers as illustrated in Figure 24. This is an important point, as only registers clocked directly by GClk can be reliably read or written using this method. June 1, 1996 (Version 1.0) 8-Bit Data Bus Example XC6200 Boundary User-defined register within array Cell Array Map Register 1 1 0 0 Bit 7 Bit 6 1 Data 1 Bus 1 1 1 0 0 0 Bit 5 Bit 4 Bit 3 1 0 Bit 2 1 0 0 Address Bus Address Decode Bit 1 Bit 0 1 1 Cells RdWr CS CPU Interface Write Enable Figure 24: Internal Register Access Figure 29 shows two separate read cycles - a normal cycle immediately followed by an extended cycle. In the normal read cycle CS is sampled low on the first rising GClk edge (t1) and high on the next (t2). The data bus is then driven until the next rising GClk edge (t3). In cases where this is not long enough, the read cycle can be extended by keeping CS asserted beyond t2. This is equivalent to adding wait states. In this case the data bus is driven until CS is deasserted. CS should not be allowed to go high and low again. This would cause another cycle to begin. CS is sampled on every rising GClk edge. Other CPU interface signals such as RdWr and the Address Bus are only sampled on the first GClk edge of the cycle (t1 for the first cycle and t3 for the second in the figure examples). June 1, 1996 (Version 1.0) Extended write cycles are also possible, however these are functionally no different to normal write cycles, the data and address busses still being sampled on the first rising GClk edge of the cycle (t3 in Figure 28). CS must always be sampled as a `1' before the next cycle can begin. In Figure 29 the extended read cycle starts immediately after the normal read cycle at time t3. A write cycle could not start until the next rising GClk edge as the data from the read cycle is still on the data bus. The SRAM programming interface is supplemented by additional hardware resources designed to minimize the number of processor cycles required for reconfiguration. 4- 269 XC6200 Field Programmable Gate Arrays These resources are initially inactive after a reset so the device looks like an SRAM. used to determine which area of the control store is to be accessed according to Table 4. The control store layout is designed to minimize the overhead of computations required for dynamic access while maintaining adequate density to minimize the external storage required for device configurations. When an external processor is used to configure the device it may be convenient to use a compressed format of the configuration information. Table 4: Address Mode Selection A feature of the XC6200 architecture is that a rectangular area of cells specified as a hierarchical block within a user's design corresponds directly with a rectangular area within the configuration memory of the XC6200 device. This means that a block within the user's design can be dynamically replaced with another block by the host processor, reconfiguring only the corresponding area of the control store. The binary data for both blocks can be pre-calculated from the cellular design and the actual replacement can be carried out very rapidly using a block transfer operation. The format of the address bus to the XC6216 device is shown in Table 3. Larger XC6200 devices have proportionally more bits allocated to row and column addresses. Table 3: Address Bus Format (XC6216) Mode(1:0) Column(5:0) Column Offset<1:0> Row(5:0) 15:14 13:8 7:6 5:0 All the configuration memory can be accessed as 8-bit bytes. When a 16-bit transfer occurs Address<0> is irrelevant. When a 32-bit transfer occurs Address<1:0> is irrelevant. Data Bus bits <7:0> are written to the address with Address<1:0>=00, bits <15:8> are written to the address with Address<1:0> = 01, etc. The Address Mode bits are 4- 270 Mode1 0 0 1 1 Mode0 0 1 0 1 Area Selected Cell Configuration and State East/West Switch or IOB North/South Switch or IOB Device Control Registers Wildcard Registers The wildcard register allows many cell configuration memories within the same column of cells to be written simultaneously with the same data. This is used during device testing to allow regular patterns to be loaded efficiently into the control memory but is more generally useful, especially with regular bit sliced designs, since it allows many cells to be changed simultaneously. For example, a 16-bit 2:1 multiplexer could be built using cell routing multiplexers and switched between sources using a single control store access. Similarly, the column address decoder has a wildcard register which allows several cells on the same row to be written with the same configuration. The column address decoder drives the word lines to enable particular columns of RAM cells. In this case the number of columns which can be written simultaneously is limited to 32: that is at most five don't care bits can be set. The row and column wildcard registers can be used simultaneously to rapidly configure regular structures onto the device. The address decoding for the XC6216 FPGA is summarized in Table 5. June 1, 1996 (Version 1.0) Serial Programming Interface Table 5: XC6216 Memory Map Address Bus Decode 00 Cells A[15:14] 01 East/West Switch or IOB (Mode[1:0]) 10 North/South Switch or IOB 11 Control Registers Cell Mode - Cell column North/South Mode - Switch column A[13:8] (Column[5:0]) East/West Mode Column[5:2] = 4x4 block number Column[1:0] decoded as: 00 West Switch 01 West IOB (Column[5:2]=0000) 10 East IOB (Column[5:2]=1111) 11 East Switch Cell Mode A[7:6] (Column Offset[1:0]) 00 Neighbor Routing 01 Function Input Routing 10 Function 11 State Access (Cell Registers) 00 N/S Switch or N/S IOB Reg 0 01 N/S Switch or N/S IOB Reg 1 10 N/S Switch or N/S IOB Reg 2 11 N/S Secondary Clock Mux (Column[1:0] = 00 or 11) 00 E/W Switch or E/W IOB Reg 0 01 E/W IOB Reg 1 Cell Mode - Cell row East/West Mode - Switch row (Row[5:0]) The serial PROM interface consists of 6 dedicated I/O pins: Serial North/South Mode Row[5:2] = 4x4 block number Row[1:0] decoded as: 00 South Switch 01 South IOB (Row[5:2]=0000) 10 North IOB (Row[5:2]=1111) 11 North Switch June 1, 1996 (Version 1.0) Input that controls transitions between states in serial mode state machine. 0 => serial mode, 1 => parallel mode Wait Input that controls transitions between states in serial mode state machine. 0 => continue loading, 1 => pause until Wait deasserted SEReset Output from Master FPGA that resets serial PROM address counter. SECE Output from Master FPGA that enables serial PROM output. SEClk Output from Master FPGA that clocks serial PROM and slave FPGAs. SEData is clocked into the FPGAs on the rising edge of SEClk. SEData Serial data input to FPGA. This is sampled in the FPGA by SEClk and retimed by the FPGA's own GClk. North/South Switch Mode East/West Switch Mode A[5:0] All the memory mapped locations in an XC6200 device may be written in parallel or serial mode. All the operations which can be carried out with the parallel interface may also be done serially. The serial interface gives random access to all the XC6200 memory locations. The serial interface is designed to operate with any Xilinx serial PROM. A single serial PROM may be used to configure several FPGAs. In this case one of the FPGAs acts as a `Master' and the others as `Slaves'. The Master controls the serial PROM and the Slaves. This is illustrated in Figure 25. In a multi-FPGA configuration a user I/O also will have to be available to provide the Wait input to the next device in the chain. On Reset each FPGA examines its Serial and Wait inputs. Any FPGA that sees both these signals low at this time assumes it is the master and drives SEReset, SECE and SEClk. All User I/Os are held in a high-impedance state (with pull-up) until a valid configuration is loaded. In Figure 25, the User I/Os will be pulled high on Reset, hence the Wait input to the Slaves will be high and they will configure as Slaves. A valid configuration is assumed when the device ID register is loaded with the correct ID. Programmable I/Os can only be enabled when this is present. Serial data is loaded in address/data pairs. Once an address/data pair has been shifted into the FPGA, the data word is parallel written to the corresponding address inside the FPGA just as though a parallel CPU write had occurred. This means it is possible to do all the things which can be accomplished with the parallel interface, e.g. use of the mask register, writes to cell state registers, etc. 4- 271 XC6200 Field Programmable Gate Arrays MASTER FPGA Serial Gnd Wait SLAVE FPGA 1 Serial User I/O Wait SLAVE FPGA 2 Serial User I/O Wait etc... SEReset SERIAL SECE PROM SEClk SEClk SEClk SEData SEData SEData Figure 25: Master-Slave Serial Configuration The write operation is pipelined so there need be no interruption in the serial data stream. The first address/data pair must be preceded by a Synchronization Byte = 1111_1110. There are no start/stop bits, checksums or error check/correction bits. The address and data are shifted in MSB first. The address is always 16-bits. The data word is initially 8-bits but may be increased to 16 or 32 bits by loading the device configuration register with the appropriate code. The bits are shifted in on the rising edge of SEClk. The SEClk rate may also be increased by writing the appropriate code to the device configuration register. Initially SEClk is 1/16 GClk frequency. It can also be set to 1/8, 1/4 or 1/2 GClk. An example is shown in Figure 25. Data1 is loaded into Addr1 after the address lsb has been shifted in. In this example the first write was to the device configuration register and the data bus width was changed from 8 to 32 bits. Data word 2 starts immediately after Addr1 has been shifted in. Due to the new data bus width, 32 data bits will be shifted in. If the width had not been changed data word 2 would also have been 8 bits. Data will continue to be loaded until Serial goes high or Wait goes low. 4- 272 Reset And Initialization When the XC6200 FPGA is powered up or after a reset, all configuration memory is cleared and the cell state registers are cleared. The Reset pin is not required to be active during or after power-up to initialize the FPGA. To avoid potential high current random configurations, the power-up reset is carried out automatically. The automatic power-up initialization takes 2.5 s. All the XC6200 I/O pads are disabled during this time and it is impossible to access the device. The XC6200 may be re-initialized at any time by asserting the Reset input for a minimum of 20 ns. This acts as a signal to the chip to initialize itself. This initialization occurs after Reset has been deasserted. Therefore there is a 1.0 s (typ.) reset recovery time when no device accesses are possible. June 1, 1996 (Version 1.0) Pin Descriptions OE The pins are labelled as follows: When this signal is low the outputs of all programmable I/O pads are forced into a high impedance state (independent of the contents of the control store). All the IO-pad pull-up resistors are also enabled. This pin is always configured as an input and cannot be used as a fully flexible User I/O like the majority of other control signals. VDD Connections to the nominal +5V supply. All must be connected. GND Connections to ground. All must be connected. CS Serial Input which controls transitions between states in serial mode state machine. Chip Select enables the programming circuitry and initiates address decoding. When CS is low, data can be read from or written to the control memory. This signal is intended to be used in conjunction with address decoding circuitry to select one part within a larger array for programming. Wait D SEReset (d+1)-bit bidirectional data bus. Used for device configuration and direct cell register access. Output from Master FPGA which resets serial PROM address counter. A SECE Address bus for CPU access of internal registers and configuration memory. `a' varies between family members. Output from Master FPGA which enables serial PROM output. RdWr SEClk When CS is low this signal determines whether data is read from or written to the control memory. If RdWr is high then a read cycle takes place. If RdWr is low, then a write cycle takes place. Output from Master FPGA which clocks serial PROM and slave FPGAs. GClk, GClr, G1, G2 Global signals. GClk should be used for global user clocks, GClr for global user clears and G1 and G2 for other global, low-skew signals. The GClk pin is always configured as an input and cannot be used as a fully flexible User I/O like the majority of other control signals. Reset When Reset is taken low the programming registers (mask unit and address wildcard unit) are re-initialized, resulting in the XC6200 device appearing as a conventional SRAM. The control store of the cell array is initialized into a low power consumption configuration. All programmable output pad enable signals are forced inactive. All the IO-pad pullup resistors are also enabled. This signal should be taken low immediately after power up to initialize the device. This pin is always configured as an input and cannot be used as a fully flexible User I/O like the majority of other control signals. Input which controls transitions between states in serial mode state machine. 0 => continue loading, 1 => pause until Wait deasserted SEData Serial data input to FPGA. This is sampled in the FPGA by SEClk and retimed by the FPGA's own GClk. ConfigOK Signal is active (high) when a valid pattern is present in the ID register and inactive when the pattern is invalid. Nx North I/Os. Connections to I/O Blocks on the north of the array. Sx South I/Os. Connections to I/O Blocks on the south of the array. Ex East I/Os. Connections to I/O Blocks on the east of the array. Wx West I/Os. Connections to I/O Blocks on the west of the array June 1, 1996 (Version 1.0) 4- 273 XC6200 Field Programmable Gate Arrays Electrical Parameters The XC6200 series is fabricated in 0.65 micron triple metal n-well CMOS. Foundry sources for this part have been chosen to meet or exceed relevant military standards and industry practice. As with all CMOS devices, care must be exercised when handling this part as it can be damaged by static discharge, although standard circuit design procedures have been adopted to minimize this risk. The power consumption of a XC6200 device can vary from a few tens to several hundreds of milliamps depending on its configuration and the data applied to it. The most significant sources of power consumption are I/O blocks and dynamic dissipation within the array, both of which are largely under user control. Dynamic power dissipation is of most concern where the XC6200 device is used to implement highly concurrent computations. Power dissipation must be considered carefully, not only because excessive dissipation could result in device failure but also because operating speed is reduced at high temperature. A 0.22F decoupling capacitor across VCC and GND per part is recommended. Surface mounted, radial, plastic or ceramic capacitors are suitable. Where possible, user designs that could result in many output pads making a simultaneous transition in the same 4- 274 direction should be avoided. This is especially important on heavily loaded connections to non-XC6200 parts. To minimize power dissipation, redundant connections in user designs (which may arise in hierarchical design styles to promote sub-block re-use) should be deleted by CAD programs prior to programming XC6200 devices. As a general guideline, users should attempt to minimize the number of cell resources used. Where buffers must drive heavy external loads it may be helpful to choose I/O blocks near GND pads. XC6200 parts automatically reset themselves after power up, since the random values in the control store at this time could correspond to a relatively high power dissipation configuration. The XC6200 part distributes power using a redundant scheme which ensures minimal voltage drop between pads and internal circuitry. Power for pads is distributed on a separate power and ground ring. The maximum power consumption of the XC6200 is limited by two factors: the metal conductors supplying the part and heat dissipation. The metal conductors can handle up to 100mA each. Heat dissipation is generally a much more serious consideration: a full discussion of thermal characteristics for the different package options is given in section 4 of this data book. June 1, 1996 (Version 1.0) XC6200 Switching Characteristics Notice: The information contained in this data sheet pertains to products in the initial production phases of development. These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest sheet before finalizing a design. XC6200 Operating Conditions Symbol Parameter VCC Supply voltage relative to GND Commercial TJ = 0o C to 85o C junction Supply voltage relative to GND Industrial TJ = -40o C to 100o C junction VILT Low-level input voltage - TTL configuration VIHT High-level input voltage - TTL configuration VILC Low-level input voltage - CMOS configuration VIHC High-level input voltage - CMOS configuration TIN Input signal transition time Min 4.75 4.50 0 2.0 0 70% Max 5.25 5.50 0.80 VCC 20% 100% 250 Units V V V V V V ns XC6200 DC Characteristics Over Operating Conditions Symbol Parameter VOH High-level output voltage VOL Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins ICC2 Quiescent Supply Current Test Conditions IOH = -8.0 mA VDD = Min IOL = 8mA VDD = Min VDD = Max VIN = GND or VCC VDD = Max VO = GND or VCC VIN = GND f = 1.0 MHz VIN = VCC or GND VDD = 5 V f = 1.0 MHz @ 25C Min Max 3.86 10 Units V 0.4 V 10 A TBA A 15 pF TBA mA Notes: 1. Sample tested. 2. Measured with no output loads, no active input pull-up resistors and all package pins at VCC or GND. XC6200 Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC+0.5 -0.5 to VCC+0.5 -65 to +150 +260 Units V V V C C Warning: Stresses beyond those listed under XC6200 Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under XC6200 Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. June 1, 1996 (Version 1.0) 4- 275 XC6200 Field Programmable Gate Arrays XC6200 Power-on/Reset Timing Parameters Symbol TWMR TMRR TPRR Parameter Master Reset input Low pulse width Recovery time after Master Reset deasserted Recovery time after power up Min Typ 20 1 2.5 Advance Max Units ns s s Min Max TBA TBA TBA TBA Advance Units ns ns ns ns XC6200 Serial Configuration Timing SEClk Description SEData setup SEData hold Setup before GClk Hold after GClk Symbol 1 2 3 4 TDC TCD TCG TGC XC6200 Global Buffer Switching Characteristic Guidelines Symbol TPGClk TPG TPClr TPCkS TPClS Note: Speed Grade: Parameter From pad through GClk buffer to any register clock From pad through G1,G2,GClr buffers to any register clock From pad through global buffers to any register clear Skew between any pair of register clocks using the same global Skew between any pair of register clears using the same global -2 Min Max 12 12 11 0.9 0.9 Advance Units ns ns ns ns ns Typical loading values are used. XC6200 Cell Switching Characteristic Guidelines Speed Grade: Symbol TILO1 TILO23 TICK1 TICK23 TIHCK1 TIHCK23 TCH TCL fTOG TCLW TCKO TCKLO Parameter X1 change to Function Output(1) X2/X3 change to Function Output(2) Internal Register Set-Up Time @ X1(1) Internal Register Set-Up Time @ X2/X3(2) Internal Register Hold Time @ X1(1) Internal Register Hold Time @ X2/3(2) Clock High Time(3) Clock Low Time(3) Export Control Max. flip-flop toggle rate Clear Pulse Width(3) Clock to Function Output Clock to Function Output via X2/X3 feedback mux's -2 Min Max 2 3 3.5 4 -1.5 -2 4.5 4.5 111 1 2 3 Units ns ns ns ns ns ns ns ns MHz ns ns ns Advance Notes: 1.Data input measured at input to X1 routing multiplexer. Clock input measured at register. 2.Data input measured at input to X2/X3 routing multiplexers. Clock input measured at register. 3.Measured at the actual register in the cell. 4.Typical loading values are used. 4- 276 June 1, 1996 (Version 1.0) XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) All values listed below are tested directly and guaranteed over all the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The delay calculator software uses this indirect method. When there is a discrepancy between these two methods, the directly tested values listed below should be used and the derived values should be ignored. Speed Grade: Symbol TICKOF TICKO TPSUF TPSU TPHF TPH Parameter Global Clock (GClk) to Output (fast) Global Clock (GClk) to Output (slew limited) Input Set-up Time (fast) Input Set-up Time with delay Input Hold Time (fast) Input Hold Time with delay -2 Best I/O Min Max Worst I/O Min Max 19 22.6 -4 5 6.5 -2.5 Advance Units ns ns ns ns ns ns Notes: All appropriate AC specifications tested using Figure 27 as test load circuit. These parameters are tested directly and guaranteed over the operating conditions. As the parameters vary between I/Os, values are given for best and worst I/Os. The parameters for other I/Os will be somewhere between these two extremes. The delay calculator software will calculate the correct value for each I/O used. All parameters assume the cell register is the closest one to the IOB. XC6200 IOB Switching Characteristic Guidelines Speed Grade: Symbol Parameter -2 Best I/O Min Max Worst I/O Min Max INPUT Pad to Neighbor data Pad to L4 Fastlane Pad to L4 Fastlane with delay OUTPUT Neighbor data to Output (fast) TOPF TOPS Neighbor data to Output (slew rate limited) TTSHZ 3-state to Pad begin hi-Z (slew rate independent) TTSONF 3-state to Pad active and valid (fast) TTSONS 3-state to Pad active and valid (slew rate limited) TPID TPID4 TPDID4 Units 4 5 13 ns ns ns 4 8 5 5.2 9 ns ns ns ns ns Advance Notes: As the parameters vary between I/Os, values are given for best and worst I/Os. The parameters for other I/Os will be somewhere between these two extremes. The delay calculator software will calculate the correct value for each I/O used. Typical loading values are used. June 1, 1996 (Version 1.0) 4- 277 XC6200 Field Programmable Gate Arrays XC6200 Internal Routing Delays Speed Grade: Symbol TFN TNN TMagic TL4 TL16 TL64 Parameter Function Output to Neighbor Route Neighbor In to Neighbor Out Route X2/X3 to Magic Out Length-4 Fastlane delay Length-16 Fastlane delay Chip-Length Fastlane delay -2 Min Max 1 1.5 2.5 2 2.5 5 Units ns ns ns ns ns ns Advance Notes: Delays vary depending on direction. Worst case figures are given here. The delay calculator software will calculate the correct delay for each direction. Typical loading values are used. XC6200 CPU Interface Timing Speed Grade: 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol TsuCS ThCS TsuRdWr ThRdWr TsuA ThA TsuD ThD TWC TRC TCKD TCKDZ TCSDZ Parameter CS set up before Clock1 CS hold after Clock1 RdWr set up before Clock RdWr hold after Clock Address Bus set up before Clock Address Bus hold after Clock Data Bus set up before Clock Data Bus hold after Clock Write cycle time2 Read cycle time2 Clock to Valid Data Clock to Data high impedance3 CS to Data high impedance3 -2 Min 6 0 6 0 6 0 6 0 40 40 Max 8 9 9 Units ns ns ns ns ns ns ns ns ns ns ns ns ns Advance Notes: 1. CS must be correctly sampled as a `0' at the start of the cycle (t1) and sampled as a `1' at the end of the cycle (t2). Other signals only require to be correctly sampled at t1. 2. The minimum time for a read or write cycle is two CPU clock periods, although the cycles shown do not start and finish at the start of a clock period. 3. Data is removed from the bus TCKDZ after t3 unless CS is still asserted at this time. In this case, data is removed from the bus asynchronously TCSDZ after CS goes high. 4- 278 June 1, 1996 (Version 1.0) GClk 3 tCG 1 tDC 4 tGC 2 tCD SEClk SEData D7 D6 D0 A15 A14 A13 D4 D3 D2 1st Data Word Synchronization Byte D1 D5 A12 A11 A10 A9 A8 A7 A6 A5 A4 D25 D24 D23 D22 1st Address Word Write Data Word 1 A3 A2 A1 A0 D31 D30 D29 D28 D27 D26 2nd Data Word Figure 26: Serial Configuration Timing VTEST R1 Device Output Device Input Rise and Fall Times < 3ns Test Point R2 CL Figure 27: AC Load Circuit June 1, 1996 (Version 1.0) 4- 279 XC6200 Field Programmable Gate Arrays 9 tWC GClk 2 thCS 1 tsuCS CS 4 thRdWr RdWr 3 tsuRdWr 6 thA A 5 tsuA 8 thD D 7 tsuD t2 t1 Write Cycle t3 Extended Write Cycle Figure 28: Configuration Memory Write Cycles 4- 280 June 1, 1996 (Version 1.0) 10 tRC GClk 2 thCS 1 tsuCS CS 4 thRdWr RdWr 3 tsuRdWr 6 thA A 5 tsuA 12 tCKDZ 13 tCSDZ 11 tCKD D t2 t1 Read Cycle t3 Extended Read Cycle Figure 29: Configuration Memory Read Cycles June 1, 1996 (Version 1.0) 4- 281 XC6200 Field Programmable Gate Arrays XC6200 Pinout Tables XC6216 Pinouts - West Side Pin Description D0/W1(2) GND W14 NC D1/W3 W16 D2/W5 W18 D3/W7 NC NC NC NC W20 D4/W9 W22 W24 W26 D5/W11 NC NC GND W28 W30 W32 D6/W13 VCC D16/W33 W34 GND NC NC NC NC D7/W15 D17/W35 W36 D18/W37 D8/W17 W38 PQ240 60 59 58 57(1) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PG299 C18 A19 A20 C17(1) D16 E15 B18 B17 C16 D15(1) A18(1) E14 C15 B16 D14 A17 C14 E13(1) B15(1) A15 D13 B14 C13 A14 A16 B13 E12 D12(1) C12(1) A13(1) B12(1) A12 D11 E11 C11 B11 B10 Pin Description VCC GND D19/W39 W40 D9/W19 D20/W41 W42 D21/W43 D10/W21 W44 W46 D22/W45 GND W48 W50 VCC D24/W49 D11/W23 D23/W47 D25/W51 GND W52 W54 W56 D12/W25 W58 D26/W53 D27/W55 D13/W27 W60 W62 NC NC D28/W57 D14/W29 D29/W59 D15/W31 D30/W61 D31/W63 GND PQ240 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PG299 A11 A10 C10 D10 A9 E10 B9 C9 A8 B8 D9 A7 E9 C8 A6 B7 C7 D8 B6 A5 B5 E8 C6 D7 A4 C5 B4 E7 D6 A3 C4 D5 E6 B3 B2 D4 B1 Notes: 1. Pin not connected. 2. Pins with a dual function have the `Control' signal shown first. See section "Input/Output Blocks (IOBs)" on page 261 for details. 4- 282 June 1, 1996 (Version 1.0) XC6216 Pinouts - South Side Pin Description VCC RdWr/S1 CS/S3 W12/S0 OE/S5 W10/S2 Reset/S7 W8/S4 NC NC W6/S6 W4/S8 W2/S10 W0/S12 S14 S16 S18 S20 S22 S24 GND S26 S33 Serial/S9 Wait/S11 VCC S28 S35 GND S30 S32 S34 S36 GClk/S13 S38 GClr/S15 S37 S40 S39 VCC Note: PQ240 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PG299 B20 D17 B19 C19 F16 E17 D18 C20 F17 G16 D19 E18 D20 G17 F18 H16 E19 F19 E20 H17 G18 G19 H18 F20 J16 G20 J17 H19 H20 J18 J19 K16 J20 K17 K18 K19 L20 Pin Description GND G1/S17 G2/S19 S42 S41 S44 S43 S46 S48 E0/S50 E2/S52 GND E4/S54 S45 VCC S21 SEData/S23 E6/S56 S47 GND NC NC E8/S58 S49 S51 S53 S55 S57 E10/S60 E12/S62 NC NC SECE/S25 SEReset/S27 S59 S61 SEClk/S29 ConfigOK/S31 GND S63 PQ240 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PG299 K20 L19 L18 L16 L17 M20 M19 N20 M18 M17 M16 N19 P20 T20 N18 P19 N17 R19 R20 N161 P181 U20 P17 T19 R18 P16 V20 R17 T18 U19 V19 R16 T17 U18 X20 W20 V18 1. Pin not connected. June 1, 1996 (Version 1.0) 4- 283 XC6200 Field Programmable Gate Arrays XC6216 Pinouts - East Side Pin Description VCC E14 A0/E1 E16 A1/E3 E18 A2/E5 E20 NC NC NC NC A3/E7 E22 E24 E26 A4/E9 E28 NC NC GND E30 E32 A5/E11 E33 VCC E34 E35 GND NC NC NC NC A6/E13 E36 E37 E38 A7/E15 E39 VCC Note: 4- 284 PQ240 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PG299 X19 U17 W19 W18 T15 U16 V17 X18 U151 T141 W17 V16 X17 U14 V15 T13 W161 W151 X16 U13 V14 W14 V13 X15 T12 X14 U12 W13 X13 V12 W12 T11 X12 U11 V11 W11 X10 Pin Description GND A8/E17 E40 A9/E19 E41 E42 E43 NC E44 E46 E48 GND A10/E21 E50 VCC E45 E52 A11/E23 E47 GND E54 E56 E58 E49 A12/E25 E51 E53 E55 NC NC A13/E27 E57 E60 E62 A14/E29 E59 A15/E31 E61 E63 VCC PQ240 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PG299 X11 W10 V10 T10 U10 X9 W9 X81 V9 U9 T9 W8 X7 X5 V8 W7 U8 W6 X6 T8 V7 X4 U7 W5 V6 T7 X3 U6 V5 W4 W3 T6 U5 V4 X1 V3 W1 1. Pin not connected. June 1, 1996 (Version 1.0) XC6216 Pinouts - North Side Pin Description VCC NC N1 N3 N0 N2 N4 N6 N8 N10 NC NC N5 N7 N12 N14 N16 N18 N20 N22 GND N24 N26 N33 N28 VCC N30 N32 N34 N36 N35 N9 GND N11 N38 N37 N40 N39 N13 VCC Note: PQ240 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 PG299 A2 C3 D3 E4 F5 C2 D2 E3 F4 C1 G5 F3 E2 G4 D1 G3 H5 F1 F2 H4 G2 H3 E1 G1 H2 J5 J4 J3 H1 J2 J1 K4 K5 K3 K2 K1 Pin Description GND N15 N17 N19 N42 N41 N44 GND N43 N21 N46 N48 N50 N52 VCC N23 N54 N45 N56 GND NC N47 N58 N49 N51 N53 N55 N57 N60 N62 NC NC N59 N25 N27 N61 N63 N29 GND N31 PQ240 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 PG299 L1 L2 L3 L4 M1 L5 M2 M3 N1 N2 M4 P1 M5 R1 N3 P2 P3 N4 T1 R21 T2 N5 R3 P4 U1 T3 U2 P5 R4 V1 U3 T4 R5 V2 W2 X2 U4 1. Pin not connected. June 1, 1996 (Version 1.0) 4- 285 XC6200 Field Programmable Gate Arrays Product Availability Devices are available in small and large packages. The small packages are useful where board area is at a premium and the design can make use of the wireless I/O parallel CPU interface to determine the state of internal nodes. The large package options give a very high user programmable I/O count where this is a prime requirement. The available packaging options for the XC6216 are summarized in Table 6. (These options are advance information and subject to change. Please confirm availability with Xilinx. Signal pins are all the non-supply pins that drive into the array or control circuitry. Some of these pins are shared between control signals and user I/O. The un-shared user I/Os do not share a pin with a control signal. The number of user I/Os available will be somewhere between the number 4- 286 of signal pins and the number of un-shared I/Os, depending on how many of the FPGA control signals are actually required. For example, if only an 8-bit data bus and no serial interface were required, the number of user I/Os would go up by 24+6=30 in a PGA299 package. Table 6: XC6216 Package Options Package Pins Signal Pins PLCC PQFP PGA 84 240 299 68 199 242 Max Data Bus Pins 16 32 32 Unshared User I/O 22 137 180 June 1, 1996 (Version 1.0) XC3000 Series Table of Contents XC3000 Series Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Configuration Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Readback Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General XC3000 Series Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unrestricted User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 44-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 64-Pin Plastic VQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 100-Pin QFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 144-Pin Plastic TQFP Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 160-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 176-Pin TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series 208-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289 4-289 4-290 4-291 4-291 4-292 4-294 4-295 4-296 4-296 4-300 4-302 4-303 4-304 4-304 4-306 4-307 4-307 4-308 4-310 4-310 4-312 4-314 4-316 4-318 4-319 4-320 4-321 4-321 4-322 4-322 4-323 4-323 4-323 4-324 4-325 4-326 4-327 4-328 4-329 4-330 4-331 4-332 4-333 4-334 4-335 4-336 4-337 4-287 XC3000 Series Table of Contents XC3195A PQ208 and PG223 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-338 Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-339 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-340 XC3000A Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341 4-341 4-342 4-342 4-342 4-343 4-343 4-344 4-346 4-348 4-348 XC3000L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349 4-349 4-350 4-350 4-350 4-351 4-351 4-352 4-354 4-356 4-356 XC3100A Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357 4-357 4-358 4-358 4-358 4-359 4-359 4-360 4-362 4-364 4-364 XC3100L Field Programmable Gate Arrays Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3100L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-288 4-365 4-365 4-366 4-366 4-366 4-367 4-367 4-368 4-370 4-372 4-372 XC3000 Series Field Programmable Gate Arrays June 1, 1996 (Version 2.0) Product Description Features * * * * * * * * Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 9 to 1.5 ns - System clock speeds over 80 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L XC3064A, 3064L, 3164A XC3090A, 3090L, 3190A, 3190L XC3195A June 1, 1996 (Version 2.0) Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 Description XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, userprogrammable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in Figure 2. The XACTstep development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program. The FPGA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package. The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades. Typical Gate CLBs Range 1,000 - 1,500 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 Complete XACTstep Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization - Timing calculator - Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others 64 100 144 224 320 484 Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22 User I/Os Flip-Flops Max 64 80 96 120 144 176 256 360 480 688 928 1,320 Horizontal Longlines 16 20 24 32 40 44 Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984 4-289 XC3000 Series Field Programmable Gate Arrays XC3000 Series Overview Introduced in 1987/88, the XC3000 series is the industry's most successful family of FPGAs, with over 10 million devices shipped. In 1992/93, Xilinx introduced three additional families, offering more speed, functionality, and a new supply-voltage option. There are now four distinct family groupings within the XC3000 Series of FPGA devices, with emphasis on those listed below: * * * * XC3000A Family XC3000L Family XC3100A Family XC3100L Family All six families share a common architecture, development software, design and programming methodology, and also common package pin-outs. An extensive Product Description covers these common aspects. The much shorter individual Product Specifications then provide detailed parametric information for the XC3000A, XC3000L, XC3100A, and XC3100L product families. (The XC3000 and XC3100 families are not recommended for new designs, and their individual product specifications are not included in this book.) Here is a simple overview of those XC3000 products currently emphasized: * * * XC3000A Family -- The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements. The ease-of-use of the XC3000A family makes it the obvious choice for all new designs that do not require the speed of the XC3100A or the 3-V operation of the XC3000L. XC3000L Family -- The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications. XC3100A Family -- The XC3100A is a performanceoptimized relative of the XC3000A family. While both families are bitstream and footprint compatible, the 4-290 * XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A. The XC3100A is best suited for designs that require the highest clock speed or the shortest net delays. XC3100L Family -- The XC3100L is identical in architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V. Figure 1 illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and, coming soon, increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100A family offers substantially higher speed and higher density with the XC3195A. nality Functio 0A XC310 00L 0 XC310XC31 0A XC300 0L XC300 Speed ) 195A (XC3 Gate city Capa X7068 Figure 1: XC3000 FPGA Families June 1, 1996 (Version 2.0) Detailed Functional Description bitstream used to configure the device. The memory loading process is independent of the user logic functions. The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Configurable Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI packages. Configuration Memory The static memory cell used for the configuration memory in the Field Programmable Gate Array has been designed specifically for high reliability and noise immunity. Integrity of the device configuration memory based on this design is assured even under adverse conditions. As shown in Figure 3, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration and only read during readback. During normal operation, the cell provides continuous control and the pass transistor is off and does not affect cell stability. This is quite different from the operation of conventional memory devices, in which the cells are frequently read and rewritten. The block logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors. These FPGA functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the device at power-up and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive configuration. Program data may be either bit serial or byte parallel. The XACTstep development system generates the configuration program PWR P9 P8 P7 P6 P5 P4 P3 P2 GND DN I/O Blocks P11 3-State Buffers With Access to Horizontal Long Lines Configurable Logic Blocks TCL KIN AA AB AC AD P12 Interconnect Area BA U61 BB Frame Pointer P13 Configuration Memory X3241 Figure 2: Field Programmable Gate Array Structure. It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources. These are all controlled by the distributed array of configuration program memory cells. June 1, 1996 (Version 2.0) 4-291 XC3000 Series Field Programmable Gate Arrays Q Q Read or Write testing, no soft errors have been observed even in the presence of very high doses of alpha radiation. Configuration Control The method of loading the configuration data is selectable. Two methods use serial data, while three use byte-wide data. The internal configuration logic utilizes framing information, embedded in the program data by the XACTstep development system, to direct memory-cell loading. The serial-data framing and length-count preamble provide programming compatibility for mixes of various FPGA device devices in a synchronous, serial, daisy-chain fashion. Data X5382 Figure 3: Static Configuration Memory Cell. It is loaded with one bit of configuration program and controls one program selection in the Field Programmable Gate Array. I/O Block Each user-configurable IOB shown in Figure 4, provides an interface between the external package pin of the device and the internal user logic. Each IOB includes both registered and direct input paths. Each IOB provides a programmable 3-state output buffer, which may be driven by a registered or direct output signal. Configuration options allow each IOB an inversion, a controlled slew rate and a high impedance pull-up. Each input circuit also provides input clamping diodes to provide electrostatic protection, and circuits to inhibit latch-up produced by input currents. The memory cell outputs Q and Q use ground and VCC levels and provide continuous, direct control. The additional capacitive load together with the absence of address decoding and sense amplifiers provide high stability to the cell. Due to the structure of the configuration memory cells, they are not affected by extreme power-supply excursions or very high levels of alpha particle radiation. In reliability Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK IK (GLOBAL RESET) CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 Figure 4: Input/Output Block. Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds. 4-292 June 1, 1996 (Version 2.0) The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to be compatible with either TTL or CMOS levels. The buffered input signal drives the data input of a storage element, which may be configured as either a flip-flop or a latch. The clocking polarity (rising/falling edge-triggered flip-flop, High/Low transparent latch) is programmable for each of the two clock lines on each of the four die edges. Note that a clock line driving a rising edge-triggered flip-flop makes any latch driven by the same line on the same edge Low-level transparent and vice versa (falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however, are positive edge-triggered flip-flops or High transparent latches. When one clock line must drive flip-flops as well as latches, it is necessary to compensate for the difference in clocking polarities with an additional inverter either in the flip-flop clock input or the latch-enable input. I/O storage elements are reset during configuration or by the activeLow chip RESET input. Both direct input (from IOB pin I) and registered input (from IOB pin Q) signals are available for interconnect. For reliable operation, inputs should have transition times of less than 100 ns and should not be left floating. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor, which may be selected by the program to provide a constant High for otherwise undriven package pins. Although the Field Programmable Gate Array provides circuitry to provide input protection for electrostatic discharge, normal CMOS handling precautions should be observed. Flip-flop loop delays for the IOB and logic-block flip-flops are short, providing good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition that can result from assertion of the clock during data transitions. Because of the short-loop-delay characteristic in the Field Programmable Gate Array, the IOB flip-flops can be used to synchronize external signals applied to the device. Once synchronized in the IOB, the signals can be used internally without further consideration of their clock relative timing, except as it applies to the internal logic and routing-path delays. IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high fan-out CMOS or TTL- com- June 1, 1996 (Version 2.0) patible signal levels (8 mA in the XC3100A family). The network driving IOB pin O becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB) pin T can control output activity. An open-drain output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer output is enabled only for a Low. Configuration program bits for each IOB control features such as optional output register, logic signal inversion, and 3-state and slew-rate control of the output. The program-controlled memory cells of Figure 4 control the following options. * * * * * Logic inversion of the output is controlled by one configuration program bit per IOB. Logic 3-state control of each IOB output buffer is determined by the states of configuration program bits that turn the buffer on, or off, or select the output buffer 3-state control interconnection (IOB pin T). When this IOB output control signal is High, a logic one, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is Low, a logic zero, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control-logic sense (output enable) is controlled by an additional configuration program bit. Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked flip-flop. The clock source may be supplied (IOB pin OK) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive-load peak currents of non-critical outputs and minimize system noise. An internal high-impedance pull-up resistor (active by default) prevents unconnected inputs from floating. Summary of I/O Options * * Inputs - Direct - Flip-flop/latch - CMOS/TTL threshold (chip inputs) - Pull-up resistor/open circuit Outputs - Direct/registered - Inverted/not - 3-state/on/off - Full speed/slew limited - 3-state/output enable (inverse) 4-293 XC3000 Series Field Programmable Gate Arrays Configurable Logic Block resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks. The array of CLBs provides the functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8 rows and 8 columns. The XACTstep development system is used to compile the configuration data which is to be loaded into the internal configuration memory to define the operation and interconnection of each block. User definition of CLBs and their interconnecting networks may be done by automatic translation from a schematic-capture logic diagram or optionally by installing library or user macros. Data input for either flip-flop within a CLB is supplied from the function F or G outputs of the combinatorial logic, or the block input, DI. Both flip-flops in each CLB share the asynchronous RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops' present states and inhibits response to the data-in or combinatorial function inputs on a CLB. The user may enable these control inputs and select their sources. The user may also select the clock net input (K), as well as its active sense within each CLB. This programmable inversion eliminates the need to route both phases of a clock signal throughout the device. Flexible routing allows use of common or individual CLB clocking. Each CLB has a combinatorial logic section, two flip-flops, and an internal control section. See Figure 5. There are: five logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an enable clock (EC). All may be driven from the interconnect DI DATA IN 0 MUX F D Q 1 DIN G QX RD QX X A F F B LOGIC VARIABLES C D COMBINATORIAL FUNCTION E CLB OUTPUTS G G QY Y QY F DIN G 0 MUX D Q 1 EC ENABLE CLOCK RD 1 (ENABLE) K CLOCK DIRECT RESET RD 0 (INHIBIT) (GLOBAL RESET) X3032 Figure 5: Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of function. It has the following: - five logic variable inputs A, B, C, D, and E - a direct data in DI - an enable clock EC - a clock (invertible) K - an asynchronous direct RESET RD - two outputs X and Y 4-294 June 1, 1996 (Version 2.0) The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal block flip-flops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function generated and is spike free for single input variable changes. This technique can generate two independent logic functions of up to four variables each as shown in Figure 6a, or a single function of five variables as shown in Figure 6b, or some functions of seven variables as shown in Figure 6c. Figure 7 shows a modulo-8 binary counter with parallel enable. It uses one CLB of each type. The partial functions of six or seven variables are implemented using the input variable (E) to dynamically select between two functions of four different variables. For the two functions of four variables each, the independent results (F and G) may be used as data inputs to either flipflop or either logic block output. For the single function of five variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the interchange of CLB outputs to optimize routing efficiencies of the networks interconnecting the CLBs and IOBs. Programmable Interconnect Programmable-interconnection resources in the Field Programmable Gate Array provide routing paths to connect inputs and outputs of the IOBs and CLBs into logic networks. Interconnections between blocks are composed of a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins. Figure 8 is an example of a routed net. The XACTstep development system provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for design optimization. The inputs of the CLBs or IOBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the switch connections to block inputs are unidirectional, as are block outputs, they are usable only for block input connection and not for routing. Figure 9 illustrates routing access to logic block input variables, control inputs and block outputs. Three types of metal resources are provided to accommodate various network interconnect requirements. * * * General Purpose Interconnect Direct Connection Longlines (multiplexed busses and wide AND gates June 1, 1996 (Version 2.0) A B QX QY Any Function of Up to 4 Variables F QY Any Function of Up to 4 Variables G C D E A B QX C D E 5a A B QX F QY Any Function of 5 Variables G C D E 5b A B QX QY C Any Function of Up to 4 Variables D F M U X A B G QX QY Any Function of Up to 4 Variables C D E 5c FGM Mode X5442 Figure 6: Combinational Logic Options 6a. Combinatorial Logic Option FG generates two functions of four variables each. One variable, A, must be common to both functions. The second and third variable can be any choice of B, C, QX and QY. The fourth variable can be any choice of D or E. 6b. Combinatorial Logic Option F generates any function of five variables: A, D, E and two choices out of B, C, QX, QY. 6c. Combinatorial Logic Option FGM allows variable E to select between two functions of four variables: Both have common inputs A and D and any choice out of B, C, QX and QY for the remaining two variables. Option 3 can then implement some functions of six or seven variables. 4-295 XC3000 Series Field Programmable Gate Arrays Count Enable Parallel Enable Clock Terminal Count Dual Function of 4 Variables D Q Q0 D0 FG Mode D Q Q1 D1 Function of 5 Variables F Mode D Q Q2 D2 Function of 6 Variables FGM Mode Figure 8: An XACT Design Editor view of routing resources used to form a typical interconnection network from CLB GA. X5383 Figure 7: C8BCP Macro. The C8BCP macro (modulo-8 binary counter with parallel enable and clock enable) uses one combinatorial logic block of each option. General Purpose Interconnect General purpose interconnect, as shown in Figure 10, consists of a grid of five horizontal and five vertical metal segments located between the rows and columns of logic and IOBs. Each segment is the height or width of a logic block. Switching matrices join the ends of these segments and allow programmed interconnections between the metal grid segments of adjoining rows and columns. The switches of an unprogrammed device are all non-conducting. The connections through the switch matrix may be established by the automatic routing or by using Editnet to select the desired pairs of matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 11 and may be highlighted by the use of the Show-Matrix command in the XACT Design Editor. Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. The interconnect buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above 4-296 and to the right and may be highlighted by the use of the Show BIDI command in the XACT Design Editor. The other PIPs adjacent to the matrices are accessed to or from Longlines. The development system automatically defines the buffer direction based on the location of the interconnection network source. The delay calculator of the XACTstep development system automatically calculates and displays the block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worstcase delay model is provided by an XACT option. Direct Interconnect Direct interconnect, shown in Figure 12, provides the most efficient implementation of networks between adjacent CLBs or I/O Blocks. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general interconnect resources. For each CLB, the X output may be connected directly to the B input of the CLB immediately to its right and to the C input of the CLB to its left. The Y output can use direct interconnect to drive the D input of the block immediately above and the A input of the block below. Direct interconnect should be used to maximize the speed of high-performance portions of logic. Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the die. The right edge provides additional direct connects from CLB outputs to adjacent IOBs. Direct interconnections of IOBs with CLBs are shown in Figure 13. June 1, 1996 (Version 2.0) Figure 9: XACT Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. This is indicated on the XACT Design Editor status line: ND is a nondirectional interconnection. D:H->V is a PIP that drives from a horizontal to a vertical line. D:V->H is a PIP that drives from a vertical to a horizontal line. D:C->T is a "T" PIP that drives from a cross of a T to the tail. D:CW is a corner PIP that drives in the clockwise direction. P0 indicates the PIP is non-conducting, P1 is on. June 1, 1996 (Version 2.0) 4-297 XC3000 Series Field Programmable Gate Arrays Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for CLB and IOB inputs and outputs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 12: CLB X and Y Outputs. The X and Y outputs of each CLB have single contact, direct access to inputs of adjacent CLBs 383 16 Figure 11: Switch Matrix Interconnection Options for Each Pin. Switch matrices on the edges are different. Use Show Matrix menu option in the XACT Design Editor. 4-298 June 1, 1996 (Version 2.0) Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: Global Buffer Inerconnect Alternate Buffer Direct Input XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. June 1, 1996 (Version 2.0) 4-299 XC3000 Series Field Programmable Gate Arrays Longlines The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical Longlines, and each interconnection row has two horizontal Longlines. Two additional Longlines are located adjacent to the outer sets of switching matrices. In devices larger than the XC3020A, two vertical Longlines in each column are connectable halflength lines. On the XC3020A, only the outer Longlines are connectable half-length lines. Longlines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low skew control or clock line within each column of logic blocks. Interconnections of these Longlines are shown in Figure 15. Isolation buffers are provided at each input to a Longline and are enabled automatically by the development system when a connection is made. Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA. 4-300 June 1, 1996 (Version 2.0) Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Threestate buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two nonclock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as connectable half-length lines. VCC VCC Z = DA * DB * DC * ... * DN (LOW) DA DB DC DN X3036 Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low. Z = DA * A + DB * B + DC * C + ... + DN * N WEAK KEEPER CIRCUIT DA DB DC DN A B C N X1741A Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal. June 1, 1996 (Version 2.0) 4-301 XC3000 Series Field Programmable Gate Arrays of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See Figure 16. The user is required to avoid contention which can result from multiple drivers with opposing logic levels. Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND function. A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables the buffer to drive the Longline Low. See Figure 17. Pull-up resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals drive the 3-state control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention through multiple active buffers of conflicting levels on a common line. Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the previous logic level when the line is not driven by an active buffer or a pull-up resistor. Figure 18 shows 3-state buffers, Longlines and pull-up resistors. A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all of the IOBs and CLBs. Configuration bits for the K input to each logic block can select this global line or another routing resource as the clock source for its flip-flops. This net may also be programmed to drive the die edge clock lines for IOB use. An enhanced speed, CMOS threshold, direct access to this buffer is available at the second pad from the top of the left die edge. A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to a vertical Longline in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buffer's Longlines can be selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the third pad from the bottom of the right die edge. Internal Busses A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation BIDIRECTIONAL INTERCONNECT BUFFERS 3 VERTICAL LONG LINES PER COLUMN GLOBAL NET I/O CLOCKS GG GH P48 HORIZONTAL LONG LINE PULL-UP RESISTOR HORIZONTAL LONG LINE OSCILLATOR AMPLIFIER OUTPUT P47 HG BCL KIN HH DIRECTINPUT OF P47 TO AUXILIARY BUFFER CRYSTAL OSCILLATOR BUFFER 3-STATE INPUT OS C 3-STATE CONTROL P46 .l .lk .q .ck .Q D P G M 3-STATE BUFFER ALTERNATE BUFFER P40 P41 P42 P43 RST X1245 Figure 18: XACT Design Editor. An extra large view of possible interconnections in the lower right corner of the XC3020A. 4-302 June 1, 1996 (Version 2.0) Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an onchip crystal oscillator. It is associated with the auxiliary buffer in the lower right corner of the die. When the oscillator is configured by MakeBits and connected as a signal source, two special user IOBs are also configured to connect the oscillator amplifier with external crystal oscillator components as shown in Figure 19. A divide by two option is available to assure symmetry. The oscillator circuit becomes active early in the configuration process to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. In Figure 19 the feedback resistor R1, between the output and input, biases the amplifier at threshold. The inversion of the amplifier, together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the D Pierce oscillator. A series resistor R2 may be included to add to the amplifier output impedance when needed for phase-shift control, crystal resistance matching, or to limit the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The amplifier is designed to be used from 1 MHz to about one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across C2, turning this parallel resonant circuit to double the fundamental crystal frequency, i.e., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O. Q Internal Alternate Clock Buffer External XTAL1 XTAL2 (IN) R1 Suggested Component Values R1 0.5 - 1 M R2 0 - 1 k (may be required for low frequency, phase shift and/or compensation level for crystal Q) C1, C2 10 - 40 pF Y1 1 - 20 MHz AT-cut parallel resonant XTAL 1 (OUT) XTAL 2 (IN) 44 PIN 68 PIN PLCC PLCC 30 47 26 43 84 PIN PGA PLCC J11 57 L11 53 100 PIN CQFP PQFP 67 82 61 76 R2 Y1 C1 132 PIN PGA P13 M13 C2 160 PIN 164 PIN CQFP PQFP 105 82 99 76 175 PIN 176 PIN 208 PIN PGA TQFP PQFP T14 91 110 P15 85 100 X7064 Figure 19: Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional divide-by-two mode is available to assure symmetry. June 1, 1996 (Version 2.0) 4-303 XC3000 Series Field Programmable Gate Arrays Configuration Initialization Phase An internal power-on-reset circuit is triggered when power is applied. When VCC reaches the voltage at which portions of the FPGA device begin to operate (nominally 2.5 to 3 V), the programmable I/O output buffers are 3-stated and a high-impedance pull-up resistor is provided for the user I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the power-down mode is inhibited. The Initialization state time-out (about 11 to 33 ms) is determined by a 14-bit counter driven by a selfgenerated internal timer. This nominal 1-MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices are available as determined by the input levels of three mode pins; M0, M1 and M2. Table 1: Configuration Mode Choices M0 M1 M2 CCLK 0 0 0 output 0 0 1 output 0 1 0 -- 0 1 1 output 1 0 0 -- 1 0 1 output 1 1 0 -- 1 1 1 input Mode Master Master reserved Master reserved Peripheral reserved Slave Data Bit Serial Byte Wide Addr. = 0000 up -- Byte Wide Addr. = FFFF down -- Byte Wide -- Bit Serial In Master configuration modes, the device becomes the source of the Configuration Clock (CCLK). The beginning of configuration of devices using Peripheral or Slave modes must be delayed long enough for their initialization to be completed. An FPGA with mode lines selecting a Master configuration mode extends its initialization state using four times the delay (43 to 130 ms) to assure that all daisychained slave devices, which it may be driving, will be ready even if the master is very fast, and the slave(s) very slow. Figure 20 shows the state sequences. At the end of Initialization, the device enters the Clear state where it clears the configuration memory. The active Low, opendrain initialization signal INIT indicates when the Initialization and Clear states are complete. The FPGA tests for the absence of an external active Low RESET before it makes a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a configuration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the FPGA will initiate an abort, returning to the Clear state to clear the partially loaded configuration memory words. The FPGA will then resample RESET and the mode lines before re-entering the Configuration state. A re-program is initiated.when a configured XC3000 series device senses a High-to-Low transition and subsequent >6 s Low level on the DONE/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low transi- All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low INIT Output = Low Power Down No HDC, LDC or Pull-Up PWRDWN Inactive Initialization Power-On Time Delay PWRDWN Active Active RESET Clear Configuration Memory RESET Active No Test Mode Pins Configuration Program Mode Start-Up Active RESET Operates on User Logic Low on DONE/PROGRAM and RESET Power-On Delay is 214 Cycles for Non-Master Mode--11 to 33 ms 216 Cycles for Master Mode--43 to 130 ms Operational Mode Clear Is ~ 200 Cycles for the XC3020A--130 to 400 s ~ 250 Cycles for the XC3030A--165 to 500 s ~ 290 Cycles for the XC3042A--195 to 580 s ~ 330 Cycles for the XC3064A--220 to 660 s ~ 375 Cycles for the XC3090A--250 to 750 s X3399 Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram. 4-304 June 1, 1996 (Version 2.0) tion and subsequent >6 s Low time on the RESET package pin. The device returns to the Clear state where the configuration memory is cleared and mode lines re-sampled, as for an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle. Length count control allows a system of multiple Field Programmable Gate Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program generated by the MakePROM program of the XACTstep development system begins with a preamble of 11111111 0010 < 24-Bit Length Count > 1111 0 111 0 111 0 111 . . . . . . . . . 0 111 0 111 1111 111111110010 followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data framing is shown in Figure 21. All FPGAs connected in series read and shift preamble and length count in on positive and out on negative configuration clock edges. A device which has received the preamble and length count then presents a High Data Out until it has intercepted the appropriate number of data frames. When the configuration program memory of an FPGA is full and the length count does not yet compare, the device shifts any additional data through, as it did for preamble and length count. When the F{GA configuration memory is full and the length count --Dummy Bits* --Preamble Code --Configuration Program Length --Dummy Bits (4 Bits Minimum) Header For XC3120 197 Configuration Data Frames Program Data (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Repeated for Each Logic Cell Array in a Daisy Chain Postamble Code (4 Bits Minimum) *The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits Device Gates CLBs Row x Col IOBs Flip-flops Horizontal Longlines TBUFs/Horizontal LL Bits per Frame (including1 start and 3 stop bits) Frames Program Data = Bits x Frames + 4 bits (excludes header) PROM size (bits) = Program Data + 40-bit Header X5300 XC3020A XC3020L XC3120 XC3120A 1,000 to 1,500 64 (8 x 8) 64 256 16 9 75 XC3030A XC3030L XC3130A 1,500 to 2,000 100 (10 x 10) 80 360 20 11 92 XC3042A XC3042L XC3142A XC3142L 2,000 to 3,000 144 (12 x 12) 96 480 24 13 108 XC3064A XC3064L XC3164A 3,500 to 4,500 224 (16 x 14) 120 688 32 15 140 XC3090A XC3090L XC3190A XC3190L 5,000 to 6,000 320 (20 x 16) 144 928 40 17 172 XC3195A 6,500 to 7,500 484 (22 x 22) 176 1,320 44 23 188 197 14,779 241 22,176 285 30,784 329 46,064 373 64,160 505 94,944 14,819 22,216 30,824 46,104 64,200 94,984 Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data frames generated by the XACTstep Development System. The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device) rounded up to multiple of 8] - (2 K 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached. June 1, 1996 (Version 2.0) 4-305 XC3000 Series Field Programmable Gate Arrays compares, the device will execute a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected in MakeBits, the internal user-logic RESET is released either one clock cycle before or after the I/O pins become active. A similar timing selection is programmable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired ANDing. The High During Configuration (HDC) and Low During Configuration (LDC) are two user I/O pins which are driven active while an FPGA is in its Initialization, Clear or Configure states. They and DONE/PROG provide signals for control of external logic signals such as RESET, bus enable or PROM enable during configuration. For parallel Master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At power-up, all inputs have TTL thresholds and can change to CMOS thresholds at the completion of configuration if the user has selected CMOS thresholds. The threshold of PWRDWN and the direct clock inputs are fixed at a CMOS level. If the crystal oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is connected to the internal circuitry. Configuration Data Configuration data to define the function and interconnection within a Field Programmable Gate Array is loaded from an external storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of the required data are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to be used. See Table 1. The data may be either bit-serial or byte-parallel, depending on the configuration mode. The different FPGAs have different sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use compatible configuration formats. For the XC3020A, configuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header. See Figure 22. The specific data format for each device is produced by the MakeBits command of the development system and one or more of these files can then be combined and appended to a length count preamble and be transformed into a PROM format file by the MakePROM command of the XACTstep development system. A compatibility exception precludes the use of an XC2000-series device as the master for XC3000-series devices if their DONE or RESET are programmed to occur after their outputs become active. The Tie Option of the MakeBits program defines output levels of unused blocks of a design and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic Postamble Last Frame Data Frame 12 24 4 3 4 3 STOP DIN Stop Preamble Length Count Data Start Bit Length Count* Start Bit The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated FPGA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and the result rounded up to a byte boundary. The length count is two less than the number of resulting bits. Weak Pull-Up PROGRAM Timing of the assertion of DONE and termination of the INTERNAL RESET may each be programmed to occur one cycle before or after the I/O outputs become active. Heavy lines indicate the default condition I/O Active DONE Internal Reset X5988 Figure 22: Configuration and Start-up of One or More FPGAs. 4-306 June 1, 1996 (Version 2.0) supply currents. If unused blocks are not sufficient to complete the tie, the Flagnet command of EditLCA can be used to indicate nets which must not be used to drive the remaining unused routing, as that might affect timing of user nets. Norestore will retain the results of tie for timing analysis with Querynet before Restore returns the design to the untied condition. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count. When configuration is initiated, a counter in the FPGA is set to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the device, it is internally assembled into a data word, which is then loaded in parallel into one word of the internal configuration memory array. The configuration loading process is complete when the current length count equals the loaded length count and the required configuration program data frames have been written. Internal user flip-flops are held Reset during configuration. Two user-programmable pins are defined in the unconfigured Field Programmable Gate Array. High During Configuration (HDC) and Low During Configuration (LDC) as well as DONE/PROG may be used as external control signals during configuration. In Master mode configurations it is convenient to use LDC as an active-Low EPROM Chip Enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MakeBits program allow timing choices of one clock earlier or later for the timing of the end of the internal logic RESET and the assertion of the DONE signal. The open-drain DONE/PROG output can be ANDtied with multiple devices and used as an active-High READY, an active-Low PROM enable or a RESET to other portions of the system. The state diagram of Figure 20 illustrates the configuration process. Configuration Modes Master Mode In Master mode, the FPGA automatically loads configuration data from an external memory device. There are three Master modes that use the internal timing source to supply the configuration clock (CCLK) to time the incoming data. Master Serial mode uses serial configuration data supplied to Data-in (DIN) from a synchronous serial source such as the Xilinx Serial Configuration PROM shown in Figure 23. Master Parallel Low and High modes automatically use parallel data supplied to the D0-D7 pins in response to the 16-bit address generated by the FPGA. Figure 25 shows an example of the parallel Master mode connections required. The HEX starting address is 0000 and increments for Master Low mode and it is FFFF and decrements for June 1, 1996 (Version 2.0) Master High mode. These two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory. Peripheral Mode Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor peripheral. Figure 27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two active low and one active high Chip Selects (CS0, CS1, CS2). The FPGA generates a configuration clock from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on Data Out (DOUT). A output High on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisychain of slave devices. Slave Serial Mode Slave Serial mode provides a simple interface for loading the Field Programmable Gate Array configuration as shown in Figure 29. Serial data is supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisy-chain configurations in which the data input is driven from the previous FPGA's data out, while the clock is supplied by a lead device in Master or Peripheral mode. Data may also be supplied by a processor or other special circuits. Daisy Chain The XACTstep development system is used to create a composite configuration for selected FPGAs including: a preamble, a length count for the total bitstream, multiple concatenated data programs and a postamble plus an additional fill bit per device in the serial chain. After loading and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration data frames while providing a High DOUT to possible down-stream devices as shown in Figure 25. Loading continues while the lead device has received its configuration program and the current length count has not reached the full value. The additional data is passed through the lead device and appears on the Data Out (DOUT) pin in serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output data and data in of down-stream FPGAs. Data is read in on DIN of slave devices by the positive edge of CCLK and shifted out the DOUT on the negative edge of CCLK. A parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM address rate, while a Peripheral mode device produces a burst of 8 CCLKs for each chip select and write-strobe cycle. The internal timing generator continues to operate for general timing and synchronization of inputs in all modes. 4-307 XC3000 Series Field Programmable Gate Arrays Special Configuration Functions The configuration data includes control over several special functions in addition to the normal user logic functions and interconnect. * * * * * * Input thresholds Readback disable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided by two Each of these functions is controlled by configuration data bits which are selected as part of the normal XACTstep development system bitstream generation process. Input Thresholds Prior to the completion of configuration all FPGA input thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRDWN input and direct clocks which always have a CMOS input. Prior to the completion of configuration the user I/O pins each have a high impedance pull-up. The configuration program can be used to enable the IOB pull-up resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of a Field Programmable Gate Array may be read back if it has been programmed with a bitstream in which the Readback option has been enabled. Readback may be used for verification of configuration and as a method of determining the state of internal logic nodes during debugging. There are three options in generating the configuration bitstream. * * * "Never" inhibits the Readback capability. "One-time," inhibits Readback after one Readback has been executed to verify the configuration. "On-command" allows unrestricted use of Readback. Readback is accomplished without the use of any of the user I/O pins; only M0, M1 and CCLK are used. The initiation of Readback is produced by a Low to High transition of the M0/RTRIG (Read Trigger) pin. The CCLK input must then be driven by external logic to read back the configuration data. The first three Low-to-High CCLK transitions clock out dummy data. The subsequent Low-to-High CCLK transitions shift the data frame information out on the M1/ RDATA (Read Data) pin. Note that the logic polarity is always inverted, a zero in configuration becomes a one in Readback, and vice versa. Note also that each Readback frame has one Start bit (read back as a one) but, unlike in configuration, each Readback frame has only one Stop bit (read back as a zero). The third leading dummy bit men- 4-308 tioned above can be considered the Start bit of the first frame. All data frames must be read back to complete the process and return the Mode Select and CCLK pins to their normal functions. Readback data includes the current state of each CLB flipflop, each input flip-flop or latch, and each device pad. These data are imbedded into unused configuration bit positions during Readback. This state information is used by the XACTstep development system In-Circuit Verifier to provide visibility into the internal operation of the logic while the system is operating. To readback a uniform time-sample of all storage elements, it may be necessary to inhibit the system clock. Reprogram To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGA internal timing generator. When reprogram begins, the user-programmable I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the Clear state and clears the configuration memory before it indicates `initialized'. Since this Clear operation uses chip-individual internal timing, the master might complete the Clear operation and then start configuration before the slave has completed the Clear operation. To avoid this problem, the slave INIT pins must be AND-wired and used to force a RESET on the master (see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls DONE/PROG Low. Once a stable request is recognized, the DONE/PROG pin is held Low until the new configuration has been completed. Even if the re-program request is externally held Low beyond the configuration period, the FPGA will begin operation upon completion of configuration. DONE Pull-up DONE/PROG is an open-drain I/O pin that indicates the FPGA is in the operational state. An optional internal pullup resistor can be enabled by the user of the XACT development system when MakeBits is executed. The DONE/ PROG pins of multiple FPGAs in a daisy-chain may be connected together to indicate all are DONE or to direct them all to reprogram. DONE Timing The timing of the DONE status signal can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This facilitates control of external functions such as a PROM enable or holding a system in a wait state. June 1, 1996 (Version 2.0) RESET Timing As with DONE timing, the timing of the release of the internal reset can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 22. This reset keeps all user programmable flip-flops and latches in a zero state during configuration. Crystal Oscillator Division A selection in the MakeBits program allows the user to incorporate a dedicated divide-by-two flip-flop between the crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency stability of a crystal oscillator is very good, the symmetry of its waveform can be affected by bias or feedback drive. Bitstream Error Checking Bitstream error checking protects against erroneous configuration. Each Xilinx FPGA bitstream consists of a 40-bit preamble, followed by a device-specific number of data frames. The number of bits per frame is also device-specific; however, each frame ends with three stop bits (111) followed by a start bit for the next frame (0). All devices in all XC3000 families start reading in a new frame when they find the first 0 after the end of the previous frame. XC3000 device does not check for the correct stop bits, but XC3000A/XC3100A/XC3000L and XC3100L devices check that the last three bits of any frame are actually 111. Under normal circumstances, all these FPGAs behave the same way; however, if the bitstream is corrupted, an XC3000 device will always start a new frame as soon as it finds the first 0 after the end of the previous frame, even if the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done, June 1, 1996 (Version 2.0) but with incorrect configuration and the possibility of internal contention. An XC3000A/XC3100A/XC3000L/XC3100L device starts any new frame only if the three preceding bits are all ones. If this check fails, it pulls INIT Low and stops the internal configuration, although the Master CCLK keeps running. The user must then start a new configuration by applying a >6 s Low level on RESET. This simple check does not protect against random bit errors, but it offers almost 100 percent protection against erroneous configuration files, defective configuration data sources, synchronization errors between configuration source and FPGA, or PC-board level defects, such as broken lines or solder-bridges. Reset Spike Protection A separate modification slows down the RESET input before configuration by using a two-stage shift register driven from the internal clock. It tolerates submicrosecond High spikes on RESET before configuration. The XC3000 master can be connected like an XC4000 master, but with its RESET input used instead of INIT. (On XC3000, INIT is output only). Soft Start-up After configuration, the outputs of all FPGAs in a daisychain become active simultaneously, as a result of the same CCLK edge. In the original XC3000/3100 devices, each output becomes active in either fast or slew-rate limited mode, depending on the way it is configured. This can lead to large ground-bounce signals. In XC3000A/ XC3000L/XC31000A/XC3100L devices, all outputs become active first in slew-rate limited mode, reducing the ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective configuration bit. 4-309 XC3000 Series Field Programmable Gate Arrays Configuration Timing This section describes the configuration modes in detail. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. This puts the next data bit on the SPROM data output, connected to the DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 M0 The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but LDC is then restricted to be a permanently High user output. Using DONE also avoids contention on DIN, provided the early DONE option is invoked. +5 V * DURING CONFIGURATION THE 5 k M2 PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER I/O. DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge. M1 PWRDWN TO DIN OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS DOUT M2 TO CCLK OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS HDC LDC GENERALPURPOSE USER I/O PINS INIT OTHER I/O PINS TO CCLK OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS * * * * * XC3000 FPGA DEVICE TO DIN OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS +5 V RESET RESET VCC DIN CCLK VPP DATA DATA CLK CLK SCP D/P CE INIT OE/RESET CEO CE CASCADED SERIAL MEMORY OE/RESET XC17xx (LOW RESETS THE XC17xx ADDRESS POINTER) X5989 Figure 23: Master Serial Mode Circuit Diagram 4-310 June 1, 1996 (Version 2.0) CCLK (Output) 2 TCKDS 1 TDSCK Serial Data In Serial DOUT (Output) n n+1 n-3 n-2 n+2 n-1 n X3223 CCLK Description Data In setup Data In hold 1 2 Symbol TDSCK CKDS Min 60 0 Max Units ns ns Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. 3. Master-serial-mode timing is based on slave-mode testing. Figure 24: Master Serial Mode Programming Switching Characteristics June 1, 1996 (Version 2.0) 4-311 XC3000 Series Field Programmable Gate Arrays Master Parallel Mode In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an internal * If Readback is * +5 V Activated, a 5-k Resistor is Required in Series With M1 5 k +5 V delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data, and also changes the EPROM address, until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next device in the daisy chain accepts data on the subsequent rising CCLK edge. * +5 V M0 M1PWRDWN M0 M1PWRDWN CCLK CCLK DOUT DIN HDC RCLK 5 k A14 LDC A13 A13 A12 A12 A11 A11 A10 A10 A9 A9 D7 A8 A8 D6 A7 A7 D7 D5 A6 A6 D6 D4 A5 A5 D5 D3 A4 A4 D4 D2 A3 A3 D3 D1 A2 A2 D2 D0 A1 A1 D1 A0 A0 D0 D/P OE ..... FPGA Master RESET INIT N.C. EPROM Other I/O Pins M2 GeneralPurpose User I/O Pins LDC Other I/O Pins INIT ... A14 Other I/O Pins FPGA Slave #n HDC ... HDC DOUT DIN ... A15 5 k CCLK M2 A15 GeneralPurpose User I/O Pins M0 M1PWRDWN DOUT FPGA Slave #1 M2 * +5 V GeneralPurpose User I/O Pins INIT D/P D/P RESET Reset Note: XC2000 Devices Do Not Have INIT to Hold Off a Master Device. Reset of a Master Device Should be Asserted by an External Timing Circuit to Allow for LCA CCLK Variations in Clear State Time. CE +5 V 8 Reprogram Open Collector 5 k Each System Reset X5990 Figure 25: Master Parallel Mode Circuit Diagram 4-312 June 1, 1996 (Version 2.0) A0-A15 (output) Address for Byte n Address for Byte n + 1 1 TRAC D0-D7 Byte 3 TRCD 2 TDRC RCLK (output) 7 CCLKs CCLK CCLK (output) DOUT (output) D6 D7 Byte n - 1 RCLK Description To address valid To data setup To data hold RCLK High RCLK Low 1 2 3 Symbol TRAC TDRC TRCD TRCH TRCL X5380 Min 0 60 0 600 4.0 Max 200 Units ns ns ns ns s Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements. Figure 26: Master Parallel Mode Programming Switching Characteristics June 1, 1996 (Version 2.0) 4-313 XC3000 Series Field Programmable Gate Arrays Peripheral Mode Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overflows the lead device) on the DOUT pin. when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. The length of the BUSY signal depends on the activity in the UART. If the shift register had been empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. The Ready/Busy output from the lead device acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered. +5 V CONTROL SIGNALS ADDRESS BUS DATA BUS * 8 M0 D0-7 5 k M1 PWR DWN D0-7 CCLK OPTIONAL DAISY-CHAINED FPGAs WITH DIFFERENT CONFIGURATIONS DOUT ... ADDRESS DECODE LOGIC * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 M2 CS0 HDC +5 V FPGA GENERALPURPOSE USER I/O PINS LDC CS1 CS2 ... OTHER I/O PINS RDY/BUSY WS INIT REPROGRAM OC D/P RESET X5991 Figure 27: Peripheral Mode Circuit Diagram 4-314 June 1, 1996 (Version 2.0) WRITE TO FPGA WS, CS0, CS1 CS2 1 TCA 2 TDC D0-D7 TCD 3 Valid CCLK 4 TWTRB TBUSY 6 RDY/BUSY DOUT D6 D7 D0 Previous Byte D1 D2 New Byte X5992 WRITE RDY Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end of WS 2 3 4 TDC TCD TWTRB 60 0 Earliest next WS after end of BUSY 5 TRBWT 0 BUSY Low time generated 6 TBUSY 2.5 1 Symbol TCA Min 100 Max 60 Units ns ns ns ns ns 9 CCLK periods Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration must be delayed until the INIT of all FPGAs is High. 3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the internal timing generator for CCLK. 4. CCLK and DOUT timing is tested in slave mode. 5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY. Figure 28: Peripheral Mode Programming Switching Characteristics June 1, 1996 (Version 2.0) 4-315 XC3000 Series Field Programmable Gate Arrays Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short set-up time before each rising CCLK edge. The lead device then presents the preamble data (and all data that over- flows the lead device) on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next device in the daisy-chain accepts data on the subsequent rising CCLK edge. +5 V * If Readback is Activated, a 5-k Resistor is Required in Series with M1 * M0 M1 PWRDWN Micro Computer 5 k STRB CCLK D0 DIN DOUT HDC D1 I/O Port D2 D3 Optional Daisy-Chained LCAs with Different Configurations M2 GeneralPurpose User I/O Pins LDC +5 V FPGA D4 D6 D7 RESET ... Other I/O Pins D5 D/P INIT RESET X5993 Figure 29: Slave Serial Mode Circuit Diagram 4-316 June 1, 1996 (Version 2.0) DIN Bit n 1 TDCC Bit n + 1 2 TCCD 5 TCCL CCLK 4 TCCH DOUT (Output) 3 TCCO Bit n - 1 Bit n X5379 Description To DOUT CCLK DIN setup DIN hold High time Low time (Note 1) Frequency 3 1 2 4 5 Symbol TCCO Min TDCC TCCD TCCH TCCL FCC 60 0 0.05 0.05 Max 100 Units ns 5.0 10 ns ns ns s MHz Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA. 2. Configuration must be delayed until the INIT of all FPGAs is High. 3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). Figure 30: Slave Serial Mode Programming Switching Characteristics June 1, 1996 (Version 2.0) 4-317 XC3000 Series Field Programmable Gate Arrays Program Readback Switching Characteristics DONE/PROG (OUTPUT) 1 TRTH RTRIG (M0) 2 TRTCC 4 TCCL 4 TCCL CCLK(1) 5 3 TCCRD M1 Input/ RDATA Output HI-Z VALID READBACK OUTPUT VALID READBACK OUTPUT X6116 RTRIG CCLK Notes: 1. 2. 3. 4. 4-318 Description RTRIG High RTRIG setup RDATA delay High time Low time 1 2 3 4 5 Symbol TRTH TRTCC TCCRD TCCHR TCCLR Min 250 200 Max 100 0.5 0.5 5 Units ns ns ns s s During Readback, CCLK frequency may not exceed 1 MHz. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins. Readback should not be initiated until configuration is complete. TCCLR is 5 s min to 15 s max for XC3000L. June 1, 1996 (Version 2.0) General XC3000 Series Switching Characteristics 4 TMRW RESET 2 TMR 3 TRM M0/M1/M2 5 TPGW DONE/PROG 6 TPGI INIT (Output) User State Clear State Configuration State PWRDWN Note 3 VCC (Valid) VCCPD X5387 Description M0, M1, M2 setup time required RESET (2) M0, M1, M2 hold time required RESET Width (Low) req. for Abort Width (Low) required for Re-config. DONE/PROG INIT response after D/P is pulled Low PWRDWN (3) Power Down VCC 2 3 4 5 6 Symbol TMR TRM TMRW TPGW TPGI VCCPD Min 1 4.5 6 6 Max 7 2.3 Units s s s s s V Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a nonmonotonically rising VCC may require a >1-s High level on RESET, followed by a >6-s Low level on RESET and D/P after Vcc has reached 4.0 V (2.5 V for XC3000L). 2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration. 3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L). June 1, 1996 (Version 2.0) 4-319 XC3000 Series Field Programmable Gate Arrays Device Performance The XC3000 families of FPGAs can achieve very high performance. This is the result of * * * A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. Careful optimization of transistor geometries, circuit design, and lay-out, based on years of experience with the XC3000 family. A look-up table based, coarse-grained architecture that can collapse multiple-layer combinatorial logic into a single function generator. One CLB can implement up to four layers of conventional logic in as little as 1.5 ns. Actual system performance is determined by the timing of critical paths, including the delay through the combinatorial and sequential logic elements within CLBs and IOBs, plus the delay in the interconnect routing. The AC-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000-families architecture. Figure 31 shows a variety of elements involved in determining system performance. Logic block performance is expressed as the propagation time from the interconnect point at the input to the block to the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table within a CLB, the combinatorial delay through the CLB, called TILO, is always the same, regardless of the function being implemented. For the combinatorial logic function driving the data input of the storage element, the critical timing is data set-up relative to the clock edge provided to the flip-flop element. The delay from the clock source to the output of the logic block is critical in the timing signals produced by storage elements. Loading of a logic-block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature. See Figure 32. Interconnect performance depends on the routing resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast path. Local interconnects go through switch matrices (magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of the driven metal line. Longlines carry the signal across the length or breadth of the chip with only one access delay. Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from 1 to 8 changes the CLB delay by only 10%. Clocks can be distributed with two low-skew clock distribution networks. The tools in the XACTstep Development System used to place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays along each signal path. This timing information can be back-annotated to the design's netlist for use in timing simulation or examined with X-Delay, a static timing analyzer. Actual system performance is applications dependent. The maximum clock rate that can be used in a system is determined by the critical path delays within that system. These delays are combinations of incremental logic and routing delays, and vary from design to design. In a synchronous system, the maximum clock rate depends on the number of combinatorial logic layers between re-synchronizing flipflops. Figure 33 shows the achievable clock rate as a function of the number of CLB layers. Clock to Output Combinatorial Setup TCKO TILO TICK CLB TOP CLB Logic CLB IOB Logic PAD (K) (K) CLOCK IOB TCKO PAD T PID TOKPO X3178 Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing. factors. Overall performance can be evaluated with the XDelay timing calculator or by an optional simulation. 4-320 June 1, 1996 (Version 2.0) SPECIFIED WORST-CASE VALUES 1.00 IAL C MER MAX 5 V) (4.7 COM ) .5 V RY (4 ILITA M MAX NORMALIZED DELAY 0.80 TYPICAL COMMERCIAL (+ 5.0 V, 25C) 0.60 TYPICAL MILITARY 0.40 ARY (4.5 75 V) ERCIAL (4. MIN COMM 25 V) ERCIAL (5. MIN COMM MIN MILIT MIN MILITARY V) (5.5 V) 0.20 - 55 - 40 - 20 0 25 40 70 80 100 125 TEMPERATURE (C) X6094 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations Power Power Distribution 300 System Clock (MHz) 250 200 150 100 XC3100A-3 50 XC3000A--6 0 CLB Levels: 4 CLBs Gate Levels: (4-16) 3 CLBs (3-12) 2 CLBs (2-8) 1 CLB (1-4) Toggle Rate X7065 Figure 33: Clock Rate as a Function of Logic Complexity (Number of Combinational Levels between Flip-Flops) June 1, 1996 (Version 2.0) Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated VCC and ground ring surrounding the logic array provides power to the I/O drivers. An independent matrix of VCC and groundlines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1-F capacitor connected near the VCC and ground pins will provide adequate decoupling. Output buffers capable of driving the specified 4- or 8-mA loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the ground pads. The I/O Block output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability, but generate less external reflections and internal noise. 4-321 XC3000 Series Field Programmable Gate Arrays Dynamic Power Consumption One CLB driving three local interconnects One global clock buffer and clock line One device output with a 50 pF load XC3042A 0.25 2.25 1.25 XC3042L 0.17 1.40 1.25 XC3142A 0.25 1.70 1.25 mW per MHz mW per MHz mW per MHz Power Consumption The Field Programmable Gate Array exhibits the low power consumption characteristic of CMOS ICs. For any design, the configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells that hold the configuration data is very low and may be maintained in a powerdown mode. Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and frequency dependent power is 25 W/pF/MHz per output. Another component of I/O power is the external dc loading on all output pins. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an FPGA, the fraction of nodes changing on a given clock is typically low (10-20%). For example, in a long binary counter, the total activity of all counter flip-flops is equivalent to that of only two CLB outputs toggling at the clock frequency. Typical global clock-buffer power is between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz for the XC3090A. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each CLB output requires about 0.25 mW per MHz of its output frequency. Because the control storage of the FPGA is CMOS static memory, its cells require a very low standby current for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA 4-322 has built in powerdown logic which, when activated, will disable normal operation of the device and retain only the configuration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull-ups. Different from the XC3000 family which can be powered down to a current consumption of a few microamps, the XC3100A draws 5 mA, even in power-down. This makes power-down operation less meaningful. In contrast, ICCPD for the XC3000L is only 10 A. To force the FPGA into the Powerdown state, the user must pull the PWRDWN pin Low and continue to supply a retention voltage to the VCC pins. When normal power is restored, VCC is elevated to its normal operating voltage and PWRDWN is returned to a High. The FPGA resumes operation with the same internal sequence that occurs at the conclusion of configuration. Internal-I/O and logic-block storage elements will be reset, the outputs will become enabled and the DONE/PROG pin will be released. When VCC is shut down or disconnected, some power might unintentionally be supplied from an incoming signal driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and ground. A positive voltage applied to an input (or output) will cause the positive protection diode to conduct and drive the VCC connection. This condition can produce invalid power conditions and should be avoided. A large series resistor might be used to limit the current or a bipolar buffer may be used to isolate the input signal. June 1, 1996 (Version 2.0) Pin Descriptions Permanently Dedicated Pins Once configuration is done, a High-to-Low transition of this pin will cause an initialization of the FPGA and start a reconfiguration. VCC M0/RTRIG Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. As Mode 0, this input is sampled on power-on to determine the power-on delay (214 cycles if M0 is High, 216 cycles if M0 is Low). Before the start of configuration, this input is again sampled together with M1, M2 to determine the configuration mode to be used. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains configuration. All flip-flops and latches are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When PWDWN returns High, the FPGA becomes operational with DONE Low for two cycles of the internal 1-MHz clock. Before and during configuration, PWRDWN must be High. If not used, PWRDWN must be tied to VCC. RESET This is an active Low input which has three functions. Prior to the start of configuration, a Low input will delay the start of the configuration process. An internal circuit senses the application of power and begins a minimal time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins. If RESET is asserted during a configuration, the FPGA is re-initialized and restarts the configuration at the termination of RESET. A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of configuration and storage-element data clocked by CCLK. By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single Readback, or be inhibited altogether. M1/RDATA As Mode 1, this input and M0, M2 are sampled before the start of configuration to establish the configuration mode to be used. If Readback is never used, M1 can be tied directly to ground or VCC. If Readback is ever used, M1 must use a 5-k resistor to ground or VCC, to accommodate the RDATA output. As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data. User I/O Pins That Can Have Special Functions M2 If RESET is asserted after configuration is complete, it provides a global asynchronous RESET of all IOB and CLB storage elements of the FPGA. During configuration, this input has a weak pull-up resistor. Together with M0 and M1, it is sampled before the start of configuration to establish the configuration mode to be used. After configuration, this pin is a user-programmable I/O pin. CCLK HDC During configuration, Configuration Clock is an output of an FPGA in Master mode or Peripheral mode, but an input in Slave mode. During Readback, CCLK is a clock input for shifting configuration data out of the FPGA. During configuration, this output is held at a High level to indicate that configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. CCLK drives dynamic circuitry inside the FPGA. The Low time may, therefore, not exceed a few microseconds. When used as an input, CCLK must be "parked High". An internal pull-up resistor maintains High when the pin is not being driven. LDC DONE/PROG (D/P) DONE is an open-drain output, configurable with or without an internal pull-up resistor of 2 to 8 k . At the completion of configuration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High one cycle either before or after the outputs go active. June 1, 1996 (Version 2.0) During Configuration, this output is held at a Low level to indicate that the configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. LDC is particularly useful in Master mode as a Low enable for an EPROM, but it must then be programmed as a High after configuration. INIT This is an active Low open-drain output with a weak pull-up and is held Low during the power stabilization and internal clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired 4-323 XC3000 Series Field Programmable Gate Arrays AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in the lower right corner. XTL1 This user I/O pin can be used to operate as the output of an amplifier driving an external crystal and bias circuitry. XTL2 This user I/O pin can be used as the input of an amplifier connected to an external crystal and bias circuitry. The I/O Block is left unconfigured. The oscillator configuration is activated by routing a net from the oscillator buffer symbol output and by the MakeBits program. CS0, CS1, CS2, WS These four inputs represent a set of signals, three active Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous assertion of all four inputs generates a Write to the internal data buffer. The removal of any assertion clocks in the D0D7 data. In Master-Parallel mode, WS and CS2 are the A0 and A1 outputs. After configuration, these pins are userprogrammable I/O pins. RDY/BUSY During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be written to it. After configuration is complete, this pin becomes a user-programmed I/O pin. RCLK During Master Parallel mode configuration, each change on the A0-15 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration is complete, this pin becomes a user-programmed I/O pin. D0-D7 This set of eight pins represents the parallel configuration byte for the parallel Master and Peripheral modes. After configuration is complete, they are user-programmed I/O pins. A0-A15 During Master Parallel mode, these 16 pins present an address output for a configuration EPROM. After configuration, they are user-programmable I/O pins. DIN During Slave or Master Serial configuration, this pin is used as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. After configuration is complete, this pin becomes a user-programmed I/O pin. DOUT During configuration this pin is used to output serial-configuration data to the DIN pin of a daisy-chained slave. After configuration is complete, this pin becomes a user-programmed I/O pin. TCLKIN This is a direct CMOS-level input to the global clock buffer. This pin can also be configured as a user programmable I/O pin. However, since TCLKIN is the preferred input to the global clock net, and the global clock net should be used as the primary clock source, this pin is usually the clock input to the chip. Unrestricted User I/O Pins I/O An I/O pin may be programmed by the user to be an Input or an Output pin following configuration. All unrestricted I/O pins, plus the special pins mentioned on the following page, have a weak pull-up resistor of 50 k to 100 k that becomes active as soon as the device powers up, and stays active until the end of configuration. Note: Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50 k to 100 k pull-up resistor. 4-324 June 1, 1996 (Version 2.0) Pin Functions During Configuration *** Configuration Mode SLAVE SERIAL <1:1:1> MASTERSERIAL <0:0:0> POWR DWN (I) POWER DWN (I) PERIPH <1:0:1> MASTERHIGH <1:1:0> MASTERLOW <1:0:0> POWER DWN (I) POWER DWN (I) POWER DWN (I) *** 100 44 64 68 84 84 100 VQFP 132 144 160 175 176 208 223 PLCC VQFP PLCC PLCC PGA PQFP TQFP PGA TQFP PQFP PGA TQFP PQFP PGA 7 17 10 12 M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) 16 31 25 M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) Mo (LOW) (I) 17 32 26 User Function POWER DWN (1) B2 29 26 A1 1 159 B2 1 3 B2 31 J2 52 49 B13 36 40 B14 45 48 C16 RDATA 32 L1 54 51 A14 38 42 B15 47 50 B17 RTRIG (I) M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) 18 33 27 33 K2 56 53 C13 40 44 C15 49 56 A17 I/O HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) 19 34 28 34 K3 57 54 B14 41 45 E14 50 57 A18 I/O LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) 20 36 30 36 L3 59 56 D14 45 49 D16 54 61 E16 I/O INIT* INIT* INIT* INIT* INIT* 22 40 34 42 K6 65 62 G14 65 59 H15 65 77 J16 I/O GND GND GND GND GND 23 41 35 43 J6 66 63 H12 55 19 J14 67 79 K15 GND 26 47 43 53 L11 76 73 M13 69 76 P15 85 100 V18 XTL2 OR I/O RESET (I) RESET (I) RESET (I) RESET (I) RESET (I) RESET (I) 27 48 44 54 K10 78 75 P14 71 78 R15 87 102 U17 DONE DONE DONE DONE DONE 28 49 45 55 J10 80 77 N13 73 80 R14 89 107 V17 PROGRAM (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) 50 46 56 K11 81 78 M12 74 81 N13 90 109 T16 I/O 30 51 47 57 J11 82 79 P13 75 82 T14 91 110 U16 XTL1 OR I/O I/O DATA 6 (I) DATA 7 (I) DATA 6 (I) 52 48 58 H10 83 80 N11 78 86 P12 96 115 U15 DATA 6 (I) DATA 6 (I) DATA 6 (I) 53 49 60 F10 87 84 M9 84 92 T11 102 122 U12 I/O 54 50 61 G10 88 85 N9 85 93 R10 103 123 V11 I/O I/O CS0 (I) DATA (4) DATA (4) DATA (4) 55 51 62 G11 89 86 N8 88 96 R9 108 128 U10 DATA (3) DATA (3) DATA (3) 57 53 65 F11 92 89 N7 92 102 P8 112 132 T9 I/O 58 54 66 E11 93 90 P6 93 103 R8 113 133 U9 I/O CS1 (I) DATA (2) DATA (2) DATA (2) 59 55 67 E10 94 91 M6 96 106 R7 118 138 V8 I/O DATA (1) DATA (1) DATA (1) 60 56 70 D10 98 95 M5 102 114 R5 124 145 U5 I/O RDY/BUSY RCLK RCLK 61 57 71 C11 99 96 N4 103 115 P5 125 146 U4 I/O DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) 38 62 58 72 B11 100 97 N2 106 119 R3 130 151 U3 I/O DOUT DOUT DOUT DOUT DOUT 39 63 59 73 C10 1 98 M3 107 120 N4 131 152 V2 I/O CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (O) 40 64 60 74 A11 2 99 P1 108 121 R2 132 153 U2 CCLK (I) WS (I) A0 A0 1 61 75 B10 5 2 M2 111 124 P2 135 161 T3 I/O CS2 (I) A1 A1 2 62 76 B9 6 3 N1 112 125 M3 136 162 V1 I/O A2 A2 3 63 77 A10 8 5 L2 115 128 P1 140 165 R2 I/O A3 A3 4 64 78 A9 9 6 L1 116 129 N1 141 166 T1 I/O A15 A15 65 81 B6 12 9 K1 119 132 M1 146 172 N2 5 A4 A4 5 66 82 B7 13 10 J2 120 133 L2 147 173 M4 I/O A14 A14 6 67 83 A7 14 11 H1 123 136 K2 150 178 L4 I/O A5 A5 7 68 84 C7 15 12 H2 124 137 K1 151 179 L2 I/O A13 A13 9 2 2 A6 17 14 G2 128 141 H2 156 184 K3 I/O I/O A6 A6 10 3 3 A5 18 15 G1 129 142 H1 157 185 J1 A12 A12 11 4 4 B5 19 16 F2 133 147 F2 164 192 G1 I/O A7 A7 12 5 5 C5 20 17 E1 134 148 E1 165 193 G4 I/O A11 A11 13 6 6 A3 23 20 D1 137 151 D1 169 199 F4 I/O A8 A8 14 7 9 A2 24 21 D2 138 152 C1 170 200 E2 I/O A10 A10 15 8 10 B3 25 22 B1 141 155 E3 173 203 E3 I/O A9 A9 16 9 11 A1 26 26 C2 142 156 C2 174 204 B1 I/O X X X X All Others X X X X X X X X X X X X** X** Notes: * (I) ** *** **** Note: XC3x20A etc. X** XC3x30A etc. X X X X X XC3x42A etc. XC3x64A etc. X X X X X X XC3x90A etc. X XC3195A Generic I/O pins are not shown. For a detailed description of the configuration modes, see page 310 through page 319. For pinout details, see page 327 through page 338. Represents a 50-k to 100-k pull-up before and during configuration. INIT is an open drain output during configuration. Represents an input. Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown. Peripheral mode and master parallel mode are not supported in the PC44 package. Pin assignments for the XC3195A PQ208 differ from those shown. Pin assignments of PGA Footprint PLCC sockets and PGA packages are not indentical. The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages. Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 100-kW pull-up resistor. June 1, 1996 (Version 2.0) 4-325 XC3000 Series Field Programmable Gate Arrays XC3000 Series Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223. Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. Most package types are also offered with different chips to accommodate design changes without the need for PC board changes. Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package. In some cases, the chip has more pads than there are pins on the package, as indicated by the information ("unused" pads) below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified propagation delays and set-up times are acceptable. In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected (n.c.), as shown above the line in the following table. Number of Unbounded or Unconnected Pins Number of Package Pins 132 144 160 175 176 208 223 10 n.c. 26 n.c. -- -- -- -- -- -- -- 14 u 2 n.c. -- -- -- -- -- -- -- -- 34 u 18 u -- -- -- -- -- -- 50 u -- 10 u 2u 18 n.c. -- -- -- -- -- 82 u -- -- -- 6u 9 n.c -- 9 n.c. 32 u 44 64 68 3020A 74 -- -- 6u 3030A 98 54 u 34 u 30 u 3042A 118 -- -- 3064A 142 -- -- 3090A 166 -- -- Device Pads 3195A 198 -- 114 u -- -- 100 84 -- 14 n.c. 26 n.c. -- -- 10 n.c. 42 n.c. -- -- 10 n.c. 25 n.c. n.c. = Unconnected package pin u = Unbonded device pad X7066 Number of Available I/O Pins Number of Package Pins Max I/O XC3020A/XC3120A XC3030A/XC3130A XC3042A/XC3142A XC3064A/XC3164A XC3090A/XC3190A XC3195A 64 80 96 120 144 176 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 240 34 54 58 58 64 74 74 70 70 70 64 80 82 96 96 110 110 120 120 138 144 144 144 144 138 144 176 176 X7067 4-326 June 1, 1996 (Version 2.0) XC3000 Series 44-Pin PLCC Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 XC3030A GND I/O I/O I/O I/O I/O PWRDWN TCLKIN-I/O I/O I/O I/O VCC I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O INIT-I/O Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 XC3030A GND I/O I/O XTL2(IN)-I/O RESET DONE-PGM I/O XTL1(OUT)-BCLK-I/O I/O I/O I/O VCC I/O I/O I/O DIN-I/O DOUT-I/O CCLK I/O I/O I/O I/O Peripheral mode and Master Parallel mode are not supported in the PC44 package June 1, 1996 (Version 2.0) 4-327 XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4-328 XC3030A A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XC3030A M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O INIT-I/O GND I/O I/O I/O I/O I/O XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O VCC D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK June 1, 1996 (Version 2.0) XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts 68 PLCC XC3030A XC3020A XC3020A, XC3030A, XC3042A 84 PLCC 84 PGA 68 PLCC XC3030A XC3020A XC3020A, XC3030A, XC3042A 84 PLCC 84 PGA XC3020A 10 10 PWRDN 12 B2 44 RESET 54 K10 44 11 11 TCLKIN-I/O 13 C2 45 DONE-PG 55 J10 45 12 -- I/O* 14 B1 46 D7-I/O 56 K11 46 13 12 I/O 15 C1 47 XTL1(OUT)-BCLKIN-I/O 57 J11 47 14 13 I/O 16 D2 48 D6-I/O 58 H10 48 -- -- I/O 17 D1 -- I/O 59 H11 -- 15 14 I/O 18 E3 49 D5-I/O 60 F10 49 16 15 I/O 19 E2 50 CS0-I/O 61 G10 50 -- 16 I/O 20 E1 51 D4-I/O 62 G11 51 17 17 I/O 21 F2 -- I/O 63 G9 -- 18 18 VCC 22 F3 52 VCC 64 F9 52 19 19 I/O 23 G3 53 D3-I/O 65 F11 53 -- -- I/O 24 G1 54 CS1-I/O 66 E11 54 20 20 I/O 25 G2 55 D2-I/O 67 E10 55 -- 21 I/O 26 F1 -- I/O 68 E9 -- 21 22 I/O 27 H1 -- I/O* 69 D11 -- 22 -- I/O 28 H2 56 D1-I/O 70 D10 56 23 23 I/O 29 J1 57 RDY/BUSY-RCLK-I/O 71 C11 57 24 24 I/O 30 K1 58 D0-DIN-I/O 72 B11 58 25 25 M1-RDATA 31 J2 59 DOUT-I/O 73 C10 59 26 26 M0-RTRIG 32 L1 60 CCLK 74 A11 60 27 27 M2-I/O 33 K2 61 A0-WS-I/O 75 B10 61 28 28 HDC-I/O 34 K3 62 A1-CS2-I/O 76 B9 62 29 29 I/O 35 L2 63 A2-I/O 77 A10 63 30 30 LDC-I/O 36 L3 64 A3-I/O 78 A9 64 -- 31 I/O 37 K4 -- I/O* 79 B8 -- I/O* 38 L4 -- I/O* 80 A8 -- I/O 39 J5 65 A15-I/O 81 B6 65 -- 31 32 32 33 I/O 40 K5 66 A4-I/O 82 B7 66 33 -- I/O* 41 L5 67 A14-I/O 83 A7 67 34 34 INIT-I/O 42 K6 68 A5-I/O 84 C7 68 35 35 GND 43 J6 1 GND 1 C6 1 36 36 I/O 44 J7 2 A13-I/O 2 A6 2 37 37 I/O 45 L7 3 A6-I/O 3 A5 3 38 38 I/O 46 K7 4 A12-I/O 4 B5 4 39 39 I/O 47 L6 5 A7-I/O 5 C5 5 -- 40 I/O 48 L8 -- I/O* 6 A4 -- -- 41 I/O 49 K8 -- I/O* 7 B4 -- 40 I/O* 50 L9 6 A11-I/O 8 A3 6 41 I/O* 51 L10 7 A8-I/O 9 A2 7 42 42 I/O 52 K9 8 A10-I/O 10 B3 8 43 43 XTL2(IN)-I/O 53 L11 9 A9-I/O 11 A1 9 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a dash (--) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages. June 1, 1996 (Version 2.0) 4-329 XC3000 Series Field Programmable Gate Arrays XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PLCC Pin Number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 XC3064A, XC3090A, XC3195A PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O GND* VCC I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O I/O INIT/I/O* VCC* GND I/O I/O I/O I/O I/O I/O I/O I/O I/O XTL2(IN)-I/O PLCC Pin Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 XC3064A, XC3090A, XC3195A RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O D5-I/O CS0-I/O D4-I/O I/O VCC GND* D3-I/O* CS1-I/O* D2-I/O* I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O A14-I/O A5-I/O GND VCC* A13-I/O* A6-I/O* A12-I/O* A7-I/O* I/O A11-I/O A8-I/O A10-I/O A9-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin definition than XC3020A/XC3030A/XC3042A. 4-330 June 1, 1996 (Version 2.0) XC3000 Series 100-Pin QFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin No. TQFP CQFP PQFP VQFP 1 16 13 2 17 14 3 18 15 4 19 16 5 20 17 6 21 18 7 22 19 8 23 20 9 24 21 10 25 22 11 26 23 12 27 24 13 28 25 14 29 26 15 30 27 16 31 28 17 32 29 18 33 30 19 34 31 20 35 32 21 36 33 22 37 34 23 38 35 24 39 36 25 40 37 26 41 38 27 42 39 28 43 40 29 44 41 30 45 42 31 46 43 32 47 44 33 48 45 34 49 46 XC3020A XC3030A XC3042A GND A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O VCC* GND* PWRDN TCLKIN-I/O I/O** I/O* I/O* I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O Pin No. XC3020A TQFP XC3030A CQFP PQFP VQFP XC3042A 35 50 47 I/O* 36 51 48 I/O* 37 52 49 M1-RD 38 53 50 GND* 39 54 51 MO-RT 40 55 52 VCC* 41 56 53 M2-I/O 42 57 54 HDC-I/O 43 58 55 I/O 44 59 56 LDC-I/O 45 60 57 I/O* 46 61 58 I/O* 47 62 59 I/O 48 63 60 I/O 49 64 61 I/O 50 65 62 INIT-I/O 51 66 63 GND 52 67 64 I/O 53 68 65 I/O 54 69 66 I/O 55 70 67 I/O 56 71 68 I/O 57 72 69 I/O 58 73 70 I/O 59 74 71 I/O* 60 75 72 I/O* 61 76 73 XTL2-I/O 62 77 74 GND* 63 78 75 RESET 64 79 76 VCC* 65 80 77 DONE-PG 66 81 78 D7-I/O 67 82 79 BCLKIN-XTL1-I/O 68 83 80 D6-I/O Pin No. TQFP CQFP PQFP VQFP 69 84 81 70 85 82 71 86 83 72 87 84 73 88 85 74 89 86 75 90 87 76 91 88 77 92 89 78 93 90 79 94 91 80 95 92 81 96 93 82 97 94 83 98 95 84 99 96 85 100 97 86 1 98 87 2 99 88 3 100 89 4 1 90 5 2 91 6 3 92 7 4 93 8 5 94 9 6 95 10 7 96 11 8 97 12 9 98 13 10 99 14 11 100 15 12 XC3020A XC3030A XC3042A I/O* I/O* I/O D5-I/O CS0-I/O D4-I/O I/O VCC D3-I/O CS1-I/O D2-I/O I/O I/O* I/O* D1-I/O RDY/BUSY-RCLK-I/O DO-DIN-I/O DOUT-I/O CCLK VCC* GND* AO-WS-I/O A1-CS2-I/O I/O** A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * This table describes the pinouts of three different chips in three different packages. The pin-description column lists 100 of the 118 pads on the XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 326.) June 1, 1996 (Version 2.0) 4-331 XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin Number C4 A1 C3 B2 B3 A2 B4 C5 A3 A4 B5 C6 A5 B6 A6 B7 C7 C8 A7 B8 A8 A9 B9 C9 A10 B10 A11 C10 B11 A12 B12 A13 C12 XC3042A XC3064A GND PWRDN I/O-TCLKIN I/O I/O I/O* I/O I/O I/O* I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O* I/O I/O* I/O PGA Pin Number B13 C11 A14 D12 C13 B14 C14 E12 D13 D14 E13 F12 E14 F13 F14 G13 G14 G12 H12 H14 H13 J14 J13 K14 J12 K13 L14 L13 K12 M14 N14 M13 L12 XC3042A XC3064A M1-RD GND M0-RT VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O* I/O I/O I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O* I/O I/O I/O I/O XTL2(IN)-I/O GND PGA Pin XC3042A Number XC3064A P14 RESET M11 VCC N13 DONE-PG M12 D7-I/O P13 XTL1-I/O-BCLKIN N12 I/O P12 I/O N11 D6-I/O M10 I/O P11 I/O* N10 I/O P10 I/O M9 D5-I/O N9 CS0-I/O P9 I/O* P8 I/O* N8 D4-I/O P7 I/O M8 VCC M7 GND N7 D3-I/O P6 CS1-I/O N6 I/O* P5 I/O* M6 D2-I/O N5 I/O P4 I/O P3 I/O M5 D1-I/O N4 RDY/BUSY-RCLK-I/O P2 I/O N3 I/O N2 D0-DIN-I/O PGA Pin Number M3 P1 M4 L3 M2 N1 M1 K3 L2 L1 K2 J3 K1 J2 J1 H1 H2 H3 G3 G2 G1 F1 F2 E1 F3 E2 D1 D2 E3 C1 B1 C2 D3 XC3042A XC3064A DOUT-I/O CCLK VCC GND A0-WS-I/O A1-CS2-I/O I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O I/O* A14-I/O A5-I/O GND VCC A13-I/O A6-I/O I/O* A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. *Indicates unconnected package pins (14) for the XC3042A. 4-332 June 1, 1996 (Version 2.0) XC3000 Series 144-Pin Plastic TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Number XC3042A XC3064A XC3090A XC3042A XC3064A XC3090A Pin Number Pin Number XC3042A XC3064A XC3090A 1 PWRDN 49 I/O 97 I/O 2 I/O-TCLKIN 50 I/O* 98 I/O 3 I/O* 51 I/O 99 I/O* 4 I/O 52 I/O 100 I/O 5 I/O 53 INIT-I/O 101 I/O* 6 I/O* 54 VCC 102 D1-I/O 7 I/O 55 GND 103 RDY/BUSY-RCLK-I/O 8 I/O 56 I/O 104 I/O 9 I/O* 57 I/O 105 I/O 10 I/O 58 I/O 106 D0-DIN-I/O 11 I/O 59 I/O 107 DOUT-I/O 12 I/O 60 I/O 108 CCLK 13 I/O 61 I/O 109 VCC 14 I/O 62 I/O 110 GND 15 I/O* 63 I/O* 111 A0-WSI/O 16 I/O 64 I/O* 112 A1-CS2-I/O 17 I/O 65 I/O 113 I/O 18 GND 66 I/O 114 I/O 19 VCC 67 I/O 115 A2-I/O 20 I/O 68 I/O 116 A3-I/O 21 I/O 69 XTL2(IN)-I/O 117 I/O 22 I/O 70 GND 118 I/O 23 I/O 71 RESET 119 A15-I/O 24 I/O 72 VCC 120 A4-I/O 25 I/O 73 DONE-PG 121 I/O* 26 I/O 74 D7-I/O 122 I/O* A14-I/O 27 I/O 75 XTL1(OUT)-BCLKIN-I/O 123 28 I/O* 76 I/O 124 A5-I/O 29 I/O 77 I/O 125 I/O (XC3090 only) GND 30 I/O 78 D6-I/O 126 31 I/O* 79 I/O 127 VCC 32 I/O* 80 I/O* 128 A13-I/O A6-I/O 33 I/O 81 I/O 129 34 I/O* 82 I/O 130 I/O* 35 I/O 83 I/O* 131 I/O (XC3090 only) 36 M1-RD 84 D5-I/O 132 I/O* 37 GND 85 CS0-I/O 133 A12-I/O 38 MO-RT 86 I/O* 134 A7-I/O 39 VCC 87 I/O* 135 I/O 40 M2-I/O 88 D4-I/O 136 I/O 41 HDC-I/O 89 I/O 137 A11-I/O 42 I/O 90 VCC 138 A8-I/O 43 I/O 91 GND 139 I/O 44 I/O 92 D3-I/O 140 I/O 45 LDC-I/O 93 CS1-I/O 141 A10-I/O 46 I/O* 94 I/O* 142 A9-I/O 47 I/O 95 I/O* 143 VCC 48 I/O 96 D2-I/O 144 GND Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (24) for the XC3042A. June 1, 1996 (Version 2.0) 4-333 XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts XC3064A, XC3090A, XC3195A PQFP Pin Number XC3064A, XC3090A, XC3195A PQFP Pin Number XC3064A, XC3090A, XC3195A 41 GND 42 M0-RTRIG 81 D7-I/O 121 CCLK 82 XTL1-I/O-BCLKIN 122 I/O 43 VCC VCC 83 I/O* 123 GND 4 I/O 5 I/O 44 M2-I/O 84 I/O 124 A0-WS-I/O 45 HDC-I/O 85 I/O 125 A1-CS2-I/O 6 7 I/O 46 I/O 86 D6-I/O 126 I/O I/O 47 I/O 87 I/O 127 8 I/O I/O 48 I/O 88 I/O 128 A2-I/O PQFP Pin Number XC3064A, XC3090A, XC3195A PQFP Pin Number 1 I/O* 2 I/O 3 9 I/O 49 LDC-I/O 89 I/O 129 A3-I/O 10 I/O 50 I/O* 90 I/O 130 I/O 11 I/O 51 I/O* 91 I/O 131 I/O 12 I/O 52 I/O 92 D5-I/O 132 A15-I/O 13 I/O 53 I/O 93 CS0-I/O 133 A4-I/O 14 I/O 54 I/O 94 I/O* 134 I/O 15 I/O 55 I/O 95 I/O* 135 I/O 16 I/O 56 I/O 96 I/O 136 A14-I/O 17 I/O 57 I/O 97 I/O 137 A5-I/O 18 I/O 58 I/O 98 D4-I/O 138 I/O* 19 GND 59 INIT-I/O 99 I/O 139 GND 20 VCC 60 VCC 100 VCC 140 VCC 21 I/O* 61 GND 101 GND 141 A13-I/O 22 I/O 62 I/O 102 D3-I/O 142 A6-I/O 23 I/O 63 I/O 103 CS1-I/O 143 I/O* 24 I/O 64 I/O 104 I/O 144 I/O* 25 I/O 65 I/O 105 I/O 145 I/O 26 I/O 66 I/O 106 I/O* 146 I/O 27 I/O 67 I/O 107 I/O* 147 A12-I/O 28 I/O 68 I/O 108 D2-I/O 148 A7-I/O 29 I/O 69 I/O 109 I/O 149 I/O 30 I/O 70 I/O 110 I/O 150 I/O 31 I/O 71 I/O 111 I/O 151 A11-I/O 32 I/O 72 I/O 112 I/O 152 A8-I/O 33 I/O 73 I/O 113 I/O 153 I/O 34 I/O 74 I/O 114 D1-I/O 154 I/O 35 I/O 75 I/O* 115 RDY/BUSY-RCLK-I/O 155 A10-I/O 36 I/O 76 XTL2-I/O 116 I/O 156 A9-I/O 37 I/O 77 GND 117 I/O 157 VCC 38 I/O* 78 RESET 118 I/O* 158 GND 39 I/O* 79 VCC 119 D0-DIN-I/O 159 PWRDWN 40 M1-RDATA 80 DONE/PG 120 DOUT-I/O 160 TCLKIN-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed IOBs are default slew-rate limited. *Indicates unconnected package pins (18) for the XC3064A. 4-334 June 1, 1996 (Version 2.0) XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin Number XC3090A, XC3195A PGA Pin Number XC3090A, XC3195A PGA Pin Number XC3090A, XC3195A PGA Pin Number XC3090A, XC3195A B2 PWRDN D13 I/O R14 DONE-PG N4 DOUT-I/O D4 TCLKIN-I/O B14 M1-RDATA N13 D7-I/O R2 CCLK B3 I/O C14 GND T14 XTL1(OUT)-BCLKIN-I/O P3 VCC C4 I/O B15 M0-RTRIG P13 I/O N3 GND B4 I/O D14 VCC R13 I/O P2 A0-WS-I/O A4 I/O C15 M2-I/O T13 I/O M3 A1-CS2-I/O D5 I/O E14 HDC-I/O N12 I/O R1 I/O C5 I/O B16 I/O P12 D6-I/O N2 I/O B5 I/O D15 I/O R12 I/O P1 A2-I/O A3-I/O A5 I/O C16 I/O T12 I/O N1 C6 I/O D16 LDC-I/O P11 I/O L3 I/O D6 I/O F14 I/O N11 I/O M2 I/O B6 I/O E15 I/O R11 I/O M1 A15-I/O A6 I/O E16 I/O T11 D5-I/O L2 A4-I/O B7 I/O F15 I/O R10 CS0-I/O L1 I/O C7 I/O F16 I/O P10 I/O K3 I/O D7 I/O G14 I/O N10 I/O K2 A14-I/O A7 I/O G15 I/O T10 I/O K1 A5-I/O A8 I/O G16 I/O T9 I/O J1 I/O B8 I/O H16 I/O R9 D4-I/O J2 I/O C8 I/O H15 INIT-I/O P9 I/O J3 GND D8 GND H14 VCC N9 VCC H3 VCC D9 VCC J14 GND N8 GND H2 A13-I/O C9 I/O J15 I/O P8 D3-I/O H1 A6-I/O B9 I/O J16 I/O R8 CS1-I/O G1 I/O A9 I/O K16 I/O T8 I/O G2 I/O A10 I/O K15 I/O T7 I/O G3 I/O D10 I/O K14 I/O N7 I/O F1 I/O C10 I/O L16 I/O P7 I/O F2 A12-I/O B10 I/O L15 I/O R7 D2-I/O E1 A7-I/O A11 I/O M16 I/O T6 I/O E2 I/O B11 I/O M15 I/O R6 I/O F3 I/O D11 I/O L14 I/O N6 I/O D1 A11-I/O C11 I/O N16 I/O P6 I/O C1 A8-I/O A12 I/O P16 I/O T5 I/O D2 I/O B12 I/O N15 I/O R5 D1-I/O B1 I/O C12 I/O R16 I/O P5 RDY/BUSY-RCLK-I/O E3 A10-I/O D12 I/O M14 I/O N5 I/O C2 A9-I/O A13 I/O P15 XTL2(IN)-I/O T4 I/O D3 VCC B13 I/O N14 GND R4 I/O C3 GND C13 I/O R15 RESET P4 I/O A14 I/O P14 VCC R3 D0-DIN-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist. June 1, 1996 (Version 2.0) 4-335 XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Number XC3090A Pin Number XC3090A Pin Number XC3090A Pin Number 1 PWRDWN 45 M1-RDATA 89 DONE-PG 133 VCC 2 TCLKIN-I/O 46 GND 90 D7-I/O 134 GND 3 I/O 47 M0-RTRIG 91 XTAL1(OUT)-BCLKIN-I/O 135 A0-WS-I/O 4 I/O 48 VCC 92 I/O 136 A1-CS2-I/O 5 I/O 49 M2-I/O 93 I/O 137 - 6 I/O 50 HDC-I/O 94 I/O 138 I/O 7 I/O 51 I/O 95 I/O 139 I/O 8 I/O 52 I/O 96 D6-I/O 140 A2-I/O XC3090A 9 I/O 53 I/O 97 I/O 141 A3-I/O 10 I/O 54 LDC-I/O 98 I/O 142 - 11 I/O 55 - 99 I/O 143 - 12 I/O 56 I/O 100 I/O 144 I/O 13 I/O 57 I/O 101 I/O 145 I/O 14 I/O 58 I/O 102 D5-I/O 146 A15-I/O 15 I/O 59 I/O 103 CS0-I/O 147 A4-I/O 16 I/O 60 I/O 104 I/O 148 I/O 17 I/O 61 I/O 105 I/O 149 I/O 18 I/O 62 I/O 106 I/O 150 A14-I/O 19 I/O 63 I/O 107 I/O 151 A5-I/O 20 I/O 64 I/O 108 D4-I/O 152 I/O 21 I/O 65 INIT-I/O 109 I/O 153 I/O 22 GND 66 VCC 110 VCC 154 GND 23 VCC 67 GND 111 GND 155 VCC 24 I/O 68 I/O 112 D3-I/O 156 A13-I/O 25 I/O 69 I/O 113 CS1-I/O 157 A6-I/O 26 I/O 70 I/O 114 I/O 158 I/O 27 I/O 71 I/O 115 I/O 159 I/O 28 I/O 72 I/O 116 I/O 160 - 29 I/O 73 I/O 117 I/O 161 - 30 I/O 74 I/O 118 D2-I/O 162 I/O 31 I/O 75 I/O 119 I/O 163 I/O 32 I/O 76 I/O 120 I/O 164 A12-I/O 33 I/O 77 I/O 121 I/O 165 A7-I/O 34 I/O 78 I/O 122 I/O 166 I/O 35 I/O 79 I/O 123 I/O 167 I/O 36 I/O 80 I/O 124 D1-I/O 168 - 37 I/O 81 I/O 125 RDY/BUSY-RCLK-I/O 169 A11-I/O 38 I/O 82 - 126 I/O 170 A8-I/O 39 I/O 83 - 127 I/O 171 I/O 40 I/O 84 I/O 128 I/O 172 I/O 41 I/O 85 XTAL2(IN)-I/O 129 I/O 173 A10-I/O 42 I/O 86 GND 130 D0-DIN-I/O 174 A9-I/O 43 I/O 87 RESET 131 DOUT-I/O 175 VCC 44 - 88 VCC 132 CCLK 176 GND Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. 4-336 June 1, 1996 (Version 2.0) XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 XC3090A - GND PWRDWN TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M1-RDATA GND M0-RTRIG - - Pin Number 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 XC3090A - - VCC M2-I/O HDC-I/O I/O I/O I/O LDC-I/O I/O I/O - - - - I/O I/O I/O I/O - - I/O I/O I/O INIT-I/O VCC GND I/O I/O I/O - - I/O I/O I/O I/O I/O - - - I/O I/O I/O I/O I/O I/O I/O XTL2-I/O GND RESET - - Pin Number XC3090A 105 - 106 VCC 107 D/P 108 - 109 D7-I/O 110 XTL1-BCLKIN-I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 D6-I/O 116 I/O 117 I/O 118 I/O 119 - 120 I/O 121 I/O 122 D5-I/O 123 CS0-I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 D4-I/O 129 I/O 130 VCC 131 GND 132 D3-I/O 133 CS1-I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 D2-I/O 139 I/O 140 I/O 141 I/O 142 - 143 I/O 144 I/O 145 D1-I/O 146 RDY/BUSY-RCLK-I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 DIN-D0-I/O 152 DOUT-I/O 153 CCLK 154 VCC 155 - 156 - Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 XC3090A - - - GND WS-A0-I/O CS2-A1-I/O I/O I/O A2-I/O A3-I/O I/O I/O - - - A15-I/O A4-I/O I/O I/O - - A14-I/O A5-I/O I/O I/O GND VCC A13-I/O A6-I/O I/O I/O - - I/O I/O A12-I/O A7-I/O - - - I/O I/O A11-I/O A8-I/O I/O I/O A10-I/O A9-I/O VCC - - - Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. *In PQ208, XC3090A and XC3195A have different pinouts. June 1, 1996 (Version 2.0) 4-337 XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 and PG223 Pinouts Pin Description A9-I/O A10-I/O I/O I/O I/O I/O A8-I/O A11-I/O I/O I/O I/O I/O A7-I/O A12-I/O I/O I/O I/O I/O I/O I/O A6-I/O A13-I/O VCC GND I/O I/O A5-I/O A14-I/O I/O I/O I/O I/O A4-I/O A15-I/O I/O I/O I/O I/O A3-I/O A2-I/O I/O I/O I/O I/O A1-CS2-I/O A0-WS-I/O GND VCC CCLK DOUT-I/O PG223 PQ208 B1 206 E3 205 E4 204 C2 203 C1 202 D2 201 E2 200 F4 199 F3 198 D1 197 F2 196 G2 194 G4 193 G1 192 H2 191 H3 190 H1 189 H4 188 J3 187 J2 186 J1 185 K3 184 J4 183 K4 182 K2 181 K1 180 L2 179 L4 178 L3 177 L1 176 M1 175 M2 174 M4 173 N2 172 N3 171 P2 169 R1 168 N4 167 T1 166 R2 165 P3 164 T2 163 P4 162 U1 161 V1 160 T3 159 R3 158 R4 157 U2 156 V2 155 Pin Description D0-DIN-I/O I/O I/O I/O I/O PG223 PQ208 U3 154 V3 153 R5 152 T4 151 V4 150 RDY/BUSY-RCLK-I/O U4 149 D1-I/O U5 148 I/O R6 147 I/O T5 146 I/O U6 145 I/O T6 144 I/O V7 141 I/O R7 140 I/O U7 139 D2-I/O V8 138 I/O U8 137 I/O T8 136 I/O R8 135 I/O V9 134 CS1-I/O U9 133 D3-I/O T9 132 GND R9 131 VCC R10 130 I/O T10 129 D4-I/O U10 128 I/O V10 127 I/O R11 126 I/O T11 125 I/O U11 124 CS0-I/O V11 123 D5-I/O U12 122 I/O R12 121 I/O V12 120 I/O T13 119 I/O U13 118 I/O T14 117 I/O R13 116 I/O U14 115 D6-I/O U15 114 I/O V15 113 I/O T15 112 I/O R14 111 I/O V16 110 XTLX1(OUT)BCLKN-I/O U16 109 D7-I/O T16 108 D/P V17 107 VCC R15 106 RESET U17 105 GND R16 104 XTL2(IN)-I/O V18 103 Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC INIT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LDC-I/O I/O I/O I/O HDC-I/O M2-I/O VCC M0-RTIG GND M1/RDATA I/O PG223 PQ208 U18 102 P15 101 T17 100 T18 99 P16 98 R17 97 N15 96 R18 95 P17 94 N17 93 N16 92 M15 89 M18 88 M17 87 L18 86 L17 85 L15 84 L16 83 K18 82 K17 81 K16 80 K15 79 J15 78 J16 77 J17 76 J18 75 H16 74 H15 73 H17 72 H18 71 G17 70 G18 69 G15 68 F16 67 F17 66 E17 63 C18 62 F15 61 D17 60 E16 59 C17 58 B18 57 E15 56 A18 55 A17 54 D16 53 B17 52 D15 51 C16 50 B16 49 Pin Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCLKIN-I/O PWRDN PG223 PQ208 A16 48 D14 47 C15 46 B15 45 A15 44 C14 43 D13 42 B14 41 C13 40 B13 39 B12 38 D12 37 A12 36 B11 35 C11 34 A11 33 D11 32 A10 31 B10 30 C10 29 C9 28 D10 27 D9 26 B9 25 A9 24 C8 23 D8 22 B8 21 A8 20 B7 19 A7 18 D7 17 B6 14 C6 13 B5 12 A4 11 D6 10 C5 9 B4 8 B3 7 C4 6 D5 5 C3 4 A3 3 A2 2 B2 1 GND D4 208 VCC D3 207 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected. In the PG223 package, the following pins are not connected: A5, A6, A13, A14, D18, E1, E18, F1, F18, N1, N18, P1, P18, V5, V6, V13, and V14. *In PQ208, XC3090A and XC3195A have different pinouts. 4-338 June 1, 1996 (Version 2.0) Product Availability Pins 44 Type Code XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A -7 -6 -7 -6 -7 -6 -7 -6 -7 -6 -8 -8 -8 -8 -8 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 -5 -4 -3 -2 -1 -09 64 68 84 100 132 Plast. PGA PP132 Plast. PLCC Plast. VQFP Plast. PLCC Plast. PLCC Cer. PGA Plast.P QFP Plast. TQFP PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 CI C CI C CI C CI C CI C CI C CI C CI C C C C C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI C CI C CI C CI C CI C CI C CI C CI C CI C C CI CI CI CI C C CI CI CI CI C C June 1, 1996 (Version 2.0) CI CI CI CI C C CI CI CI CI C C Plast. VQFP TopBrazed CQFP CI C CI C 144 160 164 Plast. PQFP TopBrazed CQFP Plast. PGA PG132 TQ144 PQ160 CB164 PP175 Cer. PGA CI C CI C C C CI CI CI CI C C CI CI CI CI C C CIMB CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C C C CI CI C C Plast. TQFP CI C CI C CI C CI C CI C 175 CI C Cer. PGA C C CI CI C C CI CI CI CI C C CIMB CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C 208 223 Plast. TQFP Plast. PQFP Cer. PGA PG175 TQ176 PQ208 PG223 CI C C C C MB 176 CI C CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C MB MB CI CI CI CI C C CI CI CI CI C C CIMB CI CI CI C C CIMB CI CI CI C C CI CI CI CI C C CI CI CI CI C C CI CI CI CI C C CIMB CI CI CI C C 4-339 XC3000 Series Field Programmable Gate Arrays Pins 44 Type Code XC3142L XC3190L Notes: 64 68 84 100 132 Plast. PGA PP132 Plast. PLCC Plast. VQFP Plast. PLCC Plast. PLCC Cer. PGA Plast.P QFP Plast. TQFP PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 -3* -2* -3* -2* C C C C Plast. VQFP TopBrazed CQFP 144 160 164 Plast. PQFP TopBrazed CQFP Plast. PGA PG132 TQ144 PQ160 CB164 PP175 Cer. PGA C C Plast. TQFP C C C C 175 Cer. PGA 176 208 223 Plast. TQFP Plast. PQFP Cer. PGA PG175 TQ176 PQ208 PG223 C C * Advance Information C = Commercial, TJ= 0 to +85C M=Military Temp, TC= -55 to +125C I = Industrial, TJ = -40 to +100C B = MIL-STD-883C Class B Ordering Information Example: Device Type Speed Grade XC3030A-3 PC44C Temperature Range Number of Pins Package Type 4-340 June 1, 1996 (Version 2.0) XC3000A Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Product Specification Features Description * The XC3000A family offers the following enhancements over the popular XC3000 family: Enhanced, high performance FPGA family with five device types - Improved redesign of the basic XC3000 FPGA family - Logic densities from 1,000 to 6,000 gates - Up to 144 user-definable I/Os * Superset of the industry-leading XC3000 family - Identical to the basic XC3000 in structure, pin out, design methodology, and software tools - 100% compatible with all XC3000, XC3000L, and XC3100A bitstreams - Improved routing and additional features * Additional programmable interconnection points (PIPs) - Improved access to longlines and CLB clock enable inputs - Most efficient XC3000-class solution to bus-oriented designs * Advanced 0.8 and 0.6 CMOS static memory technology - Low quiescent and active power consumption * Performance specified by logic delays, faster than corresponding XC3000 versions * XC3000A-specific features - 4 mA output sink and source current - Error checking of the configuration bitstream - Soft startup starts all outputs in slew-limited mode upon power-up - Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production. Device XC3020A XC3030A XC3042A XC3064A XC3090A Max Logic Gates 1,500 2,000 3,000 5,000 6,000 June 1, 1996 (Version 1.0) Typical Gate Range 1,000 - 1,500 1,500 - 2,000 2,000 - 3,000 4,000 - 5,000 5,000 - 6,000 CLBs 64 100 144 224 320 The XC3000A family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3000A devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option. The XC3000A family is a superset of the XC3000 family. Any bitstream used to configure an XC3000, XC3100 or XC3100A device configures an XC3000A device exactly the same way. Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 User I/Os Horizontal Configuration Max Flip-Flops Longlines Data Bits 64 256 16 14,779 80 360 20 22,176 96 480 24 30,784 120 688 32 46,064 144 928 40 64,160 4-341 XC3000A Field Programmable Gate Arrays XC3000A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000A Operating Conditions Symbol VCC VIHT VILT VIHC VILC TIN Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. Note: XC3000A DC Characteristics Over Operating Conditions Symbol VOH VOL VOH VOL VCCPD ICCPD ICCO IIL CIN IRIN IRLL Description High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Quiescent FPGA supply current in addition to ICCPD Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Commercial Industrial Min 3.86 Max 0.40 3.76 0.40 2.30 3020A 3030A 3042A 3064A 3090A -10 0.02 Units V V V V V 100 160 240 340 500 A A A A A 500 10 +10 A A A 10 15 pF pF 16 20 0.17 3.4 pF pF mA mA Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA device configured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A. 4-342 June 1, 1996 (Version 1.0) XC3000A Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC3000A Global Buffer Switching Characteristics Guidelines Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Speed Grade Symbol -7 Max -6 Max Units TPID 7.5 7.0 ns TPIDC 6.0 5.7 ns TIO TON TON TPUS TPUF 4.5 9.0 11.0 16.0 10.0 4.0 8.0 10.0 14.0 8.0 ns ns ns ns ns TBIDI 1.7 1.5 ns Note: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator. June 1, 1996 (Version 1.0) 4-343 XC3000A Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y -7 Min -6 Max Min Max Units 1 TILO 5.1 5.6 4.1 4.6 ns ns 8 TCKO 4.5 4.0 ns TQLO 9.5 10.0 8.0 8.5 ns ns 2 TICK 4 6 TDICK TECCK 4.5 5.0 4.0 4.5 3.5 4.0 3.0 4.0 ns ns ns ns 3 5 7 TCKI TCKDI TCKEC 0 1.0 2.0 0 1.0 2.0 ns ns ns 11 12 TCH TCL FCLK 4.0 4.0 113.0 3.5 3.5 135.0 ns ns MHz 13 9 TRPW TRIO 6.0 TMRW TMRQ 16.0 5.0 6.0 5.0 ns ns 17.0 ns ns 14.0 19.0 Notes: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator. 2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 4-344 June 1, 1996 (Version 1.0) XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) T ILO 1 CLB Input (A,B,C,D,E) 2 T ICK 3 T CKI CLB Clock 12 TCL 11 T CH 4 TDICK 5 TCKDI 6 T ECCK 7 TCKEC CLB Input (Direct In) CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 T RIO T CLB Output (Flip-Flop) X5424 June 1, 1996 (Version 1.0) 4-345 XC3000A Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) Speed Grade Symbol 3 -7 Min -6 Max Min Max Units 3.0 14.0 2.5 ns ns ns 4 TPID TPTG TIKRI 1 TPICK 7 7 10 10 9 9 8 8 TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON 5 6 TOOK TOKO 8.0 0 7.0 0 ns ns 11 12 TIOH TIOL FCLK 4.0 4.0 113.0 3.5 3.5 135.0 ns ns MHz 13 15 15 TRRI TRPO TRPO 4.0 15.0 3.0 14.0 12.0 8.0 18.0 6.0 16.0 10.0 20.0 11.0 21.0 24.0 33.0 43.0 ns 7.0 15.0 5.0 13.0 9.0 12.0 10.0 18.0 ns ns ns ns ns ns ns ns 23.0 29.0 37.0 ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input. 4-346 June 1, 1996 (Version 1.0) XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) 3 T PID I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 TOKPO I/O Pad Output (Registered) I/O Pad TS 8 9 TTSON T TSHZ I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK IK (GLOBAL RESET) CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER June 1, 1996 (Version 1.0) = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 4-347 XC3000A Field Programmable Gate Arrays Product Availability PINS 44 64 68 TYPE PLAST. PLCC PLAST. VQFP PLAST. PLCC PLAST. PLCC CERAM PGA PLAST. PQFP PLAST. TQFP PLAST. VQFP PC44 VQ64 PG84 CI C CI C CI C PQ100 CI C CI C CI C VQ100 CI C PC84 CI C CI C CI C CI C CI C TQ100 CI C PC68 CI C CI C CODE XC3020A XC3030A XC3042A XC3064A XC3090A -7 -6 -7 -6 -7 -6 -7 -6 -7 -6 PINS 132 PLAST. CERAM. PLAST. PGA PGA TQFP TYPE CODE XC3020A XC3030A XC3042A XC3064A XC3090A Note: 144 PP132 PG132 TQ144 CI C CI C CI C CI C CI C CI C CI C -7 -6 -7 -6 -7 -6 -7 -6 -7 -6 C = Commercial, TJ = 0 to +85C 84 100 CI C CI C 160 164 175 176 TOPPLAST. PLAST. CERAM. PLAST. BRAZED PQFP PGA PGA TQFP CQFP PQ160 CB164 PP175 PG175 TQ176 CI C CI C CI C CI C TOPBRAZED CQFP CB100 CI C 208 223 PLAST. CERAM. PQFP PGA PQ208 PG223 CI C I = Industrial, TJ = -40 to +100C Ordering Information Example: XC3020A-6PC84C Device Type Speed Grade Temperature Range Number of Pins Package Type 4-348 June 1, 1996 (Version 1.0) Mar XC3000L Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Product Specification Features family is in all respects identical with the XC3000A family, and is a superset of the XC3000 family. * Part of the Zero+ family of 3.3 V FPGAs - JEDEC-compliant 3.3 V version of theXC3000A FPGA family - Logic densities from 1,000 to 6,000 gates - Up to 144 user-definable I/Os * Advanced, low power 0.8 and 0.6 CMOS static memory technology - Very low quiescent current consumption, 20A - Operating power consumption 56% less than XC3000A, 66% less than previous generation 5 V FPGAs * Superset of the industry-leading XC3000 family - Identical to the basic XC3000A in structure, pinout, design methodology, and software tools - 100% compatible with all XC3000, XC3000A, XC3100L and XC3100A bitstreams - Improved routing and additional features * Additional programmable interconnection points (PIPs) - Improved access to Longlines and CLB clock enable inputs - Most efficient XC3000-class solution to bus-oriented designs * XC3000L-specific features - Guaranteed over the 3.0 to 3.6 V Vcc range - 4 mA output sink and source current - Error checking of the configuration bitstream - Soft startup starts all outputs in slew-limited mode upon power-up - Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production Description The XC3000L family of FPGAs is optimized for operation from a nominally 3.3 V supply. Aside from the electrical and timing parameters listed in this data sheet, the XC3000L Device XC3020L XC3030L XC3042L XC3064L XC3090L Max Logic Gates 1,500 2,000 3,000 5,000 6,000 June 1, 1996 (Version 1.0) Typical Gate Range 1,000 - 1,500 1,500 - 2,000 2,000 - 3,000 4,000 - 5,000 5,000 - 6,000 CLBs 64 100 144 224 320 The operating power consumption of Xilinx FPGAs is almost exclusively dynamic, and it changes with the square of the supply voltage. For a given complexity and clock speed, the XC3000L consumes, therefore, only 44% of the power used by the equivalent XC3000A device. In accordance with its use in battery-powered equipment, the XC3000L family was designed for the lowest possible power-down and quiescent current consumption. In mixed supply-voltage systems, the XC3000L, fed by a 3.3 V (nominal) supply, can directly drive any device with TTL-like input thresholds. When a 5 V device drives the XC3000L, a current-limiting resistor (1 k) or a voltage divider is required to prevent excessive input current. Like the XC3000A family, XC3000L offers the following functional improvements over the popular XC3000 family: The XC3000L family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3000L devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option. The XC3000L family is a superset of the XC3000 family. Any bitstream used to configure an XC3000 device configures an XC3000L device the same way. Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 User I/Os Horizontal Configuration Max Flip-Flops Longlines Data Bits 64 256 16 14,779 80 360 20 22,176 96 480 24 30,784 120 688 32 46,064 144 928 40 64,160 4-349 XC3000L Field Programmable Gate Arrays XC3000L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000L Operating Conditions Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC+0.3 0.8 250 Units V V V ns Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. 2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 to 6.0 V range later, when smaller device geometries might preclude operation at 5V. Operating conditions are guaranteed in the 3.0 - 3.6 V VCC range. XC3000L DC Characteristics Over Operating Conditions Symbol VOH VOL VOH VOL VCCPD ICCPD ICCO IIL CIN IRIN IRLL Description High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) High-level output voltage (@ IOH = -4.0 mA, VCC min) Low-level output voltage (@ IOL = 4.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Power-down supply current (VCC(MAX) @ TMAX) Quiescent FPGA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Min 2.40 Max 10 Units V V V V V A 20 +10 A A 10 15 pF pF 15 20 0.17 2.50 pF pF mA mA 0.40 VCC -0.2 0.2 2.30 -10 0.02 Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA device configured with a MakeBits tie option. ICCO is in addition to ICCPD. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L. 4-350 June 1, 1996 (Version 1.0) XC3000L Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC3000L Global Buffer Switching Characteristics Guidelines Description Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -8 Max Units TPID 9.0 ns TPIDC 7.0 ns TIO TON TPUS 5.0 12.0 24.0 ns ns ns TBIDI 2.0 ns 1. Timing is based on the XC3042A, for other devices see XACT timing calculator. 2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices. June 1, 1996 (Version 1.0) 4-351 XC3000L Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y FG Mode F and FGM Mode Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y FG Mode F and FGM Mode Set-up time before clock K Logic Variables A, B, C, D, E FG Mode F and FGM Mode Data In DI Enable Clock EC Hold Time after clock K Logic Variables A, B, C, D, E Data In DI2 Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad)1 RESET width (Low) delay from RESET pad to outputs X or Y -8 Min Max Units 1 TILO 6.7 7.5 ns ns 8 TCKO 7.5 ns TQLO 14.0 14.8 ns ns 2 TICK 4 6 TDICK TECCK 5.0 5.8 5.0 6.0 ns ns ns ns 3 5 7 TCKI TCKDI TCKEC 0 2.0 2.0 ns ns ns 11 12 TCH TCL FCLK 5.0 5.0 80.0 ns ns MHz 13 9 TRPW TRIO 7.0 7.0 ns ns TMRW TMRQ 16.0 23.0 ns ns Notes: 1. Timing is based on the XC3042L, for other devices see XACT timing calculator. 2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 4-352 June 1, 1996 (Version 1.0) XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) T ILO 1 CLB Input (A,B,C,D,E) 2 T ICK 3 T CKI CLB Clock 12 TCL 11 T CH 4 TDICK 5 TCKDI 6 T ECCK 7 TCKEC CLB Input (Direct In) CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 T RIO T CLB Output (Flip-Flop) X5424 June 1, 1996 (Version 1.0) 4-353 XC3000L Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042A) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) 3 -8 Min Max Units 5.0 24.0 6.0 ns ns ns 4 TPID TPTG TIKRI 1 TPICK 7 7 10 10 9 9 8 8 TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON 5 6 TOOK TOKO 12.0 0 ns ns 11 12 TIOH TIOL FCLK 5.0 5.0 80.0 ns ns MHz 13 15 15 TRRI TRPO TRPO 22.0 ns 12.0 28.0 9.0 25.0 12.0 28.0 16.0 32.0 ns ns ns ns ns ns ns ns 25.0 35.0 51.0 ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input. 4-354 June 1, 1996 (Version 1.0) XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) 3 T PID I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 TOKPO I/O Pad Output (Registered) I/O Pad TS 8 9 TTSON T TSHZ I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK IK (GLOBAL RESET) CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER June 1, 1996 (Version 1.0) = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 4-355 XC3000L Field Programmable Gate Arrays Product Availability PINS 44 64 68 TYPE PLAST. PLCC PLAST. VQFP PLAST. PLCC PLAST. PLCC CERAM PGA PLAST. PQFP PLAST. TQFP PLAST. VQFP PC44 VQ64 PC68 PC84 C C C C C PG84 PQ100 TQ100 VQ100 CODE XC3020L XC3030L XC3042L XC3064L XC3090L C PINS 132 TYPE CODE XC3020L XC3030L XC3042L XC3064L XC3090L Note: 84 144 160 PLAST. PGA CERAM. PGA PLAST. TQFP PLAST. PQFP PP132 PG132 TQ144 PQ160 100 164 TOPBRAZED CQFP CB164 TOPBRAZED CQFP CB100 C C 175 176 208 223 PLAST. PGA CERAM. PGA PLAST. TQFP PLAST. PQFP CERAM. PGA PP175 PG175 TQ176 PQ208 PG223 C C C C C = Commercial, TJ = 0 to +85C Ordering Information Example: XC3042L-8VQ100C Device Type Speed Grade Temperature Range Number of Pins Package Type 4-356 June 1, 1996 (Version 1.0) XC3100A Field Programmable Gate Arrays June 1, 1996 (Version 4.1) Product Specification Features Description * The XC3100A is a performance-optimized relative of the XC3000A and XC3100A families. While all families are footprint compatible, XC3100A family extends the typical system performance beyond 85 MHz. * * * * * * Ultra-high-speed FPGA family with six members - 50-95 MHz system clock rates - 190 to 370 MHz guaranteed flip-flop toggle rates - 1.55 to 4.1 ns logic delays High-end additional family member in the 22 X 22 CLB array-size XC3195A device 8 mA output sink current and 8 mA source current Maximum power-down and quiescent current is 5 mA 100% architecture and pin-out compatible with other XC3000 families Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families 100% PCI complaint (A-2, A-1, A-09 speed grade in plastic quad flat pack (PQFP) packaging). The XC3100A family follows the XC4000 speed-grade nomenclature, indicating device performance with a number that is based on the internal logic-block delay, in ns. The XC3100A family offers the following enhancements over the popular XC3000 family. XC3100A combines the features of the XC3000A and XC3100 families. * * * * Additional interconnect resources for TBUFs and CE inputs Error checking of the configuration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More advanced CMOS process The XC3100A family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3100A devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in all XC3000 families, determined by the individual configuration option. The XC3100A family is a superset of the XC3000 families. Any bitstream used to configure an XC3000, XC3000A, XC3000L or XC3100 device, will configure the same-size XC3100A device exactly the same way. Device XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 June 1, 1996 (Version 4.1) Typical Gate Range 1,000 - 1,500 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 CLBs 64 100 144 224 320 484 Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22 User I/Os Horizontal Configuration Max Flip-Flops Longlines Data Bits 64 256 16 14,779 80 360 20 22,176 96 480 24 30,784 120 688 32 46,064 144 928 40 64,160 176 1,320 44 94,944 4-357 XC3100A Field Programmable Gate Arrays XC3100A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100A Operating Conditions Symbol VCC VIHT VILT VIHC VILC TIN Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.25 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. Note: XC3100A DC Characteristics Over Operating Conditions Symbol VOH VOL VOH VOL VCCPD ICCO IIL CIN IRIN IRLL Description High-level output voltage (@ IOH = -8.0 mA, VCC min) Commercial Low-level output voltage (@ IOL = 8.0 mA, VCC min) High-level output voltage (@ IOH = -8.0 mA, VCC min) Industrial Low-level output voltage (@ IOL = 8.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent LCA supply current in addition to ICCPD1 Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Min 3.86 Max 0.40 3.76 0.40 2.30 -10 0.02 0.20 Units V V V V V 8 14 +10 mA mA A 10 15 pF pF 15 20 0.17 2.80 pF pF mA mA Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA device configured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package. 4-358 June 1, 1996 (Version 4.1) XC3100A Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic Units V V V C C C C -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC3100A Global Buffer Switching Characteristics Guidelines Speed Grade -5 Description Symbol Max Global and Alternate Clock Distribution1 Either: Normal IOB input pad through clock buffer 6.8 to any CLB or IOB clock input TPID Or: Fast (CMOS only) input pad through clock TPIDC 5.4 buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) (XC3100) TIO 4.1 (XC3100A) TIO 3.6 T to L.L. active and valid with single pull-up resistor TON 5.6 T to L.L. active and valid with pair of pull-up resistors TON 7.1 T to L.L. High with single pull-up resistor TPUS 15.6 T to L.L. High with pair of pull-up resistors TPUF 12.0 BIDI Bidirectional buffer delay TBIDI 1.4 -4 Max -3 Max -2 Max -1 Max -09 Max Units 6.5 5.6 4.7 4.3 3.9 ns 5.1 4.3 3.7 3.5 3.1 ns 3.7 3.6 5.0 6.5 13.5 10.5 3.1 3.1 4.2 5.7 11.4 8.8 3.1 4.2 5.7 11.4 8.1 2.9 4.0 5.5 10.4 7.1 2.1 3.1 4.6 8.9 5.9 ns ns ns ns ns ns 1.2 1.0 0.9 0.85 0.75 ns Prelim Note: 1. Timing is based on the XC3142A, for other devices see XACT timing calculator. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A devices. June 1, 1996 (Version 4.1) 4-359 XC3100A Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade -5 -4 -3 -2 -1 Description Symbol Min Max Min Max Min Max Min Max Min Max Combinatorial Delay 4.1 3.3 2.7 2.2 1.75 Logic Variables A, B, C, D, E, 1 TILO to outputs X or Y Sequential delay 3.1 2.5 2.1 1.7 1.4 Clock k to outputs X or Y 8 TCKO Clock k to outputs X or Y when Q is returned through function generators F TQLO 6.3 5.2 4.3 3.5 3.1 or G to drive X or Y Set-up time before clock K 2.5 2.1 1.8 1.7 Logic Variables A, B, C, D, E 2 TICK 3.1 1.6 1.4 1.3 1.2 Data In DI 4 TDICK 2.0 3.2 2.7 2.5 2.3 Enable Clock EC 6 TECCK 3.8 1.0 1.0 1.0 1.0 1.0 Reset Direct inactive RD Hold Time after clock K 0 0 0 0 0 Logic Variables A, B, C, D, E 3 TCKI 1.0 0.9 0.9 0.8 Data In DI 5 TCKDI 1.0 0.8 0.7 0.7 0.6 Enable Clock EC 7 TCKEC 1.0 Clock 2.4 2.0 1.6 1.3 1.3 Clock High time 11 TCH 2.4 2.0 1.6 1.3 1.3 Clock Low time 12 TCL FCLK 188 227 270 323 323 Max. flip-flop toggle rate Reset Direct (RD) 3.2 2.7 2.3 2.3 RD width 13 TRPW 3.8 4.4 3.7 3.1 2.7 2.4 delay from RD to outputs X or Y 9 TRIO 1 Global Reset (RESET Pad) TMRW 14.0 RESET width (Low) (XC3142A) 14.0 12.0 12.0 12.0 TMRQ delay from RESET pad to outputs X or Y 17.0 14.0 12.0 12.0 12.0 -09 Min Max Units 1.5 ns 1.25 ns 2.7 ns 1.5 1.0 2.05 1.0 ns ns ns ns 0 0.7 0.55 ns ns ns 1.3 1.3 370 ns ns MHz 2.05 2.15 12.0 12.0 Prelim ns ns ns ns Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and 0.30 ns (-09). 4-360 June 1, 1996 (Version 4.1) XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) T ILO 1 CLB Input (A,B,C,D,E) 2 T ICK 3 T CKI CLB Clock 12 TCL 11 T CH 4 TDICK 5 TCKDI 6 T ECCK 7 TCKEC CLB Input (Direct In) CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 T RIO T CLB Output (Flip-Flop) X5424 June 1, 1996 (Version 4.1) 4-361 XC3100A Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent (XC3100A) Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3120A, XC3130A XC3142A XC3164A XC3190A XC3195A Speed Grade -5 -4 -3 -2 -1 -09 Symbol Min Max Min Max Min Max Min Max Min Max Min Max Units Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) (XC3100A) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) (XC3100A) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100A) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142A) (XC3190A) RESET Pad to output pad (fast) (slew-rate limited) 3 TPID 2.8 2.5 2.2 2.0 1.7 1.55 ns 4 TPTG TIKRI 14.0 2.8 12.0 2.5 11.0 2.2 11.0 1.9 10.0 1.7 9.2 1.55 ns ns 1 TPICK 10.9 11.0 11.2 11.5 12.0 10.6 10.7 11.0 11.2 11.6 9.4 9.5 9.7 9.9 10.3 8.9 9.0 9.2 9.4 9.8 8.0 8.1 8.3 8.5 8.9 7.2 7.3 7.5 7.7 8.1 ns ns ns ns ns 7 TOKPO 7 TOKPO 10 TOPF 5.5 14.0 4.1 5.0 12.0 3.7 4.4 10.0 3.3 3.7 9.7 3.0 3.4 8.4 3.0 3.3 6.9 2.9 10 TOPS 12.1 11.0 9.0 8.7 8.0 6.5 ns ns ns ns ns 9 TTSHZ 9 TTSHZ 6.9 6.9 6.2 6.2 5.5 5.5 5.0 5.0 4.5 4.5 4.05 4.05 ns ns 8 TTSON 8 TTSON 10.0 18.0 10.0 17.0 9.0 15.0 8.5 14.2 6.5 11.5 5.0 8.6 ns ns 5 TOOK 6 TOKO 5.0 0 4.5 0 11 TIOH 12 TIOL FCLK 2.4 2.4 188 2.0 2.0 227 13 TRRI 15 TRPO 15 TRPO 18.0 29.5 24.0 32.0 1.6 1.6 270 15.0 25.5 20.0 27.0 13.0 21.0 17.0 23.0 3.6 0 3.2 0 2.9 ns ns 1.3 1.3 323 1.3 1.3 323 1.3 1.3 370 ns ns MHz 13.0 21.0 17.0 23.0 13.0 21.0 17.0 22.0 14.4 21.0 17.0 21.0 Preliminary ns ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input. 4-362 June 1, 1996 (Version 4.1) XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) 3 T PID I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 TOKPO I/O Pad Output (Registered) I/O Pad TS 8 9 TTSON T TSHZ I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK IK (GLOBAL RESET) CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER June 1, 1996 (Version 4.1) = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 4-363 XC3100A Field Programmable Gate Arrays Product Availability PINS 44 TYPE CODE XC3120/A XC3130A XC3142A XC3164A XC3190A XC3195A Note: 64 68 84 132 100 144 160 164 175 176 208 223 TopTopPlast. Plast. Plast. Plast. Ceram Plast. Plast. Plast. Plast. Ceram Plast. Plast. Plast. Ceram Plast. Plast. Ceram Brazed Brazed PLCC VQFP PLCC PLCC PGA PQFP TQFP VQFP PGA PGA TQFP PQFP PGA PGA TQFP PQFP PGA CQFP CQFP PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223 -5 CI CI CI CI -4 CI CI CI CI -3 CI CI CI CI -2 CI CI CI CI -1 C C C C -09 C C C C -5 CI CI CI CI CI CI CI -4 CI CI CI CI CI CI CI -3 CI CI CI CI CI CI CI -2 CI CI CI CI CI CI CI -1 C C C C C C C -09 C C C C C C C -5 CI CIMB CI CI CI CIMB CI -4 CI CI CI CI CI CI CI -3 CI CI CI CI CI CI CI -2 CI CI CI CI CI CI CI -1 C C C C C C C -09 C C C C C C C -5 CI CI CI CI CI -4 CI CI CI CI CI -3 CI CI CI CI CI -2 CI CI CI CI CI -1 C C C C C -09 C C C C C -5 CI CI CI CIMB CI CI -4 CI CI CI CI CI CI -3 CI CI CI CI CI CI -2 CI CI CI CI CI CI -1 C C C C C C -09 C C C C C C -5 CI CI CI CIMB CI CIMB -4 CI CI CI CI CI CI -3 CI CI CI CI CI CI -2 CI CI CI CI CI CI -1 C C C C C C -09 C C C C C C C = Commercial, TJ = 0 to +85C MB I = Industrial, TJ = -40 to +100C MB MB M = Military, TC = -55 to +125 C B = MIL-STD-883C Class B Ordering Information Example: XC3130A-3PC44C Device Type Speed Grade Temperature Range Number of Pins Package Type 4-364 June 1, 1996 (Version 4.1) XC3100L Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Advance Product Specification Features The XC3100L family follows the XC4000 speed-grade nomenclature, indicating device performance with a number that is based on the internal logic-block delay, in ns. * * * * * * * * * * Ultra-high-speed FPGA family with two members - 50-85 MHz system clock rates - 270 to 325 MHz guaranteed flip-flop toggle rates - 2.2 to 2.7 ns logic delays 4 mA output sink current and 4 mA source current JEDEC compliant 3.3 V version of XC3100A FPGA family The XC3100L is 100% architecture, pin-out and bitstream compatible with the XC3000A, XC3000L and XC3100A families Advanced, 0.6 TLM CMOS technology XC3100L combines the features of the XC3000L and XC3100A families. Additional interconnect resources for TBUFs and CE inputs Error checking of the configuration bitstream Soft startup holds all outputs slew-rate limited during initial power-up More advanced CMOS process The XC3100L family offers the following enhancements over the popular XC3000 family. The XC3100L family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3100L devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in all XC3000 families, determined by the individual configuration option. Description XC3100L is a performance-optimized relative of the XC3000L and XC3100A families. While all families are footprint compatible, the XC3100L family extends the typical system performance beyond 80 MHz. Device XC3142L XC3190L Max Logic Gates 3,000 6,000 June 1, 1996 (Version 1.0) Typical Gate Range 2,000 - 3,000 5,000 - 6,000 CLBs 144 320 Any bitstream used to configure an XC3000, XC3000A, XC3000L or XC3100A device, will configure the same-size XC3100L device exactly the same way. Array 12 x 12 16 x 20 User I/Os Horizontal Configuration Max Flip-Flops Longlines Data Bits 96 480 24 30,784 144 928 40 64,160 4-365 XC3100L Field Programmable Gate Arrays XC3100L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100L Operating Conditions Symbol VCC VIH VIL TIN Description Supply voltage relative to GND Commercial 0C to +85C junction High-level input voltage Low-level input voltage Input signal transition time Min 3.0 2.0 -0.3 Max 3.6 VCC + 0.3 0.8 250 Units V V V ns Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. 2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V. Operating conditions are guaranteed in the 3.0 - 3.6 V VCC range. XC3100L DC Characteristics Over Operating Conditions Symbol VOH VOL VCCPD ICCO IIL CIN IRIN IRLL Description High-level output voltage (@ IOH = -4.0 mA, VCC min) High-level output voltage (@ IOH = -100.0 A, VCC min) Low-level output voltage (@ IOH = 4.0 mA, VCC min) Low-level output voltage (@ IOH = +100.0 A, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent FPGA supply current Chip thresholds programmed as CMOS levels1 Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA175 (sample tested) All pins except XTL1 and XTL2 XTL1 and XTL2 Pad pull-up (when selected) @ VIN = 0 V (sample tested) Horizontal long line pull-up (when selected) @ logic Low Min 2.4 VCC -0.2 Max 1.5 Units V V V V V mA +10 A 10 15 pF pF 15 20 0.17 2.80 pF pF mA mA 0.40 0.2 2.30 -10 0.02 0.20 Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC3190L. 4-366 June 1, 1996 (Version 1.0) XC3100L Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic Junction temperature ceramic -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 +150 Units V V V C C C C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC3100L Global Buffer Switching Characteristics Guidelines Description Global and Alternate Clock Distribution1 Either:Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Longline (L.L.)1 I to L.L. while T is Low (buffer active) T to L.L. active and valid with single pull-up resistor T to L.L. High with single pull-up resistor BIDI Bidirectional buffer delay Speed Grade Symbol -3 Max -2 Max Units TPID 5.6 4.7 ns TPIDC 4.3 3.7 ns TIO TON TPUS 3.1 4.2 11.4 3.1 4.2 11.4 ns ns ns TBIDI 1.0 0.9 ns Advance Notes: 1. Timing is based on the XC3142L, for other devices see XACT timing calculator. 2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices. June 1, 1996 (Version 1.0) 4-367 XC3100L Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Symbol Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct Inactive RD Hold Time after clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset (RESET Pad) RESET width (Low) (XC3142L) delay from RESET pad to outputs X or Y -3 Min -2 Max Min Max Units 1 TILO 2.7 2.2 ns 8 TCKO 2.1 1.7 ns TQLO 4.3 3.5 ns 2 4 6 TICK TDICK TECCK 2.1 1.4 2.7 1.0 1.8 1.3 2.5 1.0 ns ns ns ns 3 5 7 TCKI TCKDI TCKEC 0 0.9 0.7 0 0.9 0.7 ns ns ns 11 12 TCH TCL FCLK 1.6 1.6 270 1.3 1.3 325 ns ns MHz 13 9 TRPW TRIO 2.7 TMRW TMRQ 12.0 2.3 3.1 2.7 ns ns 12.0 12.0 Advance ns ns 12.0 Notes: 1. The CLB K to Q delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2). 4-368 June 1, 1996 (Version 1.0) XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) T ILO 1 CLB Input (A,B,C,D,E) 2 T ICK 3 T CKI CLB Clock 12 TCL 11 T CH 4 TDICK 5 TCKDI 6 T ECCK 7 TCKEC CLB Input (Direct In) CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 T RIO T CLB Output (Flip-Flop) X5424 June 1, 1996 (Version 1.0) 4-369 XC3100L Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch (XC3100L) transparent Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3142L XC3190L Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited)(XC3100L) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast)(XC3100L) same (slew -rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time (XC3100L) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Export Control Maximum flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q) (XC3142L) (XC3190L) RESET Pad to output pad (fast) (slew-rate limited) Speed Grade Symbol -3 Min -2 Max Min Max Units 3 TPID TPTG 2.2 11.0 2.0 11.0 ns ns 4 TIKRI 2.2 1.9 ns 1 TPICK 9.5 9.9 9.0 9.4 ns ns 7 7 10 10 9 9 8 8 TOKPOTOK 5 6 TOOK TOKO 4.0 0 3.6 0 ns ns 11 12 TIOH TIOL FTOG 1.6 1.6 270 1.3 1.3 325 ns ns MHz 13 TRRI 15 15 TRPO TRPO 4.4 10.0 3.3 9.0 5.5 5.5 9.0 15.0 PO TOPF TOPF TTSHZ TTSHZ TTSON TTSON 4.0 9.7 3.0 8.7 5.0 5.0 8.5 14.2 16.0 21.0 17.0 23.0 Advance ns ns ns ns ns ns ns ns 16.0 21.0 17.0 23.0 ns ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized. 4-370 June 1, 1996 (Version 1.0) XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) 3 T PID I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 TOKPO I/O Pad Output (Registered) I/O Pad TS 8 9 TTSON T TSHZ I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK IK (GLOBAL RESET) CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER June 1, 1996 (Version 1.0) = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 4-371 XC3100L Field Programmable Gate Arrays Product Availability PINS 44 64 68 TYPE PLAST. PLCC PLAST. VQFP PLAST. PLCC PLAST. PLCC CERAM PGA PLAST. PQFP PLAST. TQFP PLAST. VQFP PC44 VQ64 PC68 PC84 C C C C PG84 PQ100 TQ100 VQ100 C C CODE XC3142L XC3190L -3 -2 -3 -2 84 100 TOPBRAZED CQFP CB100 Adv. PINS 132 PLAST. CERAM. PLAST. PGA PGA TQFP TYPE CODE XC3142L XC3190L 144 PP132 PG132 -3 -2 -3 -2 TQ144 C C C C 160 164 175 176 TOPPLAST. PLAST. CERAM. PLAST. BRAZED PQFP PGA PGA TQFP CQFP PQ160 CB164 PP175 PG175 TQ176 208 223 PLAST. PQFP CERAM. PGA PQ208 PG223 C C Adv. Note: C = Commercial, TJ = 0 to +85C Ordering Information Example: XC3142L-3PC84C Device Type Speed Grade Temperature Range Number of Pins Package Type 4-372 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products OTP FPGA Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors OTP FPGA Products Table of Contents XC8100 FPGA Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimating XC8100 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Cell (CLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Cell (IOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metastability Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XACTstep Series 8000 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Synthesis Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8100 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8101 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8103 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8106 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC8109 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-3 5-3 5-4 5-4 5-5 5-5 5-6 5-6 5-6 5-6 5-6 5-7 5-9 5-9 5-10 5-10 5-11 5-12 5-13 5-13 5-15 5-15 5-16 5-16 5-16 5-16 5-16 5-16 5-19 5-24 5-24 5-25 5-25 5-26 5-27 5-28 5-29 5-30 5-33 5-42 5-42 XC8100 FPGA Family June 1, 1996 (Version 1.0) Preliminary Product Specification Features Description * The XC8100 family of field programmable gate arrays (FPGAs) provides the same overall benefits as other Xilinx FPGAs: fast time-to-market, reduced design risk, low power, standard product availability, and the use of existing design methodologies. It combines the density of mask gate arrays with the flexibility of programmable logic. Synthesis-targeted sea-of-gates architecture - Efficient results with top-down design - Design without architecture knowledge - Predictable pre-layout timing estimation - Accurate back-annotation - Very high routability - ASIC design flow * Fine-grain architecture - High, predictable utilization: >95% - TrueMap logic mapping * Innovative programmable cell - Combinatorial, synchronous, or three-state - High logic utilization for all designs * Family of devices: 1K-45K usable gates - Same pinout as XC4000 and XC5200 - MicroViaTM antifuse technology * Low power CMOS * System features - JTAG boundary scan - Fast, wide internal decode - On-chip three-state for internal bussing - I/O drive = 24 mA; PCI drive compliant - Slew-rate options to control ground bounce - Modular clock/buffer resources - 5 V, 3.3 V operation * One-time programmable, single-chip solution - Design security - Xilinx and third party programmers - Self-test logic for 100% testability - Automatic post-programming test * XACTstepTM Series 8000 development system - Xilinx unified design entry libraries - Floorplanning, incremental design - High-speed PowerMazeTM router - PC: Windows 3.1/95/NT - WS: Sparcstation, HP PA, RS6000 * Supported by XACTstep Foundation Series The XC8100 family is targeted to be extremely efficient and cost effective when using top-down, technology-independent design methods. The XC8100 employs a new sea-ofgates FPGA architecture. The basic cell is small and was specifically architected for technology-independent design. A new process, the Xilinx MicroVia technology, minimizes the area taken up by the many interconnect elements used in a fine-grain structure. Programmable interconnect elements are stacked vertically between metal layers and are above the logic cells, using significantly less area than other programmable logic technologies. (Note that architectural diagrams in this data sheet do not necessarily show this internal structure). The result is that XC8100 devices have very rich interconnect resources while maintaining cost effectiveness. The XC8100 sea-of-gates architecture delivers high gate utilization, high routability, low cost, and fast design cycles. For high speed, the MicroVia antifuse has a typical on-resistance less than 50 . Like all true FPGAs, as shown in Figure 1, the XC8100 family consists of an array of logic cells and programmable routing resources surrounded by a ring of I/O connections. Unlike most FPGAs, which attempt to offer the "best" fixed cell, the XC8100 logic cells are themselves programmable. They can implement synchronous, combinatorial, or threestate functions. This means the XC8100 software has the flexibility to choose the best cell structure, depending on the logic to be implemented. A design does not have to be evaluated to see if it "fits", but instead can be implemented top-down. Table 1: Product Line Product Max Logic Gates Typical Gate Range Cells Flip-Flops (Max) I/O Note: XC8100 1K .6 - 1K 192 96 32 XC8101 2K 1K - 2K 384 192 72 XC8103 7K 3K - 7K 1024 512 128 XC8106 13K 6K - 13K 1728 864 168 XC8109 20K 9K - 20K 2688 1344 192 XC8112* 27K 12K - 27K 3744 1872 248 XC8116* 36K 16K - 36K 4800 2400 280 XC8120* 45K 20K - 45K 6144 3072 320 * Future product plans June 1, 1996 (Version 1.0) 5-1 XC8100 FPGA Family Active Design Viewer - count32.xb File View Highlight Preferences Row Buffer IOC Horizontal Routing Global Clock Net GCK Pin Cursor Location X1Y4 add_11/U2/I2 (xnor 2) I3 I2 I1 I0 O Cell X5980 Figure 1: XC8100 Architecture in Viewer Window Compared to Xilinx XC2000, XC3000, or XC4000 FPGAs, this architecture has many more cells, each with fewer gates. It also has fewer preconfigured resources -- for example, no flip-flops in the logic cells or in the I/O cells. Routing resources are abundant and there is a very large ratio of interconnects to logic cell inputs and outputs. The architecture's objective is to achieve the highest gate utilization and routability across a diverse set of applications. Unlike Xilinx SRAM FPGAs, which are infinitely reprogrammable, the XC8100 family is one-time programmable (OTP). XC8100 devices use MicroVia process technology, a combination of CMOS, a metal-to-metal antifuse and three layers of metal. Programming is done by Xilinx or third-party programmers, similar to OTP PLDs. There is no need for configuration storage in the target application and design security is very high. 5-2 The XC8100 design flow is exactly like that of an ASIC or gate array. Designs are entered and simulated with thirdparty CAE tools and then placed and routed by Xilinx XACTstep Series 8000 tools. A key feature of the synthesis design flow is that technology mapping occurs in the synthesizer. All instance names, net names, and hierarchy in the EDIF netlist from the synthesizer are maintained by the Series 8000 software. Every logic gate in the design corresponds to a logic gate/CLC in the FPGA. Every net in the design corresponds to a net in the FPGA. Therefore, this information and the associated timings are available for backannotation, simulation and debugging. Figure 2 shows this mapping process - called TrueMap. The XC8100 architecture maximizes the chance that a design will be completed automatically. Because of the architecture and new software written for it, device utiliza- June 1, 1996 (Version 1.0) A B I1 C D n1 I3 n3 D Q Q I4 I2 Clock 3. Applications requiring a single-chip FPGA. These include high security and fast initial power-up operation. Logic Design n1 B A I1 I2 n2 I3 n3 C D Clock I4 XC8100 devices, especially the XC8100 and XC8101, can also implement logic traditionally done in CPLDs, with less than one-tenth the power. Q Portion of Physical XC8100 Chip Security The XC8100 offers a high level of security for designs that are subject to reverse-engineering. The security strategy includes the software, the IC architecture, and the process. X5776 Figure 2: TrueMapTM Logic Mappings tion does not degrade when technology independent design entry is used. Designs can be entered in HDLs with little concern for the IC architecture. With the very high probability of routing, different logic implementations can be accurately evaluated before place and route. The Series 8000 software allows user control, primarily for maximizing the speed of the design. High level floorplanning works with constraints based on hierarchical block names. The fast PowerMaze router makes incremental design easier. The router can route a fully-utilized XC8106 in less than one minute - in most cases in only seconds. Applications The XC8100 family is targeted at three primary applications: 1. High-level design language (HDL) using logic synthesis. The architecture was developed to give very high gate utilization and low cost when designs are entered with a technology-independent methodology. Most synthesis algorithms were originally designed for gate arrays, and they are sub-optimal for the different architectures used in FPGAs and complex PLDs. The XC8100 architecture was specifically designed to fit the logic implementations that are produced by synthesis algorithms. During development, architectural simulations were run using actual synthesis products. The XC8100 programmable cell and design library were chosen to give cost-effective results when using logic synthesis. The XC8100 software is very ASIC-like and gives accurate estimations when synthesizing and evaluating architectural tradeoffs before place and route. 2. General logic applications, especially telecommunications and industrial control. The XC8100 offers high and predictable utilization over a wide range of logic functions. It can handle designs that are heavily synchronous or heavily combinatorial. Since the architecture delivers "usable gates" irrespective of the target application, designs can be quickly entered and results will be predictable. There is no need to analyze the target design for flip-flops, latches, three-states, etc., to determine how well the design "fits." June 1, 1996 (Version 1.0) The XC8100 software automatically stores design information (.xb file) in a compressed and encrypted file format. In addition, there is an optional password capability that only allows the design file to be used for programming, not for viewing or writing or manipulating. In other words, the password-protected design file can be given out for device programming while still maintaining security. XC8100 devices receive programming information through the JTAG (boundary scan) port and data registers. While this information can be read back for factory testing purposes, these JTAG instructions are not documented. The user can program a bit which defeats the JTAG test/programming readback instructions, thereby eliminating this form of reverse engineering. The third part of the security strategy involves the process. The physical implementation of a design occurs by programming the desired connection pattern. The connection is formed by creating a metal filament through a layer of amorphous silicon. Only a small percentage of the antifuses are programmed. In a typical design in the XC8106, about 2% of the approximately 700,000 antifuses will be programmed. The functionality of the design can only be copied by knowing exactly which of the antifuses were programmed. The antifuses are located between the second and third layer of metal. This means that programmed and unprogrammed antifuses are covered by a layer of metal and a protective passivation layer. It is impossible to distinguish programmed antifuses from unprogrammed antifuses by inspection of the top of the chip. Attempts to remove the protection and metal layers will certainly result in damage or removal of the conductive filament between the metal layers. Moreover, antifuses, whether programmed or unprogrammed, are difficult to distinguish from regular, permanent connections between the second and third layers of metal (vias). Note that this is different from a gate array, where vias only exist where connections are intended. In the XC8100, vias, programmed antifuses, and unprogrammed antifuses all exist simultaneously. Another method of reverse engineering is hot spot analysis, which relies on distinguishing programmed from unprogrammed fuses by investigation of heat dissipation. Since 5-3 XC8100 FPGA Family - the on-resistance of the programmed antifuses is very low, the heat dissipation is very low also. This makes this technique useless for determination of the state of the antifuse. - Performance Overview flexible CLC - many flip-flops possible - allows pipelining cascade High drive outputs specified for 50 pF XOR2 The XC8100 family has been benchmarked with many actual customer designs running synchronous clock rates of 20-40 MHz (-1 speed grade). The performance of any design depends on the type of circuit implemented, including the delay through the combinatorial and sequential logic elements plus the delay in the interconnect routing. Figure 3 shows some performance numbers for representative circuits, using worst case timing parameters. A rough estimate of timing can be made by assuming 6 ns per logic level. This includes 3 ns for the CLC delay and 3 ns for the routing delays. More accurate estimations can be made using the information in the next section. 175 MHz 150 100 16-bit Loadable Shift Register 75 (-1) (-3) 16-bit Johnson Counter 16-bit Prescaled Counter 50 16-bit Loadable Counter 25 16-bit Accumulator Complexity X5935 Figure 3: Representative Circuit Performance Function 16-bit decoder from input pads (delay from strobe) (delay for full decode) 16-to-1 multiplexer 16-bit loadable shift register 16-bit Johnson counter 16-bit prescaled counter 16-bit loadable counter 16-bit accumulator XC8100 Performance -1 -3* 5.1 7.9 14.2 172 161 125 77 41 ns ns ns MHz MHz MHz MHz MHz The XC8100 architecture and software are architected to deliver the maximum device performance when using synthesis CAE tools. This is possible due to: 5-4 net n63 X5810 Figure 4: Example Path Delay Calculation Estimating XC8100 Timing Accurate timing estimates prior to place and route are necessary when exploring a design space with synthesis tools. This allows the synthesizer to make the proper speed/area trade-offs without leaving the synthesis environment (i.e. without going through a full place and route cycle). The timing estimates for the XC8100 architecture are accurate to within 10% of the post place and route numbers. This high correlation between pre- and post- timing numbers is a result of the following architecture and design flow features: * 7.6 11.7 18.8 148 109 91 51 28 *Advance Information - FD I0 Like an ASIC or FPGA, XC8100 circuit timings depend on the actual layout (placement and routing) of the design. XC8100 software calculates the timing using a very accurate SPICE-like timing model. However, prior to layout actual circuit performance can be estimated. This is done automatically by synthesis tools using the XC8100 library and can be done manually using information in this data sheet. 200 125 SOP3 AND8 CLC designed to fit synthesis algorithms predictable prelayout timing for accurate synthesis block-level hierarchical floorplanning buffer resources for high fanout nets or critical signals * * No logic mapping - the placed and routed design matches the synthesized design netlist exactly. There is no technology mapping phase where logic gates from the design netlist are mapped into different physical gates on the chip. All cell delays are built into the synthesis library. This, in conjunction with point 1, means that all cell delays used in the synthesis tool are preserved in the final chip. The wire load model is well characterized. The abundant routing in the architecture increases the likelihood of direct routes between CLCs rather than circuitous paths. This reduces the standard deviation of the estimated versus actual net delays. The timing for the XC8100 is modeled with two elements: the cell delay and a fanout-dependent net delay (wireload model). Cell delay timings for most of the primitive library elements are shown in the AC Timing section of the data sheet. For example, the data sheet shows four numbers for the AND4 primitive. Worst-case numbers are worst-case voltage, worst-case temperature, worst-case process, and June 1, 1996 (Version 1.0) worst-case falling or rising edge. Note that the XC8100 library has input-to-output numbers, both rising and falling edges, for all pins. Synthesis software will automatically take advantage of the fastest pin if required, and schematic users can do this manually. Pre-layout net delays are modeled as a function of fanout and can be estimated by using Table 2. Note that various buffers, as explained later, can be used to limit the delay of wide fanout nets. Table 2: Pre-Layout Net Delays vs. Fanout mine the cell logic functions, I/O functions, and the interconnections. Programmable Cell (CLC) The XC8100 implements combinatorial and sequential logic by configuring and interconnecting identical Configurable Logic Cells (CLC). Each CLC is equivalent to 3.25 "LSI-Logic gates." This figure was derived by synthesizing a range of designs first to the XC8100, and then to an LSI Logic library. Architecture In order to allow the widest range of logic - combinatorial, synchronous, and three-state - to map efficiently to the XC8100 architecture, CLCs are internally programmable. While this is also true of Xilinx SRAM FPGAs, other antifuse FPGA architectures have fixed cell structures with only programmable interconnect. A programmable cell ensures that logic will more frequently fit efficiently into a cell. The cell is programmable as to: input inversions, combinatorial function choice, synchronous logic internal feedback path, three-state, and cascade enable. The XC8100 software automatically configures the cell based on the user's design netlist. The variety of building blocks means a higher device utilization for a range of logic functions. Xilinx field-programmable gate arrays are comprised of three major configurable elements: configurable cells, input/output blocks and interconnections. The cells provide the functional elements for constructing the design's logic. The I/O cells provide the interface between the package pins and internal signal lines. The programmable interconnect resources provide routing paths to connect the inputs and outputs of the cells and I/O blocks onto the appropriate nets. In the XC8100, user configuration is established by one-time programming of MicroVia antifuses that deter- Figure 5 shows the different possible implementations of a single CLC. Each CLC has four logic inputs plus a cascade input, and one logic output plus a cascade output (cascade not shown). The logic output has three-state control, and each CLC is also connected to a global reset network. Each of the four inputs can be configured as inverted or non-inverted, so input signal inversions ("bubbling") are free and output bubbles don't matter. Cells do not have to be "wasted" as inverters, which would lower the gate utilization. Any input can be hardwired to logic zero or one. Fanout 1 2 3 4 n Net Delay (ns) (-1) 1.2 2 3 4 n For example, in Figure 4, net n63 has a fanout of 3, so the estimated delay (-1 speed grade) from the I0 input of the AND8 to the D input of FD is: 3.0 + 3 = 6.0 ns. SOP Combinatorial Logic AND I3 I3 I2 I2 O O I1 I1 I0 I0 O = I3 * I2 + I1 * I0 O = I3 * I2 * I1 * I0 D Latch Three-State Logic I D G Q O Programmable Inversion Note: Cascade not shown E X5811 Figure 5: Programmable Cell June 1, 1996 (Version 1.0) 5-5 XC8100 FPGA Family For combinatorial logic, the cell has two programmable functions, AND or Sum-of-Products (SOP). Pairs of CLC inputs are internally ANDed, and the two signals are then combined in a circuit programmable as either an OR or an AND gate. The SOP can also be considered a 2-input multiplexer, or a 2-input XOR and XNOR. For synchronous logic, configuring the cell-internal feedback path makes any CLC a latch with D and G inputs (LD primitive). When G is high, the latch is in the pass-through state. Both inputs can be configured to be either active High or active Low. A two-cell latch (LDC primitive) adds an asynchronous CLR input. All latches are also controlled by the global Reset signal. The XC8100 software automatically combines two adjacent latches through the Cascade connection to create a D-flipflop. One CLC is the master latch and the second is the slave latch. The flip-flop has a global Reset which does not involve user routing and also has an overriding asynchronous Clear input (FDC primitive). It can also have an asynchronous Preset input that overrides the D input (FDP primitive). Note that neither the feedback connections of both latches nor the master-slave connection use general routing elements, or have programming elements in their paths. This gives the flip-flops excellent speed and metastability behavior. The XC8100 "semi-dedicated" flip-flops combine performance with flexibility in utilization. For three-state logic, one of the CLC inputs controls a tristate buffer in the output path (BUFE primitive). The Data and Enable control inputs can be configured active High or active Low. Combining the latch and three-state functions gives a register file capability (LDE4 primitive) which can be used to build FIFOs, see Figure 6. Q0 D1 Q1 D2 D3 Q2 Q3 G A master reset of the chip is accomplished by pulling the MR pin low. This starts the power-on reset sequence, presetting all asynchronous preset flip-flops (FDP) and resetting all other flip-flops and latches. The master reset locks out the device for several ms. See the AC timings. The primary use of the master reset is as part of a system, board or module reset. Cascade Each CLC has a fifth input and second output for cascade. The cascade inputs and outputs use dedicated routing to the nearest cells, extending along an entire row. See Figure 8. Combining two adjacent CLCs through their cascade connection expands the functionality. For synchronous logic, cascade is used to automatically build flip-flops, as explained earlier. For combinatorial functions, the software cascades CLCs to build the wider ANDs and SOPS in the primitive library. Cascade can also be used (with ANDCC and SOPCC primitives) to build functions like wide decode and fast shift registers. The cascade connection has several advantages over conventional routing: * * * It is faster because it doesn't need a programmable element and it avoids the delay of the cell output driver. It has known timing. It does not consume any general routing resources. Address Decoders Programmable Interconnect LDE4 X5632 Figure 6: Quad Latch Bank with Three-State Output Uses Four CLCs Global Reset A global reset signal is automatically distributed to each CLC latch, and therefore each flip-flop. It is controlled internally by the GRST library primitive. It is activated automatically on power-up. When active, the net presets all asynchronous preset flip-flops (FDP primitive) and resets all other flip-flops. In the case of the latches, the clear only takes place when the latches are in the latching state. In 5-6 Master Reset The cascade can be used to build wide decode functions. See Figure 7. For example, five CLCs, each configured as a four-input AND gate, can feed a CLC configured as a four-input AND with cascade (ANDCX). The delay for this 20 input decoder is less than 12 ns. Using two-CLC AND8 primitives produces a forty-input decoder that has a delay less than 15 ns. If the address is available, the strobe delay is about 8 ns (-1). E D0 other words, reset does not affect the output in passthrough mode. Global reset is typically complete within 100 ns. See AC timings. Most programmable logic devices have to balance routing/ interconnect resources with die size and cost. However, the XC8100 architecture offers a small die size with an abundant amount of routing, both metal-segment wires and interconnections. The routing software has many alternatives to make sure a design is fully routed. Figure 8 is an example diagram of the interconnect, showing only the wires actually used for nets in a design. In the horizontal direction, there are 47 wires that each cell can connect to (not all shown in Figure 8). There are 5 separate types, three of which can also be connected horizontally: June 1, 1996 (Version 1.0) ANDXC ANDXC AND8 8 Net uses cascade AND4B1 AND4B1 Address Bits AND4 8 ANDCXB1 IBUF AND4 ANDCX 8 AND8 ANDCX AND8 AND4B2 8 Strobe AND4 AND4 Address Bit AND8 8 IBUF 6 CLCs AND8 11 CLCs X5812 Figure 7: Wide Decode Using Cascade * * * * * single-block (a block is 4 cells wide) length wires extend for one block only. They are used primarily to connect the cells within the block. double-block length wires connect left and right to adjacent blocks. quad-block length wires connect left and right for a length of four blocks. They can connect any cells that are spanned within the four-block length. horizontal long lines run the entire width of the device. They can connect any cells in a row. These wires are optionally used by the row buffers. constant 0 used for logic 0 and 1 inputs. There are two wire types in the vertical direction: * * double-block length wires, analogous to the horizontal ones. quad-block length wires. In addition to the wires that run along all the rows and columns of the device, there are twelve vertical long lines (VLLs) on each side of the device. They interconnect with any horizontal wire and make routing with preassigned I/Os easier. Global Nets Global nets are those needing optimized timing or low skew for the distribution of clock, time-critical and/or high fan-out control signals. The XC8100 has dedicated hardware resources for this purpose. The XC8100 system is very flexible since the various buffers can be used independently or together, for clocks or data. See Table 3, Figure 9, and Figure 10. Four package pins, GCK1-4, feed four dedicated high drive buffers (BUFEDGE) that drive four vertical long lines (not part of the general lines described in the Programmable Interconnect section) on two sides of the device. If the GCK pins are not used, they are available for user I/O. Each pair of rows of CLCs also has four dedicated buffers (BUFROW). To limit fanout, the XC8100 software can also use CLCs as buffers (BUF1X primitive). These buffers can be automatically selected by the synthesis software. Cascade CLC I I I I O CLC I I I I CLC I I I I O CLC I I I O Horizontal Routing Clock Net I I I I CLC I I I I O CLC I I I I O CLC I I I I O CLC Cascade Vertical Routing X5813 Figure 8: Example Routing Detail June 1, 1996 (Version 1.0) 5-7 XC8100 FPGA Family Table 3: XC8100 Buffers Name BUFGP Description This global buffer is formed by a BUFEDGE driving some number of BUFROWs. The source for this buffer is one of four specific external pins, GCK1 - 4. The output of the buffer can drive all CLCs in a chip. The maximum number of BUFGP buffers is four. BUFGS This can be thought of as an internal BUFGP. It is accessible internally and can drive any number of BUFROWs. BUF1X This buffer is formed by using a single CLC. It has the same drive and fanout characteristics as the CLC. It can be automatically selected by synthesis tools to limit fanout in critical paths. BUFROW This is a dedicated high drive buffer whose output drives all CLCs in the driven row. The input to this buffer is from a CLC or from external pads through IBUF cells. Using this buffer automatically constrains the placement of the driven CLCs to the row. Each BUFROW drives two rows of CLC/FFs: XC8100 48 CLCs (24 FFs) XC8101 48 CLCs (24 FFs) XC8103 64 CLCs (32 FFs) XC8106 96 CLCs (48 FFs) XC8109 112 CLCs (56 FFs) GCK Pin GCK Pin BUFEDGE BUFEDGE CLC BUFROWs BUFROWs CLC BUFROWs BUFROWs GCK Pin BUFEDGE BUFEDGE GCK Pin X5623 Figure 9: XC8100 Buffer Configurations 5-8 June 1, 1996 (Version 1.0) BUFGP Global Buffer There are four BUFGP buffers in each XC8100 device. They are only driven by the four external GCK pins. BUFGP is the low-skew global clock driver, and should be used for any high-fanout net, as it can connect to all input pins on all CLCs. To use the BUFGP, either add the BUFGP symbol to your schematic, instantiate the BUFGP primitive in your HDL code, or see the XACTstep Series 8000 User Guide for information on directing synthesis tools to automatically include the BUFGP. GCK BUFROW Row Buffer IBUF O There are four BUFROW buffers for every two rows of CLCs, two on each end. The BUFROW can only drive the inputs of CLCs in the two rows adjacent to the BUFROW. Any CLC in any row can drive the input to the BUFROW. Using the BUFROWs as individual clock drivers allows more than four different clocks in a design. The above figure shows two BUFROW examples; one BUFROW driven by an IBUF input buffer, the other BUFROW driven by an internal CLC. BUFGS Secondary Global Buffer O BUFGS is a library primitive that utilizes BUFROWs to form a global low-skew driver. The BUFGS can drive any number of CLCs, since it uses a BUFROW to drive the CLCs in each row. If there are no driven CLCs in a row, then no BUFROW is used in that row. Like the BUFROW, the BUFGS can be driven by a CLC (shown above) or by an IBUF input buffer. X5936 Figure 10: XC8100 Buffer Usage Input/Output Cell (IOC) Input The IOCs form the interface between the internal logic and the I/O pads of the device. Each IOC consist of a programmable output section that drives the pad, and a programmable input section that receives data from the pad. See Figure 11. Aside from being connected to the same pad, the input and output sections have nothing else in common. The input section receives data from the pad or the JTAG circuitry and passes it to the interconnect structure. Inputs can be globally programmed for TTL or CMOS input thresholds. TTL is the default. There are two input buffer timing specifications. The faster one is selected by using the IBUF library element, while a delayed timing is available with the DBUF library element. The DBUF is used for the data signal to guarantee zero hold time if data and clock signals are going from external pins to an internal flip-flop. June 1, 1996 (Version 1.0) 5-9 XC8100 FPGA Family Pull-up Resistor Each I/O pad can be programmed with or without a pull-up resistor. This selection is independent of the IOC usage. The default is for the software to automatically program the pull-up resistor to prevent a floating input. The pullup is about 50K ohms. Output The output section takes data and three-state control information from the interconnect structure. It can also take data from the JTAG scan circuitry. Output data can be inverted or non-inverted. The output driver has four options: 1) it can be permanently disabled, making the pad an input-only pad (IBUF, DBUF primitives); 2) the driver can be permanently active, making the pad output only (OBUF, RBUF primitives); 3) it can be three-state controlled from either the internal logic or the JTAG circuitry (OBUFE, RBUFE primitives): or 4) a combination (IOBUF). The three-state control signal can be inverted, allowing the signal to be thought of as either active Low Output Enable, or active Low three-state. The outputs are CMOS compatible, which results in an unloaded rail-to-rail signal swing. Each output can be individually configured for either of two slew-rate options, which affect only the pull-down operation. See Figure 12. When programmed for resistive mode (RBUF, RBUFE primitives), the pull-down transistor is driven hard, resulting in a practically constant on-resistance of < 20 . This results in the fastest High-to-Low transition, and the capability to sink up to 24 mA. Resistive mode is required for driving terminated transmission lines with 4 to 24 mA of dc sink current and for highly capacitive loads (>200 pF). When many resistive mode outputs switch simultaneously High to Low, this configuration option may result in excessive ground bounce. The user must limit the number of simultaneous transitions per package ground pin - see the DC specification section. The slew rate limited configuration is capacitive mode (OBUF, OBUFE). This mode uses a novel, patent-pending method of slew rate control that reduces ground bounce without any significant delay penalty. The High-to-Low transition starts as described above, but the drive to the pulldown transistor is reduced as soon as the output voltage reaches a value around 1V. This results in a higher resistance in the pull-down transistor, a slowing down of the falling edge, and significantly reduced ground bounce. In this mode the output driver sinks 4 mA at VOL. This mode is recommended for outputs requiring less than 4 mA DC or for capacitive loads of less than 200 pF. See Figure 13 for typical output V/I characteristics. OUTPUT INTEST/ EXTEST Programmable Inversion 3-State TS Slew Rate Pull Up VCC TS/OE TS - Capture JTAG TS - Update Programmable Inversion Output Data O ESD O - Capture CMOS Output Buffer PAD JTAG O - Update ESD INPUT Input Data I CMOS/TTL Input Buffer I - Update JTAG I - Capture Figure 11: Input/Output Cell Diagram 5-10 Resistive/capacitive modes selectable on a pin basis Globally selectable X5775 June 1, 1996 (Version 1.0) Resistive Mode "Sharp Pull Down" 4 mA < IOUT (DC) < 24 mA VCC VOLmax 0.5 V Capacitive Mode "SoftEdge" IOUT (DC) < 4 mA VCC VOLmax 0.5 V Gnd Gnd t TR t TR >TC TC RBUF, RBUFE, IRBUF, DRBUF OBUF, OBUFE, IOBUF, DOBUF X5814 Figure 12: Output Slew Rate Options IEEE 1149.1 Boundary Scan The XC8100 has similar IEEE 1149.1/JTAG (Joint Test Action Group) capabilities as the XC4000. Three differences are that: * * * The XC8100 JTAG pins TDI, TDO, TMS and TCK are dedicated. The XC8100 supports the JTAG instruction IDCODE. The XC8100 instruction word length is 10 bits. JTAG is an industry-standard serial access interface designed to provide an efficient and convenient means of testing and monitoring integrated circuit components on a circuit board. It was designed to provide an alternative to the traditional bed-of-nails circuit board testers which have difficulty accommodating high pin count, fine pitch component packages, and which are unable to support surface mount boards with components on both sides. In the XC8100, the JTAG interface both serves its traditional board testing role and is also the primary test and antifuse programming interface. Virtually all factory test and programming operations are accessed via the JTAG interface. The 1149.1 interface consists of four pins, TDI, TDO, TCK, and TMS. The basic concept is that the TDI and TDO pins form the beginning and end of serial shift registers within the device. See Figure 14. TCK and TMS provide a means to select a specific shift register and when and what to shift. Resistive Mode Capacitive Mode 20 0000000001 1111111101 1111111110 Instruction INTEST/ EXTEST SAMPLE USERCODE IDCODE Description Forces state of I/O cells Samples state of I/O cells User-programmable register Samples existing device code 1111111111 BYPASS Selects bypass register INTEST/EXTEST This instruction combines the mandatory JTAG EXTEST with the optional INTEST instruction. When selected, this instruction uses the JTAG boundary scan register values to: * * * Drive the signal at the output of the input buffer (INTEST) Drive the data input of the output buffer (EXTEST) Drive the enable input of the output buffer (EXTEST) SAMPLE 40 I OL mA 30 Instruction Code 0000000000 To do this, the signals which normally drive these nodes are disabled via multiplexers. 4.5 V, 90C, 1 Output 60 50 In order to provide control of the JTAG data registers, the JTAG specification includes a definition of what is called the test access port (TAP) controller. Since there are only two pins to control it, the TAP controller is designed as a state machine with one input, TMS. The XC8100 TAP controller is clocked by the TMS pin and uses the standard IEEE JTAG state diagram.The XC8100 provides the full set of IEEE 1149.1 boundary scan instructions, including the optional IDCODE. See the following Table: 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VOL Volts 4.5 V, 90C, 1 Output 40 This instruction samples the logic values at each pin. For a bidirectional I/O pin, three values are sampled: * * * The signal at the output of the input buffer The signal at the data input of the output buffer The signal at the enable input of the output buffer IDCODE 30 I OH mA 20 10 3.0 3.5 VOH Volts 4.0 X5777 This instruction provides access to a 32-bit data register that always captures a 32-bit word built into the device. The register can be read by the programming software. See Figure 15. Figure 13: Typical Output V/I Characteristics June 1, 1996 (Version 1.0) 5-11 XC8100 FPGA Family Power Consumption Test/Programming Registers The XC8100 has the power consumption characteristics of Xilinx CMOS FPGAs. There are two components to the power. DC quiescent power is low and almost all of the power dissipation is a function of the design speed, the number of nodes toggling, and the capacitive loading on the outputs. Boundary Scan Register ID Code Register (32 bits) Quiescent current can be minimized by attention to its six sources: TDO MUX TDI User Code Register (32 bits) 1. Using the TTL input voltage mode draws current of about 8 mA to 30 mA, worst case, depending on the device, the package, and the voltage state of the input pins. There are two components to this current. First, the reference circuit draws 8 mA worst case, 4 mA typical, independent of device. Second, each I/O pin will draw about 100 A worst-case if the input to the pin is held at DC low. Therefore this component depends on the circuit and the package (number of I/Os available). Both components are eliminated by selecting CMOS input levels (2.2 V trip point). At 3.3 V operation, the input level must be CMOS, so this source of current is not applicable. Bypass Register (1 bit) Instruction Register (10 bits) TMS TCK TAP Controller X5626 Figure 14: XC8100 IEEE 1149.1 Architecture In hex, the IDCODEs are: XC8100 XC8101 XC8101 XC8103 XC8103 XC8106 XC8106 XC8109 -- 1X 2X 1X 2X 1X 2X 2X X7E90093 X7E94093 X7E95093 X7E9C093 X7E9D093 X7EA8093 X7EA9093 X7B58093 2. Pulling down an I/O pin with the weak pull-up transistor enabled draws about 50 A per pin at 3.3 V, 100 A per pin at 5 V. The weak I/O pull-ups are automatically enabled by the design software (although they are automatically turned off when an I/O is driven by the FPGA). They can be disabled within the Series 8000 software by the command: set_attribute -port my_input_pin pullup false. USERCODE 3. Leaving a non-pulled up I/O pin floating can produce a worst-case current of about 0.5 mA per pin at 3.3 V, 1mA per pin at 5 V. This occurs when the input voltage is at the I/O trip point. To eliminate this source of quiescent current, do not allow non-pulled up pins to float. Remember the default is that all I/Os have pull-ups. The JTAG TCK pin, which by the IEEE specification may not have a pullup or pulldown, must be connected to VCC or GND to eliminate it as a source of quiescent current. This instruction provides access to a 32-bit data register which can be programmed by the user, for example with the design version. BYPASS This instruction places a single flip-flop between TDI and TDO. Its capture value is 0. The Boundary Scan Register bits are shown in the pinout tables (The pinout tables section begins on page 25). There are three bits for each I/O pin. The bits are TS, O, and I, as shown in Figure 11, with TS closest to the TDO end. There is a fourth bit for the four GCK/I/O pins. 4. MicroVia leakage current depends on the design and is not under user control. It is typically very small and can be calculated after the design is placed and routed. Series 8000 software has a command (report LSB MSB 31 28 27 Part Number Version XXXX X 14 13 12 11 0111 7 X 1110 E 8,106 1010 A Family Code 10 00 0 1 0 Manufacturer ID 0000 0 1001 9 001 3 1 Xilinx = 147 X5633 Figure 15: XC89106 IDCODE Register 5-12 June 1, 1996 (Version 1.0) stress_factor) that shows the number of antifuses to be programmed in the design and the number of "critical" antifuses. Critical antifuses are those which have the potential of being between two active and different nets. Only these antifuses can contribute to quiescent current. The worst-case theoretical MicroVia leakage current, assuming all critical antifuses have opposite logic potential on their terminals, is calculated by multiplying each critical antifuse by 100 pA at 3.3 V, 10 nA at 5 V. On small designs (XC8100, XC8101) this number is typically less than a few hundred A, worst case temperature and 5.25 V. At room temperature, 5.0 V, the MicroVia leakage would be about an order of magnitude less. 5. CMOS leakage current is proportional to the device and is not under user control. It is typically a few A. Current (May 96) test limits are a few mA for the XC8106 at 5 V with other devices proportionally less or more. 6. A small current is used by an internal voltage detector on the VPP pin. With VPP tied to VCC, this current is about 100 A at 5 V, 30 A at 3.3 V. A larger current exists if VPP is tied to ground. A minor enhancement is scheduled for 2H 1996 to eliminate this source of current. Attention to these factors can result in a typical quiescent current of a few As for small designs at 3.3 V. Almost all power is dynamic, and is determined by the number of nodes, their capacitance, and the frequency they are discharging and charging. This number is very design dependent, especially on the number and frequency of inputs that are toggling, not just the circuit implementation in the FPGA. Figure 16 is a test design that illustrates the power consumption of an XC8106 at 5 V and 3.3 V. The design uses 1550 CLCs (90% of the XC8106), with 10% sequential logic and 90% combinational. All outputs are unloaded. The design consists of a 16-bit counter, a 16-bit 4-to-1 MUX, and a 16-bit multiplier. The select lines, by controlling one of the multiplier inputs, determine the number of nodes that switch. 3.3 V Operation XC8100 devices can be operated at 5 V or 3.3 V. At 3.3, the timing parameters are derated (see "Device Specifications" on page 33). I/O pins cannot be directly driven above VCC, although there are standard resistor solutions. The CMOS/ TTL input voltage choice should be set in the software to CMOS. Programming Programming XC8100 FPGAs is supported by several methods: 1) the Xilinx HW-130 Programmer; 2) selected third-party programmers; 3) distributors; and 4) Xilinx for volume designs. Series 8000 software has a Demo Mode where no key is needed. The software can be copied for programming XC8100 devices in parallel using multiple PCs or workstations. Another option is to run multiple Windows 95 sessions to multiple serial ports. On the device, only 5 pins are required for the programming interface. The JTAG pins TDI, TDO, TCK, and TMS are used for addressing the elements to be programmed, for shifting the programming data in, for verification, and for testing. The Vpp pin provides a high voltage during programming and is used to measure the resistance of the programmed antifuse. XC8106 5.0 V Current Consumption 350 Sel-00 Sel-01 16 +1 Current (mA) 300 (15:0) Sel-10 Sel-11 250 200 150 100 50 32 32 0 32 * Clk 10 0 Output 20 Frequency (MHz) 30 40 XC8106 3.3 V Current Consumption 140 Sel Sel-00 Sel-01 120 Clk Current (mA) (15:0) 11 (0:15) 10 16 01 FFFF 0002 00 Sel-10 Sel-11 100 80 60 40 20 0 Figure 16: XC8106 Example Design June 1, 1996 (Version 1.0) 0 5 10 15 20 Frequency (MHz) 25 30 X5839 5-13 XC8100 FPGA Family Series 8000 Design System File Edit Place/Route Analysis Program Help Initializing design data-base for 36 rows by 48 columns... cmd> factory_test_suite Requesting programmer on serial port /dev/ttya, 19200 baud... Found HW-130 Running factory tests... Power-up Current Test: ID Code Power-Up Test: ID Code Test: Metal Data Register Test: Metal Test: VP Line Short Test: CCU Loop Test: CCU Chain Test: CCU Capture Test: Constant Zero Test: TTL Bit Test: Boundary Scan Test: Row Buffer Test: Edge Buffer Test: Intest-In Test: Output Test: Input Test: PROM Test: CLC Test sop4 61 00 0: CLC Test sop4 61 03 1: CLC Test sop4 61 0a 0: CLC Test sop4 61 0c 1: CLC Test sop4 61 05 0: CLC Test sop4 61 0f 1: CLC Test and4 21 00 0: CLC Test and4 21 01 0: CLC Test and4 21 03 0: CLC Test and4 21 07 0: CLC Test and4 21 0f 1: CLC Test and4b1a 31 01 0: CLC Test and4b1a 31 0e 1: CLC Test and4b1b 29 02 0: CLC Test and4b1b 29 0d 1: CLC Test and4b1c 25 04 0: CLC Test and4b1c 25 0b 1: CLC Test and4b1d 23 08 0: CLC Test and4b1d 23 07 1: Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Passed Summary of test results: cmd> Design (unnamed) Part: XC8106PC84 Placement Routing Timing X5937 Figure 17: Series 8000 Software Testing a Device in an HW-130 The programming algorithm includes measuring the resistance of the programmed MicroVia antifuse to guarantee the speed and functionality of the part. Since this is the one aspect that cannot be verified during factory test, it completes the 100% functional testing of the device. There are several unique capabilities in the XC8100 programming architecture. They are aimed at addressing the issues of accurate programming and 100% post-programming yield. Series 8000 programming software takes advantage of a unique XC8100 feature that each and every antifuse can be randomly addressed. The capabilities include: * Series 8000 software can run a complete functional factory test on an unprogrammed part in a programmer using the JTAG port. Figure 17 is a screen shot of the Series 8000 software running the test suite on an 5-14 unprogrammed device As noted above, during programming the actual resistance of each programmed fuse is measured; * To guarantee post-programming yield, after programming all nets are checked to see that only intended nets have been programmed, i.e. no unintended antifuses have been programmed. This is done without user test vectors; * While these capabilities ensure that XC8100 devices are 100% testable without vectors, it is possible to apply post-programming test vectors using the programmer hardware. The XC8100 software can take simulation vectors and apply them to the device and read back the results through the JTAG port. * June 1, 1996 (Version 1.0) Testing The functionality of gate arrays and older one-time programmable (OTP) PLDs has to be verified with test vectors after personalization. Even then, fault coverage is often below the standards of off-the-shelf devices. XC8100 FPGAs address this problem through the following: * * * An architecture designed for testability. The use of extensive on-chip test circuitry. A novel method of post-programming net verification. The test circuitry is used in conjunction with a set of special test instructions which are written to the dedicated JTAG port. This circuitry allows each device function -- except the actual antifuses to be programmed -- to be separately isolated and 100% tested before shipping. The programmed antifuses are later verified by the programmer. The result is the XC8100 family achieves the 100% tested level of Xilinx SRAM-based reprogrammable devices. In concept, XC8100 FPGAs are tested in four stages. The first three are done at the factory before programming, the last by the programming hardware. First, both the functionality and speed performance of all CMOS logic on the device are verified. This includes programming circuitry, the CLC logic, the IOC logic, and the long line and clock buffers. The inputs and outputs of all the internal logic are accessible for 100% testing. Second, all metal interconnect lines are tested. Special patented circuitry allows all metal lines to be accessible. Third, all antifuses are stressed and tested to be in the correct state (off) before programming. Fourth, during programming the programmer checks that all interconnect elements meet their resistance specification after programming. The current through each programmed antifuse is measured so that the resistance meets the speed specification. Moreover, all nets are tested to ensure no antifuses have been inadvertently programmed. Metastability Calculation Whenever a clocked flip-flop synchronizes an asynchronous input, there is a small probability that the flip-flop will exhibit an unpredictable clock-to-Q delay. This occurs when the input transition not only violates the setup and hold time specifications, but actually occurs within the tiny timing window where the flip-flop accepts the new input. This results in the flip-flop's output being between a logic zero and logic one - a "metastable" state. The time required to transition from the metastable state to a valid logic one or zero is the delay. The Mean Time Between Failure (MTBF) for metastability is defined statistically. Figure 19 shows the data for the XC8100 using a 1 MHz data rate and a 10 MHz clock. Device ID Check ContinuityI/O Opens and Shorts ICC Max Test I/O Leakage Test Metal Test Serpentine Test For All Interconnect Lines Fuse Stress and Test Verify All Antifuses Are Open CLC Test Verify All CLC Functions Clock Buffer Test Row Buffers, Edge Buffers I/O Functionality Test Boundary Scan, R/C Output Modes, DC Specifications: VOH, VOL, VIH, VIL Speed Test X5815 Figure 18: XC8100 Factory Test Flow Chart Used for the Factory Test of all XC8100 FPGAs which automatically use two flip-flops connected through cascade. This option has one additional clock cycle of latency. This may make sense for certain signals given the large number of CLCs/FFs on XC8100 FPGAs. Figure 19 shows that for these flip-flops, a delay of 3 ns has a MTBF over 100 years. The XC8100 offers two options in designing for metastability. The standard XC8100 flip-flops (FD, FDC, FDP) provide MTBFs that are in the range of programmable logic devices today. An additional option is the four-CLC, double-synchronized versions of the flip-flop elements, (FD_SYNC), June 1, 1996 (Version 1.0) 5-15 XC8100 FPGA Family with little concern for the architecture or implementation details. In most cases, the software automatically chooses all the capabilities described in the Architecture section. (seconds) MTBF 14 10 13 10 12 10 11 10 10 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 10 Design Implementation FD_SYNC 1000 Years The second step in the process takes an EDIF netlist output from the design entry stage and: Double-synchronized * * 1 Year 1 Month FD, FDC, FDP 1 Day * 1 Hour * fDATA = 1 MHz fCLOCK = 10 MHz 2 4 6 (ns) 8 10 * X5779 Figure 19: Metastable MTBF XACTstep Series 8000 Development System The XC8100 development system, part of the Xilinx XACTstep system, employs many new features to take advantage of the new architecture: * * * * * * * command shell and unified database structure new placement and routing software ASIC-like design flow 1-to-1 mapping between input netlist and CLCs in the device: TrueMap Logic maintains hierarchical information throughout the design flow maintains original net and instance names throughout the flow EDIF and SDF for CAE tool interfacing Similar to other Xilinx FPGAs, the XC8100 FPGA design flow is based on a four-step process: 1. Design entry and functional verification using standard CAE tools. 2. Design implementation using XC8100 tools. 3. Design verification using standard CAE tools. 4. For the XC8100, programming is the fourth step. * reads the design netlist, including hierarchy. places the netlist primitives on specific CLCs without changing any of the logic. This insures a 1-1 correspondence between design and implementation. routes all nets. The router uses rip-up-and-retry algorithms to shift congestion. calculates actual timing delays for all nets. This information is used for timing analysis and by third party timing/simulation tools. shows a view of the design at the physical level. Figure 21 is an output of the Viewer, showing the dense routing used to implement a 6502 VHDL model in an XC8106. generates fusemap and files for the programmer hardware. Design Verification The third step lets the designer use third-party CAE tools for analysis or simulation of the timings exported by Series 8000 software. Programming All programming software is included in XACTstep Series 8000. The software connects to the programmer hardware through a serial port. Platforms The XC8100 software runs under Windows 3.1, Windows 95, Windows NT, SunOS 4.1.1 or later, Solaris 2.4 or later, HPUX 9.05 or later, and AIX 3.2 or later. Platforms include PC, Sparcstation, HP PA, and RS6000. Workstation General Requirements - Design Entry The design is first described using a variety of methods: Verilog, VHDL, schematic, equations, or state machine. The designer uses standard CAE tools in this phase -- Xilinx supplies a design kit (synthesis models, schematic library) for the third-party CAE vendor's tool. Some CAE vendors supply the design kit themselves. The flexibility of the XC8100 architecture means that the user can design 5-16 - minimum 32 MB of memory hard disk with at least 40 MB available for XC8100 programs, symbol libraries and data files minimum swap space of 100 MB color console monitor (any text terminal is sufficient when using only the XC8100 command shell) two or three-button mouse (no mouse is required when using only XC8100 command shell) postscript printer such as the Apple Laser Writer II Sun Sparcstation - SunOS 4.1.1 or later, Solaris 2.4 or later access to CD ROM drive Motif Window Manager or OpenLook Window June 1, 1996 (Version 1.0) HP PA series - access to CD ROM drive HPUX 9.0 or later HP VUE 3.0 or later RS 6000 series - access to CD ROM drive AIX 3.2 or later IBM Compatible PC's - Run on 386 or 486, Pentium recommended 8 MB RAM (small designs), 16 MB recommended hard disk space varies with the selected installation: 8 MB min, 13 MB typ, and 57 MB full color monitor capable of running in VGA mode or better two or three button Windows-compatible mouse Windows driver program for graphics adapter and display access to CD ROM drive HW-130 Programmer - PC or workstation serial port June 1, 1996 (Version 1.0) 5-17 XC8100 FPGA Family Series 8000 Software Ordering Information Verilog/ VHDL DS-8000-STD-PC1-C Speed/Area Constraints Synthesis Netlist Series 8000 Simulator Timing EDIF Design System Media C = CD Series 8000 XC8100 Platform PC1 = PC Windows SN2 = Sun 4 HP7 = HP700 RS6 = RS6000 STD = Schematic bundle EXT = Synthesis + schematic Placement & Routing Timing Analysis HW-130-PC1-01 Programming Programmer Hardware Device Programmer 130 = Programmer Power Supply 01 = US/Asia 02 = EC 03 = UK 04 = Japan HW-138-PC84 Programmed FPGA X5816 Figure 20: XC8100 Synthesis Design Flow Programmer 138 = Package Adapters VQ44 = VQFP44 PC44 = PLCC44 PC84 = PLCC84 PQ100 = PQFP100 PQ160 = PQFP160 BG225 = BGA225 X5938 Figure 21: XC8100 Architecture in Software Viewer 5-18 June 1, 1996 (Version 1.0) XC8100 Synthesis Library list for the XC8100 software tools. It does not include macros used for schematic design entry. The library uses the standardized conventions of the Xilinx unified library. The XC8100 synthesis library is the set of primitives used by synthesis CAE tools to generate the gate-level EDIF net AND Gates (1 CLC) O I1 I0 I2 I1 I0 AND2 AND3 I2 I1 I0 AND2B1 O AND3B1 O I1 I0 I3 I2 I1 I0 I3 I2 I1 I0 O AND4 O I1 I0 O I2 I1 I0 AND2B2 I3 I2 I1 I0 AND3B2 I2 I1 I0 O AND4B3 I3 I2 I1 I0 O AND4B1 O I3 I2 I1 I0 O O AND4B4 O AND4B2 AND3B3 AND Gates (2 CLCs) I4 I3 I2 I1 I0 O AND5 I4 I3 I2 I1 I0 O O O AND5B4 I4 I3 I2 I1 I0 I5 I4 I3 I2 I1 I0 I5 I4 I3 I2 I1 I0 O I5 I4 I3 I2 I1 I0 O O AND6B6 O I6 I5 I4 I3 I2 I1 I0 AND7 I6 I5 I4 I3 I2 I1 I0 I6 I5 I4 I3 I2 I1 I0 O O I6 I5 I4 I3 I2 I1 I0 O AND7B4 O I6 I5 I4 I3 I2 I1 I0 O O AND7B3 O AND7B5 I6 I5 I4 I3 I2 I1 I0 AND7B2 AND6B4 AND5B5 I5 I4 I3 I2 I1 I0 I6 I5 I4 I3 I2 I1 I0 AND7B1 O AND6B3 I5 I4 I3 I2 I1 I0 O AND6B5 AND6B2 O AND5B3 I4 I3 I2 I1 I0 I5 I4 I3 I2 I1 I0 AND6B1 AND5B2 I4 I3 I2 I1 I0 O AND6 AND5B1 I4 I3 I2 I1 I0 I5 I4 I3 I2 I1 I0 O I7 I6 I5 I4 I3 I2 I1 I0 AND8 I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 O AND7B7 O I7 I6 I5 I4 I3 I2 I1 I0 O AND8B3 I7 I6 I5 I4 I3 I2 I1 I0 O AND8B6 I7 I6 I5 I4 I3 I2 I1 I0 AND8B2 O O AND8B5 I7 I6 I5 I4 I3 I2 I1 I0 AND8B1 O AND7B6 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 O AND8B7 I7 I6 I5 I4 I3 I2 I1 I0 O AND8B8 O AND8B4 June 1, 1996 (Version 1.0) 5-19 XC8100 FPGA Family FDC - D Flip-Flop with Asynchronous Clear ANDCC - AND with Cascade In and Out 2 CLCs 1 CLC COUT CIN I3 I2 I1 I0 COUT CIN I3 I2 I1 I0 O ANDCC O CIN I3 I2 I1 I0 ANDCCB1 COUT O COUT CIN I3 I2 I1 I0 ANDCCB2 COUT CIN I3 I2 I1 I0 O ANDCCB3 D D Q Q D Q D Q O C ANDCCB4 C CLR C CLR C CLR FDC FDC_1 CLR FDC_2 FDC_3 ANDCX - AND with Cascade In D D Q C CIN I3 I2 I1 I0 CIN I3 I2 I1 I0 O ANDCX CIN I3 I2 I1 I0 O ANDCXB1 O CIN I3 I2 I1 I0 ANDCXB2 CIN I3 I2 I1 I0 O ANDCXB3 Q C D Q C O CLR CLR CLR FDC_4 ANDCXB4 ANDXC - AND with Cascade Out FDC_5 DC QC DC C Q C CLR 1 CLC CLR FDC_6 COUT I3 I2 I1 I0 O ANDXC COUT I3 I2 I1 I0 O ANDXCB1 COUT I3 I2 I1 O O ANDXCB3 O PRE D FDC_XC PRE D Q C Q C PRE D Q C D Q C 1 CLC O I BUFROW FDP O O I FDP_1 PRE BUF1X D Q FDP_3 PRE Q PRE D Q D Q O C BUFGS FDP_2 PRE D I CLR FDC_CX 2 CLCs BUF - Clock/Net Buffers I Q C FDP - D Flip-Flop with Asynchronous Preset ANDXCB4 PRE 0 CLCs D COUT I3 I2 I1 I0 I0 ANDXCB2 FDC_7 QC CLR FDC_CC COUT Q C Q I3 I2 I1 I0 D C C C BUFGP FDP_4 FDP_5 FDP_6 FDP_7 BUFE - Three-State Buffers GND - Ground Signal Tag 1 CLC E E I O EB I BUFE O EB I BUFEB1A O 0 CLCs I BUFEB1B O BUFEB2 GROUND FD - D Flip-Flops GRST 2 CLCs 0 CLCs D Q C D Q C D Q C FD FD_1 D Q C FD_2 Q GRSTB1 IBUF, DBUF - Input Pad Buffers D C FD_CX 0 CLCs FD_XC I O IBUF 5-20 GSR Q C FD_CC IB RTN QC Q C GSR GRST FD_3 QC DC DC I RTN 0 CLCs I O DBUF June 1, 1996 (Version 1.0) INV - Inverting Buffers M2_1 - 2 to 1 Multiplexers 1 CLC 1 CLC I D0 D1 S0 O INV1X O D0 D1 S0 M2_1 D0 D1 S0 O M2_1B1A M2_1B1B IOBUF, DBUF, IRBUF, DRBUF - Bidirectional Three-State Pad Buffers NAND Gates (1 CLC) 0 CLCs 1 CLC IO E E EB EB I I I I O IO O IO O IO IOBUFB1A IOBUFB1B IOBUFB2 DOBUF DOBUFB1A DOBUFB1B DOBUFB2 IRBUF IRBUFB1A IRBUFB1B IRBUFB2 DRBUF DRBUFB1A DRBUFB1B DRBUFB2 I2 I1 I0 NAND2 I1 I0 O IOBUF O I1 I0 I2 I1 I0 O I3 I2 I1 I0 NAND3B1 O I2 I1 I0 NAND2B2 LD - Transparent Data Latches I3 I2 I1 I0 O Q D Q D O NAND4B2 NAND3B3 D O NAND4B1 O I2 I1 I0 1 CLC Q O NAND4 O NAND3B2 D O M2_1B2 I3 I2 I1 I0 O NAND3 NAND2B1 I1 I0 D0 D1 S0 O I3 I2 I1 I0 Q O NAND4B3 G G LD G LD_1 G LD_2 I3 I2 I1 I0 LD_3 O NAND4B4 LDC - Transparent Data Latch with Asynchronous Clear NAND Gates (2 CLCs) 2 CLCs 2 CLCs D Q G D Q G CLR Q D CLR LDC_2 D Q D Q D G G G CLR CLR CLR CLR LDC_5 LDC_6 Q LDC_7 LDE4 - Quad Latch Bank with Three-State Output 4 CLCs I4 I3 I2 I1 I0 O NAND5 LDC_3 G LDC_4 Q G CLR LDC_1 D Q G CLR LDC D I4 I3 I2 I1 I0 O NAND5B3 E E D0 Q0 D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 Q3 D3 Q3 G G LDE4 EB LDE4B1A EB O NAND7 I7 I6 I5 I4 I3 I2 I1 I0 O NAND8 O NAND5B4 I4 I3 I2 I1 I0 O NAND5B5 D0 Q0 D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 Q3 D3 Q3 G I4 I3 I2 I1 I0 I6 I5 I4 I3 I2 I1 I0 O NAND5B2 I4 I3 I2 I1 I0 O NAND6 O NAND5B1 I4 I3 I2 I1 I0 I5 I4 I3 I2 I1 I0 G LDE4B1B LDE4B2 June 1, 1996 (Version 1.0) 5-21 XC8100 FPGA Family NOR Gates (1 CLC) OBUFE, RBUFE - Output Pad Three-State Buffers 1 CLC I1 I0 O I2 O I1 NOR3 I1 I0 O I2 E O EB I O O I0 I2 OBUFE RBUFE OBUFEB1A RBUFEB1A OBUFEB1B RBUFEB1B 1 CLC I3 I0 I2 NOR3B3 I1 I0 O I1 I0 O NOR4B3 I2 O I1 I0 NOR4B4 O OR4B1 I2 O I1 I0 I3 I0 NOR5 OR4B3 I3 I6 I5 I4 I3 I2 I1 I0 NOR5B1 I2 OR4B4 O OR Gates (2 CLCs) NOR7 2 CLCs I7 I6 I5 I4 I3 I2 I1 I0 NOR5B2 O O NOR8 NOR5B3 I4 I3 I2 I1 I0 O I4 I3 I2 I1 I0 O OR5 I4 I3 I2 I1 I0 NOR5B4 O I4 I3 I2 I1 I0 O OBUF, RBUF - Output Pad Buffers (C, R modes) O OBUFB1 I O RBUF I O RBUFB1 I6 I5 I4 I3 I2 I1 I0 O OR7 I4 I3 I2 I1 I0 O I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 O OR8 OR5B3 0 CLCs O O OR5B2 NOR5B5 I5 I4 I3 I2 I1 I0 OR6 OR5B1 I4 I3 I2 I1 I0 I O I1 I0 O I4 I3 I2 I1 I0 O O I1 I0 O NOR6 O I4 I3 I2 I1 I0 I2 OR3B3 I5 I4 I3 I2 I1 I0 O OR4B2 O I1 O I1 I0 I2 2 CLCs I3 I2 OR3B2 NOR Gates (2 CLCs) O I1 I0 OR3B1 OR2B2 I3 I2 I0 O O OR4 I2 I1 I2 I1 I0 OR3 OR2B1 O O I0 I1 I0 I1 I0 I3 I2 I1 OR2 I3 I4 I3 I2 I1 I0 O OBUFEB2 RBUFEB2 NOR4B2 O I1 I4 I3 I2 I1 I0 I O I1 I0 I2 OBUF O OR Gates (1 CLC) I3 NOR3B2 I EB I NOR4B1 I2 I1 NOR2 O I1 I0 NOR3B1 O I I3 O I0 NOR2 I1 I0 E NOR4 I2 I1 O I1 I0 I0 NOR2 0 CLCs I3 I2 O OR5B4 I4 I3 I2 I1 I0 O OR5B5 5-22 June 1, 1996 (Version 1.0) SOP - Sum of Products (1 CLC) SOPCC - Sum of Products with Cascade In and Out 1 CLC 1 CLC I2 O I1 I0 I3 I2 CIN I3 I2 O I1 I0 SOP3 O I2 I3 I2 SOP3B1B I2 O SOP4B2A I3 I2 SOP3B2A O I1 I0 I2 O I1 I0 SOPCCB2B O I3 I2 I1 I0 CIN I3 I2 I1 I0 I3 I2 CIN I3 I2 O O I1 I0 SOP6 O O I1 I0 SOPCXB4 SOPCXB2C COUT I3 I2 SOPXC I3 I2 I1 I0 O I1 I0 SOPXCB1 O SOPXCB3 COUT I3 I2 O COUT I1 I0 SOPXCB2A COUT I3 I2 O O I1 I0 O I5 I4 I3 I2 I1 I0 COUT I3 I2 O I3 I2 COUT O I1 I0 SOPXCB2B SOPXCB4 VCC - VCC Signal Tag 0 CLCs SOP6B4B O VCC +5 I5 I4 I3 I2 I1 I0 SOP6B2B I5 I4 I3 I2 I1 I0 O I1 I0 I1 I0 I5 I4 I3 I2 I1 I0 SOP6B2A SOPCXB3B CIN I3 I2 1 CLC SOP6B4A O O I1 I0 SOPXC - Sum of Products with Cascade Out SOP6B3B SOP6B1 I5 I4 I3 I2 I1 I0 O CIN I3 I2 SOPCXB2B SOPCXB1B I5 I4 I3 I2 I1 I0 O CIN I3 I2 I1 I0 O SOPCXB3A I1 I0 CIN I3 I2 2 CLCs CIN I3 I2 I1 I0 CIN I3 I2 SOPCXB1A I5 I4 I3 I2 I1 I0 SOPCCB4 SOPCXB2A CIN I3 I2 SOP - Sum of Products (2 CLCs) O I1 I0 SOPCX O SOP4B4 O O I1 I0 SOPCCB2C I1 I0 I1 I0 I5 I4 I3 I2 I1 I0 COUT 1 CLC O SOP4B3 O O CIN I3 I2 SOPCX - Sum of Products with Cascade In SOP3B3 I5 I4 I3 I2 I1 I0 O SOPCCB3B COUT SOPCCB1B O I1 I0 COUT I1 I0 CIN I3 I2 COUT I1 I0 SOP4B2B SOP3B2B O CIN I3 I2 I1 I0 CIN I3 I2 O SOPCCB3A COUT SOPCCB1A O I1 I0 I1 I0 I2 SOPCCB2A O COUT I1 I0 CIN I3 I2 COUT I1 I0 SOP4B1 O I1 I0 O CIN I3 I2 I1 I0 CIN I3 I2 O I1 I0 SOP3B1A COUT SOPCC I3 I2 I1 I0 O I1 I0 SOP4 I2 CIN I3 I2 COUT O VCC XOR2, XNOR2 - Two-Input Exclusion OR/NOR SOP6B5 O SOP6B3A June 1, 1996 (Version 1.0) I5 I4 I3 I2 I1 I0 1 CLC O I1 I0 SOP6B6 O XOR2 I1 I0 O XNOR2 5-23 XC8100 FPGA Family Pin Descriptions VCC Two or more, depending on the package type. All must be connected to the +5 V/3.3 V supply voltage. is unused. All synchronous logic is reset time TMRQ after MR is raised high. It is recommended that MR on the XC8100 (625 gate) device have a 1k resistor in series to limit current from signals that violate the VIN specification of -0.5V. VPP I/O Vpp is the programming voltage. This pin can be left floating, but will draw slightly less ICCO if connected to VCC during operation. These pins are configured by the user to be either input or output. Programmable options include input voltage levels (CMOS or TTL on a per-chip basis) and output slew rate (resistive or capacitive mode on a per-pin basis). If an I/O is not used, an internal pull-up resistor is automatically enabled, so no external resistor is required. GND Four or more, depending on the package type. All must be connected to ground. GCK1 - GCK4 - I/O Four global clock inputs each connect to a dedicated internal global buffer (bufedge) with short delay and minimal skew. If not used for this purpose, these pins are user I/O. TDO Test Data Output pin for JTAG operation and testing. This is a dedicated pin and is not available for user I/O. It has no pull-up or pull-down. TDI, TCK, TMS Test Data In, Test Clock, and Test Mode Select inputs for JTAG boundary scan, programming, and testing. These are dedicated pins and are not available for user I/O. TMS and TDI have pull-ups, TCK does not. MASTER RESET This active-low pin has the same functionality as removing VCC and then reapplying power. It resets all synchronous logic. Master Reset three-states all I/O pins while held low, and can be useful for board testing. The pin has an internal pull-up resistor, so no external resistor is needed if the pin 5-24 XC8100 Pin Assignments The XC8100 pinout is based on the XC4000 pinouts. This means that, for any package, power and control pins are on the same pins as in the XC4000. However, not all the control pins have the same function. Typically the XC4000 M0/ M1/M2 pins are fixed. If JTAG is not used on the XC8100, this is compatible. DONE can be an input or an output. If it's an input, the XC8100 trace would have to be cut. The VPP pin is compatible with either CCLK as an input or outputs, although VPP has a larger input capacitance. Following is the mapping: Type VCC GND Control XC8100 Same as XC4000 Same as XC4000 TMS TCK TDI TDO VPP MR XC4000 - - M0 M1 M2 TDO CCLK DONE June 1, 1996 (Version 1.0) Number of Available I/O Pins Device Max I/O 32 72 128 168 192 XC8100 XC8101 XC8103 XC8106 XC8109 Note: PC44 32 (32) 32 - - Packages PC84 - 61 61 61 61 VQ44 32 (32) 32 - - PQ100 - 72 64 76 - PQ160 - - (128) (129) 129 BG225 - - - (168) 192 Parentheses indicates future products XC8100 Pinouts Pin Description PC44 VQ44 Bound Scan Pin Description Bound Scan Pin Description VCC 2 40 - TDI 16 I/O 3 41 69 GCK2-I/O 17 10 - MR 31 25 - 11 0 I/O 32 26 38 I/O 4 42 72 I/O 18 I/O 5 43 75 I/O 19 12 4 GCK3-I/O 33 27 41 13 7 GND 34 28 I/O 6 44 78 I/O - 20 14 10 I/O 35 29 44 I/O 7 1 81 I/O 8 2 84 I/O 21 15 13 I/O 36 30 47 I/O 22 16 16 VPP 37 31 GCK1-I/O 9 3 - 87 VCC 23 17 - TDO 38 32 - PC44 VQ44 PC44 VQ44 Bound Scan I/O 10 4 91 GND 24 18 - I/O 39 33 51 GND 11 5 - I/O 25 19 19 GCK4-I/O 40 34 54 I/O 12 6 94 I/O 26 20 22 I/O 41 35 57 I/O 13 7 97 I/O 27 21 25 I/O 42 36 60 TCK 14 8 - I/O 28 22 28 I/O 43 37 63 TMS 15 9 - I/O 29 23 31 I/O 44 38 66 I/O 30 24 34 GND 1 39 - June 1, 1996 (Version 1.0) 5-25 XC8100 FPGA FamilyXC8100 FPGA Family XC8101 Pinouts Pin Description PC84 PQ100 Bound Scan Pin Description VCC 2 I/O 3 92 - GND 31 26 93 159 TMS 32 27 I/O 4 94 162 VCC 33 28 - I/O - 95 165 TDI 34 29 I/O - 96 168 GCK2-I/O 35 30 I/O 5 97 171 I/O 36 31 I/O 6 98 174 I/O - - I/O 7 99 177 I/O - - 10 I/O I/O 8 100 180 I/O - 32 13 VCC I/O - - 193 I/O 37 33 16 GND 64 67 - I/O - - 196 I/O 38 34 19 I/O 65 68 98 101 PC84 PQ100 Bound Scan Pin Description PC84 PQ100 Bound Scan - I/O 58 58 80 - I/O - 59 83 I/O 59 60 86 - I/O 60 61 89 0 NC - 62 - 4 NC - 63 - 7 I/O 61 64 92 62 65 95 63 66 - I/O 9 1 189 I/O 39 35 22 I/O 66 69 I/O 10 2 192 I/O - 36 25 NC - 70 - VCC 11 3 - I/O - 37 28 I/O 67 71 104 GND 12 4 - I/O 40 38 31 I/O 68 72 107 GCK1-I/O 13 5 195 I/O 41 39 34 I/O 69 73 110 I/O 14 6 199 VCC 42 40 - I/O 70 74 113 I/O 15 7 202 GND 43 41 - I/O 71 75 116 I/O 16 8 205 I/O 44 42 37 I/O 72 76 119 I/O 17 9 208 I/O 45 43 40 VPP 73 77 - I/O 18 10 211 I/O - 44 43 VCC 74 78 - NC - 11 - I/O - 45 46 TDO 75 79 - I/O 19 12 214 I/O 46 46 49 GND 76 80 - 5-26 I/O 20 13 217 I/O 47 47 52 I/O 77 81 123 GND 21 14 - I/O 48 48 55 GCK4-I/O 78 82 126 VCC 22 15 - I/O 49 49 58 I/O - - 129 I/O 23 16 220 I/O - - 61 I/O - - 132 I/O 24 17 223 I/O - - 64 I/O 79 83 135 NC - 18 - I/O 50 50 67 I/O 80 84 138 I/O 25 19 226 I/O 51 51 70 I/O 81 85 141 I/O 26 20 229 GND 52 52 - I/O 82 86 144 I/O 27 21 232 MR 53 53 - I/O - 87 147 I/O - 22 235 VCC 54 54 - I/O - 88 150 I/O 28 23 238 NC 55 55 - I/O 83 89 153 I/O 29 24 241 I/O 56 56 74 I/O 84 90 156 TCK 30 25 - GCK3-I/O 57 57 77 GND 1 91 - June 1, 1996 (Version 1.0) XC8103 Pinouts Bound Pin Bound Pin Description Pin PC84 PQ100 Scan Description PC84 PQ100 Scan Description PC84 PQ100 Bound VCC 2 92 - I/O 28 23 190 - - - I/O 3 93 123 I/O 29 24 193 GND - - I/O 4 94 126 TCK 30 25 - - - - NC - 95 - GND 31 26 - - - - NC - 96 - TMS 32 27 - I/O 59 60 62 I/O 5 97 129 VCC 33 28 - I/O 60 61 65 I/O 6 98 132 TDI 34 29 - NC - 62 - - - - - GCK2-I/O 35 30 0 NC - 63 - Scan - - - - I/O 36 31 4 I/O 61 64 68 GND - - - I/O - - - I/O 62 65 71 - - - - I/O - - - VCC 63 66 - - - - - I/O - 32 7 GND 64 67 - I/O 7 99 135 I/O 37 33 10 I/O 65 68 74 I/O 8 100 138 - - - - I/O 66 69 77 I/O - - - - - - - NC - 70 - I/O - - - GND - - - I/O - - - I/O 9 1 141 - - - - I/O 67 71 80 I/O 10 2 144 - - - - I/O 68 72 83 - VCC 11 3 - I/O 38 34 13 - - - GND 12 4 - I/O 39 35 16 - - - - GCK1-I/O 13 5 147 NC - 36 - GND - - - I/O 14 6 151 NC - 37 - - - - - I/O - - - I/O 40 38 19 - - - - I/O - - - I/O 41 39 22 I/O 69 73 86 I/O 15 7 154 VCC 42 40 - I/O 70 74 89 I/O 16 8 157 GND 43 41 - I/O - - - - - - - I/O 44 42 25 I/O - - - - - - - I/O 45 43 28 I/O 71 75 92 GND - - - NC - 44 - I/O 72 76 95 - - - - NC - 45 - VPP 73 77 - - - - - I/O 46 46 31 VCC 74 78 - I/O 17 9 160 I/O 47 47 34 TDO 75 79 - I/O 18 10 163 - - - - GND 76 80 - NC - 11 - - - - - I/O 77 81 99 I/O - - - GND - - - GCK4-I/O 78 82 102 I/O 19 12 166 - - - - I/O - - - I/O 20 13 169 - - - - I/O - - - GND 21 14 - I/O 48 48 37 I/O 79 83 105 VCC 22 15 - I/O 49 49 40 I/O 80 84 108 I/O 23 16 172 I/O - - - - - - - I/O 24 17 175 I/O - - - - - - - NC - 18 - I/O 50 50 43 GND - - - I/O - - - I/O 51 51 46 - - - - I/O 25 19 178 GND 52 52 - - - - - I/O 26 20 181 MR 53 53 - I/O 81 85 111 - - - - VCC 54 54 - I/O 82 86 114 - - - - NC 55 55 - - - - - GND - - - I/O 56 56 50 NC - 87 - - - - - GCK3-I/O 57 57 53 NC - 88 - - - - - I/O - - - I/O 83 89 117 I/O 27 21 184 I/O - - - I/O 84 90 120 I/O - 22 187 I/O 58 58 56 GND 1 91 - I/O - - - I/O - 59 59 I/O - - - - - - - June 1, 1996 (Version 1.0) 5-27 XC8100 FPGA FamilyXC8100 FPGA Family XC8106 Pinouts Pin Bound Pin Bound Pin Bound Description PC84 PQ100 Scan PQ160 Description PC84 PQ100 Scan PQ160 Description PC84 PQ100 Scan VCC 2 92 - 142 I/O 28 23 250 36 I/O - - - PQ160 90 I/O 3 93 165 143 I/O 29 24 253 37 GND - - - 91 I/O 4 94 168 144 TCK 30 25 - 38 I/O - - - 92 I/O - 95 171 145 GND 31 26 - 39 I/O - - - 93 I/O - 96 174 146 TMS 32 27 - 40 I/O 59 60 86 94 I/O 5 97 177 147 VCC 33 28 - 41 I/O 60 61 89 95 I/O 6 98 180 148 TDI 34 29 - 42 I/O - - - 96 I/O - - - 149 GCK2-I/O 35 30 0 43 NC - 62 - - I/O - - - 150 I/O 36 31 4 44 I/O - 63 92 97 GND - - - 151 I/O - - 7 45 I/O 61 64 95 98 I/O - - - 152 I/O - - 10 46 I/O 62 65 98 99 I/O - - - 153 I/O - 32 13 47 VCC 63 66 - 100 I/O 7 99 183 154 I/O 37 33 16 48 GND 64 67 - 101 I/O 8 100 186 155 I/O - - - 49 I/O 65 68 101 102 I/O - - 189 156 I/O - - - 50 I/O 66 69 104 103 I/O - - 192 157 GND - - - 51 I/O - 70 107 104 I/O 9 1 195 158 I/O - - - 52 I/O - - - 105 I/O 10 2 198 159 I/O - - - 53 I/O 67 71 110 106 107 VCC 11 3 - 160 I/O 38 34 19 54 I/O 68 72 113 GND 12 4 - 1 I/O 39 35 22 55 I/O - - - 108 GCK1-I/O 13 5 201 2 I/O - 36 25 56 I/O - - - 109 I/O 14 6 205 3 I/O - 37 28 57 GND - - - 110 I/O - - - 4 I/O 40 38 31 58 I/O - - - 111 I/O - - - 5 I/O 41 39 34 59 I/O - - - 112 I/O 15 7 208 6 VCC 42 40 - 60 I/O 69 73 116 113 I/O 16 8 211 7 GND 43 41 - 61 I/O 70 74 119 114 I/O - - - 8 I/O 44 42 37 62 I/O - - - 115 I/O - - - 9 I/O 45 43 40 63 I/O - - - 116 GND - - - 10 I/O - 44 43 64 I/O 71 75 122 117 I/O - - - 11 I/O - 45 46 65 I/O 72 76 125 118 I/O - - - 12 I/O 46 46 49 66 VPP 73 77 - 119 I/O 17 9 214 13 I/O 47 47 52 67 VCC 74 78 - 120 I/O 18 10 217 14 I/O - - - 68 TDO 75 79 - 121 I/O - - - 15 I/O - - - 69 GND 76 80 - 122 I/O - 11 220 16 GND - - - 70 I/O 77 81 129 123 I/O 19 12 223 17 I/O - - - 71 GCK4-I/O 78 82 132 124 I/O 20 13 226 18 I/O - - - 72 I/O - - 135 125 GND 21 14 - 19 I/O 48 48 55 73 I/O - - 138 126 VCC 22 15 - 20 I/O 49 49 58 74 I/O 79 83 141 127 I/O 23 16 229 21 I/O - - 61 75 I/O 80 84 144 128 I/O 24 17 232 22 I/O - - 64 76 I/O - - - 129 I/O - 18 235 23 I/O 50 50 67 77 I/O - - - 130 I/O - - - 24 I/O 51 51 70 78 GND - - - 131 I/O 25 19 238 25 GND 52 52 - 79 I/O - - - 132 I/O 26 20 241 26 MR 53 53 - 80 I/O - - - 133 I/O - - - 27 VCC 54 54 - 81 I/O 81 85 147 134 135 I/O - - - 28 NC 55 55 - 82 I/O 82 86 150 GND - - - 29 I/O 56 56 74 83 I/O - - - 136 I/O - - - 30 GCK3-I/O 57 57 77 84 I/O - 87 153 137 5-28 I/O - - - 31 I/O - - - 85 I/O - 88 156 138 I/O 27 21 244 32 I/O - - - 86 I/O 83 89 159 139 I/O - 22 247 33 I/O 58 58 80 87 I/O 84 90 162 140 I/O - - - 34 I/O - 59 83 88 GND 1 91 - 141 I/O - - - 35 I/O - - - 89 June 1, 1996 (Version 1.0) XC8109 Pinouts Pin PC PQ PG BG Bound Description 84 160 223 225 Scan Pin PC PQ PG BG Bound Description 84 160 223 225 Scan Pin PC PQ PG BG Bound Description 84 160 223 225 Scan Pin PC PQ PG BG Bound Description 84 160 223 225 Scan VCC 2 142 J4 D8 - I/O 24 22 B10 H5 559 I/O 44 62 K16 L8 85 I/O 65 102 T9 H12 242 I/O 3 143 J3 E8 399 I/O - 23 A9 J2 562 I/O 45 63 K17 P9 88 I/O 66 103 U9 H11 245 I/O 4 144 J2 B7 402 I/O - 24 A10 J1 565 I/O - 64 K18 R9 91 I/O - 104 V9 G14 248 I/O - 145 J1 A7 405 I/O - - A11 J3 568 I/O - 65 L18 N9 94 I/O - 105 V8 G15 251 I/O - 146 H1 C7 408 I/O - - C11 J4 571 I/O - - L17 M9 97 I/O - - U8 G13 254 I/O - - H2 D7 411 I/O - - D11 J5 574 I/O - - L16 L9 100 I/O - - T8 G12 257 I/O - - H3 E7 414 I/O - - D12 K1 577 I/O - - L15 R10 103 I/O 67 106 V7 G11 260 I/O 5 147 G1 A6 417 I/O 25 25 B11 K2 580 I/O - - M15 P10 106 I/O 68 107 U7 F15 263 I/O 6 148 G2 B6 420 I/O 26 26 A12 K3 583 I/O - - - - 109 I/O - 108 V6 F14 266 I/O - - - - 423 I/O - 27 B12 J6 586 I/O - - - - 112 I/O - 109 U6 F13 269 I/O - - - - 426 I/O - 28 A13 L1 589 I/O - - - - 115 I/O - - R8 G10 272 I/O - - - - 429 GND - 29 C12 ** - I/O 46 66 M18 N10 118 I/O - - R7 E15 275 I/O - - H4 C6 432 I/O - - D13 L2 592 I/O 47 67 M17 121 GND - 110 T7 ** - I/O - - G4 F7 435 I/O - - D14 K4 595 I/O - 68 N18 R11 124 I/O - - R6 E14 278 I/O - 149 F1 A5 438 I/O - - B13 L3 598 I/O - 69 P18 P11 127 I/O - - R5 F12 281 I/O - 150 E1 B5 441 I/O - - A14 M1 601 GND - 70 M16 ** - I/O - - V5 E13 284 GND - 151 G3 ** - I/O - 30 A15 K5 604 I/O - - - - I/O - - - - 444 I/O - 31 C13 M2 607 I/O - - I/O - - F2 D6 447 I/O 27 32 B14 L4 610 I/O - I/O - - D1 C5 450 I/O - 33 A16 N1 613 I/O - I/O - 152 C1 A4 453 I/O - 34 B15 M3 616 I/O I/O - 153 E2 E6 456 I/O - 35 C14 N2 619 I/O I/O 7 154 F3 B4 459 I/O 28 36 A17 K6 622 I/O - 72 I/O 8 155 D2 D5 462 I/O 29 37 B16 P1 625 I/O 48 73 I/O - - F4 A3 465 TCK 30 38 C15 N3 - I/O 49 74 T17 N12 154 I/O 72 118 I/O - - E4 C4 468 GND 31 39 D15 ** - I/O - 75 R17 P13 157 VPP 73 119 I/O - 156 B1 B3 471 TMS 32 40 A18 P2 - I/O - 76 P16 K10 160 VCC 74 120 I/O - 157 E3 F6 474 VCC 33 41 D16 R1 - I/O 50 77 U18 R14 163 TDO I/O 9 158 C2 A2 477 TDI 34 42 C16 M4 - I/O 51 78 T16 N13 166 K9 130 I/O - - V4 D15 287 N15 M10 133 I/O - 111 U5 F11 290 - P15 N11 136 I/O - 112 T6 D14 293 - N17 R12 139 I/O 69 113 V3 E12 296 - - R18 L10 142 I/O 70 114 - 71 T18 P12 145 I/O P17 M11 148 I/O N16 R13 151 I/O C15 299 D13 302 116 T5 C14 305 71 117 U3 F10 308 T4 B15 311 V1 C13 - R4 B14 - 75 121 U2 A15 - GND 76 122 R3 D12 315 115 - I/O 10 159 B2 C3 480 GCK2-I/O 35 43 B17 R2 0 GND 52 79 R16 - I/O 77 123 T3 A14 VCC 11 160 D3 B2 - I/O 36 44 E16 P3 4 MR 53 80 U17 P14 - GCK4-I/O 78 124 U1 B13 318 GND 12 D4 A1 - I/O - 45 C17 L5 7 VCC 54 81 R15 R15 - I/O 1 ** V2 U4 - - 125 P3 E11 321 - GCK1-I/O 13 2 C3 D4 483 I/O - 46 D17 N4 10 NC 53 82 V18 M12 - I/O 126 R2 C12 324 I/O 14 3 C4 B1 487 I/O - 47 B18 R3 13 I/O 56 83 T15 P15 170 I/O 79 127 T2 A13 327 I/O - 4 B3 C2 490 I/O 37 48 E17 P4 16 GCK3-I/O 57 84 U16 N14 173 I/O 80 128 N3 B12 330 I/O - 5 C5 E5 493 I/O - 49 F16 K7 19 I/O - 85 T14 L11 176 I/O - - P4 F9 333 I/O 15 6 A2 D3 496 I/O - 50 C18 M5 22 I/O - 86 U15 M13 179 I/O - - N4 D11 336 I/O 16 7 B4 C1 499 I/O - - D18 R4 25 I/O - - R14 N15 182 I/O - 129 P2 A12 339 I/O - 8 C6 D2 502 I/O - - F17 N5 28 I/O - - R13 M14 185 I/O - 130 T1 C11 342 I/O - 9 A3 G6 505 I/O - - E15 P5 31 I/O 58 87 V17 J10 188 I/O - - R1 B11 345 I/O - - B5 E4 508 I/O - - F15 L6 34 I/O - 88 V16 L12 191 I/O - - N2 E10 I/O - - B6 D1 511 I/O - - - - 37 I/O - 89 T13 M15 194 I/O I/O - - D5 E3 514 GND - 51 G16 ** - I/O - 90 U14 L13 197 GND - 131 M3 ** - I/O - - D6 E2 517 I/O - 52 E18 R5 40 I/O - - V15 L14 200 I/O - 132 P1 A11 354 GND - 10 C7 ** - I/O - 53 F18 M6 43 I/O - - V14 K11 203 I/O - 133 N1 D10 357 I/O - 11 A4 F5 520 I/O 38 54 G17 N6 46 GND - 91 - I/O - - M4 C10 360 I/O - 12 A5 E1 523 I/O 39 55 G18 P6 49 I/O - - R12 L15 206 I/O - - L4 B10 363 I/O 17 13 B7 F4 526 I/O - - - - 52 I/O - - R11 K12 209 I/O - - - - 366 I/O 18 14 A6 F3 529 I/O - - - - 55 I/O - 92 U13 K13 212 I/O - - - - 369 I/O - - D7 F2 532 I/O - - - - 58 I/O - 93 V13 K14 215 I/O - - - - 372 I/O - - D8 F1 535 I/O - - H16 R6 61 I/O 59 94 U12 K15 218 I/O 81 134 M2 A10 375 I/O - - C8 G4 538 I/O - - H17 M7 64 I/O 60 95 V12 J12 221 I/O 82 135 M1 D9 378 I/O - - A7 G3 541 I/O - - G15 N7 67 I/O - - T11 J13 224 I/O - - L3 C9 381 I/O - 15 B8 G2 544 I/O - - H15 P7 70 I/O - - U11 J14 227 I/O - 136 L2 B9 384 I/O - 16 A8 G1 547 I/O - 56 H18 R7 73 I/O - 96 V11 J15 230 I/O - 137 L1 A9 387 I/O 19 17 B9 G5 550 I/O - 57 J18 L7 76 I/O - 97 V10 J11 233 I/O - 138 K1 E9 390 T12 ** 348 351 I/O 20 18 C9 H3 553 I/O 40 58 J17 N8 79 I/O 61 98 U10 H13 236 I/O 83 139 K2 C8 393 GND 21 19 D9 H2 - I/O 41 59 J16 P8 82 I/O 62 99 T10 H14 239 I/O 84 140 K3 B8 396 VCC 22 20 D10 H1 - VCC 42 60 J15 R8 - VCC 63 100 R10 H15 - GND 1 K4 A8 - I/O 23 21 C10 H4 556 GND 43 61 K15 M8 - GND 64 101 - Note: R9 ** 141 ** These BGA225 balls are connected to ground: F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8 June 1, 1996 (Version 1.0) 5-29 XC8100 FPGA FamilyXC8100 FPGA Family (40) (1) GND (2) VCC (6) Package Pinout Diagrams (7) (39) (38) TDO (37) VPP GND (11) Top View (34) GND TCK (14) (31) MR TMS (15) TDI (16) (17) (28) GND (24) VCC (23) (18) (29) X5831 (23) (25) MR (33) (32) TDO (31) VPP (28) GND Figure 22: PC44 PLCC with 44 Leads, 50 mil Lead Pitch (22) (34) Top View GND (39) VCC (40) (18) GND (17) VCC (12) TCK (8) TMS (9) TDI (10) (11) GND (5) (1) (44) X5939 Figure 23: VQ44 VQFP with 44 Leads, 0.8 mm Lead Pitch 5-30 June 1, 1996 (Version 1.0) (76) GND (75) TD0 (78) GCK4-I/O (2) VCC (1) GND (11) VCC GND (12) GCK1-I/O (13) (74) VCC (73) VPP GND (21) VCC (22) (64) GND (63) VCC Top View (57) GCK3-I/O TCK (30) GND (31) TMS (32) GND (52) MR (53) VCC (33) TDI (34) GCK2-I/O (35) VCC (42) GND (43) (55) NC (54) VCC X5628 (57) GCK3-I/O (55) NC (54) VCC (53) MR (52) GND (51) (63) * (62) * (67) GND (66) VCC (70) * (80) GND (79) TD0 (78) VCC (77) VPP Figure 24: PC84 PLCC with 84 Leads, 50 mil Lead Pitch (50) (81) GCK4-I/O (82) (41) GND (40) VCC Top View GND (91) VCC (92) (31) TCK (25) GND (26) TMS (27) VCC (28) TDI (29) GCK2-I/O (30) * (18) * (11) GND (14) VCC (15) (1) VCC (3) GND (4) GCK1-I/O (5) (100) * Depends on device X5780 Figure 25: PQ100 PQFP with 100 Leads, .65 mm Lead Pitch June 1, 1996 (Version 1.0) 5-31 (84) GCK3-I/O (82) NC (81) VCC (93) * (92) * (91) GND (90) * (89) * (120) VCC (119) VPP (112) * (111) * (110) GND (109) * (108) * (101) GND (100) VCC XC8100 FPGA FamilyXC8100 FPGA Family TD0 (121) GND (122) GCK4-I/O (124) * (129) * (130) GND (131) * (132) * (133) * (136) (80) MR (79) GND (72) * (71) * (70) GND (69) * (68) * GND (141) VCC (142) (61) GND (60) VCC Top View (53) * (52) * (51) GND (50) * (49) * * (149) * (150) GND (151) * (152) * (153) (43) GCK2-I/O (42) TDI (41) VCC TCK (38) GND (39) TMS (40) * (27) * (28) GND (29) * (30) * (31) GND (19) VCC (20) * (8) * (9) GND (10) * (11) * (12) GND (1) GCK1-I/O (2) VCC (160) * Depends on device X5781 Figure 26: PQ160 PQFP with 160 Leads, .65mm Lead Pitch Top View (through package) R MR P N NC * * * F GND GND GND * GND * * * * D VPP * * * VCC * VCC * 15 14 13 12 11 10 * Depends on device * * VCC GND * C TD0 GND VCC GND GND GND GND GND * B * * GND GND GND VCC * GND * G A TCK TDI GND * * TMS * * * J E VCC * * * K H VCC * * M L * VCC GND GND 9 8 7 6 5 4 3 2 1 X5807 Figure 27: BG225 Plastic Ball Grid Array with 225 PbSn Balls, 15 x 15 Array, 1.50 mm Lead Pitch 5-32 June 1, 1996 (Version 1.0) Device Specifications Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Note: Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to three-state output Storage temperature (ambient) Maximum soldering temperature (10 sec @ 1/16 inch) Junction temperature - Ceramic Junction temperature - Plastic -0.5 to + 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to + 150 + 260 + 150 + 125 Units V V V C C C C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 5 V Operating Conditions Symbol VCC VIHT VIHC VILT VILC TIN Description Supply voltage relative to GND Commercial High-level input voltage for TTL threshold High-level input voltage for CMOS threshold Low-level input voltage for TTL threshold Low-level input voltage for CMOS threshold Input signal transition time 0C to 70C Min 4.75 2.0 70% 0 0 Max 5.25 VCC 100% 0.8 20% 250 Units V V VCC V VCC ns Min 3.86 Max 0.50 Units V V 0.40 V 0.8 1.5 3.0 6.0 10.0 + 10 0.20 15 mA mA mA mA mA A mA pF DC Characteristics Over 5 V Operating Conditions Symbol VOH VOLR VOLC ICCO II IRIN CIN Description High-level output voltage, IOH = -4 mA, VCC min Low-level output voltage, IOL = 24 mA, VCC min resistive mode (Note 1) Low-level output voltage, IOL = 4 mA, VCC min capacitive mode (Note 1) Quiescent supply current, CMOS mode, (Note 2) - actual ICCO depends on the design - TTL mode adds 8-30 mA - see Power Consumption section Input leakage current Pad pull-up current, VIN = 0 V (sample tested) Input capacitance (sample tested) XC8100 XC8101 XC8103 XC8106 XC8109 - 10 0.02 Notes: 1. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies by package. 2. With no output current loads, no active inputs, all package pins at VCC or GND. Typical quiescent supply current at room temperature is less than 50% of the maximum. June 1, 1996 (Version 1.0) 5-33 XC8100 FPGA FamilyXC8100 FPGA Family DC Characteristics Over 3.3 V Operating Conditions Symbol VCC VIH VIL VOH VOLR VOLC ICCO Description Supply voltage relative to GND Commercial 0C to 70C High-level input voltage (Note 1) Low-level input voltage (Note 1) High-level output voltage, IOH = -4.0 mA, VCC min IOH = -100 A, VCC min Low-level output voltage, IOL = 12.0 mA, VCC min resistance mode Low-level output voltage, IOL = 4.0 mA, VCC min capacitive mode Quiescent supply current, CMOS mode, (Note 2) XC8100 - actual ICCO depends on the design XC8101 - see Power Consumption section XC8103 XC8106 XC8109 Min 3.0 2.0 - 0.3 2.4 VCC -0.2 Max 3.6 VCC + 0.3 0.8 0.4 Units V V V V V V 0.4 V 250 500 800 1500 3000 A A A A A Notes: 1. Set CMOS/TTL input threshold to CMOS mode for use at 3.3 V. 2. With no output current loads, no active inputs, all package pins at VCC or GND. Typical quiescent supply current at room temperature is less than 25% of the maximum. 5-34 June 1, 1996 (Version 1.0) CLC Combinatorial Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested except for the programmed resistance of the fuses that will be used in the end application. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing information Speed Grade -1 -2 Supply Voltage 5V 3.3 V 5V 3.3 V Sym Min Max Min Max Min Max Min Max Units Description AND4 I3 I2 I1 I0 O Input I0 to output O Input I1 to output O Input I2 to output O Input I3 to output O i0r i1r i2r i3r 3.0 2.9 3.2 2.9 5.3 5.2 5.8 5.2 ns ns ns ns Input I0 to output O Input I4 to output O Input I7 to output O i0r i4r i7r 3.0 5.4 5.3 5.4 9.9 9.7 ns ns ns Input I0 to output O Input I3 to output O Input I0 to output COUT Input I3 to output COUT Input CIN to output COUT i0r i3r i0rc i3rc circ 3.0 3.3 2.3 2.6 2.4 5.4 6.1 4.2 4.9 4.6 ns ns ns ns ns Input I to output O flow-through Three-state E to output O begin hi-Z Three-state E to output O active ir ehz ezh 2.8 4.6 4.6 4.8 7.3 7.3 ns ns ns Input D0 to output O Input D1 to output O Select input S to output O d0r d1r s0r 3.0 2.8 3.1 5.1 5.0 5.6 ns ns ns Input I0 to output O Input I1 to output O Input I2 to output O Input I3 to output O i0r i1r i2r i3r 3.1 3.0 3.1 2.8 5.5 5.3 5.5 4.9 ns ns ns ns Input I0 to output O Input I2 to output O Input I5 to output O i0r i2r i5r 3.1 4.8 4.6 5.5 8.4 7.9 ns ns ns AND8 I7 I6 I5 I4 I3 I2 I1 I0 O Note: Inputs I0 to I3 are faster than the cascaded inputs I4 to I7 ANDCC CIN I3 I2 I1 I0 COUT O BUFE E I O M2_1 D0 D1 S0 O SOP4 I3 I2 O I1 I0 SOP6 I5 I4 I3 I2 I1 I0 O Note: Inputs I0 and I1 are faster and are approximately the same delay June 1, 1996 (Version 1.0) 5-35 XC8100 FPGA FamilyXC8100 FPGA Family CLC Combinatorial Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested except for the programmed resistance of the fuses that will be used in the end application. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing information. Speed Grade -1 Supply Voltage 5V 3.3 V Sym Min Max Min Max Description SOPCC CIN I3 I2 COUT O I1 I0 -2 5V Min Max 3.3 V Min Max Units Input I0 to output O Input I3 to output O Input I0 to output COUT Input I3 to output COUT Input CIN to output COUT i0r i3r i0r i3r circ 3.1 3.2 2.3 2.4 2.2 5.5 5.8 4.3 4.7 4.2 ns ns ns ns ns Input I0 to output O Input I1 to output O i0r i1r 3.3 3.0 5.6 5.1 ns ns XOR2 I1 I0 O Notes: 1. Symbol names are those used in timing parameters in the XC8100 software, e.g., and4_i0r. 2. CLC combinatorial worst-case timings use rising edges. Falling edge signals are typically 0.6 ns faster. 3. Using inverted inputs ("bubbled") has minimal change on rising edge combinatorial timings. Inverting falling edge signals typically adds 0.4 - 0.5 ns. 5-36 June 1, 1996 (Version 1.0) CLC Sequential Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested except for the programmed resistance of the fuses that will be used in the end application. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing information. Speed Grade -1 -2 Supply Voltage 5V 3.3 V 5V 3.3 V Sym Min Max Min Max Min Max Min Max Units Description FD D Q C Clock C to output Q delay Data set-up time before clock C Data hold time after clock C ckqr su hold 3.5 2.3 0.0 6.1 ns ns ns 6.1 ns ns ns ns ns 3.3 0.0 FDC D Q C CLR Clock C to output Q delay Data set-up time before clock C Data hold time after clock C Asynchronous CLR to output Q CLR width ckqr su 2.3 hold 0.0 clqf clpmin 1.7 3.5 dqr gqr su hold gpmin 2.8 3.0 3.3 0.0 3.0 5.9 3.3 Note: timings are similar for FDP (D FF with Reset) LD D Q G Data D to output Q delay Latch G to output Q delay Data set-up time to G Data hold time from G G width 2.2 0.0 2.5 5.1 5.4 ns ns ns ns ns 5.8 6.4 ns ns ns ns ns ns 4.5 0.0 5.3 Note: when G is high, data flows through. G latches on the falling edge LDC D Q G CLR Data D to output Q delay Latch G to output Q delay Data set-up time to G Data hold time from G Asynchronous CLR to output Q CLR width dqr gqr su 2.2 hold 0.0 clqr clpmin 2.2 High time Low time Toggle Frequency TCH TCL FTOG 3.2 3.4 4.5 0.0 5.1 9.1 3.9 Clock 2.6 2.6 5.2 5.2 ns ns MHz 144 Note: Sequential worst-case timings delays use rising edges. Falling edge signals are typically 0.5 ns faster for single-CLC functions (e.g. LD) and 1.0 ns faster for double-CLC functions (e.g. FD).Toggle frequency based on worst-case data from XC8100 software. T CH T CL CLK T SU T HOLD D, G T CKQR Q T CLQR CLR, PRE T CLPMIN June 1, 1996 (Version 1.0) X5631 5-37 XC8100 FPGA FamilyXC8100 FPGA Family Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested except for the programmed resistance of the fuses that will be used in the end application. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing information. Speed Grade -1 Supply Voltage 5V 3.3 V Sym Min Max Min Max Description BUF1X I Input I to output O delay O -2 5V Min Max 3.3 V Min Max Units TIO ir 2.8 4.8 ns TIO ir 4.6 7.6 ns TIO ir 2.0 3.3 ns TIO ir 3.0 5.1 ns BUFGP I O Input I to output O delay Note: Timing is for buffer only, and does not include device-dependent wire delays BUFROW I O Input I to output O delay Notes: 1. Same delay for BUFGS 2. Timing is for buffer only, and does not include device-dependent wire delays INV1X I Note: 5-38 O Input I to output O delay 1. Symbols are Xilinx standard names and timing parameters used in XC8100 software, e.g., ibuf_ir. June 1, 1996 (Version 1.0) I/O Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested except for the programmed resistance of the fuses that will be used in the end application. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing information. Speed Grade -1 Supply Voltage 5V 3.3 V Sym Min Max Min Max Description IBUF I O Input propagation delay -2 5V Min Max 3.3 V Min Max Units TPID ir 1.8 3.0 ns TPID ir 14.5 26.3 ns Output delay to pin (capacitive mode) TOP ir if 3.4 5.4 6.7 7.2 ns ns Output delay to pin (capacitive mode) ir if ehz ezl 3.4 5.4 3.9 5.7 6.8 7.3 7.0 9.2 ns ns TOPR ir if 3.5 4.5 6.1 6.0 ns ns Note: same timing for IOBUF B-to-O DBUF I O Input propagation delay (with delay) Note: same timing for DOBUF B-to-O OBUF I O OBUFE E I O Three-state input E to pad O begin hi-Z Three-state input E to pad O active ns ns Note: same timing for IOBUF E-to-O RBUF I O Output delay to pin (resistive mode) Note: same timing for RBUFE Notes: 1. Symbols are Xilinx standard names (e.g. TPID) and timing parameters used in XC8100 software, e.g., ibuf_ir. 2. Timing is measured at pin threshold, with 50 pF load. 3. RBUF loading: 5V R1 177 3.3 V 217 370 294 R2 VCC R1 Output 50 pF R2 X5943 4. Output delays (except input E to pad O begin hi Z) change with capacitive load according to the following table. Delays above are calculated for 50 pF. As an example, obuf_ir at 20 pF is: 3.4 -(30 x 0.21) = 2.77 ns. XC8100 software can make these calculations automatically. 5V Resistive Mode Capacitive Mode Rise 0.017 0.021 3.3 V Fall 0.030 0.046 Rise 0.033 0.054 Fall 0.026 0.049 Units ns/pF ns/pF 5. Unused (bonded or unbonded) pads are automatically pulled-up internally with a ~50K resistor. June 1, 1996 (Version 1.0) 5-39 XC8100 FPGA FamilyXC8100 FPGA Family Input and Output Parameters (Pin-to-Pin) The following values reflect worst-case values over the recommended operating conditions. The exact timing depends on placement and routing so results may vary from design to design. See the XC8100 software for complete timing information. Speed Grade -1 -2 Supply Voltage 5V 3.3 V 5V 3.3 V Sym Min Max Min Max Min Max Min Max Units Description Global clock pin to output pin (resistive), 24 FF per row, all rows TICKO XC8100 XC8101 RBUF (Max) XC8103 BUFGP FD XC8106 XC8109 18.8 19.0 20.0 21.5 21.9 28.0 29.0 30.1 31.6 32.0 ns ns ns ns ns 15.5 15.6 16.0 16.7 17.4 24.0 24.1 24.2 25.1 25.8 ns ns ns ns ns Global Clock-to-Output X5783 I/O pin to row output pin (resistive) 24 FF, 1 row RBUF IBUF BUFROW FD Clock-to-Output TICKO XC8100 XC8101 (Max) XC8103 XC8106 XC8109 X5636 Input set-up time, no delay, 1 FF IBUF Input Set-Up & Hold Time BUFGP FD X5784 TPSUF XC8100 XC8101 (Min) XC8103 XC8106 XC8109 0.1 0.3 0.3 0.1 0 0 0 0 0 0 ns ns ns ns ns TPHF XC8100 XC8101 XC8103 XC8106 XC8109 7.8 7.9 8.0 8.3 9.3 11.5 11.6 11.6 12.1 13.1 ns ns ns ns ns XC8100 XC8101 XC8103 XC8106 XC8109 12.9 13.1 13.0 12.9 13.0 22.9 23.2 23.1 23.1 23.0 ns ns ns ns ns XC8100 XC8101 XC8103 XC8106 XC8109 0 0 0 0 0 0 0 0 0 0 ns ns ns ns ns Input hold time, no delay, 24 FF per row, all rows IBUF Input Set-Up & Hold Time BUFGP FD (Min) X5784 Input set-up time, with DBUF delay, 1 FF TPSU DBUF Input Set-Up & Hold Time BUFGP FD (Min) X5630 Input hold time, with DBUF delay, 24 FF per row, all rows TPH DBUF Input Set-Up & Hold Time BUFGP FD (Min) X5630 Note: 5-40 The external pin-to-pin setup and hold times for synchronous elements depend on the intrinsic setup and hold requirements of the appropriate CLC and the relative delays of the data and clock input nets. Specifically: Tsetup = Delaydata + TsetupCLC - Delayclock Thold = Delayclock + TholdCLC - Delaydata Delay Data Data FD Clock Delay Clock CLC X5840 June 1, 1996 (Version 1.0) The data and clock delays consist of the delays associated with any blocks in the path (e.g. input buffers) and the net or wire delays. Once the design has been placed, routed and timed, the Series 8000 timing tool can be used to calculate the maximum possible delay for all paths. The actual delay will be less than these values particularly under non-worst case conditions. In most cases the delays on the clock and data paths will track. However not all nets depend identically on the same physical properties (resistance, capacitance, threshold voltage etc.) and hence not all delays will track perfectly. Extensive simulation and characterization has shown that tracking between nets within one device will be better than 70%. To guarantee actual worst case setup and hold times, the worst possible tracking should be assumed. Therefore the formulae become: Tsetup = Delaydata + TsetupCLC - 0.7* (Delayclock) Thold = Delayclock + TholdCLC - 0.7* (Delaydata) Description Reset Switching Characteristics Guidelines Delay from Master Reset pin high to device active Low width on external MR pin Delay from internal GRST to FF reset -5 V Delay from internal GRST to FF reset -3.3 V GRST input I width (High or Low) -5 V GRST input I width (High or Low) -3.3 V Power-On Reset and Initalization Time VCC above 2.5 V to device active. VCC must rise monotonically. June 1, 1996 (Version 1.0) The user should use the 70% tracking factor when analyzing and interpreting timing information. Achieving a 0 ns hold time at the pin level is a common requirement for FPGA designs. This entails having a data path which is slower than the clock path, which may be difficult if the clock has high fanout. To facilitate 0 ns hold times, an input buffer with additional delay (DBUF) is provided. This element has been designed to guarantee a 0 ns hold time even for a very heavily loaded clock signal. When using DBUF to achieve 0 ns, the clock signal must be driven by a BUFGP element and should drive no more than 24 FFs per row. All rows may be driven provided each row contains a maximum of 24 FFs. If these conditions are met then the 0 ns hold time is guaranteed and this guideline supersedes the timing requirements indicated by the Series 8000 tool. If the extra setup delay needed for DBUF cannot be tolerated, then IBUF should be used. In this case, the user may need to guarantee a positive hold time for data with respect to the clock for correct operation. The Series 8000 timing requirements combined with the tracking factor should be followed. Symbol TMRQ TMRW TGRIQ TGRIQ TGRW TGRW TPOR Device Min Max Units 3 90 120 ms s ns ns ns ns 3 ms 5 45 60 5-41 XC8100 FPGA FamilyXC8100 FPGA Family Ordering Information Example: XC8106-1 PC84C Device Type Temperature Range Speed Grade -1 Standard -2 -3 Number of Pins Package Type Note: Each Speed Grade can operate at 5 V or 3.3 V X5944 Product Availability (5/96) Pins Type Code XC8100-1 XC8101-1 XC8103-1 XC8106-1 XC8109-1 44 Plastic VQFP VQ44 C (C) (C) 44 Plastic PLCC PC44 C (C) C 84 Plastic PLCC PC84 100 Plastic PQFP PQ100 C C C C C C C 160 Plastic PQFP PQ160 225 Plastic BGFP BG225 (C) (C) C (C) C Notes: Parentheses indicate future product plans 5-42 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products SPROM Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors SPROM Products Table of Contents XC1700D Family of Serial Configuration PROMs Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlling Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPGA Master Serial Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the XC1700 Family Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC1718D, XC1736D, XC1765D, XC17128D and XC17256D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC1718L, XC1765L, XC17128L and XC17256L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-2 6-3 6-3 6-5 6-5 6-6 6-6 6-6 6-6 6-7 6-7 6-7 6-7 6-8 6-10 6-10 XC1700D Family of Serial Configuration PROMs June 1, 1996 (Version 1.0) Product Specification Features Description * The XC1700 family of serial configuration PROMs (SCPs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. * * * * * * * * * * Extended family of one-time programmable (OTP) bit-serial read-only memories used for storing the configuration bitstreams of Xilinx FPGAs On-chip address counter, incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions XC17128D or XC17256D supports XC4000 fast configuration mode (12.5 MHz) Low-power CMOS EPROM process Available in 5 V and 3.3 V versions Available in plastic and ceramic packages, and commercial, industrial and military temperature ranges Space efficient 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or 20-pin surface-mount packages. Programming support by leading programmer manufacturers. VCC VPP When the FPGA is in master serial mode, it generates a configuration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, the XACT development system compiles the FPGA design file into a standard Hex format, which is then transferred to the programmer. GND CEO CE RESET/ OE or OE/ RESET CLK Address Counter EPROM Cell Matrix TC Output OE DATA X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) June 1, 1996 (Version 1.0) 6-1 XC1700D Family of Serial Configuration PROMs Pin Description VCC DATA Positive supply pin. Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. GND CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGA's INIT pin. The polarity of this pin is controlled in the programmer interface by writing data into four high-end byte locations. This input pin is easily inverted using the Xilinx PROM programmer software (XPP). Third-party programmers have different methods to invert this pin. For RESET/OE, fill the four polarity bytes with Ones or do nothing. For RESET/OE, fill these four bytes with Zeros. CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode. CEO Chip Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! 6-2 Ground pin. Serial PROM Pinouts Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-Pin 20-Pin 1 2 3 4 5 6 7 8 2 4 6 8 10 14 17 20 Capacity Device Configuration Bits XC1718D or L XC1736D XC1765D or L XC17128D or L XC17256D or L 18,144 36,288 65,536 131,072 262,144 plus 32 bits for reset polarity control Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type Device XC3020/A/L+3120A XC3030/A/L+3130A XC3042/A/L+3142A XC3064/A/L+3164A XC3090/A/L+3190A XC3195A XC4003E XC4005E/L XC4006E XC4008E XC4010E/L XC4013E/L XC4020E Configuration Bits 14,819 22,216 30,824 46,104 64,200 94,984 53,976 95,000 119,832 147,544 178,136 247,960 329,304 XC4025E 422,168 XC5202 XC5204 XC5206 XC5210 XC5215 42,416 70,704 106,288 165,488 237,744 SCP XC1718D XC1736D XC1736D XC1765D XC1765D XC17128D XC1765D XC17128D/L XC17128D XC17256D XC17256D/L XC17256D/L XC17256D + XC17128D XC17256D + XC17256D XC1765D XC17128D XC17128D XC17256D XC17256D June 1, 1996 (Version 1.0) Controlling Serial PROMs Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. * * * * * The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC3000 or XC4000 lead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods - such as driving RESET/OE from LDC or system reset - assume that the Serial PROM internal power-on-reset is always in step with the FPGA's internal power-on-reset, which may not be a safe assumption. The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. FPGA Master Serial Mode Summary The I/O and logic functions of the Logic Cell Array and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial Mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the Serial Configuration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the Serial Configuration PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. June 1, 1996 (Version 1.0) If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The XC3000 and XC4000 families take care of this automatically with an onchip default pull-up resistor. With XC2000-family devices, the user must either configure DIN as an active output, or provide a defined level, e.g., by using an external pull-up resistor, if DIN is configured as an input. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a Serial Configuration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the D/P line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (24) and D/P goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded SCPs provide additional memory. After the last bit from the first SCP is read, the next clock signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. 6-3 XC1700D Family of Serial Configuration PROMs * If Readback is +5 V * Activated, a 5-k Resistor is Required in Series With M1 M0 During Configuration the 5 k M2 Pull-Down Resistor Overcomes the Internal Pull-Up, but it Allows M2 to be User I/O. M1 PWRDWN DOUT OPTIONAL Daisy-chained FPGAs with Different Configurations M2 HDC LDC GeneralPurpose User I/O Pins INIT * * * * * Other I/O Pins OPTIONAL Slave FPGAs with Identical Configurations XC3000 FPGA Device +5 V RESET RESET DIN CCLK VPP VCC DATA DATA CLK CLK SCP D/P CE INIT OE/RESET CEO CE Cascaded Serial Memory OE/RESET (Low Resets the Address Pointer) CCLK (OUTPUT) DIN DOUT (OUTPUT) X5090 Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. 6-4 June 1, 1996 (Version 1.0) Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. (A technique for further reducing the standby current of a Serial Configuration PROM is described in the XCELL journal, Issue 11, page 13.) Programming the XC1700 Family Serial PROMs The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and voltages are used. Different product types use different algorithms and voltages, and the wrong choice can permanently damage the device. Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET CE Inactive Low Active Inactive Active Low High High Outputs Internal Address if address < TC: increment if address > TC: don't change Held reset Not changing Held reset DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. Table 2: Data I/O Programmer Locations for Programming RESET Polarity Device XC1718D or L XC1736D XC1765D or L XC17128D or L XC17256D or L Hex Address 8DC through 8DF 11B8 through 11BB 2000 through 2003 4000 through 4003 8000 through 8003 IMPORTANT: Always be sure to use the proper programming algorithm. "D" series PROMs will not program properly using "A" -series algorithms. Always tie the VPP pin to VCC in your application. Never leave VPP floating. June 1, 1996 (Version 1.0) 6-5 XC1700D Family of Serial Configuration PROMs XC1718D, XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND -0.5 to +7.0 V VPP Supply voltage relative to GND -0.5 to +12.5 V VIN Input voltage relative to GND -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V TSTG Storage temperature (ambient) -65 to +125 C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Min Max Units Commercial Supply voltage relative to GND 0C to +70C junction 4.75 5.25 V Industrial Supply voltage relative to GND -40C to +85C junction 4.50 5.50 V Military Supply voltage relative to GND -55C to +125C case 4.50 5.50 V DC Characteristics Over Operating Condition Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) 0.4 V ICCA Supply current, active mode 10.0 mA ICCS Supply current, standby mode, XC17128D, XC17256D 50.0 A Supply current, standby mode, XC1718D, XC1736D, XC1765D 1.5 mA 10.0 A IL Input or output leakage current Commercial 3.86 V 0.32 Industrial 3.76 V 0.37 Military 3.7 -10.0 V V V Note: During normal read operation VPP must be connected to VCC 6-6 June 1, 1996 (Version 1.0) XC1718L, XC1765L, XC17128L and XC17256L Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND -0.5 to +6.0 V VPP Supply voltage relative to GND -0.5 to +12.5 V VIN Input voltage with respect to GND -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Commercial Min Max Units 3.0 3.6 V Supply voltage relative to GND 0C to +70C junction DC Characteristics Over Operating Condition Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) 0.4 V ICCA Supply current, active mode 5.0 mA ICCS Supply current, standby mode, XC1718L, XC1765L Supply current, standby mode, XC17128L, XC17265L 1.5 50.0 mA A IL Input or output leakage current 10.0 A 2.4 -10.0 V Note: During normal read operation VPP must be connected to VCC June 1, 1996 (Version 1.0) 6-7 XC1700D Family of Serial Configuration PROMs AC Characteristics Over Operating Condition CE 9 9 TSCE TSCE 10 THCE RESET/OE 11 THOE TLC 8 THC 6 TCYC 7 CLK TOE 2 1 3 TCAC 4 TOH 5 TDF TCE DATA 4 TOH X2634 Symbol Description XC1718D XC1736D XC1765D Min 1 2 3 4 5 6 7 8 9 TOE TCE TCAC TOH TDF TCYC TLC THC TSCE 10 THCE 11 THOE OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay2 Clock Periods CLK Low Time3 CLK High Time3 CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset) Max 45 60 150 XC1718L XC1765L Min Max 45 60 200 XC17128D XC17256D XC17128L XC17256L Min Min Max 25 45 50 Max 30 60 60 Units 200 100 100 25 400 100 100 40 80 20 20 20 100 25 25 25 ns ns ns ns ns ns ns ns ns 0 0 0 0 ns 100 100 20 25 ns 0 0 50 0 50 0 50 50 Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. 6-8 June 1, 1996 (Version 1.0) AC Characteristics Over Operating Condition (continued) RESET/OE CE CLK 12 TCDF Last Bit DATA First Bit 13 TOCK 15 TOOE CEO 14 TOCE 14 TOCE X3183 Symbol Description XC1718D XC1736D XC1765D Min 12 13 14 15 TCDF TOCK TOCE TOOE CLK to Data Float Delay2 CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Max 50 65 45 40 XC1718L XC1765L Min Max 50 65 45 40 XC17128D XC17256D XC17128L XC17256L Min Min Max 50 30 35 30 Max 50 30 35 30 Units ns ns ns ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. June 1, 1996 (Version 1.0) 6-9 XC1700D Family of Serial Configuration PROMs Ordering Information XC1736D - PC20 C Device Number XC1718D XC1718L XC1736D XC1765D XC1765L XC17128D XC17128L XC17256D XC17256L Operating Range/Processing C I M B Package Type PD8 DD8 SO8 VO8 PC20 = = = = = 8-Pin Plastic DIP 8-Pin CerDIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier = = = = Commercial (0 to +70C) Industrial (-40 to +85C) Military (-55 to +125C) Military (-55 to +125C) MIL-STD-883 Level B compliant Valid Ordering Combinations XC17128DPD8C XC17128DVO8C XC17128DPC20C XC17128DPD8I XC17128DVO8I XC17128DPC20I XC17128DDD8M XC1718DPD8C XC1718DSO8C XC1718DVO8C XC1718DPC20C XC1718DPD8I XC1718DSO8I XC1718DVO8I XC1718DPC20I XC17256DPD8C XC17256DVO8C XC17256DPC20C XC17256DPD8I XC17256DVO8I XC17256DPC20I XC17256DDD8M XC17256DDD8B XC17128LPD8C XC17128LVO8C XC17128LPC20C XC17128LPD8I XC17128LVO8I XC17128LPC20I XC1718LPD8C XC1718LSO8C XC1718LVO8C XC1718LPC20C XC1718LPD8I XC1718LSO8I XC1718LVO8I XC1718LPC20I XC17256LPD8C XC17256LVO8C XC17256LPC20C XC17256LPD8I XC17256LVO8I XC17256LPC20I XC1736DPD8C XC1736DSO8C XC1736DVO8C XC1736DPC20C XC1736DPD8I XC1736DSO8I XC1736DVO8I XC1736DPC20I XC1736DDD8M XC1765DPD8C XC1765DSO8C XC1765DVO8C XC1765DPC20C XC1765DPD8I XC1765DSO8I XC1765DVO8I XC1765DPC20I XC1765DDD8M XC1765DDD8B XC1765LPD8C XC1765LSO8C XC1765LVO8C XC1765LPC20C XC1765LPD8I XC1765LSO8I XC1765LVO8I XC1765LPC20I Marking Information Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. 1736D P C Device Number XC1718D XC1718L XC1736D XC1765D XC1765L XC17128D XC17128L XC17256D XC17256L 6-10 Operating Range/Processing Package Type P D S V J = = = = = 8-Pin Plastic DIP 8-Pin CerDIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier C I M B = = = = Commercial (0 to +70C) Industrial (-40 to +85C) Military (-55 to +125C) Military (-55 to +125C) MIL-STD-883 Level B compliant June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products 3V Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors 3V Products Table of Contents 3.3 V and Mixed Voltage Compatible Products FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L, XC8100 . . . . . . . . . . . . . 3 V PCI-Compliant FPGA: XC3100L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL. . . . . . . . . . . . . . . . . . . . . High-Density FPGAs Without On-chip RAM: XC5200L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Compatible Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-Time-Programmable FPGAs: XC8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX . . . . . . . . . . . . . . . . CPLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing Between 5 V and 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V Devices Driving Inputs on 5 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Devices Driving Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E/EX is Fully Compatible With 3.3 V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-1 7-2 7-2 7-2 7-2 7-3 7-4 3.3 V and Mixed Voltage Compatible Products June 1, 1996 (Version 1.0) In anticipation of the market shift from 5 V to 3.3 V products, Xilinx introduced the Zero+ product line, the industry's first 3.3 V FPGAs, in 1993. The number of 3.3 V product offerings has since tripled and includes high-performance devices with system clock speeds of 85 MHz, high-density devices, and mixed-voltage devices. Complete data sheets for the products mentioned below can be found in Chapters 3, 4, and 5 of this Data Book. 3.3 V versions of the Serial PROM devices also are available (see Chapter 6). FPGAs The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L, XC8100 The Zero+ Product Line includes three major families: the XC3000L, XC4000L and XC8100 FPGAs. These devices have quiescent supply currents below 1mA, with some below 50 A. This is important in systems where prolonged battery life is critical. 3 V PCI-Compliant FPGA: XC3100L The XC3100L is the highest performance 3.3 V FPGA, and is the only 3.3 V FPGA family that meets the stringent specifications of 3.3 V PCI applications. High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL Ranging from 5,000 to over 60,000 gates, the XC4000L and XC4000XL FPGA families represent the broadest 3.3 V product line in the industry. High-Density FPGAs Without On-chip RAM: XC5200L The XC5200L family features 5 V compatible inputs and densities from 2,000 to 23,000 gates. June 1, 1996 (Version 1.0) 5 V Compatible Inputs on 3.3 V Devices Conventional 3.3 V device inputs cannot or should not be driven substantially higher than 3.6 V. The new XC5200L inputs can, however, be driven up to 5.5 V, provided that the 5 V supply voltage is connected to one dedicated bias supply pin, called VTT, on the 3.3 V device. All Xilinx device inputs maintain their excellent protection against Electro-Static Discharge (ESD), typically 10,000 V, even in mixed-voltage applications. One-Time-Programmable FPGAs: XC8100 The XC8100 family consumes very low quiescent current when operating at 3.0 to 3.6 V. Thus, the feature-rich XC8100 is an excellent candidate for use in portable and hand-held applications. 5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX While the market slowly shifts from 5V systems to 3.3V systems, a need exists for devices to function in dual environments. The 5 V XC4000E and XC4000EX FPGA families feature a unique output structure which makes them suitable for mixed-voltage system applications. When configured in TTL mode, the XC4000E and XC4000EX can be directly mixed with 3.3 V devices without the aid of external components such as current limiting resistors. This is described in more detail under, "Interfacing Between 5 V and 3.3 V Devices" on page 7-2. CPLDs 5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 Xilinx CPLDs are an excellent fit for 5 V only and mixedvoltage systems. The Input/Output (I/O) ring can be powered by either a 5 V VCCIO or a 3.3 V VCCIO. Independent of the VCCIO voltage level, the inputs can accept 5 V and 3.3 V inputs. The rail-to-rail output level is defined by VCCIO. These single-chip solutions function extremely well in mixed-voltage systems without any performance penalty. 7-1 3.3 V and Mixed Voltage Compatible Products Supply Voltage Options Mixed-Voltage Applications Core VCC = 5 V VCC = 5 V VCC = 3.3 V Single Single I/O VCC = 3.3 V Inputs are Inputs are 5V 3.3 V 5V Dual Inputs are 5 V 3.3 V Availability Supply Supply Supply Compatible Compatible Compatible1 Key Features Reconfigurable Yes FPGAs XC3000A Now Yes Low quiescent current XC3000L Now Yes A powerdown current and A quiescent current XC3100A Now Yes Yes Highest performance 5 V FPGA XC3100L XC4000E XC4000L XC4000EX XC4000XL XC5200 Now Now Now 2H96 2H96 Now Yes XC5200L OTP FPGAs XC8100 4H96 Yes Now Yes CPLDs XC7300 XC9500 Now 2H96 Yes Yes Yes Yes Yes Yes Note 2 Note 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Highest performance 3.3 V FPGA Mixed voltage system capable High Density 3.3 V FPGAs Mixed voltage system capable Highest Density 3.3 V FPGA Best value and broadest density FPGAs Best 3.3 V FPGA value Yes 1. Hundreds of A quiescent current. 2. Design security Yes Yes Mixed voltage system capable Mixed voltage system capable Notes: 1. Provided VTT pin is connected to 5 V supply. 2. Initial XC4000XL devices do not have 5 V tolerant inputs. Future XC4000XL devices will have 5 V tolerant inputs. Contact the factory. Interfacing Between 5 V and 3.3 V Devices This section discusses the compatibility issues between devices with different supply voltages, and explains how 5 V XC4000E/EX devices are directly compatible with 3.3 V devices. In the past, almost all digital logic devices used a 5 V supply voltage. To reduce chip size and meet the demand for higher integration and lower power consumption, the semiconductor industry has started the transition to 3.3 V logic. In the future, 3.3 V will become the dominant supply voltage. Today, many designs must accommodate both types of ICs on the same board. Since both types of supply share a common ground, there are no problems interfacing logic Low levels in either direction, but there are compatibility issues for the logic High levels. 3.3 V Devices Driving Inputs on 5 V Devices The lowest output High voltage (VOH) of the 3.3 V device must exceed the VIH requirements of the 5 V device. This is not a problem if the 5 V device uses TTL-compatible input thresholds, available on all Xilinx devices. If, however, the 5 V device has CMOS input thresholds, an external pull-up resistor to 5 V on each such input will assure a sufficiently high input voltage. The resistor should be somewhere between 10 k and 1 k in value. The upper limit causes the rising input transition to be 7-2 slow; the lower limit is set by the output current sinking capability of the 3.3 V device output. In the High state, the voltage will be clamped by the ESD protection diode of the 3.3 V device, as described later in this application note. With less than 1.5 V across this resistor, the current will be fairly small, but care should be taken that the sum of these pull-up currents does not exceed the 3.3 V supply current, thereby reverse-biasing the power supply and raising the 3.3 V supply voltage to an undefined level (but obviously lower than the 5 V VCC minus a diode drop of ~0.7 V). 5 V Devices Driving Inputs on 3.3 V Devices The highest 5 V device output voltage must not force excessive current into the input of the 3.3 V device. If the 5 V device has a truly complementary CMOS output (like all Xilinx FPGAs and CPLDS except the XC4000 family devices have), then the input current must be limited by a series resistor of no less than 150 . This guarantees an input current below 10 mA, flowing through the ESD input protection diode backwards into the 3.3 V supply. That amount of input current is generally considered safe, causing neither metal migration nor latch-up problems. Care must be taken to avoid forcing the nominally 3.3 V supply voltage above its 3.6 V maximum whenever a large number of active High June 1, 1996 (Version 1.0) inputs drive the 3.3 V device, potentially causing the 3.3 V supply current to go negative. If the 5 V device has "totem-pole" n-channel-only outputs, VOH is reduced by one threshold and the series resistor can be eliminated, provided the nominally 5 V supply does not exceed 5.25 V. This is described in detail in the following section. Figure 2 shows the same curves, but with 5.25 V and 3.0 V VCC respectively. The intersection of the two curves defines the worst-case operating point of 3.8 V and 6 mA. That means that the XC4000E output drives 6 mA into the forward-biased ESD protection diode, raising the input voltage 0.8 V above 3.0 V, the assumed lowest value of the nominally 3.3 V supply voltage. XC4000E/EX is Fully Compatible With 3.3 V Logic As a default option, all XC4000E/EX have a TTL-like input threshold (compatible with 3.3 V output levels) and an nchannel-only "totem-pole" or TTL-like output structure with an n-channel transistor pulling the output to a VOH level that is one threshold below VCC. At a nominal 5.0 V VCC, the unloaded output High voltage VOH is <3.7 V. When applied to the input of a device with a nominal 3.3 V VCC, there is no additional input current, and the input level does not violate the conventional specification that prohibits input voltages more than 0.5 V above VCC. See Figure 1. If both 5 V and 3.3 V supply voltages track reasonably between their max and min values, there will never be any additional input current in excess of 1 A at any commercial or industrial operating temperature. A worst-case analysis of the interface might assume the (unrealistic) condition where the 5 V supply is at its max value (5.25 V for commercial applications), while the 3.3 V supply is at its min value of 3.0 V. Under these conditions, the interface violates the conventional specification, and drives current into the input of the 3.3 V device, as shown in figure 2. The following paragraphs explain that this interface is nevertheless reliable. For protection against electro-static discharge (ESD), all CMOS inputs and I/O pins usually have a diode between the pin and the nearest VCC connection. This diode prevents the input from going substantially more positive than VCC, which might destroy the input transistor by rupturing its gate oxide. At room temperature, this ESD protection diode conducts negligible current at < 0.6 V forward bias, and conducts ~1 mA at ~0.7 V forward bias, typical for any silicon junction diode. These voltages have a predictable negative temperature coefficient of -2 mV per degree C. At 85 degrees C, these voltages are, therefore 120 mV lower. Figure 1 superimposes the output characteristic of the XC4000E/EX and the input current characteristic of a typical 3.3 V device input. Both supply voltages are at their nominal value, but the die temperatures are at their worstcase value of 85 degrees C, and worst-case processing is assumed. June 1, 1996 (Version 1.0) IIN I mA 10 9 Nominal Supply Voltages 85C IOUT 8 7 6 5 4 3 2 1 VCC 3.0 3.3 3.5 4.0 4.5 5.0 5.5 X5969 Figure 1: XC4000E Output in "TTL-Mode" driving 3.3 V Device Input with Both Supplies at Nominal Voltage (5.0 V and 3.3 V) IIN I mA IOUT 10 9 8 7 6 5 4 3 2 1 VCC 3.0 3.5 4.0 4.5 5.0 5.5 X5970 Figure 2: XC4000E Output in "TTL-Mode" driving 3.3 V Device Input with Both Supplies at Extreme Values (5.25 V and 3.0 V) 7-3 3.3 V and Mixed Voltage Compatible Products Although this input condition is not covered by the conventional specification, it does not cause any harm and does not affect reliability. ESD protection diodes are designed to conduct hundreds of mA, and the absolute value of the input voltage with respect to ground will never exceed 3.9 V. If the input pin is part of an I/O structure, there is theoretically possibility of causing latch-up, but all reputable IC manufacturers design their circuits such that latch-up does not occur below 100 mA of input current per pin. The system designer must estimate the sum of all maximum input currents, and calculate the impact of this current flowing backwards towards the 3.3 V supply. But even if the total 3.3 V supply current goes to zero, VCC for the 3.3 V device is still limited to < 3.6 V (the highest output voltage of the 5 V device minus the forward voltage drop of the ESD diode). 7-4 Conclusion 5 V XC4000E/EX devices can be freely mixed with 3.3 V devices, without any current or voltage limiting interface resistors, if the following conditions are met: * The 5 V XC4000E/EX devices are in their default "TTL mode" with respect to input thresholds and output levels. * The upper limit on the 5 V VCC is 5.25 V and the lower limit on the 3.3 V supply is 3.0 V, as per standard commercial specifications. * For industrial operating conditions with higher Vcc max, the user must make sure that the absolute difference between the two supply voltages does not exceed 2.20 V. Specifically, if the nominally 5 V VCC is at its max value of 5.50 V, the nominally 3.3 V VCC must not be lower than 3.30 V. June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products HardWire Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors HardWire Products Table of Contents Xilinx HardWireTM Array Overview Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advantages of Using Xilinx HardWire Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire versus Full ASIC Gate Array Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Coverage and Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging and Silicon Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for the Entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The HardWire Product Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-1 8-2 8-2 8-3 8-3 8-3 Xilinx HardWireTM Array Overview June 1, 1996 (Version 1.0) Features * * Mask-programmed versions of Xilinx programmable devices - Specifically designed for easy conversions - Significant cost reduction for high-volume applications - Same specifications and architecture as the programmable devices - On-chip scan path test registers - High-performance CMOS process Easy conversion with guaranteed results - "Design Once Methodology" requires no customer engineering resources for conversion - Fully pin-for-pin compatible with the programmable device - Support for most popular package types - PLD database file used to generate productionready prototypes - Automatic test vector generation with >95% fault coverage - Prototypes built on production line The following is an overview of the Xilinx HardWire device product line. Product specifications for the HardWire devices and additional information are available in a separate publication - The HardWire Data Book. HardWire Arrays are mask-programmed versions of the popular XC2000, XC3000, XC4000, XC5000, and XC8000 series FPGAs, as well as the XC9500 CPLDs. The HardWire devices provide a transparent migration path from a programmable logic device to a cost-reduced device without the engineering burden associated with conventional gate-array re-design. In standard programmable logic, the functions and interconnections are determined by configuration data stored in memory cells. In the HardWire components, the memory cells and the logic they control are replaced by metal connections. All other circuitry in the HardWire devices is identical to the corresponding programmable logic's internal circuitry. Thus, a HardWire device is a semicustom device manufactured to provide a specific functionality, yet is completely compatible with the programmable device it replaces. June 1, 1996 (Version 1.0) Advantages of Using Xilinx HardWire Arrays Xilinx offers an easy, seamless process for achieving the shortest Time-to-Volume solution possible. Simply stated, our unique Design Once methodology allows engineers to develop their design in a programmable device, then switch to a lower cost mask-programmed product without utilizing additional internal resources. Production is often started using the same programmable logic in which the application was designed. This flexibility allows the product to be introduced to the market quickly. Later in the production process, the PLD can be replaced with a HardWire Array without expending additional engineering time and effort to redesign either the FPGA's circuit or the printed circuit board. Other conversion methodologies introduce risk at each project milestone of the conversion process. Only the Xilinx Design Once Methodology can offer this no risk, 100% pin-for-pin compatible path to dramatic cost reductions. Whenever a system incorporating Xilinx PLDs ramps to high production volumes, the HardWire mask-programmed solution should be the first consideration for cost reduction. Because the HardWire implementation dramatically reduces the die size by removing programmable elements, the resulting device is much smaller than the equivalent PLD. This smaller die provides a no-risk path to achieve dramatic cost reductions. HardWire versus Full ASIC Gate Array Implementation Converting a device from programmable logic to a HardWire Array has many advantages over generic gate array redesign. The most important is that the Xilinx HardWire methodology requires no additional customer engineering to convert the programmable logic design into a fully tested, completely verified mask-programmed design. This ease of conversion is available only through Xilinx because the PLD database file is the actual physical data base previously created and verified in the process of developing the PLD design. Xilinx has the only methodology that preserves all attributes of the original physical data base file. If the design is mapped to a third party library for conversion at the schematic level to another technology, the design must be verified and prototyped. Third party implementation will change the placement and routing, thereby changing the design's performance characteristics. 8-1 Xilinx HardWireTM Array Overview Thus, the revised device needs to be re-verified and retested in the system to be certain both the functionality and the performance still meet the application's requirements. coverage. However, they often settle for significantly less because the iterative process is extremely time consuming and increases exponentially as fault coverage is increased. A comparison of the activities required to convert a HardWire Array versus a standard array is shown in Figure 1. Any third-party conversion from a Xilinx FPGA or CPLD to a gate array or other similar technology will require test vector generation. Typically, the original designers create the test vectors, since they are most familiar with the design implementation. This method ties up valuable design resources and reverses the value of the original decision to use programmable logic for their ease of design and time-to-market advantages. Another alternative is to contract with the conversion or gate array vendor to create the test vectors. This method can be both time-consuming and expensive, since vendors usually charge by the vector. In some cases, conversion or gate array vendors will accept a design without test vectors, but the customer accepts all the liability of determining whether the resulting device is production worthy. In today's competitive market, many projects can not afford the risk of possible respins if the design doesn't work. Reverifying the Design In conventional gate array conversion (redesign), the design must be re-verified after the schematic is translated or recaptured. The process of reverifying a design is rigorous and time-consuming. Functional simulation vectors need to be created, and the device must be exhaustively simulated before and after place and route. A suitable test methodology must be considered and implemented. In contrast, no additional effort is required when converting to Xilinx HardWire Arrays. The HardWire design is self-verifying because the actual PLD database file is used for the conversion. Fault Coverage and Test Vectors All designs need to be testable. In a traditional mask-programmed gate array, the designer is required to build in testability and generate test vectors that verify chip performance by exercising as much of the device's circuitry as possible. Most designers strive for greater than 95% fault Converting from a Xilinx programmable to a HardWire device requires no test vector generation. Xilinx guarantees greater than 95% fault coverage through a proprietary Automatic Test Vector Generation methodology. All HardWire Arrays are 100% fully guaranteed to work in the user's application exactly like the programmable logic. Working Xilinx FPGA Design Generic Gate Array * Convert netlist to G/A format * Logic changes for design compatibility * Logic changes for pin compatibility * Logic changes for configuration emulation * Logic changes for Boundary Scan * Design Check * Functional Simulation * Place and Route * Back-Annotation * Timing simulation and new models * Test Vector generation * Create 2-4 custom masks Xilinx HardWire Array * Design Check * Design Conversion * Custom Mask X5945 Figure 1: Steps Involved in Converting a PLD Design to a Gate Array as Compared to a Hard Wire Array 8-2 June 1, 1996 (Version 1.0) Packaging and Silicon Considerations All of the physical attributes of the HardWire Arrays are virtually identical to the programmable logic devices. Xilinx uses the same qualified fabrication facilities for both the PLD and HardWire devices. The same IC process, as well as packaging, assembly, and test facilities, are used. This allows users to circumvent costly and time-consuming requalification efforts. Converting from a Xilinx programmable logic device to anything but a Xilinx HardWire Array means a change to silicon, packaging, assembly and test. Each of these changes adds an element of risk into the qualification process. Support for the Entire Product Life Cycle Figure 2 shows the typical life cycle of a high-volume product, and illustrates the optimal way for using the programmable and HardWire devices. During the development, prototype, and initial production stages, the programmable device is the best choice. Later in the life-cycle, when the design is stable and in high volume production, the HardWire Array can be used in place of the original programmable device. Since the circuit board was designed initially for a programmable device, production can be switched back from the HardWire Array to the programmable device if the situation warrants. For example, if demand for the product increases dramatically, production can be increased in days or weeks by using programmable devices. In addition, a change can be quickly made to the product, since there is no manufacturing lead-time for an off-the-shelf programmable device. Production can be switched to programmable devices as the product nears the end of the life cycle, avoiding end-oflife buys and the risk of obsolescence. Furthermore, designs implemented with multiple static RAM-based FPGAs can be cost reduced incrementally, converting one or more of the programmable devices while leaving the others for future conversion. As each PLD is converted to a Xilinx HardWire Array, the user enjoys a lower cost for that unit, while maintaining the ease-of-use of off-the-shelf programmable logic in the other sockets. When all of the devices are converted, the storage element can then be removed, giving even further cost reductions. This flexibility is unique to Xilinx, and allows OEMs to achieve cost reductions quickly with minimal effort. The HardWire Product Series As listed in Table 1, the HardWire product chart, there is a range of products available for Xilinx FPGAs and XC9500 CPLDs. For designs developed using the Xilinx XC4000 family, there are two HardWire options. The XC4400 family is based on Xilinx advanced technology. It is most beneficial for higher volume applications, as well as XC4000E designs utilizing Xilinx's Select-RAMTM features, and low power 3.3 volt designs. For an application with low annual volumes (as low as 1500 units) and where a low NRE is required, the XC4300 family provides the best fit. Xilinx also supports the low-power 3.3 volt XC2000L and XC3000L. Programmable Logic Volume HardWire Array Volume Unplanned Upside Production Ramp-Up V O L U M E End-of-Life HardWire Array X5946 Figure 2: Typical High Volume Product Life Cycle June 1, 1996 (Version 1.0) 8-3 Xilinx HardWireTM Array Overview Table 1: HardWire Product Chart1 PLD Family H/W Equivalent XC2000 XC3000/A XC2300 XC3330 XC3342 XC3390 XC4495T XC4303 XC4305 XC4310 XC4313 XC4403/H XC4405/H XC4406 XC4408 XC4410 XC4413 XC4425 XH4028EX XH4036EX XH4044EX XH4052EX XH4062EX XC5402 XC5404 XC5406 XC5410 XC5415 XH8103 XH8106 XH8109 XC95144 XC95180 XC95216 XC95288 XC3100A XC3195 XC4000/E2 XC4000EX XC5200 XC8100 XC9500 Minimum Order Quantity (KU) 7 10 6 4 10 6 4 1.5 1.5 10 10 5 5 5 3.5 2.5 2.5 2.5 2.5 2.5 2.5 10 10 5 5 3.5 10 10 6 10 10 10 10 Minimum Shipment (KU) 2 2 1 0.5 2 2 1 0.4 0.4 2 2 1 1 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 1 1 0.5 2 2 1 10 10 10 10 Production Availability Now Q4/96 Q4/96 Q1/97 Q1/97 Q1/97 Now Q2/97 Notes: 1. Industrial temperature grades are available for all products. 2. The XC4300 supports the XC4000 design features. The XC4400 supports both the XC4000 and XC4000E design features. 8-4 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Military Products 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Military Products Table of Contents High-Reliability and Military Products Unmatched Hi-Rel Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Committed to the Hi-Rel Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Xilinx Hi-Rel Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 High-Reliability and Military Products June 1, 1996 (Version 1.0) Xilinx is the world's leading supplier of High-Reliability Programmable Logic Devices (Hi-REL PLDs) to the aerospace, military, defense electronics, and related markets. These devices are being used in a wide variety of programs, including applications such as electronic warfare, missile guidance and targeting, RADAR/SONAR, communications, signal processing, aerospace and avionics. Unmatched Hi-Rel Product Offering Xilinx offers a wide variety of devices, delivering the fastest and biggest Hi-Rel devices available. Products with up to 25,000 gates are available today, with even higher densities to come. Xilinx offers multiple product families to allow you to select the right device to meet your design requirements. This broad range of devices is available in a wide variety of speed and package options. Both military temperature range and full MIL-STD-883B/SMD versions are available as standard, off-the-shelf products, in through-hole and surface mount packages. Committed to the Hi-Rel Market Xilinx understands that you need to be able to count on your Hi-Rel supplier. Xilinx is committed to our customers, and we are expanding our Hi-Rel support and product portfolio. The unique capabilities of the Xilinx FPGA solution provide increased design flexibility, field-upgradability and system feature integration, while eliminating the NREs, lead-time and inventory problems of custom logic and gate arrays. Now more than ever, Xilinx is your Hi-Rel logic solution. Xilinx Hi-Rel Products Table 1 summarizes Xilinx high density and high performance product offerings. The following pages contain a complete listing of current Xilinx SMD (Standard Microcircuit Drawings) devices and "B" grade equivalents. Architectural descriptions for these FPGA products can be found in Chapter 4. For additional information, including Data Sheets on Hi-Rel devices, contact the nearest Xilinx Sales Office or Sales Representative. Table 1: High Density and High Performance Products Family XC4000/E XC3100A June 1, 1996 (Version 1.0) Devices XC4003A XC4005/E XC4010/E XC4013/E XC4025E XC3142A XC3190A XC3195A Features Highest Density/Most Features Family * 3,000-25,000+ gates * Up to 256 user-definable I/Os * Extensive system features include on-chip user RAM, built-in 1149.1 test support and fast carry logic Highest Performance Family * 2,500-7,500 gates * Up to 144 user-definable I/Os 9-1 High-Reliability and Military Products Table 2: Xilinx SMD (Standard Microcircuit Drawing) XC1700 Products SMD Number 5962-9471701MPA 5962-9561701MPA Equivalent "B" Grade P/N XC1765DDD8B XC17256DDD8B Speed Package DD8 DD8 Mark Loc TOP TOP XC2000 Products SMD Number 5962-8863801XC 5962-8863802XC 5962-8863803XC 5962-8863804XC Equivalent "B" Grade P/N XC2018-33PG84B XC2018-50PG84B XC2018-70PG84B XC2018-100PG84B Speed -33 -50 -70 -100 Package PG84 PG84 PG84 PG84 Mark Loc TOP TOP TOP TOP Equivalent "B" Grade P/N XC3020-50PG84B XC3020-70PG84B XC3020-100PG84B XC3020-50CB100B XC3020-70CB100B XC3020-100CB100B Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 Package PG84 PG84 PG84 CB100 CB100 CB100 CB100 CB100 CB100 CQ100 CQ100 CQ100 CQ100 CQ100 CQ100 Mark Loc TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID XC3000 Products SMD Number 5962-8994801MXC 5962-8994802MXC 5962-8994803MXC 5962-8994801MNC 5962-8994802MNC 5962-8994803MNC 5962-8994801MMC 5962-8994802MMC 5962-8994803MMC 5962-8994801MYA* 5962-8994802MYA* 5962-8994803MYA* 5962-8994801MTA* 5962-8994802MTA* 5962-8994803MTA* XC3020-50CQ100B XC3020-70CQ100B XC3020-100CQ100B * Do Not Use for New Designs (package to be obsoleted). Use "CB" Package Instead. 9-2 June 1, 1996 (Version 1.0) XC3000 Products (continued) SMD Number Equivalent "B" Grade P/N 5962-8971301MXC XC3042-50PG84B 5962-8971302MXC XC3042-70PG84B 5962-8971303MXC XC3042-100PG84B 5962-8971301MZC XC3042-50PG132B 5962-8971302MZC XC3042-70PG132B 5962-8971303MZC XC3042-100PG132B 5962-8971301M9C XC3042-50CB100B 5962-8971302M9C XC3042-70CB100B 5962-8971303M9C XC3042-100CB100B 5962-8971301MMC 5962-8971302MMC 5962-8971303MMC 5962-8971301MYA* XC3042-50CQ100B 5962-8971302MYA* XC3042-70CQ100B 5962-8971303MYA* XC3042-100CQ100B 5962-8971301MNA* 5962-8971302MNA* 5962-8971303MNA* Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 Package PG84 PG84 PG84 PG132 PG132 PG132 CB100 CB100 CB100 CB100 CB100 CB100 CQ100 CQ100 CQ100 CQ100 CQ100 CQ100 Mark Loc TOP TOP TOP TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID * Do Not Use for New Designs (package to be obsoleted). Use "CB" Package Instead. SMD Number 5962-8982301MXC 5962-8982302MXC 5962-8982303MXC 5962-8982301MZC 5962-8982302MZC 5962-8982303MZC 5962-8982301MTC 5962-8982302MTC 5962-8982303MTC 5962-8982301MYA* 5962-8982302MYA* 5962-8982303MYA* 5962-8982301MUA* 5962-8982302MUA* 5962-8982303MUA* Equivalent "B" Grade P/N XC3090-50PG175B XC3090-70PG175B XC3090-100PG175B XC3090-50PG164B XC3090-70PG164B XC3090-100PG164B XC3090-50CQ164B XC3090-70CQ164B XC3090-100CQ164B Speed -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 Package PG175 PG175 PG175 CB164 CB164 CB164 CB164 CB164 CB164 CQ164 CQ164 CQ164 CQ164 CQ164 CQ164 Mark Loc TOP TOP TOP BASE BASE BASE LID LID LID BASE BASE BASE LID LID LID * Package OBSOLETE. Use "CB" Package Instead. June 1, 1996 (Version 1.0) 9-3 High-Reliability and Military Products XC3100A Products SMD Number 5962-9561001MXC 5962-9561002MXC 5962-9561001MUC 5962-9561002MUC 5962-9561001MYC 5962-9561002MYC 5962-9561001MZC 5962-9561002MZC 5962-9561101MXC 5962-9561102MXC 5962-9561101MYC 5962-9561102MYC 5962-9561101MZC 5962-9561102MZC 5962-9561201MXC 5962-9561202MXC 5962-9561201MYC 5962-9561202MYC 5962-9561201MZC 5962-9561202MZC XC4000 Products SMD Number 5962-9471201MXC 5962-9471202MXC 5962-9471201MYC 5962-9471202MYC 5962-9471201MZC 5962-9471202MZC 5962-9225201MXC 5962-9225202MXC 5962-9225203MXC 5962-9225201MYC 5962-9225202MYC 5962-9225203MYC 5962-9225201MZC 5962-9225202MZC 5962-9225203MZC 9-4 Equivalent "B" Grade P/N XC3142A-5PG84B XC3142A-4PG84B XC3142A-5PG132B XC3142A-4PG132B XC3142A-5CB100B XC3142A-4CB100B XC3190A-5PG175B XC3190A-4PG175B XC3190A-5CB164B XC3190A-4CB164B XC3195A-5PG175B XC3195A-4PG175B XC3195A-5CB164B XC3195A-4CB164B Equivalent "B" Grade P/N XC4003A-10PG120B XC4003A-6PG120B XC4003A-10CB100B XC4003A-6CB100B XC4005-10PG156B XC4005-6PG156B XC4005-5PG156B XC4005-10CB164B XC4005-6CB164B XC4005-5CB164B Speed -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 -5 -4 Package PG84 PG84 PG132 PG132 CB100 CB100 CB100 CB100 PG175 PG175 CB164 CB164 CB164 CB164 PG175 PG175 CB164 CB164 CB164 CB164 Mark Loc TOP TOP TOP TOP BASE BASE LID LID TOP TOP BASE BASE LID LID TOP TOP BASE BASE LID LID Speed -10 -6 -10 -6 -10 -6 -10 -6 -5 -10 -6 -5 -10 -6 -5 Package PG120 PG120 CB100 CB100 CB100 CB100 PG156 PG156 PG156 CB164 CB164 CB164 CB164 CB164 CB164 Mark Loc TOP TOP BASE BASE LID LID TOP TOP TOP LID LID LID BASE BASE BASE June 1, 1996 (Version 1.0) XC4000 Products (continued) SMD Number Equivalent "B" Grade P/N 5962-9230501MXC XC4010-10PG191B 5962-9230502MXC XC4010-6PG191B 5962-9230503MXC XC4010-5PG191B 5962-9230501MYC XC4010-10CB196B 5962-9230502MYC XC4010-6CB196B 5962-9230503MYC XC4010-5CB196B 5962-9230501MZC 5962-9230502MZC 5962-9230503MZC 5962-9473001MXC XC4013-10PG223B 5962-9473002MXC XC4013-6PG223B 5962-9473001MYC XC4013-10CB228B 5962-9473002MYC XC4013-6CB228B 5962-9473001MZC 5962-9473002MZC June 1, 1996 (Version 1.0) Speed -10 -6 -5 -10 -6 -5 -10 -6 -5 -10 -6 -10 -6 -10 -6 Package PG191 PG191 PG191 CB196 CB196 CB196 CB196 CB196 CB196 PG223 PG223 CB228 CB228 CB228 CB228 Mark Loc TOP TOP TOP BASE BASE BASE LID LID LID TOP TOP BASE BASE LID LID 9-5 High-Reliability and Military Products 9-6 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Programming Support 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Programming Support Table of Contents HW-130 Programmer Programs All Xilinx Nonvolatile Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Socket Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Requirements and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Selector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-1 10-1 10-1 10-1 10-1 10-2 HW-130 Programmer June 1, 1996 (Version 1.0) Programs All Xilinx Nonvolatile Devices Programming Socket Adapters * * * * * * XC1700 Serial PROMs XC7000 CPLDs XC8100 FPGAs XC9500 CPLDs Supports all Xilinx package types Programmer Accessories * * * * Universal international power supply Power cord options for US/Asia, UK, EU and KK standards. Serial download cable and adapters Users manual * Supports all package styles: PLCC, PQFP, BGA, SOIC, VOIC, PGA and DIP CPLD adapters for the HW-120 may be used on the HW-130 Electrical Requirements and Physical Specifications * * * * * Operating voltage: 100-250 VAC, 50-60 Mhz Power consumption: 1.0 Amps Dimensions: 6" x 7.75" x 2" Weight: 1 lb. Safety standards: approved by UL, CSA, TUV Interface Software and System Requirements New Programming Algorithm Support The programmer software operates on a variety of different platforms. Table 1 indicates the minimum system requirements for each of the supported platforms. In all cases, a 3.5" disk drive or a CD-ROM drive and an RS-232 serial port are required. A mouse is recommended. * * * Available via the Xilinx BBS and e-mail. Send e-mail to xdocs@Xilinx. com with "search hw130" in the subject field. For the bulletin board, refer to page 6-2 in the data book. Type "F" and select directory #3. Select either Programming Support or type "Zhw130" to view all HW130 related files. Programmer Functional Specifications * * * * * * * * Device programming and verification CPLD security control PROM reset polarity control Checksum calculation and comparison Blank check and signature ID tests Master device program upload File transfer and comparison Self check and auto calibration Table 1: Interface Software and System Requirements Requirements Memory Needed Hard Disk Space System Software DOS Windows 3.1 Windows 95 Windows NT Sun OS Solaris HP9000/700 IBM RS6000 540KB 4MB 8MB 16MB -- -- -- -- 2MB 2MB 2MB 2MB 1MB 1MB 1MB 1MB 3.3 or 3.1 or greater 4.00 3.1 or greater SunOS 4.1.3 or SunOS 5.4 or HP-UX A09.05 AIX 3.2 or greater greater, X11R5 greater, or greater, greater, with Motif 1.2 or X11R5 with X11R5 with X11R5 with greater Motif 1.2 or Motif 1.2 or Motif 1.2 or greater greater greater June 1, 1996 (Version 1.0) 10-1 HW-130 Programmer Adapter Selector Table Product Family XC7200A XC7200A XC7200A XC7200A XC7300 XC7300 XC7300 XC7300 XC7300 XC7300 XC7300 XC7300 XC7300 Package Types PLCC/CLCC 44 PLCC/CLCC 68 PLCC/CLCC 84 PGA 84 PLCC/CLCC 44 PQFP 44 VQFP 44 PLCC/CLCC 68 PLCC/CLCC 84 PQFP 100 PGA 144 PQFP 160 BGA 225 Adapter P/N HW-132-PC44 HW-132-PC68 HW-132-PC84 HW-132-PG84 HW-133-PC44 HW-133-PQ44 HW-133-VQ44 HW-133-PC68 HW-133-PC84 HW-133-PQ100 HW-133-PG144 HW-133-PQ160 HW-133-BG225 XC1700 XC1700 DIP 8 PLCC20/SO8/VO8 HW-137-DIP8 HW-137-PC20/SO8 XC8100 XC8100 XC8100 XC8100 XC8100 XC8100 PLCC/CLCC 44 VQFP 44 PLCC 84 PQFP 100 PQFP 160 BGA 225 HW-138-PC44 HW-138-VQ44 HW-138-PC84 HW-138-PQ100 HW-138-PQ160 HW-138-BG225 Calibration Adapter 10-2 HW-130-CAL June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Packages and Thermal Characteristics 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Packages and Thermal Characteristics Table of Contents Packages and Thermal Characteristics Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow Soldering Process Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic DIP Packages -- PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Packages -- SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSOP Packages -- VO8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLCC Packages -- PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQFP Packages -- PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP Packages -- TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . VQFP Packages -- VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA Packages -- BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic DIP Packages -- DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic PGA Packages -- PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299, PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ceramic Brazed QFP Packages -- CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . CLCC Packages -- CC20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic PGA Packages -- PP132, PP175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windowed CLCC Packages -- WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal Quad Packages -- MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-3 11-6 11-6 11-14 11-15 11-17 11-18 11-21 11-23 11-25 11-26 11-27 11-29 11-30 11-31 11-32 11-38 11-42 11-45 11-48 11-49 11-61 11-67 11-68 11-70 11-71 Packages and Thermal Characteristics June 1, 1996 (Version 1.0) Number of Available I/O Pins Max 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 225 228 240 299 304 352 411 432 499 I/O XC7236A 36 XC7272A 72 XC7318 38 36 56 72 38 XC7336 38 38 XC7336Q 38 38 XC7354 58 38 XC7372 84 57 72 84 XC73108 120 72 84 XC73144 156 XC9536 34 XC9572 72 69 72 XC95108 108 69 81 108 XC95144 133 81 133 XC95180 168 133 168 XC95216 168 133 168 XC95288 192 XC95432 240 240 XC95576 240 240 XC3020/A/L & XC3120A 64 58 64 64 XC3030/A/L & XC3130A 80 34 54 58 74 80 XC3042/A/L & XC3142A/L 96 74 82 96 XC3064/A/L & XC3164A 120 70 110 110 XC3090/A/L & XC3190A/L 144 70 120 XC3195A 176 70 58 120 120 120 136 156 34 168 XC4003E 80 61 77 XC4005E 112 61 77 XC4005L 112 61 XC4006E 128 XC4008E XC4010E 192 96 120 138 144 144 144 144 138 176 176 144 80 112 112 112 112 112 61 113 125 128 128 144 61 129 144 160 61 129 160 160 160 XC4010L 160 61 XC4013E 192 XC4013L 192 160 XC4020E 224 160 192 112 153 129 144 160 160 160 192 192 192 192 192 XC4025E 256 XC4028EX 256 160 193 256 256 256 XC4028XL 256 160 193 256 256 256 XC4036EX 288 256 288 288 XC4036XL 288 256 288 288 June 1, 1996 (Version 1.0) 192 192 193 192 193 256 256 11-1 Packages and Thermal Characteristics Number of Available I/O Pins (Continued) Max 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 225 228 240 299 304 352 411 432 499 I/O XC4044EX 320 320 320 XC4044XL 320 320 320 XC4052XL 352 352 352 XC4062XL 384 384 XC5202 84 65 81 84 XC5204 124 65 81 117 124 124 XC5206 148 65 81 117 133 148 148 148 XC5210 196 65 117 133 149 164 196 196 196 XC5215 244 164 197 244 244 244 XC6209 180 180 180 XC6216 242 199 242 XC6236 384 XC6264 512 XC8100 32 32 XC8101 80 32 61 72 XC8103 128 32 61 64 XC8106 168 61 76 129 192 XC8109 208 61 129 192 11-2 84 133 196 June 1, 1996 (Version 1.0) Package Options PLCC JEDEC 50 mil Plastic PQFP EIAJ 0.65/0.5 mm Plastic HQFP EIAJ 0.65/0.5 mm Plastic/Metal TQFP EIAJ 0.5 mm Plastic VQFP EIAJ 0.5 mm Plastic CQFP JEDEC 25 mil Ceramic BGA JEDEC 1.5 mm FR4 C, I C, I C, I C, I C, I M, B C Throughhole PGA JEDEC 100 mil Ceramic/ Plastic C, I, M, B PC PQ HQ TQ/HT VQ CB BG PG, PP Surface Mount Standard Lead Pitch Body Temperature Options Ordering Code XC7236A XC7272A XC7318 XC7336 XC7336Q XC7354 XC7372 XC73108 XC73144 44 68, 84 44 44 44 44, 68 68, 84 84 XC9536 XC9572 44 84 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576 84 XC3020/A/L & XC3120A XC3030/A/L & XC3130A XC3042/A/L & XC3142A/L XC3064/A/L & XC3164A XC3090/A/L & XC3190A/L XC3195A XC4003E XC4005E XC4005L XC4006E XC4008E XC4010E XC4010L XC4013E XC4013L XC4020E 84 44 44 44 44 100 100,160 160 225 225 44 100 100, 160 100, 160 160 160 100 100 100 208 208 208, 304 304 304 68, 84 100 44, 68, 84 100 100 100 68, 84 100 100, 144 100, 144 84 160 144 144 84 160, 208 84 160, 208 84 84 84 84 84 84 84 100 100, 160, 208 208 160, 208 160, 208 160, 208 208 160, 208, 240 208, 240 June 1, 1996 (Version 1.0) 144 184 100 84 64 84 100 84, 132 132 144, 176 164 175 175, 223 100 144 164 120 156 196 255 156 191 191 228 225 225 144 176 208, 240 208, 240 223 223 11-3 Packages and Thermal Characteristics Package Options (Continued) PLCC JEDEC 50 mil Plastic PQFP EIAJ 0.65/0.5 mm Plastic HQFP EIAJ 0.65/0.5 mm Plastic/Metal TQFP EIAJ 0.5 mm Plastic VQFP EIAJ 0.5 mm Plastic CQFP JEDEC 25 mil Ceramic BGA JEDEC 1.5 mm FR4 C, I C, I C, I C, I C, I M, B C Throughhole PGA JEDEC 100 mil Ceramic/ Plastic C, I, M, B PC PQ HQ TQ/HT VQ CB BG PG, PP 352 352 432 432 432 432 432 223, 299 299 299 411 411 411 411 411 499 Surface Mount Standard Lead Pitch Body Temperature Options Ordering Code XC4025E XC4028EX XC4028XL XC4036EX XC4036XL XC4044EX XC4044XL XC4052XL XC4062XL 240, 304 208, 240, 304 208, 240, 304 304 304 XC5202 XC5204 XC5206 XC5210 XC5215 84 84 84 84 100 100, 160 100, 160, 208 160, 208, 240 160 208, 240, 304 XC6209 XC6216 XC6236 XC6264 84 84 240 XC8100 XC8101 XC8103 XC8106 XC8109 44 84 84 84 84 100 100 100, 160 160 228 144 144 144, 176 144, 176 100 100 100 225 225, 352 240 156 156 191 223 299 299 299 44 44 44 225 225 Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or 0.100"). The EIAJ standards for PQFP, HQFP, TQFP, and VQFP packages define package dimensions in millimeters. These 11-4 packages have a lead spacing of 0.5 mm, except for the 100- and 160-pin PQFP packages, which have a lead spacing of 0.65 mm. Because of the potential for measurement discrepancies, this Data Book provides measurements in the controlling standard only, either inches or millimeters. June 1, 1996 (Version 1.0) EIA Standard Board Layout of Soldered Pads for QFP Devices M ID e e e M IE b2 l2 e Table 1: Dimensions for Xilinx Quad Flat Packs1 Dim. PQ44 VQ64 PQ100 PQ160 HQ/MQ/PQ208 VQ/TQ100 TQ144 TQ176 HQ/MQ/PQ240 HQ304 MID 10.40 9.80 20.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20 MIE 10.40 9.80 14.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20 e 0.80 0.50 0.65 0.65 0.50 0.50 0.50 0.50 0.50 0.50 b2 0.4 - 0.6 0.3 - 0.4 0.3 - 0.5 0.3 - 0.5 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 I2 1.80 1.60 1.802 1.80 1.60 1.60 1.60 1.60 1.60 1.60 Notes: 1. Dimensions in millimeters 2. For 3.2 mm footprint per MS022, JEDEC Publication 95. Cavity Up or Cavity Down Clockwise or Counterclockwise Most Xilinx devices attach the die against the inside bottom of the package (the side that does not carry the Xilinx logo). This is called cavity-up, and has been the standard IC assembly method for over 25 years. This method does not provide the best thermal characteristics. Pin Grid Arrays (greater than 130 pins) and Ceramic Quad Flat Packs are assembled "Cavity Down", with the die attached to the inside top of the package, for optimal heat transfer to the ambient air. The orientation of the die in the package and the orientation of the package on the PC board affect the PC board layout. PLCC and PQFP packages specify pins in a counterclockwise direction, when viewed from the top of the package (the surface with the Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages have pin 1 in one corner, with one exception: The 100- and 165pin CQFPs (CB100 and CB164) for the XC3000 devices have pin 1 in the center of one edge. For most packages this information does not affect how the package is used because the user has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack (CQFP) packages however, the leads can be formed to either side. Therefore, for best heat transfer to the surrounding air, CQFP packages should be mounted with the logo up, facing away from the PC board. CQFP packages specify pins in a clockwise direction, when viewed from the top of the package. The user can make the pins run counterclockwise by forming the leads such that the logo mounts against the PC board. However, heat flow to the surrounding air is impaired if the logo is mounted down. June 1, 1996 (Version 1.0) 11-5 Packages and Thermal Characteristics Thermal Management Modern high speed logic devices consume an appreciable amount of electrical energy. This energy invariably turns into heat. Higher device integration drives technologies to produce smaller device geometry and interconnections. With smaller chip sizes and higher circuit densities, heat generation on a fast switching CMOS circuit can be very significant. The heat removal needs for these modern devices must be addressed. in junction temperature is monitored with the forward-voltage drop of the precalibrated diode. Typically, three identical samples are tested at each data point. The reproducibility error in the set-up is within 6%. Definition of Terms TJ Junction Temperature -- the maximum temperature on the die, expressed in C (degree Celsius) TA Ambient Temperature -- expressed in C. Managing heat generation in a modern CMOS logic device is an industry-wide pursuit. However, unlike the power needs of a typical Application Specific Integrated Circuit (ASIC) gate array, the power requirements for FPGAs are not determined as the device leaves the factory. Designs vary in power needs. TC The temperature of the package body taken at a defined location on the body. This is taken at the primary heat flow path on the package and represents the hottest part on the package -- expressed in C. Tl The isothermal fluid temperature when junction to case temperature is taken -- expressed in C. There is no way of anticipating the power needs of an FPGA device short of depending on compiled data from previous designs. For each device type, primary packages are chosen to handle `typical' designs and gate utilization requirements. For the most part the choice of a package as the primary heat removal casing works well. Pd The total device power dissipation -- expressed in watts. Junction-to-Reference General Setup Occasionally designers exercise an FPGA device, particularly the high gate count variety, beyond "typical" designs. The use of the primary package without enhancement may not adequately address the device's heat removal needs. Heat removal management through external means or an alternative enhanced package should be considered. Removing heat ensures the functional and maximum design temperature limits are maintained. The device may go outside the temperature limits if heat build up becomes excessive. As a consequence, the device may fail to meet electrical performance specifications. It is also necessary to satisfy reliability objectives by operating at a lower temperature. Failure mechanisms and the failure rate of devices depend on device operating temperature. Control of the package and the device temperature ensures product reliability. Package Thermal Characterization Methods & Conditions Method and Calibration Xilinx uses the indirect electrical method for package thermal resistance characterization. The forward-voltage drop of an isolated diode residing on a special test die is calibrated at constant forcing current of 0.520mA with respect to temperature over a correlation temperature range of 22C to 125C (degree Celsius). The calibrated device is then mounted in an appropriate environment (still air, forced convection, circulating FC-40, etc.) Depending on the package, between 0.5 to 4 watts of power (Pd) is applied. Power (Pd) is applied to the device through diffused resistors on the same thermal die. The resulting rise 11-6 Figure 1: Thermal Measurement Set-Up (Schematic for Junction to Reference) Junction-to-Case Measurement -- JC JC is measured in a 3M Flourinert (FC-40) isothermal circulating fluid stabilized at 25C. The Device Under Test (DUT) is completely immersed in the fluid and initial stable conditions are recorded. Pd is then applied. Case temperature (TC) is measured at the primary heat-flow path of the particular package. Junction temperature (TJ) is calculated from the diode forward-voltage drop from the initial stable condition before power was applied. JC = (TJ - TC)/Pd The junction-to-isothermal-fluid measurement (JI) is also calculated from the same data. JL = (TJ - TI)/Pd June 1, 1996 (Version 1.0) The latter data is considered as the ideal JA data for the package that can be obtained with the most efficient heat removal scheme. Other schemes such as airflow, heatsinks, use of copper clad board, or some combination of all these will tend towards this ideal figure. Since this is not a widely used parameter in the industry, and it is not very realistic for normal application of Xilinx packages, the JI data is not published. The thermal lab keeps such data for package comparisons. junction to ambient thermal resistance is calculated as follows: JA = (TJ - TA)/Pd Junction-to-Ambient Measurement -- JA The setup described herein lends itself to the application of various airflow velocities from 0 - 800 Linear Feet per Minute (LFM), i.e., 0 - 4.06 m/s. Since the board selection (copper trace density, absence or presence of ground planes, etc.) affects the results of the thermal resistance, the data from these tests shall always be qualified with the board mounting information. JA is measured on FR4 based PC boards measuring 4.5" x 6.0" x .0625" (114.3mm x 152.4mm x 1.6mm) with edge connectors. There are two main board types. Data Acquisition and Package Thermal Database Type I, 2L/0P board, is single layer with 2 signal planes (one on each surface) and no internal Power/GND planes. The trace density on this board is less than 10% per side. Type II, the 4L/2P board, has 2 internal copper planes (one power, one ground) and 2 signal trace layers on both surfaces. Data may be taken with the package mounted in a socket or with the package mounted directly on the board. Socket measurements typically use the 2L/0P boards. SMT devices may use either board. Published data always reflects the board and mount conditions used. Data is taken at the prevailing temperature and pressure conditions (22C to 25C ambient). The board with the DUT is mounted in a cylindrical enclosure. The power application and signal monitoring are the same as JC measurements. The enclosure (ambient) thermocouple is substituted for the fluid thermocouple and two extra thermocouples brought in to monitor room and board temperatures. The June 1, 1996 (Version 1.0) Xilinx gathers data for a package type in die sizes, power levels and cooling modes (air flow and sometimes heatsink effects) with a Data Acquisition and Control system (DAS). The DAS controls the power supplies and other ancillary equipment for hands-free data taking. Different setups within the DAS software are used to run calibration, JA, JC, fan tests, as well as the power effect characteristics of a package. A package is characterized with respect to the major variables that influence the thermal resistance. The results are stored in a database. Thermal resistance data is interpolated as typical values for the individual Xilinx devices that are assembled in the characterized package. Table 1 shows the typical values for different packages. Specific device data may not be the same as the typical data. However, the data will fall within the given minimum and maximum ranges. The more widely used packages will have a wider range. Customers may contact the Xilinx application group for specific device data. 11-7 Packages and Thermal Characteristics Table 2: Summary of Thermal Resistance for Packages PKG-CODE BG225 CB100 CB164 CB196 CB228 CQ100 DD8 HQ208 HQ240 HQ304 MQ208 MQ240 PC20 PC44 PC68 PC84 PD48 PD8 PG120 PG132 PG144 PG156 PG175 PG191 PG223 PG299 PG411 PG68 PG84 PP132 PP175 PQ100 PQ160 PQ208 PQ240 PQ44 SO8 TQ100 TQ144 TQ176 VO8 VQ100 VQ44 VQ64 11-8 JA at 07 (Max) C/Watt 37 44 29 25 19 46 114 15 13 11 18 17 86 51 46 41 43 82 32 32 26 25 25 24 24 18 16 39 37 35 29 35 37 35 28 52 147 37 35 29 162 47 44 44 JA at 07 (Typ) C/Watt 30 41 26 24 18 45 109 14 12 11 18 17 84 46 42 33 43 79 27 28 25 23 23 21 20 17 15 37 34 34 29 33 32 32 23 51 147 31 32 28 162 38 44 41 JA at 07 (Min) C/Watt 24 38 25 24 17 44 97 14 12 10 17 16 76 42 38 28 43 73 25 24 23 21 20 18 18 16 14 34 31 33 28 32 22 26 19 51 147 31 30 27 162 32 44 39 JA at 2506 JA at 5006 JA at 7506 (Typ) (Typ) (Typ) C/Watt C/Watt C/Watt 19 17 16 25 19 17 17 12 11 15 11 10 11 8 7 37 30 25 90 73 60 10 8 7 9 7 6 7 5 5 14 13 12 12 11 10 63 56 53 35 31 29 31 28 26 25 21 17 33 29 27 60 54 50 19 15 13 20 17 15 17 14 13 15 11 10 14 11 10 15 12 11 15 12 11 10 9 8 9 8 7 26 20 17 24 18 16 23 18 17 19 15 13 29 28 27 24 21 20 23 21 19 17 15 14 40 36 35 112 105 98 26 24 23 25 21 20 21 18 17 123 116 108 32 30 29 36 34 33 34 32 31 JC (Typ) C/Watt 3.3 5.1 3.6 1.8 1.3 7.1 8.2 1.7 1.5 0.9 1.2 1.2 25.8 13.7 9.3 5.3 11.6 22.2 3.6 2.8 3.7 2.6 2.6 1.5 1.5 1.9 1.2 7.8 5.8 6.0 2.5 5.5 4.6 4.3 2.8 12.4 48.3 7.5 5.3 5.3 48.3 9.0 8.2 8.2 Comments Various Socketed Socketed Socketed Socketed Socketed Socketed 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Socketed Estimated Socketed Socketed Socketed Socketed 4L/2P-SMT 2L/0P-SMT 2L/0P-SMT 2L/0P-SMT 4L/2P-SMT IEEE-(Ref) 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT Estimated 4L/2P-SMT 4L/2P-SMT 4L/2P-SMT June 1, 1996 (Version 1.0) Table 2: Summary of Thermal Resistance for Packages (Continued) PKG-CODE WB144 WB225 WC44 WC68 WC84 JA at 07 (Max) C/Watt 28 28 47 46 43 JA at 07 (Typ) C/Watt 28 28 46 43 41 JA at 07 (Min) C/Watt 28 28 45 40 38 JA at 2506 JA at 5006 JA at 7506 (Typ) (Typ) (Typ) C/Watt C/Watt C/Watt -- -- -- -- -- -- 38 31 25 31 26 23 29 24 21 JC (Typ) C/Watt 6.0 6.0 9.1 7.0 3.9 Comments 2L/0P-SMT 2L/0P-SMT Socketed Socketed Socketed Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time of compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data in a package may be obtained from the factory. 2. Package configurations and drawings are in the package section of the data book. 3. 2L/0P - SMT: the data is from a surface mount type I board -- no internal planes on the board. 4. 4L/2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket. 5. Thermal data is in degree Celsius/watt. 6. Airflow is reported in Linear Feet per minute (LFM). 7. Columns 1, 2 and 3 are for JA in still air. Application of Thermal Resistance Data Thermal resistance data gauges the IC package thermal performance. JC measures the internal package resistance to heat conduction from the die surface, through the die mount material to the package exterior. JC strongly depends on the package's heat conductivity, architecture and geometrical considerations. also needs to be established for the system. The following inequality will hold. JA measures the total package thermal resistance including JC. JA depends on the package material properties and such external conditions as convective efficiency and board mount conditions. For example, a package mounted on a socket may have a JA value 20% higher than the same package mounted on a 4 layer board with power and ground planes. Example 1: By specifying a few constraints, devices are ensured to operate within the intended temperature range. This also ensures device reliability and functionality. The system ambient temperature needs to be specified. A maximum TJ June 1, 1996 (Version 1.0) TJ(max) > JA* Pd +TA The following two examples illustrates the use of this inequality. The manufacturer's goal is TJ (max) < 100C A module is designed for a TA = 45C max. A XC3042 in a PLCC 84 has a JA = 32C/watt. Given a XC3042 with a logic design with a rated power Pd of 0.75watt. With this information, the maximum die temperature can be calculated as: TJ = 45 + (32 x .75) ==> 69C. The system manufacturer's goal of TJ < 100C is met. 11-9 Packages and Thermal Characteristics Example 2: power of 2.50 watts. The module manufacturers goal is TJ(max.) < 100C. Table 3 shows the package and thermal enhancement combinations required to meet the goal of TJ < 100C. A module has a TA = 55C max. The Xilinx XC4013E is in a PQ240 package (HQ240 is also considered). A XC4013E, in an example logic design, has a rated Table 3: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages Dev Name XC4013E XC4013E Package PQ240 HQ240 JA still air 23.7 12.5 JA (250 LFM) 17.5 8.6 JA JA JC (500 LFM) (750 LFM) 15.4 14.3 2.7 6.9 6.2 1.5 Comments Cu, SMT 2L/0P 4 Layer Board data Possible Solutions to meet the module requirements of 100C: 1a. 1b. 2a. 2b. Using the standard PQ240; Using standard PQ240 with 250LFM forced air Using standard HQ240 Using HQ240 with 250 LFM forced air For all solutions, the junction temperature is calculated as: TJ = Power x JA + TA All solutions meet the module requirement of less than 100C, with the exception of the PQ240 package in still air. 11-10 TJ = 55 + (23.7 x 2.50) ==> 114.25 C. TJ = 55 + (17.5 x 2.50) ==> 98.75 C TJ = 55 + (12.5 x 2.50) ==> 86.25 C TJ = 55 + (8.6 x 2.50) ==> 76.5 C In general, depending on ambient and board temperatures conditions, and most importantly the total power dissipation, thermal enhancements -- such as forced air cooling, heat sinking, etc. may be necessary to meet the TJ(max) conditions set. June 1, 1996 (Version 1.0) PQ/HQ Thermal Data Comparison HQ/PQ Thermal Data Size effect on JA 35 30 JA (C/watt) 25 HQ208 20 HQ240 15 HQ304 PQ208 10 PQ240 5 200 300 400 500 600 700 Die size (mils) HQ/PQ Thermal Data Effect of Forced Air on JA 30 JA (C/watt) 25 20 15 10 5 0 0 200 400 600 800 Airflow - LFM XC4010E-HQ208 XC4010E-PQ208 June 1, 1996 (Version 1.0) XC4013E-HQ240 XC4013E-PQ240 XC4025E-HQ304 11-11 Packages and Thermal Characteristics BGA Thermal Resistance Effect of Air Flow on JA 40 35 JA (C/watt) 30 25 20 15 10 0 200 400 Air Flow - LFM 600 XC4010E-BG225 (2L) XC4013E-BG225(4L) XC73108-BG225(2L) XC5210-BG225(2L) 800 XC73144-BG225(4L) PG299 Thermal Resistance Effects of Active & Passive Heat sinks 20 JA (C/watt) 15 10 5 0 A B C D E F PG299 - Various Enhancements A Standard Pkg B Pkg+Finned HS (Passive) C Pkg+Active Fan (V=0) 11-12 D Pkg+Active Fan (V=12) E Std Pkg +250LFM F Pkg+Finned HS+ 250LFM June 1, 1996 (Version 1.0) PGA 299 Thermal Resistance Effect of Air Flow on JA 25 JA (C/watt) 20 15 10 5 0 0 100 200 300 400 500 600 700 Air Flow - LFM June 1, 1996 (Version 1.0) PG191-XC4010E PG223-XC4013E PG299-XC4025E PG299-FHS(XC4025E) 11-13 Packages and Thermal Characteristics Some Power Management Options FPGA devices are usually not the dominating power consumers in a system, and do not have a big impact on power supply designs. There are obvious exceptions. When the actual or estimated power dissipation appears to be more than the specification of the chosen package, some options can be considered. Details on the engineering designs and analysis of some of these suggested considerations may be obtained from the references listed at the end of the section. The options include: * * * * * A Xilinx low power (L) version of the circuit in the same package. With the product and speed grade of choice, up to a 40% power reduction can be anticipated. For more information, contact the Xilinx Hotline group. Explore thermally enhanced package options available for the same device. As illustrated above, the HQ240 package has a thermal impedance of about 50% of the equivalent PQ240. Besides, the 240 lead, the 208 lead and the 304 lead Quad packages have equivalent heatsink enhanced versions. Typically 25% to 40% improvement in thermal performance can be expected from these heatsink enhanced packages. Most of the high gate count devices above the XC4013 level come either exclusively in heat enhanced packages or have these packages as options. If the use of a standard PQ appears to be a handicap in this respect, a move to the equivalent HQ package if available may resolve the issue. The heat enhanced packages are pin to pin compatible and they use the same board layout. The use of forced air is an effective way to improve thermal performance. As seen on the graphs and the calculations above, forced air (200 -- 300 LFM) can reduce junction to ambient thermal resistance by 30%. If space will allow, the use of finned external heatsinks can be effective. If implemented with forced air as well, the benefit can be a 40% to 50% reduction. The HQ304, all cavity down PGAs, and the BG352 with exposed heatsink lend themselves to the application of external heatsinks for further heat removal efficiency. Outside the package itself, the board on which the package sits can have a significant impact. Board designs may be implemented to take advantage of this. 11-14 Heat flows to the outside of a board mounted package and is sunk into the board to radiate. The effect of the board will be dependent on the size and how it conducts heat. Board size, the level of copper traces on it, the number of buried copper planes all lower the junction-to-ambient thermal resistance for a package. Some of the heatsink packages with the exposed heatsink on the board side can be glued to the board with thermal compound to enhance heat removal. References Forced Air Cooling Application Engineering COMAIR ROTRON 2675 Custom House Court San Ysidro, CA 92173 1-619-661-6688 Heatsink Application Engineering The following facilities provide heatsink solutions for industry standard packages. AAVID Thermal Technologies 1 Kool Path Box 400 Laconia, NH 03247-0400 1-603-528-3400 Thermalloy, Inc. 2021 W. Valley View Lane Box 810839 Dallas, TX 75381-0839 1-214-243-4321 Wakefield Engineering, Inc. 60 Audubon Road Wakefield MA 01880-1255 1-617-245-5900 Xilinx does not endorse these vendors nor their products. They are listed here for reference only. Any materials or services received from the vendors should be evaluated for compatibility with Xilinx components. June 1, 1996 (Version 1.0) Component Mass (Weight) by Package Type Package BG225 BG352 BG432 CB100 CB100 CB164 CB164 CB196 CB228 CC20 DD8 HQ208 HQ240 HQ304 MQ208 MQ240 PC20 PC28 PC44 PC68 PC84 PD48 PD8 PG120 PG132 PG144 PG156 PG175 PG184 PG191 PG223 PG299 PG299 PG411 PG68 PG84 PP132 PP175 PQ100 PQ160 PQ208 PQ240 PQ44 SO8 TQ100 Description MOLDED BGA 27mm- ANAM SUPERBGA - 35X35MM AMKOR SUPERBGA - 40X40MM AMKOR NCTB TOP BRAZE 3K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 3K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 4K VER NCTB TOP BRAZE 4K VER CERAMIC LEADED CHIP CARRIER .300 CERDIP PACKAGE METRIC 28 X 28 - H/S DIE UP METRIC QFP 32 32 - H/S DIE UP METRIC QFP 40 40-H/S DIE DOWN METAL QUAD EIAJ METAL QUAD PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 DIP .600 DIP .300 STANDARD CERAMIC PGA 13 X 13 MATRIX CERAMIC PGA 14 X 14 MATRIX CERAMIC PGA 15 X15 CAVITY UP CERAMIC PGA 16 X 16 MATRIX CERAMIC PGA 16X16 STD VER. CERAMIC PGA 15 X15 CAVITY UP CERAMIC PGA 18 X 18 STD - ALL CERAMIC PGA 18 X 18 TYPE CERAMIC PGA 20 X 20 HEATSINK CERAMIC PGA 20 X 20 TYPE CERAMIC PGA 39 X 39 STAGGER CERAMIC PGA CAV UP 11X11 CERAMIC PGA CAV UP 11X11 PLASTIC PGA 14 X 14 MATRIX PLASTIC PGA 16X16 BURRIED EIAJ 14X20 QFP - 1.60 EIAJ 28X28 .65MM 1.60 EIAJ 28X28 .5MM 1.30 EIAJ 32 X 32 .5MM EIAJ 10 X 10 X 2.0 VERSION 1 - .150/55MIL THIN QFP 1.4mm thick June 1, 1996 (Version 1.0) JEDEC Outline # MO-151-CAL MO-151-BAR MO-151-BAU MO-113 MO-113 MO-113-AA MO-113-AA MO-113-AB MO-113 N/A MO-036-AA MO-143-FA1 MO-143-GA MO-143-JA N/A N/A MO-047-AA MO-047-AB MO-047-AC MO-047-AE MO-047-AF N/A MO-001-AA MO-067-AE MO-067-AF MO-067-AG MO-067-AH MO-067-AH MO-067-AG MO-067-AK MO-067-AK MO-067-AK MO-067-AM MO-128-AM MO-067-AC MO-067-AC MO-83-AF MO-83-AH MO-108-CC1 MO-108-DD1 MO-143-FAI MO-143-GA MO-108-AA2 MO-150 MS-026-BDE Xilinx # OBG0001 OBG0008 OBG0009 OCQ0008 OCQ0006 OCQ0003 OCQ0007 OCQ0005 OCQ0012 OCQ0011 OPD0005 OPQ0020 OPQ0019 OPQ0014 OPQ0006 OPQ0011 OPC0006 OPC0001 OPC0005 OPC0001 OPC0001 OPD0001 OPD0002 OPG0012 OPG0004 OPG0017 OPG0007 OPG0009 OPG0019 OPG0008 OPG0016 OPG0022 OPG0015 OPG0019 OPG0002 OPG0003 OPG0001 OPG0006 OPQ0013 OPQ0002 OPQ0003 OPQ0010 OPQ0015 OPD0006 OPQ0004 Mass (g) 2.2 7.1 9.1 10.8 10.8 11.5 11.5 15.3 17.6 8.4 1.1 10.8 15.0 26.2 6.1 8.0 0.8 1.1 1.2 4.8 6.8 7.9 0.5 11.5 11.8 16.9 17.1 17.7 17.5 21.8 26.0 37.5 29.8 36.7 7.0 7.2 8.1 11.1 1.6 5.8 5.3 7.1 0.5 0.1 0.7 11-15 Packages and Thermal Characteristics Component Mass (Weight) by Package Type (Continued) Package TQ144 TQ176 VO8 VQ100 VQ44 VQ64 WC44 WC68 WC84 Description THIN QFP 1.4mm thick THIN QFP 1.4mm thick THIN SOIC-II THIN QFP 1.0 thick EIAJ 10 X 10 X 1.0 THIN QFP 1.0 thick JEDEC WINDOWED CQUAD WINDOWED CERQUAD WINDOWED CERQUAD JEDEC Outline # MS-026-BFB MS-026-BGA N/A MS-026-AED MS-026-ACB MS-026-ACD MO-087 MO-087 MO-087 Xilinx # OPQ0007 OPQ0008 OPD0007 OPQ0012 OPQ0017 OPQ0009 OCQ0004 OCQ0009 OCQ0010 Mass (g) 1.4 0.9 0.1 0.6 0.4 0.5 2.9 7.3 11.0 Notes: 1. Data represents average values for typical packages with typical devices. The accuracy is between 7% to 10%. 2. More precise numbers (below 5% accuracy) for specific devices may be obtained from Xilinx through a factory representative or by calling the Xilinx Hotline. 11-16 June 1, 1996 (Version 1.0) Xilinx Thermally Enhanced Packaging The Package Offering Xilinx Code Body (mm) THK (mm) Mass (gm) HQ304 HQ240 HQ208 40x40 32x32 28x28 3.80 3.40 3.37 26.2 15.0 10.0 Heatsink Location TOP DOWN DOWN JEDEC No. Xilinx No. MO-143-JA MO-143-GA MO-143-FA OPQ0014 OPQ0019 OPQ0020 Overview Mass Comparison Xilinx offers thermally enhanced quad flat pack packages on certain devices. This section discusses the performance and usage of these packages (designated HQ). In summary: Because of the copper heatsink, the HQ series of packages are about twice as heavy as the equivalent PQ. Here is a quick comparison. * * * * The HQ-series and the regular PQ packages conform to the same JEDEC drawings. The HQ and PQ packages use the same PCB land patterns. The HQ packages have more mass Thermal performance is better for the HQ packages - - HQ packages are offered as the thermally enhanced equivalents of PQ packages. They are used for high gate count or high l/O count devices in packages, where heat dissipation without the enhancement may be a handicap for device performance. Such devices include XC4013E, XC4020E, XC4025E, and XC5215. They are also being used in place of MQUAD (MQ) packages of the same lead count for new devices. The HQ series at the 240 pin count level or below are offered with the heatsink at the bottom of the package. This was done to ensure pin to pin compatibility with the existing PQ and MQ packages. At the 304 pin count level, the HQ is offered with the heatsink up. This arrangement offers a better potential for further thermal enhancement by the designer. A PQ (gm) 5.3 7.1 N/A MQ (gm) 6.1 8.0 N/A HQ (gm) 10.0 15.0 26.2 Thermal Data for the HQ The data for individual devices may be obtained from Xilinx. Where and When Offered - 208 Pin 240 Pin 304 Pin Die Up/Heatsink Down Still Air Data Comparison HQ MQ PQ JA (C/Watt) JA (C/watt) JA (C/watt) 208 Pin 240 Pin 304 Pin Note: 10-14 11-14 10-12 17-19 15-17 N/A 25-32 18-28 N/A JC is typically between 1 and 2 C/Watt for HQ and MQ Packages. For PQ's, it is between 2 and 7 C/Watt. Data Comparison at Airflow - 250 LFM HQ MQ PQ JA (C/watt) JA (C/watt) JA (C/watt) 208 Pin 240 Pin 304 Pin 9-10 8-9 6.5-8 14-15 11-13 N/A 19-25 14-20 N/A Other Information - B Die Down/Heatsink Up A - Heatsink down orientation B - Heatsink up orientation June 1, 1996 (Version 1.0) X5962 - Leadframe: Copper EFTEC-64 or C7025 Heat Slug: Copper - Nickel plated Heatsink metal is Grounded Lead Finish 85/15 Sn/Pb 300 microinches minimum D/A material - Same as PQ; Epoxy 84-1LMISR4 Mold Cpd. Same as PQ - EME7304LC Packed in the same JEDEC trays 11-17 Packages and Thermal Characteristics Moisture Sensitivity of PSMCs Moisture Induced Cracking During Solder Reflow The surface mount reflow processing step subjects the Plastic Surface Mount Components (PSMC) to high thermal exposure and chemicals from solder fluxes and cleaning fluids during user's board mount assembly. The plastic mold compounds used for device encapsulation are, universally, hygroscopic and absorb moisture at a level determined by storage environment and other factors. Entrapped moisture can vaporize during rapid heating in the solder reflow process generating internal hydrostatic pressure. Additional stress is added due to thermal mismatch, and the Thermal Coefficient of Expansion (TCE) of plastic, metal lead frame, and silicon die. The resultant pressure may be sufficient to cause delamination within the package, or worse, an internal or external crack in the plastic package. Cracks in the plastic package can allow high moisture penetration, inducing transport of ionic contaminants to the die surface and increasing the potential for early device failure. How the effects of moisture in plastic packages and the critical moisture content result in package damage or failure is a complex function of several variables. Among them are package construction details -- materials, design, geometry, die size, encapsulant thickness, encapsulant properties, TCE, and the amount of moisture absorbed. The PSMC moisture sensitivity has, in addition to package cracking, been identified as a contributor to delaminationrelated package failure artifacts. These package failure artifacts include bond lifting and breaking, wire neckdown, bond cratering, die passivation, and metal breakage. Because of the importance of the PSMC moisture sensitivity, both device suppliers and device users have ownership and responsibility. The background for present conditions, moisture sensitivity standardized test and handling proce- 11-18 dures have been published by two national organizations. Users and suppliers are urged to obtain copies of both documents (listed below) and use them rigorously. Xilinx adheres to both. * JEDEC STANDARD JESD22-A112. Test Method A112 "Moisture-Induced Stress Sensitivity for Plastic Surface Mounted Devices". Available through Global Engineering Documents Phone: USA and Canada 800-854-7179, International 1-303-792-2181 * IPC Standard IPC-SM-786A "Procedures for Characterizing and Handling of Moisture/Reflow Sensitive ICs". Available through IPC Phone: 1-708-677-2850 None of the previously stated or following recommendations apply to parts in a socketed application. For board mounted parts careful handling by the supplier and the user is vital. Each of the above publications has addressed the sensitivity issue and has established 6 levels of sensitivity (based on the variables identified). A replication of those listings, including the preconditioning and test requirements, and the factory floor life conditions for each level are outlined in Table 4. Xilinx devices are characterized to their proper level as listed. This information is conveyed to the user via special labeling on the Moisture Barrier Bag (MBB). In Table 4, the level number is entered on the MBB prior to shipment. This establishes the user's factory floor life conditions as listed in the time column. The soak requirement is the test limit used by Xilinx to determine the level number. This time includes manufacturer's exposure time or the time it will take for Xilinx to bag the product after baking. June 1, 1996 (Version 1.0) Table 4: Package Moisture Sensitivity Levels per JEDEC A112 Level 1 2 3 4 5 6 Notes: Factory Floor Life Conditions Time 30C / 90% Unlimited RH 30C / 60% 1 year RH 30C / 60% RH 30C / 60% RH 30C / 60% RH 30C / 60% RH Soak Requirements (Preconditioning) Time Conditions 168 hours 85C / 85% RH 168 hours 85C / 60% RH 168 hours X + 24 Time (hours) Y = 168 Z 192 30C / 60% RH 72 hours 12 72 84 30C / 60% RH 24 hours 6 24 30 30C / 60% RH 6 hours 0 6 6 30C / 60% RH X = Default value of semiconductor manufacturer's time between bake and bag. If the semiconductor manufacturer's actual time between bake and bag is different from the default value, use the actual time. Y = Floor life of package after it is removed from dry pack bag. Z = Total soak time for evaluation. Factory Floor Life Factory floor life conditions for Xilinx devices are clearly stated on MBB containing moisture sensitive PSMCs. These conditions have been ascertained by following Test Methods outlined in JEDEC JESD22-A112 and are replicated in Table 4. If factory floor conditions are outside the stated environmental conditions (85C/85% RH for level 1, and 30C/60% RH for Levels 2-6) or if time limits have been exceeded, then recovery can be achieved by baking the devices before the reflow step. Identified in the next section are two acceptable bake schedules. Either can be used for recovery to the required factory floor level. Dry Bake Recommendation and Dry Bag Policy Xilinx recommends, as do the mentioned publications and other industry studies, that all moisture sensitive PSMCs be baked prior to use in surface mount applications, or comply strictly with requirements as specified on the MBB. Tape and Reeled parts are universally dry packed. Level 1 parts are shipped without the need for, or use of, an MBB. Two bake schedules have been identified as acceptable and equivalent. The first is 24 hours in air at 125C., in shipping media capable of handling that temperature. The second bake schedule is for 192 hours in a controlled atmosphere of 40C, equal to or less than 5% RH. Dry Devices are sealed in special military specification Moisture Barrier Bags (MBB). Enough desiccant pouches June 1, 1996 (Version 1.0) are enclosed in the MBB to maintain contents at less than 20% RH for up to 12 months from the date of seal. A reversible Humidity Indicator Card (HIC) is enclosed to monitor the internal humidity level. The loaded bag is then sealed shut under a partial vacuum with an impulse heat sealer. Artwork on the bags provides storage, handling and use information. There are areas to mark the seal date, quantity, and moisture sensitivity level and other information. The following paragraphs contain additional information on handling PSMCs. Handling Parts in Sealed Bags Inspection Note the seal date and all other printed or hand entered notations. Review the content information against what was ordered. Thoroughly inspect for holes, tears, or punctures that may expose contents. Xilinx strongly recommends that the MBB remain closed until it reaches the actual work station where the parts will be removed from the factory shipping form. Storage The sealed MBB should be stored, unopened, in an environment of not more than 90% RH and 40C. The enclosed HIC is the only verification to show if the parts have been exposed to moisture. Nothing in part appearance can verify moisture levels. 11-19 Packages and Thermal Characteristics Expiration Date Other Conditions The seal date is indicated on the MBB. The expiration date is 12 months from the seal date. If the expiration date has been exceeded or HIC shows exposure beyond 20% upon opening the bag bake the devices per the earlier stated bake schedules. The three following options apply after baking: Open the MBB when parts are to be used. Open the bag by cutting across the top as close to the seal as possible. This provides room for possible resealing and adhering to the reseal conditions outlined above. After opening, strictly adhere to factory floor life conditions to ensure that devices are maintained below critical moisture levels. Use the devices within time limits stated on the MBB. Reseal the parts completely under a partial vacuum with an impulse sealer (hot bar sealer) in an approved MBB within 12 hours, using fresh desiccant and HIC, and label accordingly. Partial closures using staples, plastic tape, or cloth tape are unacceptable. Bags opened for less than one hour (strongly dependent on environment) may be resealed with the original desiccant. If the bag is not resealed immediately, new desiccant or the old one that has been dried out may be used to reseal, if the factory floor life has not been exceeded. Note that factory floor life is cumulative. Any period of time when MBB is opened must be added to all other opened periods. Store the out-of-bag devices in a controlled atmosphere at less than 20% RH. A desiccator cabinet with controlled dry air or dry nitrogen is ideal. Both the desiccant pouches and the HIC are reversible. Restoration to dry condition is accomplished by baking at 125C for 10-16 hours, depending on oven loading conditions. 11-20 June 1, 1996 (Version 1.0) Tape and Reel Xilinx offers a tape & reel packing for PLCC, BGA, QFP, and SO packages. The packing material is made of black conductive Polystyrene and protects the packages from mechanical and electrical damage. The reel material provides a suitable medium for pick and place equipment. The tape & reel packaging consists of a pocketed carrier tape, sealed with a protective cover. The device sits on pedestals (for PLCC, QFP packages) to protect the leads from mechanical damage. All devices loaded into the tape carriers are baked, lead scanned before the cover tape is attached and sealed to the carrier. In-line mark inspection for mark quality and package orientation is used to ensure shipping quality. Benefits * * * * * * * * * Increased quantity of devices per reel versus tubes improves cycle time and reduces the amount of time to index spent tubes. Tape & reel packaging enables automated pick and place board assembly. Reels are uniform in size enabling equipment flexibility. Transparent cover tape allows device verification and orientation. Anti-static reel materials provides ESD protection. Carrier design include a pedestal to protect package leads during shipment. Bar code labels on each reel facilitate automated inventory control and component traceability. All tape & reel shipments include desiccant pouches and humidity indicators to insure products are safe from moisture. Compliant to Electronic Industries Association (EIA) 481. Material and Construction Carrier Tape * * The pocketed carrier Tape is made of conductive polystyrene material, or equivalent, with a surface resistivity level of less than 106 ohms per square inch. Devices are loaded `live bug' or leads down, into a device pocket. June 1, 1996 (Version 1.0) * * Each carrier pocket has a hole in the center for automated sensing of whether a unit is in the pocket or not. Sprocket holes along the edge of the carrier tape enable direct feeding into an automated board assembly equipment. Cover Tape * * An anti-static, transparent, polyester cover tape, with heat activated adhesive coating, sealed to the carrier edges to hold the devices in the carrier pockets. Surface resistivity on both sides is less than 1011 ohms per square inch. Reel * * * * The reel is made of anti-static Polystyrene material. The loaded carrier tape is wound onto this conductive plastic reel. A protective strip made of conductive Polystyrene material is placed on the outer part of the reel to protect the devices from external pressure in shipment. Surface resistivity is less than 1011 ohms per square inch. Device loading orientation is in compliance with EIA Standard 481. Bar Code Label * * * * The bar code label on each reel provides customer identification, device part number, date code of the product and quantity in the reel. Print quality are in accordance with ANSI X3.182-1990 Bar Code Print Quality Guidelines. Presentation of Data on labels are EIA-556-A compliant. The label is an alphanumeric, medium density Code 39 labels. This machine-readable label enhances inventory management and data input accuracy. Shipping Box * The shipping container for the reels are in a 13" x 13" x 3" C-flute, corrugated, # 3 white `pizza' box, rated to 200 lb test. 11-21 Packages and Thermal Characteristics l Table 5: Tape & Reel Packaging Package Type PLCC (Plastic Leaded Chip Carrier) SO (Plastic Small Outline) QFP (Plastic Quad Flat Pack) BGA (Plastic Ball Grid Array) Notes: Pin Count 20 20 44 68 84 8 100 160 225 Carrier Width 16 mm 16 mm 32 mm 44 mm 44 mm 12 mm 44 mm 44 mm 44 mm Cover Width 13.3 mm 13.3 mm 25.5 mm 37.5 mm 37.5 mm 9.2 mm 37.5 mm 37.5 mm 37.5 mm Pitch 12 mm 12 mm 24 mm 32 mm 36 mm 8 mm 32 mm 40 mm 32 mm Reel Size 7 inch 13 inch 13 inch 13 inch 13 inch 7 inch 13 inch 13 inch 13 inch Qty per Reel 250 750 500 250 250 750 250 200 500 1.A minimum of 230mm of empty pockets are provided at the beginning (leader) of each reel. 2.A minimum of 160mm of empty pockets are provided at the end (trailer) of each reel. 3.Tape Leader/Trailer requirements are in compliance to EIA Standards 481. 4.Peel Strength between 20 and 120 grams ensures consistency during de-reeling operations and is compliant to EIA Standard 481. 5.Each reel is subject to peel back strength tests. 6.For packages not listed above, please contact your Xilinx sales representative for updated information. Standard Bar Code Label Locations 11-22 June 1, 1996 (Version 1.0) Reflow Soldering Process Guidelines In order to implement and control the production of surface mount assemblies, the dynamics of the solder reflow process, and how each element of the process is related to the end result, must be thoroughly understood. The primary phases of the reflow process are as follows: 1. Melting the particles in the solder paste 2. Wetting the surfaces to be joined 3. Solidifying the solder into a strong metallurgical bond Each phase of a surface mount reflow profile has min/max limits that should be viewed as a process window. The process requires a careful selection and control of the materials, geometries of the mating surfaces (package footprint vs. PCB land pattern geometries) and the time temperature of the profile. If all of the factors of the process are sufficiently optimized, there will be good solder wetting and fillet formation (between component leads and the land patterns on the substrate). If factors are not matched and optimized there can be potential problems as summarized in Figure 3. The sequence of five actions that occur during this process is shown in Figure 2. Potential Reflow Soldering Issues 6 Temperature Reflow Soldering Phases Time Figure 2: June 1, 1996 (Version 1.0) 5 2 3 1 Cool Down Phase Solder Melting Completes, Surface Tension Takes Over 50 Flux Reduces Metal Oxides 100 Solder Balls Melt, Wetting and Wicking Begin 150 Solvent Evaporation Temperature (C) 200 4 Time X5975 1. Insufficient Temperature to Evaporate Solvent 2. Component Shock and Solder Splatter 3. Insufficient Flux Activation 4. Excessive Flux Activity and Oxidation 5. Trapping of Solvent and Flux, Void Formation 6. Component and/or Board Damage X5976 Figure 3: 11-23 Packages and Thermal Characteristics T-Max (leads) 220 - 235C Temperature C 2 - 4C/s 215 - 219C 45 s max 2 Ramp down 2 - 4C/s Temperature C Figure 4 and Figure 5 show typical conditions for solder reflow processing using Vapor Phase or IR Reflow. The moisture sensitivity of Plastic Surface Mount Components (PSMCs) must be verified prior to surface mount flow. See the preceding sections for a more complete discussion on PSMC moisture sensitivity. t183 Dwell = 30 - 60 s Preheat & drying dwell 3 120 s min between 95 - 180C 2 Ramp down 2 - 4C/s Temp = 183C Time (s) t183 Preheat & drying dwell 120 - 180 s between 95 - 180C 3 60s < t183 < 120s applies to lead area 2 Time (s) X5973 Figure 4: Typical conditions for IR reflow soldering Notes: 1. Max temperature range = 220C-235C (leads) Time at temp 30-60 seconds 2. Preheat drying transition rate 2-4C/s 3. Preheat dwell 95-180C for 120-180 seconds 4. IR reflow shall be performed on dry packages X5974 Figure 5: Typical conditions for vapor phase reflow soldering Notes: 1. Solvent - FC5312 or equivalent - ensures temperature range of leads @ 215-219C 2. Transition rate 4-5C/s 3. Dwell is intended for partial dryout and reduces the difference in temperature between leads and PCB land patterns. 4. These guidelines are for reference. They are based on laboratory runs using dry packages. It is recommended that actual packages with known loads be checked with the commercial equipment prior to mass production. The IR process is strongly dependent on equipment and loading differences. Components may overheat due to lack of thermal constraints. Unbalanced loading may lead to significant temperature variation on the board. This guideline is intended to assist users in avoiding damage to the components; the actual profile should be determined by the users using these guidelines. 11-24 June 1, 1996 (Version 1.0) Sockets Table 6 lists manufacturers known to offer sockets for Xilinx Package types. This summary does not imply an endorse- ment by Xilinx. Each user has the responsibility to evaluate and approve a particular socket manufacturer. Table 6: Socket Manufacturers Manufacturer AMP Inc. 470 Friendship Road Harrisburg, PA 17105-3608 (800) 522-6752 Augat Inc. 452 John Dietsch Blvd. P.O. Box 2510 Attleboro Falls, MA 02763-2510 (508) 699-7646 McKenzie Socket Division 910 Page Avenue Fremont, CA 94538 (510) 651-2700 3M Textool 6801 River Place Blvd. Austin, TX 78726-9000 (800) 328-0411 (612) 736-7167 Wells Electronics 1701 South Main Street South Bend, IN 46613-2299 (219) 287-5941 Yamaichi Electronics Inc. 2235 Zanker Road San Jose, CA 95131 (408) 456-0797 June 1, 1996 (Version 1.0) Packages PQ HQ TQ PG VQ PP DIP SO VO PC WC X X X X X X X X X X CB BG CG X X X X X X X 11-25 Packages and Thermal Characteristics Physical Dimensions Plastic DIP Packages -- PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SOIC Packages -- SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TSOP Packages -- VO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PLCC Packages -- PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PQFP Packages -- PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304 . . . . . 32 TQFP Packages -- TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 VQFP Packages -- VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 BGA Packages -- BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ceramic DIP Packages -- DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ceramic PGA Packages -- PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299, PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ceramic Brazed QFP Packages -- CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 CLCC Packages -- CC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Plastic PGA Packages -- PP132, PP175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Windowed CLCC Packages -- WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Metal Quad Packages -- MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11-26 June 1, 1996 (Version 1.0) Plastic DIP Packages -- PD8, PD48 June 1, 1996 (Version 1.0) 11-27 Packages and Thermal Characteristics 11-28 June 1, 1996 (Version 1.0) SOIC Packages -- SO8 June 1, 1996 (Version 1.0) 11-29 Packages and Thermal Characteristics TSOP Packages -- VO8 11-30 June 1, 1996 (Version 1.0) PLCC Packages -- PC20, PC28, PC44, PC68, PC84 June 1, 1996 (Version 1.0) 11-31 Packages and Thermal Characteristics PQFP Packages -- PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304 11-32 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-33 Packages and Thermal Characteristics 11-34 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-35 Packages and Thermal Characteristics 11-36 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-37 Packages and Thermal Characteristics TQFP Packages -- TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 11-38 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-39 Packages and Thermal Characteristics 11-40 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-41 Packages and Thermal Characteristics VQFP Packages -- VQ44, VQ64, VQ100 11-42 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-43 Packages and Thermal Characteristics 11-44 June 1, 1996 (Version 1.0) BGA Packages -- BG225, BG352, BG432 June 1, 1996 (Version 1.0) 11-45 Packages and Thermal Characteristics 11-46 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-47 Packages and Thermal Characteristics Ceramic DIP Packages -- DD8 11-48 June 1, 1996 (Version 1.0) Ceramic PGA Packages -- PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299, PG411 June 1, 1996 (Version 1.0) 11-49 Packages and Thermal Characteristics 11-50 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-51 Packages and Thermal Characteristics 11-52 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-53 Packages and Thermal Characteristics 11-54 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-55 Packages and Thermal Characteristics 11-56 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-57 Packages and Thermal Characteristics 11-58 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-59 Packages and Thermal Characteristics 11-60 June 1, 1996 (Version 1.0) Ceramic Brazed QFP Packages -- CB100, CB164, CB196, CB228 June 1, 1996 (Version 1.0) 11-61 Packages and Thermal Characteristics 11-62 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-63 Packages and Thermal Characteristics 11-64 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-65 Packages and Thermal Characteristics 11-66 June 1, 1996 (Version 1.0) CLCC Packages -- CC20 June 1, 1996 (Version 1.0) 11-67 Packages and Thermal Characteristics Plastic PGA Packages -- PP132, PP175 11-68 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) 11-69 Packages and Thermal Characteristics Windowed CLCC Packages -- WC44, WC68, WC84 11-70 June 1, 1996 (Version 1.0) Metal Quad Packages -- MQ208, MQ240 June 1, 1996 (Version 1.0) 11-71 Packages and Thermal Characteristics 11-72 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Testing, Quality, and Reliability 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Testing, Quality, and Reliability Table of Contents Quality Assurance and Reliability Quality Assurance Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Integrity and Assembly Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cell Design in the FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Temperature Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 12-2 12-2 12-2 12-3 12-6 12-6 12-7 12-8 12-8 Quality Assurance and Reliability June 1, 1996 (Version 1.0) Quality Assurance Program All aspects of the Quality Assurance Program at Xilinx have been designed to eliminate the root cause of defects, rather than to try to remove them by inspection. A quality system was put in place which is in full compliance with the requirements of ISO9002. Xilinx was found to be in full compliance of the requirements of ISO9002:1994 by an independent auditor in October, 1995. At that time Xilinx was registered for "the manufacturing and testing of programmable logic devices". * * * The aspects of ISO compliance in place at Xilinx include the following seventeen points: * * * * * Management Review: a comprehensive system of management attention and direction for all aspects of company performance that directly affect our customers. These include (among others) Xilinx performance in the areas of Quality, Reliability and OnTime Delivery. Management assures that this quality policy is understood, implemented and maintained at all levels in the organization. Quality Systems: are in place to ensure that product conforms to customer specifications. These systems facilitate, measure and continuously improve Xilinx performance in those areas that affect customer satisfaction. Xilinx remains committed to achieving 100% customer satisfaction. Contract Review: is conducted to ensure each contract adequately defines and documents requirements, that differences between customer and Xilinx standard specifications are mutually satisfactorily resolved, and that Xilinx has the capability to meet contract requirements. Document Control: procedures are established and maintained to control all documents and data that relate to the performance of Xilinx business and processing requirements. All organizations who need access to such documentation during the performance of their functions are assured availability of the latest, controlled versions of that documentation. Purchasing: procedures are in place to ensure that all purchased products conform to the specified requirements. As Xilinx is a "fabless" manufacturing company, special attention is paid to our subcontract partners. They are required to demonstrate the type of control and capabilities that our customers require. All key Xilinx subcontract partners are ISO certified. June 1, 1996 (Version 1.0) * * * * * * * Product Identification & Traceability: is maintained throughout the manufacturing process. Traceability back to the starting materials is available through unique product identification techniques and markings throughout the manufacturing process. Process Control: is assured by identifying and controlling those processes that directly affect the quality of our products, whether those processes are performed directly by Xilinx, or by our subcontract partners. Inspection & Test: is performed to ensure that incoming product is not used or processed until it has been verified as conforming to required specifications. This inspection is done jointly by Xilinx and by its subcontract partners. Inspection, Measuring and Test Equipment: is calibrated in conformance with the requirements of Mil Ref 45662 and/or other international standards. Equipment is maintained in such a manner to ensure that measurement uncertainty is known and is consistent with specification requirements. Inspection & Test Status: of product is uniquely identified throughout the manufacturing process both at Xilinx and at our subcontract partners. Records are kept to identify the authority responsible for the release of conforming production. Control of Non-Conforming Product: is assured through disposition procedures that are defined in such a manner as to prevent the shipping of non-conforming products. The responsibility and authority for the disposition of such products are well defined. Corrective Action: processes are documented and implemented to prevent the recurrence of nonconforming product. These processes are the key to implementing the Xilinx strategy of eliminating the root causes of nonconformity, rather that to apply inspection to try to remove nonconformity. Handling, Storage, Packing & Delivery: procedures are defined and implemented to prevent damage or deterioration of product once the manufacturing process is complete. Quality Records: procedures are established and maintained for the identification, collection, indexing, filing, storage, maintenance and disposition of quality records. Internal Quality Audits: are carried out to verify whether quality activities comply with planned arrangements and to determine the effectiveness of the quality system. These audits are regularly 12-1 Quality Assurance and Reliability * * Description of Tests supplemented by quality audits performed by our customers, and by our independent ISO auditors. Training: procedures have been established and are maintained to identify the training needs of all personnel affecting quality during the production of Xilinx products. Personnel performing such activities are qualified based upon appropriate education, training and/or experience. Statistical Techniques: are in place at Xilinx and at our subcontract partners for verifying the acceptability of process capabilities and product characteristics. Die Qualification 1. High Temperature Life: This test is performed to evaluate the long-term reliability and life characteristics of the die. It is defined by the Military Standard from which it is derived as a "Die-Related Test" and is contained in the Group C Quality Conformance Tests. Because of the acceleration factor induced by higher temperatures, (typically 125C and/or 145C) data representing a large number of equivalent hours at a normal temperature of 25C can be accumulated in a reasonable period of time. These key requirements are in place at Xilinx and at our subcontract partners to ensure our ability to achieve customer satisfaction through the on-time delivery of quality products that meet customer requirements and are reliable. 2. Biased Moisture Life: This test is performed to evaluate the reliability of the die under conditions of long-term exposure to severe, high-moisture environments that could cause corrosion. Although it clearly stresses the package as well, this test is typically grouped under the die-related tests. The device is operated at maximumrated voltage, 5.5 Vdc, and is exposed to a temperature of 85C and a relative humidity of 85% throughout the test. Device Reliability Device reliability is often expressed in a measurement called Failures in Time (FITs). In this measure one FIT equals one failure per billion (109) device operating hours. A failure rate in FITS must include the operating temperature to be meaningful. Hence failure rates are often expressed in FITS at 70C (or some other temperature in excess of the application). Package Integrity and Assembly Qualification Since one billion hours is well in excess of 100,000 years, the FIT rate of modern ICs can only be measured by accelerating the failure rate by testing at a higher junction temperature (usually 125C or 145C). Extensive testing of Xilinx devices (performed on actual production devices taken directly from finished goods) has been accomplished continuously since 1989 and reported quarterly. Quarterly reports on the reliability of Xilinx products are available through your Xilinx sales representative. During the last two years, over 20,000 devices have accumulated a total of over 36,000,000 hours of both static and dynamic operation at 125C (equivalent) to yield the FIT rates shown in Figure 1. 1. Unbiased Pressure Pot: This test is performed at a temperature of 121C and a pressure of 2 atm of saturated steam to evaluate the ability of the plastic encapsulating material to resist water vapor. Moisture penetrating the package could induce corrosion of the bonding wires and nonglassivated metal areas of the die (bonding pads only for FPGA devices). Under extreme conditions, moisture could cause drive-in and corrosion under the glassivation. Although it is difficult to correlate this test to actual field conditions, it provides a wellestablished method for relative comparison of plastic packaging materials and assembly and molding techniques. Failure Rate in FITs @ 70C 50 Failure Rate 40 XC4000 XC1700 30 XC3000 20 10 XC3100 XC2000 0 -10 6/94 9/94 10/94 3/95 Time 6/95 9/95 12/95 X5977 Figure 1: Failure Rates in FITs 12-2 June 1, 1996 (Version 1.0) 2. Thermal Shock: This test is performed to evaluate the resistance of the package to cracking and resistance of the bonding wires and lead frame to separation or damage. It involves nearly instantaneous change in temperature from -65C to +150C (condition "C"). 3. Temperature Cycling: This test is performed to evaluate the long-term resistance of the package to damage from alternating exposure to temperature extremes. The range of temperatures is -65C to +150C (condition "C"). The transition time is longer than that in the Thermal Shock test but the test is conducted for many more cycles. 4. Salt Atmosphere: This test was originally designed by the US Navy to evaluate resistance of military-grade ship-board electronics to corrosion from sea water. It is used more generally for non-hermetic industrial and commercial products as a test of corrosion resistance of the package marking and finish. 5. Resistance to Solvents: This test is performed to evaluate the integrity of the package marking during exposure to a variety of solvents. This is an especially important test, since an increasing number of boardlevel assemblies are subjected to severe conditions of June 1, 1996 (Version 1.0) automated cleaning before system assembly. This test is performed according to the methods specified by MILSTD-883. 6. Solderability: This test is performed to evaluate the solderability of the leads under conditions of low soldering temperature following exposure to the aging effects of water vapor. 7. Lead Fatigue: This test is performed to evaluate the resistance of the completed assembly to vibrations during storage, shipping, and operation. Testing Facilities Xilinx has complete capability to perform High Temperature Life Testing, Thermal Shock, Temperature Cycling, Biased Moisture Life Test, Unbiased Pressure Pot, Solderability and Hermeticity, as well as complete Failure Analysis in house. Table 1 and Table 2 show typical qualification requirements for new and/or changed process flows. Table 3 is a list of current failure analysis capabilities. These laboratories are dedicated exclusively to increasing customer satisfaction through continuous improvements in our processes and technologies. 12-3 Quality Assurance and Reliability Table 1: Plastic Package/Product Qualification Requirements New Assy Techniques (Mat'l/Process/Method Test Seq Test Description (note 1) Acc# New S.Size Assy (note 2) Plant New New Pkg Pkg Type I Type II (note3) (note4) B1 * Phy. Dimension 0/5 X B2 * Resist. to Solvents 0/3 X X B3 * Solderability Test (note 7) 0/5 X B4 Solder Heat Test (Optn'l) 0/15 B5 Auto Clave (SPP)(Optn'l) 0/76 0/76 X X B6 * Ball Shear/Bond Pull (note 7) 0/5 X X B7 ** X-Ray (note 7) 0/5 X B8 * S.A.T/Dye Pen Test (note 7) 0/10 X B9 * Adhesion of L/Finish (Optn'l) Die Coat Wire Bond X X X X X X X X X X X X X X X X 0/3 X 0/25 X X X B11 Internal Visual (note 7) 0/5 X X X B12 * Die Shear (note 7) 0/5 X X 0/76 C1-B Low Temp Life Test (note 7) 0/22 0/76 New Fab Proc X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X C2-A:HAST (0/22) or C2-B: 85/85 C3 ESD (HBM) 0/3 C4 High Temp Storage (Optn'l) 0/77 D1 * Lead Integrity 0/3 D2 Thermal Shock (Optn'l) 0/76 D3 Temp Cycle 0/76 X X E1 Electrical Test & Data Log 0/30 X X X E2 Electrical Characterization 0/30 X X X E3 T.D.D.B (note 7) - X X X E4 Latch-up 0/9 X X X E5 Electromigration (note 7) - X X X E6 Photosensitivity (Optn'l) 0/11 X X X E7 Data Retention Bake EPLD & EPR 0/22 X X X E8 Input/Output Capacitance 0/5 X X X E9 Power Cycling (Optn'l) 0/22 X X X 393 464 636 Qty required per lot X X C2 E.Good X X X X X X X X X X Full Qual X X X X Lead New Finish Device Mask (note6) X Per lot C1-A High Temp Life Test Mold CLP X B10 * External Visual (note 7) B13 Flammability Test (note 7) New Lead Die Pkg Frame Attach Type III LF Design (note5) X X X X X X X X X X X X X X X 239 X 238 X 162 X 248 X 248 X 157 X 314 X 86 X 325 0 E.Reject 63 48 43 35 43 5 5 5 43 29 10 10 64 Total 302 286 205 283 291 162 319 91 368 29 403 474 700 Notes: 1) Test method and stress conditions available upon request. 2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is required. 3) Any new package which has not been qualified in the qualified assembly facility. 4) Any new package where the same body size with different lead pitch has been qualified. 5) New leadframe design whereby the paddle size is larger than the existing leadframe paddle size used in the same qualified package. 6) For new mask from same device family, only high temp life test, ESD, Latch & Capacitance are required. 7) In-process monitor data may be used to satisfy this requirement. *) Electrical rejects can be used as test sample. **) This is a non-destructive test, sample can be re-used. 12-4 June 1, 1996 (Version 1.0) Table 2: Hermetic Package/Product Qualification Requirements (Commercial) New Assy Techniques (Mat'l/Process/Method Test Seq Test Description (note 1) Acc# New S.Size Assy (note 2) Plant New New Lead Die Pkg Pkg Frame Attach Family Qual (note3) Family (note4) B1 Solder Heat Test (Optn'l) 0/15 B2 * Resist. to Solvents (note 7) 0/3 X X X B3 * Solderability Test (note 7) 0/3 X X B4 * Die Shear/Stud Pull (note 7) 0/5 X X X B5 * Bond Pull (note 7) 0/2 X X X X B6 * External Visual (note 7) 0/25 X X X X B7 Internal Visual (note 7) X X 0/5 X X C1-A High Temp Life Test 0/76 X X C1-B Low Temp Life Test (note 7) 0/22 Die Coat Wire Type of Lead New New Bond Seal Finish Cavity Device Size (note6) (note6) X X X X X C2 High Temp Storage (Optn'l) 0/77 C3 ESD (HBM) 0/3 D1 * Phy. Dimension 0/15 X X X D2 * Lead Integrity 0/3 X X X X D3 Thermal Shock + Temp Cycl + Moisture Resistance 0/32 X X X X X D4 Mech. Shock + Vibration + Constant Acceleration 0/32 X X X X X D5 * Salt Atmosphere 0/15 X X X D6 * Internal Vapor Content (note 7) 0/3 X X X D7 * Adhesion of L/Finish (Optn'l) 0/2 X X X D8 * Lid Torque 0/5 X X X D9 Temp Cycle 0/45 X X X E1 Electrical Test & Data Log E2 Electrical Characterization E3 T.D.D.B (note 7) E4 Latch-up E5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Full Qual X X X New Fab Proc X X X X X X X 0/30 X X X 0/30 X X X - X X X 0/9 X X X Electromigration (note 7) - X X X E6 Photosensitivity (Optn'l) 0/11 X X X E7 Data Retention Bake 0/22 X X X E8 Input/Output Capacitance 0/5 X X X 414 Qty required per lot X X X X X X X X X X X X X X X X E.Good 190 205 129 69 114 235 190 124 32 124 399 399 E.Reject 81 81 75 50 8 5 2 33 41 48 7 50 81 Total 271 286 204 119 122 240 192 157 73 172 406 449 495 Notes: 1) Test method and stress conditions available upon request. 2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is required. 3) Package Family - A set of package type with the same package, material, Package construction techniques, terminal pitch, lead shape, row spacing and with identical package assembly tech. 4) Package Type - A package with a unique case outline, configuration, material, piece parts and assembly process. 5) Application to new piece parts or leadframe where cavity size is larger than the largest cavity size for the same package. 6) For new mask from same device family, only high temp life test, ESP, Latch & Capacitance are required. 7) In-process monitor data may be used to satisfy this requirement, for Qual data, data from Assy. lot traveler maybe used. *) Electrical rejects can be used as test samples June 1, 1996 (Version 1.0) 12-5 Quality Assurance and Reliability Table 3: Failure Analysis Equipment List Vendor JEOL Model Number JMS-6401F ANATECH Hummer VIII OXFORD INST. F.E.I. LINK ISISL200C FIB-600 19 Solder Wave/Pot FXS-100.10 21 Conventional Oven (C.D.A.) Micro-Scan 4HF-200 MBS-200 22 Drill-bit to open MQUADS XRF Lead Finish/Composition Twin City, Inc. Measurement System 9 Liquid Crystal Hot Spot Detec- Technology tion System/Kit, with 3 temp. Associates Hypervision 10 Emission Microscope for Multilayer Inspection (EMMI) BID Services 11 Curve Tracer XRF-5500 24 Stud Pull Tester P/N 4330 25 Work Benches Visionary 2000 26 Cabinets 12 Metallurgical High Power see quote (various) 28 Tool Maker Microscope see quote (various) 29 Flowhood & Rinse Station Item 1 2 3 4 Equipment Scanning Electron Microscope Gold Sputter (SEM Sample Prep) Energy Dispersive X-Ray 6 F.I.B. - Focused Ion Beam Workstation Real-Time X-Ray Imaging Sys- FEIN FOCUS tem Scanning Acoustic Microscopy Sonix 7 Ball Shear Strength Tester 5 KELLER 8 Item Equipment 17 Die-Shear Tester Vendor KELLER 18 Steam Aging System Robotic Systems Robotic Systems B&G 20 Lead Fatigue Tester Model Number see #7 ST2D RPS-202 004-012-00 BID Services + Decapping vise 23 Color Printer Tektronic B&G Tektronic Phaser IISD 003-010-00 27 Facilities (Lab Area and Equipment Installation Costs) Microscope 13 Stereozoom Low Power Microscope - video camera + monitor 14 Micro-Etcher System Scientific Instrument Company Scientific Instrument Company TM Associates 30 Precision X-Sectioning Equipment 15 Viseco Camera Interface with High Power Microscope 16 Hermeticity Test System - Fine Leak - Gross Leak Computer Modules BID Services -Trio-tech 486 - Veeco MS170 31 Plasma Etcher March Instruments CS-1701 32 E-Beam IDS-3000 Data Integrity Memory Cell Design in the FPGA Device An important aspect of SRAM-based FPGA device reliability is the robustness of the static memory cells used to store the configuration program. The basic cell is a single-ended 5-transistor memory element (Figure 2). By eliminating a sixth transistor, which would have been used as a pass transistor for the complementary bit line, a higher circuit density is achieved. During normal operation, the outputs of these cells are fixed, since they determine the user configuration. Write and readback times, which have no relation to the device performance during normal operation, will be slower without the extra transistor. In return, the user receives more functionality per unit area. This explains the basic cell, but how is the FPGA user assured of high data integrity in a noisy environment? Con12-6 sider three different situations: normal operation, a Write operation and a Read operation. In the normal operation, the data in the basic memory element is not changed. Since the two circularly linked inverters that hold the data are physically adjacent, supply transients result in only small relative differences in voltages. Each inverter is truly a complementary pair of transistors. Therefore, whether the output is High or Low, a low-impedance path exists to the supply rail, resulting in extremely high noise immunity. Power supply or ground transients of several volts have no effect on stored data. The transistor driving the bit line has been carefully designed so that whenever the data to be written is opposite the data stored, it can easily override the output of the feedback inverter. The reliability of the Write operation is guaranteed within the tolerances of the manufacturing process. June 1, 1996 (Version 1.0) VCC VCC Configuration Data Shift Regiater Q N-1 DS Q DS DR DR DK SEL DK SEL Q Read Data Clock Clock WR/RD Address QN-1 D Q CK Precharge Word N Memory Cell Circuit Word Line Driver Memory Cell Configuration Address Shift Regiater D Q Memory Cell Word Line Driver Word N+1 Memory Cell CK Memory Cell Bit M Bit M+1 X3124 Figure 2: Configuration Memory Cell In the Read mode, the bit line, which has a significant amount of parasitic capacitance, is precharged to a logic one. The pass transistor is then enabled by driving the word line High. If the stored value is a zero, the line is then discharged to ground. Reliable reading of the memory cell is achieved by reducing the word line High level during reading to a level that insures that the cell will not be disturbed. Electrostatic Discharge Electrostatic-discharge (ESD) protection for each pad is provided by circuitry that uses distributed transistors and/or diodes, represented by the circles in Figure 3. In older devices, these protection circuits are conventional diffused structures. In newer designs, Xilinx utilizes proprietary device structures which exhibit substantially enhanced ESD performance (see Table 4). June 1, 1996 (Version 1.0) Whenever the voltage on a pad approaches a dangerous level, current flows through the protective structures to or from a power supply rail (VCC or ground). In addition, the capacitances in these structures integrate the pulse to provide sufficient time for the protection networks to clamp the input, avoiding damage to the circuit being protected. Geometries and doping levels are chosen to provide ESD protection on all pads for both positive and negative voltages. Table 4: ESD Performance of Xilinx Components Human Body Model 883D Method 3015 Machine Model EIAJ Method 20 Charged Device Model CDM XC1700D >6,000 V 800 V - 900 V >2,000 V XC2000 2,000 V - 2,500 V 250 V - 280 V Circuit Family XC3000A 3,000 V - 8,000 V 600 V - 700 V XC3100 2,500 V - 3,500 V 600 V - 700 V XC4000 4,000 V - 9,000 V 800 V - 900 V XC4000E 4,000 V- 5,000 V 600 V- 900 V XC5200 3,000 V- 5,000 V tbd XC7000 2,000 V- 4,000 V 250 V- 300 V >2,000 V >2,000 V >2,000 V >2,000 V 12-7 Quality Assurance and Reliability VCC VCC ROUT Output Pad Ground VCC Input Pad RIN Ground X1825 = Symbol for electrostatic discharge protection circuit X3132 Figure 3: Input/Output Protection Circuity Figure 4: SCR Model Latchup Latchup is a condition in which parasitic bipolar transistors form a positive feedback loop (Figure 4), which quickly reaches current levels that permanently damage the device. Xilinx uses techniques based on doping levels and circuit placement to avoid this phenomenon. The beta of each parasitic transistor is minimized by increasing the base width. This is achieved with large physical spacings. The butting contacts effectively short the n+ and p+ regions for both wells, which makes the VBE of each parasitic very close to zero. This also makes the parasitic transistors very hard to forward bias. Finally, each well is surrounded by a dummy collector, which forces the VCE of each parasitic almost to zero and creates a structure in which the base width of each parasitic is large, thus making latchup extremely difficult to induce. 12-8 At elevated temperatures, 100 mA will not cause latchup. At room temperature, the FPGA can withstand more than 300 mA without latchup; the EPLD device can withstand more than 200 mA without latchup. However, to avoid metalmigration problems, continuous currents in excess of 10 mA are not recommended. High Temperature Performance Although Xilinx guarantees parts to perform only within the specifications of the data sheet, extensive high temperature life testing has been done at 145C with excellent results. June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Technical Support 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Technical Support Table of Contents Technical Support Technical Support Hotlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hotline Support, Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-TALX: The Xilinx Network of Electronic Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WebLINX World Wide Web Site (www.xilinx.com) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XDOCs E-mail Document Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XFACTS Document Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Technical Bulletin Board Service (408) 559-9327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-mail addresses for questions related to specific applications . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support E-mail addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AppLINX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCELL Newsletter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What You Will Learn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hands-On Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Course Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic-Based Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis-Based Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesis-Based Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Update and Advanced Training Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer-Site Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-2 13-2 13-2 13-3 13-3 13-3 13-3 13-3 13-4 13-4 13-5 13-5 13-5 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-6 13-7 13-7 13-7 13-7 13-8 13-8 13-9 Technical Support June 1, 1996 (Version 1.0) A complete and uniquely accessible offering of worldwide technical support services is available to Xilinx users. Xilinx Field Application Engineers, located at sales offices and technical support centers worldwide, provide local engineering support, including design evaluation of new projects, close consultation throughout the design process, special training assignments, and new product presentations. Because their role as advisors and troubleshooters keeps them constantly on the go, they are best used, not for general questions, but for more targeted queries such as those related to architectural recommendations. The worldwide network of Xilinx sales representatives and distributors also provide local technical support for Xilinx users. More general queries can be directed to the telephone "hotlines". Permanent teams of expert Technical Support Engineers located in the United States, United Kingdom, France, Germany, and Japan can handle problems and answer questions right on the spot, ensuring that the design process keeps moving forward. In addition, Xilinx has several automated services, collectively referred to as X-TALX, to provide answers to user's queries 24 hours a day. These include a world wide web site, E-mail server, automated FAX system, bulletin board system, and special interest E-mail groups. June 1, 1996 (Version 1.0) Many different publications assist users in completing designs quickly and efficiently, including technical manuals, data sheets, the AppLINX CD-ROM (a regularly-updated collection of the latest application notes and design hints), and the quarterly XCell newsletter. For more in-depth support and instruction, a dedicated training organization conducts technical training classes worldwide. Courses geared for both novice and experienced users are available. The following Technical Support Services are discussed in more detail in this chapter: * * * * * * Technical Support Hotline X-TALX: The Xilinx Network of Electronic Services - WebLINX World Wide Web Site - XDOCs E-mail document server - XFACTS document server - Xilinx Technical Bulletin Board Service Technical Literature AppLINX CD-ROM XCELL newsletter Training Courses 13-1 Technical Support Technical Support Hotlines The technical support hotlines give Xilinx users direct telephone access to Xilinx Technical Support Engineers worldwide, providing a quick resolution to any problem that occurs during the design process. Technical questions also may be submitted via FAX or E-mail. Hotline Support, U.S. Hotline Support, Japan telephone: (81) 3-3297-9163 fax: (81) 3-3297-0067 e-mail: jhotline@xilinx.com Hotline Support, Europe UK, London Office Customer Support Hotline 800-255-7778 Hrs: 8:00 a.m. - 5:00 p.m. Pacific time 408-879-4442 Avail: 24 hrs/day-7 days/week hotline@xilinx.com 408-559-9327 Customer Support Fax Number E-mail Address Electronic Technical Bulletin Board Customer Service 408-559-7778, (Call for software up- Ask for customer service dates, authorization codes, documentation updates, etc.) 13-2 telephone: (44) 1932 820821 fax: (44) 1932 828522 Bulletin Board Service: (44) 1932 333540 e-mail: ukhelp@xilinx.com France, Paris Office telephone: (33) 1 3463 0100 fax: (33) 1 3463 0959 e-mail: frhelp@xilinx.com Germany, Munich Office telephone: (49) 89 991 54930 fax: (49) 89 904 4748 e-mail: dlhelp@xilinx.com June 1, 1996 (Version 1.0) X-TALX: The Xilinx Network of Electronic Services WebLINX World Wide Web Site (www.xilinx.com) Our World Wide Web site provides access to current information, including product data sheets, application notes, press releases, financial status, employment opportunities, and an on-line technical support database. SmartSearch, our industry-wide search engine, is the definitive resource for programmable logic information. SmartSearch Agents will watch the Web for you and inform you, via e-mail, when new or updated information is found. An FTP site also is available to facilitate the quick and easy transfer of design and data files (ftp.xilinx.com). XDOCs E-mail Document Server The XDOCS E-mail system provides 24-hour a day, 7 days a week access to the same database that the Technical Support Engineers use. This database is updated regularly with information on bugs, workarounds, and helpful hints. Via E-mail, users can search for a specific record, or supply keywords to trigger a search of the database; XDOCS will send the requested information by return E-mail. Automated updates also can be sent on a periodic basis notifying users of new additions to the system. To subscribe to XDOCS, send an E-mail to xdocs@xilinx.com with "help" as the only word in the subject header. New bulletin board users must answer a questionnaire when they first access the BBS. After answering the questionnaire, callers can browse through the file areas or upload files. A caller with a valid XACT protection key or valid host ID will be given full user privileges within 24 hours. The software and hardware requirements for accessing the BBS are as follows: Baud Rate 28.8K or less bps Character Format 8 data bits, no parity, 1 stop bit Transfer Protocols ASCII, Xmodem, Ymodem, Zmodem The Xilinx Technical Support BBS is a menu-driven system. To choose a menu command, simply type the highlighted first letter of the command. Most commands are "hot keys" and do not require you to press the return key. Here is a quick description of the available menu commands: Main U)pload Upload a file to the Technical Support group. D)ownload Download a file. This assumes you already know the filename, otherwise select the File Manager. F)ile Manager Takes you to the File Manager menu. This menu is for locating files. S)ystem Folder Takes you to the System menu. This menu is for changing your password, display options, etc. XFACTS Document Server The XFACTS automated FAX system provides the same information as XDOCS, but uses a phone/FAX interface instead of E-mail. Using a touch-tone telephone, users can request documents that are sent to their FAX machine. Located in San Jose, California, the XFACTS system can be reached at 408-879-4400. File Manager F)lag Flag files for download. L)ocate Files Use wildcards to search for files. N)ew Files Lists recently added files. Z)ippy DIR scan Searches for text in file descriptions. Xilinx Technical Bulletin Board Service (408) 559-9327 #'s Chooses a file area to browse. To provide users with up-to-date information and software support, Xilinx provides a 24-hour electronic bulletin board system (BBS). The Xilinx Technical Support BBS is available to all registered Xilinx development system users. Users with full privileges can browse files on the bulletin board, download those of interest, or upload files to Technical Support Engineers. M)ode of display Toggles between text and graphics display P)age length Changes the number of printed lines between "More?" prompts. T)ransfer Protocol Changes the default transfer protocol. V)iew Settings Shows current settings and user information. W)rite User Info Changes current user settings. All BBS files can be accessed through the Xilinx Web and FTP locations. June 1, 1996 (Version 1.0) System 13-3 Technical Support E-mail addresses for questions related to specific applications Digital Signal Processing applications PCI-bus applications Plug and Play ISA applications PCMCIA card applications Asynchronous Transfer Mode applications Reconfigurable Computing applications dsp@xilinx.com pci@xilinx.com PnP@xilinx.com pcmcia@xilinx.com atm@xilinx.com reconfig@xilinx.com Technical Support E-mail addresses hotline@xilinx.com ukhelp@xilinx.com frhelp@xilinx.com dlhelp@xilinx.com jhotline@xilinx.com 13-4 USA, Xilinx Headquarters United Kingdom France Germany Japan June 1, 1996 (Version 1.0) Technical Literature XCELL Newsletter Xilinx offers many different publications to assist users in completing designs quickly and efficiently. These include technical manuals, Data Books, data sheets, application notes, AppLINX CD, and the XCELL newsletter. Many of these publications are available on-line at the Xilinx WebLINX World Wide Web site. XCELL, the quarterly journal for Xilinx programmable logic users, is dedicated to supplying up-to-date information for system designers. A typical issue includes descriptions of new products, updates on component and software availability and revision levels, application ideas, design hints and techniques, and answers to frequently-asked questions. As part of the development system products, Xilinx provides manuals and supporting documents for the development system tools, libraries, CAE tool interfaces, and related software tools. Many of these manuals are available on the CD that holds the software as well as hardcopy format. On-line help facilities also are an integral part of the development system products. To add your name to the XCELL subscription list, please send your name, company affiliation, and mailing address to Brad Fawcett, XCELL editor, via FAX at 408-879-4676 or via e-mail sent to brad.fawcett@xilinx.com. AppLINX AppLINX is a collection of current application notes and other new technical documentation provided on a CD-ROM for easy reference by the design engineer. All the material on the CD is provided in Adobe Acrobat format for easy viewing and printing. The AppLINX CD is updated regularly as new material becomes available. June 1, 1996 (Version 1.0) 13-5 Technical Support Programmable Logic Training Courses All users of Xilinx products should attend one of our Training Courses. Attending a Xilinx Training Course is one of the fastest and most efficient ways to learn how to design with FPGA or CPLD devices from Xilinx. Hands-on expert instruction with the latest information and software will allow you to implement your own designs in less time with more effective use of the devices. Xilinx offers a variety of classes to meet your specific needs. Training centers around the world schedule classes on a regular basis, and the classes can even be brought to your own facility. What You Will Learn Not only will you learn about our products, but we will recommend the best ways to use the software based on our years of experience with thousands of designs. You will learn how to efficiently enter, implement, and verify your design. The powerful yet easy-to-use Xilinx development system allows you to utilize the Xilinx automatic mode, or take a power-user approach and direct the automatic tools to the best implementation of your design. Prerequisites Instructors Students need only have a background in digital logic design. Basic familiarity with the PC or workstation is helpful but not required. It will benefit you to learn your design entry tool of choice before attending the Xilinx class, including an HDL language for the synthesis-based classes. Update or Advanced classes require previous experience with the Xilinx products. Xilinx Training Courses have been successfully held worldwide for over six years. The instructors are Xilinx experts who are skilled at passing that knowledge on to fellow engineers. A dedicated Training organization at Xilinx works closely with the Applications and Engineering groups to keep the classes up-to-date with the latest improvements and recommendations for Xilinx and third-party tools. Benefits Course Materials * * * * * * All course materials are supplied by Xilinx. Every student gets an excellent reference tool in the form of course notes, that include all the material presented during the class. The course notes are bound for easy use and include additional reference material beyond what is covered in the class. Start or Complete Your Design During the Class Reduce Your Learning Time Make Fewer Design Iterations Get to Market Faster Lower Production Costs Increase Quality The Training Classes Xilinx offers classes for both schematic entry users and synthesis users, and both new and experienced users. All Xilinx classes focus on the Xilinx products, independent of the specific design entry tool. Product Coverage Xilinx classes will cover the latest released versions of our devices and development systems. While all available products are covered, emphasis is placed on the more popular and/or recommended solutions. New products are added to the class as they become available. Hands-On Experience Each class includes over two hours each day for hands-on labs. There is at least one computer for every two people in the class. 13-6 June 1, 1996 (Version 1.0) Schematic-Based Course Outline Synthesis-Based Course Outline The schematic-based Xilinx Training Class lasts three days. All North American training sites, and most international locations, teach the same class. The following is a complete outline of the three-day synthesis-based class: * * * * * * * * * Introduction - Development System Overview - Architecture Overview Xilinx Design Flow - Schematic Entry Guidelines - Design Manager - Flow Engine Automatic Translation Timing Specification - XACT-Performance Delay Specification - Static Timing Analyzer Designing for Xilinx FPGAs - Combinatorial Logic - Registered Logic - Memory Design - I/O Design - X-BLOX Module Generation Designing for Xilinx CPLDs Text Entry Guidelines - Xilinx-ABEL software Floorplanning - Incremental Design - XACT-Floorplanner - Relationally-Placed Macros Timing Analysis - Good Design Practices - Simulation Guidelines Configuration - Programming Modes - Bitstream Generator - PROM File Formatter - Hardware Debugger Download & Readback Synthesis-Based Classes Designing with high-level languages (VHDL and Verilog) and synthesis tools can be very different from using schematic entry. As a result, Xilinx offers classes that focus on VHDL and Verilog design entry for Xilinx products. Xilinx highly recommends the synthesis-based class for anyone using VHDL or Verilog for design entry. Synthesis-based classes include the following additional topics, using HDL code for design entry: * * * * Good coding styles Hierarchy within synthesis Synthesis design flow Controlling Xilinx implementation tools with synthesis June 1, 1996 (Version 1.0) * * * * * * * * * * Introduction FPGA Architecture Xilinx-Synopsys Design Flow - Good Coding Styles - Synopsys Scripts - Design Manager - Automatic Translation Timing Specification - XACT-Performance Delay Specification - Static Timing Analyzer Simulation Guidelines Good Design Practices Coding for Xilinx FPGAs - Combinatorial Logic - Carry Logic and X-BLOX Module Generation - Registered Logic - I/O Design - Memory Design Hierarchy Floorplanning - Incremental Design - XACT-Floorplanner Configuration - Programming Modes - Bitstream Generator - PROM File Formatter - XChecker Download & Readback Update and Advanced Training Classes If you have already attended a Xilinx class or have experience using Xilinx products, consider attending a one-day Update or Advanced Training session. These sessions will be most useful if you have the latest software. Update Classes One-day Update classes focus on the latest released products from Xilinx, describing them in relation to previous versions. For example, an Update class is available describing the new features in XACTstep 6.0. The class will be offered for a limited time at regional sites, or can be brought to your facility. Browse the Xilinx web site (www.xilinx.com) for the latest information regarding special Update classes on new products from Xilinx. 13-7 Technical Support Advanced Training Classes Customer-Site Classes If you have already attended a Xilinx class or have experience using Xilinx products, consider attending a one-day Advanced Training session. Advanced Training classes are offered at no charge to current in-warranty Xilinx customers; otherwise tuition is $200. Advanced Training sessions can vary according to the interests of the students. Popular topics include: Xilinx can bring a Training Course to your own facility for the greatest convenience to your company. * * * * * * Example Logic Design Techniques Timing Analysis and Avoiding Timing Hazards Design Methodology for Tough Designs Details of Advanced Optimization Capabilities XACT Design Editor Floorplanning Advanced Training classes are held regularly at Xilinx headquarters, and sometimes at regional locations, but are replaced by Update Classes when appropriate. See the web site (www.xilinx.com) for scheduled classes, or contact Xilinx Training to hold an Advanced Training session at your site. On-Site Classes Provide Additional Benefits: No Travel Costs On-site Xilinx training classes eliminate travel time and expenses: - No airfare No hotel bills No car rental Classes Tailored To Your Needs On-site classes can be tailored to meet the specific needs of your company: - Training Locations Convenient class time and location Projects of a proprietary nature can be discussed openly Students can use their own equipment and begin an actual design right in class Costs: North America Xilinx Headquarters Classes are held regularly at Xilinx headquarters in San Jose, California. During the class, you may elect to meet one-on-one with Xilinx Applications engineers to discuss specific issues not covered in the class. Topics may include using a specific third-party tool, optimizing your particular design, or more advanced issues beyond the coverage of the class. North American Distributor Locations Xilinx distributors sponsor training classes jointly with Xilinx, using the same material as the headquarters classes. Since the distributor sponsors the class, the tuition cost is often reduced to $495 for customers of the sponsoring distributor. Check with the distributor when registering. Locations include over fifty cities across North America. International Locations Xilinx classes are held throughout Europe, Asia, India, Israel, South Africa, Australia, South America, and other international locations. Classes vary in length and tuition, but are based on the same material used in North America. Contact your local Xilinx sales office or representative for classes in your area. 13-8 Prices start at $4,500 for a minimum class size of six students. Costs: International - Prices vary; contact your local Xilinx sales representative. Included in class fees: - A Xilinx-certified instructor Training materials for each student PC for every two students (or if you prefer, the training labs can be done on your PCs or workstations) Scheduling a Class To schedule a training class at your facility and determine pricing, call the Xilinx sales office nearest you, or your local Xilinx sales representative. On-site training classes are popular, so the more advanced notice we have, the better our ability to schedule your class exactly when you want it. June 1, 1996 (Version 1.0) Registration Enrollment Tuition To enroll, call the registrar for the location where you would like to attend a class. Or you may call the Training Registrar at Xilinx headquarters at (800) 231-3386 or contact your local sales office. You may also register on-line at www.xilinx.com. Class tuition in North America is $1,000 per student for the three-day classes, including the synthesis-based and workstation-based classes at Xilinx headquarters. The distributor-sponsored, schematic-based classes are offered at a reduced rate of $495 for customers of the sponsoring distributor. On-site classes start at $4500 per class, and vary according to the class and the number of students. For international locations, call the local registrar for pricing. Most classes include a full lunch, with morning and afternoon snacks. Let the registrar know if you have any special dietary needs when registering for the class. Money-back Guarantee Xilinx Training Registrar Training Registrar Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: (800) 231-3386 x1 Fax: (408) 879-4676, attn: Customer Training Registrar E-mail: customer.training@xilinx.com Register on-line: www.xilinx.com We are so confident you will be satisfied with the benefits of a Xilinx training class that we offer the following guarantee: Full refund of the class cost if you are not completely satisfied. Location Xilinx Headquarters North America Distributor Locations Customer Site Update Advanced International Locations International Customer Site June 1, 1996 (Version 1.0) Tuition $1,000 * * * $495 * * Starts at $4,500 * Typically $100 * Free * Varies * * Varies * * Benefits Can meet with applications engineers Classes held frequently All class types available Lower cost for distributor's customers Local Convenience; can focus on specific issues One day, focus on new products For experienced, in-warranty users Offered in over 21 countries Native language Convenience Can focus on specific issues 13-9 Technical Support 13-10 June 1, 1996 (Version 1.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Product Technical Information 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Product Technical Information Table of Contents Product Technical Information Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . . . . . . 14-35 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45 Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47 Boundary Scan in XC4000 and XC5000 Series Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49 Product Technical Information Table of Contents Choosing a Xilinx Product Family Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM-Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200) . . . . . . . . . . . . . . . . . . . Overview of SRAM-Based FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) . . . . . . . . . . . . . . . Antifuse-Based FPGAs (XC8100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM- and FLASH-Based CPLDs (XC7300, XC9500) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of CPLD Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Appropriate Xilinx Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Features Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14-3 14-3 14-4 14-5 14-5 14-5 14-5 14-6 14-6 14-6 14-8 XC4000 Series Technical Information Voltage/Current Characteristics of XC4000-Family Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Output Delays When Driving Capacitive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Bounce in XC4000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpretation of the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Reducing Ground-Bounce Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground-Bounce vs Delay Trade-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 and XC4000E Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14-10 14-10 14-10 14-11 14-11 14-11 14-12 XC3000 Series Technical Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generator Avoids Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Bus Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vertical Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal-Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCLK Frequency Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCLK Low-Time Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Back-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beware of a Slow-Rising XC3000 Series RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14-13 14-13 14-14 14-15 14-15 14-16 14-17 14-17 14-17 14-17 14-18 14-18 14-18 14-19 14-19 14-21 14-21 14-21 14-22 14-22 14-23 1 Product Technical Information Table of Contents FPGA Configuration Guidelines Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Against Data or Format Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Best Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . When Configuration Fails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for all Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for the XC2000 and XC3000 Families . . . . . . . . . . . . . . . . . . . . . . . . General Debugging Hints for the XC4000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Mode-Specific Debugging Hints for All Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Debugging Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potential Length-Count Problem in Parallel or Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14-26 14-26 14-26 14-28 14-29 14-29 14-29 14-30 14-30 14-30 14-31 14-32 14-32 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 Configuration Issues: Power-up, Volatility, Security, Battery Back-up Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity to VCC Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security when Configuration Data is Accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security by Hiding the Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Back-up and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14-35 14-36 14-36 14-37 14-37 Dynamic Reconfiguration Important Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reconfiguration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initiating Reconfiguration in Different Xilinx Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC2000 and XC3000 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 Series and XC5200 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 14-40 14-40 14-40 14-40 Metastable Recovery Metastability Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 Metastability Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot 14-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47 Boundary Scan in XC4000 and XC5000 Series Devices Overview of XC4000/XC5000 Boundary-Scan Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deviations from the IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Boundary-Scan Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14-49 14-50 14-51 14-51 14-51 14-51 14-53 14-53 14-54 14-57 14-57 June 1, 1996 (Version 1.0) Choosing a Xilinx Product Family Application Note By PETER ALFKE Summary This Application Note describes the various Xilinx product families. Differences between the families are highlighted. The focus of the discussion is how to choose the appropriate family for a particular application. Xilinx Families Demonstrates XC2000, XC3000, XC4000, XC5000, XC6000, XC7000, XC8000, XC9000 Choosing an appropriate Xilinx family based on the intended application Table of Contents SRAM-Based FPGAs SRAM-Based FPGAs Antifuse-Based FPGAs Xilinx SRAM-based FPGAs fall into two distinct categories. All are reconfigurable and can be programmed in-system; only the XC6200 family can be partially reconfigured and offers a built-in microprocessor interface. The two categories of devices are separately described below. EPROM and FLASH-Based CPLDs Selecting the Appropriate Xilinx Family Introduction Xilinx offers Field-Programmable Logic circuits, mass-produced standard integrated circuits that the user can customize for the specific application. Xilinx products offer the following advantages: * * * * High integration (less space, lower power, higher reliability, lower cost) than solutions based on existing standard devices like MSI and PALs. No non-recurring engineering charges and associated risk, typically required for mask-programmed gate array solutions. Fast design time and easy design modification, important for early time-to-market. Designs can be upgraded in the field for added functionality. Some potential users might be confused by the wide diversity of Xilinx product offerings. This application note provides a broad overview from the user's perspective. Xilinx offers programmable logic circuits in three distinctly different technologies. * * * SRAM-based FPGAs, the original Xilinx offering, now encompassing the XC2000, XC3000, XC4000, XC5200, and XC6200 series and their sub-families, like the XC3000A, XC3000L, XC3100, XC3100A, XC4000A, XC4000H, XC4000E, XC4000L, XC4000EX, and XC4000XL. Antifuse-based FPGAs, the new sea-of-gates XC8100 family. Complex PLDs or EPLDs, XC7300, and XC9500 families. June 1, 1996 (Version 1.0) SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200) These families represent an ongoing evolution of the original Xilinx FPGA architecture, characterized by structural flexibility and an abundance of flip-flops. Logic is implemented in look-up tables, and is interconnected by a hierarchy of metal lines controlled by pass transistors. Attractive systems features include on-chip bidirectional busses and individual output 3-state and slew-rate control, common reset for all flip-flops, and multiple global low-skew clock networks. The configuration can be loaded while the devices are connected into a system, and can be changed an unlimited number of times by reloading the "bitstream," the series of bits used to program the device. Configuration must be reloaded whenever Vcc is re-applied. Reconfiguration takes 20 to 200 ms, during which time all outputs are inactive. Static power consumption is very low, down to microwatts for some of the families. Dynamic power consumption is proportional to the clock frequency, and depends on the logic activity inside the device and on the outputs. The description "SRAM-based" refers primarily to the standard high-volume manufacturing process, and secondarily to the fact that configuration data is stored in latches. Different from typical SRAMs, these latches use low-impedance active pull-up and pull-down transistors. An on-chip voltage monitor 3-states the outputs and initiates reconfiguration when Vcc drops significantly (to 3.2 V in a 5-V system). 14-3 Choosing a Xilinx Product Family These FPGAs are available in different sizes and many different packages. Usually each device type is available in many package types. Any package can accommodate different sized devices with compatible pinouts, so the user can migrate to a larger or smaller device without changing the PC-board layout. Overview of SRAM-Based FPGA Families XC2000: Oldest, simplest, smallest, and lowest-cost FPGA family; not recommended for new designs * * Used for simple, very cost-sensitive applications. Accept limited logic flexibility, 3-input look-up tables, no clock enables, no output slew-rate control, only two device types covering the narrow complexity range of 600 to 1500 gates. The XC5200 and XC8100 FPGA families, or the XC7300 and XC9500 EPLD families, may often be a better alternative. XC2000L: 3.3-V version of XC2000; not recommended for new designs * Used for simple, battery-operated applications. * Accept significantly slower speed at 3.3 V, compared to XC2000 at 5 V. XC3000: Superseded Don't use this venerable family for new designs, since it has been superseded by the improved, but fully backwards compatible, XC3000A family. XC3000A: Newest version of the popular XC3000 family Five device types cover a complexity range from 1,300 to 7,500 gates, with 256 to 928 flip-flops. Logic is implemented in 4-input look-up tables; two tables can be combined to implement any logic function of five variables with only one combinatorial delay of 4 or 5 ns. Flip-flop toggle rate is over 110 MHz. Global choice of input thresholds (1.2 V or 2.5 V), output slew-rate control, and an on-chip crystal oscillator circuit are attractive system features. * * Use for medium-speed, medium-complexity applications. Accept lack of dedicated carry circuits, resulting in less efficient and slower arithmetic and counters than in XC4000E families. No on-chip RAM; data storage is thus limited to the available 256 to 928 flip flops. XC3000L: 3.3-V version of XC3000A * * Use for battery-operated applications. Accept significantly slower speed at 3.3 V, compared to XC3000A at 5 V. XC3100A: Newest version of the popular high-speed XC3100 family XC3100A devices are functionally and bitstream identical with the XC3000A, and are available in the same packages with the same pinouts. The only difference is the higher speed of the XC3100A, with a look-up table delay of 1.5 to 4 ns, and the slightly higher standby current of 8 to 14 mA. One additional high-end family member, the XC3195A, can implement up to 9,000 gates and 1,320 flip-flops. * * XC3100L: 3.3-V version of XC3100A * * 14-4 Use for 3.3-V applications. Accept significantly slower speed at 3.3 V, compared to XC3100A at 5 V, as well as higher quiescent power and much higher powerdown current than XC3000L at 3.3 V. XC4000: Superseded Don't use this family for new designs, since it has been superseded by the improved, but fully backwards compatible XC4000E family. XC4000A: Superseded Don't use this family for new designs, since it has been superseded by the improved, faster, less expensive, and pinout-compatible - but not bitstream-compatible - XC4000E family. XC4000E: Enhanced superset of the XC4000 family The XC4000E family is recommended for new designs. The ten devices in this family stretch from 2,000 to 25,000 gate complexity. The emphasis is on systems features and speed. The function generators are more versatile than in the XC3000-Series parts, and there is a dedicated carry network to speed up arithmetic and counters and make them more efficient. Most importantly, the function generators can be used as user RAM with asynchronous or synchronous write addressing, even as dual-port RAMs. This capability makes register files, shift registers and especially FIFOs faster and much more efficient than in any other FPGA. Logic speed is not as fast as XC3100, but dedicated carry logic can speed up wide arithmetic and long counters even above XC3100 speed. * XC3100: Superseded Don't use this family for new designs, since it has been superseded by the improved, but fully backwards compatible XC3100A family. Use for high performance design with system clock rates up to 100 MHz. Accept lack of dedicated carry circuits, resulting in less efficient and possibly slower arithmetic and counters than in XC4000E. No on-chip RAM; data storage is thus limited to the available 256 to 1,320 flip-flops. * Use for general-purpose logic and data-path logic that can take advantage of internal busses and fast arithmetic carry logic. Use for on-chip distributed RAMs, e.g. 50-MHz FIFOs up to 64 deep, 32 bits wide. Accept lack of crystal oscillator circuitry and lack of Powerdown feature. June 1, 1996 (Version 1.0) XC4000EX: Larger version of the XC4000E family, largest devices made by Xilinx Extension of the XC4000E family from 28k to 125k gates, with greatly increased routing resources, faster clocking options and more versatile output logic. * Use for designs beyond 20,000 gate complexity. XC4000H: High I/O version of XC4000, not recommended for new designs Variations of XC4003 and XC4005, with significantly increased number of I/Os. Internal functionality identical to XC4003 and XC4005, but number of I/Os increased from 80 to 160 for XC4003H, from 112 to 192 for XC4005H. No input or output flip-flops in the IOBs, but 24 mA sink current and sophisticated slew-rate control that can minimize ground bounce. * * Used for I/O-intensive applications, but also consider XC5200 as a lower-cost alternative when internal RAM is not required. Accept lack of I/O flip-flops, thus larger output delay, larger uncertainty in input set-up time. XC5200: Low-cost FPGA New architecture optimized for low cost, good routability, and the ability to lock pinout while internal logic is being modified. Dedicated carry structure similar to XC4000, but no RAM. Four-input function generators avoid the XC3000 input constraints. IOBs are less rigidly coupled to the internal matrix of CLBs and interconnects, which greatly improves the flexibility of pin-locked designs. IOBs have no flip-flops. * * Use for innovative reconfigurable-processor solutions, and for general purpose solutions where fast (re)configuration is an advantage, or for registerintensive, datapath-oriented, highly structured designs. Accept product availability starting later in 1996. Antifuse-Based FPGAs (XC8100) The XC8100 family uses antifuses in a sea-of-gates architecture, with programmable interconnects physically on top of the relatively fine-grained logic blocks. Antifuses offer a one-chip non-volatile solution with a very high level of design security, i.e. protection against reverse engineering. The XC8100 family covers a very wide range of logic densities from 500 gates to 15,000 gates. The architecture uses many relatively simple blocks, and is thus closer than other FPGAs to the structure of traditional gate arrays. This architecture simplifies and speeds up logic synthesis and design compilation. * * Use XC8100 for design flexibility, for single-chip and secure applications, and for designs that need to take advantage of the easy-to-use synthesis-friendly software. Accept one-time-programmability, and the need to program devices in external programming equipment. EPROM- and FLASH-Based CPLDs (XC7300, XC9500) Performance is similar to XC3000A, but dedicated carry logic can speed up wide arithmetic and long counters. These device families are extensions of the popular PAL architecture, implementing logic as wide AND gates, ORed together, driving either a flip-flop or an output directly. The simple logic structure makes these devices easy to understand, and results in both fast design compilation and short pin-to-pin delays. Wide input gating and fast system clock rates up to 150 MHz are attractive features for state machines and complex synchronous counters. * The XC7300 CPLDs use EPROM technology. The XC5200 family offers the lowest cost per gate of all Xilinx FPGAs, whenever RAM is not required. * Use for medium-speed general-purpose logic, and for data-path logic that can take advantage of internal busses and fast arithmetic carry logic. Alternative to XC3000A at lower cost, and with additional benefits, such as dedicated carry for arithmetic and counters, improved routing, and ability to cope with locked pinout. High I/O count. Package pinout compatible with XC4000. Accept lack of internal RAM and lack of crystal oscillator circuitry. Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) This new fine-grained architecture is very different from the other Xilinx families. It offers partial and very fast reconfigurability, supported by an 8/16/32 bit wide microprocessor bus interface. This interface can directly write to and read from any internal cell, and can even treat part of the internal configuration as user RAM. June 1, 1996 (Version 1.0) The new XC9500 in-system programmable family, based on FLASH technology, eliminates the need for a separate programmer. These new devices also offer boundary scan (JTAG) to simplify board testing. Overview of CPLD Families XC7200A: Superseded Not recommended for new designs. Use XC7300 instead. XC7300: EPROM-Based CPLD Six devices cover the range from 18 to 144 macrocells in 44- to 225-pin packages. * Use for high-speed logic, short pin-to-pin delays, for state machines and flexible address decoding, and as PAL replacement. Dedicated carry logic offers fast and efficient adders, subtractors, comparators, and counters. 14-5 Choosing a Xilinx Product Family * * Accept higher power consumption and fewer available flip-flops compared to SRAM-based or antifuse-based FPGAs. The XC7318, XC7336/Q, and XC7354 are very effective as PAL replacements. The XC7336Q boasts significantly reduced power consumption. Delays are deterministic, and compile times are very short. 3. For fast counters/adders/subtractors/accumulators/ comparators: Use XC4000E/EX, XC5200 or XC7300 for wide functions. Use XC3100A for very fast, but short or simple counters. XC4000E/EX and XC5200 have dedicated carry-logic that is most effective over the range of 8 to 32 bits. Nine devices cover the range from 36 to 576 macrocells. XC7300 has dedicated carry within a function block, and can implement unlimited carry look-ahead in the Universal Interconnect Matrix. The new XC9500 family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. XC3100A achieves high speed for short word-length and simple operations (such as non-loadable counters) through its extremely fast logic blocks. XC9500: FLASH-Based CPLD * * Use XC9500 for CPLD applications requiring fast pinto-pin speeds. Accept higher power consumption and fewer available flip-flops compared to SRAM- or antifuse-based FPGA. 4. For I/O-intensive applications with a high ratio of I/O to gates: Use XC5200. Selecting the Appropriate Xilinx Family 5. For shortest design compilation time: It is not always obvious which Xilinx family is the "right" choice for a particular application. To make a decision, start with the known data, the target application. Then address the following questions: XC9500 achieves fast compilation through the simplicity of its PAL-like architecture. * * What type of logic is used in the application? What special features are required? Type of Logic All Xilinx devices are general-purpose. Any family can implement any type of logic. There are, however, some features that make certain families more appropriate than others. The following items should be interpreted as "soft" suggestions, not as absolute, unequivocal choices. 1. For shortest pin-to-pin delays and fastest flip- flops: Use XC9500, XC7300, or, if fan-in is sufficient, XC3100A, XC4000E/EX. XC9500 and XC7300 CPLDs have a PAL-like AND/OR structure that is inherently very fast. XC3100 has extremely fast logic blocks, but the single-level fan-in is limited to five. XC4000E/EX have slower logic blocks, but a wider fan-in of nine. XC4000EX FPGAs offer a very fast pin-to-pin path using a FastClk buffer and a 2-input function generator in the IOB. 2. For fastest state machines: For encoded state machines, use XC9500, XC7300. For "one-hot" state machines, use XC3100, XC4000E/EX, XC5200. 14-6 Use XC9500, XC6200 or XC8100. XC8100 and XC6200 achieve fast compilation through their ASIC-like small granularity, which requires no logic partitioning effort. 6. For lowest cost per gate, when on-chip RAM is not required: Use XC5200, XC8100, XC3000A (XC2000 for small devices in high volume). 7. For pinout compatibility within and between families: Use XC4000E/EX, XC5200, XC8100. These three families are carefully designed to fit the same pinout in any given available package. This allows easy migration to different device sizes or families in the same package. The user can add logic or streamline the design or even use a less costly or faster family without any need to change the existing PC-board layout. 8. For Digital Signal Processing (multiply-accumulate) applications: Use XC4000E/EX. The look-up-table architecture and the dedicated carry structure are very efficient for distributed arithmetic, a fast and effective way to implement fixed-point multiplication in digital filters. Special Features Required The sixteen items below describe specific features and characteristics available only in the listed families. These are, therefore, "hard" selection criteria. June 1, 1996 (Version 1.0) 9. For on-chip RAM: Use XC4000E, XC4000EX, or XC6200. XC4000E/EX has many 16x1 or 32x1 RAMs with synchronous or asynchronous write and dual-port capability. XC6200 can implement an arbitrary portion of the configuration-memory space as user RAM. 10. For on-chip (bidirectional) bussing: Use XC3000A, XC3100A, XC4000E, XC4000EX, XC5200, XC7300, XC9500, XC8100 (i.e., use any Xilinx family except XC2000). 15. For avoiding pin-locking problems with routingintensive designs: Use XC9500, XC7300, XC4000EX, XC5200, XC8100. XC9500 and XC7300 have special architectural features to enable pin locking. XC4000EX and XC5200 provide additional routing channels, called VersaRing, between the core logic and the I/O. XC8100 has very generous routing resources that eliminate most pin-locking problems. 16. For Boundary-Scan support: XC3000A, XC3100A, XC4000, and XC5200 families have horizontal Longlines that can be driven by internal 3-state drivers. Use XC4000E, XC4000EX, XC5200, XC8100, XC9500. XC9500 and XC7300 devices implement busses indirectly using the wired-AND capability in the switch matrix. Use XC2000, XC3000A, XC3100A, XC4000H, XC4000E, XC4000EX, XC5200, XC6200, XC8100. XC8100 uses internal 3-state drivers on arbitrarily defined interconnects. (In XC4000H/E/EX, rail-to-rail is a user-option.) 11. For on-chip crystal oscillator circuitry: Use XC2000/L, XC3000A/L, XC3100A/L. The on-chip circuit is just a dedicated single-stage inverting amplifier that can be configured between two dedicated pins. It is not recommended for designs requiring very low power consumption or crystal frequencies below 1 MHz. 12. For very fast or partial reconfiguration, and for a dedicated microprocessor interface: Use XC6200. All other SRAM-based families must be completely reconfigured. 13. For non-volatile single-chip solutions: Use XC9500, XC7300, XC8100 or any HardWire device. The SRAM-based devices require an external configuration source, which may be contained in the microprocessor's memory. XC3000A and XC3000L devices can be used with a battery-backed-up supply, thus eliminating the need for external configuration storage. 14. For lowest possible static power consumption at 5V: 17. For rail-to-rail output voltage swing at 5 V Vcc: XC4000, XC7300, and XC9500 have a "totem-pole" output structure with lower Voh. XC4000E/EX can be configured with a global choice of either totem-pole or rail-to-rail outputs. XC4000H has this option per individual pin. 18. For 3.3-V operation: Use XC2000L, XC3000L, XC4000L, XC4000XL, XC8100. 19. For 5-V operation Interfacing with 3.3-V devices: Use XC9500, XC7300 or XC4000E/EX. Any XC4000E/EX "totem-pole" output drives 3.3-V inputs safely, and the TTL-like input threshold can be driven from 3.3-V logic. 20. For In-system programmability: Use all Xilinx families except XC7300 and XC8100. 21. For PCl compatibility: Use XC4000E/EX and XC9500. Target and Initiator designs are available for the XC4000E. XC3100 and XC7300 can implement target-only interfaces. Use XC2000, XC3000A, XC8100 and, to a lesser extent, XC5200, XC4000E, XC4000EX. 22. For Hi-Rel, military, or mil temperature-range applications: For Icc down to a few microamps, use XC2000/L or XC3000A/L in powerdown. The other families consume a few milliamps. Use XC2018, XC3000, XC3100A, XC4003A, XC4005, XC4010, XC4013. Configurations for CMOS input thresholds on all inputs reduce supply current significantly. 23. For battery-operated applications requiring low stand-by current: Use XC2000/L, XC3000A/L, XC4000E/EX, XC5200, XC6200, XC8100. June 1, 1996 (Version 1.0) 14-7 Choosing a Xilinx Product Family XC2000L and XC3000L have inherently very low static power consumption. 24. For best protection against Illegal copying of a design (design security): XC2000 and XC3000A can use powerdown to ignore all input activity and tolerate Vcc down to 2.3 V, while maintaining configuration. Use XC8100, XC7300, XC9500 with security bit activated. Use XC2000, XC2000L, XC3000A, XC3000L with powerdown battery-backed-up configuration. XC4000E/EX and XC8100 must be configured for CMOS input thresholds, and must shut down clock and logic activities externally. Further Information For further information on any of the Xilinx products discussed in this application note, see the Xilinx WEBLINX at http://www.xilinx.com, or call your local sales office. Table 1: Selecting a Xilinx Family XC3000 Feature 1. Shortest pin-to-pin 2. Fastest state machines 3. Fastest arithmetic counters 4. High I/O to gate ratio 5. Fastest compilation 6. Lowest cost, no RAM 7. Footprint compatible families 8. DSP (multiply/accumulate) 9. RAM 10. Bidirectional busses 11. Crystal oscillator 12. Fast/partial configuration 13. Non-volatile/single chip 14. Low power @ 5 V 15. Tolerates pin-locking 16. Boundary scan 17. Full-swing 5 V output 18. 3.3 V operation 19. 5 V out drives 3.3 V 20. In-system programmable 21. PCI-compatible 22. Hi-rel, mil, mil-temp 23. Low standby current 24. Design security 14-8 A L XC3100 A L X X X XC4000 E L X X X EX XL X X XC XC XC XC XC 5200 6200 8100 7300 9500 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X option X X X X X X X X X X X X X X X X X X option X option X X X X X X X X X X X X X X X X option X X X X X X X X X June 1, 1996 (Version 1.0) XC4000 Series Technical Information June 1, 1996 (Version 1.0) Application Note Summary This Application Note contains additional information that may be of use when designing with XC4000 Series devices. This information supplements the product descriptions and specifications, and is provided for guidance only. Xilinx Family XC4000/XC4000A/XC4000H/XC4000E/XC4000L Introduction This application note describes the electrical characteristics of the output drivers, their static output characteristics or I/V curves, the additional delay caused by capacitive loading, and the ground bounce created when many outputs switch simultaneously. Voltage/Current Characteristics of XC4000-Family Outputs Figures 1 and 2 show the output source and sink currents, both drawn as absolute values. Note that the XC4000E/EX families offer a configuration choice between an n-channel only, totem-pole like output structure that pulls a High output to a voltage level that is one threshold drop lower than VCC, and a conventional complementary output with a p-channel transistor pulling to the positive supply rail. When driving inputs that have a 1.4-V threshold, the lower VOH of the totem-pole ("TTL") output offers faster speed and more symmetrical switching delays. These curves represent typical devices. Measurements were taken at VCC= 5 V, T = 25C. These characteristics vary by manufacturing lot, and will be affected by future changes in minimum device geometries. These characteristics are not production-tested as part of the normal device test procedure; they can, therefore, not be guaranteed. Although these measurements show that the output sink and source capability far exceeds the guaranteed data sheet limits, continuous high-current operation beyond the data sheet limits can cause metal migration of the on-chip metal traces, permanently damaging the device. Output currents in excess of the data-sheet limits are, therefore, not recommended for continuous operation. These output characteristics can, however, be used to calculate or model output transient behavior, especially when driving transmission lines or large capacitive loads. 200 200 180 180 160 160 140 140 IOL 120 120 mA 100 mA 100 80 80 IOH 40 CMOS 40 TTL 20 0 IOL 60 60 1 2 Volts 3 4 5 X5291 Figure 1: Output Voltage/Current Characteristics for XC4000E June 1, 1996 (Version 1.0) IOH 20 0 1 2 Volts 3 4 5 X5292 Figure 2: Output Voltage/Current Characteristics for XC4000L 14-9 XC4000 Series Technical Information Additional Output Delays When Driving Capacitive Load Ground Bounce in XC4000 Devices Xilinx Product Specifications in chapter 4 give guaranteed worst-case output delays with a 50-pF load. The values below are based on actual measurements on a small number of mid-93 production XC4005-5, all in PQ208 packages, measured at room temperature and VCC = 5.5 V. Listed is the additional output delay, measured crossing 1.5 V, relative to the delays specified in this Data Book. These parameters are not part of the normal production test flow, and can, therefore, not be guaranteed. Table 1: Increase in Output Delay When Driving Light Capacitive Loads (<150 pF) XC4000 Note: Slew Mode Slow Fast High-to-Low Low-to-High 10 50 100 10 -1.6 -1.6 0* 0* 1.4 -1.4 1.2 -1.2 50 100 pF 0* 0* 1.4 1.1 ns ns *Zero by definition Table 2: Increase in Output Delay When Driving Heavy Capacitive Loads (>150 pF) Slew Mode XC4000 Slow Fast High-toLow 1.7 1.5 Low-toHigh 1.2 1.2 ns/100 pF ns/100 pF T High-to-Low for XC4005-5 with Fast-mode output driving 250 pF: 1.2 ns (from Table 1) plus (250-100) pF * 1.5 ns/100 pF = 1.2 ns + 2.25 ns = 3.45 ns TOKPOF + 3.45 ns = 7.0 ns + 3.45 ns = 10.45 ns VCC bounce is not as important as ground bounce, because it is of lower magnitude due to the weaker pull-up transistors. Also, the noise immunity in the High state is usually better than in the Low state, and input levels are referenced to ground, not VCC. All this is the result of our industry's TTL heritage. Test Method Example: Total propagation delay, clock to pad: Ground-bounce is a problem with high-speed digital ICs, when multiple outputs change state simultaneously causing undesired transient behavior on an output, or in the internal logic. This is also referred to as the Simultaneous Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metallization. The ICinternal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects outputs that are supposed to be stable Low, and it also affects all inputs since they interpret the incoming level by referencing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input will be interpreted as a short pulse with a polarity opposite to the ground bounce. Data was taken on XC4005-5, devices in the PQ208 package, soldered to the Xilinx Ground Bounce Test Board. Pin 82, two pins away from the nearest ground pin, was configured as a permanently Low output driver, effectively monitoring the internal ground level. The simultaneously switching outputs were on pins 80 and 83, for two outputs switching; additionally, pins 80 and 86 were used for four outputs switching. The closest ground pins are 79 and 90. Four ground-bounce parameters were measured at room temperature, with Vcc set at 5.5 V as shown in Figure 3. * VOLP-HLPeak ground noise when switching High-to-Low * VOLV-HLValley ground noise when switching High-to-Low * VOLP-LHPeak ground noise switching Low-to-High * VOLV-LHValley ground noise switching Low-to-High All four parameters can affect system reliability. VOH VOH Switching Outputs VOL VOLP-HL VOL VOLP-LH Non-Switching Active-Low Output VOL VOLV-HL VOLV-LH X5299 Figure 3: Ground Bounce 14-10 June 1, 1996 (Version 1.0) The two positive peak values can cause problems with a signal leaving the ground bounce chip, driving another chip. The positive ground bounce voltage is added to the VOL, and may exceed the receiving input's noise margin. A continuously logic Low input may thus be interpreted as a short-duration High pulse. The two negative valley parameters can cause problems with a signal arriving at the ground-bounce chip, reducing the Low-level noise immunity. The incoming voltage may not be Low enough, and may, therefore, be interpreted as a short-duration High input pulse. Table 3: Ground Bounce, 16 Outputs Switching, Each With 50 or 150 pF Load, VCC = 5.5 V Load 16 x 50 pF 16 x 150 pF Slew Rate Slow Fast Slow Fast High-to-Low VOLP VOLV 670 480 1,170 710 740 330 1,180 420 Low-to-High VOLP VOLV 240 240 480 660 210 280 350 710 Unit mV mV mV mV the slew-rate mode of these outputs. Switching outputs closer to the monitoring output also cause larger peaks and valleys than outputs further away. Guidelines for Reducing Ground-Bounce Effects * * * * * Interpretation of the Results Ground bounce is a linear phenomenon. When multiple outputs switch, the total ground bounce is the sum of the ground-bounce values caused by individual outputs switching. Since the actual switching of multiple outputs is usually not quite simultaneous, small timing differences between the switching outputs, caused by routing delays, can indirectly affect the amplitude. With low capacitive loading, < 50 pF, the peaks and valleys might even partially cancel each other. With larger capacitive loads, the tendency is for valleys to combine with valleys and peaks to combine with peaks. * Minimize the impedance of the system ground distribution network and its connection to the IC pins. PQFPs are best suited, PGAs are worst, and PLCCs are in-between. Use PC-boards with ground- and VCC-planes, connected directly to the ICs' supply pins. Place decoupling capacitors very close to these ground and VCC pins. Keep the ground plane as undisturbed as possible. A row of vias can easily cause a dynamic ground-voltage drop. Keep the clock inputs physically away from the outputs that create ground bounce, and connect clocks to input pins that are close to a ground pin. Make sure that all clock and asynchronous inputs have ample noise margin, especially in the Low state. If possible, avoid simultaneous switching by staggering output delays, e.g. through additional local routing of signals or clocks. Spread simultaneously switching outputs around the IC periphery. For a 16-bit bus, use two outputs each on either side of four ground pins. Ground-Bounce vs Delay Trade-Off After the external sources of ground bounce have been reduced or eliminated. the designer can trade reduced ground bounce for additional delay by selecting between families and slew-rate options. Figure 4 shows the trade-off for 16 outputs switching simultaneously High-to-Low. In most devices tested, the load capacitance does not directly affect the ground-bounce amplitude, but it does affect the duration of the ground-bounce signals. With a 50 pF load on the switching outputs, the ground bounce resonant frequency is 90 MHz, with a half-cycle time of 5 ns, staying 1.7 ns above 90% of peak amplitude. With a 150 pF load on the switching outputs, the ground bounce resonant frequency is 40 to 60 MHz, with a halfcycle time of 8 to 12 ns, staying 3 ns above 90% of peak amplitude. The main problem with large load capacitances is not an increase in amplitude, but rather an increase in duration of the ground-bounce signal. The amplitude is mainly affected by the number of outputs switching simultaneously, and by June 1, 1996 (Version 1.0) 1800 1600 Ground-Bounce Voltage (mV) On the fastest outputs, minimal load capacitance created a ground-bounce resonant frequency of 340 MHz, with a half-cycle time of 1.5 ns. Such a signal exceeds 90% of its peak amplitude for about 0.4 ns. FAST SLEW RATE 16 x 50 pF 16 x 150 pF 1400 1200 1000 SLOW SLEW RATE 16 x 150 pF 16 x 50 pF 800 600 400 200 0 2 3 4 5 Additional 6 Delay (ns) X5981 Figure 4: Ground-Bounce vs. Delay Trade-off for 16 Outputs Switching 50 and 150 pF Each 14-11 XC4000 Series Technical Information XC4000 and XC4000E Power Consumption Below are the dynamic power consumption values for typical design elements in XC4000 and XC4000E. The following elements are obviously device-size dependent: * One Global Clock driving all CLB flip-flops, but no flipflop changing: in XC4005: 4 mW/MTps = 8 mW/MHz in XC4010: 8 mW/MTps = 16 mW/MHz in XC4013: 12 mW/MTps = 24 mW/MHz in XC4020: 16 mW/MTps = 32 mW/MHz in XC4025: 20 mW/MTps = 40 mW/MHz * One full-length horizontal or vertical Longline with one driving CLB source and one driven CLB load: in XC4005: 0.10 mW/MHz = 0.20 mW/MHz in XC4010: 0.15 mW/MTps = 0.30 mW/MHz in XC4013: 0.18 mW/MTps = 0.36 mW/MHz in XC4020: 0.20 mW/MTps = 0.40 mW/MHz in XC4025: 0.24 mW/MTps = 0.48 mW/MHz The differences between XC4000 and XC4000E are too small to be statistically relevant: Global clocks in XC4000E are 3% higher, and Longlines and unloaded outputs in XC4000E are 5 to 10% lower than in XC4000. Power consumption is given at nominal 5.0-V supply and 25C. Power is proportional to the square of the supply voltage, but is almost constant over temperature changes. Power is given as "mW per million transitions per second", since the more commonly used "MHz" can be ambiguous. When a 10-MHz clock toggles a flip-flop, the clock line obviously makes 20 MTps, the flip-flop output only 10 MTps. The first six elements are device-size independent, i.e. they are applicable to all XC4000 or XC4000E devices operating at 5-V Vcc. * One CLB flip-flop driving nothing but a neighboring flipflop in the same or adjacent CLB (a typical shift register design): 0.1 mW per million transitions per second = 0.1 mW/MTps These numbers do not account for the 10 mA of static power consumption when all device inputs are configured in TTL mode, which is always the default mode, and in XC4000 is actually the only user-accessible mode. These numbers assume short rise and fall times on all inputs, avoiding the cross-current when both the n-channel pull-down and the p-channel pull-up transistor in the input buffer might conduct simultaneously. Tutorial Comments: In its pure form, a CMOS output driving a capacitive load has a power consumption that is independent of drive impedance or rise and fall time. For a full-swing signal, the power consumed when charging the capacitor is C x V2 x f where f is the frequency of charge operations. In each charge operation, half the total energy consumed ends up on the capacitor, and the other half of the energy is dissipated in the current-limiting resistor or transistor, whatever its value may be. * One CLB flip-flop driving its neighbor plus 9 lines of interconnect: 0.2 mW per million transitions per second = 0.2 mW/MTps * One unloaded or unbonded TTL-level output: 0.25 mW per million transitions per second = 0.25 mW/MTps * 50 pF on a TTL-level output: add 0.5 mW/MTps = 1.0 mW/MHz The subsequent discharge cycle does not take any new energy from the power supply, but dissipates in the currentlimiting resistor/transistor all the energy that was formerly stored in the capacitor. * One unloaded or unbonded XC4000E CMOS-level output: 0.31 mW per million transitions per second = 0.31 mW/MTps It is assumed here that the frequency is low enough so that the capacitors are completely charged and discharged in each half-cycle. * 50 pF on a CMOS-level output: add 0.625 mW/MTps = 1.25 mW/MHz 14-12 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) XC3000 Series Technical Information Application Note By Peter Alfke and Bernie New Summary This Application Note contains additional information that may be of use when designing with the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for guidance only. Xilinx Family XC3000/XC3000A/XC3000L/XC3100/XC3100A/XC3100L Contents Configurable Logic Blocks CLBs Function Generators Flip-flops Longline Access IOBs Inputs Outputs Routing Horizontal Longlines Bus contention Vertical Longlines Vertical Longlines Clock Buffers Vertical Longlines Clock Buffers Power Dissipation Crystal Oscillator CCLK Frequency Stability and Low-time restriction Powerdown and Battery-Backup Configuration and Start-Up Reset Beware of slow rise-time The XC3000/XC3100 CLB, shown in Figure 1, contains a combinatorial function generator and two D-type flip-flops. Two output pins may be driven by either the function generators or the flip-flops. The flip-flop outputs may be routed directly back to the function generator inputs without going outside of the CLB. Introduction The background information provided in this Application Note supplements the XC3000, XC3000A, XC3000L, XC3100A and XC3100L data sheets. It covers a wide range of topics, including a number of electrical parameters not specified in the data sheets, and unless otherwise noted, applies to all six families. These additional parameters are sufficiently accurate for most design purposes; unlike the parameters specified in the data sheets, however, they are not worst-case values over temperature and voltage, and are not 100% production tested. They can, therefore, not be guaranteed. June 1, 1996 (Version 1.0) The function generator consists of two 4-input look-up tables that may be used separately or combined into a single function. Figure 2 shows the three available options. Since the CLB only has five inputs to the function generator, inputs must be shared between the two look-up tables. In the FG mode, the function generator provides any two 4input functions of A, B and C plus D or E; the choice between D and E is made separately for each function. In the F mode, all five inputs are combined into a single 5input function of A, B, C, D and E. Any 5-input function may be emulated. The FGM mode is a superset of the F mode, where two 4-input functions of A, B, C and D are multiplexed together according to the fifth variable, E. In all modes, either of the B and C inputs may be selectively replaced by QX and QY, the flip-flop outputs. In the FG mode, this selection is made separately for the two look-up tables, extending the functionality to any two functions of four variables chosen from seven, provided two of the variables are stored in the flip-flops. This is particularly useful in state-machine-like applications. In the F mode, the function generators implement a single function of five variables that may be chosen from seven, as described above. The selection of QX and QY is constrained to be the same for both look-up tables. The FGM mode differs from the F mode in that QX and QY may be selected separately for the two look-up tables, as in the FG mode. This added flexibility permits the emulation of selected functions that can include all seven possible inputs. 14-13 XC3000 Series Technical Information Data In DI F DIN G Logic Variables A B C D E 0 MUX 1 D Q QX RD QX X F F G G Combinatorial Function CLB Outputs Y QY F DIN G Enable Clock QY 0 MUX 1 D Q EC RD 1 (Enable) Clock Reset Direct K RD Figure 1: Configurable Logic Block (CLB) 0 (Inhibit) (Global Reset) X3217 Function Generator Avoids Glitches The combinatorial logic in all CLBs is implemented as a function generator in the form of a multiplexer, built out of transfer gates. The logic inputs form the select inputs to this multiplexer, while the configuration bits drive the data inputs to the multiplexer. The Xilinx circuit designers were very careful to achieve a balanced design with similar (almost equal) propagation delays from the various select inputs to the data output. The delay from the data inputs to the output is, of course, immaterial, since the data inputs do not change dynamically. They are only affected by configuration. This balanced design minimizes the duration of possible decoding glitches when more than one select input changes. Note that there can never be a decoding glitch when only one select input changes. Even a non-overlapping decoder cannot generate a glitch problem, since the node capacitance will retain the previous logic level until the new transfer gate is activated about a nanosecond later. When more than one input changes "simultaneously," the user should analyze the logic output for any possible intermediate code. If any such code permutation produces a different result, the user must assume that such a glitch might occur and must make the system design immune to it. The glitch might be only a few nanoseconds long, but that is long enough to upset an asynchronous design. If none of the possible address sequences produces a different result, the user can be sure that there will be no glitch. The designer of synchronous systems generally doesn't worry about such glitches, since synchronous designs are fundamentally immune to glitches on all signals except clocks or direct SET/RESET inputs. 14-14 A B QX QY Any Function of Up To 4 Variables F QY Any Function of Up To 4 Variables G C D E A B QX C D E 2a FG Mode 2b F Mode A B QX F QY Any Function of 5 Variables C D E G A B QX QY Any Function of Up To 4 Variables C D F M U X A B QX QY G Any Function of Up To 4 Variables C D E 2c FGM Mode X3218 Figure 2: CLB Logic Options June 1, 1996 (Version 1.0) The automatic logic-partitioning software in the XACTstep development system only uses the FG and F modes. However, all three modes are available with manual partitioning, which may be performed in the schematic. If FG or F modes are required, it is simply a matter of including in the schematic CLBMAP symbols that define the inputs and outputs of the CLB. Input/Output Blocks The FGM mode is only slightly more complicated. Again, a CLBMAP must be used, with the signal that multiplexes between the two 4-input functions locked onto the E pin. The CLB will be configured in the FGM mode if the logic is drawn such that the gates forming the multiplexer are shown explicitly with no additional logic merged into them. The IOB input may also be direct or registered. Additionally, the input flip-flop may be configured as a latch. When an IOB is used exclusively as an input, an optional pull-up resistor is available, the value of which is 40-150 k. This resistor cannot be used when the IOB is configured as an output or as a bidirectional pin. The two D-type flip-flops share a common clock, a common clock enable, and a common asynchronous reset signal. An asynchronous preset can be achieved using the asynchronous reset if data is stored in active-low form; the Low created by reset corresponds to the bit being asserted. The flip-flops cannot be used as latches. Unused IOBs should be left unconfigured. They default to inputs pulled High with the internal resistor. If input data to a CLB flip-flop is derived directly from an input pad, without an intervening flip-flop, the data-pad-toclock-pad hold time will typically be non-zero. This hold time is equal the delay from the clock pad to the CLB, but may be reduced according to the 70% rule, described later in the IOB Input section of this Application Note. Under this rule, the hold time is reduced by 70% of the delay from the data pad to the CLB, excluding the CLB set-up time. The minimum hold time is zero, even when applying the 70% rule results in a negative number. The CLB pins to which Longlines have direct access are shown in Table 1. Note that the clock enable pin (EC) and the TBUF control pin are both driven from to the same vertical Long Line. Consequently, EC cannot easily be used to enable a register that must be 3-stated onto a bus. Similarly, EC cannot easily be used in a register that uses the Reset Direct pin (RD). Table 1: Longline to CLB Direct Access Longline Left Most Vertical (GCLK) Left Middle Vertical CLB TBUF A B C D E K EC RD X T X X X X Right Most Vertical (ACLK) Upper Horizontal Lower Horizontal X X Right Middle Vertical X X June 1, 1996 (Version 1.0) X X The XC3000/XC3100 IOB, shown in Figure 3, includes a 3state output driver that may be driven directly or registered. The polarities of both the output data and the 3-state control are determined by configuration bits. Each output buffer may be configured to have either a fast or a slow slew rate. Inputs All inputs have limited hysteresis, typically in excess of 200 mV for TTL input thresholds and in excess of 100 mV for CMOS thresholds. Exceptions to this are the PWRDWN pin, and the XTL2 pin when it is configured as the crystal oscillator input. Experiments show that the input rise and fall times should not exceed 250 ns. This value was established through a worst-case test using internal ring oscillators to drive all I/O pins except two, thus generating a maximum of on-chip noise. One of the remaining I/O pins was configured as an input, and tested for single-edge response; the other I/O was used as an output to monitor the response. These test conditions are, perhaps, overly demanding, although it was assumed that the PC board had negligible ground noise and good power-supply decoupling. While conservative, the resulting specification is, in most instances, easily satisfied. IOB input flip-flops are guaranteed to operate correctly without data hold times (with respect to the device clockinput pad) provided that the dedicated CMOS clock input pad and the GCLK buffer are used. The use of a TTL clock or a different clock pad will result in a data-hold-time requirement. The length of this hold time is equal to the delay from the actual clock pad to the GCLK buffer minus the delay from the dedicated CMOS clock pad to the GCLK buffer. To ensure that the input flip-flop has a zero hold time, delay is incorporated in the D input of the flip-flop, causing it to have a relatively long set-up time. However, the set-up time specified in the data sheet is with respect to the clock reaching the IOB. Since there is an unavoidable delay between the clock pad and the IOB, the input-pad-to-clockpad set-up time is actually less than the data sheet number. 14-15 XC3000 Series Technical Information Program-Controlled Memory Cells Out Invert 3-State (OUTPUT ENABLE) Out Output Select 3-State Invert VCC Slew Rate Passive Pull Up T O D Q Output Buffer FlipFlop I/O Pad R Direct In Registered In I Q Q D FlipFlop or Latch TTL or CMOS Input Threshold R OK (Global Reset) IK CK1 CK2 Program Controlled Multiplexer = Programmable Interconnection Point or PIP X3216 Figure 3: Input/Output Block (IOB) Part of the clock delay can be subtracted from the internal set-up time. Ideally, all of the clock delay could be subtracted, but it is possible for the clock delay to be less than its maximum while the internal set-up time is at its maximum value. Consequently, it is recommended that, in a worst-case design, only 70% of the clock delay is subtracted. The clock delay can only be less than 70% of its maximum if the internal set-up time requirement is also less than its maximum. In this case, the pad-to-pad set-up time actually required will be less than that calculated. For example, in the XC3000-125, the input set-up time with respect to the clock reaching the IOB is 16 ns. If the delay from the clock pad to the IOB is 6 ns, then 70% of this delay, 4.2 ns, can be subtracted to arrive at a maximum pad-topad set-up time of ~12 ns. The 70% rule must be applied whenever one delay is subtracted from another. However, it is recommended that delay compensation only be used routinely in connection with input hold times. Delay compensation in asynchronous circuits is specifically not recommended. In any case, the compensated delay must not become negative. If 70% of the compensating delay is greater than the delay from which it is deducted, the resulting delay is zero. 14-16 The 70% rule in no way defines the absolute minimum values delays that might be encountered from chip to chip, and with temperature and power-supply variations. It simply indicates the relative variations that might be found within a specific chip over the range of operating conditions. Typically, all delays will be less than their maximum, with some delays being disproportionately faster than others. The 70% rule describes the spread in the scaling factors; the delay that decreases the most will be no less than 70% of what it would have been if it had scaled in proportion to the delay that decreased the least. In particular, in a worstcase design where it is assumed that any delay might not have scaled at all, and remains at its maximum value, other delays will be no less than 70% of their maximum. Outputs All XC3000/XC3100 FPGA outputs are true CMOS with nchannel transistors pulling down and p-channel transistors pulling up. Unloaded, these outputs pull rail-to-rail. Some additional ac characteristics of the output are listed in Table 2. Figure 4 and Figure 5 show output current/voltage curves for typical XC3000 and XC3100 devices. Output-short-circuit-current values are given only to indicate the capability to charge and discharge capacitive June 1, 1996 (Version 1.0) IOB latches have active-Low Latch Enables; they are transparent when the clock input is Low and are closed when it is High. The latch captures data on what would otherwise be the active clock edge, and is transparent in the half clock period before the active clock edge. 200 180 160 140 120 Routing IOL mA 100 Horizontal Longlines 80 60 IOH 40 20 0 1 2 Volts 3 4 5 X5294 Figure 4: Output Current/Voltage Characteristics for XC3000, XC3000A, XC3100 and XC3100A Devices As shown in Table 3, there are two horizontal Longlines (HLLs) per row of CLBs. Each HLL is driven by one TBUF for each column of CLBs, plus an additional TBUF at the left end of the Longline. This additional TBUF is convenient for driving IOB data onto the Longline. In general, the routing resources to the T and I pins of TBUFs are somewhat limited. Table 3: Number of Horizontal Longlines loads. In accordance with common industry practice for other logic devices, only one output at a time may be short circuited, and the duration of this short circuit to VCC or ground may not exceed one second. Xilinx does not recommend a continuous output or clamp current in excess of 20 mA on any one output pin. The data sheet guarantees the outputs for no more than 4 mA at 320 mV to avoid problems when many outputs are sinking current simultaneously. The active-High 3-state control (T) is the same as an active-Low output enable (OE). In other words, a High on the T-pin of an OBUFZ places the output in a high impedance state, and a Low enables the output. The same naming convention is used for TBUFs within the FPGA device. I/O Clocks Internally, up to eight distinct I/O clocks can be used, two on each of the four edges of the die. While the IOB does not provide programmable clock polarity, the two clock lines serving an IOB can be used for true and inverted clock, and the appropriate polarity connected to the IOB. This does, however, limit all IOBs on that edge of the die to using only the two edges of the one clock. Table 2: Additional AC Output Characteristics AC Parameters Unloaded Output Slew Rate Unloaded Transition Time Additional rise time for 812 pF normalized Additional fall time for 812 pF normalized Fast* 2.8 V/ns 1.45 ns 100 ns 0.12 ns/pF 50 ns 0.06 ns/pF Slow* 0.5 V/ns 7.9 ns 100 ns 0.12 ns/pF 64 ns 0.08 ns/pF * Fast and Slow refer to the output programming option. June 1, 1996 (Version 1.0) Part Name Rows x Columns CLBs Horizontal Longlines TBUFs per HLL XC3020 XC3030 XC3042 XC3064 XC3090 XC3195 8x8 10 x 10 12 x 12 16 x 14 20 x 16 22 x 22 64 100 144 224 320 484 16 20 24 32 40 44 9 11 13 15 17 23 Optionally, HLLs can be pulled up at either end, or at both ends. The value of each pull-up resistor is 3-10 k. In addition, HLLs are permanently driven by low-powered latches that are easily overridden by active outputs or pullup resistors. These latches maintain the logic levels on HLLs that are not pulled up and temporarily are not driven. The logic level maintained is the last level actively driven onto the line. When using 3-state HLLs for multiplexing, the use of fewer than four TBUFs can waste resources. Multiplexers with four or fewer inputs can be implemented more efficiently using CLBs. Internal Bus Contention XC3000 and XC4000 Series devices have internal 3-state bus drivers (TBUFs). As in any other bus design, such bus drivers must be enabled carefully in order to avoid, or at least minimize, bus contention. (Bus contention means that one driver tries to drive the bus High while a second driver tries to drive it Low). Since the potential overlap of the enable signals is lay-out dependent, bus contention is the responsibility of the FPGA user. We can only supply the following information: While two internal buffers drive conflicting data, they create a current path of typically 6 mA. This current is tolerable, but should not last indefinitely, since it exceeds our (conservative) current density rules. A continuous contention 14-17 XC3000 Series Technical Information could, after thousands of hours, lead to metal migration problems. local interconnect should only be considered for individual flip-flops. In a typical system, 10 ns of internal bus contention at 5 MHz would just result in a slight increase in Icc. Power Dissipation 16 bits x 6 mA x 10 ns x 5 MHz x 50% probability = 2.5 mA. As in most CMOS ICs, almost all FPGA power dissipation is dynamic, and is caused by the charging and discharging of internal capacitances. Each node in the device dissipates power according to the capacitance in the node, which is fixed for each type of node, and the frequency at which the particular node is switching, which can be different from the clock frequency. The total dynamic power is the sum of the power dissipated in the individual nodes. There is a special use of the 3-state control input: When it is directly driven by the same signal that drives the data input of the buffer, i.e. when D and T are effectively tied together, the 3-state buffer becomes an "open collector" driver. Multiple drivers of this type can be used to implement the "wiredAND" function, using resistive pull-up. In this situation there cannot be any contention, since the 3state control input is designed to be slow in activating and fast in deactivating the driver. Connecting D to ground is an obvious alternative, but may be more difficult to route. Vertical Longlines There are four vertical Longlines per routing channel: two general purpose, one for the global clock net and one for the alternate clock net. Clock Buffers XC3000/XC3100 devices each contain two high-fan-out, low-skew clock-distribution networks. The global-clock net originates from the GCLK buffer in the upper left corner of the die, while the alternate clock net originates from the ACLK buffer in the lower right corner of the die. The global and alternate clock networks each have optional fast CMOS inputs, called TCLKIN and BCLKIN, respectively. Using these inputs provides the fastest path from the PC board to the internal flip-flops and latches. Since the signal bypasses the input buffer, well-defined CMOS levels must be guaranteed on these clock pins. To specify the use of TCLKIN or BCLKIN in a schematic, connect an IPAD symbol directly to the GCLK or ACLK symbol. Placing an IBUF between the IPAD and the clock buffer will prevent TCLKIN or BCLKIN from being used. The clock buffer output nets only drive CLB and IOB clock pins. They do not drive any other CLB inputs. In rare cases where a clock needs to be connected to a logic input or a device output, a signal should be tapped off the clock buffer input, and routed to the logic input. This is not possible with clocks using TCLKIN or BCLKIN. The clock skew created by routing clocks through local interconnect makes safe designs very difficult to achieve, and this practice is not recommended. In general, the fewer clocks that are used, the safer the design. High fan-out clocks should always use GCLK or ACLK. If more than two clocks are required, the ACLK net can be segmented into individual vertical lines that can be driven by PIPs at the top and bottom of each column. Clock signals routed through 14-18 While the clock line frequency is easy to specify, it is usually more difficult to estimate the average frequency of other nodes. Two extreme cases are binary counters, where half the total power is dissipated in the first flip-flop, and shift registers with alternating zeros and ones, where the whole circuit is exercised at the clocking speed. A popular assumption is that, on average, each node is exercised at 20% of the clock rate; a major EPLD vendor uses a 16-bit counter as a model, where the effective percentage is only 12%. Undoubtably, there are extreme cases, where the ratio is much lower or much higher, but 15 to 20% may be a valid approximation for most normal designs. Note that global clock lines must always be entered with their real, and obviously well-known, frequency. Consequently, most power consumption estimates only serve as guidelines based on gross approximations. Table 4 shows the dynamic power dissipation, in mW per MHz, for different types of XC3000 nodes. While not precise, these numbers are sufficiently accurate for the calculations in which they are used, and may be used for any XC3000/ XC3100 device. Table 5 shows a sample power calculation. Table 4: Dynamic Power Dissipation XC3020 XC3090 One CLB driving three local interconnects One device output with a 50 pF load One Global Clock Buffer and line One Longline without driver 0.25 0.25 mW/MHz 1.25 1.25 mW/MHz 2.00 0.10 3.50 0.15 mW/MHz mW/MHz Table 5: Sample Power Calculation for XC3020 Quantity Node MHz 1 5 10 40 8 20 Clock Buffer CLBs CLBs CLBs Longlines Outputs 40 40 20 10 20 20 mW/MHz mW 2.00 80 0.25 50 0.25 50 0.25 100 0.10 16 1.25 500 Total Power ~800 June 1, 1996 (Version 1.0) Crystal Oscillator XC3000 and XC3100 devices contain an on-chip crystal oscillator circuit that connects to the ACLK buffer. This circuit, Figure 5, comprises a high-speed, high-gain inverting amplifier with its input connected to the dedicated XTL2 pin, and its output connected to the XTL1 pin. An external biasing resistor, R1, with a value of 0.5 to 1 M is required. A crystal, Y1, and additional phase-shifting components, R2, C1 and C2, complete the circuit. The capacitors, C1 and C2, in series form the load on the crystal. This load is specified by the crystal manufacturer, and is typically 20 pF. The capacitors should be approximately equal: 40 pF each for a 20 pF crystal. Either series- or parallel-resonant crystals may be used, since they differ only in their specification. Crystals constrain oscillation to a narrow band of frequencies, the width of which is <<1% of the oscillating frequency; the exact frequency of oscillation within this band depends on the components surrounding the crystal. Series-resonant crystals are specified by their manufacturers according to the lower edge of the frequency band, parallel-resonant crystals according to the upper edge. The resistor R2 controls the loop gain and its value must be established by experimentation. If it is too small, the oscillation will be distorted; if it is too large, the oscillation will fail to start, or only start slowly. In most cases, the value of R2 is non-critical, and typically is 0 to 1 k. Once the component values have been chosen, it is good practice to test the oscillator with a resistor (~1 k) in series with the crystal. If the oscillator still starts reliably, independent of whether the power supply turns on quickly or slowly, it will always work without the resistor. For operation above 20 to 25 MHz, the crystal must be operated at its third harmonic. The capacitor C2 is replaced by a parallel-resonant LC tank circuit tuned to ~2/3 of the desired frequency, i.e., twice the fundamental frequency of the crystal. Table 6 shows typical component values for the tank circuit. XTAL_OUT XTAL_IN FPGA R1 R2 Y1 C1 C2 L 3RD Overtone Only X6128 Figure 5: Crystal Oscillator Table 6: Third-Harmonic Crystal Oscillator Tank-Circuit Frequency LC Tank (MHz) L (H) C2 (pF) Freq (MHz) R2 () C1 (pF) 32 1 60 20.6 430 23 35 1 44 24.0 310 23 49 1 31 28.6 190 23 72 1 18 37.5 150 12 Crystal-Oscillator Considerations There is nothing Xilinx-specific about the oscillator circuit. It's a wide-band inverting amplifier, as used in all popular microcontrollers. When a crystal and some passive components close the feedback path, this circuit becomes a reliable and stable clock source. The path from XTAL2 to XTAL1 inside the LCA device is a single-stage inverting amplifier, which means it has a lowfrequency phase response of 180, increasing by 45 at the 3-dB frequency. Input impedance is 10-15 pF, input threshold is CMOS, but dc bias must be supplied externally through a megohm resistor from XTAL1 to XTAL2. Low-frequency gain is about 10, rolling off 3dB at 125 MHz. Output impedance is between 50 and 100 and the capacitance on the output pin is 10 to 15 pF. Pulse response is a delay of about 1.5 ns and a rise/fall time of about 1.5 ns. June 1, 1996 (Version 1.0) 14-19 XC3000 Series Technical Information For stable oscillation, * * the loop gain must be exactly one, i.e., the internal gain must be matched by external attenuation, and the phase shift around the loop must be 360 or an integer multiple thereof. The external network must, therefore, provide 180 of phase shift. A crystal is a piezoelectric mechanical resonator that can be modeled by a very high-Q series LC circuit with a small resistor representing the energy loss. In parallel with this series-resonant circuit is unavoidable parasitic capacitance inside and outside the crystal package, and usually also discrete capacitors on the board. circuit equals the gain in the FPGA device, and where the total phase shift, internal plus external, equals 360. Figure 7 explains the function. At the frequency of oscillation, the series-resonant circuit is effectively an inductor, and the two capacitors act as a capacitive voltage divider, with the center-point grounded. This puts a virtual ground somewhere along the inductor and causes the non-driven end of the crystal to be 180 out of phase with the driven end, which is the external phase shift required for oscillation. This circuit is commonly known as a Pierce oscillator. XC2000/XC3000 The impedance as a function of frequency of this whole array starts as a small capacitor at low frequencies (Figure 6). As the frequency increases, this capacitive reactance decreases rapidly, until it reaches zero at the series resonant frequency. C L R Inductive jL XTAL Series Resonance Parallel Resonance X5321 Frequency 1 jC Figure 7: Pierce Oscillator Practical Considerations * Capacitive C L R X2818 Figure 6: Reactance as a Function of Frequency At slightly higher frequencies, the reactance is inductive, starting with a zero at series resonance, and increasing very rapidly with frequency. It reaches infinity when the effective inductive impedance of the series LC circuit equals the reactance of the parallel capacitor. The parallel resonance frequency is a fraction of a percent above the series-resonance frequency. Over this very narrow frequency range between series and parallel resonance, the crystal impedance is inductive and changes all the way from zero to infinity. The energy loss represented by the series resistor prevents the impedance from actually reaching zero and infinity, but it comes very close. Microprocessor- and FPGA-based crystal oscillators all operate in this narrow frequency band, where the crystal impedance can be any inductive value. The circuit oscillates at a frequency where the attenuation in the external 14-20 * * * The series resonance resistor is a critical parameter. To assure reliable operation with worst-case crystals, the user should experiment with a discrete series resistor roughly equal to the max internal resistance specified by the crystal vendor. If the circuit tolerates this additional loss, it should operate reliably with a worstcase crystal without the additional resistor. The two capacitors affect the frequency of oscillation and the start-up conditions. The series connection of the two capacitors is the effective capacitive load seen by the crystal, usually specified by the crystal vendor. The two capacitors also determine the minimum gain required for oscillation. If the capacitors are too small, more gain is needed, and the oscillator may be unstable. If the capacitors are too large, oscillation is stable but the required gain may again be higher. There is an optimum capacitor value, where oscillation is stable, and the required gain is at a minimum. For most crystals, this capacitive load is around 20 pF, i.e., each of the two capacitors should be around 40 pF. Crystal dissipation is usually around 1 mW, and thus of no concern. Beware of crystals with "drive-level dependence" of the series resistor. They may not start up. Proper drive level can be checked by varying Vcc. The frequency should increase slightly with an increase in Vcc. A decreasing frequency or unstable amplitude indicate an over-driven crystal. Excessive swing at the June 1, 1996 (Version 1.0) * * XTAL2 input results in clipping near Vcc and ground. An additional 1 to 2 k series resistor at the XTAL1 output usually cures that distortion problem. It increases the amplifier output impedance and assures additional phase margin, but results in slower start-up. Be especially careful when designing an oscillator that must operate near the specified max frequency. The circuit needs excess gain at small signal amplitudes to supply enough energy into the crystal for rapid start-up. High-frequency gain may be marginal, and start-up may be impaired. Keep the whole oscillator circuit physically as compact as possible, and provide a single ground connection. Grounding the crystal can is not mandatory but may improve stability. and fastest Xilinx FPGA is compatible with the oldest and slowest device ever manufactured. The CCLK frequency is fairly insensitive to changes in VCC, varying only 0.6% for a 10% change in VCC. It is, however, very temperature dependent, increasing 40% as the temperature drops from 25C to -30C, (Table 7.) Table 7: Typical CCLK Frequency Variation VCC 4.5 V 5.0 V 5.5 V 4.5 V 4.5 V Temp 25C 25C 25C -30C +130C Frequency 687 kHz 691 kHz 695 kHz 966 kHz 457 kHz CCLK Low-Time Restriction Series Resonant or Parallel Resonant? Crystal manufacturers label some crystals as seriesresonant, others as parallel-resonant, but there really is no difference between these two types of crystals, they all operate in the same way. Every crystal has a series resonance, where the impedance of the crystal is extremely low, much lower than at any other frequency. At a slightly higher frequency, the crystal is inductive and in parallel resonance with the unavoidable stray capacitance or the deliberate capacitance between its pins. The only difference between the two types of crystal is the manufacturer's choice of specifying either of the two frequencies. If series resonance is specified, the actual frequency of oscillation is a little higher than the specified value. If parallel resonance is specified, the frequency of oscillation is a little lower. In most cases, these small deviations are irrelevant. CCLK Frequency Variation The on-chip R-C oscillator that is brought out as CCLK also performs several other internal functions. It generates the power-on delay, 216 = 65,536 periods for a master, 214 = 16,384 periods for a slave or peripheral device. It generates the shift pulses for clearing the configuration array, using one clock period per frame, and it is the clock source for several small shift registers acting as low-pass filters for a variety of input signals. The nominal frequency of this oscillator is 1 MHz with a max deviation of +25% to -10%. The clock frequency, therefore, is between 1.25 MHz and 0.5 MHz. In the XC4000 family, the 1-MHz clock is derived from an internal 8-MHz clock that also can be used as CCLK source. Xilinx circuit designers make sure that the internal clock frequency does not get faster as devices are migrated to smaller geometries and faster processes. Even the newest June 1, 1996 (Version 1.0) When used as an input in Slave Serial and Readback modes, CCLK does not tolerate a Low time in excess of 5 s. For very low speed operation, the CCLK High time can be stretched to any value, but the Low time must be kept short. XC4000 and XC5200 devices do not have this restriction. Battery Back-up Since SRAM-based FPGAs are manufactured using a high-performance low-power CMOS process, they can preserve the configuration data stored in the internal static memory cells even during a loss of primary power. This is accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current requirement of VCC from a battery. Circuit techniques used in XC3100, XC4000 and XC5200 devices prevent ICC from being reduced to the level need for battery back-up. Consequently, battery back-up should only be used for XC2000, XC2000L, XC3000, XC3000A and XC3000L devices. There are two primary considerations for battery backup which must be accomplished by external circuits. * Control of the Power-Down (PWRDWN) pin * Switching between the primary VCC supply and the battery. Important considerations include the following. * Insure that PWRDWN is asserted logic Low prior to VCC falling, is held Low while the primary VCC is absent, and returned High after VCC has returned to a normal level. PWRDWN edges must not rise or fall slowly. * Insure "glitch-free" switching of the power connections to the FPGA device from the primary VCC to the battery and back. * Insure that, during normal operation, the FPGA VCC is maintained at an acceptable level, 5.0 V 5% (10% for Industrial and Military). 14-21 XC3000 Series Technical Information Figure 8 shows a power-down circuit developed by Shel Epstein of Epstein Associates, Wilmette, IL. Two Schottky diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal power monitor circuit monitors VCC and pulls PWRDWN Low whenever VCC falls below 4 V. VCC IN5817 During powerdown, the Vcc monitoring circuit is disabled. It is then up to the user to prevent Vcc dips below 2.3 V, which would corrupt the stored configuration. Seiko S8054 Specifications Detect Voltage 3.995 V min 4.305 V max 208 mV typ Hysteresis Temp. Coeff. 0.52 mV/C 2.6 A typ ICC @ + 6V 2 SEIKO 1 PWRDWN S 8054 IN5817 VCC B35 Lithium Battery FPGA 3 X5997 Figure 8: Battery Back-up Circuit Powerdown Operation A Low level on the PWRDWN input, while Vcc remains higher than 2.3 V, stops all internal activity, thus reducing Icc to a very low level: * * * * * * * All internal pull-ups (on Long lines as well as on the I/O pads) are turned off. The crystal oscillator is turned off All package outputs are three-stated. All package inputs ignore the actual input level, and present a High to the internal logic. All internal flip-flops or latches are permanently reset. The internal configuration is retained. When PWRDWN is returned High, after VCC is at its nominal value, the device returns to operation with the same sequence of buffer enable and D/P as at the completion of configuration. Things to Remember Powerdown retains the configuration, but loses all data stored in the device. Powerdown three-states all outputs and ignores all inputs. No clock signal will be recognized, and the crystal oscillator is stopped. All internal flip-flops and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully functional. Things to Watch Out For Make sure that the combination of all inputs High and all internal flip-flop outputs Low in your design will not generate internal oscillations or create permanent bus contention 14-22 by activating internal bus drivers with conflicting data onto the same Longline. These two situations are farfetched, but they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function generators. During configuration, the PWRDWN pin must be High, since configuration uses the internal oscillator. Whenever Vcc goes below 4 V, PWRDWN must already be Low in order to prevent automatic reconfiguration at low Vcc. For the same reason, Vcc must first be restored to 4 V or more, before PWRDWN can be made High. PWRDWN has no pull-up resistor. A pull-up resistor would draw supply current when the pin is Low, which would defeat the idea of powerdown, where Icc is only microamperes. Configuration and Start-up Start-Up Start-up is the transition from the configuration process to the intended user operation. This means a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic "wakes up" gracefully, that the outputs become active without causing contention with the configuration signals, and that the internal flip-flops are released from the global Reset or Set at the right time. Figure 10 describes Start-up timing for the XC3000 families in detail. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os become active one clock later. Reset is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 11, but the designer can modify it to meet particular requirements. Until the chip goes active after configuration, all I/O pins not involved in the configuration process remain in a highimpedance state with weak pull-up resistors; all internal flip-flops and latches are held reset. Multiple FPGA devices hooked up in a daisy chain will all go active simultaneously June 1, 1996 (Version 1.0) Length Count Match unasserted, but D remains High since the function generator acts as an R-S latch; Q stays Low, and RESET is still pulled High by the external resistor. On the first system clock after configuration ends, Q is clocked High, resetting the latch and enabling the output driver. which forces RESET Low. This resets the whole chip until the Low on Q permits RESET to be pulled High again. CCLK Period CCLK F DONE I/O The whole chip has thus been reset by a short pulse instigated by the system clock. No further pulses are generated, since the High on LDC prevents the R-S latch from becoming set. Global Reset X5967 Figure 9: Start-up Timing Beware of a Slow-Rising XC3000 Series RESET Input on the same CCLK edge. This is well documented in the data sheets. It is a wide-spread habit to drive asynchronous RESET inputs with a resistor-capacitor network to lengthen the reset time after power-on. This can also be done with Xilinx FPGAs, but the user should question the need, and should beware of certain avoidable problems. Not documented, however, is how the internal combinatorial logic comes alive during configuration: As configuration data is shifted in and reaches its destination, it activates the logic and also "looks at" the IOB inputs. Even the crystal oscillator starts operating as soon as it receives its configuration data. Since all flip-flops and latches are being held reset, and all outputs are being held in their high-impedance state, there is no danger in this "staggered awakening" of the internal logic. The operation of the logic prior to the end of configuration is even useful; it ensures that clock enables and output enables are correctly defined before the elements they control become active. Xilinx FPGAs contain an internal voltage-monitoring circuit, and start their internal housekeeping operation only after VCC has reached ~3.5 V. The internal housekeeping and configuration memory clearing operation then takes between about 10 and 100 ms, depending on configuration mode and processing variations. Any RC delay shorter than 40 ms for a device in master configuration mode, or shorter than 10 ms for a device in slave configuration mode, is clearly redundant. Once configuration is complete, the FPGA device is activated. This occurs on a rising edge of CCLK, when all outputs and clocks that are enabled become active simultaneously. Since the activation is triggered by CCLK, it is an asynchronous event with respect to the system clock. To avoid start-up problems caused by this asynchronism, some designs might require a reset pulse that is synchronized to the system clock. A significantly longer RC delay can be used to hold off configuration. Without the use of an external Schmitt trigger circuit, the rise time on the RESET input will be very slow, and is likely to cross the threshold of ~1.4 V several times, due to external or internal noise. This can cause the FPGA to start configuration, then immediately abort it, then start it again, after having automatically cleared the configuration memory once more. The circuit shown in Figure 10 generates a short Global Reset pulse in response to the first system clock after the end of configuration. It uses one CLB and one IOB, and also precludes the use of the LDC pin as I/O. This is no problem for the FPGA, but it requires that the source of configuration data, especially an XC1700 serial PROM, be reset accordingly. This is another reason to use the INIT output of the lead FPGA, instead of LDC, to drive the RESET input of the XC1700 serial PROMs. During Configuration, LDC is asserted Low and holds the D-input of the flip-flop High, while Q is held Low by the internal reset, and RESET is kept High by internal and external pull-up resistors. At the end of configuration, the LDC pin is VCC OE = High T = Low D Q System Clock Low CLB MR IOB RESET High LDC IOB X3222 June 1, 1996 (Version 1.0) Figure 10: Synchronous Reset 14-23 XC3000 Series Technical Information 14-24 June 1, 1996 (Version 1.0) FPGA Configuration Guidelines June 1, 1996 (Version 1.0) Application Note By PETER ALFKE Summary These guidelines describe the configuration process for XC2000, XC3000 and XC4000-Series FPGA devices. The average user need not understand all details, but should refer to the debugging hints when problems occur. The XC2000, XC3000, and XC4000 series FPGAs share a basic configuration concept, and can be combined in a common configuration bitstream, but there are small differences among the three families as described below. Following their initial power-on configuration-memory initialization, these Xilinx FPGAs are configured by a serial configuration bitstream. The byte-parallel configuration modes just activate an internal parallel-to-serial converter, and then use the serial bitstream internally. Express mode in XC4000EX operates on 8 bits in parallel. This mode is not covered in this application note. The software generates a bitstream that starts with a 40-bit header, see Figure 1. Each device uses a few of the leading 1s to prepare for configuration, then detects the 0010 pattern and stores the following 24 bits as a length-count value in an internal register. The content of this register is continuously compared against a running counter that increments on every rising CCLK edge. CCLK is either an output (in Master and Asynchronous Peripheral modes) or an input (in Slave Serial and Synchronous Peripheral modes). In all modes, it is the externally observable Low-to-High transition on the CCLK pin that causes the internal action. Every CCLK rising edge that occurs while INIT and RESET are High is counted, even during the preamble. Note that XC2000 and XC3000 use quasi-static circuitry which imposes a 5 s max limit on the CCLK Low time, while XC4000 is completely static and has no max CCLK time limit. This is, of course, only of interest in XC2000 and XC3000 Slave Serial mode, where CCLK is generated by the user. While it is permissible, although not meaningful, to modify the number of leading ones by adding additional ones, or subtracting up to four ones, this would inevitably affect the number of CCLK pulses received by the counter, and thus change the moment when the internal counter is equal to the value stored in the length-count register. Don't add or delete preamble-leading ones! 11111111 0010 (MSB) 24-Bit Length Count (LSB) 1111 Data X5553 Figure 1: 40-Bit Header June 1, 1996 (Version 1.0) Each device passes the incoming header, including the length-count value, on to the DOUT pin, delayed by half a CCLK period, i.e. the bits are clocked out on a falling CCLK edge. In this way, the header is passed on to all devices that might be connected in a daisy-chain. After the length-count data has been passed on, DOUT goes active High and stays High until the device has been filled with the appropriate number of configuration frames. After that, DOUT again passes all incoming configuration data on to other devices that might be part of the daisy chain. DOUT is thus the best observation point to see whether the configuration process has started properly. Immediately following the header, configuration data is received, formatted in a device-specific sequence of frames. Each frame starts with a single 0 as start bit, followed by a device-specific number of configuration bits per frame, followed by three 1s as stop bits (XC2000, XC3000) or, in XC4000, by four bits that are either 0110, or four bits of a running 16-bit CRC error-checking code. (The choice is made in Makebits, where the default is "CRC disabled"). The header is not included in the CRC calculation. Each frame is physically shifted into a serial shift register that had been preset to all ones. When the zero start bit hits the far end of this shift register, the data frame is transferred in parallel into the configuration memory, as addressed by the position of an internal token or pointer. The three stop or four error-check bits provide ample time for this transfer, even at the 10 MHz CCLK rate allowed for XC3000 and XC4000 devices. After this transfer, the shift-in procedure continues with the following frame. Note that there is no counter for the number of bits in the frame or for the number of frames. The operation is self-synchronized by detecting the presence of a start bit at the far end of the shift register, and by moving the frame pointer. Each Xilinx FPGA requires a number of configuration bits that is device-dependent, but independent of the configuration content, and independent of the configuration mode. The number of configuration bits per device varies from 12,038 for the XC2064 to 422,168 for the XC4025, roughly 20 bits per gate. The exact numbers of configuration bits are listed in the specific family data sheets. 14-25 FPGA Configuration Guidelines Protection Against Data or Format Errors The serial configuration scheme has proven reliable in thousands of designs and millions of devices, but there have been cases where an erroneous bitstream was loaded accidentally. The original XC2000 and XC3000 devices provide no effective protection against this type of error. If long enough, any random sequence of 0s and 1s will configure a device. This inevitably takes more CCLK pulses than specified in the length-count value. This means that the CCLK counter equals the length-count value before the FPGAs are filled. This comparison is, therefore, ignored, and an additional 16 million CCLK pulses are required to roll the 24-bit length counter and finish the configuration. Such a configuration will, of course, be wrong and might result in excessive power consumption due to internal or external contentions. XC3000A, XC3100A, XC3000L and XC3100L devices use a simple and effective method to protect against erroneous configuration files or against loss (or gain) of CCLK pulses: All Xilinx FPGA devices recognize a new frame when its leading zero reaches the end of the shift register. XC2000, XC3000, and XC3100 devices do not check for the presence of valid stop bits, but XC3000A/XC3100A/XC3000L/ XC3100L devices always check whether the three bits at the end of the defined frame length are 111. If this check fails, INIT is pulled Low and the internal configuration is stopped, although a master CCLK keeps running. The user must recognize this state and start a new configuration by applying a >6 s Low level on RESET. This simple check does not protect against single-bit random errors, but it offers almost 100% protection against erroneous configuration files, defective configuration data sources, synchronization errors between configuration source and FPGA, as well as PC-board defects, such as broken lines or solder bridges. The XC4000 series uses, optionally, four bits of a running 16-bit cyclic redundancy check code at the end of each frame, combined with additional CRC bits at the end of the bit stream. These error-detecting CRC codes provide excellent protection against errors, even those that do not change the frame structure. When an error is detected, INIT goes Low and stays Low until the user initiates a reconfiguration. (A master device does, however, continue generating CCLK pulses and incrementing or decrementing the parallel PROM address). Daisy-Chain Operation Multiple FPGAs can be configured by a single concatenated bitstream. The device daisy chain is formed by connecting DOUT to the next device's DIN, and connecting all CCLK pins in parallel. Since DOUT goes active on a falling clock edge, and DIN is used on the subsequent rising clock edge, each DOUT-to-DIN connection adds one extra bit of delay to the bitstream. Since the header is passed through all devices, they all receive this information almost simultaneously (staggered by one bit per device), but all devices maintain perfect synchronism between their CCLK counters. Xilinx recognizes the need for all devices in a daisy chain to finish their configuration and begin user operation simultaneously, as a result of one common CCLK edge. Therefore, all devices in a daisy-chain need a common timing reference. They cannot rely on the start pattern received through the pipelined chain, but must all count the common CCLK pulses exactly the same way. This explains the importance of well-defined configuration clocking. Start-Up Procedure The transition from configuration to user operation faces several difficulties. During configuration, all outputs that are not involved in the configuration process are 3-stated, although the crystal oscillator circuit is activated as soon as possible. All internal flip-flops and latches are held reset (set or reset in XC4000), and the DONE output is held Low. At the end of configuration, these three conditions must change: As shown in detail in Figure 2, the three families offer different options: XC2000 has no options; the I/Os go active one CCLK period after length-count match. DONE goes active and the global reset is released one CCLK period later. XC3000 makes the I/Os go active two CCLK periods after length-count match; but DONE and the release of the global reset can each occur either one CCLK period before or after the I/Os go active. The default is "early DONE and late release of the global reset". This makes the outputs go active while the internal logic is still held reset. The other Makebits option, "early release of global reset", lets the internal logic be clocked out of its reset state before the outputs go active. Normally, there is no defined timing relationship between the last configuration events triggered by the rising edge of CCLK, and the subsequent events that are controlled by the system clock. The user must be aware of the potential problems of this asynchronous relationship. See the XC4000 solution described below. XC4000 has more options for the relative timing of I/Os, DONE and GSR, the release of the global set or reset. 14-26 June 1, 1996 (Version 1.0) Length Count Match CCLK Period CCLK F DONE I/O XC2000 Global Reset F DONE XC3000 I/O Global Reset F DONE C1 XC4000/ XC5200 C2 C3 C4 C2 C3 C4 C2 C3 C4 I/O CCLK_NOSYNC GSR Active DONE IN F DONE XC4000/ XC5200 C1, C2 or C3 I/O CCLK_SYNC Di Di+1 GSR Active Di Di+1 F DONE C1 XC4000/ XC5200 U2 U3 U4 U2 U3 U4 U2 U3 U4 I/O UCLK_NOSYNC GSR Active DONE IN F DONE C1 XC4000/ XC5200 U2 I/O Di UCLK_SYNC Di+1 Di+2 Di+1 Di+2 GSR Active Synchronization Uncertainty Note: Thick lines are default option Figure 2: Start-up Timing June 1, 1996 (Version 1.0) Di UCLK Period F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing X5972 14-27 FPGA Configuration Guidelines XC4000 can also use DONE as an input to hold off the activation of the I/Os and the release of GSR, until DONE is no longer pulled Low. The change then takes place either immediately upon the release of DONE, or as a result of the next CCLK rising edge. When all DONE pins in a daisy chain are interconnected, this start-up mode guarantees that all devices in the daisy chain will go active only when all of them have reached the DONE state, another protection against configuration errors. XC4000 can also be configured to employ the system (user) clock instead of CCLK, again either using DONE as an output, or as a bidirectional pin. The user clock provides a properly synchronized and racefree transition from the end of configuration to the beginning of user operation. The unspecified on-chip delay in the release of GSR (about 100 ns in XC4013) requires some caution, however, when using a high clock frequency for configuration. While XC2000, XC3000, and XC4000 can be arbitrarily interspersed in a daisy-chain, there is one restriction: the lead device must belong to the highest family in the chain. If the chain contains XC4000 devices, the lead device cannot be XC2000 or XC3000; if the chain contains XC3000, then the lead device cannot be XC2000. The reason is shown in Figure 2. Since all devices in the chain store the same length-count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge. The master device then generates additional CCLK pulses until it reaches its finish point F. As shown in Figure 2, the different families generate and require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device has not really finished its configuration process, although DONE may have gone High, the outputs became active, and the internal reset has been released. For XC4000, not reaching F means that READBACK cannot be initiated, and most boundary scan instructions cannot be used. This limitation has been criticized by designers who want to use an inexpensive lead device in Peripheral Mode, and save the more precious XC4000 I/O pins. Here is a solution for that case (Figure 3): One CLB and one IOB in the lead XC3000 device are used to generate the additional CCLK pulse required by the XC4000 devices. When the lead device releases its internal reset signal, the 2-bit shift register starts responding to its clock input, and it generates an active Low output signal for the duration of one clock period. An external connection between this IOB pin and the CCLK pin thus creates the extra CCLK pulse. This solution requires one CLB, one IOB and pin, and an internal clock source with a frequency of up to 5 MHz. Obviously, the XC3000 lead device must be configured with late internal reset, which happens to be the default option. 14-28 OE/T Reset 0 0 1 0 1 1 0 1 0 1 etc Output Connected to CCLK Active Low Output Active High Output 3-Stated Output 3-Stated Output X5552 Figure 3: Additional CCLK-Pulse Generator Configuration Modes There are six different configuration modes, hardwareselected by applying logic levels to the three mode inputs, M0, M1, and M2. The six modes are: Master Serial, Master Parallel Up, Master Parallel Down, Synchronous Peripheral (XC4000 only), Asynchronous Peripheral, and Slave Serial. In Master modes, the FPGA addresses an external PROM or EPROM storage device, and reads data from it. No additional timing or control signals are used. In Peripheral mode, the FPGA accepts byte-wide data (bitserial in XC2000), and interacts with the source of data, usually a microprocessor, with a Ready/Busy handshake. In Slave mode, the FPGA receives bit-serial data and a clock from an external data and timing source, either from a microprocessor, or from the lead device in an FPGA-daisy chain. The modes are selected by putting the appropriate logic levels on the three mode inputs, M0, M1, and M2 prior to the beginning of configuration. These three pins can be hardwired to VCC or Ground, but they can then never be used as user I/O. It is better to force a mode pin Low with a 3 k pull-down resistor to ground, acting against the 50 to 100 k internal pull-up resistor, and to rely on the built-in pull-up resistor to establish a High level on the M1, M2 mode pins, and a 50 k external pull-up resistor on M0. This eliminates the restrictions on using M2 as logic output on XC2000 and XC3000, or M1 on XC4000, and the use of M1 as readback data output in XC2000 and XC3000. When mode pin levels are driven by external logic, these levels must be established very soon after power-up. Establishing a mode level later might eliminate the extra master power-on delay that makes a master wait for slave devices to be ready after power-on. Delaying mode levels until the beginning of configuration will obviously cause the configuration to fail. Note that some EPLD devices have surprisingly long power-up delays. Be very careful when controlling mode levels in creative ways. June 1, 1996 (Version 1.0) Selecting the Best Configuration Mode * The selection of the most appropriate configuration mode is influenced by many factors, like * * * * * the need for interface simplicity, the need for rapid configuration, the need for multiple configuration sources, the availability of a microprocessor-based configuration driver. The simplest interface is Master Serial, using only two FPGA pins, CCLK and DIN, and no external timing or control signals. The fastest configuration mode is Slave Serial or XC4000 Synchronous Peripheral. In these modes, the user can supply a well-defined CCLK frequency of up to 10 MHz for all XC3000 and XC4000 5-Volt devices. No other configuration mode is that fast. For prototyping and rapid configuration change, the PC can configure the FPGA directly in Slave Serial mode, using the Xilinx-provided Download Cable or XChecker. * * * Multiple configuration codes are most conveniently stored in a microprocessor memory, using Peripheral mode to configure the FPGA. For field upgrades, Peripheral mode offers the greatest flexibility. New files can be supplied via diskette or modem, and can be downloaded by the microprocessor. When Configuration Fails General Debugging Hints for all Families If the DONE output does not go High, there are several things to check. Checking all supply and configuration-related pins with an oscilloscope or logic analyzer can reveal wiring errors, bad socket pins, noisy ground, noisy CCLK, a serial configuration PROM VPP pin not connected to VCC, PWRDWN not pulled High, poor or noisy RESET, missing pull-up resistors on DONE (or INIT in the XC3000), etc. * Monitor the DOUT pin of the lead device, i.e. the FPGA that is either configured alone, or forms the beginning of a daisy chain. At the start of configuration, you should see the 40-bit header shown in Figure 1. After this sequence, the DOUT pin remains High until the device has received all its data. Then, the device becomes transparent and passes additional data (provided there is a daisy chain) through the DOUT pin to the Slave devices. If you don't see this pattern, you have a gross error somewhere. Check the following items: * INIT going Low again after configuration start indicates a configuration bitstream or framing error in XC3000A, XC3000L or XC4000 families. * If RESET is used to delay configuration, make sure it has a rise time of <100 ns and that it is glitch-free. * * June 1, 1996 (Version 1.0) Ringing on the CCLK line can cause spurious clocking and loss of frame synchronization in the FPGA. Configuration functions can be disrupted by signal contention between configuration inputs and the FPGA user outputs which become active at the end of configuration. This change is indicated by I/O pins going active and HDC/LDC no longer at their configuration levels. Contention can be avoided by rearranging pinouts, maintaining additional 3-state control of user-I/O outputs, or matching start-up output levels to the configuration input levels on inputs other than chipselect. It is also possible to use a series resistor (1-10 k) to provide isolation between conflicting signal sources that could occur after configuration is complete. If an FPGA heats up significantly, this is usually the result of applying the wrong bitstream, e.g. the bitstream for a different device, causing contention. During reprogramming, user logic must generate a time-out that insures all devices have completed the Clear cycle before any configuration data is sent. Removing the FPGA supply voltage while externally powered signals continue to drive input pins, might keep the FPGA VCC pins at a 0.5-to-2.0 V level, which can leave the FPGA in an invalid state. The FPGA input-protection diodes are there to clamp input-voltage excursions to the two supply connections. When the FPGA supply voltage falls more than 0.5 V below an active input signal, this input signal will supply degenerate VCC levels. If the input signals are not current-limited, the FPGA inputs can even be damaged by the excessive input current. If extraneous CCLK pulses are applied after Clear but before the beginning of the header, the internal clock count will equal the stored length-count value before the configuration data is completely loaded. In this case, the DONE output does not become active until the clock counter equals length count a second time. This requires 224 extra clocks, or about 20 s at the typical rate of 0.7 MHz. Whenever configuration takes 15 to 25 seconds, this is due to a mismatch between length count and the number of CCLK pulses received. * * XChecker or the XACT Download Cable provide an alternate method of configuration to verify configuration data and to isolate wiring errors, such as interchanged or inverted configuration data or control signals. Try a different device. Although the chips are 100% factory-tested, an individual device might have been damaged later. 14-29 FPGA Configuration Guidelines General Debugging Hints for the XC2000 and XC3000 Families An undefined (floating) or active Low PWRDWN during configuration can disturb the operation. A Low level on PWRDWN immediately before the start of configuration causes problems in XC2000, forces XC3000 into Slave mode, but is acceptable in XC3000A and L. * In the XC2000 and XC3000 families, the configurationclock input signal drives quasi-static circuitry that does not tolerate a Low time of more than 5 s. * At power-up, make sure VCC rises in 25 ms or less. If this cannot be guaranteed, hold RESET active on the FPGAs and on the serial PROMs until VCC has reached 4.5 V. * A slowly rising or noisy RESET can cause multiple FPGAs to get out of synchronization. Always debounce reset switches. * * General Debugging Hints for the XC4000 Family At power-up, make sure VCC rises in 25 ms or less. If this cannot be guaranteed, hold PROGRAM or INIT active Low on the FPGAs and hold the serial PROMs reset until VCC has reached 4.5 V. * The boundary scan input pins are active during configuration, even if boundary scan is not used in the design. Toggling TCK, TMS and TDI during configuration might send the device into EXTEST mode, which interferes with configuration. Keeping at least one of these three inputs continuously High during configuration avoids this problem. * * * * Master Serial Mode * * * Additional Mode-Specific Debugging Hints for All Families Master Parallel Up and Down Mode * * Review the general debugging hints. Check that the PROM data pins are connected to the FPGA input pins D0-D7. Check that the PROM address pins are connected to the FPGA output pins A0-A15. Verify that all these connections are in the right order. Monitor the FPGA pins, not the socket pins. Make sure the socket is good. * If the PROM is dedicated to the FPGA, the CS and OE PROM inputs should be driven from the DONE or LDC FPGA output. * Verify that the FPGA is sending addresses to the PROM. If it is not, check the FPGA mode pins. M0 = 0, M1 = 0, M2 = 1 for Master Parallel Up M0 = 0, M1 = 1, M2 = 1 for Master Parallel Down Check that the PROM is receiving addresses and is sending out data. If it is not, check that the PROM is enabled and has VCC and ground connected, and verify that the PROM is programmed with the correct data. Check for contention between the PROM address or data pins and other signals on the board. Check that the FPGA is addressing the correct memory segment. In Master Parallel Up mode, the FPGA starts at address 0000 hex and counts up; in Master Parallel Down mode it starts at address FFFF hex (3FFFF hex in XC4000) and counts down. If the PROM requires different addressing, that must be taken care of by external hardware. Check for ringing and noise on address and data lines. Make sure the data in the PROM is correct. You can check it against the Rawbits file. Review the general debugging hints. Verify that the FPGA is generating a clock signal on its CCLK pin and that this signal is reaching the CLK pin of the XC1700-series Serial-Configuration PROM. If it is not, check the mode pins. M0 = 0, M1 = 0, M2 = 0 for Master Serial mode * Verify that the XC1700-series Serial Configuration PROM is sending data. If it is not, check that power and ground are applied to the Serial PROM, and VPP is connected to VCC. Do Not Let the VPP Pin Float A floating VPP pin results in temperature-dependent operation, the most notorious cause of unreliable configuration. * Check that the DATA pin of the Serial PROM is connected to the DIN pin of the FPGA, and that the PROM is enabled with CE Low and OE active. Note that the OE/RESET pin is programmable for either polarity. * Verify that the PROM is programmed with the correct data. * At power-up, make sure VCC rises from 2.0 V to 4.5 V in less than 25 ms. If it does not, hold the FPGA RESET and the PROM RESET active until VCC reaches 4.5 V. A typical result of a slow VCC rise time is that the FPGA sends out CCLK continuously, the CEO pin on the PROM(s) goes Low, but the DONE pin never goes High. * If you abort configuration by asserting XC3000 RESET or by pulling XC4000 PROGRAM Low, you must also reset the serial PROM by asserting its RESET. Note that this pin can be programmed for either polarity. Make sure VCC, RESET and PWRDWN are at 5 V and all ground pins are at 0 V. 14-30 June 1, 1996 (Version 1.0) Asynchronous Peripheral Mode Slave Serial Mode * * * * Review the general debugging hints. Check the mode pin levels. M0 = 1, M1 = 0, M2 = 1 for Peripheral mode * * See schematics on pages 2-40 and 2-128. Verify that the FPGA is receiving data at its input pin(s) and that it is receiving valid Write-Strobe and ChipSelect signals. If not, check the device driving the FPGA. Make sure that these signals meet the timing requirements listed in the product family documentation. XC3000 Family: Check that the minimum Write-Strobe active time (TCA min = 100 ns) is met and observe the RDY/BUSY signal. XC2000 Family: Be sure maximum and minimum Write-Strobe active times (TCA max = 5.0 s, min = 0.25 s) are met. * Make sure that the FPGA is ready to receive data. XC3000 Family: On power up, make sure that the INIT pin has gone High, or wait at least 34 ms before you begin sending data to the FPGA. Make sure that the RDY/BUSY signal is High before sending each data byte. XC2000 Family: On power up, make sure that the FPGA has had time to "wake up," at least 34 ms, before sending it data. * Check for contention between the Chip Select and Write Strobe signals and monitor the levels on those pins after configuration. It is best to use the Chip Select pins only as inputs after configuration. Avoid contention if they are used as outputs. With XC2000 family devices, the I/Os become active before the FPGA receives its final data bits and clocks, and also before the DONE pin goes High. If the user function for any of the Chip Selects or the Write Strobe become outputs after configuration, they could contend and, in effect, de-select the FPGA so that it never receives its final data bits. See also next page, left column. Beware of contention! * Check for contention between the FPGA pins and other signals on the board. XC4000 and XC3000 Families: Data is received as eight bits in parallel. Make sure bit 0 is connected to the D0 pin, bit 1 to D1 pin, etc. XC2000 Family: Data is received serially. If a PROM file is used as a data source, check that data is properly serialized LSB first. Data must be LSB first, although length count is MSB first. June 1, 1996 (Version 1.0) Review the general debugging hints. Check the mode pin levels. M0 =1, M1 = 1, M2 = 1 for Slave Serial mode * * See schematics on pages 2-35 and 2-130. Make sure Vcc, RESET, and PWRDWN are at 5 V, and ground pins are at 0 V. * Verify that the FPGA is receiving data on DIN and that it is receiving a valid clock signal on CCLK. Check the device sending the data. Check the device sending the clock signal, and make sure the clock meets the timing requirements specified in the product family documentation. A CCLK generated by a Master FPGA always meets the timing requirements. Don't violate the XC3000 and XC2000 CCLK Low time specification of 5.0 s. * Make sure the FPGA is ready to receive data. XC3000 Family: On power up, make sure the INIT pin is High or wait at least 34 ms before you begin sending data to the FPGA. XC2000 Family: On power up, make sure that the FPGA has had time to "wake up" at least 34 ms, before sending it data. * At power up, make sure VCC rises from 2.0 V to 4.5 V in less than 25 ms. If it does not, hold RESET Low until the VCC pins reach 4.5 V. Daisy Chain Debugging Hints * * * * * The key to debugging daisy-chain configurations is to isolate the problem and attempt to configure a single FPGA. Remove all but the first device from the board and configure it. Then insert the second device and configure both. Repeat as you add one device at a time until they all configure. The first device in the chain can be in any of the configuration modes. Debug it first, using the hints provided for the appropriate mode. All devices after the first one are in Slave Serial mode, so refer to the Slave Serial mode debugging hints above to solve any problems with Slave device. Monitor the DOUT pin of each device in the chain and verify that the 40-bit header appears at the beginning of configuration, staggered by one CCLK period per device. If the Master device in the chain is an XC2000-family device and the Slaves are XC3000-family, make sure the XC3000-family devices are configured with early DONE. 14-31 FPGA Configuration Guidelines Potential Length-Count Problem in Parallel or Peripheral Modes It is highly desirable that the complete change from configuration to user operation occur as the result of one single byte-wide input. The activation of outputs and DONE, the de-activation of the global reset (set/reset in XC4000), and the progression to the "finished" state F (see Figure 2) should all occur as a result of one common byte input. Under normal circumstances, the software achieves this by manipulating the length-count value appropriately, taking into account the additional bits between devices, and adjusting for the fact that byte-wide interfaces always leave the last bit sitting in the P-S converter, shifting it out at the beginning of the next byte. These complexities, combined with the many possible daisy-chain arrangements have occasionally led to problems, where the device outputs go active before the last required byte had been received. This can lead to contention on the address outputs or data inputs and might prevent the device from going DONE, or reaching the real end of its configuration sequence. Not reaching this "finished" state limits the use of readback and boundary scan. A new Makebits option solves this problem: Since XACT 5.0, the default option is "Length-Count aligned" which adjusts the length-count value such that length-count match occurs during the first bit in the last configuration byte. This assures sufficient CCLK pluses to complete any selected type of start-up sequence. The other option is "DONE-aligned", which adjusts length count value to make DONE go active at the end of a configuration data byte, which can cause problems in Peripheral mode. Only Peripheral modes seem to be sensitive to the difference between these two options. Miscellaneous Notes CCLK is the most important configuration signal. Once the INIT output is High, each device counts every Low-to-High transition of this configuration clock. In all modes except Slave Serial and XC4000 Synchronous Peripheral, CCLK is a very fast output that cannot be made slew-rate limited. When distributing this clock, the user should pay special attention to glitches, overshoots, and undershoots. In severe cases, a 33 resistor in series with the CCLK output might improve the signal integrity. In other cases, it might be better to provide a pull-up resistor at the far end of the CCLK net. Since the clock net has a transmission-line characteristic impedance of always less than 100 , the limited output drive capability of the CCLK output precludes proper parallel termination. DOUT is an excellent observation point, since every device must output the preamble on this pin, irrespective of the selected configuration mode, and irrespective of the position in, or the existence of, a daisy chain. INIT of all XC4000 and XC3000 devices in a daisy chain should be interconnected to prevent the configuration from starting before all devices are ready. A 10 k pull-up resistor is recommended. The parallel INIT of the daisy-chained devices must be connected to the INIT of the lead XC4000 device, or to the RESET input of the lead XC3000 device. This is especially important for re-configuration, where the master does not have a four-times longer wait period. The DONE output indicates the end of the configuration process. In XC2000 and XC3000 systems, it makes sense to ground DONE permanently. The RESET input then becomes the reconfiguration input, and cannot be used as the dedicated asynchronous user RESET input. LDC can be used to indicate end of configuration. PWRDWN (on XC2000 and XC3000 devices) must be High before and during the configuration process. Don't let PWRDWN float! 14-32 June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) Xilinx FPGAs can be configured in a common daisy-chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC2000, XC3000, XC4000, and XC5200 series devices can be mixed freely with only one constraint: the lead device must be a member of the highest-order family used in the chain. (For the purposes of this discussion, there is no difference between the XC4000 series and the XC5200 family, when XC5200 is used in any configuration mode except Express Mode). The lead device must generate a sufficient number of CCLK pulses after length-count-match was achieved, but XC3000-series devices generate fewer CCLK pulses than XC4000-series or XC5200-family devices require, and XC2000 devices generate even fewer CCLK pulses after length-count match. See Figure 1. In a daisy-chain, all CCLK pins are interconnected, and DOUT of any upstream device feeds the DIN input of its downstream neighbor. Those are the basic connections. For control purposes, it is advisable to interconnect all the slave INIT pins (the XC2000 does not have this pin) and connect them to the INIT pin of the lead XC4000/XC5200 device or the RESET input of the lead XC3000 device. Configuring Mixed FPGA Daisy Chains Application Note by PETER ALFKE Length Count Match CCLK Period CCLK F DONE I/O XC2000 Global Reset F DONE XC3000 I/O Global Reset F DONE C1 XC4000/ XC5200 C2 C3 C4 C2 C3 C4 C2 C3 C4 I/O CCLK_NOSYNC GSR Active DONE IN F DONE XC4000/ XC5200 C1, C2 or C3 I/O CCLK_SYNC Di Di+1 GSR Active Interconnected INIT pins prevent the master from starting the configuration process until all slaves are ready. For power-up this is assured automatically, since the master uses four times as many internal clocks for the power-up as any slave does, but, when re-configuring, master and slave devices consume the same number of clocks to clear a frame, and a fast master might be ready before a slow slave is. Interconnecting INITs solves this problem. The DONE/PROG (D/P) and RESET pins (XC2000, XC3000) and the XC4000/XC5200 PROGRAM pins can be used in different ways, depending on the designer's preferences regarding reconfiguration, pin utilization, and need for a global RESET input. If there is no need for a global logic RESET input, then it is best to permanently ground the XC2000/3000 D/P pin, which means that the RESET input functions as the Reconfigure input, and should be connected to all XC4000/ XC5200 PROGRAM inputs. Di Di+1 F DONE C1 XC4000/ XC5200 U2 U3 U4 U2 U3 U4 U2 U3 U4 I/O UCLK_NOSYNC GSR Active DONE IN F DONE C1 XC4000/ XC5200 U2 I/O Di UCLK_SYNC Di+1 Di+2 Di+1 Di+2 GSR Active Synchronization Uncertainty Note: Thick lines are default option Di UCLK Period F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing X5972 Figure 1: Start-up Timing June 1, 1996 (Version 1.0) 14-33 Configuring Mixed FPGA Daisy Chains put) and that, if Serial mode is chosen for the lead device, the XC1700 device(s) store only one configuration for the whole daisy chain. The serial PROM(s) must, therefore, be reset before the daisy chain is to be (re)programmed. VCC 5 K To All D/P Wired Together REPROGRAM GLOBAL RESET VCC To All RESET, Except Lead Device 5 K From All INIT Pins Wired Together To RESET of Lead Device X5982 There are three possible types of daisy chains using XC3000 and XC4000/XC5200 devices. Here are the recommended connections for the configuration control pins. Case 1: Daisy chain consists of nothing but XC3000-series devices: Figure 2: Use lead device's LDC to drive XC1700 CE. If there is a need for a global logic RESET input that can reset all flip-flops in the user logic without causing reconfiguration, then external logic must combine RESET and D/P in such a way, that pulling Low RESET does not affect D/P, but pulling Low D/P also pulls down RESET. See Figure 2. Use lead device's INIT to drive XC1700 RESET. The following simple recommendations guarantee a welldefined beginning for any FPGA configuration or reconfiguration process, after the initialization and clearing of the configuration memory in all FPGAs has been completed, and the address counter in the serial PROM(s) has been reset. The connections described below guarantee reliable operation even under adverse operating conditions such as VCC glitches. The lead device can use any configuration mode available. In all modes except Slave Serial, its CCLK pin is the output that clocks all other devices. Obviously, all CCLK and XC1700 CLK pins must be interconnected, the DATA outputs from multiple XC1700 serial PROMs must be interconnected and connected to the DIN input of the lead device, and the daisy-chain must be established by connecting each DOUT output to the downstream DIN input. Configuration control pins are: XC3000, XC3000A, XC3000L, XC3100, XC3100A: DONE/PROGRAM (open-drain output/input) RESET (input) INIT (open-drain output) XC4000 Series (XC4000, XC4000A, XC4000D, XC4000E, XC4000EX, XC4000H) and XC5200-family: DONE (open-drain output / input) PROGRAM (input) INIT (open-drain output / input) XC1700: RESET (input with programmable polarity) The following recommendations assume that there are no XC2000 devices in the daisy chain (they lack the INIT out- 14-34 Interconnect all slave INITs and connect them to the lead RESET input. Interconnect all DONE pins. Interconnect all slave RESET inputs Instigate Reprogram by pulling the slave RESET net Low for at least 6 s while all DONE pins are Low. (DONE can be permanently wired Low, but that sacrifices the use of RESET as a global reset of the user logic. If DONE is not wired Low, reprogram must pull DONE Low with an open-collector or open-drain driver). Case 2: Lead device is XC4000-series or XC5200 family, driving any mixture of XC3000, XC4000 and XC5200 devices: Use lead device's LDC to drive XC1700 CE. Use lead device's INIT to drive XC1700 RESET. Interconnect all INIT pins. Interconnect all DONE pins. Interconnect all XC4000/XC5200 PROGRAM inputs. Interconnect all XC3000 RESET inputs. Combine these two nets into one PROGRAM/RESET net Instigate Reprogram by pulling the combined PROGRAM/ RESET Low. Case 3: Daisy chain consists of nothing but XC4000/ and XC5200-type devices: Use lead device's LDC to drive XC1700 CE. Use lead device's INIT to drive XC1700 RESET. Interconnect all INIT pins. Interconnect all DONE pins (only required for UCLK-SYNC option). Interconnect all XC4000/XC5200 PROGRAM inputs. Instigate Reprogram by pulling PROGRAM Low. June 1, 1996 (Version 1.0) June 1, 1996 (Version 1.0) Configuration Issues: Power-up, Volatility, Security, Battery Back-up Application Note by PETER ALFKE Summary This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to powersupply glitches? Is there any danger of picking up erroneous data and configuration? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse-engineering? Xilinx Families XC2000, XC3000, XC4000, XC5200 Power-Up Here is a detailed description of XC3000 Series, XC4000 Series and XC5200 device behavior during supply ramp-up and ramp-down. When Vcc is first applied and is still below about 3 V, the device wakes up in the pre-initialization mode. HDC is High; INIT, LDC and DONE or DONE/PROG (D/P) are Low, and all other outputs are 3-stated with a weak pull-up resistor. When VCC has risen to a value above ~3 V, and a 1 and a 0 have been successfully written into two special cells in the configuration memory, the initialization power-on time delay is started. This delay compensates for differences in VCC detect threshold and internal CCLK oscillator frequency between different devices in a daisy chain. The initialization delay counts clock periods of an on-chip oscillator (CCLK) which has a 3:1 frequency uncertainty depending on processing, voltage and temperature. Time-out, therefore, takes between 11 and 33 ms for a slave device, four times longer for a master device. This factor of four makes sure that even the fastest master will always take longer than any slave. We assume that the worst- case difference between 33 ms and 4 x 11 ms is enough to compensate for the VCC rise time spent between threshold differences (max 2 V) of devices in a daisy chain. Only in cases of very slow VCC rise time (>25 ms), must the user hold RESET Low until VCC has reached a proper level. Interconnecting the INIT pins of all devices in a daisy-chain is a better method of synchronizing start-up, but cannot be used with XC2000 devices, since they lack an INIT pin. After the end of the initialization time-out, each device clears its configuration memory in a fraction of a millisecond, then tests for inactive RESET or PROGRAM, stores the MODE value and starts the configuration process, as described in the Data Sheet. After the device is configured, the 5-V VCC may dip to about 3.5 V without any significant consequences beyond an increase in delays (circuit speed is proportional to Vcc), and a reduction in output drive. If Vcc drops into the 3-V range, it triggers a sensor that forces the June 1, 1996 (Version 1.0) device back to the pre-initialization mode described above. All flip-flops are reset, HDC goes High; INIT, LDC and D/P or DONE go Low, and all other outputs are 3-stated with a weak resistive pull-up. If VCC dips substantially lower, the active outputs become weaker, but the device stays in this preinitialization mode. When VCC rises again, a normal configuration process is initiated, as described above. Sensitivity to VCC Glitches The user need not be concerned about power supply dips: The XC3000/XC4000/XC5200 devices stay configured for small dips and they are "smart enough" to reconfigure themselves (if a master) or to ask for reconfiguration by pulling INIT and D/P or DONE Low (if a slave). The devices will not lock up; the user can initiate re-configuration at any time just by pulling D/P or PROGRAM Low or, if D/P is Low, by forcing a High-to-Low transition on RESET. Any digital logic device with internal data storage in latches or flip-flops is sensitive to power glitches. This includes every RAM, microprocessor, microcontroller, and peripheral circuit. Only purely combinatorial circuits can be guaranteed to survive a severe power glitch without any problem. Xilinx SRAM-based FPGAs store their configuration in latches that lose their data when the supply voltage drops below a critical value (which is substantially below 3 V for the 5-V devices), but configuration data is extremely robust and reliable while VCC stays above 3 V. All Xilinx configuration latches are implemented as cross-coupled complementary inverters with active pull-down n-channel transistors and active pull-up p-channel transistors. Both High and Low logic levels have an impedance of less than 5k with respect to their respective supply rail. Typical SRAM memory devices use passive poly-silicon pull-up resistors with an impedance of about 5,000 M. A current of one nanoamp (!) is sufficient to upset the typical SRAM cell, whereas it takes a million times more current to upset the Xilinx configuration latch. 14-35 Configuration Issues: Power-up, Volatility, Security, Battery Back-up This does not mean that SRAMs are unreliable, it just shows that the levels in Xilinx configuration latches are six orders of magnitude more resistant to upsets caused by external events, like cosmic rays or alpha particles. Xilinx has never heard about any occurrence of a spontaneous change in the configuration store in any of its ~50 million FPGA devices sold over the past twelve years. Whereas most digital circuits rely on Vcc staying within specification, Xilinx FPGAs have an internal voltage monitoring circuit. For example, in the 5-Volt devices, whenever the supply voltage dips below 3 V, the internal monitoring circuit causes the Xilinx FPGA to stop normal operation. All outputs go 3-state, and the device waits for the supply voltage to rise closer to 4 V, when it either demands (slave or peripheral mode) or initiates (master mode) a reconfiguration. In the range between 5.5 and 3 V, all typical CMOS devices maintain their functionality and their data storage, they just get slower as the voltage goes down. Xilinx has made sure that the FPGA cannot be corrupted by a power glitch. The most sensitive circuit is the low-voltage detector. It kicks in while all other configuration storage and user logic is still guaranteed to be functional. The voltagemonitoring feature in the Xilinx device can even be used to protect other circuitry, or it can be coordinated with external monitoring circuits. There is no possibility of a VCC dip causing the device to malfunction, i.e., to operate with erroneous configuration information. * If VCC stays above the trip point, the device functions normally, albeit at reduced speed, like any other CMOS device. * If VCC dips below the trip point, the device 3-states all outputs and waits for reconfiguration. Xilinx production-tests the VCC-dip tolerance of all XC3000 devices in the following way. After the device is configured, VCC is reduced to 3.5 V, and then raised back to 5.0 V. Configuration data is then read back and compared against the original configuration bit stream. Any discrepancy results in rejection of the device. Subsequently, VCC is reduced to 1.5 V and then raised to 5.0 V. The device must first go 3-state, then respond with a request for reconfiguration. Both these tests are performed at high temperature (>85C for commercial parts, >100C for military). Any part failing any of these tests is rejected as a functional failure. operation. A Xilinx FPGA detects the power glitch and always plays it safe by flagging the problem. No complex system of any kind can function reliably when Vcc is unreliable. Xilinx FPGAs do the safest thing possible, whenever such problems occur. Design Security Some Xilinx customers are concerned about the security of their designs. How can they protect their designs against unauthorized copying or reverse-engineering? We must distinguish between two very different situations: * * Configuration data in accessible from a serial or parallel EPROM or in a microprocessor's memory. This is the normal case. Configuration data is hidden from the user, since the design does not permanently store a source of configuration data. After the FPGA was configured, the EPROM or other source was removed from the system, and configuration is kept alive in the FPGA through battery-back-up. Design Security when Configuration Data is Accessible In the first case, it is obviously very easy to make an identical replica of the design by copying the configuration data and the pc-board interconnect pattern of the standard devices, but it is virtually impossible to interpret the bitstream in order to understand the design or make intelligent modifications to it. Xilinx keeps the interpretation of the bitstream a closely guarded secret. Reverse-engineering an FPGA would require an enormously tedious analysis of each individual configuration bit, which would still only generate an XACT view of the FPGA, not a usable schematic. The best protection against a mindless copy is legal. The bitstream is easily protected by copyright laws that have proven to be more successfully enforced than the intellectual property rights of circuit designs. The combination of copyright protection, and the almost insurmountable difficulty of creating any design variation for the intended function, provides good design security. The recent successes of small companies in reverse-engineering microprocessors and microprocessor support circuits show that a non-programmable device can actually be more vulnerable than an FPGA. For advice on legal protection of the configuration bitstream, see the following paragraphs. As a result of these careful precautions, we contend that Xilinx FPGAs are safer than all other types of circuitry (except purely combinatorial circuits). A microprocessor can loose the content of its address register, its accumulator or other control register due to an undetected power glitch, with disastrous consequences to the subsequent 14-36 June 1, 1996 (Version 1.0) Legal Protection of Configuration Bit-Stream Programs The bit-stream program loaded into the FPGA may qualify as a "computer program" as defined in Section 101, Title 17 of the United States Code, and as such may be protectable under the copyright law. It may also be protectable as a trade secret if it is identified as such. We suggest that a user wishing to claim copyright and/or trade secret protection in the bit stream program consider taking the following steps. Place an appropriate copyright notice on the FPGA device or adjacent to it on the PC board to give notice to third parties of the copyright. For example, because of space limitations, this notice on the FPGA device could read "(c)1996 XYZ Company" or, if on the PC board, could read "Bit Stream (c))1996 XYZ Company". File an application to register the copyright claim for the bit-stream program with the U.S. Copyright Office. If practicable, given the size of the PC board, notice should also be given that the user is claiming that the bit- stream program is the user's trade secret. A statement could be added to the PC board such as: "Bitstream proprietary to XYZ Company. Copying or other use of the bitstream program except as expressly authorized by XYZ Company is prohibited." To the extent that documentation, data books, or other literature accompanies the FPGA-based design, appropriate wording should be added to this literature providing third parties with notice of the user's claim of copyright and trade secret in the bit-stream program. For example, this notice could read: "Bit-Stream(c))1996 XYZ Company. All rights reserved. The bit-stream program is proprietary to XYZ Company and copying or other use of the bit- stream program except as expressly authorized by XYZ Company is expressly prohibited." To help prove unauthorized copying by a third party, additional nonfunctional code should be included at the end of the bit-stream program. Therefore, should a third party copy the bit-stream program without proper authorization, if the non-functional code is present in the copy, the copier cannot claim that the bit-stream program was independently developed. These are only suggestions, and Xilinx makes no representations or warranties with respect to the legal effect or consequences of the above suggestions. Each user is advised to consult legal counsel with respect to seeking protection of a bit-stream program and to determine the applicability of these suggestions to the specific circumstances. If the user has any questions, contact the Xilinx legal department at 408-879-4984. June 1, 1996 (Version 1.0) Design Security by Hiding the Configuration Data If the design does not contain the source of configuration data, but relies on battery-back-up of the FPGA configuration, then there is no conceivable way of copying this design. Opening up the package and probing thousands of latches in undocumented positions to read out their data without ever disturbing the configuration is impossible. This mode of operation offers the ultimate design security. It is being used by several Xilinx customers who have reason to be concerned about illegal pirating of their designs. Battery Back-up and Powerdown Since SRAM-based FPGAs are manufactured using a high-performance low-power CMOS process, they can preserve the configuration data stored in the internal static memory cells even during a loss of primary power. This is accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current requirement of VCC from a battery. Circuit techniques used in XC3100, XC4000 and XC5200 devices prevent ICC from being reduced to the level needed for battery back-up. Consequently, battery back-up should only be used for XC2000, XC2000L, XC3000, XC3000A and XC3000L devices. There are two primary considerations for battery backup which must be accomplished by external circuits. * Control of the Power-Down (PWRDWN) pin * Switching between the primary VCC supply and the battery. Important considerations include the following. * Insure that PWRDWN is asserted logic Low prior to VCC falling, is held Low while the primary VCC is absent, and returned High after VCC has returned to a normal level. PWRDWN edges must not rise or fall slowly. * Insure "glitch-free" switching of the power connections to the FPGA device from the primary VCC to the battery and back. * Insure that, during normal operation, the FPGA VCC is maintained at an acceptable level, 5.0 V 5% (10% for Industrial and Military). Figure 1 shows a power-down circuit developed by Shel Epstein of Epstein Associates, Wilmette, IL. Two Schottky diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal power monitor circuit monitors VCC and pulls PWRDWN Low whenever VCC falls below 4 V. 14-37 Configuration Issues: Power-up, Volatility, Security, Battery Back-up Things to Remember: VCC IN5817 Seiko S8054 Specifications Detect Voltage 3.995 V min 4.305 V max 208 mV typ Hysteresis Temp. Coeff. 0.52 mV/C 2.6 A typ ICC @ + 6V 2 SEIKO 1 PWRDWN S 8054 IN5817 VCC B35 Lithium Battery FPGA 3 X5997 Figure 1: Battery Back-up Circuit Powerdown Operation A Low level on the PWRDWN input, while VCC remains higher than 2.3 V, stops all internal activity, thus reducing ICC to a very low level: * * * * * * * All internal pull-ups (on Long lines as well as on the I/O pads) are turned off. The crystal oscillator is turned off All package outputs are three-stated. All package inputs ignore the actual input level, and present a High to the internal logic. All internal flip-flops or latches are permanently reset. The internal configuration is retained. When PWRDWN is returned High, after VCC is at its nominal value, the device returns to operation with the same sequence of buffer enable and D/P as at the completion of configuration. 14-38 Powerdown retains the configuration, but loses all data stored in the device. Powerdown three-states all outputs and ignores all inputs. No clock signal will be recognized, and the crystal oscillator is stopped. All internal flip- flops and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial logic is fully functional. Things to Watch Out for: Make sure that the combination of all inputs High and all internal flip-flop outputs Low in your design will not generate internal oscillations or create permanent bus contention by activating internal bus drivers with conflicting data onto the same long line. These two situations are farfetched, but they are possible and will result in considerable power consumption. It is quite easy to simulate these conditions since all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function generators. During powerdown, the VCC monitoring circuit is disabled. It is then up to the user to prevent VCC dips below 2.3 V, which would corrupt the stored configuration. During configuration, the PWRDWN pin must be High, since configuration uses the internal oscillator. Whenever VCC goes below 4 V, PWRDWN must already be Low in order to prevent automatic reconfiguration at low VCC. For the same reason, VCC must first be restored to 4 V or more, before PWRDWN can be made High. PWRDWN has no pull-up resistor. A pull-up resistor would draw supply current when the pin is Low, which would defeat the idea of powerdown, where ICC is only microamperes. June 1, 1996 (Version 1.0) Dynamic Reconfiguration June 1, 1996 (Version 1.0) Application Note By PETER ALFKE All Xilinx SRAM-based FPGAs can be in-system configured and re-configured an unlimited number of times. The XC6200 family has additional features that allow partial and very fast (re-)configuration from a microprocessor bus. See the XC62000 product documentation for details. Important Considerations This application note describes the procedures for reconfiguring the more traditional Xilinx FPGAs of the XC2000, XC3000, XC3100, XC4000, and XC5200 families. All configuration information is stored in latches that are loaded serially, conceptually like a shift register. There are several different bit-serial or byte-parallel configuration data interfaces, selected by logic levels on three mode inputs, but - with the exception of the XC5200 Express mode - they all result in the bit-serial loading of the configuration latches. The byte-parallel interfaces in Master Parallel and Peripheral modes act just as an 8-bit parallel-to-serial converter. Between devices in a daisy-chain, the configuration information is transmitted bit-serially with a common Configuration Clock (CCLK). In Master and Peripheral modes, CCLK is generated by the lead FPGA device, in Slave Serial mode, CCLK comes from an external source. Reconfiguration of an operational device, or a daisy-chain of devices, goes through the following sequence of events: * * * * * * Reconfiguration is initiated by pulling a specific device pin Low. First, all outputs are 3-stated, except HDC = High, LDC and DONE = Low Then, all internal registers, flip-flops and latches, as well as the configuration storage latches are cleared. During this time, the INIT output is being pulled Low. Then, the Mode inputs and RESET or PROGRAM inputs are sampled to determine the selected configuration mode and whether to start the new configuration process, or to wait. Then configuration data is accepted and loaded into the internal latches and distributed through the daisy-chain. When all configuration information has been entered, the user outputs are activated, DONE goes High and the internal reset is released, all in the order specified in the configuration bitstream. All devices in a daisy-chain perform each of these operations in synchronism. June 1, 1996 (Version 1.0) * * * Reconfiguration is "all or nothing". There is no way to restrict reconfiguration to a part of the chip (Note that XC6200 devices do not have this limitation). Reconfiguration takes a specific time, determined only by device type, size and clock speed, independent of the particular configuration pattern. Configuration takes from tens to hundreds of milliseconds. During that time, all user-outputs of the device, or the whole daisy-chain of devices, are 3-stated with weak internal pull-ups, except for HDC and LDC, which are active High or Low respectively. All user-data stored in registers, flip-flops or latches is erased. There is no way to retain data inside the device from one configuration to the next. These limitations are absolute. If they are not acceptable, the user must resort to creative solutions, like piggy-backing multiple devices. The designer of reconfigurable applications should be familiar with the normal configuration process of each device, as described in the individual product descriptions. There is also pertinent information about daisy-chain operation, especially about mixed daisy chains, on previous pages. Interconnecting the INIT pins of all devices in a daisy-chain is mandatory for reconfiguration, since this is the only way to guarantee that the master device does wait for the rest of the daisy-chain to be cleared, before starting the reconfiguration. Only the first configuration after power-up makes the master device spend four times as many clock periods as any slave during the initial clear operation, so that the master cannot possibly get ahead of the slaves. Reconfiguration, however, does not slow down the master this way, so the interconnection of all INIT pins must serve that same purpose. Note that the XC2000-family devices do not have an INIT pin. In Master Serial mode, it is highly recommended that the active Low level of INIT be used to reset the XC1700-family Serial PROM. 14-39 Dynamic Reconfiguration Reconfiguration Time Reconfiguration time is usually more critical than the original power-on configuration time, which is often masked by the general power-on delays. Initiating Reconfiguration in Different Xilinx Device Families XC2000 and XC3000 Series Here are some suggestions to reduce reconfiguration time. There are three alternatives: * 1. Pull RESET Low while DONE is permanently grounded externally. * * A daisy-chain is obviously not conducive to fast configuration, it should be broken up into shorter blocks, perhaps single devices. Multiple devices can be configured in parallel, but can still use a common CCLK, and can also be made to start up together. If the devices differ in size or family, they should all be given the same length count as the largest device in the group. Configuration Mode Parallel and Peripheral modes are not any faster than Master Serial mode, since all modes (with the exception of XC4000EX and XC5200 Express mode) internally operate on serial data. The internally generated CCLK frequency is guard-banded to never approach the upper limit of what the device can tolerate. Therefore, the fastest possible configuration mode for XC3000 and XC4000-series devices is Slave Serial, with an external well-controlled source for CCLK. Its frequency can be up to 10 MHz for all 5-V devices, and there are ways to increase the average clock rate well beyond that, but they require dynamic clock frequency changes and an intimate understanding of the configuration frame structure. At 10 MHz, configuration time per device ranges from 1.5 ms for the XC3020A to 42 ms for the XC4025E and 143 ms for the XC4062EX. Possible Contention Problems: Certain user outputs become active during the configuration process: Address outputs during Master Parallel mode, Chip Select and Ready/Busy during Peripheral modes. The designer must make sure that these active outputs do not cause contention with other logic that might use the same pins as device inputs. 14-40 This is the simplest scheme, but it precludes the use of RESET to clear the flip-flops and latches in the operating user-design. RESET must be pulled Low for more than six microseconds to overcome its internal low-pass filtering. Configuration starts when RESET has gone High again. 2. Pull DONE Low with an open-drain ("open-collector") output. This assumes that DONE was High, i.e. that the previous configuration was successful. Reconfiguration starts as soon as the internal memory has been cleared. DONE can be released anytime. 3. Pull DONE Low with an open-drain ("open-collector") output and pull RESET Low. Keep RESET Low for at least six microseconds while DONE is Low. DONE can be released anytime after that, or not released at all. See alternative 1. XC4000 Series and XC5200 Family Pull the PROGRAM input Low for at least 0.3 microseconds to initiate clearing the configuration memory, then pull PROGRAM up to start the new configuration process. While PROGRAM is held Low, a Low level on INIT indicates that the device is continuously clearing the configuration memory. When PROGRAM has been pulled up, INIT stays Low during one more clear operation, then goes High. All device families, except the original XC4000, have a continuously active pull-up resistor on the PROGRAM pin. June 1, 1996 (Version 1.0) Metastable Recovery June 1, 1996 (Version 2.0) Application Note By PETER ALFKE and BRIAN PHILOFSKY Whenever a clocked flip-flop synchronizes an asynchronous input, there is a small probability that the flip-flop output will exhibit an unpredictable delay. This happens when the input transition not only violates the setup and hold-time specifications, but actually occurs within the tiny timing window where the flip-flop accepts the new input. Under these circumstances, the flip-flop can enter a symmetrically balanced transitory state, called metastable (meta = between). With the help of a self-contained circuit, Xilinx evaluated the XC4000 and XC3000-series flip-flops. The result of this evaluation shows the Xilinx flip-flop to be superior in metastable performance to many popular MSI and PLD devices. While the slightest deviation from perfect balance will cause the output to revert to one of its two stable states, the delay in doing so depends not only on the gain-bandwidth product of the circuit, but also on how perfect the balance is, and on the noise level within the circuit; the delay can, therefore, only be described in statistical terms. The problem for the system designer is not the illegal logic level in the balanced state (it's easy enough to translate that to either a 0 or a 1), but the unpredictable timing of the final change to a valid logic state. If the metastable flip-flop drives two destinations with differing path delays, one destination might clock in the final data state while the other does not. Asynchr, Input D QA D QB Since metastability can only be measured statistically, this data was obtained by configuring several different Xilinx FPGAs with a detector circuit shown in Figure 1. The flipflop under test receives the asynchronous ~1-MHz signal on its D input, and is clocked by a much higher manually adjustable frequency. The output QA feeds two flip-flops in parallel, one (QB) being clocked by the same clock edge, the other (QC) being clocked by the opposite clock edge. When clocked at a low frequency, each input change gets captured by the rising clock edge and appears first on QA, then, after the falling clock edge, on QC, and finally, after the subsequent rising clock edge, on QB. If a metastable event in the first flip-flop increases the settling time on QA so much that QC misses the change, but QB still captures it on the next rising clock edge, this error can be detected by feeding the XOR of QB and QC into a falling-edge triggered flip-flop. Its output (QD) is normally D QC D QD 16-Bit Counter 16 LEDs Clock Clock Asynchr, Input QA QB NO ERROR QC ERROR ERROR QD NO ERROR X5985 Figure 1: Test Circuit and Timing Diagram June 1, 1996 (Version 2.0) 14-41 Metastable Recovery Low, but goes High for one clock period each time the asynchronous input transition caused such a metastable delay in QA. The frequency of metastable events can be observed with a 16-bit counter driven by QD. By changing the clock frequency, and thus the clock halfperiod, the amount of acceptable metastable delay on the QA output can be varied, and the resulting frequency of metastable events can be observed on the counter outputs. As expected, no metastable events were observed at clock rates below 70 MHz for the XC4005-6, or below 100 MHz for the XC4005E-3, since a half clock period at those frequencies is adequate for almost any metastability-resolution delay. Increasing the clock rate slightly brought a sudden burst of metastable events. Careful adjustment of the clock frequency gave repeatable, reliable measurements. Metastability Measurements The circuit of Figure 1 was implemented in four different Xilinx devices: two cutting-edge devices using 0.5 micron, 3layer-metal technology, the XC4005E-3 and the XC3142A09, and, for comparison purposes, also in two older-technology devices, the XC4005-6 and the XC3042-70. In each device two different implementations put QA, the flip-flop under test, into an IOB and a CLB. The XC4000series devices showed little difference between IOB and CLB behavior, but in the XC3000-series devices, the IOB flip-flops showed dramatically better metastable performance than the CLB flip-flops. This difference can be traced to subtle differences in circuit design and layout, and will guide us to further improvements in metastable performance in future designs. Metastable measurement results are listed in Table 1, and are plotted in Figure 2. The results for XC4000E-3 (IOB and CLB) and for XC3100A-09 IOB flip-flops are outstanding, far superior to most metastable data published anywhere else. When granted 2 or 3 ns of extra settling delay, these devices come close to eliminating the problems caused by metastability, since their MTBF exceeds millions of years. Table 1: Metastable Measurement Results Device XC4005E-3 IOB XC4005E-3 CLB XC4005-6 IOB XC4005-6 CLB XC3142A-09 IOB XC3142A-09 CLB XC3042-70 IOB XC3042-70 CLB FL (MHz) 111.5 109.0 73.0 71.2 152.2 107.4 46.6 41.9 FH Half-period K2 (MHz) Difference (ns) (1/ ns) 131.6 0.685 16.1 124.4 0.568 19.4 90.0 1.294 8.5 88.8 1.392 7.9 206.6 0.87 12.7 211.3 2.29 4.8 61.5 2.60 4.2 64.8 4.22 2.6 Metastability Calculations The Mean Time Between Failures (MTBF) can only be defined statistically. It is inversely proportional to the product of the two frequencies involves, the clock frequency and the average frequency of the asynchronous data changes, provided that these two frequencies are independent and have no correlation. The generally accepted equation for MTBF is MTBF = eK2 * t F1 * F2 * K1 K1 represents the metastability-catching set-up time window, which describes the likelihood of going metastable. K2 is an exponent that describes the speed with which the metastable condition is being resolved. K2 is an indication of the gain-bandwidth product in the feedback path of the master latch of the master-slave flip-flop. A small increase in K2 results in an enormous improvement in MTBF. With F1 = 1 MHz, F2 = 10 MHz and K1 = 0.1 ns = 10-10 s, MTBF (in seconds) = 10-3 * eK2*t Experimentally derived (see Table 1): K2 = 16.1 per ns, for the XC4005E-3 IOB flip-flops The older-technology devices are obviously less impressive, but they still show acceptable performance, especially in the IOB input flip-flops that are normally used to synchronize asynchronous input signals. K2 = 19.4 per ns, for the XC4005E-3 CLB flip-flops Table 1 lists the experimental results from which the exponential factor K2 was derived. The clock frequency was adjusted manually, while observing the LSB and the MSB of the 16-bit error counter. FL is the clock frequency that generated a ~1 Hz error rate, FH generated a ~64,000 Hz error rate. K2 = 12.7 per ns, for the XC3142A-09 IOB flip-flops K2 = 8.5 per ns, for the XC4005-6 IOB flip-flops K2 = 7.9 per ns, for the XC4005-6 CLB flip-flops K2 = 4.8 per ns, for the XC3142A-09 CLB flip-flops K2 = 4.2 per ns, for the XC3042-70 IOB flip-flops K2 = 2.6 per ns, for the XC3042-70 CLB flip-flops K2 is derived by dividing ln 64,000 by the half-period difference. 14-42 June 1, 1996 (Version 2.0) MTBF XC4005E-3 CLB 1M Years XC3142A-09 IOB XC4005-6 IOB 13 XC4005-6 CLB 12 XC4005E-3 IOB 11 1,000 Years Log Seconds 10 9 XC3142A-09 CLB 8 1 Year 7 XC3042-70 IOB 6 5 1 Day 4 1 Hour 3 XC3042-70 CLB 2 1 Minute 1 0 -1 -2 1 2 3 4 5 6 Acceptable Extra Delay (ns) -3 X5986 Figure 2: Mean Time Between Failure for various IOB and CLB flip-flop outputs when synchronizing a ~1 MHz asynchronous input with a 10 MHz clock. For other operating conditions, divide MTBF by the product of the two frequencies. For a ~10 MHz asynchronous input synchronized by a 40 MHz clock, the MTBF is 40 times June 1, 1996 (Version 2.0) shorter than plotted; for a ~50 kHz signal synchronized by a 1 MHz clock, the MTBF is 200 times longer than plotted here. 14-43 Metastable Recovery 14-44 June 1, 1996 (Version 2.0) Set-up and Hold Times June 1, 1996 (Version 1.0) Application Brief By PETER ALFKE Beware of hold-time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates. This means that the data source, usually another IC driven by the same clock, must guarantee to maintain data beyond the clock edge. In other words, the data source is not allowed to be very fast. If it is, the receiver might erroneously input the new data instead of the data created by the previous clock, as it should. This is called a race condition, and can be a fatal system failure. "Set-up time" and "hold time" describe the timing requirements on the data input of a flip-flop or register with respect to the clock input. The set-up and hold times describe a window of time during which data must be stable in order to guarantee predictable performance over the full range of operating conditions and manufacturing tolerances. A positive set-up time describes the length of time that the data must be available and stable before the active clock edge. A positive hold time, on the other hand, describes the length of time that the data to be clocked into the flip-flop must remain available and stable after the active clock edge. A positive set-up time limits the maximum clock rate of a system, but a positive hold time can cause malfunction at any clock rate. Thus, chip designers and system designers strive to eliminate hold-time requirements. The IC design usually guarantees that any individual flipflop does not require a positive hold time with respect to the clock signal at this flip-flop. Hold-time requirements between flip-flops or registers on the same chip can be avoided by careful design of the onchip clock distribution network. If the worst-case clock-skew value is shorter than the sum of minimum clock-to-Q plus minimum interconnect delays, there is never any on-chip hold-time problem. It is, however, far more difficult to avoid a hold time problem in the device input flip-flops, with respect to the device clock input pin. When specifying the data pin-to-clock pin set-up and hold times, the chip-internal clock distribution delay must be taken into consideration. It effectively moves the timing window to the right (see figure), thus subtracting from the specified internal set-up time (which is good), but adding to the hold time (which is very bad). If the clock distribution delay is any longer than the data input delay - and it easily might be - the device data input has a hold-time requirement with respect to the clock input. June 1, 1996 (Version 1.0) If the receiving device has a hold time requirement, the source of data must guarantee an equivalent minimum value for its clock-to-output delay. Almost no IC manufacturer is willing to do this, and in the few cases where it is done, the minimum value is usually a token 1 ns. Any input hold time requirement is, therefore, an invitation to system failure. Any clock distribution skew on the PC-board can compound this issue and wipe out even the specified short minimum delay. Xilinx has addressed this problem by adding a deliberate delay to every FPGA data input. In XC3000, and XC3100 FPGAs, this delay is fixed and always present; in XC4000 and XC5200 FPGAs, this delay is optional, and its value is tailored to the clock distribution delay (i.e. it is larger for bigger devices). As a result we can claim that no Xilinx FPGA Data input has a hold-time problem (i.e., none has a positive hold time with respect to the externally applied clock), when the design uses the internal global clock distribution network (and, in XC4000 and XC5200, uses the delayed input option). Most competitive devices do not offer this feature. Internal Clock Delay External Clock Internal Clock Conventional Input Pin Set-up and Hold Time Input Pin Set-up Time With Delay SET-UP H SET-UP X5971 14-45 Set-up and Hold Times 14-46 June 1, 1996 (Version 1.0) Overshoot and Undershoot June 1, 1996 (Version 1.0) Application Brief By PETER ALFKE The "Absolute Maximum Ratings" table in the Xilinx Data Book restricts the signal-pin voltage to a maximum 500 mV excursion above VCC and below ground. The reason for this tight specification is to prevent uncontrolled current in the input-clamping ESD-protection diodes. Such tight specifications are common in the industry; some manufacturers limit the excursion to 300 mV. Fortunately, this problem has an easy solution: This specification seems to be clean and simple, but it is violated in almost every practical design. When users put modern CMOS devices on PC boards, and interconnect them with unterminated traces, there are reflections, commonly called "ringing", that cause overshoots and undershoots of substantial amplitude (2 V and more). The recent migration to smaller device geometries has made the IC outputs even faster and increased the slew-rate, causing more reflections even on short PC-board traces. PC-board reflections, on the other hand, usually have a short duration of just a few nanoseconds, and have an impedance of 40 to 100 , which makes them incapable of causing latch-up. They don't drive enough current and they don't last long enough to cause any harm. June 1, 1996 (Version 1.0) The concern is not the input voltage, but rather the current through the input protection diode and other input structures. Excessive current can cause latch-up if it exceeds hundreds of milliamps AND if it lasts for microseconds (shorter duration current spikes do not activate the SCRlike latch-up mechanism). Here is the new Xilinx specification: "Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns". 14-47 Overshoot and Undershoot 14-48 June 1, 1996 (Version 1.0) Boundary Scan in XC4000 and XC5000 Series Devices June 1, 1996 (Version 2.0) Summary XC4000 and XC5000 Series FPGA devices contain boundary-scan facilities that are compatible with IEEE Standard 1149.1. This Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design. Xilinx Family XC4000 Series, XC5200 Demonstrates Boundary Scan Introduction In production, boards must be tested to assure the integrity of the components and the interconnections. However, as integrated circuits have become more complex and multilayer PC-boards have become more dense, it has become increasingly difficult to test assembled boards. Originally, manufacturers used functional tests, applying input stimuli to the input connectors of the board, and observing the results at the output. Later, "bed-of-nails" testing became popular, where a customized fixture presses sharp, nail-like stimulus- and test-probes into the exposed traces on the board. These probes were used to force signals onto the traces and observe the response. its internal shift registers, and passing the serial data directly to the next device. XC4000/XC5000 FPGA devices contain boundary-scan registers that are compatible with the IEEE Standard 1149.1, that was derived from a proposal by the Joint Test Action Group (JTAG). External (I/O and interconnect) testing is supported; there is also limited support for internal self-test. Overview of XC4000/XC5000 Boundary-Scan Features However, increasingly dense multi-layer PC boards with ICs surface-mounted on both sides have stretched the capability of bed-of-nail testing to its limit, and the industry is forced to look for a better solution. Boundary-scan techniques provide that solution. XC4000/XC5000 devices support all the mandatory boundary-scan instructions specified in the IEEE Standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD and BYPASS instructions. The TAP can also support two USERCODE instructions. The inclusion of boundary-scan registers in ICs greatly improves the testability of boards. Boundary scan provides a mechanism for testing component I/Os and inter-connections, while requiring as few as four additional pins and a minimum of additional logic in each IC. Component testing may also be supported in ICs with self-test capability. Note: If boundary scan is not used after the device is configured, the user can use the special boundary scan pads as input or output pins. And like the regular IOBs, these input and output pins have pullups and pulldowns available. The TDI, TMS, and TCK pads can be used as input pads. The TDO pad can be used as an output pad. Devices containing boundary scan have the capability of driving or observing the logic levels on I/O pins. To test the external interconnect, devices drive values onto their outputs and observe input values received from other devices. A central test controller compares the received data with expected results. Data to be driven onto outputs is distributed through a chain of shift registers, and observed input data is returned through the same shift-register path. Boundary-scan operation is independent of individual IOB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability even after configuration affords tremendous flexibility for interconnect testing. Data is passed serially from one device to the next, thus forming a boundary-scan path or loop that originates at the test controller and returns there. Any device can be temporarily removed from the boundary-scan path by bypassing June 1, 1996 (Version 2.0) Additionally, internal signals can be captured during EXTEST by connecting them to unbonded IOBs, or to the unused outputs in IOBs used as unidirectional input pins. This partially compensates for the lack of INTEST support. 14-49 Boundary Scan in XC4000 and XC5000 Series Devices It should also be noted that the Test Data Register contains three Xilinx test bits (BSCANT.UPD, TDO.O and TDO.T) and that bits of the register may correspond to unbonded or unused pins. The public boundary-scan instructions are always available prior to configuration. After configuration, the public instructions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. Additionally, the EXTEST instruction incorporates INTESTlike functionality that is not specified in the standard, and system clock inputs are not disabled during EXTEST, as recommended in the standard. In addition to the test instructions outlined above, the boundary-scan circuitry can also be used to configure the FPGA device, and readback the configuration data. The TAP pins (TMS, TCK, TDI and TDO) are scanned, but connections to the TAP controller are made before the boundary-scan logic. Consequently, the operation of the TAP controller cannot be affected by boundary-scan test data. The following description assumes that the reader is familiar with boundary-scan testing and the IEEE Standard. Only issues specific to the XC4000/XC5000 implementation are discussed in detail. For general information on boundary scan, please refer to the bibliography. When the TAP is in the shift-DR state the contents of all data registers are shifted; if you are in the middle of shifting out data from the data register in a XC4000, complete shifting out of all data first, before switching to the instruction or bypass register. Deviations from the IEEE Standard The XC4000/XC5000 boundary scan implementation deviates from the IEEE standard in that three dedicated pins (CCLK, PROGRAM and DONE) are not scanned. 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 1 1 SELECT-IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 1 1 1 EXIT1-DR 0 0 PAUSE-DR 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 EXIT1-IR 0 0 0 SHIFT-IR 0 NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. 1 0 X2680 Figure 1: State Diagram for the TAP Controller 14-50 June 1, 1996 (Version 2.0) Boundary-Scan Hardware Description Test Access Port The boundary-scan logic is accessed through the Test Access Port (TAP), which comprises four semi-dedicated pins: Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI) and Test Data Output (TDO), as defined in the IEEE specification. The TAP pins are permanently connected to the boundaryscan circuitry. However, once the device is configured, the connections may be ignored unless the use of boundary scan is specified in the design (See "Using Boundary Scan"). If the use of boundary scan is specified, the TAP input pins (TMS, TCK and TDI) may still be shared with other logic, subject to limitations imposed by external connections and the operation of the TAP Controller. In designs that do not use boundary scan after configuration, the TAP pins can be used as inputs or outputs from the user logic in the FPGA device. TMS, TCK and TDI are available as unrestricted I/Os, while TDO only provides a 3-state output. TAP Controller The TAP Controller is a 16-state state machine that controls the operation of the boundary-scan circuitry in response to TMS. This state machine implements the state diagram specified by the IEEE standard (Figure 1) and is clocked by TCK. Upon power-on, or if the boundary scan logic is not used in the application, the TAP controller is forced into the TestLogic-Reset state. After configuration, the controller remains disabled, unless its use is explicitly specified in the user design. PROGRAM resets the latched decodes for EXTEST, CONFIGURE, and READBACK instructions. Loading a 3-bit instruction into the Instruction Register (IR) determines the subsequent operation of the boundaryscan logic, Table 1. The instruction selects the source of the TDO pin, and selects the source of device input and output data (boundary-scan register or input pin/user logic) Note: In the XC4000, whenever the TAP Controller is in the Shift-DR state, all data registers are shifted, regardless of the instruction. DR data is modified even if a BYPASS instruction is executed. The instruction register is not used only to hold the current instruction. If the TAP is in the capture-IR state and TCK goes high, the instruction register captures the current boundary-scan state of the device. I0 is 1 by default. I1 is 0 by default. I2 is 0 if the devices is in configure by boundary scan mode. Before and after configure by boundary scan mode, I2 will capture 1. Note that I0 is shifted out of TDO first, then I1, and then I2. June 1, 1996 (Version 2.0) Table 1: Boundary Scan Instructions. Instruction Test I2 I1 I0 Selected 0 0 0 EXTEST 0 0 1 SAMPLE/ PRELOAD 0 1 0 USER 1 0 1 1 USER 2 1 0 0 READBACK 1 0 1 CONFIGURE 1 1 0 RESERVED 1 1 1 BYPASS TDO Source DR DR I/O Data Source DR Pin/Logic TDO1 TDO2 Readback Data DOUT -- Bypass Reg Pin/Logic Pin/Logic Pin/Logic Disabled -- Pin/Logic IO is closest to DTO The Boundary-Scan Data Register The Data Register (DR) is a serial shift register implemented in the IOBs of the FPGA device, (Figure 2). Potentially, each IOB can be configured as an independently controlled bidirectional pin. Therefore, three data register bits are provided per IOB: for input data, output data and 3state control. In practice, many of these bits are redundant, but they are not removed from the scan chain. An update latch accompanies each bit of the DR, and is used to hold injected test data stable during shifting. The update latch is opened during the Update-DR state of the TAP Controller when TCK is Low. In a typical DR instruction, the DR captures data during the Capture-DR state (on the rising edge of TCK). This data is then shifted out and replaced with new test data. Subsequently, the update latch opens, and the new test data becomes available for injection into the logic or the interconnect. The injection of data occurs only if an EXTEST instruction is in progress. Note: The update latch is opened whenever the TAP Controller is in the Update-DR state, regardless of the instruction. Care must be exercised to ensure that appropriate data is contained in the update latch prior to initiating an EXTEST. Any DR instruction, including BYPASS, that is executed after the test data is loaded, but before the EXTEST commences, changes the test data. The IEEE Standard does not require the ability to inject data into the on-chip system logic and observe the results during EXTEST. However, this capability helps compensate for the lack of INTEST. Logic inputs may be set to specific levels by a SAMPLE/PRELOAD or EXTEST instruction and the resulting logic outputs captured during a subsequent EXTEST. It must be recognized, however, that all DR bits are captured during an EXTEST and, therefore, may change. Pull-up and pull-down resistors remain active during boundary scan. Before and during configuration, all pins 14-51 Boundary Scan in XC4000 and XC5000 Series Devices From TDI Pull-Up Pull-Down sd 1 D 0 D Q Q To Global Clock Buffer (CLK Pad Only) LE 1 IOB.I (To FPGA Interconnect) VCC 0 IOB sd 1 D 0 Q D Q LE 1 0 IOB.O (From FPGA Interconnect) IOB.T 0 sd 1 D 0 Q D Q 1 LE Towards TDO Shift/Capture DRCK Update Test Logic Reset EXTEST X5998 Figure 2: Boundary Scan Logic in a Typical IOB are pulled up. After configuration, the IOB can be configured with a pull-up resistor, a pull-down resistor or neither. Note: Internal pull-up/pull-down resistors must be taken into account when designing test vectors to detect open circuit PC traces. The primary and secondary global clock inputs (PGCK1-4 and SGCK1-4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if necessary, it is possible to drive the clock input from boundary scan. The external clock source is 3-stated, and the clock net is driven with boundary scan data through the output driver in the clock-pad IOB. If the clock-pad IOBs are used for non-clock signals, the data may be overwritten normally. Note: All IOBs remain in the DR, independent of whether they are actually used, or even bonded. Three bits, BSCANT.UPD, TDO.O and TDO.T, are included for Xilinx test purposes, and may be ignored by other users. CCLK, PROGRAM and DONE are not included in the boundary scan. Table 2: Boundary Scan Order Bit 0 ( TDO end) Bit 1 Bit 2 Top-edge IOBs (Right to Left) Figure 3 shows the data-register cell for a TAP pin. An ORgate permanently disables the output buffer if boundaryscan operation is selected. Consequently, it is impossible for the outputs in IOBs used by TAP inputs to conflict with TAP operation. TAP data is taken directly from the pin, and cannot be overwritten by injected boundary-scan data. Left-edge IOBs (Top to Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Table 2 lists, in data-stream order, the boundary-scan cells that make up the DR. The cell closest to TDO corresponds to the first bit of the data-stream, and is at the top of the table. This order is consistent with the BSDL description. Each IOB corresponds to three bits in the DR. The 3-state control is first (closest to TDO), the output is next, and the input is last. Other signals correspond to individual register bits. IOB locations assume that the die is viewed from the top, as in XDE. 14-52 TDO.T TDO.O Bottom-edge IOBs (Left to Right) Right-edge IOBs (Bottom to Top) (TDI end) B SCANT.UPD X2674 June 1, 1996 (Version 2.0) From TDI Pull-Up Pull-Down sd 1 D 0 D Q Q LE To Tap Controller 1 IOB.I IOB VCC 0 (To FPGA Interconnect) sd 1 D 0 Q D Q LE 1 0 IOB.O (From FPGA Interconnect) IOB.T 1 D 0 Q Boundary Scan Enabled Towards TDO Shift/Capture DRCK Update Test Logic Reset Device Not Configured EXTEST X5999 Figure 3: Boundary Scan Logic in a TAP Input (TMS, TCK, and TDI Only) Tables in the data sheet show the DR order for all XC4000 family devices. The DR also includes the following non-pin bits: TDO.T and TDO.I, which are always bits 0 and 1 of the DR, respectively, and BSCANT.UPD which is always the last bit of the DR. The Bypass Register This is a 1-bit shift register that passes the serial data directly to TDO when a bypass instruction is executed. User Registers The XC4000 boundary-scan instruction set includes two USERCODE instructions, USER1 and USER2. Connections are provided to the TAP and TAP controller that, together with direct connections to the TAP pins, permit the user to include boundary-scan self-test features in the design. The boundary scan block has six connections for user registers: SEL1, SEL2, TDO1, TDO2, DRCK and IDLE. TDI is available directly from the IOB that provides the TDI pin. Note: The TDI signal supplied to user test logic is overwritten by boundary-scan test data during EXTEST. During user tests, it is not altered. June 1, 1996 (Version 2.0) SEL1, SEL2 - SEL1 and SEL2 enable user logic. They are asserted (High) when the instruction register contains instructions USER1 and USER2, respectively. TDO1, TDO2 - TDO1 and TDO2 are inputs to the TDO output multiplexer, permitting user access to the serial boundary-scan output. They are selected when executing the instructions USER1 and USER2, respectively. Input to user data registers can be derived directly from the TDI pin, thus completing the boundary-scan chain. There is a one flip-flop delay between TDO1/TDO2 and the TDO output. This flip-flop is clocked on the falling edge of TCK. DRCK - Data register clock (DRCK) is a gated and inverted version of TCK. It is provided to clock user test-data registers. TDI data should be sampled with the falling edge of DRCK (rising edge of TCK). The TDO output flip-flop accepts data on the rising edge of DRCK (falling edge of TCK). DRCK is active only during the Capture-DR and Shift-DR states of the TAP controller. IDLE - IDLE is a second gated and inverted version of TCK. It is active during the Run-Test/Idle state of the TAP controller, and may be used to clock user test logic a set number of times, determined through TMS by the central test controller. 14-53 Boundary Scan in XC4000 and XC5000 Series Devices Using Boundary Scan Figure 4 is a flow chart of the FPGA start-up sequence that shows when the boundary-scan instructions are available. Since PROGRAM resets the TAP controller, boundary-scan operations cannot commence until PROGRAM has been taken High. Full boundary-scan capabilities are then available until INIT is High. Without external intervention, INIT automatically goes High after ~1 ms. If more time is required for boundary-scan testing, INIT may be held Low beyond this period by applying an external Low signal to the INIT pin until testing is complete. Boundary scan can be accessed before the FPGA is configured and after the FPGA is configured. If you want to access boundary scan before the device is configured, then when you power-up the device, hold the INIT pin low until VCC has risen to Vcc(min). If you have already started configuring the device, data frames are already being sent to the FPGA, then you have two choices. You can either access full-boundary scan mode, or limited boundary scan mode. If you want to access full-boundary scan mode, then both INIT and PROGRAM must be brought low (Hold INIT and PROG low for over 300 ns and then release PROGRAM. After releasing PROGRAM, continue to hold INIT low while sending signals to the TAP. If you can use the limited boundary scan mode (which means you only can use the SAMPLE/PRELOAD and BYPASS instructions), then just bring INIT low. VCC >3.5 V Boundary Scan Instructions Available: No Yes Test M0 Generate One Time-Out Pulse of 16 or 64 ms PROGRAM = Low Yes Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) INIT High? if Master ~1.3 s per Frame No Master Waits 50 to 250 s Before Sampling Mode Lines Yes Sample Mode Lines Master CCLK Goes Active Load One Configuration Data Frame Frame Error Yes No SAMPLE/PRELOAD BYPASS Configuration memory Full Pull INIT Low and Stop LDC Output = L, HDC Output = H Full access to the built-in boundary-scan logic is always available between power-up and the start of configuration. Optionally, the built-in logic is fully available after configuration if boundary scan is specified in the design. At this time, user test logic is also available, and may be accessed through the boundary-scan port. During configuration, a reduced boundary-scan capability remains available: the SAMPLE/PRELOAD and BYPASS instructions only. No Yes Pass Configuration Data to DOUT Accessing boundary scan after the device is configured has one requirement. The BSCAN symbol must be instantiated/inserted into your design with the correct syntax (see Figure 5). In this case, activating boundary scan after configuration amounts to toggling the TAP pins. CCLK Count Equals Length Count No Yes Start-Up Sequence EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK I/O Active F Operational If Boundary Scan is Selected X6076 Figure 4: Start-up Sequence 14-54 June 1, 1996 (Version 2.0) BSCAN TDI TDI TMS TMS DRCK TCK TCK IDLE TDO1 SEL1 TDO2 SEL2 From User Logic TDO TDO TDO OBUFT X2676 Figure 6: Typical Non-Boundary-Scan TDO Connection 4k BSCAN Syntax for BSCAN after configure symbol BSCAN IBUF TDI TMS OBUF TDI TDO TDO IBUF TMS DRCK IBUF TCK TCK IDLE TDO1 SEL1 TDO2 SEL2 5k BSCAN Syntax for BSCAN after configure symbol X5966 Figure 5: Boundary-Scan Schematic Capture - DR Update - DR From Previous Cell Test Data Register DRCK To Next Cell Update Latch EN Update - DR T System Logic O I EXTEST X2677 Figure 7: EXTEST Data Flow June 1, 1996 (Version 2.0) 14-55 Boundary Scan in XC4000 and XC5000 Series Devices The IEEE definition of EXTEST only requires that test data be driven onto outputs, that 3-state output controls be overridden, and that input data be captured. The capture of output data and 3-state controls and the forcing of test data into the system logic is normally performed during INTEST. update-IR state, the FPGA is now in the JTAG configuration mode and will start clearing the configuration memory. The XC4000 effectively performs EXTEST and INTEST simultaneously. This added functionality permits the testing of internal logic, and compensates for the absence of a separate INTEST instruction. However, when performing an EXTEST, care must be taken over what signals are driven into the system logic; data captured from internal system logic must be masked out of the test-data stream before performing check-sum analysis. 4. Once the Xilinx Configure instruction has been made current, the user must go from the update-IR state to the shift-DR state before the FPGA has finished clearing it's configuration memory. SAMPLE/PRELOAD - The SAMPLE/PRELOAD instruction permits visibility into system operation by capturing the state of the I/O. It also permits valid data to be loaded into the update register before commencing an EXTEST. If the user doesn't get to the shift-dr state before INIT goes high, then the bitstream will not be shifted into the FPGA in the right sequence and the device will not configure as expected. The DR and update latch operate exactly as in EXTEST (see above). However, data flows through the I/O unmodified. 5. Once INIT has gone high, the TAP should already be in the shift-DR state. BYPASS - The BYPASS instruction permits data to be passed synchronously to the next device in the boundaryscan path. There is a 1-bit shift register between the TDI and TDO flip-flop. USER1, USER2 - These instructions permit test logic, designed by the user and implemented in CLBs, to be accessed through the TAP. Test clocks and paths to TDO are provided, together with two signals that indicate that user instructions have been loaded. For details, see the User Registers section above. User tests depend upon CLBs and interconnect that must be configured to operate. Consequently, they may only be performed after configuration. CONFIGURE - Steps to Follow to configure a Xilinx XC4000, XC4000E, or XC5200 via JTAG: 1. Turn `on' the boundary scan circuitry. This can be done one of two ways, either via powerup or via a configured device with boundary scan enabled. If you want to do this via powerup, then just hold the INIT pin low when power is turned on. When VCC has reached VCC(min), then the TAP can be toggled to enter JTAG instructions. If you want to do this from a configured device, then just start toggling the JTAG port pins to go from test-logic-reset to run-test-idle. 2. Load the Xilinx Configure instruction into the IR. The Xilinx Configure instruction is 101(I2 I1 I0). I0 is the bit shifted in first into the IR. 3. After shifting in the Xilinx Configure instruction, make the Configure instruction the current JTAG instruction by going to the update-IR state. When TCK goes low in the 14-56 At this point, the user should be in the update-IR state in the TAP. The approximate time it takes to clear an FPGA's configuration memory is: 2 * 1 us * (# of frames per device bitstream). In the shift-DR state, start shifting in the bitstream. Continue shifting in the bitstream until DONE has gone high and the startup sequence has finished. During the time you are shifting in the bitstream via the TAP, the configuration pins LDC. HDC, INIT, PROGRAM, etc. all function as they normally do during nonJTAG configuration. Some Additional Notes: (a) If you want to power-up the FPGA in JTAG mode, this can be done by placing a pulldown of approximately 4.7 Kohms on the INIT pin. This pulldown has the merit of holding INIT low to allow the user to get into JTAG, *and* allow the user during JTAG configuration to 'see' the INIT pin; With the pulldown attached to INIT, the user will see a drop of approximately 0.5V if INIT drops low. The alternative to using a pulldown on the INIT pin on powerup is for the 'user' to hold INIT low during powerup, and once the TAP is in run-test-idle, release the INIT pin and pull it up to VCC. (b) It is possible to configure several 4K, 4KE, and/or 5K devices in a JTAG chain. But unlike non-JTAG daisychain configuration, this doesn't mean merging all the bitstreams into one bitstream. In the case of JTAG configuration of Xilinx devices in a JTAG chain, all devices, except the one being configured, will be placed in BYPASS mode. The one device in CONFIGURE will have its bitstream downloaded to it. After configuring this device it will be placed in BYPASS, and another device will be taken out of BYPASS into CONFIGURE. (c) In general for the XC4000, XC4000E, and XC5200, if you are configuring these devices via JTAG, finish configuring the device first before executing any other June 1, 1996 (Version 2.0) JTAG instructions. If the bitstream has not finished loading, then if you decide to execute some other JTAG instructions, then the configuration process via JTAG must be re-started from test-logic-reset. (d) If boundary scan is not available after the FPGA is configured, then make sure that the release of I/Os is the last event in the startup sequence. If boundary scan is not available, the FPGA is configured, and the I/Os are released before the startup sequence is finished, the FPGA will not respond to input signals and outputs won't respond at all. READBACK - Readback through the TAP allows the user to access the readback features of the device, which would normally need to be accessed through user-specified pins. All limits of `normal' readback are the same with readback through the TAP. Like regular readback, readback through the TAP is at a minimum of 10 KHz and at a maximum of 1 MHz. Like regular readback, the readback bistream through boundary scan has the same format. Unlike regular readback, which can be done over and over again, readback through the TAP requires the following circuit: 1. In your schematic, or top-level synthesis design, instantiate the BSCAN and READBACK symbols. 2. Connect the BSCAN symbol pins TDI, TMS, TCK, and TDO to the boundary scan pads TDI, TMS, TCK, and TDO, respectively. 3. Next, connect the net between the TCK pad and TCK pin on the BSCAN symbol to an IBUF. Take the output of the IBUF and connect it to the CLK pin of the READBACK symbol. See Figure 8. 7. After performing the first readback, another readback can be performed by going to the test-logic-reset state, and re-loading the READBACK instruction and performing the READBACK as described in the previous paragraph. In summary, consecutive readbacks are performed by starting from test-logic-reset, loading the IR with the READBACK instruction, shifting out the readback bitstream plus three additional TCK's, and then going back to the test-logic-reset state. Alternatively, if you do not want to go back to the testlogic-reset state, realize that after shifting out readback bitstream, a minimum of 3 additional clocks are needed on the readback register. So, after doing a readback, instead of going back to test-logic-reset, a user can opt to execute some other JTAG instruction, and then perform another readback. Also, this above procedure is only needed if you intend to do more than 1 readback. If you intend only to do a readback once, then connection between the BSCAN symbol and the READBACK symbol is not needed. In that case, all that is needed is the BSCAN symbol instantiated with the boundary scan pads (TDI, TMS, TCK, & TDO) on the top-level of the design. BSCAN TDO TDI TDI TMS TMS TCK TCK IDLE TDO1 SEL1 CLK TDO2 SEL2 TRIG TDO DRCK READBACK DATA RIP IBUF 4. After entering the above circuit, compile the design to an .lca file. 5. Make the .bit file for the .lca file by using the following option with makebits: * 4k BSCAN Symbol setup for multiple READBACKS through TAP * For the 5k, add IBUFs to TDI, TMS, and TCK. For TDO, add an OBUF. (see figure 5) X5968 Figure 8: Symbol Setup for Multiple Readbacks -f readclk:rdbk For example, at a unix prompt: % makebits -f readclk:rdbk designame 6. Now the FPGA is ready to perform consecutive readbacks. READBACK is performed by loading the IR with the READBACK instruction and then shifting out the captured data from the shift-dr state in the TAP. Boundary Scan Description Language Files Boundary Scan Description Language (BSDL) files describe boundary-scan-capable parts in a standard format used by automated test-generation software. The order and function of bits in the boundary-scan data register are included in this description. BSDL files are available via the Xilinx BBS (408-559-9327) Perform the first readback by loading the IR with the READBACK instruction. This first readback must be finished, which means shifting out the *entire* readback bitstream. To be safe, shift out the entire bitstream and then send three additional TCK's. June 1, 1996 (Version 2.0) Bibliography The following publications contains information about the IEEE Standard 1149.1, and should be consulted for gen- 14-57 Boundary Scan in XC4000 and XC5000 Series Devices eral boundary-scan information beyond the scope of this application note. GenRad Inc. Meeting the Challenge of Boundary Scan. GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174. Colin M. Maunder & Rodham E. Tulloss. The Test Access Port and Boundary Scan Architecture. IEEE Computer Society Press, 10662 Los Vaqueros Circle, P.O. BOX 3014, Los Alamitos, CA 90720-1264. Ken Parker. The Boundary Scan Handbook. Kluwer Academic Publications, (617) 871-6600. John Fluke Mfg. Co. Inc. The ABC of Boundary Scan Test. John Fluke Mfg. Co. Inc., P.O. BOX 9090, Everett, WA 98206. 14-58 June 1, 1996 (Version 2.0) 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Index 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Index A B C D E F G H I J K Numerics 3-state buffer XC3000 Series 4-293, 4-302, 14-17 XC4000 Series 4-29 XC5200 4-191 3-state net, global. See Global 3-State 5-input function XC3000 Series 14-13 XC5200 4-188 70% rule 14-16 7400 equivalents XC4000 Series 4-10 A ABEL 2-6, 2-7 See also XABEL-CPLD See also Xilinx ABEL absolute maximum ratings overshoot and undershoot 14-47 specifications XC1700D 6-6 XC3000A 4-343 XC3000L 4-351 XC3100A 4-359 XC3100L 4-367 XC4000E 4-81 XC5200 4-207 XC5200L 4-250 XC6200 4-275 XC8100 5-33 ACLK symbol 14-18 adaptor selector for programmer 10-2 address pins pin descriptions XC3000 Series 4-324 XC4000 Series 4-49 XC5200 4-198 XC6200 4-273 advance specifications, definition of 1-1, 4-80, 4-206 algorithms, programmer 10-1 Alliance Program 2-7 Alliance Series 2-6, 2-7, 2-11 Base System OrCAD (PC) 2-16 Viewlogic (PC) 2-18 Viewlogic Stand-Alone (PC) 2-20 Extended System Viewlogic Stand-Alone (PC) 2-22 Standard System Cadence (Workstation) 2-26 Mentor V8 (Workstation) 2-24 L M N O P Q R S T U V W X Y Z OrCAD (PC) 2-17 Synopsys (Workstation) 2-25 third party 2-27 Viewlogic (PC) 2-19 Viewlogic (Workstation) 2-23 Viewlogic Stand-Alone (PC) 2-21 ALU, XC7300 3-74 antifuse 5-3, 5-13 AppLINX CD-ROM 13-1, 13-5 array data multiplexer, XC6200 4-264 asynchronous peripheral configuration mode debugging hints 14-31 specifications XC3000 Series 4-315 XC4000 Series 4-75 XC6200 4-278 XC3000 Series 4-314 XC4000 Series 4-49, 4-74 XC6200 4-268 asynchronous RAM 4-19 attribute DECODE 4-31 INIT 4-19 LOC 4-41, 4-43, 4-45 MEDDELAY 4-26, 4-27 NODELAY 4-26, 4-27 available products HardWire 8-3 high-reliability 9-1 software 2-1 XC1700D 6-10 XC3000 Series 4-339 XC3000A 4-348 XC3000L 4-356 XC3100A 4-364 XC3100L 4-372 XC4000 Series 4-174 XC5200 4-248 XC6200 4-286 XC7300 3-71 XC8100 5-42 XC9500 3-4 B bar code 11-22 Base System Alliance Series OrCAD (PC) 2-16 Viewlogic (PC) 2-18 Viewlogic Stand-Alone (PC) 2-20 Foundation Series (PC) 2-12 with VHDL 2-13 1 Index A B C D E F G H I J basic moisture life test 12-2 battery backup in XC3000 Series 14-21, 14-37 BBS bulletin board 1-5, 13-3 command summary 13-3 BCLKIN 14-18 pin description XC3000 Series 4-324 BG packages package drawings 11-45 thermal resistance 11-12 BG225 package package drawing 11-45 pinout diagram XC8100 5-32 pinout table XC4000 Series 4-152 BG352 package package drawing 11-46 pinout table XC4000 Series 4-163 BG432 package package drawing 11-47 pinout table XC4000 Series 4-170 BGA packages package drawings 11-45 thermal resistance 11-12 bidirectional (bidi) buffer XC3000 Series 4-296 bitstream combining with MakePROM 4-55, 4-305 copyrighting 14-37 format for configuration XC4000 Series 4-56 XC5200 4-200 boundary scan access to 14-54 avoiding inadvertent activation 4-53 bypass register 14-53 configuration with 4-64 daisy chain configuration 14-56 data register 14-51 effect on GTS 4-28 implementing in schematic 4-53 XC4000 Series 4-53 library symbol 4-48, 4-53 pin descriptions XC4000 Series 4-48 XC5200 4-197 specifications XC4000E 4-96 TAP controller 14-51 test access port (TAP) 14-51 2 K L M N O P Q R S T U V W X user registers 14-53 XC4000 Series 4-29, 4-50, 14-49 XC5200 4-191, 14-49 XC8100 5-3, 5-11 XC9500 3-14 Boundary Scan Description Language. See BSDL BSCAN symbol 4-48, 4-53 BSDL files XC4000 Series 4-53, 14-57 XC5200 14-57 BUF1X symbol 5-7 BUFE symbol 5-6 BUFEDGE symbol 5-7 BUFFCLK symbol 4-45, 4-48 buffer, 3-state XC3000 Series 4-293, 4-302, 14-17 XC4000 Series 4-29 XC5200 4-191 buffer, bidirectional XC3000 Series 4-296 buffered switch matrix 4-36 BUFG symbol 4-194 BUFGE symbol 4-45, 4-48 BUFGLS symbol 4-43, 4-48 BUFGP symbol 4-41 BUFGS symbol 4-41 BUFROW symbol 5-7 BUFT symbol 4-30 bulletin board (BBS) 1-5, 13-3 command summary 13-3 bus contention, internal 14-17 bypass register 14-53 C cable XChecker 2-8, 2-36 Cadence 2-2, 2-7 software 2-26 carry logic XC4000 Series 4-21 XC5200 4-189 carry lookahead XC7300 3-75 cascade logic XC5200 4-190 XC8100 5-6 CB100 package package drawing XC3000 Series 11-61 XC4000 Series 11-62 CB164 package package drawing Y Z Index A B C D E F G H I J K XC3000 Series 11-63 XC4000 Series 11-64 CB196 package package drawing 11-65 CB228 package package drawing 11-66 CC packages package drawings 11-67 CC20 package package drawing 11-67 CCLK frequency variation XC3000 Series 14-21 in configuration debug 14-32 low-time restriction in XC3000 Series 14-21 pin description XC3000 Series 4-323 XC4000 Series 4-47 XC5200 4-197 setting frequency XC4000 Series 4-56 use as configuration clock 14-25 XC3000 Series 4-307 XC4000 Series 4-54 XC5200 4-199 ceramic packages brazed CQFP package drawings 11-61 DIP package drawings 11-48 PGA package drawings 11-49 windowed package drawings 11-51 characterization data XC7300 3-135 CLB. See configurable logic block CLB-to-pad diagram XC5200 4-212 XC5202 4-212 XC5204 4-214 XC5206 4-216 XC5210 4-218 XC5215 4-220 CLC. See configurable logic cell CLCC packages package drawings 11-67 clock diagram XC4000E 4-42 XC4000EX 4-42 XC6200 4-261 CMOS input XC3000 Series 4-293 L M N O P Q R S T U V W X Y Z XC4000 Series 4-24 XC5200 4-196 XC8100 5-9, 5-12 CMOS output XC3000 Series 4-293, 14-16 XC4000 Series 4-27, 14-12 XC5200 4-196 XC8100 5-10 ConfigOK pin description XC6200 4-273 configurable logic block (CLB) block diagram XC3000 Series 4-294 XC4000 Series 4-12 XC5200 4-188 carry logic XC4000 Series 4-21 XC5200 4-189 cascade logic XC5200 4-190 flip-flop XC3000 Series 4-294, 14-15 XC4000 Series 4-12 XC5200 4-188 function generator XC3000 Series 4-295, 14-13 XC4000 Series 4-11 XC5200 4-188 latch XC4000EX 4-12 XC5200 4-188 RAM 4-14 routing associated with XC3000 Series 14-15 XC4000 Series 4-32 specifications XC3000A 4-344 XC3000L 4-352 XC3100A 4-360 XC3100L 4-368 XC4000E 4-84 XC5200 4-209 XC3000 Series 4-294, 14-13 XC4000 Series 4-11 XC5200 4-184, 4-188 differences from XC4000 and XC3000 4-182 XC6200. See function unit configurable logic cell (CLC) cascade logic 5-6 flip-flop 5-6 function generator 5-6 latch 5-6 3 Index A B C D E F G H I J K L M N O P Q R S specifications 5-35 XC8100 5-5 configuration 14-25, 14-39 asynchronous peripheral mode debugging hints 14-31 XC3000 Series 4-314 XC3000 Series specifications 4-315 XC4000 Series 4-49, 4-74 XC4000 Series specifications 4-75 XC6200 4-268 bitstream copyrighting 14-37 bitstream format XC4000 Series 4-56 XC5200 4-200 boundary scan pins, using 4-64, 14-56 clock. See CCLK configuration sequence XC4000 Series 4-59 XC5200 4-203 control pins 14-34 daisy chain 14-26 debugging hints 14-31 mixed family 4-55, 14-33 XC3000 Series 4-307 XC4000 Series 4-55 XC5200 4-199 debugging 14-29 error protection 14-26 express mode daisy chain 4-56, 4-200 XC4000 Series specifications 4-77 XC4000EX 4-47, 4-55, 4-56, 4-62, 4-76 XC5200 4-197, 4-200 XC5200 specifications 4-201 guidelines 14-25 initiating reconfiguration 14-40 length count 4-56, 4-62, 4-203, 4-305, 14-25, 14-29 master modes, general 14-28 XC3000 Series 4-304, 4-307 XC4000 Series 4-54, 4-62 XC4000 Series specifications 4-79 XC5200 4-199 XC5200 specifications 4-205 XC6200 4-271 XC6200 specifications 4-276 master parallel mode debugging hints 14-30 XC3000 Series 4-312 XC3000 Series specifications 4-313 XC4000 Series 4-47, 4-70 XC4000 Series specifications 4-71 XC5200 4-197 master serial mode 4 T U V W X debugging hints 14-30 XC3000 Series 4-310 XC3000 Series specifications 4-311 XC4000 Series 4-66 XC4000 Series specifications 4-67 memory cell 4-291, 14-35 mode 14-28 selection of 14-28, 14-29 modes, table of XC3000 Series 4-304 XC4000 Series 4-54 XC5200 4-199 peripheral mode XC3000 Series 4-314 XC3000 Series specifications 4-315 peripheral modes, general 14-28 debugging hints 14-32 XC3000 Series 4-307 XC4000 Series 4-47, 4-54 XC5200 4-197, 4-199 pin descriptions XC3000 4-323 XC4000 Series 4-47 XC5200 4-197 pin functions during XC3000 Series 4-325 XC4000 Series 4-78 XC5200 4-204 power-on reset XC3000 Series 4-304 preamble 14-25 reducing time 14-40 slave serial mode 14-28 debugging hints 14-31 XC3000 Series 4-307, 4-316 XC3000 Series specifications 4-317 XC4000 Series 4-47, 4-55, 4-68 XC4000 Series specifications 4-69 XC5200 4-199 XC6200 4-271 specifications XC3000 Series 4-310 XC4000 Series 4-66 start-up sequence 14-26 XC3000 Series 14-22 XC4000 Series 4-60 XC5200 4-203 switching characteristics XC4000 Series 4-79 XC5200 4-205 synchronous peripheral mode XC4000 Series 4-47, 4-72 XC4000 Series specifications 4-73 Y Z Index A B C D E F G H I J K L M N O P Q R S XC5200 4-197 XC3000 Series 4-304, 14-22 XC4000 Series 4-54 XC5200 4-199 differences from XC4000 and XC3000 4-183 XC6200 4-268 XC8100 5-13 copyrighting bitstream 14-37 CPLD available I/O 11-1 core software 2-31 design flow 2-5 EPROM-based 14-5 FLASH-based 14-5 overview 1-3, 1-4, 14-5 product selection guide 1-8, 14-3, 14-5, 14-6 programmer 10-1 CQ packages package drawings 11-61 CQ100 package pinout table XC3000 Series 4-331 CQFP packages package drawings 11-61 CRC error checking selecting with MakeBits 4-57 XC4000 Series 4-56, 4-57 crystal oscillator XC3000 Series 4-303, 4-309, 14-19 CS in configuration debug 14-30 pin description XC6200 4-273 CS0, CS1 pin descriptions XC4000 Series 4-49 XC5200 4-198 CS0, CS1, CS2 pin descriptions XC3000 Series 4-324 customer support. See technical support cyclic redundancy check (CRC) XC4000 Series 4-57 D daisy chain 14-26 creating bitstream 4-55, 4-305 debugging hints 14-31 express mode XC4000EX 4-56 XC5200 4-200 mixed family 4-55, 14-33 T U V W X Y Z XC3000 Series 4-307 XC4000 Series 4-55 XC5200 4-199 data integrity 12-6 data pins pin descriptions XC3000 Series 4-324 XC4000 Series 4-49 XC5200 4-198 XC6200 4-273 data register 14-51 data stream. See bitstream DBUF symbol 5-9, 5-10 DC characteristics specifications XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 XC4000E 4-80 XC5200 4-206 XC5200L 4-250 XC6200 4-275 XC8100 at 3.3 V 5-34 XC8100 at 5 V 5-33 DD8 package package drawing 11-48 debugging configuration 14-29 DECODE attribute 4-31 decode logic. See cascade logic, edge decoder decoupling capacitor XC6200 4-274 delay input delay 14-45 XC3000 Series 14-15 of configuration after power-up XC4000 Series 4-60 optional input delay XC4000 Series 4-26 output XC4000 Series 14-10 with fast capture latch 4-27 demoboard FPGA 2-8, 2-36 design flow CPLD 2-5 DS-502 software package 2-4 DS-560 software package 2-5 FPGA 2-4 software 2-2 XC8100 5-2, 5-16 Design Manager 2-1 5 Index A B C D E F G H I J design security XC7300 3-78 XC9500 3-14 development system 2-1 overview 1-5 DIN in daisy chain XC3000 Series 4-307 XC4000 Series 4-55 XC5200 4-199 pin description XC3000 Series 4-324 XC4000 Series 4-49 XC5200 4-198 DIP package ceramic 11-48 plastic 11-27 direct interconnect XC3000 Series 4-296 XC4000EX 4-37 XC5200 4-184, 4-192 XC6200 4-256 disk space requirements programmer 10-1 See also hardware requirements DONE during power-up 14-35 express mode configuration 4-56 going High after configuration XC3000 Series 4-308 XC4000 Series 4-62 in configuration debug 14-30 not going High after configuration 14-29 pin description XC4000 Series 4-47 XC5200 4-197 DONE/PROG during power-up 14-35 pin description XC3000 Series 4-323 double-length routing XC4000 Series 4-35 XC5200 4-194 DOUT 14-25 in daisy chain express mode 4-56 XC3000 Series 4-307 XC4000 Series 4-55 XC5200 4-199 pin description XC3000 Series 4-324 XC4000 Series 4-49 XC5200 4-198 6 K L M N O P Q R S T U V W X dry bag 11-19 dry bake 11-19 DS-290 software package 2-32 DS-344 software package 2-32 DS-35 software package 2-32 DS-371 software package 2-33 DS-380 software package 2-32 DS-390 software package 2-32 DS-391 software package 2-32 DS-401 software package 2-35 DS-502 software package 2-30 design flow 2-4 DS-560 software package 2-31 design flow 2-5 DS-571 software package 2-34 dual-port RAM 4-17 E edge decoder 4-31 edge-triggered RAM 4-16 advantages of 4-14 EDIF 2-6 EIAJ standards 11-4 electrical parameters programmer 10-1 XC6200 4-274 electrostatic discharge (ESD) 12-7 E-mail addresses 13-4 endurance, XC9500 3-14 EPROM-based CPLD overview 14-5 error checking, bitstream 4-57, 4-309 XC3000 Series 4-309 XC4000 Series 4-57 express configuration mode CRC not supported 4-56 specifications XC4000 Series 4-77 XC5200 4-201 synchronized to DONE XC4000EX 4-62 XC4000EX 4-47, 4-55, 4-56, 4-62, 4-76 XC5200 4-197, 4-200 Extended System Alliance Series Viewlogic Stand-Alone (PC) 2-22 F factory floor life 11-19 failure analysis 12-3, 12-6 Y Z Index A B C D E F G H I J failures in time 12-2 fast capture latch 4-26 fast carry logic. See carry logic fast function blocks, XC7300 3-72 FastCLK buffer (BUFFCLK) 4-29, 4-45, 4-48 fast pin-to-pin path 4-28 with fast capture latch 4-26 FastCONNECT switch matrix 3-11 FastFlash technology XC9500 3-16 fastlane routing, XC6200 4-256 FCLK1 - FCLK4 clock diagram 4-42 pin descriptions XC4000EX 4-48 FD symbol 5-15 FD_SYNC symbol 5-15 FDC symbol 5-15 FDCE symbol 4-13 FDP symbol 5-6, 5-15 FIFO implementing in XC4000 Series RAM 4-14 FITs 12-2 FLASH-based CPLD overview 14-5 flip-flop in CLB XC3000 Series 4-294, 14-15 XC4000 Series 4-12, 4-13 XC5200 4-188 in IOB metastability 14-41 none in XC5200 4-196 XC3000 Series 4-293, 14-15 XC4000 Series 4-24, 4-27 in XC6200 function unit 4-258 in XC8100 CLC 5-6 Floorplanner 2-1 Flow Engine 2-1 forced air cooling vendors 11-14 Foundation Series 2-6, 2-11 Base System (PC) 2-12 with VHDL 2-13 Standard System (PC) 2-14 with VHDL 2-15 FPGA advantages of 14-3 available I/O 11-1 core software 2-30 data integrity 12-6 demoboard 2-8, 2-36 design flow 2-4 overview 1-3, 1-4 K L M N O P Q R S T U V W X Y Z product selection guide 1-6, 14-3, 14-6 programmer 10-1 security 14-36 function block XC7300 3-72, 3-74 XC9500 3-5 function generator in CLB XC3000 Series 4-295, 14-13 XC4000 Series 4-11 XC5200 4-188 in IOB XC4000EX 4-28 in XC6200 function unit 4-258 in XC8100 CLC 5-6 using as RAM 4-14 function unit 4-257 block diagram 4-258 flip-flop 4-258 specifications 4-276 G G1, G2 4-257 pin description XC6200 4-273 gate array advantages of FPGAs 1-3 advantages of HardWire 8-1 GCK1 - GCK4 pin descriptions 4-197 XC8100 5-7, 5-24 GCK1 - GCK8 clock diagram 4-42 pin descriptions XC4000EX 4-48 GClk 4-257, 4-261, 4-268, 4-272 pin description XC6200 4-273 GCLK symbol 14-18 GClr 4-257, 4-261 pin description XC6200 4-273 general routing matrix (GRM) XC5200 4-184, 4-185, 4-192, 4-194 glitch avoidance in XC3000 Series 14-14 power supply 14-35 Global 3-State (GTS) XC4000 Series 4-28, 4-46 global buffer specifications XC3000A 4-343 7 Index A B C D E F G H I J K L M N O P Q R S XC3000L 4-351 XC3100A 4-359 XC3100L 4-367 XC4000E 4-81 XC5200 4-207 XC6200 4-276 XC8100 5-38 XC3000 Series 4-302, 14-18 XC4000 Series 4-41 XC4000E 4-41 XC4000EX 4-43 XC5200 4-194 XC6200 4-257, 4-261 XC8100 5-7 Global Early buffer (BUFGE) 4-29, 4-44, 4-48 fast pin-to-pin path 4-28 with fast capture latch 4-26 Global Low-Skew buffer (BUFGLS) 4-43, 4-48 with fast capture latch 4-26 Global Reset (GR) in CLB XC5200 4-191 in CLC 5-6 Global Set/Reset (GSR) in CLB XC4000 Series 4-13 in IOB XC4000 Series 4-29 GR. See Global Reset GRM. See general routing matrix ground bounce XC4000 Series 14-10 GRST symbol 5-6 GSR. See Global Set/Reset GTS. See Global 3-state H Hardware Debugger 2-1 hardware requirements Alliance Series Base System OrCAD (PC) 2-16 Base System Viewlogic (PC) 2-18 Base System Viewlogic Stand-Alone (PC) 2-20 Extended System Viewlogic Stand-Alone (PC) 2-22 Standard System Cadence (Workstation) 2-26 Standard System Mentor V8 (PC) 2-24 Standard System OrCAD (PC) 2-17 Standard System Synopsys (Workstation) 2-25 Standard System third party 2-27 Standard System Viewlogic (PC) 2-19 Standard System Viewlogic (Workstation) 2-23 8 T U V W X Standard System Viewlogic Stand-Alone (PC) 2-21 DS-502 software package 2-30 DS-560 software package 2-31 Foundation Series Base System (PC) 2-12 Base System with VHDL (PC) 2-13 Standard System (PC) 2-14 Standard System with VHDL (PC) 2-15 XABEL-CPLD 2-34 X-BLOX 2-32 Xilinx ABEL 2-33 HardWire 8-1 advantages of 8-1 design verification 8-2 feature summary 8-1 guaranteed results 8-2 overview 1-4 packaging 8-3 product availability 8-3 HDC during power-up 14-35 pin description XC3000 Series 4-307, 4-323 XC4000 Series 4-48 XC5200 4-197 HDL 2-3, 2-7 heatsink vendors 11-14 hermeticity test 12-3 high temperature life test 12-2, 12-8 high-density function blocks XC7300 3-74 high-reliability (Hi-Rel) 9-1 overview 1-5 product availability 9-1 hold time on data input 14-45 XC4000 Series 4-26 hotline, technical support 13-2 HQ packages 11-17 package drawings 11-32 thermal data 11-11 HQ100 package package drawing 11-33 HQ160 package package drawing 11-34 HQ208 package package drawing 11-35 pinout table XC4000 Series 4-146 HQ240 package package drawing 11-36 pinout table XC4000 Series 4-154 Y Z Index A B C D E F G H I HQ304 package package drawing 11-37 pinout table XC4000 Series 4-160 HQFP packages package drawings 11-32 HT packages package drawings 11-38 HT100 package package drawing 11-39 HT144 package package drawing 11-40 HT176 package package drawing 11-41 HTFP packages package drawings 11-38 HW-130 programmer 10-1 hysteresis XC3000 Series 14-15 I I/O block see also input/output block see also input/output cell XC7300 3-76 XC9500 3-12 I/O count 11-1 XC3000 Series 4-326 XC4000 Series 4-176 XC5200 4-248 XC8100 5-25 I/V characteristics. See V/I characteristics IBUF symbol 5-9, 5-10 IEEE Standard 1149.1 14-57 IFD symbol 4-24 ILD symbol 4-24, 4-45 ILDFFDX symbol 4-27, 4-45 ILDFLDX symbol 4-27, 4-45 INFF symbol 4-45 INIT during power-up 14-35 in configuration debug 14-30, 14-32 in daisy chain 14-33 pin description XC3000 Series 4-323 XC4000 Series 4-48 XC5200 4-197 INIT attribute 4-19 initializing RAM 4-19 input/output block (IOB) clock XC3000 Series 14-17 J K L M N O P Q R S T U V W X Y Z CMOS input XC3000 Series 4-293 XC4000 Series 4-24 XC5200 4-196 CMOS output XC3000 Series 4-293, 14-16 XC4000 Series 4-27, 14-12 XC5200 4-196 delay on input 14-45 XC3000 Series 14-15 XC4000 Series 4-26 during configuration XC3000 Series 4-308 XC4000 Series 4-46 XC6200 4-271 fast capture latch 4-26 flip-flop metastability 14-41 function generator on output 4-28 maximum available I/O 11-1 XC3000 Series 4-326 XC4000 Series 4-176 XC5200 4-248 multiplexer on output 4-28 optional delay with fast capture latch 4-27 pull-down resistor XC4000 Series 4-29 XC6200 4-271 pull-up resistor XC3000 Series 4-293, 4-324 XC4000 Series 4-29 XC6200 4-271 rise/fall time XC3000 Series 14-15 routing associated with XC4000 Series 4-38 XC5200 4-185, 4-196 XC6200s 4-263 slew rate control XC3000 Series 4-293 XC4000 Series 4-28 XC5200 4-196 specifications XC3000A 4-346 XC3000L 4-354 XC3100A 4-362 XC3100L 4-370 XC4000E 4-92 XC5200 4-211 XC6200 4-277, 4-278 TTL input XC3000 Series 4-293 XC4000 Series 4-24 9 Index A B C D E F G H I J K L M N O P Q R S XC5200 4-196 TTL output none in XC5200 4-196 XC3000 Series 4-293 XC4000 Series 4-27 unused I/O XC4000 Series 4-46 VersaRing XC4000 Series 4-38 XC5200 4-185, 4-196 XC3000 Series 4-292, 14-15 clock 14-17 XC4000 Series 4-24 XC5200 4-196 differences from XC4000 and XC3000 4-183 XC6200 4-261 XC7300 3-76 XC9500 3-12 input/output cell (IOC) CMOS input 5-9, 5-12 CMOS output 5-10 maximum available I/O 5-25 pull-up resistor 5-10, 5-12 slew rate control 5-10 specifications 5-39 TTL input 5-9, 5-12 TTL output not supported 5-10 XC8100 5-9 in-system programming XC9500 3-14 interconnect. See routing IOBUF symbol 5-10 IPAD symbol 4-45 ISO9002 1-5, 12-1 J JEDEC standards 11-4 JTAG. See boundary scan junction temperature junction-to-ambient 11-7 junction-to-case 11-6 L latch fast capture latch 4-26 in CLB XC4000EX 4-12, 4-13 XC5200 4-188 in IOB none in XC5200 4-196 10 T U V W X XC3000 Series 4-293 XC4000 Series 4-24 in XC8100 CLC 5-6 latchup 12-8 LC. See logic cell LDC during power-up 14-35 in configuration debug 14-30 pin description XC3000 Series 4-307, 4-323 XC4000 Series 4-48 XC5200 4-197 LDCE symbol 4-13 LDE4 symbol 5-6 lead fatigue test 12-3 leakage current XC8100 5-12 length count configuration debugging hints 14-32 error in 14-29 XC3000 Series 4-305 XC4000 Series 4-56, 4-62, 4-74 XC5200 4-203 level-sensitive RAM 4-19 library symbol 3-state buffer BUFE, XC8100 5-6 BUFT, XC4000 Series 4-30 WAND1 4-30 WOR2AND 4-30 3-state output buffer OBUFE, XC8100 5-10 AND-gate in IOB OAND2 4-28, 4-29 boundary scan BSCAN 4-48, 4-53 TCK, TDI, TDO, TMS 4-48, 4-53 fast capture latch ILDFFDX 4-27, 4-45 ILDFLDX 4-27, 4-45 flip-flop FD, XC8100 5-15 FD_SYNC, XC8100 5-15 FDC, XC8100 5-15 FDCE, XC4000 Series CLB 4-13 FDP, XC8100 5-6, 5-15 IFD, XC4000 Series IOB 4-24 Global 3-State STARTUP 4-28 global buffer ACLK, XC3000 Series 14-18 BUF1X, XC8100 5-7 BUFEDGE, XC8100 5-7 Y Z Index A B C D E F G H I J BUFFCLK, XC4000EX 4-45, 4-48 BUFG, XC5200 4-194 BUFGE, XC4000EX 4-45, 4-48 BUFGLS, XC4000EX 4-43, 4-48 BUFGP, XC4000E 4-41 BUFGS, XC4000E 4-41 BUFROW, XC8100 5-7 GCLK, XC3000 Series 14-18 global reset GRST, XC8100 5-6 Global Set/Reset STARTUP 4-13 input buffer DBUF, XC8100 5-9, 5-10 IBUF, XC8100 5-9, 5-10 input flip-flop INFF, XC4000 Series 4-45 input latch ILD, XC4000 Series 4-45 input pad IPAD 4-45 input/output buffer IOBUF, XC8100 5-10 latch ILD, XC4000 Series IOB 4-24 LDCE, XC4000EX CLB 4-13 mode pins MD0, MD1, MD2 4-54 oscillator OSC4, XC4000 Series 4-31 OSC52, XC5200 4-191 output buffer OBUF, XC8100 5-10 output multiplexer OMUX2 4-29 readback READBACK 4-64 register file LDE4, XC8100 5-6 resistive 3-state output buffer RBUFE, XC8100 5-10 resistive output buffer RBUF, XC8100 5-10 resistor PULLDOWN 4-29 PULLUP 4-29 synthesis library, XC8100 5-19 wide decoder WAND1 4-31 LIM. See local interconnect matrix LOC attribute 4-41, 4-43, 4-45 local interconnect matrix (LIM) XC5200 4-184, 4-192 K L M N O P Q R S T U V W X Y Z logic cell (LC) XC5200 4-182, 4-184 longline specifications XC4000E 4-83 XC5200 4-208 XC3000 Series 4-300, 14-15, 14-17 XC4000 Series 4-37 XC5200 4-194 lookup table (LUT). See function generator low voltage device XC4000 Series 4-5, 4-6 XC4000 Series driven by 5V 4-24 XC4000 Series driving 5V TTL 4-27 XC8100 5-13 LPM 2-6 M M0, M1, M2. See mode pins M0/RTRIG pin description XC3000 Series 4-323 M1/RDATA pin description XC3000 Series 4-323 M2 pin description XC3000 Series 4-323 macrocell XC9500 3-6 magic interconnect XC6200 4-257 MakeBits program bitstream generation XC3000 Series 4-306 XC4000 Series 4-57 CCLK frequency 4-56, 4-66 CRC error checking 4-57 crystal oscillator selection 4-309 express mode 4-56, 4-76 input thresholds XC4000 Series 4-24 output voltage levels XC4000 Series 4-27 pull-up on DONE pin 4-47, 4-63 readback options 4-65 start-up timing 4-60, 4-62 XC3000 Series 4-306 XC4000 Series 4-55 tie option 4-306 MakePROM program combining bitstreams 4-55, 4-305, 4-306 11 Index A B C D E F G H I J manufacturers. See vendors map register XC6200 4-268 mask register XC6200 4-268 mass, package 11-15 master configuration modes, general 14-28 XC3000 Series 4-304, 4-307 XC4000 Series 4-54, 4-62 XC4000 Series specifications 4-79 XC5200 4-199 XC5200 specifications 4-205 XC6200 4-271 XC6200 specifications 4-276 master parallel configuration mode debugging hints 14-30 specifications XC3000 Series 4-313 XC4000 Series 4-71 XC3000 Series 4-312 XC4000 Series 4-47, 4-70 XC5200 4-197 Master Reset (MR) 5-6 pin description 5-24 master serial configuration mode debugging hints 14-30 specifications XC3000 Series 4-311 XC4000 Series 4-67 XC3000 Series 4-310 XC4000 Series 4-66 maximum I/O 11-1 XC3000 Series 4-326 XC4000 Series 4-176 XC5200 4-248 XC8100 5-25 MD0, MD1, MD2 symbols 4-54 Mean Time Between Failures (MTBF) metastability 14-42 MEDDELAY attribute 4-26, 4-27 memory cell, configuration 4-291, 12-6, 14-35 memory requirements programmer 10-1 Mentor Graphics 2-2, 2-7 software 2-24, 2-32 metal quad packages package drawings 11-71 metastability 14-41 XC8100 5-15 MicroVia 5-2, 5-12, 5-14 MIL-STD-883B 1-5 mode pins 14-28 pin descriptions 12 K L M N O P Q R S T U V W X Y XC4000 Series 4-47 XC5200 4-197 XC3000 Series 4-304 XC4000 Series 4-54 XC5200 4-199 moisture sensitivity in surface mount packages 11-18 MQ packages package drawings 11-71 MQ208 package package drawing 11-71 MQ240 package package drawing 11-72 MR. See Master Reset multiplexer XC4000EX IOB 4-28 XC6200 4-264 N nearest neighbor routing. See direct interconnect NODELAY attribute 4-26, 4-27 O OAND2 symbol 4-28, 4-29 OBUF symbol 5-10 OBUFE symbol 5-10 octal routing 4-40 OE in configuration debug 14-30 pin description XC6200 4-273 OMUX2 symbol 4-29 on-chip oscillator. See oscillator, on-chip one-time programmable (OTP) 5-2 testing 5-15 open-drain output 4-28 operating conditions specifications XC1700D 6-6 XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 XC4000E 4-80 XC5200 4-206 XC5200L 4-250 XC6200 4-275 XC8100 5-33 OrCAD 2-2, 2-7 software 2-16, 2-17, 2-32 ordering information Z Index A B C D E F G H I J software 2-9 XC1700D 6-10 XC3000 Series 4-340 XC3000A 4-348 XC3000L 4-356 XC3100A 4-364 XC3100L 4-372 XC4000 Series 4-178 XC5200 4-248 XC8100 5-42 OSC4 symbol 4-31 OSC52 symbol 4-191 oscillator crystal XC3000 Series 4-303, 4-309, 14-19 on-chip 14-35 XC3000 Series 14-21 XC4000 Series 4-31 XC5200 4-183, 4-191 OTP. See one-time programmable output current XC3000 Series 14-17 XC4000 Series 4-27, 4-46, 14-9 XC5200 4-196 XC8100 5-10 output multiplexer in XC4000EX IOB 4-28 output slew rate XC3000 Series 4-293 XC4000 Series 4-28 XC5200 4-196 XC8100 5-10 overshoot 14-47 P package availability high-reliability 9-1 XC3000 Series 4-339 XC3000A 4-348 XC3000L 4-356 XC3100A 4-364 XC3100L 4-372 XC4000 Series 4-174 XC5200 4-248 XC6200 4-286 XC8100 5-42 XC9500 3-5 package drawing BG225 package 11-45 BG352 package 11-46 BG432 package 11-47 CB100 package XC3000 Series 11-61 K L M N O P Q R S T U V W X Y Z XC4000 Series 11-62 CB164 package XC3000 Series 11-63 XC4000 Series 11-64 CB196 package 11-65 CB228 package 11-66 CC20 package 11-67 DD8 package 11-48 HQ100 package 11-33 HQ160 package 11-34 HQ208 package 11-35 HQ240 package 11-36 HQ304 package 11-37 HT100 package 11-39 HT144 package 11-40 HT176 package 11-41 MQ208 package 11-71 MQ240 package 11-72 PC20 package 11-31 PC28 package 11-31 PC44 package 11-31 PC68 package 11-31 PC84 package 11-31 PD48 package 11-28 PD8 package 11-27 PG120 package 11-52 PG132 package 11-53 PG144 package 11-54 PG156 package 11-55 PG175 package 11-56 PG191 package 11-57 PG223 package 11-58 PG299 package 11-59 PG411 package 11-60 PG68 package 11-49 PG84 package 11-50 PP132 package 11-68 PP175 package 11-69 PQ100 package 11-33 PQ160 package 11-34 PQ208 package 11-35 PQ240 package 11-36 PQ304 package 11-37 PQ44 package 11-32 SO8 package 11-29 TQ100 package 11-39 TQ144 package 11-40 TQ176 package 11-41 TQ44 package 11-38 VO8 package 11-30 VQ100 package 11-44 VQ44 package 11-42 VQ64 package 11-43 13 Index A B C D E F G H WC44 package 11-70 WC68 package 11-70 WC84 package 11-70 WG84 package 11-51 packaging 11-1 available I/O 11-1 bar code 11-22 data acquisition 11-7 dimensions 11-4 drawings 11-26 dry bag 11-19 dry bake 11-19 EIAJ standards 11-4 EIJ standard board layout 11-5 factory floor life 11-19 handling and storage 11-19 HardWire 8-3 JEDEC standards 11-4 mass 11-15 moisture sensitivity 11-18 options 11-3 orientation 11-5 physical dimensions 11-26 reflow soldering 11-23 tape & reel packing 11-21 thermal characteristics 11-6 thermal database 11-7 thermal management 11-6 thermal resistance applying data 11-9 table of 11-8 thermally enhanced 11-17 vendors 11-14, 11-25 weight 11-15 PC packages package drawings 11-31 PC20 package package drawing 11-31 PC28 package package drawing 11-31 PC44 package package drawing 11-31 pinout diagram XC8100 5-30 pinout table XC3000 Series 4-327 PC68 package package drawing 11-31 pinout table XC3000 Series 4-329 PC84 package package drawing 11-31 pinout diagram 14 I J K L M N O P Q R S T U V W X Y XC8100 5-31 pinout table XC3000 Series 4-330 XC4000 Series 4-133 PCI compatibility XC4000 Series 4-8 PD48 package package drawing 11-28 PD8 package package drawing 11-27 performance XC3000 Series 4-320 XC5200 4-185 XC8100 5-4 peripheral configuration mode specifications XC3000 Series 4-315 XC3000 Series 4-314 peripheral configuration modes, general 14-28 debugging hints 14-32 specifications XC4000 Series 4-79 XC5200 4-205 XC6200 4-276 XC3000 Series 4-307 XC4000 Series 4-47, 4-54 XC5200 4-197, 4-199 peripheral configuration modes. See also asynchronous peripheral, synchronous peripheral PG packages package drawings 11-49, 11-68 PG120 package package drawing 11-52 pinout table XC4000 Series 4-136 PG132 package package drawing 11-53 pinout table XC3000 Series 4-332 PG144 package package drawing 11-54 PG156 package package drawing 11-55 pinout table XC4000 Series 4-140 PG175 package package drawing 11-56 pinout table XC3000 Series 4-335 PG191 package package drawing 11-57 pinout table XC4000 Series 4-149 Z Index A B C D E F G H I PG223 package package drawing 11-58 pinout table XC4000 Series 4-149 PG299 package package drawing 11-59 pinout table XC4000 Series 4-157 thermal resistance 11-12 PG411 package package drawing 11-60 pinout table XC4000 Series 4-166 PG68 package package drawing 11-49 PG84 package package drawing 11-50 pinout table XC3000 Series 4-329 PGA packages package drawings 11-49, 11-68 PGCK1 - PGCK4 clock diagram 4-42 pin descriptions 4-48 physical dimensions of packages 11-26 pin descriptions functions during configuration XC3000 Series 4-325 XC4000 Series 4-78 XC5200 4-204 XC3000 Series 4-323 XC4000 Series 4-46 XC6200 4-273 pin locking XC9500 3-13 pinout diagram BG225 package XC8100 5-32 PC44 package XC8100 5-30 PC84 package XC8100 5-31 PQ100 package XC8100 5-31 PQ160 package XC8100 5-32 VQ44 package XC8100 5-30 XC8100 5-30 pinout table BG225 package XC4000 Series 4-152 BG352 package J K L M N O P Q R S XC4000 Series BG432 package XC4000 Series CQ100 package XC3000 Series device-specific XC3000 Series XC4000 Series XC5200 4-223 XC6200 4-282 XC8100 5-24 HQ208 package XC4000 Series HQ240 package XC4000 Series HQ304 package XC4000 Series package-specific XC3000 Series XC4000 Series PC44 package XC3000 Series PC68 package XC3000 Series PC84 package XC3000 Series XC4000 Series PG120 package XC4000 Series PG132 package XC3000 Series PG156 package XC4000 Series PG175 package XC3000 Series PG191 package XC4000 Series PG223 package XC4000 Series PG299 package XC4000 Series PG411 package XC4000 Series PG84 package XC3000 Series PQ100 package XC3000 Series XC4000 Series PQ160 package XC3000 Series XC4000 Series PQ208 package XC3000 Series T U V W X Y Z 4-163 4-170 4-331 4-338 4-97 4-146 4-154 4-160 4-326 4-133 4-327 4-329 4-330 4-133 4-136 4-332 4-140 4-335 4-149 4-149 4-157 4-166 4-329 4-331 4-134 4-334 4-142 4-337 15 Index A B C D E F G H XC4000 Series 4-146 PQ240 package XC4000 Series 4-154 TQ100 package XC3000 Series 4-331 TQ144 package XC3000 Series 4-333 XC4000 Series 4-138 TQ176 package XC3000 Series 4-336 XC4000 Series 4-144 VQ100 package XC3000 Series 4-331 XC4000 Series 4-135 VQ64 package XC3000 Series 4-328 XC3000 Series 4-326 XC3195 4-338 XC4000 Series 4-97 XC4003E 4-97 XC4005E/L 4-98 XC4006E 4-100 XC4008E 4-102 XC4010E/L 4-104 XC4013E/L 4-107 XC4020E 4-110 XC4025E 4-113 XC4028EX/XL 4-113 XC4036EX/XL 4-118 XC4044EX/XL 4-123 XC4052XL 4-128 XC5200 4-223 XC5202 4-223 XC5204 4-226 XC5206 4-230 XC5210 4-235 XC5215 4-241 XC6200 4-282 XC6216 4-282 XC73108 3-121 XC73144 3-132 XC7318 3-87 XC7336/Q 3-96 XC7354 3-105 XC7372 3-113 XC8100 5-24, 5-25 XC8101 5-26 XC8103 5-27 XC8106 5-28 XC8109 5-29 XC95108 3-31 XC95144 3-37 XC95180 3-43 16 I J K L M N O P Q R S T U V W X XC95216 3-51 XC95288 3-59 XC9536 3-21 XC9572 3-25 pin-to-pin specifications XC4000E 4-90 XC5200 4-210 XC6200 4-277 XC8100 5-40 plastic packages DIP package drawings 11-27 PGA package drawings 11-68 PLCC packages package drawings 11-31 power consumption reduction of 11-14 XC3000 Series 4-322, 14-18 XC4000 Series 14-12 XC6200 4-274 XC8100 5-12 power distribution XC3000 Series 4-321 XC4000 Series 4-46 power-down mode none in XC4000 Series 4-46 none in XC5200 4-183 XC3000 Series 4-304, 4-322, 14-21, 14-37 power-on reset specifications XC6200 4-276 XC3000 Series 4-304 XC6200 4-272 power-up 14-35 power-up. See also start-up after configuration PP132 package package drawing 11-68 PP175 package package drawing 11-69 PQ packages package drawings 11-32 thermal data 11-11 PQ100 package package drawing 11-33 pinout diagram XC8100 5-31 pinout table XC3000 Series 4-331 XC4000 Series 4-134 PQ160 package package drawing 11-34 pinout diagram Y Z Index A B C D E F G H I J K L M N O P Q R S XC8100 5-32 pinout table XC3000 Series 4-334 XC4000 Series 4-142 PQ208 package package drawing 11-35 pinout table XC3000 Series 4-337 XC4000 Series 4-146 PQ240 package package drawing 11-36 pinout table XC4000 Series 4-154 PQ304 package package drawing 11-37 PQ44 package package drawing 11-32 PQFP packages package drawings 11-32 preliminary specifications, definition of 1-1, 4-80, 4-206 Primary Global Buffer (BUFGP) 4-41, 4-48 product availability HardWire 8-3 high-reliability 9-1 XC3000 Series 4-339 XC3000A 4-348 XC3000L 4-356 XC3100A 4-364 XC3100L 4-372 XC4000 Series 4-174 XC5200 4-248 XC6200 4-286 XC7300 3-71 XC8100 5-42 XC9500 3-4 product qualification requirements 12-4 product selection guide CPLD 1-8, 14-3, 14-5, 14-6 FPGA 1-6, 14-3, 14-6 product term allocator XC7300 3-74 XC9500 3-8 PROGRAM during power-up 14-35 in configuration debug 14-30 inititating reconfiguration 14-40 pin description XC4000 Series 4-47 XC5200 4-197 programmable switch matrix (PSM) XC3000 Series 4-296 XC4000 Series 4-35 XC6200 4-259 T U V W X Y Z programmer 10-1 algorithms 10-1 software 10-1 specifications 10-1 programming, in-system XC9500 3-14 programming. See configuration PROM bitstream generation XC4000 Series 4-55 configuration XC3000 Series 4-310, 4-312 XC4000 Series 4-6, 4-66, 4-70, 4-74 in configuration debug 14-30 overview 1-5 programmer 10-1 size XC4000E 4-57 XC4000EX 4-58 PROM Formatter 2-1 pseudo daisy chain for express mode XC4000EX 4-56 XC5200 4-200 pull-down resistor enabling boundary scan 14-56 IOB XC4000 Series 4-29 XC6200 4-271 PULLDOWN symbol 4-29 pull-up resistor IOB XC3000 Series 4-293, 4-324 XC4000 Series 4-29, 4-47 XC5200 4-197 XC6200 4-271 IOC 5-10, 5-12 longline none in XC5200 4-194 XC3000 Series 4-302 XC4000 Series 4-37 PULLUP symbol 4-29 PWRDWN 14-21 battery backup mode 14-37 in configuration debug 14-30, 14-32 pin description XC3000 Series 4-323 Q quad routing 4-36 qualification requirements 12-4 quality assurance 12-1 17 Index A B C D E F G H I J K L M N O P Q R S R 18 U V W X Y during power-up 14-35 in configuration debug 14-30, 14-32 in daisy chain 14-33 inititating reconfiguration 14-40 pin description XC3000 Series 4-323 XC6200 4-273 rise time requirement in XC3000 Series 14-23 RAM asynchronous 4-19 configuration options XC4000 Series 4-14 dual-port 4-17 edge-triggered 4-16 in CLB 4-14 initialization of 4-19 level-sensitive 4-19 readback of contents 4-65 setting mode 4-14 specifications XC4000E 4-86 synchronous 4-16 RBUF symbol 5-10 RBUFE symbol 5-10 RCLK pin description XC3000 Series 4-324 XC4000 Series 4-47 XC5200 4-197 Rd/Wr pin description XC6200 4-273 RDY/BUSY in configuration debug 14-31 pin description XC3000 Series 4-324 XC4000 Series 4-47 XC5200 4-197 readback CRC error checking XC4000 Series 4-57 specifications XC3000 Series 4-318 XC3000 Series 4-308 XC4000 Series 4-47, 4-64 XC5200 4-197 XChecker cable 4-65 READBACK symbol 4-64 reconfiguration XC4000 Series 4-7 reconfiguration. See also configuration reflow soldering 11-23 register access XC6200 4-267 Register Clear, XC6200 4-261 register, map, XC6200 4-268 register, mask, XC6200 4-268 reliability 12-2 RESET T reset XC3000 Series 4-309 XC4000 Series 4-46 See also Global Set/Reset XC6200 4-261 resistance to solvents test 12-3 resistor IOB XC3000 Series 4-293, 4-324 XC4000 Series 4-29 XC6200 4-271 IOC 5-10, 5-12 pull-up on longline none in XC5200 4-194 XC3000 Series 4-302 XC4000 Series 4-37 with crystal oscillator 14-20 rise/fall time on input XC3000 Series 14-15 routing bidirectional (bidi) buffer 4-296 buffered switch matrix 4-36 direct interconnect XC3000 Series 4-296 XC4000EX 4-37 XC5200 4-184, 4-192 XC6200 4-256 double-length XC4000 Series 4-35 XC5200 4-194 fastlane, XC6200 4-256 global buffer XC4000E 4-41 XC4000EX 4-43 IOB routing XC6200 4-263 longline XC3000 Series 4-300, 14-15, 14-17 XC4000 Series 4-37 XC5200 4-194 magic interconnect XC6200 4-257 multiplexer, XC6200 4-264 octal 4-40 programmable switch matrix (PSM) Z Index A B C D E F G H I J K L M N O P Q R S XC3000 Series 4-296 XC4000 Series 4-35 XC6200 4-259 quad 4-36 single-length XC4000 Series 4-35 XC5200 4-194 VersaRing (IOB routing) XC4000 Series 4-38 XC5200 4-185, 4-196 XC3000 Series 4-295, 14-15 XC4000 Series 4-32 XC5200 4-184, 4-192 differences from XC4000 and XC3000 4-183 XC6200 4-256 XC8100 5-6 RS pin description XC4000 Series 4-49 XC5200 4-198 S salt atmosphere test 12-3 SC7300 high-density function blocks 3-74 SECE pin description XC6200 4-273 SEClk pin description XC6200 4-273 Secondary Global Buffer (BUFGS) 4-41, 4-48 security 3-14, 3-78, 14-36 SEData pin description XC6200 4-273 selection guide CPLD 1-8 FPGA 1-6 SEReset pin description XC6200 4-273 Serial pin description XC6200 4-273 Series 8000 software 5-2, 5-16 service overview 1-5 setup time on data input 14-42, 14-45 XC3000 Series 14-15 XC4000 Series 4-26 SGCK1 - SGCK4 T U V W X Y Z clock diagram 4-42 pin description 4-48 single-length routing XC4000 Series 4-35 XC5200 4-194 sink current. See output current slave serial configuration mode 14-28 debugging hints 14-31 specifications XC3000 Series 4-317 XC4000 Series 4-69, 4-79 XC5200 4-205 XC6200 4-276 XC3000 Series 4-307, 4-316 XC4000 Series 4-47, 4-55, 4-68 XC5200 4-199 XC6200 4-271 slew rate XC3000 Series 4-293 XC4000 Series 4-28 XC5200 4-196 XC73144 3-128 XC8100 5-10 SMD. See Standard Microcircuit Drawing SO8 package package drawing 11-29 socket vendors 11-25 soft startup XC3000 Series 4-309 XC4000 Series 4-28 software 2-35 ABEL 2-6, 2-7 Alliance Program 2-7 Alliance Series 2-6, 2-7, 2-11 Base System OrCAD (PC) 2-16 Base System Viewlogic (PC) 2-18 Base System Viewlogic Stand-Alone (PC) 2-20 Extended System Viewlogic Stand-Alone (PC) 2-22 Standard System Cadence (Workstation) 2-26 Standard System Mentor V8 (Workstation) 2-24 Standard System OrCAD (PC) 2-17 Standard System Synopsys (Workstation) 2-25 Standard System third party 2-27 Standard System Viewlogic (PC) 2-19 Standard System Viewlogic (Workstation) 2-23 Standard System Viewlogic Stand-Alone (PC) 2-21 Cadence 2-2, 2-7, 2-26 CPLD core 2-31 design flow 2-2 Design Manager 2-1 DS-290 2-32 19 Index A B C D E F G H I J K L M N O P Q R S DS-344 2-32 DS-35 2-32 DS-371 2-33 DS-380 2-32 DS-390 2-32 DS-391 2-32 DS-401 2-35 DS-502 2-30 DS-502 design flow 2-4 DS-560 2-31 DS-560 design flow 2-5 DS-571 2-34 EDIF 2-6 Floorplanner 2-1 Flow Engine 2-1 Foundation Series 2-6, 2-11 Base System (PC) 2-12 Base System with VHDL (PC) 2-13 Standard System (PC) 2-14 Standard System with VHDL (PC) 2-15 FPGA core 2-30 Hardware Debugger 2-1 HDL 2-3, 2-7 LPM 2-6 Mentor Graphics 2-2, 2-7, 2-24, 2-32 OrCAD 2-2, 2-7, 2-16, 2-17, 2-32 ordering information 2-9 overview 1-5, 2-1 programmer 10-1 PROM Formatter 2-1 Synopsys 2-7, 2-25 interface (XSI) 2-35 synthesis 2-7 Timing Analyzer 2-1, 2-3 updates 2-5 Verilog 2-6, 2-35 VHDL 2-6, 2-7, 2-13, 2-15, 2-35 Viewlogic 2-2, 2-6, 2-7, 2-18, 2-19, 2-20, 2-21, 2-22, 2-23, 2-32 XABEL-CPLD 2-34 X-BLOX 2-3, 2-8, 2-32 XC6200 4-267 XC8000 Series 2-6, 2-8 Xilinx ABEL 2-2, 2-8, 2-33, 2-34 SOIC packages package drawings 11-29 solderability test 12-3 specifications absolute maximum ratings XC1700D 6-6 XC3000A 4-343 XC3000L 4-351 XC3100A 4-359 20 T U V W X XC3100L 4-367 XC4000E 4-81 XC5200E 4-207 XC5200L 4-250 XC6200 4-275 XC8100 5-33 advance, definition of 1-1, 4-80, 4-206 boundary scan XC4000E 4-96 CLB XC3000A 4-344 XC3000L 4-352 XC3100A 4-360 XC3100L 4-368 XC4000E 4-84 XC5200 4-209 CLC XC8100 5-35 configuration XC3000 Series 4-310 XC4000 Series 4-66 CPU interface XC6200 4-278 DC characteristics XC1700D 6-6 XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 XC4000E 4-80 XC5200 4-206 XC5200L 4-250 XC6200 4-275 XC8100 at 3.3 V 5-34 XC8100 at 5 V 5-33 function unit 4-276 global buffer XC3000A 4-343 XC3000L 4-351 XC3100A 4-359 XC3100L 4-367 XC4000E 4-81 XC5200 4-207 XC6200 4-276 XC8100 5-38 IOB XC3000A 4-346 XC3000L 4-354 XC3100A 4-362 XC3100L 4-370 XC4000E 4-92 XC5200 4-211 XC6200 4-277 Y Z Index A B C D E F G H I J IOC XC8100 5-39 longline XC4000E 4-83 XC5200 4-208 operating conditions XC1700D 6-6 XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 XC4000E 4-80 XC5200 4-206 XC5200L 4-250 XC6200 4-275 XC8100 5-33 pin-to-pin XC4000E 4-90 XC5200 4-210 XC6200 4-277 XC8100 5-40 power-on reset XC6200 4-276 preliminary, definition of 1-1, 4-80, 4-206 programmer 10-1 RAM XC4000E 4-86 readback XC3000 Series 4-318 routing XC6200 4-278 wide edge decoder XC4000E 4-82 XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 XC4000E 4-80 XC4000EX not yet available XC4000L not yet available XC4000XL not yet available XC5200 4-206 XC5200L 4-250 XC6200 4-275 speed grades available high-reliability 9-1 XC3000 Series 4-339 XC3000A 4-348 XC3000L 4-356 XC3100A 4-364 K L M N O P Q R S T U V W X Y Z XC3100L 4-372 XC4000 Series 4-174 XC5200 4-248 XC8100 5-42 SRAM. See FPGA Standard Microcircuit Drawing (SMD) 1-5, 9-1 Standard System Alliance Series Cadence (Workstation) 2-26 Mentor V8 (Workstation) 2-24 OrCAD (PC) 2-17 Synopsys (Workstation) 2-25 third party 2-27 Viewlogic (PC) 2-19 Viewlogic (Workstation) 2-23 Viewlogic Stand-Alone (PC) 2-21 Foundation Series (PC) 2-14 with VHDL 2-15 start-up after configuration 14-26 XC3000 Series 14-22 XC4000 Series 4-60 XC5200 4-203 STARTUP symbol implementing Global 3-State 4-28 implementing Global Set/Reset 4-13 support 13-1 technical support hotline 1-5, 13-2 training 13-6 support. See also technical support surface mount packages moisture sensitivity 11-18 switch matrix, programmable (PSM) XC3000 Series 4-296 XC4000 Series 4-35 XC6200 4-259 synchronous peripheral configuration mode specifications XC4000 Series 4-73 XC4000 Series 4-47, 4-72 XC5200 4-197 synchronous RAM 4-16 advantages of 4-14 Synopsys 2-7 interface (XSI) 2-35 software 2-25 synthesis 2-7 synthesis symbols in XC8100 5-19 T TAP controller 14-51 tape & reel packing 11-21 TCK,TDI,TDO,TMS. See boundary scan 21 Index A B C D E F G H TCLKIN 14-18 pin description XC3000 Series 4-324 technical support 13-1 BBS 13-3 hotline 1-5, 13-2 overview 1-5 publications 13-5 Web site 13-3 XDOCS E-mail system 13-3 XFACTS FAX system 13-3 X-TALX Xilinx network 13-3 temperature cycling test 12-3 test access port (TAP) 14-51 testing 12-2 thermal characteristics 11-1, 11-6 thermal data PQ/HQ packages 11-11 thermal management 11-6 thermal resistance applying data 11-9 table of 11-8 thermal shock test 12-3 theta-JA 11-7 theta-JC 11-6 time-to-market 1-3 Timing Analyzer 2-1, 2-3 timing model XC7300 3-78 XC9500 3-15 TQ packages package drawings 11-38 TQ100 package package drawing 11-39 pinout table XC3000 Series 4-331 TQ144 package package drawing 11-40 pinout table XC3000 Series 4-333 XC4000 Series 4-138 TQ176 package package drawing 11-41 pinout table XC3000 Series 4-336 XC4000 Series 4-144 TQ44 package package drawing 11-38 TQFP packages package drawings 11-38 training 1-5, 13-1, 13-6 locations 13-8 TrueMap 5-2 22 I J K L M N O P Q R S T U V W X Y TSOP packages package drawings 11-30 TTL input XC3000 Series 4-293, 4-308 XC4000 Series 4-24 XC5200 4-196 XC8100 5-9, 5-12 TTL output none in XC5200 4-196 none in XC8100 5-10 XC3000 Series 4-293 XC4000 Series 4-27 U unbiased pressure pot test 12-2 undershoot 14-47 universal interconnect matrix XC7300 3-76 unused I/O XC4000 Series 4-46 updates 2-5 user registers in boundary scan 14-53 V V/I characteristics XC3000 Series 14-16 XC4000 Series 14-9 XC8100 5-10 vendors forced air cooling 11-14 heatsink 11-14 socket 11-25 Verilog 2-6, 2-35 VersaBlock 4-184 VersaRing XC4000 Series 4-38 XC5200 4-185, 4-196 VHDL 2-6, 2-7 software 2-13, 2-15, 2-35 Viewlogic 2-2, 2-6, 2-7 software 2-18, 2-19, 2-20, 2-21, 2-22, 2-23, 2-32 VO8 package package drawing 11-30 VPP in configuration debug 14-30 VQ packages package drawings 11-42 VQ100 package package drawing 11-44 pinout table Z Index A B C D E F G H I J XC3000 Series 4-331 XC4000 Series 4-135 VQ44 package package drawing 11-42 pinout diagram XC8100 5-30 VQ64 package package drawing 11-43 pinout table XC3000 Series 4-328 VQFP packages package drawings 11-42 W Wait pin description XC6200 4-273 WAND1 symbol 4-30, 4-31 WC packages package drawings 11-70 WC44 package package drawing 11-70 WC68 package package drawing 11-70 WC84 package package drawing 11-70 Web site for Xilinx 1-1, 1-5, 13-3 WebLINX 1-1, 1-5, 13-3 weight, package 11-15 WG84 package package drawing 11-51 wide edge decoder 4-31 specifications XC4000E 4-82 wildcard register, XC6200 4-270 windowed packages ceramic 11-51 CLCC package drawings 11-70 wire. See routing WOR2AND symbol 4-30 World Wide Web site for Xilinx 1-1, 1-5, 13-3 WS pin description XC3000 Series 4-324 XC4000 Series 4-49 XC5200 4-198 X XABEL-CPLD 2-34 K L M N O P Q R S T U V W X Y Z XACT development system 2-1 XACTstep software overview 1-5, 2-1 X-BLOX 2-3, 2-8, 2-32 XC1700 programmer 10-1 XC1700D data sheet 6-1 XC2000 14-3 overview 14-4 use not recommended 1-1 XC3000 14-3 overview 14-4 use not recommended 1-1 XC3000 Series 4-289, 4-309, 14-3, 14-13 3-state buffer 4-293, 4-302, 14-17 5-input function 14-13 available I/O 4-326 battery backup 14-21, 14-37 CCLK frequency variation 14-21 CMOS input 4-293 CMOS output 4-293, 14-16 configurable logic block (CLB) 4-294, 14-13 configuration 4-304, 14-22 debugging hints 14-30 specifications 4-310 crystal oscillator 4-303, 4-309, 14-19 feature summary 4-289 glitch avoidance 14-14 global buffer 4-302, 14-18 hysteresis 14-15 input/output block (IOB) 4-292, 14-15 internal bus contention 14-17 on-chip oscillator 14-21 ordering information 4-340 output current 14-17 overview 14-4 performance 4-320 pin descriptions 4-323 pinout tables 4-326 power consumption 4-322, 14-18 power distribution 4-321 power-down mode 4-304, 4-322 product availability 4-339 readback 4-308 rise/fall time 14-15 routing 4-295 soft startup 4-309 specifications configuration 4-310 XC3000A 4-342 XC3000L 4-350 XC3100A 4-358 XC3100L 4-366 23 Index A B C D E F G H I TTL input 4-293 TTL output 4-293 V/I characteristics 14-16 XC3000A 4-341 feature summary 4-341 ordering information 4-348 overview 4-290 product availability 4-348 specifications 4-342 XC3000L 4-349 feature summary 4-349 ordering information 4-356 overview 4-290 product availability 4-356 specifications 4-350 XC3100 14-3 overview 14-4 use not recommended 1-1 XC3100A 4-357 feature summary 4-357 ordering information 4-364 overview 4-290, 14-4 product availability 4-364 specifications 4-358 XC3100L 4-365 feature summary 4-365 ordering information 4-372 overview 4-290, 14-4 product availability 4-372 specifications 4-366 XC3195 pinout table 4-338 XC4000 overview 14-4 use not recommended 1-1 XC4000 Series 4-5, 4-57, 14-3 3-state buffer 4-29 available I/O 4-176 bitstream format 4-56 boundary scan 4-50, 14-49 BSDL files 14-57 carry logic 4-21 CMOS input 4-24 CMOS output 4-27, 14-12 configurable logic block (CLB) 4-11 configuration 4-54 debugging hints 14-30 specifications 4-66 CRC error checking 4-56 edge decoder 4-31 feature summary 4-5 global buffer 4-41 ground bounce 14-10 24 J K L M N O P Q R S T U V W X Y input/output block (IOB) 4-24 interconnect 4-32 internal bus contention 14-17 low voltage device 4-5 mixed-voltage I/O 4-24, 4-27 on-chip oscillator 4-31 ordering information 4-178 output current 4-27, 14-9 output delay 14-10 pin descriptions 4-46 pinout tables 4-97 power consumption 14-12 power distribution 4-46 product availability 4-174 RAM 4-14 readback 4-64 routing 4-32 soft startup 4-28 specifications 4-79 configuration 4-66 XC4000E 4-80 TTL input 4-24 TTL output 4-27 V/I characteristics 14-9 wide edge decoder 4-31 XC4000A overview 14-4 XC4000D use not recommended 1-1 XC4000E clock diagram 4-42 compared to XC4000 4-8 global buffer 4-41 overview 14-4 Primary Global Buffer (BUFGP) 4-41 Secondary Global Buffer (BUFGS) 4-41 specifications 4-80 XC4000EX buffered switch matrix 4-36 clock diagram 4-42 compared to XC4000 4-8, 4-9 fast capture latch on inputs 4-26 FastCLK buffer (BUFFCLK) 4-26, 4-45 function generator in IOB 4-28 global buffer 4-43 Global Early buffer (BUFGE) 4-26, 4-44 Global Low-Skew buffer (BUFGLS) 4-26, 4-43 interconnect 4-32 latch in CLB 4-12 multiplexer in IOB 4-28 octal routing 4-40 overview 14-5 quad routing 4-36 Z Index A B C D E F G H I J K L M N O P Q R S routing 4-32 specifications not yet available VersaRing (IOB routing) 4-38 XC4000H overview 14-5 use not recommended 1-1 XC4000L 4-5, 4-6 specifications not yet available XC4000XL 4-5, 4-6 specifications not yet available XC4003E pinout table 4-97 XC4005E/L pinout table 4-98 XC4006E pinout table 4-100 XC4008E pinout table 4-102 XC4010E/L pinout table 4-104 XC4013E/L pinout table 4-107 XC4020E pinout table 4-110 XC4025E pinout table 4-113 XC4028EX/XL pinout table 4-113 XC4036EX/XL pinout table 4-118 XC4044EX/XL pinout table 4-123 XC4052XL pinout table 4-128 XC5200 4-181, 14-3 3-state buffer 4-191 5-input function 4-188 available I/O 4-248 bitstream format 4-200 boundary scan 4-191, 14-49 BSDL files 14-57 carry logic 4-189 cascade logic 4-190 CLB-to-pad diagram 4-212 CMOS input 4-196 CMOS output 4-196 compared to XC4000 and XC3000 4-182 configurable logic block (CLB) 4-184, 4-188 differences from XC4000 and XC3000 4-182 configuration 4-199 differences from XC4000 and XC3000 4-183 T U V W X Y Z feature summary 4-181 general routing matrix (GRM) 4-184, 4-185, 4-192, 4-194 global buffer 4-194 global reset (GR) 4-191 input/output block (IOB) 4-196 differences from XC4000 and XC3000 4-183 interconnect 4-184, 4-192 latch in CLB 4-188 local interconnect matrix (LIM) 4-184, 4-192 logic cell (LC) 4-182, 4-184 on-chip oscillator 4-191 ordering information 4-248 output current 4-196 overview 14-5 performance 4-185 pinout tables 4-223 product availability 4-248 routing 4-184, 4-192 differences from XC4000 and XC3000 4-183 specifications 4-205, 4-206 XC5200 4-206 XC5200L 4-250 TTL input 4-196 TTL output not supported 4-196 VersaBlock 4-184 VersaRing (IOB routing) 4-185, 4-196 XC5200L 4-249 feature summary 4-249 specifications 4-250 XC5202 CLB-to-pad diagram 4-212 pinout table 4-223 XC5204 CLB-to-pad diagram 4-214 pinout table 4-226 XC5206 CLB-to-pad diagram 4-216 pinout table 4-230 XC5210 CLB-to-pad diagram 4-218 pinout table 4-235 XC5215 CLB-to-pad diagram 4-220 pinout table 4-241 XC6200 4-253 clock diagram 4-261 configuration 4-268 decoupling capacitor 4-274 designing with 4-265 electrical parameters 4-274 feature summary 4-253 function unit 4-257 25 Index A B C D E F G H block diagram 4-258 global buffer 4-257, 4-261 input/output block (IOB) 4-261 interconnect 4-256 IOB routing 4-263 map register 4-268 mask register 4-268 overview 14-5 pin descriptions 4-273 pinout tables 4-282 power consumption 4-274 power-on reset 4-272 product availability 4-286 register 4-267 Register Clear 4-261 routing 4-256, 4-263 software 4-267 specifications 4-275 wildcard register 4-270 XC6216 pinout table 4-282 XC7000 programmer 10-1 XC7200A overview 14-5 XC7236A 3-147 XC7272A 3-163 XC7300 3.3 V or 5.5 V interface 3-77 ALU 3-74 carry lookahead 3-75 characterization data 3-135 fast function blocks 3-72 I/O block 3-76 overview 3-71, 14-5 product availability 3-71 product term assignment 3-74 timing model 3-78 XC73108 pinout table 3-121 XC73144 pinout table 3-132 XC7318 pinout table 3-87 XC7336/Q pinout table 3-96 XC7354 pinout table 3-105 XC7372 pinout table 3-113 XC8000 Series 2-6, 2-8 XC8100 5-1 antifuse 5-3 26 I J K L M N O P Q R S T U V W X available I/O 5-25 boundary scan 5-3, 5-11 cascade logic 5-6 CMOS input 5-9, 5-12 CMOS output 5-10 configurable logic cell (CLC) 5-5 configuration 5-13 design flow 5-2, 5-16 feature summary 5-1 global buffer 5-7 global reset (GR) 5-6 input/output cell (IOC) 5-9 interconnect 5-6 latch in CLC 5-6 leakage current 5-12 low voltage device 5-13 master reset 5-6 metastability 5-15 MicroVia 5-2, 5-12 one-time programmable (OTP) 5-2 ordering information 5-42 output current 5-10 overview 14-5 performance 5-4 pinout diagrams 5-30 pinout table 5-24, 5-25 power consumption 5-12 product availability 5-42 programming 5-13, 10-1 routing 5-6 software 2-6, 2-8, 5-2, 5-16 targeted applications 5-3 testing programming 5-15 TTL input 5-9, 5-12 TTL output not supported 5-10 V/I characteristics 5-10 XC8101 pinout table 5-26 XC8103 pinout table 5-27 XC8106 pinout table 5-28 XC8109 pinout table 5-29 XC9500 design security 3-14 endurance 3-14 FastCONNECT switch matrix 3-11 function block 3-5 I/O block 3-12 in-system programming 3-14 overview 3-3, 14-6 package availability and device I/O pins 3-5 Y Z Index A B C D E F G H pin locking capability 3-13 product availability 3-4 product term allocator 3-8 timing model 3-15 XC95108 pinout table 3-31 XC95144 pinout table 3-37 XC95180 pinout table 3-43 XC95216 pinout table 3-51 XC95288 pinout table 3-59 XC9536 pinout table 3-21 XC95432 3-65 XC95576 3-67 XC9572 pinout table 3-25 XCELL newsletter 1-1, 13-5 XChecker cable 2-8, 2-36 I J K L M N O P Q R S T U V W X Y Z readback XC4000 Series 4-65 XDOCS E-mail system 13-3 XFACTS FAX system 13-3 Xilinx about the company 1-2 Alliance Program 2-7 E-mail addresses 13-4 quality assurance and reliability 12-1 technical support 1-5, 13-2 Web site 1-1, 1-5, 13-3 XCELL newsletter 1-1 Xilinx ABEL 2-2, 2-8, 2-33, 2-34 XSI software package 2-35 xtal oscillator. See crystal oscillator X-TALX Xilinx network 13-1, 13-3 XTL1 pin description XC3000 Series 4-324 XTL2 pin description XC3000 Series 4-324 27 Index A 28 B C D E F G H I J K L M N O P Q R S T U V W X Y Z 1 Introduction 2 Development System Products 3 CPLD Products 4 SRAM-Based FPGA Products 5 OTP FPGA Products 6 SPROM Products 7 3V Products 8 HardWire Products 9 Military Products Sales Offices, Sales Representatives, and Distributors 10 Programming Support 11 Packages and Thermal Characteristics 12 Testing, Quality, and Reliability 13 Technical Support 14 Product Technical Information 15 Index 16 Sales Offices, Sales Representatives, and Distributors Sales Offices, Sales Representatives, and Distributors Table of Contents Sales Offices, Sales Representatives, and Distributors Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U.S. Sales Representatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Sales Representatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16-1 16-1 16-3 Sales Offices, Sales Representatives, and Distributors July 15, 1996 (Version 1.01) Headquarters XILINX, Inc. 2100 Logic Drive San Jose, CA 95124 (408) 559-7778 TWX: 510-600-8750 FAX: 408-559-7114 Xilinx Sales Offices NORTH AMERICA XILINX, Inc. 1281 Oakmead Pkwy. Suite 202 Sunnyvale, CA 94086 (408) 245-9850 FAX: 408-245-9865 XILINX, Inc. 5690 DTC Blvd. Suite 490W Englewood, CO 80111 (303) 220-7541 FAX: 303-220-8641 XILINX, Inc. 15615 Alton Parkway Suite 280 Irvine, CA 92718 (714) 727-0780 FAX: 714-727-3128 XILINX, Inc. 61 Spit Brook Rd. Suite 403 Nashua, NH 03060 (603) 891-1098 FAX: 603-891-0890 XILINX, Inc. 905 Airport Rd. Suite 200 West Chester, PA 19380 (610) 430-3300 FAX: 610-430-0470 XILINX, Inc. 939 North Plum Grove Road Suite H Schaumburg, IL 60173 (847) 605-1972 FAX: 847-605-1976 XILINX, Inc. 6080-C Six Forks Road Raleigh, NC 27609 (919) 846-3922 FAX: 919-846-8316 July 15, 1996 (Version 1.01) XILINX, Inc. 4100 McEwen, Suite 237 Dallas, TX 75244 (214) 960-1043 FAX: 214-960-0927 Marshall Industries Locations throughout the U.S. and Canada. 1-800-522-0084 FAX: 818 -307-6297 Norcomp 8880 Wagon Way Granite Bay, CA 95746 (916) 791-7776 FAX: 916-791-2223 EUROPE Insight Electronics Locations throughout the U.S. 1-800-677-7716 FAX: 619-587-1380 Norcomp 30101 Agoura Ct. #234 Agoura, CA 91301 (818) 865-8330 FAX: 818-865-2167 Nu Horizons Electronics Corp. Locations throughout the U.S. (516) 226-6000 FAX: 516-226-6262 Norcomp 30 corporate park #200 Irvine, CA 92714 (714) 260-9868 FAX: 714-260-9659 U.S. Sales Representatives Luscombe Engineering, Inc. 1500 Kansas Ave. Suite 1B Longmont, CO 80501 (303) 772-3342 FAX: 303-772-8783 XILINX, Ltd. Benchmark House 203 Brooklands Road Weybridge, Surrey KT13 ORH United Kingdom Tel: (44) 1-932-349401 FAX: (44) 1-932-349499 XILINX SARL Espace Jouy Technology 21, rue albert Calmette, Bt. C 78353 Jouy En Josas, Cedex France Tel: (33)-1-3463-01-01 FAX: (33)-1-3463-01-09 XILINX GmbH Dorfstr. 1 85609 Aschheim Germany Tel: (49) 89-991549-0 FAX: (49) 89-904-4748 ALABAMA Electro Source 4835 University Sq., Ste.11 Huntsville, AL 35816 Tel: 205-830-2533 FAX: 205-830-5567 JAPAN ARIZONA XILINX K. K. Daini-Nagaoka Bldg. 2F 2-8-5, Hatchobori, Chuo-ku Tokyo 104 Japan Tel: (81) 3-3297-9191 FAX: (81) 3-3297-9189 Quatra Associates 4645 S. Lakeshore Dr. Suite 1 Tempe, AZ 85282 (602) 820-7050 FAX: 602-820-7054 ASIA PACIFIC XILINX Asia Pacific Unit 4312, Tower II Metroplaza Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852-2-424-5200 FAX: 852-2494-7159 North American Distributors Hamilton Hallmark Locations throughout the U.S. and Canada. 1-800-332-8638 FAX: 1-800-257-0568 ARKANSAS Bonser-Philhower Sales 689 W. Renner Road Suite 101 Richardson, TX 75080 (214) 234-8438 FAX: 214-437-0897 CALIFORNIA COLORADO CONNECTICUT John E. Boeing, Co., Inc. 101 Harvest Park, Bldg. 1A No. Plains Industrial Road Wallingford, CT, 06492 (203) 265-1318 FAX: 203-265-0235 DELAWARE Delta Technical Sales, Inc. 122 N. York Rd., Suite 9 Hatboro, PA 19040 (215) 957-0600 FAX: 215-957-0920 FLORIDA Semtronic Assoc., Inc. 657 Maitland Avenue Altamonte Springs, FL 32701 (407) 831-8233 FAX: 407-831-2844 Quest-Rep Inc. 6494 Weathers Pl, Suite 200 San Diego, CA 92121 (619) 622-5040 FAX: 619-622-5047 Semtronic Assoc., Inc. 3471 N. W. 55th Street Ft. Lauderdale, FL 33309 (305) 731-2484 FAX: 305-731-1019 Norcomp 1267 Oakmead Pkwy Sunnyvale, CA 94086 (408) 733-7707 FAX: 408-774-1947 Semtronic Assoc., Inc. 1467 South Missouri Avenue Clearwater, FL 34616 (813) 461-4675 FAX: 813-442-2234 16-1 Sales Offices, Sales Representatives, and Distributors GEORGIA LOUISIANA (Northern) MISSOURI NEW YORK (Metro) Electro Source 3280 Pointe Parkway, #1500 Norcross, GA 30092 ( 770)-734-9898 FAX: 770-734-9977 Bonser-Philhower Sales 689 W. Renner Rd., Suite 101 Richardson, TX 75080 (214) 234-8438 FAX: 214-437-0897 Advanced Technical Sales 2012 Prairie Cir. Suite A Olathe, KS 66062 (913) 782-8702 FAX: 913-782-8641 Parallax 734 Walt Whitman Road Melville, NY 11747 (516) 351-1000 FAX: 516-351-1606 IDAHO (Southwest) LOUISIANA (Southern) Bonser-Philhower Sales 10700 Richmond, Suite 150 Houston, TX 77042 (713) 782-4144 FAX: 713-789-3072 Advanced Technical Sales 13755 St. Charles Rock Rd. Bridgeton, MO 63044 (314) 291-5003 FAX: 314-291-7958 NEW YORK Thorson Pacific, Inc. 14575 Bel-Red Road #102 Bellevue, WA 98007 (206) 603-9393 FAX: 206-603-9380 Luscombe Engineering, Inc. 670 East 3900 South #103 Salt Lake City, UT 84107 (801) 268-3434 FAX: 801-266-9021 MAINE ILLINOIS Beta Technology Sales, Inc. 1009 Hawthorn Drive Itasca, IL 60143 (708) 250-9586 FAX: 708-250-9592 Advanced Technical Sales 13755 St. Charles Rock Rd. Bridgeton, MO 63044 (314) 291-5003 FAX: 314-291-7958 INDIANA Gen II Marketing,Inc. 31 E. Main St. Carmel, IN 46032 (317) 848-3083 FAX: 317-848-1264 Gen II Marketing, Inc. 1415 Magnavox Way Sutie 130 Ft. Wayne, IN 46804 (219) 436-4485 FAX: 219-436-1977 IOWA Advanced Technical Sales 375 Collins Road N.E. Cedar Rapids, IA 52402 (319) 393-8280 FAX: 319-393-7258 KANSAS Advanced Technical Sales 2012 Prairie Cir. Suite A Olathe, KS 66062 (913) 782-8702 FAX: 913-782-8641 KENTUCKY Gen II Marketing, Inc. 861 Corporate Dr. #210 Lexington, KY 40503 (606) 223-9181 FAX: (606) 223-2864 16-2 Genesis Associates 128 Wheeler Road Burlington, MA 01803 (617) 270-9540 FAX: 617-229-8913 MARYLAND Micro Comp, Inc. 1421 S. Caton Avenue Baltimore, MD 21227-1082 (410) 644-5700 FAX: 410-644-5707 MASSACHUSETTS Genesis Associates 128 Wheeler Road Burlington, MA 01803 (617) 270-9540 FAX: 617-229-8913 MICHIGAN Miltimore Sales Inc. 22765 Heslip Drive Novi, MI 48375 (810) 349-0260 FAX: 810-349-0756 MONTANA Luscombe Engineering, Inc. 670 East 3900 South #103 Salt Lake City, UT 84107 (801) 268-3434 FAX: 801-266-9021 NEBRASKA Advanced Technical Sales 375 Collins Road N.E. Cedar Rapids, IA 52402 (319) 393-8280 FAX: 319-393-7258 NEVADA Norcomp 8880 Wagon Way Granite Bay, CA 95748 (916) 791-7776 FAX: 916-791-2223 Quatra Associates (Las Vegas) 4645 S. Lakeshore Dr., Suite 1 Tempe, AZ 85282 (602) 820-7050 FAX: 602-820-7054 NEW HAMPSHIRE Miltimore Sales Inc. 3684 44th St., Suite 100-J Kentwood, MI 49512 (616)-554-9292 FAX: 616-554-9210 Genesis Associates 128 Wheeler Road Burlington, MA 01803 (617) 270-9540 FAX: 617-229-8913 MINNESOTA NEW JERSEY (Northern) Beta Technology 18283 Minnetonka Blvd. Suite C Deephaven, MN 55391 (612) 473-2680 FAX: (612)473-2690 Parallax 734 Walt Whitman Road Melville, NY 11747 (516) 351-1000 FAX: 516-351-1606 MISSISSIPPI Delta Technical Sales, Inc. 122 N. York Road, Suite 9 Hatboro, PA 19040 (215) 957-0600 FAX: 215-957-0920 Electro Source 4835 University Sq., Ste.11 Huntsville, AL 35816 ( 205)-830-2533 FAX: 205-830-5567 NEW JERSEY (Southern) NEW MEXICO Quatra Associates 600 Autumwood Place, S. E. Albuquerque, NM 87123 (505) 296-6781 FAX: 505-292-2092 Electra Sales Corp. 333 Metro Park Suite M103 Rochester, NY 14623 (716) 427-7860 FAX: 716-427-0614 Electra Sales Corp. 6700 Old Collamer Rd. E. Syracuse, NY 13057 (315) 463-1248 FAX: 315-463-1717 NORTH CAROLINA Electro Source 6050 C Six Forks Rd. Raleigh, NC 27609 ( 919)-846-5888 FAX: 919-846-0408 NORTH DAKOTA Beta Technology 18283 Minnetonka Blvd. Suite C Deepaven, MN 55391 (612) 473-2680 FAX: (612) 473-2690 OHIO Bear Marketing, Inc. 3554 Brecksville Road PO Box 427 Richfield, OH 44286-0427 (216) 659-3131 FAX: 216-659-4823 Bear Marketing, Inc. 270 Regency Ridge Drive Suite 115 Dayton, OH 45459 (513) 436-2061 FAX: 513-436-9137 OKLAHOMA Bonser-Philhower Sales 689 W. Renner Rd., Suite 101 Richardson, TX 75080 (214) 234-8438 FAX: 214-437-0897 OREGON Thorson Pacific, Inc. 9600 S.W. Oak Street, Suite 320 Portland, OR 97223 (503) 293-9001 FAX: 503-293-9007 July 15, 1996 (Version 1.01) PENNSYLVANIA Delta Technical Sales, Inc. 122 N. York Rd., Suite 9 Hatboro, PA 19040 (215) 957-0600 FAX: 215-957-0920 Bonser-Philhower Sales 689 W. Renner Rd., Suite 101 Richardson, TX 75080 (214) 234-8438 FAX: 214-437-0897 TEXAS (El Paso County) Bear Marketing, Inc. 4284 Rt. 8, Suite 211 Allison Park, PA 15101 (412) 492-1150 FAX: 412-492-1155 Quatra Associates 600 Autumwood Place SE Albuquerque, NM 87123 (505) 296-6781 FAX: 505-292-2092 PUERTO RICO UTAH Semtronic Assoc., Inc Crown Hills 125 Carite ST. Esq. Avenue Parana Rio Piedras, P.R. 00926 (809) 766-0700/0701 FAX: 809-763-8071 Luscombe Engineering Co. 670 East 3900 South #103 Salt Lake City, UT 84107 (801) 268-3434 FAX: 801-266-9021 RHODE ISLAND Genesis Associates 128 Wheeler Road Burlington, MA 01803 (617) 270-9540 FAX: 617-229-8913 SOUTH CAROLINA Electro Source 6050 C Six Forks Rd. Raleigh NC 27609 (919)-846-5888 FAX: 919-846-0408 SOUTH DAKOTA Beta Technology 18283 Minnetonka Blvd. Suite C Minnetonka, MN 55345 (612) 473-2680 FAX: (612) 473-2690 TENNESSEE Electro Source 6050 C Six Forks Rd. Raleigh, NC 27609 Tel: (919) 846-5888 FAX: 919-846-0408 TEXAS Bonser-Philhower Sales 8240 MoPac Expwy. Suite 295 Austin, TX 78759 (512) 346-9186 FAX: 512-346-2393 Bonser-Philhower Sales 10700 Richmond, Suite 150 Houston, TX 77042 (713) 782-4144 FAX: 713-789-3072 July 15, 1996 (Version 1.01) VERMONT Genesis Associates 128 Wheeler Road Burlington, MA 01803 (617) 270-9540 FAX: 617-229-8913 VIRGINIA Micro Comp, Inc. 8811Timberlake Rd. Suite 107 Lynchburg, VA 24502 (804) 239-2626 FAX: 804-239-1333 WASHINGTON Thorson Pacific, Inc. 14575 Bel-Red Rd. Suite 102 Bellevue, WA 98007 (206) 603-9393 FAX: 206-603-9380 WASHINGTON (Vancouver, WA only) Thorson Pacific, Inc. 9600 S.W. Oak Street Suite 320 Portland, OR 97223 (503) 293-9001 FAX: 503-993-9007 WASHINGTON D.C. Micro Comp, Inc. 1421 S. Caton Avenue Baltimore, MD 21227-1082 (410) 644-5700 FAX: 410-644-5707 WEST VIRGINIA Bear Marketing, Inc. 4284 Rt. 8 Suite 211 Allison Park, PA 15101 (412) 492-1150 FAX:412-492-1155 WISCONSIN (Western) Beta Technology 18283 Minnetonka Blvd. Suite C Minnetonka, MN 55345 (612) 473-2680 FAX: 612-473-2690 WISCONSIN (Eastern) Advanced Component Dist. Ste. 1, 1048 Beaudesert Rd. Cooper Plains Queensland, 4108 Australia Tel: (61) 7-246-5214 FAX: (61) 7-275-3662 AUSTRIA Beta Technology Sales, Inc. 9401 N. Beloit, Suite 409 MIlwaukee, WI 53227 (414) 543-6609 FAX: 414-543-9288 SEI Elbatex GmbH Eitnergasse 6 1230 Vienna Austria Tel: (43) 1-866-4220 FAX: (43) 1-866-42201 WYOMING BELGIUM & LUXEMBURG Luscombe Engineering, Inc. 670 East 3900 South #103 Salt Lake City, UT 84107 (801) 268-3434 FAX: 801-266-9021 SEI Rodelco NV Limburg Stirum 243 1780 Wemmel Belgium Tel: (32) 2-460-0560 FAX: (32) 2-460-0271 International Sales Representatives ASEAN (Singapore, Malaysia, Indonesia, Thailand, Phillippines, Brunei) MEMEC Asia Pacific Ltd. 10 Anson Rd. #14-02 International Plaza Singapore 0207 Tel: (65) 222-4962 FAX: (65) 222-4939 AUSTRALIA Advanced Component Dist. Suite 5, Level 1, "Metro Centre" 124 Forest Rd. Hurstville 2220 P.O.Box 574 Hurstville 2220 Australia Tel: (61) 2-585-5030 FAX: (61) 2-580-1095 Advanced Component Dist. Unit 1, 14 Melrich Road Bayswater VIC 3153 Melbourne, Australia Tel: (61) 3-9762-4244 FAX: (61) 3-9761-1754 Advanced Component Dist. Suite 8, 328 Albany Highway Victoria Park, WA 6100 Australia Tel: (61) 9-472-3232 FAX: (61) 9-470-2303 Advanced Component Dist. 20D William Street Norwood SA 5067 Australia Tel: (61)8-364-2844 FAX: (61)8-364-2811 CANADA (BRITISH COLUMBIA) Thorson Pacific, Inc. 4170 Still Creek Dr. #200Burnaby BC V6C 6C6 Canada Tel: (604) 294-3999 FAX: (604) 473-7755 CANADA (ALBERTA) Electro Source 6875 Royal Oak Ave. Burnaby BC V5J 4J3 Canada Tel: (604) 435-2533 FAX: (604)-435-2538 CANADA (OTTAWA) Electro Source, Inc. 300 March Road, Suite 203 Kanata, Ontario K2K 2E4 Canada Tel: (613) 592-3214 FAX: (613)-592-4256 CANADA (QUEBEC) Electro Source 6600 TransCanada Hwy Suite 420 Point Claire Quebec H9R 4S2 Canada Tel: (514) 630-7486 FAX: 514-630-7421 CANADA (TORONTO) Electro Source, Inc. 230 Galaxy Blvd. Rexdale Ontario M9W 5R8 Canada Tel: (416) 675-4490 FAX: (416)-675-6871 16-3 Sales Offices, Sales Representatives, and Distributors CHINA PEOPLE'S REPUBLIC MEMEC (Beijing Rep Office) Rm 5851, Blk 8, Xiynan Hotel No. 1 Sarliha Rd. Beijing 100046 Tel: (86) 10-8313388 X 5851 FAX: (86) 10-2564176 MEMEC Asia Pacific Ltd. Shanghai Rep Office Rm. 2363, West Building Jim Jiang Hotel 59 Mao Ming Rd. Shanghai 200020 Tel: (86) 21-2582582 x2362 FAX: (86) 21-4723388 CZECH REPUBLIC SEI Eljapex/Elbatex GmbH Prechodni 11 CZ-140 00 Praha 4 Czech Republic Tel: (02)-692-8087 FAX: (02)-471-82-03 DENMARK Micronor A/S P.O.Box 929 Torvet 1 DK-8600 Silkenborg Denmark Tel: (45) 8681-6522 FAX: (45) 8681-2827 FINLAND Memec Finland Oy Vernissakatu 6 01300 Vantaa Finland Tel: (358) 0-7001-9830 FAX: (358) 0-7001-9839 FRANCE Rep'tronic 1 Bis, rue Marcel Paul Z.I. La Bonde 91742 Massy France Tel: (33) 1-69536720 FAX: (33) 1-60139198 Axess Technology 49, rue de l'Esterl Silic 600 94663 Rungis Cedex France Tel: (33) 1-49-78-94-94 FAX: (33)1-49-78-03-24 Axess Technology Route Joseph Coynel 38360 Engins France Tel: (33) 76-94-49-72 FAX: (33) 76-94-49-06 16-4 Axess Technology 23 le Grand Francois La Courbatiere 38140 Rives France Tel: (33)76-91-45-30 FAX: (33)76-91-45-34 AVNET/EMG. 79 Rue Pierre Semard 92 320 Chatillon France Tel: (33) 1 49 65 25 00 FAX : (33) 1 49 65 27 39 AVNET Composant Sud-Ouest Technoparc Bat.4, Voie 5-BP404 31314 Labege Cedex France Tel: (33) 61 39 21 12 FAX: (33) 61 39 21 40 AVNET Composant Aquitaine 16 Rue Francois Arago Zi du Phare 33700 Merignac France Tel: (33) 56 55 92 92 FAX: (33) 56 34 39 99 AVNET Composant Rhone-Auvergne Parc Club du Moulin a Vent Bat 32-33, rue du Dr-G.Levy 69693 Venissieux Cedex France Tel: (33) 7800-1280 FAX: (33) 7875-9597 AVNET Composant Saint Etienne Le Chatelet-5 place Carnot 42000 Saint etienne France Tel: (33) 77 92 77 66 FAX: (33) 77 92 77 30 AVNET Composant Ouest Technoparc-Bat.E 4 Av. des Peupliers, B.P. 43 35511 Cesson Sevigne Cedex France Tel: (33) 99 83 84 85 FAX: (33) 99 83 80 83 AVNET Composant Rhone-Alpes Zac des Bealieres 23 Av. de Granier 38240 Meylan France Tel: (33) 76 90 11 88 FAX: (33) 76 41 04 90 AVNET Composant Nantes Le Sillon de Bretagne 23e etage-Aile C 8 Av.des Thebaudieres 44800 Saint Herblain France Tel: (33) 40 63 23 00 FAX: (33) 40 63 22 88 AVNET Composant Marsielle 17, bd. Andri Aune 13006 Marseille France Tel: (33) 91 54 15 28 GERMANY Avnet E2000 Stahlgruberring 12 81829 Munchen Germany Tel: (49) 89-45110-01 FAX: (49) 89-45110-729 Avnet E2000 Kurfurstenstr. 130 10785 Berlin Germany Tel: (49) 30-214882-0 FAX: (49) 30-2141728 Avnet E2000 Friedrich-Ebert-Damm 145 22047 Hamburg Germany Tel: (49) 40-696-9520 FAX: (49) 40-696-2787 Avnet E2000 Benzstr. 1 70826 Gerlingen Stuttgart Germany Tel: (49) 7156-356-0 FAX: (49) 7156-28084 Avnet E2000 Heinrich-Hertz-Str. 52 40699 Erkrath Dusseldorf Germany Tel: (49) 211-92003-0 FAX: (49) 211-92003-99 Avnet E2000 Schmidtstr. 49 60326 Frankfurt/M. Germany Tel: (49) 69-973804-0 FAX: (49) 69-7380712 Avnet E2000 Further Str. 212 90429 Nurnberg Germany Tel: (49) 911-93149-0 FAX: (49) 911-320821 Metronik GmbH Leonhardsweg 2 82008 Unterhaching Munchen Germany Tel: (49) 89-611080 FAX: (49) 89-61108110 Metronik GmbH Zum Lonnenhohl 38 44319 Dortmund Germany Tel: (49) 231-927110-0 FAX: (49) 231-927110-99 Metronik GmbH Carl-Zeiss Str.6 25451 Quickborn Hamburg Germany Tel: (49) 4106-773050 FAX: (49) 4106-773052 Metronik GmbH Osmiastr. 9 69221 Dossenheim Mannheim Germany Tel: (49) 6221-87044 FAX: (49) 6221-87046 Metronik GmbH Pilotystr. 27/29 90408 Nurnberg Germany Tel: (49) 911-363536 FAX: (49) 911-353986 Metronik GmbH Lowenstr. 37 70597 Stuttgart Germany Tel: (49) 711-7640333 FAX: (49) 711-7655181 Metronik GmbH Schonauer Str. 113 04207 Leipzing Germany Tel: (49) 341-4239413 FAX: (49) 341-4239424 Metronik GmbH Bahnstrasse 9 65205 Wiesbaden Germany Tel: (49) 611-97384-0 FAX: (49) 611-97384-18 Metronik GmbH Franz-Schubert-Str.41 16548 Glienicke Berlin Germany Tel: (49) 33056-845-0 FAX: (49) 33056-845-50 Intercomp Am Hochwald 42 D-82319 Starnberg Germany Tel: (49) 8151-16044 FAX: (49) 8151-79270 July 15, 1996 (Version 1.01) Intercomp Kniebisstr. 40/1 78628 Rottweil Stuttgart Germany Tel: (49) 741-1 48 45 FAX: (49) 741-1 52 20 Intercomp Schustergasse 35 55278 Kongernheim Frankfurt Germany Tel: (49) 6737-9881 FAX: (49) 6737-9882 Intercomp Hans Ackermann Str.23 91322 Grafenberg Germany Tel: (49) 9192-998917 FAX: (49) 9192-998918 GREECE Peter Caritato & Assoc. S. A. Llia Iliot, 31 Athens 11743 Greece Tel: (30) 1-9020115 FAX: (30) 1-9017024 Core El Logic System ETD, Crompton Greaves Ltd. First Floor, Surya Bhawan Fergusson College Rd. Pune 411005 India Tel: (91) 212-323982 FAX: (91) 212-332838 IRELAND Memec Ireland Ltd. Gardner House Bank Place Limerick Ireland Tel: (353) 61-411842 FAX: (353) 61-411888 ISRAEL E.I.M International Ltd. 9 Hashiloach Street P.O. Box 4000 Kiryat Matalon Petach Tikva 49130 Israel Tel: (972) 3-92 33257 FAX: (972) 3-924 4857 ITALY Semicon 104 Aeolu Str. 10564 Athens Greece Tel: (30)-1-325 3126 FAX: (30) 1-321-6063 HONG KONG MEMEC Asia Pacific Ltd. Unit No. 2308-2319, Tower I Metroplaza, Hing Fong Road, Kwai Fong, N.T. Hong Kong Tel: (852) 2410 2780 FAX: (852) 2401 2518 HUNGARY ACSIS S.R.L. Via Alberto Mario. 26 20149 Milano, Italy Tel: (39) 2-48022522 FAX: (39) 2-48012289 Silverstar-Celdis Viale Fulvio Testi 280 20126 Milano, Italy Tel: (39) 2-66125 1 FAX: (39) 2-66101359 Silverstar-Celdis Via Collamarini, 22 40138 Bologna, Italy Tel: (39) 51-538500 FAX: (39) 538831 SEI Dataware KFT/Elbatex GmbH Angol Utca 22 1149 Budapest Hungary Tel: (36) 1-163-5081 FAX: (36) 1-251-5517 Silverstar-Celdis Via Paisiello,30 00198 Roma, Italy Tel: (39) 6-8848841 FAX: (39) 6-8553228 SEI Eljapex/Elbatex GmbH Vaci u 202 1138 Budapest Hungary Tel: (36) 1-269-9093/95 FAX: (36) 1-269-9096 Silverstar-Celdis Centro Direzionale Benelli Via Del Monaco, 16 61100 Pesaro, Italy Tel: (39) 721-26560 FAX: (39) 721-400896 INDIA Silverstar-Celdis Via A.da Noli 6 50127 Firenze, Italy Tel: (39) 55-43 5125 FAX: (39) 55-43 77184 Core El Micro Systems 45131 Manzanita Court Fremont, California 94539 USA Tel:(510) 770-1066 FAX: 510-657-1525 July 15, 1996 (Version 1.01) Silverstar-Celdis Centro Piero Della Francesca Corso Svizzera, 185 Bis 10149 Torino, Italy Tel: (39) 11 77 10082 FAX: (39) 11 77 64921 Marubun Corporation 8-1 Odenma-cho, Nihonbashi Chuo-ku Tokyo, 103 Japan Tel: (81) 3-3639-5210 FAX: (81) 3-3639-3727 Silverstar-Celdis Via G. Antonio Resti 63 00143 Roma, Italy Tel: (39) 6 519 57527 FAX: (39) 6 504 3330 Kaga Electronics Co., Ltd. 1-26-1 Otowa Bunkyo-ky Tokay 112, Japan Tel: (81) 3-3942-6224 FAX: (81) 3-3942-6215 Silverstar-Celdis Via.delle Indus.13 35010 Limena Padova, Italy Tel: (39) 49 88 40044 FAX: (39) 49 88 41079 Silverstar-Celdis Via Famagosta 1/5 17100 Savona, Italy Tel: (39) 19 81 5090 FAX: (39) 19 81 5091 JAPAN Okura Electronics Co., Ltd. 3-6, Ginza 2-chome, Chuo-ku, Tokyo, 104 Japan Tel: (81) 3-3564-6871 FAX: (81) 3-3564-6870 Okura Electronics Service Co., Ltd. Yokota Bldg Ginza 2-11-5 Chuo-Ku, Tokyo, 104 Japan Tel: (81) 3-3545-2360 FAX: (81) 3-3545-2351 Tokyo Electron Ltd. TBS Broadcasting Center 5-3-6- Akasaka, Mingto-Ku Tokyo, 163 Japan Tel: (81) 3-5561-7212 FAX: (81) 3-5561-7389 Towa Elex Co., Ltd. Unity Bldg. 5F 6-5 Nihonbashi Tomisawa-cho Chuo-Ku, Tokyo 103 Japan Tel: (81) 3-5640-1241 FAX: (81) 3-5640-1240 Varex Co., Ltd. Nippo Shin-Osaka No. 2 Bldg. 1-8-33, Nishimiyahara, Yodogawa-ku, Osaka, 532 Japan Tel: (81) 6-394-5201 FAX: (81) 6-394-5449 THE NETHERLANDS SEI Rodelco BV P.O.Box 6824 Takkebijsters 2 4802 HV Breda The Netherlands Tel: (31) 76-5722700 FAX: (31) 76-5710029 NEW ZEALAND Advanced Component Dist. P.O.Box 24-500 Royal Oak, Auckland New Zeland Tel: (64) 9-636-5984 FAX: (64) 9-636-5985 Advanced Component Dist 2 Heath St. Wainviomata, Wellington New Zealand Tel: (64) 4-564-4902 FAX: (64) 4-564-2243 Advanced Component Dist. Worchester Chambers 69 Worcester St. Christchurch New Zeland Tel: (64) 3-379-3889 FAX: (64) 3-379-3072 NORWAY BIT Elektronikk AS Smedsvingen 4 P.O. Box 194 1360 Nesbru Norway Tel: (47) 66-98 13 70 FAX: (47) 66-98 13 71 POLAND SEI NEljapex/Elbatex GmbH Ul. Wilcza 50/52 PL-00679 Warszawa Poland Tel: (48) 2621 7122 FAX: (48) 2623 0605 16-5 Sales Offices, Sales Representatives, and Distributors PORTUGAL SLOVENIA/CROATIA SOUTHEAST ASIA TURKEY TECMIC Taguspark Edificio Inovacao 1, no 222 2780 Oeiras Portugal Tel: (351) 1-422-8800 FAX: (351) 1-422-8809 SEI Eljapex/Elbatex GmbH Stegne 19, PO Box 19 SLO-61-117 Ljubljana Tel: (61) 191-126-507 FAX: (61) 192-398-507 MEMEC Asia Pacific Ltd. Unit No.2308-2319, Tower I Metroplaza, Hing Fong Road, Kwai Fong, N.T. Hong Kong Tel: (852) 410-2780 FAX: (852) 401-2518 Aztech Electronics Corp 524 42nd St. #200 Union City, New Jersey 07087 Tel: (201) 867-2271 FAX: (201) 867-2162 RUSSIA Avnet - ASD P.O. Box 3853 Pretoria 2128 South Africa Tel: (27) 11-444-2333 FAX: (27) 11-444-1706 Scan 10/32 "B" Druzhby St. 117330 Moskva Russia Tel: (7) 095-1436641 FAX: (7) 095-9382247 Scan 42 Ordjonikidze 196143 St. Petersburg Russia Tel: (7) 812 299 7028 FAX: (7) 812 264 6000 Vostorg 3 Rue des Acacias 91370 Verrieres le Buisson France Tel: (33) 1-6920-4613 FAX: (33) 1-6011-5543 SINGAPORE MEMEC Asia Pacific Ltd. Singapore Representative Office 10 Anson Road #14-02 International Plaza Singapore 079903 Tel: (65)-222-4962 FAX: (65)-222-4939 Frontline Technologies Ptc. Ltd 2 Science Park Dr. #57 The Faraday Singapore Science Park Singapore 118222 Tel: (65)-779111 FAX: (65) 779-4455 SLOVAK REPUBLIC Elbatex Slovensko Svrcia ul SK 84104 Bratislava Tel: (42) 7 722 137 FAX: (42) 7 722 139 16-6 SOUTH AFRICA SOUTH AMERICA DTS Ltda. Rosas 1444 Santiago Chile Tel: (56) 2-697-0991 FAX: (56) 2-699-3316 Reycom Electronica S.A. Bdo. de Irigoyen 972 Piso 2do "B" 1304 Buenos Aires Argentina Tel: (54) 1-304-2018 FAX: (54) 1-304-2010 Hitech El. Indl. Coml. Ltda. Rau Branco de Moraes 489 Ch. Santo Antonio Sao Paulo 04718-010 - SP - Brazil Tel: (55) 11-882-4000 FAX: (55) 11-882-4100 SOUTH KOREA MEMEC Asia Pacific Ltd. 4FL, Je Woong Bldg.,176-11 Nonhyun-dong Kangnam-ku Seoul,135-010, South Korea Tel: (82) 2-518-8181 FAX: (82) 2-518-9419 Hyunmyung Electronics Co. Ltd. Dukwha Bld. 401 44-17, Seogyu-dong Mapo-Gu Seoul South Korea Tel: (02) 2-277-7061 FAX: (02) 2-277-8470 SPAIN SEI ADM Electronica, SA Calle Tomas Breton, no 50, 3-2 Planta 28045 Madrid Spain Tel: (34) 1-5304121 FAX: (34) 1-5300164 SEI ADM Electronica, SA Mallorca 1 08014 Barcelona Spain Tel: (34) 3 426 6892 FAX: (34) 3-4250544 email:amdelec@lander.es SEI ADM Electronica, SA Herriko Gudarien, 8-1B 48200 Durango (Vizcaya) Spain Tel: (34)-4-6201572 FAX: (34)-4- 6202331 SWEDEN Aztech Electronik Farabi Sokak No.44/4 06690 Cankaya Ankara Turkey Tel: (90) 312 467-9952 FAX: (90) 312467-9828 UK Microcall Ltd. 17 Thame Park Road Thame Oxon OX9 3XD UK Tel: (44) 1-844-261939 FAX: (44) 1-844-261678 Cedar Technologies Unit One Old Barns Roycote Lane Farm Milton Common Oxfordshire OX9 2NZ UK Tel: (44) 1-844-278278 FAX: (44)1-844-278-378 DipCom Electronics AB Box 1230 Torshamnsgatan 35 S-164 28 Kista Sweden Tel: (46) 8 752 24 80 FAX: (46) 8 751 3649 Cedar Technologies 32 Enterprise House Springkerse Business Park Striling SK7 7UF UK Tel: (44) 1786-446221 FAX: (44) 1786-278378 SWITZERLAND Avnet EMG Ltd. Jubilee House Jubilee Road Letchworth Hertfordshire SG6 1QH UK Tel: (44) 1-462-488500 FAX: (44) 1-462-488567 Fenner Elektronik AG Abteilung Bauteile Gewerbestr. 10 CH-4450 Sissach Switzerland Tel: (41) 61 975 00 00 FAX: (41) 61 971 5608 TAIWAN MEMEC Asia Pacific Ltd. 14F, No. 46, Lane 11 Kuang Fu North Road Taipei Taiwan R.O.C. Tel: (886) 2-760-2028 FAX: (886) 2-765-1488w MEMEC PLC 17 Thame Park Road Thame Oxfordshire OX9 3XD UK Tel: (44) 1-1844 261919 FAX: (44) 1-1844 261683 July 15, 1996 (Version 1.01)