Data Book
The Programmable Logic Data Book
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Success
made
simple
1996
On behalf of the employees of Xilinx, our sales representatives, our distributors, and our
manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in
Xilinx products and services.
As the inventor of Field Programmable Gate Array technology and the world’s leading
supplier of programmable logic, we would like to pledge our continuing commitment to
providing you, our users, with the best possible integr ated circuit components, dev elopment
systems, and technical and sales support.
Over the past y ear , w e hav e substantially broadened our product line with the introduction of
the XC4000E, XC4000EX, XC5000, XC6000, and XC8000 series of FPGAs and the
XC9500 family of CPLDs. The recently-introduced XACTstep v6 and Foundation series
products have set a new standard for functionality and ease-of-use in programmable logic
development systems. You can expect this pace of innovation to continue, and even
increase, as we maintain our leadership role in bringing leading-edge programmable logic
solutions to the market.
We look forward to satisfying all of your programmable logic needs.
Sincerely,
Wim Roelandts
Chief Executive
Officer
Table of Contents
Introduction
Development System Products
CPLD Products (XC9500, XC7300, XC7200)
SRAM-Based FPGA Products (XC4000, XC5200, XC6200, XC3000)
OTP FPGA Products (XC8100)
SPROM Products (XC1700)
3V Products
HardWire Products
Military Products
Programming Support
Packages and Thermal Characteristics
Testing, Quality, and Reliability
Technical Support
Product Technical Information (Application Notes)
Sales Offices, Sales Representatives, and Distributors
Index
Data Book Contents
The Programmable Logic
Data Book
2100 Logic Drive
San Jose, California 95124
United States of America
Telephone: (408) 559-7778
Fax: (408) 559-7114
Technical Support Telephone Hotline: 1-800-255-7778 (North America)
1-408-879-5199 (USA, Xilinx headquarters)
(44) 1932 820821 (United Kingdom)
(33) 1 3463 0100 (France)
(49) 89 991 54930 (Germany)
(81) 3-3297-9163 (Japan)
Technical Support Direct FAX: 1-408-879-4442 (USA, Xilinx headquarters)
(44) 1932 828522 (United Kingdom)
(33) 1 3463 0959 (France)
(49) 89 904 4748 (Germany)
(81) 3-3297-0067 (Japan)
Technical Support Hotline E-mail: hotline@xilinx.com (USA, Xilinx headquarters)
ukhelp@xilinx.com (United Kingdom)
frhelp@xilinx.com (France)
dlhelp@xilinx.com (Germany)
jhotline@xilinx.com (Japan)
Xilinx BBS: 1-408-559-9327 (USA, Xilinx headquarters)
(44) 1932 333540 (United Kingdom)
8 data bits, no parity, 1 stop
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Xilinx Home Page (WWW): http://www.xilinx.com/
R
, XILINX, XACT, XC2064, XC3090, XC4005,
XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD,
NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic,
Plustran, P+, Timing Wizard, and TRACE are registered
trademarks of Xilinx, Inc.
, all XC-prefix product designations, XACT
step
, XACT-
step
Advanced, XACT
step
Foundry, XACT-Floorplanner,
XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus,
XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation
Series, BITA, Configurable Logic Cell, CLC, Dual Block,
FastCLK, FastCONNECT, FastFLASH, FastMap, Hard-
Wire, LCA, Logic Cell, LogiCore, LogicProfessor, MicroVia,
PLUSASM, PowerGuide, PowerMaze, Select-RAM,
SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock,
VersaRing, and ZERO+ are trademarks of Xilinx, Inc. The
Programmable Logic Company and The Programmable
Gate Array Company are service marks of Xilinx, Inc.
All other trademarks are the property of their respective
owners.
Xilinx does not assume any liability arising out of the appli-
cation or use of any product described or shown herein; nor
does it convey any license under its patents, copyr ights, or
maskwork rights or any rights of others. Xilinx reserves the
right to make changes, at an y time , in order to impro ve reli-
ability, function or design and to supply the best product
possible. Xilinx will not assume responsibility for the use of
any circuitry described herein other than circuitry entirely
embodied in its products. Xilinx devices and products are
protected under one or more of the following U.S. Patents:
4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822;
4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418;
4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909;
4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710;
5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858;
5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079;
5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704;
5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929;
5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250;
5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999;
5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924;
5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833;
5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181;
5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117;
5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478;
5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866;
5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192;
5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363,
RE 34,444, and RE 34,808. Other U.S. and foreign patents
pending. Xilinx, Inc. does not represent that de vices shown
or products described herein are free from patent infringe-
ment or from any other third party r ight. Xilinx assumes no
obligation to correct any errors contained herein or to
advise any user of this text of any correction if such be
made. Xilinx will not assume any liability f or the accuracy or
correctness of any engineering or software support or
assistance provided to a user.
Xilinx products are not intended for use in lif e support appli-
ances, devices, or systems. Use of a Xilinx product in such
applications without the written consent of the appropriate
Xilinx officer is prohibited.
Copyright 1996 Xilinx, Inc. All Rights Reserved.
R
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Section Titles
Introduction
An Introduction to Xilinx Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Development System Products
Development Systems Products Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Bundled Packages Product Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Individual Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
CPLD Products
XC9500 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
XC9500 In-System Programmable CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
XC95180 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
XC95432 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
XC95576 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
XC7300 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
XC7300 CMOS CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
XC7318 18-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
XC7336/XC7336Q 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
XC7354 54-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
XC7372 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
XC73108 108-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
XC73144 144-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
XC7300 Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135
XC7200 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145
Table of Contents
XC7236A 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
XC7272A 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
SRAM-Based FPGA Products
XC4000 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
XC4000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
XC5200 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-179
XC5200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
XC5200L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
XC6200 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251
XC6200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253
XC3000 Series Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287
XC3000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
XC3000A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
XC3000L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
XC3100A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
XC3100L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
OTP FPGA Products
XC8100 FPGA Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
SPROM Products
XC1700D Family of Serial Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
3V Products
3.3 V and Mixed Voltage Compatible Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
HardWire Products
Xilinx HardWire™ Array Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Military Products
High-Reliability and Military Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Programming Support
HW-130 Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Packages and Thermal Characteristics
Packages and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Testing, Quality, and Reliability
Quality Assurance and Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Technical Support
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Product Technical Information
Product Technical Information Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
FPGA Configuration Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Configuring Mixed FPGA Daisy Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Configuration Issues: Power-up, Volatility, Security, Battery Back-up. . . . . . . . . . . . . . . . . . 14-35
Dynamic Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41
Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45
Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47
Boundary Scan in XC4000 and XC5000 Series Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49
Index
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Sales Offices, Sales Representatives, and Distributors
Sales Offices, Sales Representatives, and Distributors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
1
Introduction
An Introduction to Xilinx Products
About this Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Programmable Logic vs. Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Shortest Time-to-Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Complex Programmable Logic Devices (CPLDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Development System Products
Development Systems Products Overview
XACTstep: Accelerating Your Productivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Six Powerful New Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
The Xilinx Design Manager—Simplifies the Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
.Flow Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Extensive On-line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Design Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Xilinx Software on CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Support and Update Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Software Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Base Product Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Online Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Technical Support Hotline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Xilinx Technical Bulletin Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Customer Support FAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Internet Electronic Mail Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Software Series Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Easy to Learn and Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
VHDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
ABEL-HDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Table of Contents
2
Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Migration Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Series 8000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Individual Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Development Systems:
Bundled Packages Product Descriptions
Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Foundation Series: Foundation Base System with VHDL Synthesis (PC) . . . . . . . . . . . . . . . . . . . . . . . 2-13
Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Foundation Series: Foundation Standard System with VHDL (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Alliance Series: OrCAD – Base System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Alliance Series: OrCAD – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Alliance Series: Viewlogic – Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Alliance Series: Viewlogic – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Alliance Series: Viewlogic Stand-alone – Base System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Alliance Series: Viewlogic Stand-alone – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Alliance Series: Viewlogic Stand-alone – Extended System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Alliance Series: Viewlogic – Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Alliance Series: Mentor V8 – Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Alliance Series: Synopsys – Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Alliance Series: Cadence – Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Alliance Series: Third Party Alliance – Standard System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Development Systems:
Individual Product Descriptions
FPGA Core Implementation – DS-502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
CPLD Core Implementation – DS-560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Schematic and Simulator Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
X-BLOX – DS-380. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Xilinx ABEL Design Entry – DS-371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Xilinx ABEL Design Entry – DS-571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Xilinx-Synopsys Interface (XSI) – DS-401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
XChecker Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Demonstration Board – FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
CPLD Products
XC9500 Series Table of Contents
XC9500 In-System Programmable CPLD Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
FastCONNECT Switch Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3
IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
XACTstep™ Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
XC9536 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Recommended Operating Conditions
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
XC9536 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
XC9572 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
XC9572 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
XC95108 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Recommended Operation Conditions
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
XC95108 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
XC95144 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
XC95144 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
XC95180 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
XC95180 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
4
XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
XC95180 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
XC95216 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
Recommended Operating Conditions
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
XC95216 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
XC95288 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
XC95288 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
XC95432 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
XC95576 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
XC7300 Series Table of Contents
XC7300 CMOS CPLD Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
Fast Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
Product Term Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
High-Density Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
Shared and Private Product Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
Carry Lookahead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Macrocell Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
3.3 V or 5 V Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Power-On Characteristics/Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Erasure Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
5
Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
High-Volume Production Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
XACTstep Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79
Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
XC7318
18-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
Fast Function Block (FFB) External AC Characteristics
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
XC7318 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
XC7336/XC7336Q
36-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
Fast Function Block (FFB) External AC Characteristics
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
Combinational Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
Asynchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
Synchronous Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
XC7336 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97
XC7354
54-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
6
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Fast Function Block (FFB) External AC Characteristics
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104
XC7354 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
XC7372
72-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
Fast Function Block (FFB) External AC Characteristics
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114
XC73108
108-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
Fast Function Block (FFB) External AC Characteristics
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120
XC73108 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121
XC73108 Pinouts (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123
XC73144
144-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128
Slew Rate and Programmable Ground Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128
Fast Function Block (FFB) External AC Characteristics
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131
XC73144 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132
XC73144 Pinouts (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134
XC7300 Characterization Data
XC7200 Series Table of Contents
XC7236A
36-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
FBs and macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148
Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-149
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
3.3 V or 5 V Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
Programming and Using the XC7236A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-151
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-153
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154
Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-155
Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162
XC7272A
72-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Function Blocks and Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-165
Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-166
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
8
Programming and Using the XC7272A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-169
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170
Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-171
Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172
Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-177
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
SRAM-Based FPGA Products
XC4000 Series Table of Contents
XC4000 Series
Field Programmable Gate Arrays
XC4000-Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Additional XC4000EX/XL Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
XC4000E and XC4000EX Families Compared to the XC4000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Improvements in XC4000E and XC4000EX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Additional Improvements in XC4000EX Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Configurable Logic Blocks (CLBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Function Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Latches (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Data Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Using Function Generators as RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Input/Output Blocks (IOBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
IOB Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Three-State Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
9
CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Quad Lines (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Direct Interconnect (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Octal I/O Routing (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Global Nets and Buffers (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Avoiding Inadvertent Boundary Scan Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
Cyclic Redundancy Check (CRC) for Configuration and Readback. . . . . . . . . . . . . . . . . . . . . . 4-57
Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Configuration Memory Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62
Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Release of Global Set/Reset After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . 4-65
Readback with the XChecker Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68
Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72
Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
10
Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
XC4000E Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . 4-83
XC4000E CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
XC4000E CLB Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . 4-85
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines . . . . 4-86
XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines 4-87
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . 4-88
XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs). . . . . . . . . . . . . . 4-90
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs) . . . . . . . . . . . 4-91
XC4000E IOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
XC4000E IOB Input Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . 4-93
XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
XC4000E IOB Output Switching Characteristic Guidelines (continued). . . . . . . . . . . . . . . . . . . 4-95
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . 4-96
XC4000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
XC4000EX Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
Pin Locations for XC4003E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
Pin Locations for XC4005E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98
Pin Locations for XC4006E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100
Pin Locations for XC4008E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-102
Pin Locations for XC4010E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104
Pin Locations for XC4013E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107
Pin Locations for XC4020E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110
Pin Locations for XC4036EX/XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-118
Pin Locations for XC4044EX/XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-123
Pin Locations for XC4052XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-128
Package-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133
PC84 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133
PQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134
VQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-135
PG120 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
TQ144 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-138
PG156 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-140
PQ160 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-142
TQ176 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
PG191 Package Pinouts (see PG223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-145
PG223 and PG191 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-149
BG225 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152
PQ240, HQ240 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154
PG299 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-157
HQ304 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-160
BG352 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
PG411 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-166
11
BG432 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-170
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-174
User I/O Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-176
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-178
XC5200 Series Table of Contents
XC5200
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
XC5200 Family Compared to XC4000 and XC3000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-182
Configurable Logic Block (CLB) Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-182
Input/Output Block (IOB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-184
VersaBlock: Abundant Local Routing Plus Versatile Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-184
VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
General Routing Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-186
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-186
Design Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
CLB Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
5-Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
Carry Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-189
Cascade Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-190
3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Global Reset (GR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
VersaBlock Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
Local Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
Direct Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
General Routing Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Single- and Double-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Global Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
VersaRing Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
Unrestricted User-Programmable I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-198
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Daisy Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Express Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-200
Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-200
Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
12
Power-On Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Start-Up and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204
Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-207
XC5200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-207
XC5200 Longline Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-208
XC5200 CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-209
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . 4-210
XC5200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-211
XC5200 CLB-to-Pad Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-212
Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-223
Pin Locations for XC5202 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-223
Pin Locations for XC5204 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-226
Pin Locations for XC5206 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-230
Pin Locations for XC5210 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-235
Pin Locations for XC5215 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
User I/O Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
XC5200L
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
XC5200L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC6200 Series Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253
XC6200
Field Programmable Gate Arrays
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Logical and Physical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Cells, Blocks and Tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-256
Magic Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Global Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Function Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Cell Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-258
Routing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-259
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
Clear Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
13
Input/Output Blocks (IOBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-263
Designing with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Board Design with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Logic Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Software Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-267
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-267
Map Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Wildcard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-270
Serial Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-271
Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-272
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-273
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-274
XC6200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Power-on/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Serial Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Cell Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . 4-277
XC6200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-277
XC6200 Internal Routing Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-278
XC6200 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-278
XC6200 Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-282
XC6216 Pinouts - West Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-282
XC6216 Pinouts - South Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-283
XC6216 Pinouts - East Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-284
XC6216 Pinouts - North Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-285
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-286
XC3000 Series Table of Contents
XC3000 Series
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
XC3000 Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-290
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-291
Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-291
I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-292
Summary of I/O Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-293
Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-294
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-295
General Purpose Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-296
Direct Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-296
Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-300
Internal Busses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-302
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-303
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-304
Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-304
Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-306
14
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Daisy Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Special Configuration Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
Input Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
Reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
DONE Pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
DONE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Crystal Oscillator Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Bitstream Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Reset Spike Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Soft Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-309
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-310
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-310
Master Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-312
Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-314
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-316
Program Readback Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-318
General XC3000 Series Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319
Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-320
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-321
Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-321
Dynamic Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-322
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-322
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
Unrestricted User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-324
Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-325
XC3000 Series Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-326
XC3000 Series 44-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-327
XC3000 Series 64-Pin Plastic VQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-328
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . 4-329
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-330
XC3000 Series 100-Pin QFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-331
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-332
XC3000 Series 144-Pin Plastic TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-333
XC3000 Series 160-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-334
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-335
XC3000 Series 176-Pin TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-336
XC3000 Series 208-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-337
XC3195A PQ208 and PG223 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-338
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-339
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-340
XC3000A
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
XC3000A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
XC3000A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
XC3000A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
15
XC3000A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-343
XC3000A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-343
XC3000A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-344
XC3000A CLB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . 4-345
XC3000A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-346
XC3000A IOB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . 4-347
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-348
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-348
XC3000L
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
XC3000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-351
XC3000L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-351
XC3000L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-352
XC3000L CLB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . 4-353
XC3000L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-354
XC3000L IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . 4-355
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-356
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-356
XC3100A
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
XC3100A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-359
XC3100A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-359
XC3100A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-360
XC3100A CLB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . 4-361
XC3100A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-362
XC3100A IOB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . 4-363
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-364
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-364
XC3100L
Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
XC3100L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
XC3100L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
XC3100L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-368
XC3100L CLB Switching Characteristics Guidelines (continued). . . . . . . . . . . . . . . . . . . . . . . . 4-369
XC3100L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-370
XC3100L IOB Switching Characteristics Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . 4-371
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-372
16
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-372
OTP FPGA Products
XC8100 FPGA Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Estimating XC8100 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Programmable Cell (CLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Cascade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Global Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Input/Output Cell (IOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Pull-up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
IEEE 1149.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
INTEST/EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
SAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
3.3 V Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Metastability Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
XACTstep Series 8000 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Workstation General Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Sun Sparcstation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
HP PA series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
RS 6000 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
IBM Compatible PC’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
XC8100 Synthesis Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
XC8100 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
XC8100 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
XC8101 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
XC8103 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
XC8106 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
XC8109 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
17
Package Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Product Availability (5/96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
SPROM Products
XC1700D Family of
Serial Configuration PROMs
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
RESET/OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
CE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
CEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
VPP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Serial PROM Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type 6-2
Controlling Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
FPGA Master Serial Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Programming the FPGA With Counters Unchanged Upon Completion . . . . . . . . . . . . . . . . . . . 6-3
Cascading Serial Configuration PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Programming the XC1700 Family Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
XC1718D, XC1736D, XC1765D, XC17128D and XC17256D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
XC1718L, XC1765L, XC17128L and XC17256L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
AC Characteristics Over Operating Condition (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
3V Products
3.3 V and Mixed Voltage Compatible Products
FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L, XC8100 . . . . . . . . . . . . . 7-1
3 V PCI-Compliant FPGA: XC3100L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL. . . . . . . . . . . . . . . . . . . . . 7-1
High-Density FPGAs Without On-chip RAM: XC5200L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
5 V Compatible Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
One-Time-Programmable FPGAs: XC8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX . . . . . . . . . . . . . . . . 7-1
CPLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
18
5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Supply Voltage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Interfacing Between 5 V and 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
3.3 V Devices Driving Inputs on 5 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
5 V Devices Driving Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
XC4000E/EX is Fully Compatible With 3.3 V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Hardwire Products
Xilinx HardWire™ Array Overview
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Advantages of Using Xilinx HardWire Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
HardWire versus Full ASIC Gate Array Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Reverifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Fault Coverage and Test Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Packaging and Silicon Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Support for the Entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
The HardWire Product Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Military Products
High-Reliability and Military Products
Unmatched Hi-Rel Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Committed to the Hi-Rel Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Xilinx Hi-Rel Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Programming Support
Programming Support
HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programs All Xilinx Nonvolatile Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programmer Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Interface Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programmer Functional Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programming Socket Adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Electrical Requirements and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Adapter Selector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Packages and Thermal Characteristics
Packages and Thermal Characteristics
Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Package Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Inches vs. Millimeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
EIA Standard Board Layout of Soldered Pads for QFP Devices . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Cavity Up or Cavity Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Clockwise or Counterclockwise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Method and Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
19
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Junction-to-Reference General Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Junction-to-Case Measurement — Q
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Junction-to-Ambient Measurement — Q
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Data Acquisition and Package Thermal Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Application of Thermal Resistance Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Example 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Example 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
PQ/HQ Thermal Data Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
The Package Offering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Where and When Offered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Mass Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Thermal Data for the HQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Other Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Moisture Induced Cracking During Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Factory Floor Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Dry Bake Recommendation and Dry Bag Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Handling Parts in Sealed Bags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Expiration Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Other Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Material and Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Cover Tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Bar Code Label. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Shipping Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Standard Bar Code Label Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Reflow Soldering Process Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
Plastic DIP Packages — PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
SOIC Packages — SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
TSOP Packages — VO8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
PLCC Packages — PC20, PC28, PC44, PC68, PC84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
PQFP Packages — PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240,
HQ304. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
TQFP Packages — TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . 11-38
VQFP Packages — VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
BGA Packages — BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
Ceramic DIP Packages — DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
Ceramic PGA Packages — PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223,
PG299, PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
Ceramic Brazed QFP Packages — CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . 11-61
CLCC Packages — CC20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67
Plastic PGA Packages — PP132, PP175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68
Windowed CLCC Packages — WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-70
20
Metal Quad Packages — MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-71
Testing, Quality, and Reliability
Quality Assurance and Reliability
Quality Assurance Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Device Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Description of Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Package Integrity and Assembly Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Testing Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Memory Cell Design in the FPGA Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
High Temperature Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Technical Support
Technical Support
Technical Support Hotlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
X-TALX: The Xilinx Network of Electronic Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
WebLINX World Wide Web Site
(www.xilinx.com). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
XDOCs E-mail Document Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
XFACTS Document Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Xilinx Technical Bulletin Board Service (408) 559-9327. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
File Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
E-mail addresses for questions related to specific applications . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Technical Support E-mail addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
AppLINX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
XCELL Newsletter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
What You Will Learn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
The Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Hands-On Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Instructors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Course Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Product Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Schematic-Based Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Synthesis-Based Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Synthesis-Based Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Update and Advanced Training Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Update Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Advanced Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
21
Xilinx Headquarters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
North American Distributor Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
International Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Customer-Site Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
On-Site Classes Provide Additional Benefits:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Scheduling a Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Tuition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Money-back Guarantee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Enrollment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Xilinx Training Registrar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Product Technical Information
Product Technical Information Table of Contents
Choosing a Xilinx Product Family
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
SRAM-Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200). . . . . . . . . . . . . . . . . . . 14-3
Overview of SRAM-Based FPGA Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) . . . . . . . . . . . . . . . 14-5
Antifuse-Based FPGAs (XC8100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
EPROM- and FLASH-Based CPLDs (XC7300, XC9500). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Overview of CPLD Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Selecting the Appropriate Xilinx Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Type of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Special Features Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
XC4000 Series
Technical Information
Voltage/Current Characteristics of XC4000-Family Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Additional Output Delays When Driving Capacitive Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Ground Bounce in XC4000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Test Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Interpretation of the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Guidelines for Reducing Ground-Bounce Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Ground-Bounce vs Delay Trade-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
XC4000 and XC4000E Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
XC3000 Series
Technical Information
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Configurable Logic Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Function Generator Avoids Glitches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
I/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Horizontal Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Internal Bus Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
22
Vertical Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Clock Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Crystal-Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Practical Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20
Series Resonant or Parallel Resonant? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
CCLK Frequency Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
CCLK Low-Time Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Battery Back-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Things to Remember . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Things to Watch Out For. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Configuration and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Beware of a Slow-Rising XC3000 Series RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
FPGA Configuration Guidelines
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Protection Against Data or Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Start-Up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
Selecting the Best Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
When Configuration Fails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
General Debugging Hints for all Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
General Debugging Hints for the XC2000 and XC3000 Families. . . . . . . . . . . . . . . . . . . . . . . . 14-30
General Debugging Hints for the XC4000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Additional Mode-Specific Debugging Hints for All Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Master Parallel Up and Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Do Not Let the VPP Pin Float . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
Daisy Chain Debugging Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
Potential Length-Count Problem in Parallel or Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . 14-32
Miscellaneous Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
Configuring Mixed FPGA
Daisy Chains
Configuration Issues:
Power-up, Volatility, Security, Battery Back-up
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
Sensitivity to V
CC
Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Design Security when Configuration Data is Accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Design Security by Hiding the Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
Battery Back-up and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Things to Remember: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Things to Watch Out for:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Dynamic Reconfiguration
Important Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
23
Reconfiguration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
Initiating Reconfiguration in Different Xilinx Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
XC2000 and XC3000 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
XC4000 Series and XC5200 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
Metastable Recovery
Metastability Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42
Metastability Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42
Set-up and Hold Times
Overshoot and Undershoot
Boundary Scan in XC4000 and XC5000 Series Devices
Overview of XC4000/XC5000 Boundary-Scan Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49
Deviations from the IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50
Boundary-Scan Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
The Boundary-Scan Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
The Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
Using Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54
Boundary Scan Description Language Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57
Index
Index
Sales Offices, Sales Representatives, and Distributors
Sales Offices
24
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Introduction
An Introduction to Xilinx Products
About this Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Programmable Logic vs. Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Shortest Time-to-Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Complex Programmable Logic Devices (CPLDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Introduction Table of Contents
1-1
About this Book
This Data Book provides a “snapshot in time” in its listing of
IC devices and development system software available
from Xilinx as of early 1996. New devices, speed grades,
package types and development system products are con-
tinually being added to the Xilinx product portfolio. Users
are encouraged to contact their local Xilinx sales represen-
tative and consult the W ebLINX W orld Wide Web site (http:/
/www.xilinx.com) and the quarterly XCELL newsletter for
the latest information regarding new product availability.
The product specifications for several older Xilinx FPGA
families are not included in this Data Book. This does not
imply that these products are no longer av ailable. However,
for new designs, users are encouraged to use the newer
products described in this book, which offer better perfor-
mance at lower cost than the older technologies. Product
specifications for the older products are available at
WebLINX, the Xilinx site on the W orld Wide Web , or through
your local Xilinx sales representative. These products
include the following FPGA families: the XC2000, XC3000,
XC3100, XC4000, XC4000A, XC4000D, and XC4000H
families.
Data Sheet Categories
In order to provide the most up-to-date information, some
component products included in this book may not have
been fully characterized at the time of publication. In these
cases, the AC and DC characteristics included in the data
sheets will be marked as
Advance
or
Preliminary
informa-
tion. (Not withstanding the definitions of such terms, all
specifications are subject to change without notice.) These
designations have the following meaning:
•Advance — Initial estimates based on simulation and/
or extrapolation from other speed grades, devices, or
device families. Use as estimates, but not for final
production.
•Preliminary — Based on preliminary characterization.
Changes are possible, but not expected.
•Final (unmarked) — Specifications not identified as
either Advance or Preliminary are to be considered
final.
Data Book Contents
Chapter 1 is a general overview of the Xilinx product line,
and is recommended reading for designers who are new to
the field of high-density programmable logic.
Chapter 2 contains a discussion of the overall design
methodology when using Xilinx programmable logic and
descriptions of Xilinx development system products. This
chapter is placed at the beginning of the book since these
dev elopment tools are needed to design with an y of the Xil-
inx programmable logic devices.
Chapter 3 contains the product descriptions for the Xilinx
Complex Programmable Logic Device (CPLD) products,
including the XC7000 and XC9000 series.
Chapter 4 includes the product descriptions for the Xilinx
static-memory-based Field Programmable Gate Array
(FPGA) products, including the XC3000, XC4000, XC5000,
and XC6000 series.
Chapter 5 contains the product descriptions for the one-
time-programmable XC8000 FPGA series.
Chapter 6 holds the product descriptions for the XC1700
family of Serial PROM devices. These Serial PROMs pro-
vide a convenient, low-cost means of storing configuration
programs for the SRAM-based FPGAs described in Chap-
ter 4.
Chapter 7 is an ov erview of Xilinx components appropriate
for 3.3 V and mixed-voltage systems . This chapter will refer
you bac k to the appropriate product descriptions in the ear-
lier chapters.
Chapter 8 contains a brief overview of the HardWire prod-
uct line. Detailed product specifications are available in
separate Xilinx data sheets.
Chapter 9 is an overview of Xilinx High-Reliability/Military
products. Detailed product specifications are available in
separate Xilinx data sheets.
Chapter 10 describes the HW130 device programmer for
the XC1700 series of Serial PROMs, the XC7000 and
XC9000 series of CPLDs, and the XC8000 FPGA series.
Chapter 11 contains a description of all the physical pack-
ages for the various IC products, including information
about the thermal characteristics of those packages.
Chapter 12 discusses the testing, quality, and reliability of
Xilinx component products.
Chapter 13 includes a listing of all the technical support
facilities provided by Xilinx.
Chapter 14 contains additional information about Xilinx
components that is not provided in the product specifica-
tions of the earlier chapters. This includes some additional
electrical parameters that are not in the product specifica-
An Introduction to Xilinx Products
An Introduction to Xilinx Products
1-2
tions because they are not part of the manufacturing test
program for the particular device, but may be of interest to
the user. Also included in this chapter is a discussion of the
JTAG boundary test scan logic found in several Xilinx com-
ponent families.
The final two sections contain an index to the topics
included in this Data Book and a listing of Xilinx sales
offices, sales representatives, and distributors.
About the Company
Xilinx, Inc., offers the industry’s broadest selection of pro-
grammab le logic devices. With 1995 rev en ues of o ver $500
million, Xilinx is the world’s largest supplier of programma-
ble logic, and the market leader in Field Programmable
Gate Arrays (FPGAs).
Xilinx was f ounded in 1984, based on the rev olutionary idea
of combining the logic density and versatility of gate arrays
with the time-to-market advantages and convenience of
user-programmable standard parts. One year later, Xilinx
introduced the world’ s first Field Progr ammab le Gate Arra y.
Since then, through a combination of architectural and
manufacturing process improvements, the company has
continually increased device performance, in terms of
capacity, speed, and ease-of-use, while lowering costs.
In 1992, Xilinx expanded its product line to include
advanced Complex Programmable Logic Devices (CPLDs,
also known as EPLDs). For the user, CPLDs are an attrac-
tive complement to FPGAs, offering simpler design soft-
ware and more predictable timing.
As the market leader in one of the fastest growing seg-
ments of the semiconductor industry, Xilinx strategy is to
focus its resources on creating new ICs and development
system software, providing world-class technical support,
developing mar kets, and building a diverse customer base
across a broad range of geographic and end-use applica-
tion segments. The company has avoided the large capital
commitment and overhead burden associated with sole
ownership and operation of a wafer fabrication facility.
Instead, Xilinx has established alliances with several high-
volume, state-of-the-art CMOS IC manufacturers. Using
standard, high-volume processes assures low manufactur-
ing costs, produces programmable logic devices with well-
established reliability, and provides for early access to
advances in CMOS processing technology.
Xilinx headquarters are located in San Jose, Calif ornia. The
company markets its products worldwide through a network
of direct sales offices, manufacturers’ representatives, and
distributors (as listed in the back of this book). The com-
pany has representatives and distributors in over 38 coun-
tries.
1-3
Product Line Overview
Field Programmable Gate Arrays (FPGAs) and Complex
Programmable Logic Devices (CPLDs) can be used in vir-
tually any digital logic system. Ov er 35 million Xilinx compo-
nents have been used in a wide variety of end-equipment
applications, ranging from supercomputers to hand-held
instruments, from central office s witches to centrifuges, and
from missile guidance systems to guitar synthesizers.
Xilinx achieved its leading position through a continuing
commitment to provide a complete product solution. This
encompasses a focus on all three critical areas of the high-
density programmable solution “triangle”: components (sili-
con), software, and service (Figure 1).
Programmable Logic vs. Gate Arrays
Xilinx programmable logic devices provide the benefits of
high integration levels without the risks or expenses of
semi-custom and custom IC development. Some of the
benefits of programmable logic as versus mask-pro-
grammed gate arrays are briefly discussed below.
Faster Design and Verification
Xilinx FPGAs and CPLDs can be designed and verified
quickly while the same process requires se ver al weeks with
gate arrays. There are no non-recurring engineering (NRE)
costs, no test vectors to generate, and no delay while wait-
ing for prototypes to be manufactured.
Design Changes without Penalty
Because the devices are software-configured and user-
programmed, modifications are much less risky and can be
made anytime - in a manner of minutes or hours, as
opposed to the weeks it would take with a gate array. This
results in significant cost savings in design and production.
Shortest Time-to-Market
When designing with Xilinx programmable logic, time-to-
market is measured in da ys or a f ew w eeks, not the months
often required when using gate arrays. A study by market
research firm McKinsey & Co. concluded that a six-month
delay in getting to mark et can cost a product one-third of its
lifetime potential profit. With mask-programmed gate
arra ys, design iterations can easily add that m uch time, and
more, to a product schedule.
Once the decision has been made to use Xilinx program-
mable logic , a choice must be made from a number of prod-
uct families, device options, and product types. The
information in the product selection matrices that follo w can
help guide that selection; detailed product specifications
are available in subsequent chapters of this book. Since
many component products are available in common pack-
ages with common footprints, designs often can be
migrated to higher or lo w er density devices, or ev en across
some product families, without any printed circuit board
changes. Design ideas, represented in text or schematic
format, are converted into a configuration data file for an
FPGA or CPLD device using the Xilinx XACT
step
develop-
ment software running on a PC or workstation.
Component Products
Xilinx offers the broadest line of programmable logic
devices a vailab le today, with hundreds of products featuring
various combinations of architectures, logic densities,
package types , and speed grades in commercial, industrial,
and military grades. This breadth of product offerings
allows the selection of the programmable logic device that
is best suited for the target application.
Xilinx programmab le logic off erings include se v eral families
of reprogrammable FPGAs, one-time-programmable
• Optimized circuits/architectures
• Global world class sales/distribution support
• Global world class technical support: FAEs/support center/on-line/internet
• Global world class manufacturing: quality/capacity/delivery
• Powerful but easy
• Integrated across families
• Seamless integration into
customer CAE system
• Highest performance/densities
• Deep submicron processes
• Unmatched quality 
and reliability
SOFTWARE
SILICON
SERVICE
X5955
Figure 1: The Xilinx Programmable Solution Triangle
An Introduction to Xilinx Products
1-4
FPGAs, EPROM-based CPLDs, and FLASH-memory-
based CPLDs (Figure 2). HardWire de vices are mask-pro-
grammed versions of the reprogrammable FPGAs, and
provide a transparent, no-risk migration path to lower-cost
devices for high-volume, stable designs. Additionally, a
family of Serial PR OM de vices is av ailab le to store configu-
ration programs for the reprogrammable FPGA devices.
Many devices are available in military temperature range
and/or MIL-STD-883B versions, for high-reliability and mili-
tary applications.
Field Programmable Gate Arrays (FPGAs)
FPGA devices feature a gate-array-like architecture, with a
matrix of logic cells surrounded by a peripher y of I/O cells,
as diagrammed in Figure 3. Segments of metal intercon-
nect can be linked in an arbitrary manner by progr ammab le
switches to form the desired signal nets between the cells.
FPGAs combine an abundance of logic gates, registers,
and I/Os with fast system speed. Xilinx offers several fami-
lies of reprogrammable, static-memory-based (SRAM-
based) FPGAs, including the XC2000, XC3000, XC4000,
XC5000, and XC6000 series. One Xilinx FPGA family, the
XC8100 family, is based on the one-time-programmable
MicroVia antifuse technology.
Complex Programmable Logic Devices (CPLDs)
Designers more comfortable with the speed, design sim-
plicity, and predictability of PALs may pref er CPLD devices.
Conceptually, CPLDs consist of multiple PAL-like function
blocks that can be interconnected through a switch matrix
(Figure 4). The Xilinx XC7000 CPLD series is based on
EPROM technology. The new XC9000 CPLD series fea-
tures 5V in-system programmab le FLASH technology, and,
like most of the FPGA families, includes built-in JTAG
boundary scan test logic.
HardWire devices
HardWire devices are mask ed-progr ammed versions of the
SRAM-based FPGAs. The HardWire products provide an
easy, transparent migration path to a cost-reduced device
without the engineering burden associated with conven-
tional gate array re-design. The HardWire gate array is
architecturally identical to its FPGA counterpart, but the
programmable elements in the FPGA are replaced with
fixed metal connections. The resulting die is considerably
smaller, with a correspondingly lower cost. Using propri-
etary automatic test vector generation software and pat-
Xilinx
Product Line
CPLD
ISP
PAL Architecture
Medium Density
Simple Tools
Gate Arrays
Custom
Highest Density
ASIC Tools
FPGA
Programmable
Gate Array
Architecture
High Density
ASIC Tools
HardWire™
Custom
Transparent Conversion
100% Tested
ASIC Alternatives
X5957
PAL Devices
Programmable AND/OR
Architecture
Low Density
Simple Tools
Figure 2: Application-Specific IC Products
PROGRAMMABLE
INTERCONNECT
LOGIC BLOCKS
I/O BLOCKS
X1153
Figure 3: FPGA Architecture
1-5
ented test logic, Xilinx guarantees o v er 95% f ault cov erage ,
while eliminating the need for user-generated test vectors.
The mask and test programs are generated automatically
by Xilinx from the user’s existing FPGA design file.
Serial PROMs
The XC1700 family features one-time programmable serial
PROMs ranging in density from about 18,000 bits to over
260,000 bits. These serial PROMs are an easy-to-use,
cost-effective method for storing configuration data for the
SRAM-based FPGAs.
High-Reliability Devices
Xilinx was the first company to offer high-reliability FPGAs
by introducing MIL-STD-883B qualified XC2000 and
XC3000 series devices in 1989. MIL-STD-883B members
of the XC4000 FPGA series also are available, and quali-
fied versions of additional Xilinx families are in develop-
ment. The product line also includes Standard Microcircuit
Drawing (SMD) versions of several families. Some Xilinx
devices are available in tested die form through arrange-
ments with manufacturing partners.
Development System Products
Xilinx offers a complete softw are environment f or the imple-
mentation of logic designs in Xilinx programmable logic
devices. This environment, called XACT
step
, combines
powerful technology with a flexible, easy-to-use graphical
interface to help users achieve the best possible designs,
regardless of experience level. The user has a wide range
of choices between a fully-automatic implementation and
detailed involvement in the layout process. The XACT
step
system provides all the implementation tools required to
design with Xilinx logic devices, including the following:
• libraries and interfaces for popular schematic editors,
logic synthesis tools, and simulators
• design manager/flow engine
• module generator
• map, place, and route compilation software
• graphical floorplanner
• static timing analyzer
• hardware debugger
Xilinx is committed to an “open system” approach to front-
end design creation, synthesis, and verification. Xilinx
devices are supported by the broadest number of ED A v en-
dors and synthesis vendors in the industry. Supported plat-
forms include the ubiquitous PC and several popular
workstations.
Service
Providing global, world-class manufacturing, technical sup-
por t, and sales/distribution suppor t is an essential founda-
tion of the Xilinx product strategy. Xilinx manufacturing
facilities have earned ISO9002 certification, and Xilinx
quality and reliability achievements are among the wor ld’s
best - not just for programmab le logic suppliers, but among
all semiconductor companies. Comprehensive technical
support facilities include training courses, extensive prod-
uct documentation and application notes, a quarter ly tech-
nical newsletter, automated document ser vers, a technical
bulletin board, the WebLINX World Wide Web site, techni-
cal support hotlines, and a cadre of Field Application Engi-
neers. Sales support is provided b y a w orldwide network of
representatives and distributors.
X5956
FB FB
FB
FB
FB
FB
FB
FB
I/O I/O
Interconnect
Matrix
Figure 4: CPLD Architecture
An Introduction to Xilinx Products
1-6
FPGA Product Selection Matrix
DEVICES
XC3000 Series
XC3020A/L
XC3030A/L
XC3042A/L
XC3064A/L
XC3090A/L
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
XC3142L
XC3190L
KEY
FEATURES
Low Cost/
Low Power Highest Performance
Low Voltage
(3.3 V)
Highest
Performance
DENSITY
Max Logic Gates (K) 1.5 23561.52356836
Max RAM Bits N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Typical Gate Range (K) 1-1.5 1.5-2 2-3 4-5 5-6 1-1.5 1-2 2-3 4-5 5-6 7-8 2-3 5-6
CLBs 64 100 144 224 320 64 100 144 224 320 484 144 320
Flip-Flops 256 360 480 688 928 256 360 480 688 928 1320 480 928
FEATURES
Output Drive (mA) 4444488888844
JTAG (IEEE 1149.1) NNNNNNNNNNNNN
Dedicated Arithmetic NNNNNNNNNNNNN
Quiescent Current (mA) 0.5/
0.02 0.5/
0.02 0.5/
0.02 0.5/
0.02 0.5/
0.02 8888881.51.5
PERFORMANCE
Fastest Speed Grade -6/-8 -6/-8 -6/-8 -6/-8 -6/-8 -09 -09 -09 -09 -09 -09 -2 -2
Shift Register (MHz) 124/69 124/69 124/69 124/69 124/69 312 312 312 312 312 312 256 256
Small State Machine (MHz) 42/23 42/23 42/23 42/23 42/23 112 112 112 112 112 112 68 68
Large State Machine (MHz) 21/14 21/14 21/14 21/14 21/14 55 55 55 55 55 55 33 33
4-Bit Multiply-Accumulator (MHz) 20/12 20/12 20/12 20/12 20/12 51 51 51 51 51 51 33 33
16-Bit Accumulator (MHz) 25/15 25/15 25/15 25/15 25/15 58 58 58 58 58 58 41 41
Address Map Decoder (MHz) 52/27 52/27 52/27 52/27 52/27 127 127 127 127 127 127 84 84
Data Path (MHz) 147/86 147/86 147/86 147/86 147/86 335 335 335 335 335 335 84 84
Counter Timer (MHz) 37/23 37/23 37/23 37/23 37/23 81 81 81 81 81 81 56 56
16-Bit Non Loadable Counter (MHz) 135/81 135/81 135/81 135/81 135/81 370 370 370 370 370 370 323 323
16-Bit Loadable Binary Up Counter (MHz) 39/25 39/25 39/25 39/25 39/25 91 91 91 91 91 91 63 63
16-Bit Loadable Prescaled Counter (MHz) 100/59 100/59 100/59 100/59 100/59 228 228 228 228 228 228 154 154
RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pad to Setup (ns) 14/12 14/12 14/12 14/12 14/12 2.5 2.5 2.5 2.5 2.5 2.5 4 4
Clock to Pad (ns) 7/18 7/18 7/18 7/18 7/18 44444455
Combinatorial Pad to Pad (ns) 14/25 14/25 14/25 14/25 14/25 66666688
1-7
FPGA Product Selection Matrix (continued)
*Usable gates assume 20% of CLBs used as RAM
*Usable gates assume 20% of CLBs used as RAM
DEVICES
XC4000 Series
XC4003E*
XC4005E*
XC4006E*
XC4008E*
XC4010E*
XC4013E*
XC4020E*
XC4025E*
XC4028EX
XC4036EX
XC4044EX
XC4052XL
XC4062XL
XC4003H
XC4005H
XC4005L
XC4010L
XC4013L
KEY
FEATURES
High Density
High Performance
Select-RAM™ Memory
High
I/O Low Voltage
(3 V)
DENSITY
Max Logic Gates, (no RAM) (K) 3 5 6 8 10 13 20 25 28 36 44 52 62 3 5 5 10 13
Max RAM Bits (no Logic) 3200 6272 8192 10368 12800 18342 25088 32768 32768 41472 51200 61952 73728 3200 6272 6272 12800 18432
Typical Gate Range (Logic and RAM) (K) 2-5 3-9 4-12 6-15 7-20 10-30 13-40 15-45 18-50 22-65 27-80 33-100 40-130 2-5 3-9 3-9 7-20 10-30
CLBs 100 196 256 324 400 576 784 1024 1024 1296 1600 1936 2304 100 196 196 400 576
Flip-Flops 360 616 768 936 1120 1536 2016 2560 2560 3168 3840 4576 5376 200 392 616 1120 1536
FEATURES
Output Drive (mA) 12 12 12 12 12 12 12 12 12 12 12 12 12 24 24 4 4 4
JTAG (IEEE 1149.1) Y Y Y YYYYYYYYY YYYYYY
Dedicated Arithmetic Y Y Y YYYYYYYYY YYYYYY
Quiescent Current (mA) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 0.05 0.05 0.05
PERFORMANCE
Fastest Speed Grade -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -5 -5
CONTACT FACTORY
Shift Register (MHz) 190 190 190 190 190 190 190 190 190 190 190 190 190 105 105
Small State Machine (MHz) 69 69 69 69 69 69 69 69 69 69 69 69 69 48 48
Large State Machine (MHz) 43 43 43 43 43 43 43 43 43 43 43 43 43 37 37
4-Bit Multiply-Accumulator (MHz) 39 39 39 39 39 39 39 39 39 39 39 39 39 20 20
16-Bit Accumulator (MHz) 65 65 65 65 65 65 65 65 65 65 65 65 65 36 36
Address Map Decoder (MHz) 71 71 71 71 71 71 71 71 71 71 71 71 71 43 43
Data Path (MHz) 156 156 156 156 156 156 156 156 156 156 156 156 156 105 105
Counter Timer (MHz) 117 117 117 117 117 117 117 117 117 117 117 117 117 58 58
16-Bit Non Loadable Counter (MHz) 180 180 180 180 180 180 180 180 180 180 180 180 180 95 95
16-Bit Loadable Binary Up Counter (MHz) 87 87 87 87 87 87 87 87 87 87 87 87 87 42 42
16-Bit Loadable Prescaled Counter (MHz) 115 115 115 115 115 115 115 115 115 115 115 115 115 63 63
RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 50 50
Pad to Setup (ns) 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 7 7
Clock to Pad (ns) 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 10 10
Combinatorial Pad to Pad (ns) 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 5 5
DEVICES
XC5000, XC6000, XC8000 Series
XC5202
XC5204
XC5206
XC5210
XC5215
XC6209
XC6216
XC6236
XC6264
XC8100
XC8101
XC8103
XC8106
XC8109
KEY
FEATURES
High Density
Low Cost µP Interface
Fast Configuration
Single Chip
Design Security
ASIC Design Flow
DENSITY
Max Logic Gates (K) 3 6 10 16 23 13 24 55 100 1 2 8 13 20
Max RAM Bits N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Typical Gate Range (K) 2-3 4-6 6-10 10-16 15-23 9-13 16-24 36-55 64-100 0.6-1 1-2 3-8 6-13 9-20
CLBs/Logic Cells 64 120 196 324 484 2304 4096 9216 16384 192 384 1024 1728 2688
Flip-Flops 256 480 784 1296 1936 2304 4096 9216 16384 96 192 512 864 1344
FEATURES
Output Drive (mA) 8888888882424242424
JTAG (IEEE 1149.1) YYYYYNNNNYYYYY
Dedicated Arithmetic YYYYYNNNNNNNNN
Quiescent Current (mA) 15 15 15 15 15 ––––55101010
PERFORMANCE
Fastest Speed Grade -4 -4 -4 -4 -4
CONTACT FACTORY
-1 -1 -1 -1 -1
Shift Register (MHz) 83 83 83 83 83 123 123 123 123 123
Small State Machine (MHz) 50 50 50 50 50 48 48 48 48 48
Large State Machine (MHz) 35 35 35 35 35 33 33 33 33 33
4-Bit Multiply-Accumulator (MHz) 24 24 24 24 24 N/A N/A N/A N/A N/A
16-Bit Accumulator (MHz) 60 60 60 60 60 30 30 30 30 30
Address Map Decoder (MHz) 69 69 69 69 69 N/A N/A N/A N/A N/A
Data Path (MHz) 83 83 83 83 83 103 103 103 103 103
Counter Timer (MHz) 59 59 59 59 59 N/A N/A N/A N/A N/A
16-Bit Non Loadable Counter (MHz) N/A N/A N/A N/A N/A 102 102 102 102 102
16-Bit Loadable Binary Up Counter (MHz) 58 58 58 58 58 40 40 40 40 40
16-Bit Loadable Prescaled Counter (MHz) 83 83 83 83 83 51 51 51 51 51
RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Pad to Setup (ns) 6.6 6.6 6.6 6.6 6.6 7.5 7.5 7.5 7.5 7.5
Clock to Pad (ns) 14.2 14.2 14.2 14.2 14.2 77777
Combinatorial Pad to Pad (ns) 15 15 15 15 15 9.5 9.5 9.5 9.5 9.5
An Introduction to Xilinx Products
1-8
CPLD Product Selection Matrix
DEVICES
CPLD Families
XC7318
XC7336
XC7336Q
XC7354
XC7372
XC73108
XC73144
XC9536
XC9572
XC95108
XC95144
XC95180
XC95216
XC95288
XC95432
XC95576
KEY
FEATURES
100% Routable
100% Utilization
5 ns TPD
JTAG
5 V ISP
3 V or 5 V I/O
DENSITY
Gates (K) 0.4 0.8 0.8 1.5 1.9 3.0 3.8 0.8 1.6 2.4 3.2 4.0 4.8 6.4 9.6 12.8
Macrocells 18 36 36 54 72 108 144 36 72 108 144 180 216 288 432 576
Flip-Flops 18 36 36 108 126 198 234 36 72 108 144 180 216 288 432 576
FEATURES
Output Drive (mA) 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
JTAG (IEEE 1149.1) NNNNNNNYYYYYYYYY
Dedicated Arithmetic N N N YYYYNNNNNNNNN
Quiescent Current (mA) 90 126 50 140 187 227 250 – – 140 ––––––
PERFORMANCE
Fastest Speed Grade -5 -5 -10 -7 -7 -7 -7 -5 -7 -7 -7 -10 -10 -10 – –
Shift Register (MHz) 125 125 95 95 95 95
CONTACT FACTORY
Small State Machine (MHz) 108 108 95 95 95 95
Large State Machine (MHz) 102 102 95 95 95 95
4-Bit Multiply-Accumulator (MHz) 46 46 52 52 52 52
16-Bit Accumulator (MHz) 40 40 63 63 63 63
Address Map Decoder (MHz) 108 108 95 95 95 95
Data Path (MHz) 125 125 95 95 95 95
Counter Timer (MHz) 94 94 47 47 47 47
16-Bit Non Loadable Counter (MHz) 125 125 95 95 95 95
16-Bit Loadable Binary Up Counter (MHz) 125 125 95 95 95 95
16-Bit Loadable Prescaled Counter (MHz) 125 125 95 95 95 95
RAM Read Modify Write (MHz) N/A N/A N/A N/A N/A N/A
Pad to Setup (ns) 3.5 3.5 4444
Clock to Pad (ns) 4.5 4.5 7777
Combinatorial Pad to Pad (ns) 5 5 7777
Number
of Pins
PACKAGE OPTIONS AND USER I/O
Package (Code)
MAX I/O 38 38 38 58 84 120 156 34 72 108 133 168 168 192 232 232
PLCC (PC) 44 38 38 38 38 34
PQFP (PQ) 44 38 38 38 34
CLCC (WC) 44 38 38 38
VQFP (VQ) 44 38
PLCC (PC) 68 58 57
CLCC (WC) 68 58 57
PLCC (PC) 84 72 72 69 69
CLCC (WC) 84 72 72
PGC (PG) 84
PQFP (PQ) 100 84 84 72 81 81
TQFP (TQ) 100 72 81
PGA (PG) 144 120
PQFP (PQ) 160 120 136 108 133 133 133
HQFP (HQ) 208 168 168 168
BGA (BG) 225 120 156
HQFP (HQ) 304 192 232 232
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Development System Products
Development Systems Products Overview
XACTstep: Accelerating Your Productivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Six Powerful New Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Xilinx Software on CD-ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Support and Update Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Software Series Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Individual Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Bundled Packages Product Descriptions
Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Foundation Series: Foundation Base System with VHDL Synthesis (PC) . . . . . . . . . . . . . . . . . . . . . . . 2-13
Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Foundation Series: Foundation Standard System with VHDL (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Alliance Series: OrCAD – Base System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Alliance Series: OrCAD – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Alliance Series: Viewlogic – Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Alliance Series: Viewlogic – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Alliance Series: Viewlogic Stand-alone – Base System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Alliance Series: Viewlogic Stand-alone – Standard System (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Alliance Series: Viewlogic Stand-alone – Extended System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Alliance Series: Viewlogic – Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Alliance Series: Mentor V8 – Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Alliance Series: Synopsys – Standard System (Workstation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Alliance Series: Cadence – Standard System (Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Alliance Series: Third Party Alliance – Standard System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Individual Product Descriptions
FPGA Core Implementation – DS-502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
CPLD Core Implementation – DS-560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Schematic and Simulator Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
X-BLOX – DS-380. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Xilinx ABEL Design Entry – DS-371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Xilinx ABEL Design Entry – DS-571 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Xilinx-Synopsys Interface (XSI) – DS-401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
XChecker Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Demonstration Board – FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Development System Products
Table of Contents
June 1, 1996 (Version 1.0) 2-1
XACT
step:
Accelerating Y our
Productivity
The newest version of the XACT development system,
XACT
step
, started shipping in the fourth quarter of 1995.
XACT
step
software f eatures a re volutionary combination of
power and ease-of-use to provide accelerated learning
curves, short implementation cycles, and faster design
debug. This high-productivity en vironment contains six ne w
productivity tools that are easily accessible through graphi-
cal tool bars, icons and pop-up menus. They support the
complete spectrum of programmable logic design method-
ology from fully automatic to hand-crafted.
All the tools in XACT
step
feature a ne w graphical user inter-
face (GUI). On the PC, the GUI is fully Microsoft Windows
compliant.
With this new GUI, all progr ams are ex ecuted from tool bars
and icons. Tool tips provide instant descriptions and on-line
help is available for more in-depth information. Report
browsers present message files with plain English titles and
allow simultaneous viewing of multiple documents.
Six Powerful New Tools
• The new Design Manager provides a complete project
management environment for a wide range of families.
It provides version control, device re-targeting and
design re-use.
• The configurable Flow Engine lets designers choose
the amount of control they want over the
implementation process. They can choose a fully
automatic flow or set break points that allow analysis
and optimization of results before proceeding to the
next step.
•XACT
step
contains the industry’s first gr aphically-based
hierarchical Floorplanner. This tool pro vides techniques
that have proven to be extremely valuable to gate array
and custom silicon designers. Using floorplanning, it is
easy to achiev e hand-cr afted le vels of perf ormance and
density without resorting to low-level manual
techniques. Floorplanning is valuable for any design
that has a high degree of structure or a large number of
gates. It also allows optimization of specialized
structures like Xilinx unique high-speed distributed
RAM and three-state internal bus features.
• The new interactive Timing Analyzer makes it easy to
quickly determine a design’s performance by
generating custom timing reports. Using pop-up menus,
it is quickly configured to show the delay along a
specific path or group of paths. It also shows the delay
along all paths of a certain type or those associated
with a specific clock signal. In addition, the Timing
Analyzer automatically compares the design’s actual
performance to XACT-Performance goals and shows
the estimated maximum frequency f or each cloc k in the
design.
• The Hardware Debugger allows verification of
configuration data and viewing of internal signal activity.
It takes advantage of the reprogrammability of SRAM-
based devices by configuring the FPGA in-circuit using
a cable connected to a host PC or workstation. After
configuring the device, bitstream data is read back
through the cable for automatic verification.
While the device is running, an unlimited number of
internal nodes can be probed and displayed in a wave-
form window.
• The new PROM Formatter in XACT
step
assists the
designer in creating PROM progr amming files . This tool
chooses the best PROM siz e or automatically splits the
data into multiple files if multiple PR OMs are required. It
supports serial and byte-wide PROMs in four different
formats. If the target system uses the daisy chain
capability of the Xilinx FPGA, the PROM formatter
graphically creates the load order and verifies the load
sequence.
The Xilinx Design Manager—Simplifies the
Design Flow
• Source and revision control
• Permits running all Xilinx software from menus
• Automates design translation via XMake facility
• Provides on-line help for all menus, programs and
options
.Flow Engine
• Automatically invokes all implementation programs as
required to compile a design into an FPGA or CPLD
• Supports hierarchically-structured designs
Extensive On-line Help
• The Design Manager contains on-line Help for
Every menu
Every program
Every program option
Design-flow suggestions
Development Systems Products
Overview
June 1, 1996 (Version 1.0)
Development Systems Products Overview
2-2 June 1, 1996 (Version 1.0)
Design Flow Overview
This section describes the Xilinx Automated CAE Tools
(XACT) design environment for Xilinx FPGA and CPLD
devices.
High-density programmable logic has created unique
requirements for CAE software; the tools must deliver the
ease-of-design and fast time-to-market benefits that have
popularized FPGA and CPLD technologies, must be capa-
ble of implementing high-density logic designs on an engi-
neer’s desktop system, and must be easy-to-use and
compatible with the user’s existing design environment.
In order to meet those needs, Xilinx offers a variety of
development system products optimized to support the Xil-
inx FPGA and CPLD architectures. Available products
include state-of-the-art design implementation software,
libraries and interfaces to popular schematic editors, syn-
thesis and timing simulators, and behavioral-based design
entry tools. All Xilinx development system software is inte-
grated under the Xilinx Design Manager, providing design-
ers with a common user interface regardless of their choice
of device architecture and tools.
As with other logic technologies, the basic methodology for
FPGA design consists of three interrelated steps: entry,
implementation, and verification. (Figure 2 - Figure 4). The
design process is iterative, returning to the design entry
phase for correction and optimization. Popular generic
tools are used for entry and simulation (for example, View-
logic System’s PROcapture schematic editor and PROsim
simulator), but architecture-specific tools are needed for
implementation.
Design Entry
Schematic editors and synthesis are the most-popular
methodologies for design entry. FPGA/CPLD symbol librar-
ies and netlist interfaces are a vailable for schematic editors
from vendors such as Viewlogic, OrCAD, Mentor Graphics,
and Cadence. These libraries reflect the wide variety of
logic functions that can be implemented in FPGA/CPLD
devices.
Behavioral-oriented design entry methods, including Bool-
ean equations and state-machine descriptions, are sup-
por ted by the Xilinx ABEL and LogiBloxs products, as well
as a number of products from CAE vendors such as Data
I/O, Logical Devices, MINC, and ISDATA.
As the density and complexity of FPGA and CPLD designs
increase to 10,000 gates and bey ond, gate-le vel entry tools
often are cumbersome, and the use of logic synthesis and
high-level description languages (HDLs), such as VHDL
and Verilog, can raise designer productivity. The use of
HDLs requires synthesis tools that effectively compile
designs for the target architecture. Xilinx offers interfaces
for synthesis tools from Synopsys. Other CAE vendors,
such as Mentor Graphics, Cadence Design Systems , Vie w-
logic, and Exemplar Logic, also offer synthesis tools tai-
lored for the Xilinx device architectures.
Figure 1: Design Manager Main Window
June 1, 1996 (Version 1.0) 2-3
Many engineers prefer visually oriented design-entr y tech-
niques over text-based HDLs. The benefits of HDLs are
provided to these designers with tools that provide high-
level design constructs in a symbolic format compatible
with graphics-based schematic editors . X-BLOX is a graph-
ics-based high-level language that allows designers to use
a schematic editor to enter designs as a set of generic
modules. The X-BLOX compiler optimizes the modules for
the target device architecture, automatically choosing the
appropriate architectural resources for each function.
The XACT
step
design environment supports hierarchical
design entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic in each block. The implementation tools automatically
combine the hierarchical elements of a design. Different
hierarchical elements can be specified with diff erent design
entry tools, allowing the use of the most convenient entry
method for each portion of the design. In this type of ‘mix ed-
mode’ design entry, designers can intermix schematic, te xt,
gate-level and behavioral-level design, permitting the re-
use of previously designed modules and easing the transi-
tion to higher-level design methodologies.
Design Implementation
After the design is entered, implementation tools map the
logic into the resources of the target device architecture,
determine an optimal placement of the logic, and select the
routing channels that connect the logic and I/O blocks. Xil-
inx design implementation tools apply a very high degree of
automation to these tasks. A design compilation utility auto-
matically retrieves the design’s input files and performs all
the necessary steps to create the CPLD or FPGA configu-
ration program.
For demanding applications, the user can exercise various
degrees of control over the automated implementation pro-
cess using auto-interactive tools and techniques. Option-
ally, user-designated partitioning, placement, and routing
information can be specified as part of the design entry pro-
cess (typically, right on the schematic). The implementation
of highly structured designs can greatly benefit from the
basic floorplanning techniques familiar to designers of
large gate arrays.
For Xilinx FPGAs, the automatic tools are complemented
by an interactiv e , graphics-based editor that allows users to
view and manipulate a model of the logic and routing
resources inside the FPGA device, providing the user with
visibility into the implementation of the design.
Design Verification
Verification of FPGA/CPLD designs typically involves a
combination of in-circuit testing, simulation, and static tim-
ing analysis. The user-programmable nature of these
devices allows designs to be tested immediately in the tar-
get application. For Xilinx FPGAs and in-system-program-
mable CPLDs, download cables are provided that allow for
the direct downloading of a bitstream from a PC or worksta-
tion to an FPGA or CPLD device on a target board. Demon-
stration/prototyping boards are also available. The
implementation tools include back-annotation to provide
post-layout timing of implemented designs to support tim-
ing simulation. A static timing analyzer can be used to
examine a design’s logic and timing to calculate the perfor-
mance along signal paths, identify possib le race conditions,
and detect set-up and hold-time violations. Timing analyz-
ers do not require the user to generate input stimulus pat-
terns or test vectors.
Xilinx software is available both in bundled packages con-
taining front end implementation tools and with integrated
kits to enable plug and play with 3rd party EDA environ-
ments. New enhancements are constantly being devel-
oped, and update services are available to ensure timely
access to the latest versions.
Design Entry
Design Implementation
FPGA CPLD
Timing Simulation
(Back-annotation)
Functional Simulation
Design V erification
Schematic Entry
Text-based Entry
Partition,
Place & Route Partition,
Map & Interconnect
Simulation
In-circuit V erification
Static Timing Analysis
X4351
Figure 2: FPGA/CPLD Design Flow
Development Systems Products Overview
2-4 June 1, 1996 (Version 1.0)
Xilinx Software on CD-ROM
Xilinx software and updates are now deliv ered on CD-R OM
for the PC and workstations (Sun, HP700 and RS6000
Series). Here are some of the benefits:
• F aster Installation: No more wasted time, f eeding flopp y
after floppy into the PC . No more waiting for workstation
tapes to spin, looking for the proper data. Installing or
updating Xilinx software is as easy as popping in one
CD-ROM disk.
• Software Compatibility: New install utilities monitor the
software configuration, ensure executable version
compatibility, and update only the necessary files to
keep the software up-to-date. Archiving old versions of
XACT softw are is as easy as storing one CD-R OM disk.
• On-line documentation, tutorials, application notes, and
product demonstrations.
Macro 
&
MSI
Libraries
State
Machine
Entry
XNF Netlist
Bit Stream Compiler
MakeBits & MakePROM
In-Circuit Design
Verification
Xilinx
Serial PROMs
Serial Configuration
PROM Programmer
Logic
Cell
Array
(FPGA)
Gate Level
Simulation
Interactive
Design Editor
Mapping into Blocks
Place & Route
Design
Implementation
Design
Verification
Logic & Timing
Simulation
Logic
Synthesis
DS-502
Design
Entry
Xilinx Logic Library & XNF Interface
X-BLOX (if present)
File Merging
Logic Reduction
Design Rule Check
Step 1
Step 2
Step 3
X5978
OrCAD
Viewlogic
Alliance Partner
HDL/VHDL
Mentor V8.x
Synopsys I/F
Xilinx
ABEL
LCA Netlist
LCA Netlist with
Block and Net Timing Timing Annotated
XNF Netlist
Figure 3: Detailed FPGA Design Flow
June 1, 1996 (Version 1.0) 2-5
Support and Update Services
Software Updates
A major focus of Xilinx engineering is continual improve-
ment of the Xact
step
Development System Software. This
is accomplished by developing new features to improve
your design productivity, and adding new technologies to
give you access to the latest Xilinx products. If you are on
maintenance, you will receive new revisions containing
enhancements to the software products you have licensed
from Xilinx.
Base Product Updates
The Xact
step
Base packages do not come with a standard
one-year update contract. When Xilinx releases a new ver-
sion of software, customers will be notified and may pur-
chase the new version update at the listed price.
Online Documentation
Xilinx continually updates documentation to reflect
changes to the Development System Software. As par t of
the update service, you receive new online documentation
with each update.
Macro 
&
MSI
Libraries
OrCAD
Viewlogic
Alliance Partner
Mentor V8.x
Logic Optimization
File Merging
Logic Reduction
Design Rule Checking
XNF NetlistPLUSASM
Device Fitting
Programming
Generation
Report
Generation
Timing
Netlist
Generation
Design
Reports
Device
Programming
File
Timing
Annotated
XNF Netlist
Device
Programming
HW-130
Gate Level Simulation
Logic & Timing
Xilinx
ABEL
Data I/O ABEL 6
Logical Devices-CUPL
Xilinx Logic Library & XNF Interface
DS-560
X5979
Design
Implementation
Design
Verification
Design
Entry
Step 1
Step 2
Step 3
Figure 4: Detailed CPLD Design Flow
Development Systems Products Overview
2-6 June 1, 1996 (Version 1.0)
Technical Support Hotline
The Technical Telephone Support Hotline provides you with
toll-free telephone access to trained software technical
support engineers. (See Chapter 13.) Expertise provided
includes most major third-party interfaces including View-
logic, OrCAD, Mentor Graphics, Xilinx ABEL, Synopsys,
and Cadence. Additionally, Xilinx core expertise is a vailab le
for both FPGA and CPLD product lines covering place and
route, X-BLOX, XACT Performance, XDelay, configuration
and component issues.
This support service for problem resolution assistance is
available between 8:00 am and 5:00 pm Pacific Standard
Time, Monday through Friday (except holidays).
For service outside USA, please contact your local repre-
sentative.
Xilinx Technical Bulletin Board
The Xilinx Technical Bulletin Board allows electronic
exchange of infor mation with technical support engineers.
With this service you can upload your design data making it
available to support engineers during problem resolution.
You can use the Technical Bulletin Board download capabil-
ity to obtain various software utilities, the latest released
revisions of speed and package files, detailed solutions for
commonly encountered problems, and marketing updates.
The Technical Bulletin Board number is 1-408-559-9327
and it is available 24 hours a day, 7 days a week.
Customer Support FAX
The technical support engineers can be reached directly
via facsimile by using the “Technical Support only” fax line.
This service is available to supply information to the sup-
port engineers to resolv e a specific inquiry. Additionally, this
service may be used in lieu of, or together with, the Techni-
cal Support Hotline. The fax number is 1-408-879-4442.
Internet Electronic Mail Support
Another alternative for technical support is via the Inter net
E-Mail address, hotline@xilinx.com. As with the other pre-
viously described methods, electronic mail allows full
access to Xilinx Technical Support engineers.
Software Series Overview
The Xilinx Xact
step
Software Series provides powerful,
easy to use design tools for FPGA and CPLD devices.
Three different series with se ver al choices of configurations
lets designers choose the exact system for their needs.
• Foundation Series — Complete shrink-wrapped design
solutions
• Alliance Series — Powerful systems that integrate into
existing EDA environments
• SLI Series — Value added options that enable system
level integration.
• XC8000 Series — Specifically designed for the XC8100
FPGA sea-of-gates architecture and ASIC design flow
The Foundation Series provides entry-level designers with
a complete solution in a shrink-wrapped, easy-to-use envi-
ronment. This fully integrated set of tools, which is perfect
for users that are ne w to PLD design, includes design entry
simulation, VHDL synthesis, and design implementation
tools.
The Xilinx Alliance Series is for designers who want to inte-
grate into their existing EDA tool environment. It supports
the complete spectrum of design techniques with interfaces
to over 45 EDA vendors and 80 different design tools.
Optional Viewlogic front-end products are part of the Alli-
ance Series. This is ideal for users who want a complete
system that is extensib le to board and system le v el design.
The Foundation and Alliance Series support the industr y's
broadest array of PLD solutions including the XC2000,
XC3000A, XC3100A, XC4000/E, XC5000, XC7300 and
XC9500 families . This giv es designers technology indepen-
dence by letting them choose target devices late in the
design cycle.
Both series include the powerful XA CT
step
implementation
system containing the popular Design Manager, Flow
Engine, PROM File Formatter, Floorplanner and Hardware
Debugger.
The XC8000 Series is a standalone software package that
is specifically designed for the sea-of-gates architecture. It
features ASIC-lik e design flows and interf aces to many syn-
thesis and schematic tools.
All products in the Xilinx XACT
step
Series use standards-
based design techniques that maximize design portability
and reuse. EDA design tools that support EDIF, ABEL, Ver-
ilog, VHDL and LPM formats interface easily into the Xilinx
design environment.
PLD designs can use integrated ABEL design and synthe-
sis or interfaces to any of the leading PLD design tools
environments. Schematic designs can use the integrated
capture tool in the Foundation Series or choose interfaces
to any leading EDA environment. HDL designs enjoy stan-
dards-based design using integrated VHDL synthesis in the
Foundation Series or interfaces to any leading VHDL or
Verilog synthesis tool.
This flexibility protects the user's in v estment in design tools
and training and makes it easy to re-use designs even
when EDA systems change.
Foundation Series
The Foundation Series provides everything required to
design a programmable logic device in an easy-to-use,
fully-integrated environment. This fully integrated solution
makes PLD design easy by providing push button design
June 1, 1996 (Version 1.0) 2-7
flows, on-line training and the XACT
step
windows-based
graphical user interface.
This series features broad support for standards based
HDL design. All configurations interface with the popular
ABEL language and fitters optimized for each target archi-
tecture. VHDL configurations include integrated VHDL syn-
thesis with tutorials and wizards to turn new users into
experts quickly and easily.
Easy to Learn and Use
The Foundation Series is a fully integr ated tool set allowing
users to access design entry, implementation and verifica-
tion tools from a single graphical user interface. Ever y step
in the design process is accomplished using graphical tool
bars, icons and pop-up menus supported by interactive
tutorials and comprehensive on-line help.
VHDL Synthesis
VHDL configurations of the F oundation Series contain inte-
grated VHDL synthesis and wizards with the following fea-
tures.
• On-line tutorial teaches the art of VHDL design.
• Intelligent HDL editor with color coding, syntax checking
and single click error navigation makes it easy to read
and debug VHDL designs.
• HDL Language Assistant provides libraries of common
functions with optimized VHDL code.
• FPGA specific synthesis tools produce high-density,
high-performance results.
ABEL-HDL Synthesis
ABEL configurations of the Foundation Series contain
integrated synthesis and wizards with the following fea-
tures.
• Intelligent HDL editor with color coding, syntax checking
and single click error navigation makes it easy to read
and debug ABEL designs.
• HDL Language Assistant provides libraries of common
functions with optimized ABEL code.
• FPGA/CPLD specific synthesis tools produce high-
density, high-performance results.
Alliance Series
The Alliance Series is for users who want powerful design
tools that integrate into their existing EDA environment.
With this series, designers can choose from a wide range
of design techniques including schematic capture, module-
based design and HDL from over 45 EDA vendors. With
standards based design interfaces including EDIF, ABEL,
Verilog and VHDL, this series provides maximum flexibility,
portability and design reuse.
Advanced integration with Cadence, Mentor, OrCAD, Syn-
opsys and Viewlogic provide tightly-coupled environments
that make it easy to move through the design process.
Other EDA vendors are supported through the Xilinx Alli-
ance Program, insuring high quality tools and accurate
results. Information on these vendors can be found on the
Xilinx Alliance CD or through WebLINX on the world wide
web at www.xilinx.com.
The Alliance Series includes the complete XACT
step
implementation tool set suppor ting the complete spectrum
of design methodologies from fully-automatic to hand-
crafted.
Viewlogic Standalone products are part of the Alliance
Series and are for those users who want the integ ration of a
complete solution with the power to access board and sys-
tem level design tools. These products include Viewlogic
Workvie w Office schematic capture, simulation and synthe-
sis tools.
Configurations
The Xilinx Software Series are availab le in 3 configurations
giving designers a cost effective way to match their tools to
the gate densities they require.
CPLD configurations provide support for Xilinx’s XC9500
and XC7300 CPLD families.
Base configurations provides push-b utton design flows and
support designs up to 5,000 gates.
Standard configurations combine push-button flows with
powerful auto-interactive tools. These tools give designers
more influence and control over implementation while
maintaining the benefits of design automation. Standard
configurations support designs up to 20,000 gates.
Optional LogiCores give designers access to large fully v er-
ified functions that simplify design entry and provide dra-
matic savings in engineering resources. The initial
LogiCore product set includes a complete PCI interface
module.
Migration Paths
All tools in the Xilinx XACT
step
Series use standards-
based design to protect the user's investment as design
requirements change.
For example, designers can use Foundation products to
learn ABEL or VHDL and produce code optimized for
device resources . If future requirements f orce the use of dif-
ferent design tools , users can upgr ade to the Xilinx Alliance
Series and reuse their code while gaining access to power-
ful system-level tools.
The Foundation and Alliance Series use the same core
implementation tools eliminating the need to re-learn the
design process after an upgrade.
Unified libraries and standard design file formats allow
schematic designers to enjoy the same migration capabili-
ties.
Development Systems Products Overview
2-8 June 1, 1996 (Version 1.0)
Series 8000
XC8100 FPGAs use a stand-alone software package spe-
cifically designed for the sea-of-gates architecture and
ASIC-like design flow. This package, called Series 8000, is
both simple to use and powerful with features including
incremental design, hierarchical netlist/naming, floorplan-
ning, scripting and on-line help.
The XC8100 family is architected from the ground up to be
efficient with synthesis by providing predictable pre-layout
timing, accurate backannotation and 1-1 mapping of netlist
to logic.
Although this series is designed specifically for the
XC8100, it shares common design entry methodologies
with the Foundation and Alliance series. Schematic librar-
ies use the same symbol names and sizes and HDL code is
portable between the systems. This lets designers easily
retarget designs from one family to another.
The Series 8000 includes CAE libraries and interfaces,
place and route software and programming software for all
devices in the XC8100 family.
Individual Products
Libraries and Interface – Contains schematic symbols or
HDL libraries, simulation models with timing information,
and translators to the XNF file format.
Core Implementation – Provides the software necessary
to process an XNF file into a file which can be used to pro-
gram a Xilinx FPGA or CPLD de vice. Includes tools f or logic
reduction, design rule checking, mapping, automatic place-
ment and routing, bitstream generation and PROM file gen-
eration.
X-BLOX Module Generator & Optimizer – Allows design
entry as block diagrams using a familiar schematic editor.
Using built-in expert knowledge, X-BLOX software auto-
matically optimizes y our design to take full adv antage of the
unique features of the XC3000A, XC3100A, XC4000, and
XC5000 FPGA families.
Xilinx ABEL – Supports CPLD and FPGA text-based
design entry and netlist translation using ABEL high level
description language. ABEL supports different design
styles including Boolean equations, truth tables and
encoded or symbolic state machines.
XChecker™ Cable – Supports downloading of bitstream
and PROM files, and readback of configuration data and
internal node values. This cable uses the serial port of IBM
PCs & compatibles and supported workstations.
FPGA Demoboard – Provides demonstration or prototype
capability for XC2000, XC3000, XC3000A, XC3100,
XC3100A devices in 68-pin PLCC packages, and XC4000
family devices in 84-pin PLCC. This board is designed to
offer flexibility for learning and prototyping.
June 1, 1996 (Version 1.0) 2-9
Order Codes
Order codes for Development Systems products consist of
a multiple-field part number. The first field indicates the
product category. Additional fields indicate the third-party
CAE vendor for interface tools, the package name or indi-
vidual product number and the platform.
For example, the following order code indicates the cate-
gory as Development System, the interface CAE vendor as
Viewlogic, the package as Standard, the platform as IBM
PC or compatible, and the media as CD-ROM.
DS-VL-STD-PC1-C
The follo wing tab le shows v alid product category, CAE ven-
dor, package type, platform and media type codes.
Product Category Code
Development System DS
Support and Updates SC
Base Update BU
Re-instate Updates SR
Product Upgrade DX
Hardware HW
Training Course TC
Interface V endor Code
OrCAD OR
Viewlogic VL
Viewlogic
Stand-alone
VLS
Mentor, version 8 MN8
Synopsys SY
Cadence CDN
Foundation FND
Package T ype Code
Base System BAS
Standard System STD
Extended System EXT
Advanced System ADV
Platform Code
IBM PC compatible PC1
Sun-4 SN2
HP700 HP7
IBM RS6000 RS6
Media Type Code
CD-ROM C
Development Systems Products Overview
2-10 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 2-11
This section describes the following products:
Foundation Series
• Foundation Base System (PC)
• Foundation Base System with VHDL Synthesis (PC)
• Foundation Standard System (PC)
• Foundation Standard System with VHDL Synthesis (PC)
Alliance Series
• OrCAD – Base System (PC)
• OrCAD – Standard System (PC)
• Viewlogic – Base System (PC)
• Viewlogic – Standard System (PC)
• Viewlogic Stand-alone – Base System (PC)
• Viewlogic Stand-alone – Standard System (PC)
• Viewlogic Stand-alone – Extended System (PC)
• Viewlogic – Standard System (Workstation)
• Mentor – Standard System (Workstation)
• Synopsys – Standard System (Workstation)
• Cadence Standard System (Workstation)
• Third-Party Alliance – Standard System (PC and Workstation)
Development Systems:
Bundled Packages Product
Descriptions
June 1, 1996 (Version 1.0)
Development Systems: Bundled Packages Product Descriptions
2-12 June 1, 1996 (Version 1.0)
Foundation Series: Foundation Base System (PC)
Base System Includes:
• Schematic editor with library support for XC2000,
XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and
XC7300 and XC9500 CPLDs
• Functional and Timing Simulator
• Core implementation software for FPGAs with device
support for XC2000, XC3000/A & XC3100/A up to
XC3x42/A, XC4000/E up to XC4003/E, and XC5200 up
to XC5204
• Core implementation software for CPLDs with device
support for XC7300 and XC9500
• XChecker Diagnostic Cable
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx bulletin board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
Required Hardware Environment:
• Fully compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 70 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel and two serial ports
• 16 MB of RAM
Package Features - Foundation Base (PC)
Notes: 1. XC2000, XC3000, up to XC3042/XC3142;
XC4000/E up to XC4003/E; XC5200 up to XC5204
2. XDE Design Editor and Floorplanner not included
Feature FND
Base FND
Std. FND
BaseV FND
Std. V
Libraries and Interface √√√√
Schematic Editor √√√√
Simulator (Unlimited) √√√√
CPLD Devices √√√√
FPGA Limited1√√
FPGA 2K, 3K, 4K, 5K √√
Core Implementation √2√√
2√
Synthesis Tools √√
X-BLOX √√
XChecker Cable √√√√
Hotline Support √√√√
June 1, 1996 (Version 1.0) 2-13
Foundation Series: Foundation Base System with VHDL Synthesis (PC)
Base System Includes:
• Schematic editor with library support for XC2000,
XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and
XC7300 and XC9500 CPLDs
• Functional and Timing Simulator
• VHDL Synthesis capability with HDL
• Wizard that makes HDL design entry easier and faster
with Xilinx specific templates
• VHDL multimedia tutorial
• Core implementation software for FPGAs with device
support for XC2000, XC3000/A & XC3100/A up to
XC3x42/A, XC4000/E up to XC4003/E, and XC5200 up
to XC5204
• Core implementation software for CPLDs with device
support for XC7300 and XC9500
• XChecker Diagnostic Cable
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx bulletin board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
Required Hardware Environment:
• Fully compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 70 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel and two serial ports
• 16 MB of RAM
Package Features - Foundation (PC)
Notes: 1. XC2000, XC3000, up to XC3042/XC3142;
XC4000/E up to XC4003/E; XC5200 up to XC5204
2. XDE Design Editor and Floorplanner not included
Feature FND
Base FND
Std. FND
BaseV FND
Std. V
Libraries and Interface √√√√
Schematic Editor √√√√
Simulator (Unlimited) √√√√
CPLD Devices √√√√
FPGA Limited1√ √
FPGA 2K, 3K, 4K, 5K √√
Core Implementation √2√ √2√
Synthesis Tools √√
X-BLOX √√
XChecker Cable √√√√
Hotline Support √√√√
Development Systems: Bundled Packages Product Descriptions
2-14 June 1, 1996 (Version 1.0)
Foundation Series: Foundation Standard System (PC)
Standard System Includes:
• Schematic editor with library support for XC2000,
XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and
XC7300 and XC9500 CPLDs
• Functional and Timing Simulator (unlimited gates)
• Core implementation software for FPGAs with device
support f or XC2000, XC3000/A & XC3100/A, XC4000/E
and XC5200
• Core implementation software for CPLDs with device
support for XC7300 and XC9500
• XChecker Diagnostic Cable
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx bulletin board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
Required Hardware Environment:
• Fully compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 70 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel and two serial ports
• 16 MB of RAM
Package Features - Foundation (PC)
Feature FND
Base FND
Std. FND
BaseV FND
Std. V
Libraries and Interface √√√√
Schematic Editor √√√√
Simulator (Unlimited) √√√√
CPLD Devices √√√√
FPGA Limited √√
FPGA 2K, 3K, 4K, 5K √√
Core Implementation √√√√
Synthesis Tools √√
X-BLOX √√
XChecker Cable √√√√
Hotline Support √√√√
June 1, 1996 (Version 1.0) 2-15
Foundation Series: Foundation Standard System with VHDL (PC)
Standard System Includes:
• Schematic editor with library support for XC2000,
XC3000/A, XC3100/A, XC4000/E, XC5200 FPGAs and
XC7300 and XC9500 CPLDs
• Functional and Timing Simulator (unlimited gates)
• VHDL Syntheses capability with HDL Wizard that
makes HDL design entry easier and faster with Xilinx
specific templates
• VHDL multimedia tutorial
• Core implementation software for FPGAs with device
support f or XC2000, XC3000/A & XC3100/A, XC4000/E
and XC5200
• Core implementation software for CPLDs with device
support for XC7300 and XC9500
• XChecker Diagnostic Cable
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx bulletin board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
Required Hardware Environment:
• Fully compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 70 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel and two serial ports
• 16 MB of RAM
Package Features - Foundation (PC)
Feature FND
Base FND
Std. FND
BaseV FND
Std. V
Libraries and Interface √√√√
Schematic Editor √√√√
Simulator (Unlimited) √√√√
CPLD Devices √√√√
FPGA Limited √√
FPGA 2K, 3K, 4K, 5K √ √
Core Implementation √√√√
Synthesis Tools √√
X-BLOX √√
XChecker Cable √√
Hotline Support √√√√
Development Systems: Bundled Packages Product Descriptions
2-16 June 1, 1996 (Version 1.0)
Alliance Series: OrCAD – Base System (PC)
Base System Includes:
• Schematic Interface for OrCAD SDT386+ with library
support for XC2000, XC3000, XC3000A, XC3100,
XC3100A, XC4000/E and XC5200 FPGAs and XC7000
and XC9500 Series CPLDs
• Functional and Timing Simulation Interface for OrCAD
VST386+
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A
and XC3100, XC3100A up to XC3x42, XC3x42A,
XC4000/E up to XC4003/E, XC5200 up to XC5204,
XC7300, and XC9500
Note:
• This package does not include the OrCAD SDT
schematic capture or VST simulation tools. They must
be purchased separately from OrCAD.
• XDE-Xilinx Design Editor is not included.
• This Base P ackage does not come with a standard one
year update contract. Instead, when Xilinx releases a
new version of software, customers will be notified and
may purchase the Base Update at the listed price.
• The Base Update is only available to licensees of the
DS-OR-BAS-PC1 on a one-for-one basis.
Revision Updates Include:
• Latest version software and online documentation
• Only available to customers who have purchased a
Base product before.
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 60 Mbyte hard-disk space
• One 3.5" High-Density floppy disk drive
• VGA display
• One parallel and two serial ports
• 16 Mbytes of RAM for all supported XC3000A and
XC4000/E FPGAs
• Mouse
Package Features - OrCAD PC
Notes: 1. XC2000, XC3000, up to XC3042/XC3142;
XC4000/E up to XC4003/E; XC5200 up to XC5204
2. XDE Design Editor and Floorplanner not included
Feature Base Std.
Libraries and Interface √√
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √√
FPGA Limited1√
FPGA 2K, 3K, 4K, 5K √
Core Implementation √2√
Synthesis Tools
X-BLOX √
XChecker Cable √√
Hotline Support √√
June 1, 1996 (Version 1.0) 2-17
Alliance Series: OrCAD – Standard System (PC)
Standard System Includes:
• Schematic Interface for OrCAD SDT386+ with library
support for XC2000, XC3000, XC3000A, XC3100,
XC3100A, XC4000/E FPGAs and XC7000 and XC9500
Series CPLDs
• Functional and Timing Simulation Interface for OrCAD
VST386+
• X-BLOX Module Generator and Optimizer
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A, XC4000/E, XC5200, XC7300, and
XC9500
• Software Support and Updates for first year
Note:
• This package does not include the OrCAD SDT
schematic capture or VST simulation tools. They must
be purchased separately from OrCAD.
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 80 Mbyte hard-disk space
• One ISO 9660 compatible CD-ROM drive
• VGA display
• One parallel and two serial ports
• 16 Mbytes of RAM up to XC4008
• 24 Mbytes of RAM for XC3195, XC3195A, XC4010
• 32 Mbytes of RAM for XC4013
• Mouse
Package Features - OrCAD PC
Feature Base Std.
Libraries and Interface √ √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √ √
FPGA Limited √
FPGA 2K, 3K, 4K, 5K √
Core Implementation √√
Synthesis Tools
X-BLOX √
XChecker Cable √√
Hotline Support √√
Development Systems: Bundled Packages Product Descriptions
2-18 June 1, 1996 (Version 1.0)
Alliance Series: Viewlogic – Base System (PC)
Base System Includes:
• Viewlogic Schematic Interface library support for
XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs, and XC7000 and XC9500
CPLDs
• Viewlogic Functional and Timing Simulation Interface
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A up to XC3x42/A, XC4000/E up to
XC4003/E, XC5200 up to XC5204, XC7300, and
XC9500
Note:
• This package does not include Viewlogic schematic
capture or simulation tools. They must be purchased
separately from Viewlogic or Xilinx (see Stand-alone
packages).
• Interface and libraries support Workview 6.1, Workview
PRO and Office Series.
• XDE-Xilinx Design Editor - not included
• This Base P ac kage does not come with a standard one-
year update contract. Instead, when Xilinx releases a
new version of software, customers will be notified and
may purchase the Base Update at the listed price.
• The Base Update is only available to licensees of the
DS-VL-BAS-PC1 on a one-for-one basis.
Revision Updates Include:
• Latest version software and online documentation
• Only available to customers who have purchased a
base product before.
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows version 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 60 Mbytes disk space
• One CD-ROM drive
• VGA display
• 3-Button Serial Mouse
• One parallel and two serial ports
• 16 Mbytes of RAM
Package Features - Viewlogic PC
1. XC2000, XC3000, up to XC3042/XC3142;
XC4000/E up to XC4003/E; XC5200 up to XC5204
2. XDE Design Editor and Floorplanner not included
Feature VL
Base VL
Std. VLS
Base VLS
Std. VLS
Ext.
Libraries and Interface √√√√√
Schematic Editor √√√
Simulator (Limited) √
Simulator (Unlimited) √√
EPLD Devices √√√√√
FPGA Limited1√√
FPGA 2K, 3K, 4K, 5K √√√
Core Implementation √2√√
2√√
Synthesis Tools √
X-BLOX √√√
XChecker Cable √√√√√
Hotline Support √√√√√
June 1, 1996 (Version 1.0) 2-19
Alliance Series: Viewlogic – Standard System (PC)
Standard System Includes:
• Viewlogic Schematic Interface with library support for
XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs and XC7000 and XC9500
CPLDs
• Viewlogic Functional and Timing Simulation Interface
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A, XC4000/E, XC5200, XC7300, and
XC9500
• X-BLOX Module Generator and Optimizer
• Software Support and Updates for the first year
Note:
• This package does not include Viewlogic schematic
capture or simulation tools. They must be purchased
separately from Viewlogic or Xilinx (see Stand-alone
packages).
• Interface and libraries support Workview PRO and
Office Series.
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 90 Mbytes hard-disk space
• One ISO 9660 compatible CD-ROM drive
• VGA display
• 3-Button Serial Mouse
• One parallel and two serial ports
• 16 Mbytes of RAM for devices up to XC4008
• 24 Mbytes of RAM for XC3195, XC4010
• 32 Mbytes of RAM for XC4013
Package Features - Viewlogic PC
Feature VL
Base VL
Std. VLS
Base VLS
Std. VLS
Ext.
Libraries and Interface √√√√√
Schematic Editor √√√
Simulator (Limited) √
Simulator (Unlimited) √√
EPLD Devices √√√√√
FPGA Limited √√
FPGA 2K, 3K, 4K, 5K √√√
Core Implementation √√√√√
Synthesis Tools √
X-BLOX √√√
XChecker Cable √√√√√
Hotline Support √√√√√
Development Systems: Bundled Packages Product Descriptions
2-20 June 1, 1996 (Version 1.0)
Alliance Series: Viewlogic
Stand-alone
– Base System (PC)
Stand-alone
Standard System Includes:
• Workview Office Schematic Editor with library support
for XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs and XC7000 and XC9500
CPLDs
• Workview Office Functional and Timing Simulation for
designs (limited gates)
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A, XC4000/E, XC5200, XC7300, and
XC9500
Note:
• XDE-Xilinx Design Editor - not included
• This Base P ac kage does not come with a standard one-
year update contract. Instead, when Xilinx releases a
new version of software, customers will be notified and
may purchase the Base Update at the listed price.
• The Base Update is only available to licensees on a
one-for-one basis.
Revision Updates Include:
• Latest version software and online documentation
• Only available to customers who have purchased a
base product before.
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows version 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 60 Mbytes disk space
• One CD-ROM drive
• VGA display
• 3-Button Serial Mouse
• One parallel and two serial ports
• 16 Mbytes of RAM
Package Features - Viewlogic PC
Notes: VL = Viewlogic, VLS = Viewlogic
Stand-alone
1. XC2000, XC3000, up to XC3042/XC3142;
XC4000/E up to XC4003/E; XC5200 up to XC5204
2. XDE Design Editor and Floorplanner not included
Feature VL
Base VL
Std. VLS
Base VLS
Std. VLS
Ext.
Libraries and Interface √√√√√
Schematic Editor √√√
Simulator (Limited) √
Simulator (Unlimited) √√
EPLD Devices √√√√√
FPGA Limited1√ √
FPGA 2K, 3K, 4K, 5K √√√
Core Implementation √2√ √2√√
Synthesis Tools √
X-BLOX √√√
XChecker Cable √√√√√
Hotline Support √√√√√
June 1, 1996 (Version 1.0) 2-21
Alliance Series: Viewlogic
Stand-alone
– Standard System (PC)
Stand-alone
Standard System Includes:
• Workview Office Schematic editor with library support
for XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs and XC7000 and XC9500
CPLDs
• Workview Office Functional and Timing Simulation for
designs (unlimited gates)
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A, XC4000/E, XC5200, XC7300, and
XC9500
• X-BLOX Module Generator and Optimizer
• Software Support and Updates for the first year
Support and Updates Include:
• Hotline Telephone support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 90 Mbytes hard-disk space
• One ISO 9660 compatible CD-ROM drive
• VGA display
• 3-Button SP Mouse
• One parallel and two serial ports
• 16 Mbytes of RAM for devices up to XC4008
• 24 Mbytes of RAM for XC3195, XC4010
• 32 Mbytes of RAM for XC4013
Package Features - Viewlogic PC
Feature VL
Base VL
Std. VLS
Base VLS
Std. VLS
Ext.
Libraries and Interface √√√√√
Schematic Editor √√√
Simulator (Limited) √
Simulator (Unlimited) √√
EPLD Devices √√√√√
FPGA Limited √√
FPGA 2K, 3K, 4K, 5K √√√
Core Implementation √√√√√
Synthesis Tools √
X-BLOX √√√
XChecker Cable √√√√√
Hotline Support √√√√√
Development Systems: Bundled Packages Product Descriptions
2-22 June 1, 1996 (Version 1.0)
Alliance Series: Viewlogic
Stand-alone
– Extended System (PC)
Extended
Stand-alone
System Includes:
• Workview Office Schematic editor with library support
for XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs and XC7000 and XC9500
CPLDs
• Workview Office Functional, Timing, and VHDL
Simulation (unlimited gates)
• ViewSynthesis – VHDL synthesis with X-BLOX
integration and library synthesis support for XC2000,
XC3000, XC3000A, XC3100, XC3100A, XC4000/E and
XC5200 FPGAs
• X-BLOX Module Generator and Optimizer
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000/ XC3100,
XC4000/E, XC5200, XC7300, and XC9500
• Software Support and Updates if on maintenance
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• Fully IBM compatible PC386/486/Pentium
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 90 Mbytes hard-disk space
• One ISO 9660 compatible CD-ROM drive
• VGA display
• 3-Button Serial Mouse
• One parallel and two serial ports
• 16 Mbytes of RAM for devices up to XC4008
• 24 Mbytes of RAM for XC3195, XC4010
• 32 Mbytes of RAM for XC4013
Package Features - Viewlogic PC
Feature VL
Base VL
Std. VLS
Base VLS
Std. VLS
Ext.
Libraries and Interface √√√√√
Schematic Editor √√√
Simulator (Limited) √
Simulator (Unlimited) √ √
EPLD Devices √√√√√
FPGA Limited √√
FPGA 2K, 3K, 4K, 5K √√√
Core Implementation √√√√√
Synthesis Tools √
X-BLOX √√
√
XChecker Cable √√√√√
Hotline Support √√√√√
June 1, 1996 (Version 1.0) 2-23
Alliance Series: Viewlogic – Standard System (Workstation)
Standard System Includes:
• Schematic Interface for Draw with library support for
XC2000, XC3000, XC3000A, XC3100, XC3100A,
XC4000/E, XC5200 FPGAs and XC7000 and XC9500
CPLDs
• Functional and Timing Simulation Interface for ViewSim
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000, XC3000A,
XC3100, XC3100A, XC4000/E, XC5200, XC7300, and
XC9500
• X-BLOX Module Generator and Optimizer
• Software Support and Updates if on maintenance
Note:
• This package does not include schematic capture or
simulation tools. They must be purchased separately.
• Interface supports Workview Office and PRO Series
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• 50 to 200 MB hard disk space allocated Xilinx designs.
• 32 MB of RAM (minimum)
• Color Monitor
• Swap Space: 140 MB (minimum)
• TCP/IP Software
• CD ROM Drive
Sun-4 Sparcstation Series
• Sun OS 4.1.X
• X-Windows (R3 or R4)
• Open Windows or Motif
HP700 Series
• HPUX 9.0/9.1
• X-Windows (R5)
• HP_VUE 3.0
Recommended Hardware Environment:
• Additional RAM to increase performance
Package Features - Viewlogic W/S
Feature Std.
Libraries and Interface √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √
FPGA Limited
FPGA 2K, 3K, 4K, 5K √
Core Implementation √
Synthesis Tools
X-BLOX √
XChecker Cable √
Hotline Support √
Development Systems: Bundled Packages Product Descriptions
2-24 June 1, 1996 (Version 1.0)
Alliance Series: Mentor V8 – Standard System (Workstation)
Standard System Includes:
• Mentor V8 Interf ace (Mentor Design Architect/QuickSim
II Libraries and Interface)
• Core Implementation Software for XC2000, XC3000,
XC3000A, XC3100, XC3100A, XC4000/E, XC5200
FPGAs and XC7300 and XC9500 CPLDs
• X-BLOX Module Generator and Optimizer
• Software Support and Updates if on maintenance
Note:
• This package does not include Design Architect
schematic capture, or QuickSim II simulation tools.
Contact your local Mentor Graphics sales office to
purchase these tools.
• AutoLogic synthesis prog ram, libraries and interface are
available from Mentor Graphics.
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• 50 to 200 MB hard disk space allocated Xilinx designs.
• 32 MB of RAM (minimum)
• Color Monitor
• Swap Space: 140 MB (minimum)
• TCP/IP Software
• CD ROM Drive
Sun-4 Sparcstation Series
• Sun OS 4.1.X
• X-Windows (R3 or R4)
• Open Windows or Motif
HP700 Series
• HPUX 9.0/9.1
• X-Windows (R5)
• HP_VUE 3.0
Recommended Hardware Environment:
• Additional RAM to increase performance
Package Features - Mentor W/S
Feature Std.
Libraries and Interface √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √
FPGA Limited
FPGA 2K, 3K, 4K, 5K √
Core Implementation √
Synthesis Tools
X-BLOX √
XChecker Cable √
Hotline Support √
June 1, 1996 (Version 1.0) 2-25
Alliance Series: Synopsys – Standard System (Workstation)
Standard System Includes:
• XC3000, XC3000A, XC3100, XC3100A, XC4000/E and
XC5200 synthesis library
• Core Implementation Software for XC2000, XC3000,
XC3000A, XC3100, XC3100A, XC4000/E, XC5200
FPGAs, and XC7300 and XC9500 CPLDs
• X-BLOX Module Generator and Optimizer
• Works with Synopsys Design Compiler and FPGA
Compiler
• Translator from Synopsys to Xilinx XNF
• Software Support and Updates if on maintenance
Note:
• This package does not include Synopsys Design
Compiler or FPGA Compiler. These m ust be purchased
separately from Synopsys.
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• 50 to 200 MB hard disk space allocated Xilinx designs.
• 32 MB of RAM (minimum)
• Color Monitor
• Swap Space: 140 MB (minimum)
• TCP/IP Software
• CD ROM Drive
Sun-4 Sparcstation Series
• Sun OS 4.1.X
• X-Windows (R3 or R4)
• Open Windows or Motif
HP700 Series
• HPUX 9.0/9.1
• X-Windows (R5)
• HP_VUE 3.0
Recommended Hardware Environment:
• Additional RAM to increase performance
Package Features - Synopsys W/S
Feature Std.
Libraries and Interface √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √
FPGA Limited
FPGA 2K, 3K, 4K, 5K √
Core Implementation √
Synthesis Tools
X-BLOX √
XChecker Cable √
Hotline Support √
Development Systems: Bundled Packages Product Descriptions
2-26 June 1, 1996 (Version 1.0)
Alliance Series: Cadence – Standard System (Workstation)
Standard System Includes:
• Cadence Interface (Composer and Concept Schematic
Libraries and Verilog and RapidSim simulation models
and interfaces)
• Core Implementation Software for XC2000, XC3000/A,
XC3100/A, XC4000/E, XC5200 FPGAs, and XC7300
and XC9500 CPLDs
• LogiBlox Module Generator and Optimizer
• Software Support and Updates if on maintenance
Note:
• This package does not include Composer/Concept
schematic capture, or Verilog/RapidSim simulation
tools. Contact your local Cadence sales office to
purchase these tools
• FPGA designer (Synergy based top-down FPGA
design tool) is available from Cadence.
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment:
• 50 to 200 MB hard disk space allocated Xilinx designs.
• 32 MB of RAM (minimum)
• Color Monitor
• Swap Space: 140 MB (minimum)
• TCP/IP Software
• CD ROM Drive
Sun-4 Sparcstation Series
• Sun OS 4.1.X
• X-Windows (R3 or R4)
• Open Windows or Motif
HP700 Series
• HPUX 9.0/9.1
• X-Windows (R5)
• HP_VUE 3.0
Recommended Hardware Environment:
• Additional RAM to increase performance
Package Features - Synopsys W/S
Feature Std.
Libraries and Interface √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √
FPGA Limited
FPGA 2K, 3K, 4K, 5K √
Core Implementation √
Synthesis Tools
X-BLOX √
XChecker Cable √
Hotline Support √
June 1, 1996 (Version 1.0) 2-27
Alliance Series: Third Party Alliance – Standard System
Standard System Includes:
• X-BLOX Module Generator & Optimizer
• Core Implementation Software for CPLDs and FPGAs
with device support for XC2000, XC3000/A, XC3100/A,
XC4000/E, XC7300, and XC9500
• Software Support and Updates for the first year
Note:
• Purchase schematic and simulation tools and interf aces
and libraries from a Xilinx 3rd-Party Alliance Partner
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Required Hardware Environment (PC):
• Fully compatible PC386/486/Pentium
• MS-DOS version 5.0 (minimum)
• MS-Windows 3.1 (minimum)
• Minimum 80 MB hard disk space
• One ISO 9660-type CD-ROM drive
• VGA display (higher resolutions supported)
• One parallel and two serial ports
• 16 MB of RAM for devices up to XC4008
• 24 MB of RAM for XC3195A, XC4010
• 32 MB of RAM for XC4013
• Mouse
Required Hardware Environment (Workstation):
• 50 to 200 MB hard disk space allocated Xilinx designs.
• 32 MB of RAM (minimum)
• Color Monitor
• Swap Space: 140 MB (minimum)
• TCP/IP Software
• CD-ROM Drive
Sun-4 Sparcstation Series
• Sun OS 4.1.X
• X-Windows (R3 or R4)
• Open Windows or Motif
HP700 Series
• HPUX 9.0/9.1
• X-Windows (R5)
• HP_VUE 3.0
IBM RS6000
• AIX 3.2
• X-Windows Support
Package Features - Third Party Alliance
Feature Std.
Libraries and Interface √
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD Devices √
FPGA Limited1
FPGA 2K, 3K, 4K, 5K √
Core Implementation √
Synthesis Tools
X-BLOX √
XChecker Cable √
Hotline Support √
Development Systems: Bundled Packages Product Descriptions
2-28 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 2-29
This section describes the following products:
• FPGA Core Implementation – DS-502
• CPLD Core Implementation – DS-560
• Schematic and Simulator Interfaces
• X-BLOX – DS-380
• Xilinx ABEL Design Entry – DS-371
• Xilinx ABEL Design Entry – DS-571
• Xilinx-Synopsys Interface (XSI) – DS401
• XChecker Cables
• Demonstration Boards
Development Systems:
Individual Product Descriptions
June 1, 1996 (Version 1.0)
Development Systems: Individual Product Descriptions
2-30 June 1, 1996 (Version 1.0)
FPGA Core Implementation – DS-502
Core Implementation Includes:
• Software to process an XNF file for an XC2000,
XC3000, XC3000A, XC3100, XC3100A, XC4000/E,
XC5200 device into a BIT or PROM file that can be
downloaded
• Automatic or interactive implementation
• XACT Performance™ system-level timing-driven
mapping, placement, and routing
• Fast incremental design capability
• Advanced logic reduction algorithms
• Comprehensive design rule checker
• Powerful design editor
• Static timing analyzer
• Bitstream and PROM file generators
• Original hierarchical netlist-based back-annotation
• Software Support and Updates if on maintenance
Support and Updates Include:
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Hardware Requirements:
PC
• Fully compatible PC386/486
• MS-Windows 3.1 (minimum)
• MS-DOS version 5.0 (minimum)
• Minimum 50 Mbytes hard-disk space for Xilinx software
• One 3.5" High-Density floppy disk drive or ISO 9660
type CD-ROM drive
• VGA display
• One parallel and two serial ports
• 16 Mbytes of RAM for devices up to XC4008
• 32 Mbytes of RAM for XC3195, XC4010, and XC4013
• Mouse
Workstations
• 65 Mbytes hard-disk drive space for Xilinx software
• Other hardware requirements are same as for the
Standard package
June 1, 1996 (Version 1.0) 2-31
CPLD Core Implementation – DS-560
CPLD Core Implementation Includes:
• Fitter software to process XC7000 and XC9500 family
designs
• Automatic optimization and mapping
• Automatic use of UIM resources
• Automatic arithmetic functions
• Complete optimization and collapsing
• High speed compilation
Support and Updates Include:
• Documentation Updates
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX
XACT-CPLD provides a complete, user-friendly, multi-plat-
form design environment for implementing behavioral or
schematic designs. XACT-CPLD allows users to easily cre-
ate, v erify, and implement logic designs targeting the entire
range of Xilinx XC7000 and XC9500 series devices.
Automatic Logic Mapping and Optimization
The automatic partitioning and mapping capabilities of
XACT-CPLD allow the designer to concentrate on design
functionality without concern for physical implementation;
all device resources are automatically mapped and inter-
connected with no user intervention required. In addition,
automatic logic optimization insures the highest perfor-
mance and the most efficient usage of device resources.
Because of these automatic features, the user does not
need a detailed knowledge of the de vice architecture . How-
ever, XACT-CPLD also allows the designer to fully control
the physical mapping of logic and I/O resources when nec-
essary.
Required Hardware Environment
• Fully compatible PC 486/Pentium
• MS-Windows 3.1
• MS-DOS version 5.0 (minimum)
• Minimum 26 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel port for EZTag download cable
• One serial port for Windows compatible mouse
• 16 MB of RAM
Feature Summary
• Advanced XACT
step
v6.0 XC7000 implementation
software with fully automatic device selection, multiple
pass optimization, partitioning and mapping, and timing
driven fitting.
• XC9500 implementation software with advanced
pinlocking capability.
• EZTag download software supporting the programming
of multiple Xilinx CPLDs anywhere in a JTAG chain.
• Includes XC9500 Synopsys, Viewlogic, and OrCAD
interfaces.
• On-line tutorials and documentation
• Static timing report
• Schematic Design Entry — XACT-CPLD, coupled with
the appropriate external interface , provides a schematic
library that includes familiar TTL and PAL components
for use with industry-standard schematic editors such
as those available from OrCAD, ViewLogic, Mentor
Graphics, and Cadence Design Systems.
• Simulation Support — XACT-CPLD supports various
third-party simulators such as ViewLogic PROsim,
OrCAD VST, Mentor QuickSim, Cadence Verilog, and
Cadence RapidSim. Both functional and timing
simulation are supported.
• Board-Level Simulation Support — XACT-CPLD device
models are available from Logic Modeling Corporation
for board-level simulation on a variety of platforms.
• High-Speed Compilation — Design iterations are easily
performed and the results are quickly reported.
• Predictable Design Performance — The PAL-like
architecture of the Xilinx CPLDs provides fixed
predictable delays independent of physical placement,
routing, or device utilization.
• Automatic Mapping and Logic Optimization — Device
resources are automatically mapped for optimal
efficiency and high performance. Users can focus on
design functionality without concern for the physical
implementation in the device.
• Complete Design Control — Users have the option to
override the automatic features of XACT-CPLD and
selectively control any or all device resources.
• Multiple Platform Support — XACT-CPLD runs on Sun,
HP, and PC (DOS) platforms
Development Systems: Individual Product Descriptions
2-32 June 1, 1996 (Version 1.0)
Schematic and Simulator Interfaces
Interfaces and libraries for several popular schematic edi-
tors and timing simulators are available as individual prod-
ucts, f or users that already own an editor and sim ulator . For
designers looking for a design entry tool, Xilinx offers Xilinx-
specific versions of Viewlogic’s schematic editor, simulator,
and ViewSynthesis VHDL synthesizer and VHDL simulator .
The follo wing products are a v ailab le f or the platf orms noted
in parentheses:
DS-390 Viewlogic schematic editor with Xilinx libraries and
interface (PC)
DS-290 Viewlogic simulator with Xilinx libraries and inter-
face (PC)
DS-391 Libraries and interfaces that support Viewlogic’s
Workview Office Series, PRO Series, and Powerview
design entry and simulation tools (PC, Sun, HP700)
DS-344 Libraries and interfaces for Mentor Graphics
Design Architect schematic editor and QuickSim II simula-
tor (HP700, Sun)
DS-35 Libraries and interfaces for OrCAD 386+ schematic
editor and VST 386+ simulator (PC)
Features
• Complete set of primitive and macro libraries for all
FPGA and CPLD products
• Full simulation models provides f or accurate post-la yout
timing analysis
• Unified libraries allow easy migration between all Xilinx
architectures, including CPLDs
• Converts schematic drawings to Xilinx Netlist Format
(XNF) output
• Converts XNF files to format compatible with logic and
timing simulators
• Supports unlimited levels of hierarchy
• Includes one year of support and updates
• All above products can be purchased with core
implementation tools as a package, offering easier
upgrading and reduced cost.
X-BLOX – DS-380
X-BLOX Includes:
• Parameter-based schematic and function-generation
tool. Allows block-diagram design entry using generic
function modules.
• Works with many Schematic Entry Interfaces
(Viewlogic , Mentor, OrCAD, Cadence and other Alliance
Partners)
• Expert system that automatically utilizes the advanced
features of the XC5200 family, XC4000/E family and
XC3000A and XC3100A families
• Schematic library with more than 30 frequently-used
generic modules (adders, counters, decoders,
registers, MUXes, etc.)
• Software Support and Updates for first year
Note:
• XC5200, XC4000/E and XC3000A, XC3100A families
are supported. XC2000, XC3000, and XC3100 are not
supported.
• Additional Requirements:
Five Mbytes hard-disk space for program and design
files
June 1, 1996 (Version 1.0) 2-33
Xilinx ABEL Design Entry – DS-371
The Xilinx ABEL system gives designers the ability to enter
Xilinx designs using the industry standard ABEL Hardware
Description Language (ABEL-HDL). Designers can
describe circuits with Boolean equations, state machines
and truth tables. State machine and logic optimization soft-
ware automatically generates efficient logic for Xilinx
devices.
Many designs contain portions of logic that are best
described in a text-based format; some designs can be
completely described in this way. In the Xilinx ABEL sys-
tem, Xilinx designs can be created with Boolean equations,
state machines, and truth tables. The ABEL HDL makes
designing quick and simple. Intelligent state machine and
logic optimization software automatically creates efficient,
fast state machines. The ABEL simulator allows functional
simulation of ABEL-HDL designs.
CPLD designs may be entered entirely with ABEL-HDL.
FPGA designs should be entered via a combination of
XABEL and a schematic editor to take optimal adv antage of
the Xilinx architectures. The recommended design flow is to
enter designs schematically with functional bloc ks that refer
to logic described in ABEL-HDL. From inside the Xilinx
ABEL environment, designers create and compile the logic
in these functional blocks. The Xilinx XMake program then
compiles the complete design to a bitstream that can be
downloaded to a Xilinx device. XMake automatically calls
the software that merges the v arious design files (schemat-
ics and ABEL-HDL), partitions, places and routes the
design and creates the final bitstream. The design can then
be verified with a simulator and a timing analyz er , as well as
verified in-circuit.
One-Hot Encoding
For the flop-flop rich, fan-in limited Xilinx FPGA architec-
ture, One-Hot Encoding (OHE) is the preferred technique
for implementing high-perf ormance state machines. OHE is
also know as state-per-bit encoding, since it uses one flip-
flop per state. OHE takes advantage of the abundance of
flip-flops in Xilinx FPGAs to reduce the levels of logic
required to implement a state machine. This implementa-
tion significantly increases performance over fully encoded
state machines, the traditional technique used in PLDs . Xil-
inx ABEL automatically uses OHE on symbolic state
machines created in ABEL-HDL for FPGAs.
Features
• State machine and Boolean equation entry via DATA
I/O’s ABEL language
• ABEL Functional Simulator
• Xilinx-specific ABEL environment, compiler, and
optimizer for FPGAs
• Automatic symbolic One-Hot encoding or fully encoded
state-machine implementation
• Ability to integrate ABEL designs with other schematic
elements
• Software Support and Updates for the first year
Support and Updates Include
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Software Updates if on maintenance
• Online Documentation
• World Wide W eb Access
• Technical Newsletter
• Extensive Application Notes
Additional Requirements
• 10 Mbytes hard-disk space for program and design files
Development Systems: Individual Product Descriptions
2-34 June 1, 1996 (Version 1.0)
Xilinx ABEL Design Entry – DS-571
XABEL-CPLD is the new Xilinx development system
designed for PAL and CPLD users. With this completely self
contained system, customers can quickly and easily inte-
grate their logic into Xilinx CPLDs using the industry-stan-
dard ABEL hardware description language.
XABEL-CPLD Includes
• Familiar Data I/O ABEL, Windows based environment
for design entry, simulation and fitting
• Hierarchical design entry and JEDEC file conversion
• Functional simulation with graphical waveform viewer
• Static timing report
• Advanced XACT
step
v6.0 XC7000 and XC9500 fitters
with fully automatic device selection, multiple pass
optimization, partitioning and mapping, and timing
driven fitting
• EZTag download software and cable
• Online tutorial and online help reduces learning curve
Support and Updates Include
• Hotline Telephone Support
• Access to Xilinx Technical Bulletin Board
• Apps FAX and E-Mail
• Online tutorial and help
Required Hardware Environment
• Fully compatible PC 486/Pentium
• MS-Windows 3.1
• MS-DOS version 5.0 (minimum)
• Minimum 45 MB hard disk space
• ISO 9660 type CD ROM drive
• VGA display
• One parallel port for EZTag download cable
• One serial port for Windows compatible mouse
• 16 MB of RAM
Feature Summary
• Familiar Data I/O ABEL, Windows based environment
for design entry, simulation and fitting provides a simple,
single push button design flow
• Industry-standard ABEL-HDL supports state machines,
high level logic descriptions, truth tables and equation
entry
• Hierarchical design entry and JEDEC file conversion
enables reuse of existing PAL codes, simplifying PAL
integration into Xilinx CPLDs
• Functional simulation with graphical waveform viewer
and static timing reports facilitate rapid design
verification
• Advanced XACT
step
v6.0 fitter’s architecture specific
knowledge let’s the user focus on design functionality
• Online tutorial leads users through the entire design
process in minutes
• Extensive online help system places all documentation
just a mouse-click away
June 1, 1996 (Version 1.0) 2-35
Xilinx-Synopsys Interface (XSI) – DS-401
This interface and library product supports VHDL and Ver-
ilog/HDL synthesis using either the Synopsys Design Com-
piler or FPGA Compiler products
Features
• Synthesis libraries for:
XC3000/XC3100, XC4000/E and XC5000 family
FPGAs
XC7000 and XC9500 family CPLDs
• X-BLOX synthetic library
• Translator from Synopsys to Xilinx XNF
• Ability to integrate models with other design
• Available for Sun-4, and HP700, platforms
DS-401 (XSI) lets the Synopsys FPGA Compiler and
Design Compiler target the XC3000, XC3100, XC4000/E,
and XC5000 FPGA families and XC7500 and XC9500
CPLD families. XSI consists of synthesis libraries, a trans-
lator from Synopsys to XNF, and a librar y of X-BLOX func-
tions implemented using Synopsys DesignWare.
Language Support
Either VHDL or Verilog/HDL entry is supported through the
use of the appropriate Synopsys language compiler.
Compiler Support
FPGA Compiler is highly recommended for XC4000/E and
XC5200 designs due to its specific XC4000/E algorithms.
Design Compiler is sufficient for XC3000 and XC3100
designs.
Simulation Support
Behavioral simulation before compilation using Synopsys
VHDL System Simulator (VSS) is supported. In the future,
gate-level simulation of designs after layout will be sup-
ported as well.
Support and Updates
• Software updates for one year
• Documentation updates
• Hotline Telephone Support for the first six months
• Access to Xilinx bulletin board
• Apps FAX
Notes
• This product does not support the Synopsys Test
Compiler
• A Synopsys Standard package is available which
combines XSI (DS-401) and FPGA core
implementation tools (DS-502) in one product.
P ackages off er reduced prices over modules purchased
separately.
• The X-BLOX library allows Synopsys software to
automatically insert certain X-BLOX functions (adders,
subtracters, and comparators) where possible for
maximum performance. In-warranty XSI customer
receive X-BLOX as an automatic upgrade.
Development Systems: Individual Product Descriptions
2-36 June 1, 1996 (Version 1.0)
XChecker Cables
XChecker Cable Package Includes:
• XChecker cable
• Flying wire jumper
• Flat header jumper
• XChecker diagnostics fixture
XChecker Cable Features:
• Provides bitstream and PROM-file download capability
to FPGAs
• Provides readback capability
• Works with serial ports on IBM 386/486/Pentium and
compatibles
• Compatible with XACT XChecker diagnostics software
and the XACT Probe utility
• Flying-wire and flat-header jumpers provide easy
access during prototyping
Demonstration Board – FPGA
FPGA Demo Board Includes:
• Three 7-segment displays (one for XC3000, XC3000A
and two for XC4000/E)
• Two, octal DIP switches for inputs to LCA devices (one
for XC3000 and one for XC4000/E)
• Test pins for access to all LCA I/O
• XC4003A in 84-pin PLCC package
• XC3020A in 68-pin PLCC package
• Two 8-segment bar displa ys (one f or XC3000A and one
for XC4000/E)
• Program, Reset, and Spare momentary contact
switches
FPGA Demo Board Features
• Operates from a 5-V power supply
• Compatible with XChecker and parallel download
cables
• Supports Master-Serial configuration mode f or interface
to Xilinx serial PROMs
• Two sock ets, one can be used f or any XC2000, XC3000
or XC3100 device in a 68-pin PLCC package, the other
can be used for any XC4000/E device in an 84 pin
PLCC package
• Provides sockets for up to three daisy-chained serial
PROMs
• Includes 3 inch by 3 inch prototyping area
• Daisy-chain configuration capability (XC4000/E must be
first in the chain)
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
CPLD Products
CPLD Products
XC9500 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
XC9500 In-System Programmable CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
XC95180 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
XC95432 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
XC95576 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
XC7300 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
XC7300 CMOS CPLD Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
XC7318 18-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
XC7336/XC7336Q 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
XC7354 54-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
XC7372 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
XC73108 108-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
XC73144 144-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
XC7300 Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135
XC7200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145
XC7236A 36-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
XC7272A 72-Macrocell CMOS CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
CPLD Products Table of Contents
3-1
XC9500 In-System Programmable CPLD Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
FastCONNECT Switch Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
XACTstep™ Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
XC9536 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
XC9536 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
XC9572 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
XC9572 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
XC95108 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
XC9500 Series Table of Contents
XC9500 Series Table of Contents
3-2
XC95108 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
XC95144 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
XC95144 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
XC95180 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
XC95180 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
XC95180 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
XC95180 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
XC95216 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
XC95216 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
XC95288 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
XC95288 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
XC95432 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
XC95576 In-System Programmable CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
June 1, 1996 (Version 1.0) 3-3
Features
• High-performance
- 5 ns pin-to-pin logic delays on all pins
-f
CNT to 125 MHz
• Large density range
- 36 to 576 macrocells with 800 to12,800 usable gates
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-5, -7, -10 speed grades)
• Advanced 0.6µm CMOS 5V FastFLASH technology
Description
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in Table 1, the nine de vices of the XC9500 f amily
range in logic density from 800 to ov er 12,800 usab le gates
with 36 to 576 registers, respectively. Multiple package
options and associated I/O capacity are shown in Table 2.
The XC9500 family is fully pin-compatible allowing easy
design migration across multiple density options in a given
package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmab le ground pins to help reduce system
noise. I/Os may be configured for 3.3 V or 5 V operation. All
outputs provide 24 mA drive.
Architecture Description
Each XC9500 device is a subsystem consisting of multiple
Function Blocks (FBs) and I/O Blocks (IOBs) fully intercon-
nected by the FastCONNECT switch matrix. The IOB pro-
vides buffering for device inputs and outputs. Each FB
provides programmable logic capability with 36 inputs and
18 outputs. The FastCONNECT switch matrix connects all
FB outputs and input signals to the FB inputs. For each FB ,
12 to 18 outputs (depending on package pin-count) and
associated output enable signals drive directly to the IOBs.
See Figure 1.
XC9500 In-System
Programmable CPLD Family
June 1, 1996 (Version 1.0) Preliminary Product Information
XC9500 In-System Programmable CPLD Family
3-4 June 1, 1996 (Version 1.0)
Table 1: XC9500 Device Family
Note: fCNT = Operating frequency for 16-bit counters
fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2 or 4
1
I/O
I/O
I/O
I/O
3
X5877
Function
Block 2
36
Function
Block 3
36
18
18
18
18 Function
Block N
36
FastCONNECT Switch Matrix
Figure 1: XC9500 Architecture
XC9536 XC9572 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576
Macrocells 36 72 108 144 180 216 288 432 576
Usable Gates 800 1,600 2,400 3,200 4,000 4,800 6,400 9600 12,800
Registers 36 72 108 144 180 216 288 432 576
tPD (ns) 5 7.5 7.5 7.5 10 10 10 10 12
tSU (ns) 4.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 9.5
tCO (ns) 4.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 9.5
fCNT (MHz) 125 125 125 125 111 111 111 111 100
fSYSTEM (MHz) 100 83 83 83 67 67 67 67 67
Preliminary
June 1, 1996 (Version 1.0) 3-5
Table 2: Available Packages and Device I/O Pins
Note: Does not include the dedicated JTAG pins.
Function Block
Each Function Block, as sho wn in Figure 2, is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also
receives global clock, output enable, and set/reset signals.
The FB generates 18 outputs that drive the FastCONNECT
switch matrix. These 18 outputs and their corresponding
output enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-prod-
ucts representation. Thirty-six inputs provide 72 true and
complement signals into the programmable AND-array to
form 90 product terms. An y number of these product terms,
up to the 90 available, can be allocated to each macrocell
by the product term allocator.
Each FB supports local f eedback paths that allo w any num-
ber of FB outputs to drive into its own programmable AND-
array without going outside the FB.
XC9536 XC9572 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576
44-Pin PLCC 34
44-Pin VQFP 34
84-Pin PLCC 69 69
100-Pin PQFP 72 81 81
100-Pin TQFP 72 81
160-Pin PQFP 108 133 133 133
208-Pin HQFP 168 168 168
304-Pin HQFP 192 232 232
Macrocell 18
Macrocell 1
Programmable
AND-Array Product
Term
Allocators
From
FastCONNECT
Switch Matrix
X5878
36
1
To FastCONNECT
Switch Matrix
To I/O Blocks
OUT
Global
Set/Reset
3
18
PTOE
18
18
Global
Clocks
Figure 2: XC9500 Function Block
XC9500 In-System Programmable CPLD Family
3-6 June 1, 1996 (Version 1.0)
Macrocell
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function. The macrocell and
associated FB logic is shown in Figure 3.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates)
to implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product
term allocator associated with each macrocell selects how
the five direct terms are used.
The macrocell register can be configured as a D-type or T-
type flip-flop, or it may be bypassed for combinatorial oper-
ation. Each register supports both asynchronous set and
reset operations. During power-up , all user registers are ini-
tialized to the user-defined preload state (default to 0 if
unspecified).
X5879
To
FastCONNECT
Switch Matrix
Additional
Product
Terms
(from other
macrocells)
Global
Set/Reset Global
Clocks
Additional
Product
Terms
(from other
macrocells)
To 
I/O Blocks
OUT
1
0
36
3
PTOE
D/T Q
S
R
Product
Term
Allocator
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
Figure 3: XC9500 Macrocell Within Function Block
June 1, 1996 (Version 1.0) 3-7
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enab le sig-
nals. As shown in Figure 4, the macrocell register clock
originates from either of three global clocks or a product
term clock. Both tr ue and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
D/T
S
R
Macrocell
X5880
I/O/GSR
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
I/O/GCK1
I/O/GCK2
I/O/GCK3
Figure 4: Macrocell Clock and Set/Reset Capability
XC9500 In-System Programmable CPLD Family
3-8 June 1, 1996 (Version 1.0)
Product T erm Allocator
The product term allocator controls how the five direct prod-
uct terms are assigned to each macrocell. For example, all
five direct terms can drive the OR function as shown in
Figure 5.
The product term allocator can re-assign other product
terms within the FB to increase the logic capacity of a mac-
rocell beyond five direct terms. Any macrocell requiring
additional product terms can access uncommitted product
terms in other macrocells within the FB. Up to 15 product
terms can be available to a single macrocell with only a
small incremental delay of tPTA, as shown in Figure 6.
Macrocell
Product Term
Logic
Product Term
Allocator
X5894
Figure 5: Macrocell Logic Using Direct Product Term
Macrocell Logic
With 15 P-Terms
Product Term
Allocator
Product Term
Allocator
X5895
Product Term
Allocator
Figure 6: Product Term Allocation With 15 Product
Terms
June 1, 1996 (Version 1.0) 3-9
The product term allocator can re-assign product terms
from any macrocell within the FB b y combining partial sums
of products over several macrocells, as shown in Figure 7.
In this example, the incremental delay is only 2*tPTA. All 90
product terms are available to any macrocell, with a maxi-
mum incremental delay of 8*tPTA.
Macrocell Logic
With 18 
Product Terms
Macrocell Logic
With 2 
Product Terms
Product Term
Allocator
Product Term
Allocator
X5896
Product Term
Allocator
Product Term
Allocator
Figure 7: Product Term Allocation Over Several Macrocells
XC9500 In-System Programmable CPLD Family
3-10 June 1, 1996 (Version 1.0)
The internal logic of the product term allocator is shown in Figure 8.
D/T Q
S
R
From Upper
Macrocell To Upper
Macrocell
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Set/Reset
Global Clocks
Product Term OE
Product Term
Allocator
To Lower
Macrocell
From Lower
Macrocell X5881
1
0
Figure 8: Product Term Allocator Logic
June 1, 1996 (Version 1.0) 3-11
FastCONNECT Switch Matrix
The FastCONNECT switch matrix connects signals to the
FB inputs, as shown in Figure 9. All IOB outputs (corre-
sponding to user pin inputs) and all FB outputs drive the
FastCONNECT matrix. Any of these (up to a FB fan-in limit
of 36) may be prog rammably selected to driv e each FB with
a uniform delay.
The FastCONNECT switch matrix is capable of combining
multiple internal connections into a single wired-AND out-
put before driving the destination FB. This provides addi-
tional logic capability and increases the effective logic fan-
in of the destination FB without any additional timing delay.
This capability is av ailab le for internal connections originat-
ing from FB outputs only. It is automatically invoked by the
development software where applicable.
X5882
Function Block
FastCONNECT
Switch Matrix
(36)
I/O
Function Block
I/O Block
18
18
I/O Block
(36)
Wired-AND Capability
I/O
D/T Q
D/T Q
Figure 9: FastCONNECT Switch Matrix
XC9500 In-System Programmable CPLD Family
3-12 June 1, 1996 (Version 1.0)
I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See Figure 10 fo r
details.
The input buffer is compatible with standard 5 V CMOS, 5 V
TTL and 3.3 V signal levels. The input b uff er uses the internal
5 V voltage supply (V CCINT) to ensure that the input thresh-
olds are constant and do not vary with the VCCIO voltage.
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of
the global OE signals, always “1”, or always “0”. There are
two global output enables f or de vices with up to 144 macro-
cells, and f our global output enab les f or de vices with 180 or
more macrocells. Both polarities of any of the global 3-state
control (GTS) pins may be used within the device.
I/O Block
Macrocell
X5899
Product Term OE PTOE
Switch Matrix
OUT
(Inversion in
AND-array)
Global OE 1
1
To other
Macrocells
VCCINT
Slew Rate
Control
0
Global OE 2
Available in
XC95180, XC95216
and XC95288
Global OE 3
Global OE 4
I/O/GTS1
I/O
I/O/GTS2
I/O/GTS3
I/O/GTS3
To FastCONNECT
User-
Programmable
Ground
Pull-up
Resistor
Figure 10: I/O Block and Output Enable Capability
June 1, 1996 (Version 1.0) 3-13
Each output has independent slew rate control. Output
edge rates may be programmably slowed down to reduce
system noise (with an additional time delay of tSLEW). See
Figure 11.
Each IOB provides user progr ammab le g round pin capabil-
ity. This allows device I/O pins to be configured as addi-
tional ground pins. By tying strategically located
programmable ground pins to the external ground connec-
tion, system noise generated from large numbers of simul-
taneous switching outputs may be reduced.
A control pull-up resistor (typically 10K ohms) is attached to
each device I/O pin to prevent device pins from floating
when the device is not in normal user operation. This resis-
tor is active during device programming mode and system
power-up. It is also activated for an erased device. The
resistor is deactivated during normal operation.
The output driver is capable of supplying 24 mA output
drive. All output drivers in the device may be configured for
either 5 V TTL levels or 3.3 V levels by connecting the
device output voltage supply (VCCIO) to a 5 V or 3.3 V
voltage supply. Figure 12 shows how the XC9500 device
can be used in 5 V only and mixed 3.3 V/5 V systems.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design changes depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500 devices
have architectural features that enhance the ability to
accept design changes while maintaining the same pinout.
The XC9500 provides 100% routing within the
FastCONNECT switch matrix, and incorporates a flexible
Function Block that allo ws block-wide allocation of a vailab le
p-terms. This provides a high level of confidence of main-
taining both input and output pin assignments for unex-
pected design changes.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be ab le to fit into a larger pin-compatib le device
using the same pin assignments.
Time
0 0
1.5 V
Standard
Output
Voltage
(a)
Slew-Rated Limited
tSLEW
Time
1.5 V
Output
Voltage
(b)
tSLEW
Standard
Slew-Rated Limited
X5900
Figure 11: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
IN OUT
XC9500
CPLD
VCCINT VCCIO
5 V
5 V CMOS
5 V
or
or
0 V
3.3 V
GND
(b) X5901
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
3.3 V
3.3 V
0 V
IN OUT
XC9500
CPLD
VCCINT VCCIO
5 V
5 V CMOS
5 V
or
or
0 V
GND
(a)
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
5 V TTL
~ 4 V
0 V
Figure 12: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems
XC9500 In-System Programmable CPLD Family
3-14 June 1, 1996 (Version 1.0)
In-System Programming
XC9500 devices are prog r ammed in-system via a standard
4-pin JTAG protocol, as shown in Figure 13. In-system pro-
gramming offers quick and efficient design iterations and
eliminates package handling. The Xilinx development sys-
tem provides the programming data sequence using a
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
The system designer must ensure that the system is well-
behaved before the XC9500 device is programmed with a
user pattern. During XC9500 programming, all I/Os are tri-
stated and pulled-up.
XC9500 devices also can be programmed by third-party
device programmers.
Endurance
All XC9500 CPLDs provide a minimum endurance level of
10,000 in-system program/erase cycles. Each device
meets all functional, performance, and data retention spec-
ifications within this endurance limit.
IEEE 1149.1 Boundary-Scan (JTAG)
XC9500 devices fully support IEEE 1149.1 boundar y-scan
(JTAG). Extest, Sample/Preload, Bypass, Usercode, Intest,
Idcode, and Highz instructions are supported in each
device. All in-system programming, erase, and verify
instructions are implemented as fully compliant extensions
of the 1149.1 instruction set.
Refer to the application note on the XC9500 JTAG instruc-
tion set for additional information.
Design Security
XC9500 devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming. Table 3 shows the f our diff erent security settings
available.
The read security bits can be set by the user to pre vent the
internal programming pattern from being read or copied.
Erasing the entire device is the only way to reset the read
security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming by the user.
Once set, the write-protection may be deactiv ated when the
device needs to be reprogrammed with a valid pattern.
Table 3: Data Security Options
Default
Default
Read Allowed
Read Security
Program/Erase Allowed
Read Inhibited
Program/Erase Allowed
Read Allowed
Program/Erase Inhibited
Read Inhibited
Program/Erase Inhibited
Set
Set
Write Security
X5905
X5902
GND
V
CC
(a) (b)
Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
June 1, 1996 (Version 1.0) 3-15
Low Power Mode
All XC9500 devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in low-
power mode by the user. Performance-critical parts of the
application can remain in standard power mode, while
other par ts of the application may be programmed for low-
power operation to reduce the overall power dissipation.
Macrocells programmed for low-power mode incur addi-
tional delay (t LP) in pin-to-pin combinatorial dela y as well as
register setup time. Product ter m clock to output and prod-
uct term output enable delays are unaff ected b y the macro-
cell power-setting.
Timing Model
The uniformity of the XC9500 architecture allows a simpli-
fied timing model for the entire device. The basic timing
model is shown in Figure 14. Detailed timing information on
a design, including secondary parameters, can be easily
obtained from the timing report in the XACT
step
develop-
ment system.
The basic timing model is valid for macrocell functions that
use the direct product terms only, with standard power set-
ting, and standard slew rate setting. Table 4 shows how
each of the ke y timing parameters is affected b y the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term
path. If only direct product terms are used, then the logic
span is 0. The Figure 6 example shows that up to 15 prod-
uct terms are available with a span of 1. In the case of
Figure 7, the 18 product term function has a span of 2.
X5903
Combinatorial
Logic
Propagation Delay = tPD
(a)
Combinatorial
Logic
Setup Time = tSU
tSU
tPSU
tPCO
tCO
tCO
Clock to Out Time = tCO
(b)
D/T Q
Combinatorial
Logic
Internal System Cycle Time = tSYSTEM
(d)
D/T Q
Combinatorial
Logic
Combinatorial
Logic
Propagation Delay = tPD + tFBK
With Feedback
Setup Time = tSU + tFBK
With Feedback
(f)
Combinatorial
Logic
Combinatorial
Logic
Combinatorial
Logic
All resources within FB using local Feedback
Setup
Time
Internal Cycle Time = tCNT
(e)
D/T Q
Combinatorial
Logic
Setup Time = tPSU Clock to Out Time = tPCO
(c)
P-Term Clock
Path
Clock to Out Time = tCO
D/T Q
(g)
D/T Q
Figure 14: Basic Timing Model
XC9500 In-System Programmable CPLD Family
3-16 June 1, 1996 (Version 1.0)
Power-Up Characteristics
The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until VCCINT supply voltage is at a safe level (approx-
imately 3.8 V). During this time, all device pins and JTAG
pins are disabled, and all device outputs are disabled with
the IOB pull-up resistors (~ 10K ohms) enabled. See
Table 5. When the supply voltage reaches a safe level, all
user registers become initialized (within 100 µs typical),
and the device is immediately available for operation, as
shown in Figure 15.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
the IOB pull-up resistors enabled. The JTAG pins are
enabled to allow the device to be programmed at any time.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
In mixed 3.3 V/5 V systems, it is recommended that VCCINT
≥ VCCIO at all times during the power-up sequence.
XACT
step
™ Development System
The XC9500 CPLD family is fully supported by the Xilinx
XACT
step
development system. The designer can create
the design using ABEL, schematics, equations, VHDL or
other HDL languages in a variety of software front-end-
tools. The XACT
step
development system can be used to
implement the design and generate a JEDEC bitmap which
can be used to program the XC9500 de vice. The XA CT
step
development system includes JTAG download software
that can be used to program the devices via a download
cable.
FastFLASH T echnology
An advanced 0.6 µm CMOS Flash process is used to f abricate all
XC9500 devices . Specifically developed for Xilinx in-system pro-
grammable CPLDs, the process provides high performance
logic capability and endurance of 10,000 program/erase
cycles.
Table 4: Timing Model Parameters
Note: 1. S = the logic span of the function, as defined in the text.
Table 5: XC9500 Device Characteristics
VCCINT
No
Power
3.8 V
(Typ)
0 V
No
Power
Quiescent
State Quiescent
State
User Operation
Initialization of User Registers X5904
Figure 15: Device Behavior During Power-up
Description Parameter Product T erm
Allocator1Macrocell
Low-Power Setting Output Slew-Limited
Setting
Propagation Delay tPD + tPTA * S+ t
LP + tSLEW
Global Clock Setup Time tSU + tPTA * S+ t
LP –
Global Clock-to-output tCO – – + tSLEW
Product Term Clock Setup
Time tPSU + tPTA * S+ t
LP –
Product Term Clock-to-output tPCO – – + tSLEW
Internal System Cycle Period tSYSTEM + tPTA * S + tLP –
Feedback Time tFBK + tPTA * S + tLP –
Device
Feature Quiescent
State Erased Device
Operation Valid User
Operation
IOB Pull-up Resistors Enabled Enabled Disabled
Device Outputs Disabled Disabled As Configured
Device Inputs and Clocks Disabled Disabled As Configured
Function Block Disabled Disabled As Configured
JTAG Controller Disabled Enabled Enabled
June 1, 1996 (Version 1.0) 3-17
Features
• 5 ns pin-to-pin logic delays on all pins
•f
CNT to 125 MHz
• 36 macrocells with 800 usable gates
• Up to 34 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-5, -7, -10 speed grades)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in 44-pin PLCC and 44-pin VQFP packages
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architec-
ture overview.
Power Management
P o wer dissipation can be reduced in the XC9536 b y config-
uring macrocells to standard or low-power modes of oper a-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation f or the XC9536 de vice .
XC9536 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Preliminary Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
050
(50)
(30)
(83)
(50)
100
High Performance
Low Power
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
XC9536 In-System Programmable CPLD
3-18 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5919
1
Function
Block 2
36
18
18
FastCONNECT Switch Matrix
Figure 2: XC9536 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-19
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for e xtended periods
of time may affect device reliability.
Recommended Operating Conditions1
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter Value Units
VCC Supply voltage relative to GND -0.5 to 7.0 V
VIN DC input voltage relative to GND -0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic and input buffer 4.75
(4.5) 5.25
(5.5) V
VCCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V opera-
tion 3.0 3.6 V
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCCINT +0.5 V
VOOutput voltage 0 VCCINT + 0.5 V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5 V operation IOH = -4.0 mA
VCC = Min 2.4 V
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min 2.4 V
VOL Output low voltage for 5 V operation IOL = 24 mA
VCC = Min 0.5 V
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
CIN I/O capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC Operating Supply Current
(low power mode, active) VI = GND, No load
f = 1.0 MHz 30 mA Typ
XC9536 In-System Programmable CPLD
3-20 June 1, 1996 (Version 1.0)
AC Characteristics
Note: 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.
Symbol Parameter XC9536-5 XC9536-7 XC9536-10 XC9536-15 Units
Min Max Min Max Min Max Min Max
tPD I/O to output valid 5.0 7.5 10 15 ns
tSU I/O setup time before GCK 4.5 5.5 6.5 8.0 ns
tHI/O hold time after GCK 0000ns
t
CO GCK to output valid 4.5 5.5 6.5 8.0 ns
fCNT 16-bit counter frequency 125 125 111.0 95.0 MHz
fSYSTEM 1Multiple FB Internal Operating Frequency 100 83.0 67.0 55.0 MHz
tPSU I/O setup time before p-term clock input 0.5 0.5 1.0 2.0 ns
tPH I/O hold time after p-term clock input 4.0 5.0 5.5 6.0 ns
tPCO P-term clock to output valid 7.5 10.5 12.0 14.0 ns
tOE GTS to output valid 6.0 7.0 10.0 15.0 ns
tOD GTS to output disable 6.0 7.0 10.0 15.0 ns
tPOE Product term OE to output valid 10.5 13.0 15.5 18.0 ns
tPOD Product term OE to output disable 10.5 13.0 15.5 18.0 ns
tPTA Product term allocator delay 1.5 1.5 2.0 2.0 ns
tFBK Internal combinatorial feedback delay NA 8.5 12.0 17.0 ns
tWLH GCK pulse width (High or Low) 4.0 4.0 4.5 5.0 ns
fTOG Export Control Max. flip-flop toggle rate 125 125 111 100 MHz
tSLEW Slew rate time delay 3.5 4.0 4.5 5.5 ns
tLP Low power time delay adder 8.0 8.0 8.5 8.5 ns
Preliminary
R1
VTEST
CL
R2
Device Output Output Type
VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X5906
VCCIO
5.0 V
3.3 V
Figure 3: AC Load Circuit
June 1, 1996 (Version 1.0) 3-21
XC9536 I/O Pins
Note: [1] Global control pin
XC9536 Global, JTAG and Power Pins
Function
Block Macrocell PC44 VQ44 BScan
Order Notes Function
Block Macrocell PC44 VQ44 BScan
Order Notes
1 1 2 40 105 2 1 1 39 51
1 2 3 41 102 2 2 44 38 48
1 3 5 43 99 [1] 2 3 42 36 45 [1]
1 4 4 42 96 2 4 43 37 42
1 5 6 44 93 [1] 2 5 40 34 39 [1]
1 6 8 290 2 6 39 33 36 [1]
1 7 7 1 87 [1] 2 7 38 32 33
1 8 9 384 2 8 37 31 30
1 9 11 581 2 9 36 30 27
1 10 12 678 2 10 35 29 24
1 11 13 775 2 11 34 28 21
1 12 14 872 2 12 33 27 18
1 13 18 12 69 2 13 29 23 15
1 14 19 13 66 2 14 28 22 12
1 15 20 14 63 2 15 27 21 9
1 16 22 16 60 2 16 26 20 6
1 17 24 18 57 2 17 25 19 3
1 18 ––54 2 18 ––0
Pin Type PC44 VQ44
I/O/GCK1 5 43
I/O/GCK2 6 44
I/O/GCK3 7 1
I/O/GTS1 42 36
I/O/GTS2 40 34
I/O/GSR 39 33
TCK 17 11
TDI 15 9
TDO 30 24
TMS 16 10
VCCINT 5 V 21,41 15,35
VCCIO 3.3 V/5 V 32 26
GND 23,10,31 17,4,25
No Connects — —
XC9536 In-System Programmable CPLD
3-22 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
XC9536 - 5 VQ 44 C
Device Type
Speed Options
Temperature Range
Number of Pins
Package Type
Speed
-15
-10
-7
-5
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7.5 ns pin-to-pin delay
5 ns pin-to-pin delay
Packaging Options
PC44
VQ44
44-Pin Plastic Leaded Chip Carrier (PLCC)
44-Pin Very Thin Quad Flat Pack (VQFP)
Temperature Options
C
I
Commercial 0°C to 70°C
Industrial -40°C to 85°C
X5952
Plastic
PLCC
44
XC9536
X5907
Pins
Type
Code PC44
-15
-10
-7
-5
Plastic
VQFP
VQ44
84
Plastic
PLCC
PC84
Plastic
PQFP Power
QFP
160 208
PQ160 HQ208
C(I)
C(I)
C
C
C(I)
C(I)
C
C
Plastic
PQFP Plastic
TQFP
100
PQ100 TQ100
June 1, 1996 (Version 1.0) 3-23
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-7, -10 speed grades)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in 84-pin PLCC, 100-pin PQFP and 100-pin
TQFP packages
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 1 for the architec-
ture overview.
Power Management
P o wer dissipation can be reduced in the XC9572 b y config-
uring macrocells to standard or low-power modes of oper a-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
XC9572 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC9572 In-System Programmable CPLD
3-24 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5921
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
18
18
18
18
FastCONNECT Switch Matrix
Figure 1: XC9572 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-25
XC9572 I/O Pins
Notes: [1] Global control pin
Function
Block Macrocell PC84 PQ100 TQ100 BScan
Order Notes Function
Block Macrocell PC84 PQ100 TQ100 BScan
Order Notes
1 1 4 18 16 213 3 1 25 43 41 105
1 2 1 15 13 210 3 2 17 34 32 102
1 3 6 20 18 207 3 3 31 51 49 99
1 4 7 22 20 204 3 4 32 52 50 96
1 5 2 16 14 201 3 5 19 37 35 93
1 6 3 17 15 198 3 6 34 55 53 90
1 7 11 27 25 195 3 7 35 56 54 87
1 8 5 19 17 192 3 8 21 39 37 84
1 9 9 24 22 189 [1] 3 9 26 44 42 81
1 10 13 30 28 186 3 10 40 62 60 78
1 11 10 25 23 183 [1] 3 11 33 54 52 75
1 12 18 35 33 180 3 12 41 63 61 72
1 13 20 38 36 177 3 13 43 65 63 69
1 14 12 29 27 174 [1] 3 14 36 57 55 66
1 15 14 31 29 171 3 15 37 58 56 63
1 16 23 41 39 168 3 16 45 67 65 60
1 17 15 32 30 165 3 17 39 60 58 57
1 18 244240162 3 18 – 61 59 54
2 1 63 89 87 159 4 1 46 68 66 51
2 2 69 96 94 156 4 2 44 66 64 48
2 3 67 93 91 153 4 3 51 73 71 45
2 4 68 95 93 150 4 4 52 74 72 42
2 5 70 97 95 147 4 5 47 69 67 39
2 6 71 98 96 144 4 6 54 78 76 36
2 7 76 5 3 141 [1] 4 7 55 79 77 33
2 8 72 99 97 138 4 8 48 70 68 30
2 9 74 1 99 135 [1] 4 9 50 72 70 27
2 10 75 3 1 132 4 10 57 83 81 24
2 11 77 6 4 129 [1] 4 11 53 76 74 21
2 12 79 8 6 126 4 12 58 84 82 18
2 13 80 10 8 123 4 13 61 87 85 15
2 14 81 11 9 120 4 14 56 80 78 12
2 15 83 13 11 117 4 15 65 91 89 9
2 16 82 12 10 114 4 16 62 88 86 6
2 17 84 14 12 111 4 17 66 92 90 3
2 18 – 94 92 108 4 18 – 81 79 0
XC9572 In-System Programmable CPLD
3-26 June 1, 1996 (Version 1.0)
XC9572 Global, JTAG and Power Pins
Pin Type PC84 PQ100 TQ100
I/O/GCK1 9 24 22
I/O/GCK2 10 25 23
I/O/GCK3 12 29 27
I/O/GTS1 76 5 3
I/O/GTS2 77 6 4
I/O/GSR 74 1 99
TCK 30 50 48
TDI 28 47 45
TDO 59 85 83
TMS 29 49 47
VCCINT 5 V 38,73,78 7,59,100 5,57,98
VCCIO 3.3 V/5 V 22,64 28,40,53,90 26,38,51,88
GND 8,16,27,42,49,60 2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84
No Connects — 4,9,21,26,36,45,48,75,82 2,7,19,24,34,43,46,73,80
June 1, 1996 (Version 1.0) 3-27
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT to 125 MHz
• 108 macrocells with 2400 usable gates
• Up to 108 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-7, -10 speed grades)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• A v ailable in 84-pin PLCC , 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
XC95108 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Preliminary Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
050
100
(180)
(250)
(170)
200
300
100
High Performance
Low Power
X5898
Figure 1: Typical ICC vs. Frequency for XC95108
XC95108 In-System Programmable CPLD
3-28 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5897
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 5
36
Macrocells
1 to 18
Function
Block 6
36
18
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 2: XC95108 Architecture
Note: Function Block outputs indicated b y bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-29
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for e xtended periods
of time may affect device reliability.
Recommended Operation Conditions1
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter Value Units
VCC Supply voltage relative to GND -0.5 to 7.0 V
VIN DC input voltage relative to GND -0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic and input buffer 4.75
(4.5) 5.25
(5.5) V
VCCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCCINT +0.5 V
VOOutput voltage 0 VCCINT + 0.5 V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5 V operation IOH = -4.0 mA
VCC = Min 2.4 V
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min 2.4 V
VOL Output low voltage for 5 V operation IOL = 24 mA
VCC = Min 0.5 V
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
CIN I/O capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC Operating Supply Current
(low power mode, active) VI = GND, No load
f = 1.0 MHz 100 mA Typ
XC95108 In-System Programmable CPLD
3-30 June 1, 1996 (Version 1.0)
AC Characteristics
Note: 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.
Symbol Parameter XC95108-7 XC95108-10 XC95108-15 XC95108-20 Units
Min Max Min Max Min Max Min Max
tPD I/O to output valid 7.5 10 15 20 ns
tSU I/O setup time before GCK 5.5 6.5 8.0 10.0 ns
tHI/O hold time after GCK 0000ns
t
CO GCK to output valid 5.5 6.5 8.0 10.0 ns
fCNT 16-bit counter frequency 125 111 95.0 83.0 MHz
fSYSTEM 1Multiple FB Internal Operating Frequency 83.0 67.0 55.0 50.0 MHz
tPSU I/O setup time before p-term clock input 0.5 1.0 2.0 4.0 ns
tPH I/O hold time after p-term clock input 5.0 5.5 6.0 6.0 ns
tPCO P-term clock to output valid 10.5 12.0 14.0 16.0 ns
tOE GTS to output valid 7.0 10.0 15.0 20.0 ns
tOD GTS to output disable 7.0 10.0 15.0 20.0 ns
tPOE Product term OE to output valid 13.0 15.5 18.0 22.0 ns
tPOD Product term OE to output disable 13.0 15.5 18.0 22.0 ns
tPTA Product term allocator delay 1.5 2.0 2.0 2.0 ns
tFBK Internal combinatorial feedback delay 8.5 12.0 17.0 20.0 ns
tWLH GCK pulse width (High or Low) 4.0 4.5 5.0 6.0 ns
fTOG Export Control Max. flip-flop toggle rate 125 111 100 83 MHz
tSLEW Slew rate time delay 4.0 4.5 5.0 5.5 ns
tLP Low power time delay adder 8.0 8.5 8.5 8.5 ns
Preliminary
R1
VTEST
CL
R2
Device Output Output Type
VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X5906
VCCIO
5.0 V
3.3 V
Figure 3: AC Load Circuit
June 1, 1996 (Version 1.0) 3-31
XC95108 I/O Pins
Notes: [1] Global control pin
Function
Block Macrocell PC84 PQ100 TQ100 PQ160 BScan
Order Notes Function
Block Macrocell PC84 PQ100 TQ100 PQ160 BScan
Order Notes
1 1 – – – 25 321 3 1 – – – 45 213
1 2 1 15 13 21 318 3 2 14 31 29 47 210
1 3 2 16 14 22 315 3 3 15 32 30 49 207
1 4 – 21 19 29 312 3 4 – 36 34 57 204
1 5 3 17 15 23 309 3 5 17 34 32 54 201
1 6 4 18 16 24 306 3 6 18 35 33 56 198
1 7 – – – 27 303 3 7 – – – 50 195
1 8 5 19 17 26 300 3 8 19 37 35 58 192
1 9 6 20 18 28 297 3 9 20 38 36 59 189
1 10 – 26 24 36 294 3 10 – 45 43 69 186
1 11 7 22 20 30 291 3 11 21 39 37 60 183
1 12 9 24 22 33 288 [1] 3 12 23 41 39 62 180
1 13 – – – 34 285 3 13 – – – 52 177
1 14 10 25 23 35 282 [1] 3 14 24 42 40 63 174
1 15 11 27 25 37 279 3 15 25 43 41 64 171
1 16 12 29 27 42 276 [1] 3 16 26 44 42 68 168
1 17 13 30 28 44 273 3 17 31 51 49 77 165
1 18 – – – 43 270 3 18 – – – 74 162
2 1 – – – 158 267 4 1 – – – 123 159
2 2 71 98 96 154 264 4 2 57 83 81 134 156
2 3 72 99 97 156 261 4 3 58 84 82 135 153
2 4 – 4 2 4 258 4 4 – 82 80 133 150
2 5 74 1 99 159 255 [1] 4 5 61 87 85 138 147
2 6 75 3 1 2 252 4 6 62 88 86 139 144
2 7 – – – 9 249 4 7 – – – 128 141
2 8 76 5 3 6 246 [1] 4 8 63 89 87 140 138
2 9 77 6 4 8 243 [1] 4 9 65 91 89 142 135
2 10 – 9 7 12 240 4 10 – – – 147 132
2 11 79 8 6 11 237 4 11 66 92 90 143 129
2 12 80 10 8 13 234 4 12 67 93 91 144 126
2 13 – – – 14 231 4 13 – – – 153 123
2 14 81 11 9 15 228 4 14 68 95 93 146 120
2 15 82 12 10 17 225 4 15 69 96 94 148 117
2 16 83 13 11 18 222 4 16 – 94 92 145 114
2 17 84 14 12 19 219 4 17 70 97 95 152 111
2 18 – – – 16 216 4 18 – – – 155 108
XC95108 In-System Programmable CPLD
3-32 June 1, 1996 (Version 1.0)
XC95108 I/O Pins (continued)
XC95108 Global, JTAG and Power Pins
Function
Block Macrocell PC84 PQ100 TQ100 PQ160 BScan
Order Notes Function
Block Macrocell PC84 PQ100 TQ100 PQ160 BScan
Order Notes
5 1 – – – 76 105 6 1 – – –9151
5 2 32 52 50 79 102 6 2 45 67 65 103 48
5 3 33 54 52 82 99 6 3 46 68 66 104 45
5 4 – 48 46 72 96 6 4 – 75 73 116 42
5 5 34 55 53 86 93 6 5 47 69 67 106 39
5 6 35 56 54 88 90 6 6 48 70 68 108 36
5 7 – – –7887 6 7 –– – 105 33
5 8 36 57 55 90 84 6 8 50 72 70 111 30
5 9 37 58 56 92 81 6 9 51 73 71 113 27
5 10 – – –8478 6 10 – – – 107 24
5 11 39 60 58 95 75 6 11 52 74 72 115 21
5 12 40 62 60 97 72 6 12 53 76 74 117 18
5 13 – – –8769 6 13 – – – 112 15
5 14 41 63 61 98 66 6 14 54 78 76 122 12
5 15 43 65 63 101 63 6 15 55 79 77 124 9
5 16 – 61 59 96 60 6 16 – 81 79 129 6
5 17 44 66 64 102 57 6 17 56 80 78 126 3
5 18 – – – 89 54 6 18 – – – 114 0
Pin Type PC84 PQ100 TQ100 PQ160
I/O/GCK1 9 24 22 33
I/O/GCK2 10 25 23 35
I/O/GCK3 12 29 27 42
I/O/GTS1 76 5 3 6
I/O/GTS2 77 6 4 8
I/O/GSR 74 1 99 159
TCK 30 50 48 75
TDI 28 47 45 71
TDO 59 85 83 136
TMS 29 49 47 73
VCCINT 5 V 38,73,78 7,59,100 5,57,98 10,46,94,157
VCCIO 3.3 V/5 V 22,64 28,40,53,90 26,38,51,88 1,41,61,81,121,141
GND 8,16,27,42,49,60 2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84 20,31,40,51,70,80,99
GND – – – 100,110,120,127,137
GND – – – 160
June 1, 1996 (Version 1.0) 3-33
Ordering Information
Component Availability
XC95108 - 7 PQ 160 C
Device Type
Speed Options
Temperature Range
Number of Pins
Package Type
Speed
-20
-15
-10
-7
20 ns pin-to-pin delay
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7 ns pin-to-pin delay
Packaging Options
PC84
PQ100
TQ100
PQ160
84-Pin Plastic Leaded Chip Carrier (PLCC)
100-Pin Plastic Quad Flat Pack (PQFP)
100-Pin Thin Quad Flat Pack (TQFP)
160-Pin Plastic Quad Flat Pack (PQFP)
Temperature Options
C
I
Commercial 0°C to 70°C
Industrial -40°C to 85°C
X5953
Plastic
PLCC
44
XC95108
X5941
Pins
Type
Code PC44
-20
-15
-10
-7
Plastic
VQFP
VQ44
84
Plastic
PLCC
PC84
Plastic
PQFP Power
QFP
160 208
PQ160 HQ208
C(I)
C(I)
C(I)
C
C(I)
C(I)
C(I)
C
C(I)
C(I)
C(I)
C
C(I)
C(I)
C(I)
C
Plastic
PQFP Plastic
TQFP
100
PQ100 TQ100
XC95108 In-System Programmable CPLD
3-34 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-35
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT to 111 MHz
• 144 macrocells with 3,200 usable gates
• Up to 133 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-7, -10 speed grades)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in 100-pin PQFP, and 160-pin PQFP
packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 1 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
XC95144 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC95144 In-System Programmable CPLD
3-36 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5922
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 8
36
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 1: XC95144 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-37
XC95144 I/O Pins
Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.
Function
Block Macrocell PQ100 PQ160 BScan
Order Notes Function
Block Macrocell PQ100 PQ160 BScan
Order Notes
1 1 – 38 429 3 1 – 53 321
1 2 15 21 426 3 2 27 37 318
1 3 16 22 423 3 3 – 84 315
1 4 – 25 420 3 4 – 45 312
1 5 17 23 417 3 5 29 42 309 [1]
1 6 18 24 414 3 6 30 44 306
1 7 – 32 411 3 7 – 48 303
1 8 19 26 408 3 8 31 47 300
1 9 20 28 405 3 9 32 49 297
1 10 – 74 402 3 10 – 89 294
1 11 21 29 399 3 11 34 54 291
1 12 22 30 396 3 12 35 56 288
1 13 – 39 393 3 13 – 55 285
1 14 24 33 390 [1] 3 14 36 57 282
1 15 25 35 387 [1] 3 15 37 58 279
1 16 – 78 384 3 16 – 34 276
1 17 26 36 381 3 17 38 59 273
1 18 – – 378 3 18 – – 270
2 1 – 3 375 4 1 – 149 267
2 2 4 4 372 [1] 4 2 92 143 264
2 3 – 147 369 4 3 – 107 261
2 4 – 158 366 4 4 – 123 258
2 5 5 6 363 [1] 4 5 93 144 255
2 6 6 8 360 [1] 4 6 94 145 252
2 7 – 7 357 4 7 – 151 249
2 8 8 11 354 4 8 95 146 246
2 9 9 12 351 4 9 96 148 243
2 10 – 155 348 4 10 – 114 240
2 11 10 13 345 4 11 97 152 237
2 12 11 15 342 4 12 98 154 234
2 13 – 5 339 4 13 – 150 231
2 14 12 17 336 4 14 99 156 228
2 15 13 18 333 4 15 1 159 225 [1]
2 16 – 105 330 4 16 – 14 222
2 17 14 19 327 4 17 3 2 219 [1]
2 18 – – 324 4 18 – – 216
XC95144 In-System Programmable CPLD
3-38 June 1, 1996 (Version 1.0)
XC95144 I/O Pins (continued)
Function
Block Macrocell PQ100 PQ160 BScan
Order Notes Function
Block Macrocell PQ100 PQ160 BScan
Order Notes
5 1 – 65 213 7 1 – – 105
5 2 39 60 210 7 2 55 86 102
5 3 – 27 207 7 3 – 50 99
5 4 – 76 204 7 4 – 43 96
5 5 41 62 201 7 5 56 88 93
5 6 42 63 198 7 6 57 90 90
5 7 – 67 195 7 7 – 83 87
5 8 43 64 192 7 8 58 92 84
5 9 44 68 189 7 9 60 95 81
5 10 – 93 186 7 10 – 109 78
5 11 45 69 183 7 11 61 96 75
5 12 48 72 180 7 12 62 97 72
5 13 – 66 177 7 13 – 85 69
5 14 51 77 174 7 14 63 98 66
5 15 52 79 171 7 15 65 101 63
5 16 – 52 168 7 16 – 87 60
5 17 54 82 165 7 17 66 102 57
5 18 – – 162 718––54
6 1–– 159 8 1 – –51
6 2 79 124 156 8 2 67 103 48
6 3 – 9 153 8 3 – 128 45
6 4 – 91 150 8 4 – 16 42
6 5 80 126 147 8 5 68 104 39
6 6 81 129 144 8 6 69 106 36
6 7 – 131 141 8 7 – 118 33
6 8 82 133 138 8 8 70 108 30
6 9 83 134 135 8 9 72 111 27
6 10 – 130 132 8 10 – 125 24
6 11 84 135 129 8 11 73 113 21
6 12 87 138 126 8 12 74 115 18
6 13 – 132 123 8 13 – 119 15
6 14 88 139 120 8 14 75 116 12
6 15 89 140 117 8 15 76 117 9
6 16 – 153 114 8 16 – 112 6
6 17 91 142 111 8 17 78 122 3
6 18 – – 108 8 18 ––0
June 1, 1996 (Version 1.0) 3-39
XC95144 Global, JTAG and Power Pins
Pin Type PQ100 PQ160
I/O/GCK1 24 33
I/O/GCK2 25 35
I/O/GCK3 29 42
I/O/GTS1 5 6
I/O/GTS2 6 8
I/O/GTS3 3 2
I/O/GTS4 4 4
I/O/GSR 1 159
TCK 50 75
TDI 47 71
TDO 85 136
TMS 49 73
VCCINT 5 V 7,59,100 10,46,94,157
VCCIO 3.3 V/5 V 28,40,53,90 1,41,61,81,121,141
GND 2,23,33,46,64,71,
77,86 20,31,40,51,70,80,
99,100,110,120,127,
137,160
No Connects – –
XC95144 In-System Programmable CPLD
3-40 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-41
Features
• 10 ns pin-to-pin logic delays on all pins
•f
CNT to 111 MHz
• 180 macrocells with 4,000 usable gates
• Up to 168 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-10 speed grade)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in 160-pin PQFP, and 208-pin HQFP
packages
Description
The XC95180 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of ten
36V18 Function Blocks, providing 4,000 usable gates with
propagation delays of 10 ns. See Figure 1 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95180 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
XC95180 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC95180 In-System Programmable CPLD
3-42 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5923
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 10
36
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 1: XC95180 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-43
XC95180 I/O Pins
Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
1 1 – 39 537 3 1 – 48 429
1 2 22 30 534 3 2 37 49 426
1 3 23 31 531 3 3 38 50 423
1 4 24 32 528 3 4 39 51 420
1 5 25 33 525 3 5 42 55 417 [1]
1 6 26 34 522 3 6 43 56 414
1 7 – 40 519 3 7 – 54 411
1 8 27 35 516 3 8 44 57 408
1 9 28 36 513 3 9 45 58 405
1 10 29 37 510 3 10 47 60 402
1 11 30 38 507 3 11 48 61 399
1 12 32 43 504 3 12 49 63 396
1 13 – 41 501 3 13 – 62 393
1 14 33 44 498 [1] 3 14 50 64 390
1 15 34 45 495 3 15 52 70 387
1 16 35 46 492 [1] 3 16 53 71 384
1 17 36 47 489 3 17 56 74 381
1 18 – – 486 3 18 – – 387
2 1 – 14 483 4 1 – 196 375
2 2 6 7 480 [1] 4 2 150 194 372
2 3 7 8 477 4 3 151 197 369
2 4 8 9 474 [1] 4 4 152 198 366
2 5 9 10 471 4 5 153 199 363
2 6 11 15 468 4 6 154 200 360
2 7 – 28 465 4 7 – 203 357
2 8 12 16 462 4 8 155 201 354
2 9 13 17 459 4 9 156 202 351
2 10 14 18 456 4 10 – 208 348
2 11 15 19 453 4 11 158 205 345
2 12 16 20 450 4 12 159 206 342 [1]
2 13 – 29 447 4 13 – 12 339
2 14 17 21 444 4 14 2 3 336 [1]
2 15 18 22 441 4 15 3 4 333
2 16 19 23 438 4 16 4 5 330 [1]
2 17 21 25 435 4 17 5 6 327
2 18 – – 432 4 18 – – 324
XC95180 In-System Programmable CPLD
3-44 June 1, 1996 (Version 1.0)
XC95180 I/O Pins (continued)
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
5 1 – 66 321 7 1 – 90 213
5 2 54 72 318 7 2 69 89 210
5 3 55 73 315 7 3 72 95 207
5 4 57 75 312 7 4 74 97 204
5 5 58 76 309 7 5 76 99 201
5 6 59 77 306 7 6 77 100 198
5 7 – 67 303 7 7 – 91 195
5 8 60 78 300 7 8 78 102 192
5 9 62 82 297 7 9 79 103 189
5 10 – 69 294 7 10 – 101 186
5 11 63 83 291 7 11 82 110 183
5 12 64 84 288 7 12 83 111 180
5 13 – 80 285 7 13 – 106 177
5 14 65 85 282 7 14 84 112 174
5 15 66 86 279 7 15 85 113 171
5 16 67 87 276 7 16 86 114 168
5 17 68 88 273 7 17 87 115 165
5 18 – – 270 7 18 – – 162
6 1 – 169 267 8 1 – 144 159
6 2 134 174 264 8 2 118 154 156
6 3 135 175 261 8 3 119 155 153
6 4 138 178 258 8 4 122 158 150
6 5 139 179 255 8 5 123 159 147
6 6 140 180 252 8 6 124 160 144
6 7 – 183 249 8 7 – 151 141
6 8 142 182 246 8 8 125 161 138
6 9 143 185 243 8 9 126 162 135
6 10 – 189 240 8 10 – 165 132
6 11 144 186 237 8 11 128 164 129
6 12 145 187 234 8 12 129 166 126
6 13 – 195 231 8 13 – 168 123
6 14 146 188 228 8 14 130 167 120
6 15 147 191 225 8 15 131 170 117
6 16 148 192 222 8 16 132 171 114
6 17 149 193 219 8 17 133 173 111
6 18 – – 216 8 18 – – 108
June 1, 1996 (Version 1.0) 3-45
XC95180 I/O Pins (continued)
XC95180 Global, JTAG and Power Pins
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
9 1 – – 105 10 1 – – 51
9 2 88 116 102 10 2 104 135 48
9 3 89 117 99 10 3 105 136 45
9 4 90 118 96 10 4 106 137 42
9 5 91 121 93 10 5 107 138 39
9 6 92 122 90 10 6 108 139 36
9 7 – 107 87 10 7 – 120 33
9 8 93 123 84 10 8 109 140 30
9 9 95 125 81 10 9 111 145 27
9 10 – 109 78 10 10 – 142 24
9 11 96 126 75 10 11 112 146 21
9 12 97 127 72 10 12 113 147 18
9 13 – 119 69 10 13 – 143 15
9 14 98 128 66 10 14 114 148 12
9 15 101 131 63 10 15 115 149 9
9 16 102 133 60 10 16 116 150 6
9 17 103 134 57 10 17 117 152 3
9 18––54 10 18––0
Pin Type PQ160 HQ208
I/O/GCK1 33 44
I/O/GCK2 35 46
I/O/GCK3 42 55
I/O/GTS1 6 7
I/O/GTS2 8 9
I/O/GTS3 2 3
I/O/GTS4 4 5
I/O/GSR 159 206
TCK 75 98
TDI 71 94
TDO 136 176
TMS 73 96
VCCINT 5 V 10,46,94,157 11,59,124,153,204
VCCIO 3.3 V/5 V 1,41,61,81,121,141 1,26,53,65,79,92,105,
132,157,172,181,184
GND 20,31,40,51,70,80,
99,100,110,120,127,
137,160
2,13,24,27,42,52,68,81,
93,104,108,129,130,
141,156,163,177,
190,207
No Connects – –
XC95180 In-System Programmable CPLD
3-46 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-47
Features
• 10 ns pin-to-pin logic delays on all pins
•f
CNT to 111 MHz
• 216 macrocells with 4800 usable gates
• Up to 168 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant (-10 speed grade)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in 160-pin PQFP and 208-pin HQFP
packages
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is compr ised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95216
device.
XC95216 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Preliminary Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
050
200
(360)
(500)
(340)
400
600
100
High Performance
Low Power
X5918
Figure 1: Typical ICC vs. Frequency For XC95216
XC95216 In-System Programmable CPLD
3-48 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5917
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 12
36
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 2: XC95216 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-49
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for e xtended periods
of time may affect device reliability.
Recommended Operating Conditions1
Note: 1. Numbers in parenthesis are for industrial-temperature range versions.
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter Value Units
VCC Supply voltage relative to GND -0.5 to 7.0 V
VIN DC input voltage relative to GND -0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) +260 °C
Symbol Parameter Min Max
VCCINT Supply voltage for internal logic and input buffer 4.75
(4.5) 5.25
(5.5)
VCCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5)
Supply voltage for output drivers for 3.3 V operation 3.0 3.6
VIL Low-level input voltage 0 0.80
VIH High-level input voltage 2.0 VCCINT +0.5
VOOutput voltage 0 VCCINT + 0.5
TIN Input signal transition time 50
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5 V operation IOH = -4.0 mA
VCC = Min 2.4 V
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min 2.4 V
VOL Output low voltage for 5 V operation IOL = 24 mA
VCC = Min 0.5 V
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC ±10.0 µA
CIN I/O capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC Operating Supply Current
(low power mode, active) VI = GND, No load
f = 1.0 MHz 200 mA
XC95216 In-System Programmable CPLD
3-50 June 1, 1996 (Version 1.0)
AC Characteristics
Note: 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.
Symbol Parameter XC95216-10 XC95216-15 XC95216-20 Units
Min Max Min Max Min Max
tPD I/O to output valid 10 15 20 ns
tSU I/O setup time before GCK 6.5 8.0 10.0 ns
tHI/O hold time after GCK 0 0 0 ns
tCO GCK to output valid 6.5 8.0 10.0 ns
fCNT 16-bit counter frequency 111 95.0 83.0 MHz
fSYSTEM 1Multiple FB Internal Operating Frequency 67.0 55.0 50.0 MHz
tPSU I/O setup time before p-term clock input 1.0 2.0 4.0 ns
tPH I/O hold time after p-term clock input 5.5 6.0 6.0 ns
tPCO P-term clock to output valid 12.0 14.0 16.0 ns
tOE GTS to output valid 10.0 15.0 20.0 ns
tOD GTS to output disable 10.0 15.0 20.0 ns
tPOE Product term OE to output valid 15.5 18.0 22.0 ns
tPOD Product term OE to output disable 15.5 18.0 22.0 ns
tPTA Product term allocator delay 2.0 2.0 2.0 ns
tFBK Internal combinatorial feedback delay 12.0 17.0 20.0 ns
tWLH GCK pulse width (High or Low) 4.5 5.0 6.0 ns
fTOG Export Control Max. flip-flop toggle rate 111 100 83 MHz
tSLEW Slew rate time delay 4.5 5.0 5.5 ns
Preliminary
R1
VTEST
CL
R2
Device Output Output Type
VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X5906
VCCIO
5.0 V
3.3 V
Figure 3: AC Load Circuit
June 1, 1996 (Version 1.0) 3-51
XC95216 I/O Pins
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
1 1 – – 645 3 1 – – 537
1 2 18 22 642 3 2 32 43 534
1 3 19 23 639 3 3 33 44 531 [1]
1 4 – 28 636 3 4 – 39 528
1 5 21 25 633 3 5 34 45 525
1 6 22 30 630 3 6 35 46 522 [1]
1 7 – – 627 3 7 – – 519
1 8 23 31 624 3 8 36 47 516
1 9 24 32 621 3 9 37 49 513
1 10 – 12 618 3 10 – 67 510
1 11 25 33 615 3 11 38 50 507
1 12 26 34 612 3 12 39 51 504
1 13 – – 609 3 13 – – 501
1 14 27 35 606 3 14 42 55 498 [1]
1 15 28 36 603 3 15 43 56 495
1 16 29 37 600 3 16 – 80 492
1 17 30 38 597 3 17 44 57 489
1 18 – – 594 3 18 – – 486
2 1 – – 591 4 1 – – 483
2 2 6 7 588 [1] 4 2 152 198 480
2 3 7 8 585 4 3 153 199 477
2 4 – 29 582 4 4 – 196 474
2 5 8 9 579 [1] 4 5 154 200 471
2 6 9 10 576 4 6 155 201 468
2 7 – – 573 4 7 – – 465
2 8 11 15 570 4 8 156 202 462
2 9 12 16 567 4 9 158 205 459
2 10 – 66 564 4 10 – 69 456
2 11 13 17 561 4 11 159 206 453 [1]
2 12 14 18 558 4 12 2 3 450 [1]
2 13 – – 555 4 13 – – 447
2 14 15 19 552 4 14 3 4 444
2 15 16 20 549 4 15 4 5 441 [1]
2 16 – 14 546 4 16 – 203 438
2 17 17 21 543 4 17 5 6 435
2 18 – – 540 4 18 – – 432
XC95216 In-System Programmable CPLD
3-52 June 1, 1996 (Version 1.0)
XC95216 I/O Pins (continued)
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
5 1 – – 429 7 1 – – 321
5 2 45 58 426 7 2 58 76 318
5 3 47 60 423 7 3 59 77 315
5 4 – 41 420 7 4 – 54 312
5 5 48 61 417 7 5 60 78 309
5 6 49 63 414 7 6 62 82 306
5 7 – – 411 7 7 – – 303
5 8 50 64 408 7 8 63 83 300
5 9 52 70 405 7 9 64 84 297
5 10 – 109 402 7 10 – 91 294
5 11 53 71 399 7 11 65 85 291
5 12 54 72 396 7 12 66 86 288
5 13 – – 393 7 13 – – 285
5 14 55 73 390 7 14 67 87 282
5 15 56 74 387 7 15 68 88 279
5 16 – 40 384 7 16 – 48 276
5 17 57 75 381 7 17 69 89 273
5 18 – – 378 7 18 – – 270
6 1 – – 375 8 1 – – 267
6 2 140 180 372 8 2 126 162 264
6 3 142 182 369 8 3 128 164 261
6 4 – 208 366 8 4 – 143 258
6 5 143 185 363 8 5 129 166 255
6 6 144 186 360 8 6 130 167 252
6 7 – – 357 8 7 – – 249
6 8 145 187 354 8 8 131 170 246
6 9 146 188 351 8 9 132 171 243
6 10 – 183 348 8 10 – 195 240
6 11 147 191 345 8 11 133 173 237
6 12 148 192 342 8 12 134 174 234
6 13 – – 339 8 13 – – 231
6 14 149 193 336 8 14 135 175 228
6 15 150 194 333 8 15 138 178 225
6 16 – 169 330 8 16 – 189 222
6 17 151 197 327 8 17 139 179 219
6 18 – – 324 8 18 – – 216
June 1, 1996 (Version 1.0) 3-53
XC95216 I/O Pins (continued)
Function
Block Macrocell PQ160 HQ208 BScan
Order Notes Function
Block Macrocell PQ160 HQ208 BScan
Order Notes
9 1 – – 213 11 1 – – 105
9 2 72 95 210 11 2 87 115 102
9 3 74 97 207 11 3 88 116 99
9 4 – 101 204 11 4 – 119 96
9 5 76 99 201 11 5 89 117 93
9 6 77 100 198 11 6 90 118 90
9 7 – – 195 11 7 – –87
9 8 78 102 192 11 8 91 121 84
9 9 79 103 189 11 9 92 122 81
9 10 – 90 186 11 10 – 107 78
9 11 82 110 183 11 11 93 123 75
9 12 83 111 180 11 12 95 125 72
9 13 – – 177 11 13 – –69
914 84 112 174 11 14 96 126 66
9 15 85 113 171 11 15 97 127 63
9 16 – 62 168 11 16 – 120 60
9 17 86 114 165 11 17 98 128 57
9 18 – – 162 11 18 – – 54
10 1 – – 159 12 1 – –51
10 2 113 147 156 12 2 101 131 48
10 3 114 148 153 12 3 102 133 45
10 4 – 144 150 12 4 – 106 42
10 5 115 149 147 12 5 103 134 39
10 6 116 150 144 12 6 104 135 36
10 7 – – 141 12 7 – –33
10 8 117 152 138 12 8 105 136 30
10 9 118 154 135 12 9 106 137 27
10 10 – 168 132 12 10 – 151 24
10 11 119 155 129 12 11 107 138 21
10 12 122 158 126 12 12 108 139 18
10 13 – – 123 12 13 – –15
10 14 123 159 120 12 14 109 140 12
10 15 124 160 117 12 15 111 145 9
10 16 – 165 114 12 16 – 142 6
10 17 125 161 111 12 17 112 146 3
10 18 – – 108 12 18 – – 0
XC95216 In-System Programmable CPLD
3-54 June 1, 1996 (Version 1.0)
XC95216 Global, JTAG and Power Pins
Pin Type PQ160 HQ208
I/O/GCK1 33 44
I/O/GCK2 35 46
I/O/GCK3 42 55
I/O/GTS1 6 7
I/O/GTS2 8 9
I/O/GTS3 2 3
I/O/GTS4 4 5
I/O/GSR 159 206
TCK 75 98
TDI 71 94
TDO 136 176
TMS 73 96
VCCINT 5 V 10,46,94,157 11, 59, 124, 153, 204
VCCIO 3.3 V/5 V 1,41,61,81,121,141 1, 26, 53, 65, 79, 92, 105, 132,
157, 172, 181, 184
GND 20, 31, 40, 51, 70, 80, 99, 100,
110, 120, 127, 137, 160 2, 13, 24, 27, 42, 52, 68, 81, 93,
104, 108, 129, 130, 141, 156,
163, 177, 190, 207
No Connects – –
June 1, 1996 (Version 1.0) 3-55
Ordering Information
Component Availability
XC95216 - 10 PQ 208 C
Device Type
Speed Options
Temperature Range
Number of Pins
Package Type
Speed
-20
-15
-10
20 ns pin-to-pin delay
15 ns pin-to-pin delay
10 ns pin-to-pin delay
Packaging Options
PQ160
HQ208
160-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Power Quad Flat Pack (HQFP)
Temperature Options
C
I
Commercial 0°C to 70°C
Industrial -40°C to 85°C
X5088
Plastic
PLCC
44
XC95216
X5089
Pins
Type
Code PC44
-20
-15
-10
Plastic
VQFP
VQ44
84
Plastic
PLCC
PC84
Power
QFP
208
HQ208
Plastic
PQFP Plastic
TQFP
100
PQ100 TQ100
C(I)
C
C
Plastic
PQFP
160
PQ160
C(I)
C
C
XC95216 In-System Programmable CPLD
3-56 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-57
Features
• 10 ns pin-to-pin logic delays on all pins
•f
CNT to 111 MHz
• 288 macrocells with 6,400 usable gates
• Up to 292 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• PCI compliant ( -10 speed grade)
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in a 208-pin and 304-pin HQFP packages
Description
The XC95288 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of sixteen
36V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 10 ns. See Figure 1 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95288 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
XC95288 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC95288 In-System Programmable CPLD
3-58 June 1, 1996 (Version 1.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port 3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5924
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 16
36
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 1: XC95288 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks
June 1, 1996 (Version 1.0) 3-59
XC95288 I/O Pins
Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.
Consult factory for HQ304 pinouts.
Function
Block Macrocell HQ208 BScan
Order Notes Function
Block Macrocell HQ208 BScan
Order Notes
1 1 – 861 3 1 – 753
1 2 28 858 3 2 38 750
1 3 29 855 3 3 39 747
1 4 – 852 3 4 – 744
1 5 30 849 3 5 40 741
1 6 31 846 3 6 41 738
1 7 – 843 3 7 – 735
1 8 32 840 3 8 43 732
1 9 – 837 3 9 – 729
1 10 33 834 3 10 44 726 [1]
1 11 – 831 3 11 – 723
1 12 34 828 3 12 45 720
1 13 – 825 3 13 – 717
1 14 35 822 3 14 46 714 [1]
1 15 36 819 3 15 47 711
1 16 – 816 3 16 – 708
1 17 37 813 3 17 48 705
1 18 – 810 3 18 – 702
2 1 – 807 4 1 – 699
2 2 15 804 4 2 3 696 [1]
2 3 16 801 4 3 4 693
2 4 – 798 4 4 – 690
2 5 17 795 4 5 5 687 [1]
2 6 18 792 4 6 6 684
2 7 – 789 4 7 – 681
2 8 19 786 4 8 7 678 [1]
2 9 – 783 4 9 – 675
2 10 20 780 4 10 8 672
2 11 – 777 4 11 – 669
2 12 21 774 4 12 9 666 [1]
2 13 – 771 4 13 – 663
2 14 22 768 4 14 10 660
2 15 23 765 4 15 12 657
2 16 – 762 4 16 – 654
2 17 25 759 4 17 14 651
2 18 – 756 4 18 – 648
XC95288 In-System Programmable CPLD
3-60 June 1, 1996 (Version 1.0)
XC95288 I/O Pins (continued)
Note: [1] Global control pin
Function
Block Macrocell HQ208 BScan
Order Notes Function
Block Macrocell HQ208 BScan
Order Notes
5 1 – 645 7 1 – 537
5 2 49 642 7 2 62 534
5 3 50 639 7 3 63 531
5 4 – 636 7 4 – 528
5 5 51 633 7 5 64 525
5 6 54 630 7 6 66 522
5 7 – 627 7 7 – 519
5 8 55 624 [1] 7 8 67 516
5 9 – 621 7 9 – 513
5 10 56 618 7 10 69 510
5 11 – 615 7 11 – 507
5 12 57 612 7 12 70 504
5 13 – 609 7 13 – 501
5 14 58 606 7 14 71 498
5 15 60 603 7 15 72 495
5 16 – 600 7 16 – 492
5 17 61 597 7 17 73 489
5 18 – 594 7 18 – 486
6 1 – 591 8 1 – 483
6 2 197 588 8 2 186 480
6 3 198 585 8 3 187 477
6 4 – 582 8 4 – 474
6 5 199 579 8 5 188 471
6 6 200 576 8 6 189 468
6 7 – 573 8 7 – 465
6 8 201 570 8 8 191 462
6 9 – 567 8 9 – 459
6 10 202 564 8 10 192 456
6 11 – 561 8 11 – 453
6 12 203 558 8 12 193 450
6 13 – 555 8 13 – 447
6 14 205 552 8 14 194 444
6 15 206 549 [1] 8 15 195 441
6 16 – 546 8 16 – 438
6 17 208 543 8 17 196 435
6 18 – 540 8 18 – 432
June 1, 1996 (Version 1.0) 3-61
XC95288 I/O Pins (continued)
Function
Block Macrocell HQ208 BScan
Order Notes Function
Block Macrocell HQ208 BScan
Order Notes
9 1 – 429 11 1 – 321
9 2 74 426 11 2 87 318
9 3 75 423 11 3 88 315
9 4 – 420 11 4 – 312
9 5 76 417 11 5 89 309
9 6 77 414 11 6 90 306
9 7 – 411 11 7 – 303
9 8 78 408 11 8 91 300
9 9 – 405 11 9 – 297
9 10 80 402 11 10 95 294
9 11 82 399 11 11 97 291
9 12 83 396 11 12 99 288
9 13 – 393 11 13 – 285
9 14 84 390 11 14 100 282
9 15 85 387 11 15 101 279
9 16 – 384 11 16 – 276
9 17 86 381 11 17 102 273
9 18 – 378 11 18 – 270
10 1 – 375 12 1 – 267
10 2 170 372 12 2 158 264
10 3 171 369 12 3 159 261
10 4 – 366 12 4 – 258
10 5 173 363 12 5 160 255
10 6 174 360 12 6 161 252
10 7 – 357 12 7 – 249
10 8 175 354 12 8 162 246
10 9 – 351 12 9 – 243
10 10 178 348 12 10 164 240
10 11 179 345 12 11 165 237
10 12 180 342 12 12 166 234
10 13 – 339 12 13 – 231
10 14 182 336 12 14 167 228
10 15 183 333 12 15 168 225
10 16 – 330 12 16 – 222
10 17 185 327 12 17 169 219
10 18 – 324 12 18 – 216
XC95288 In-System Programmable CPLD
3-62 June 1, 1996 (Version 1.0)
XC95288 I/O Pins (continued)
Function
Block Macrocell HQ208 BScan
Order Notes Function
Block Macrocell HQ208 BScan
Order Notes
13 1 – 213 15 1 – 105
13 2 103 210 15 2 117 102
13 3 106 207 15 3 118 99
13 4 – 204 15 4 –96
13 5 107 201 15 5 119 93
13 6 109 198 15 6 120 90
13 7 – 195 15 7 –87
13 8 110 192 15 8 121 84
13 9 – 189 15 9 –81
13 10 111 186 15 10 122 78
13 11 112 183 15 11 123 75
13 12 113 180 15 12 125 72
13 13 – 177 15 13 –69
13 14 114 174 15 14 126 66
13 15 115 171 15 15 127 63
13 16 – 168 15 16 –60
13 17 116 165 15 17 128 57
13 18 – 162 15 18 – 54
14 1 – 159 16 1 –51
14 2 144 156 16 2 131 48
14 3 145 153 16 3 133 45
14 4 – 150 16 4 –42
14 5 146 147 16 5 134 39
14 6 147 144 16 6 135 36
14 7 – 141 16 7 –33
14 8 148 138 16 8 136 30
14 9 – 135 16 9 –27
14 10 149 132 16 10 137 24
14 11 150 129 16 11 138 21
14 12 151 126 16 12 139 18
14 13 – 123 16 13 –15
14 14 152 120 16 14 140 12
14 15 154 117 16 15 142 9
14 16 – 114 16 16 –6
14 17 155 111 16 17 143 3
14 18 – 108 16 18 – 0
June 1, 1996 (Version 1.0) 3-63
XC95288 Global, JTAG and Power Pins
Pin Type HQ208
I/O/GCK1 44
I/O/GCK2 46
I/O/GCK3 55
I/O/GTS1 7
I/O/GTS2 9
I/O/GTS3 3
I/O/GTS4 5
I/O/GSR 206
TCK 98
TDI 94
TDO 176
TMS 96
VCCINT 5 V 11,59,124,153,204
VCCIO 3.3 V/5 V 1,26,53,65,79,92,105,
132,157,172,181,184
GND 2,13,24,27,42,52,68,81,
93,104,108,129,130,
141,156,163,177,
190,207
No Connects –
XC95288 In-System Programmable CPLD
3-64 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-65
Features
• 10 ns pin-to-pin logic delays on all pins
•f
CNT to 111 MHz
• 432 macrocells with 9,600 usable gates
• Up to 232 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in a 304-pin HQFP package
Description
The XC95432 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of twenty-
four 36V18 Function Blocks, providing 9,600 usable gates
with propagation delays of 10 ns.
XC95432 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC95432 In-System Programmable CPLD
3-66 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3-67
Features
• 12 ns pin-to-pin logic delays on all pins
•f
CNT to 100 MHz
• 576 macrocells with 12,800 usable gates
• Up to 232 user I/O pins
• 5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
• Advanced 0.6 µm CMOS 5V FastFLASH technology
• Available in a 304-pin HQFP package
Description
The XC95576 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is compr ised of thirty-
two 36V18 Function Blocks, providing 12,800 usable gates
with propagation delays of 12 ns.
XC95576 In-System
Programmable CPLD
June 1, 1996 (Version 1.0) Advance Product Specification
XC95576 In-System Programmable CPLD
3-68 June 1, 1996 (Version 1.0)
3-69
XC7300 CMOS CPLD Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.3 V or 5 V Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Power-On Characteristics/Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Erasure Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
High-Volume Production Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
XACTstep Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
XC7318 18-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
Fast Function Block (FFB) External AC Characteristics 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86
XC7318 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
XC7336/XC7336Q 36-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
Fast Function Block (FFB) External AC Characteristics 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
XC7336 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97
XC7354 54-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
XC7300 Series Table of Contents
XC7300 Series Table of Contents
3-70
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104
XC7354 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
XC7372 72-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114
XC73108 108-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120
XC73108 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123
XC73144 144-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128
Fast Function Block (FFB) External AC Characteristics3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128
High-Density Function Block (FB) External AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129
Fast Function Block (FFB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129
High-Density Function Block (FB) Internal AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
I/O Block External AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130
Internal AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131
XC73144 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134
XC7300 Characterization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135
June 1, 1996 (Version 1.0) 3-71
Features
• High-performance Complex Programmable Logic
Devices (CPLDs)
- 5 / 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 167 MHz maximum clock frequency
• 100% PCI compliant
• High-drive 24 mA output
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 43 to 61 MHz 18-bit accumulators
• Multiple independent clocks
• Each input programmable as direct, latched, or
registered
• Power management options
• Multiple security bits for design protection
• Supported by industry standard design and verification
tools
• Advanced Dual-Block architecture
- Fast Function Blocks
- High-Density Function Blocks
(XC7354, XC7372, XC73108, XC73144)
• 0.8 µ CMOS EPROM technology
Description
The XC7300 family employs a unique Dual-Block architec-
ture that provides high speed operations via Fast Function
Blocks and/or high density capability via High Density
Function Blocks.
Fast Function Blocks (FFBs) provide fast, pin-to-pin speed
and logic throughput for critical decoding and ultra-fast
state machine applications. High-Density Function Blocks
(FBs) provide maximum logic density and system-le v el fea-
tures to implement complex functions with predictable tim-
ing for adders and accumulators, wide functions and state
machines requiring large numbers of product terms, and
other forms of complex logic. See Figure 1.
In addition, the XC7300 architecture employs the Universal
Interconnect Matrix (UIM) which guarantees 100% inter-
connect of all internal functions. This interconnect scheme
provides constant, short interconnect delays for all routing
paths through the UIM. Constant interconnect delays sim-
plify device timing and guarantee design performance,
regardless of logic placement within the chip.
The UIM provides an intrinsic wire-AND capability called
SMARTswitch. Transferring functions into the UIM con-
serves macrocell logic. This increases the total logic capac-
ity of the device. The wire-AND capability also significantly
increases the signal fan-in of each function b loc k. All Xilinx-
supported CPLD design tools automatically implement
SMARTswitch.
XC7300 CMOS CPLD Family
June 1, 1996 (Version 1.0) Product Specification
The XC7300 Family
XC7318 XC7336 XC7354 XC7372 XC73108 XC73144
Typical 22V10 Equivalent 1.5 – 2 3 – 4 6 8 12 16
Number of Macrocells 18 36 54 72 108 144
Number of Function Blocks 24681216
Number of Flip-Flops 18 36 108 126 198 276
Number of Fast Inputs 12 12 12 12 12 12
Number of Signal Pins 38 38 58 84 120 156
XC7300 CMOS CPLD Family
3-72 June 1, 1996 (Version 1.0)
All XC7300 Dual-Block CPLDs include programmable
power management features to specify high-performance
or low-power operation on an individual macrocell-by-mac-
rocell basis. Unused macrocells are automatically turned
off to minimize power dissipation. Designers can operate
speed-critical paths at maximum performance, while non-
critical paths dissipate less power.
Fast Function Blocks
The FFB has 24 inputs that can be individually selected
from the UIM, 12 fast input pins , or the nine macrocell f eed-
backs from the FFB. The prog rammable AND arr ay in each
FFB generates 45 product terms to drive the nine macro-
cells in each FFB. Each macrocell can be configured for
registered or combinatorial logic. See Figure 2.
Five product terms from the programmable AND array are
allocated to each macrocell. Four of these product terms
are ORed together and may be optionally inverted before
driving the input of a programmable D-type flip-flop. The
fifth product term driv es the asynchronous active-High pro-
grammab le Reset or Set Input to the macrocell flip-flop . The
flip-flop can be configured as a D-type or Toggle flip-flop, or
transparent for combinatorial outputs.
Two FFB macrocell differences exist between the XC7318/
XC7336/XC73144 and the XC7354/XC7372/XC73108.
In the XC7318, XC7336 and XC73144, five product terms
from the programmable AND array are allocated to each
macrocell. Four of these product terms are OR’d together
and may be optionally inverted before driving the input of a
programmab le D-type flip-flop. The fifth product term drives
the asynchronous active High programmable Set or Reset
input to the macrocell flip-flop. The flip-flop can be config-
ured as a D-type or Toggle flip-flop, or transparent for com-
binatorial outputs. See Figure 2.
In the XC7354, XC7372 and XC73108, five product terms
from the programmable AND array are allocated to each
macrocell. Four of these product terms are OR’d together,
inverted and drive the input of a programmable D-type flip-
flop. The fifth product term drives the asynchronous active
High programmable Set input to the macrocell flip-flop. The
flip-flop can be configured as a D-type flip-flop or transpar-
ent for combinatorial outputs. See Figure 3.
The programmable clock source is one of two global Fast-
Clock signals (FCLK0 or FCLK1) that are distributed with
short delay and minimal skew over the entire chip.
The FFB macrocells drive chip outputs directly through 3-
state output buffers. Each output buffer can be individually
controlled by one of two dedicated Fast Output Enable
inputs or permanently enabled or disabled. The macrocell
output can also be routed back as an input to the FFB and
the UIM.
Each FFB output is capable of sinking 24 mA when
VCCIO = 5 volts. These include all outputs on the XC7318
and XC7336 devices and all Fast Outputs (FOs) on the
XC7354, XC7372, XC73108, and XC73144 devices.
Unlike other I/Os, the FFB inputs do not have an input reg-
ister.
Input
Output FFB
I/O
Block
FB
FB
UIM
FB
FB
I/O
Block
FFB Output
X3204
Figure 1: XC7300 Device Block Diagram
June 1, 1996 (Version 1.0) 3-73
I/O
Pin
OE Control
Sum-of-Products to
Succeeding Macrocell
5
Q
D/T
Fast
Clocks
0 1 1 of 9 Macrocells
Feedback
to UIM
24
Inputs from
UIM
AND Array
5 Private
P-Terms per
Macrocell
X5725
Sum-of-Products
from
Previous
Macrocell
P-Term
Assignment
Control
12 from Fast
Input Pins 12
9
9 from FFB
Macrocell
Feedback
S/R
3
0
1
Register
Transparent
Control
Output
Polarity
2 Global
Fast OE 2
Pin Feedback
to UIM
Input-Pad
Register/Latch
(optional)
(XC73144 only)
Figure 2: Fast Function Block and Macrocell Schematic for the XC7318, XC7336, and XC73144
Pin
OE Control
Sum-of-Products to
Succeeding Macrocell
5
Q
D
Fast
Clocks
0 1 1 of 9 Macrocells
Feedback
to UIM
24
Inputs from
UIM
AND Array
5 Private
P-Terms per
Macrocell
X5761
Sum-of-Products
from
Previous
Macrocell
P-Term
Assignment
Control
12 from Fast
Input Pins 12
9
9 from FFB
Macrocell
Feedback
S
3
0
1
Register
Transparent
Control
2 Global
Fast OE 2
Pin Feedback
to UIM (XC7354 Only)
Input-Pad
Register/Latch
(optional)
(XC7354 only)
IOL = 24 mA
Figure 3: Fast Function Block and Macrocell Schematic for the XC7354, XC7372, and XC73108
XC7300 CMOS CPLD Family
3-74 June 1, 1996 (Version 1.0)
Product T erm Assignment
Each macrocell sum-of-product OR gates can be expanded
using the FFB product term assignment scheme. Product
term assignment transfers product terms in increments of
four product terms from one macrocell to the neighboring
macrocell (Figure 4). Complex logic functions requiring up
to 36 product terms can be implemented using all nine
macrocells within the FFB. When product terms are
assigned to adjacent macrocells, the product term normally
dedicated to the Set or Reset function becomes the input to
the macrocell register.
High-Density Function Blocks
The XC7354, XC7372, XC73108 and XC73144 devices
contain multiple, High-Density FBs linked though the UIM.
Each FB contains nine macrocells. Each macrocell can be
configured for either registered or combinatorial logic. A
detailed block diagram of the FB is shown in Figure 5.
Each FB receives 21 signals and their complements from
the UIM and an additional three inputs from the Fast Input
(FI) pins.
Shared and Private Product Terms
Each macrocell contains five priv ate product terms that can
be used as the primary inputs for combinatorial functions
implemented in the Arithmetic Logic Unit (ALU), or as indi-
vidual Reset, Set, Output-Enable , and Clock logic functions
for the flip-flop. Each FB also provides an additional 12
shared product terms, which are uncommitted product
terms availab le for an y of the nine macrocells within the FB.
Four priv ate product terms can be ORed together with up to
four shared product terms to drive the D1 input to the ALU.
The D2 input is driven by the OR of the fifth priv ate product
term and up to eight of the remaining shared product terms.
The shared product terms add no logic delay, and each
shared product term can be connected to one or all nine
macrocells in the FB.
Arithmetic Logic Unit
The functional versatility of each macrocell in the FB is
enhanced through additional gating and control functions
available in the ALU. A detailed block diagram of the
XC7300 ALU is shown in Figure 6.
The ALU has two programmable modes;
logic
and
arith-
metic
. In logic mode, the ALU functions as a 2-input func-
tion generator using a 4-bit look-up table that can be
programmed to generate any Boolean function of its D1
and D2 inputs as illustrated in Table 1.
The function generator can OR its inputs, widening the OR
function to a maximum of 17 inputs. It can AND them, which
means that one sum-of-products can be used to mask the
other. It can also XOR them, toggling the flip-flop or com-
paring the two sums of products. Either or both of the sum-
of-product inputs to the ALU can be inverted, and either or
both can be ignored.
X5220
From Previous
Macrocell Single-Product-
Term Assignment
Eight-Product-
Term Assignment
4D/T Q
S/R
4
D/T Q
Global
Clocks
Output
Polarity
Output
Polarity
MCN
MCN+1
Figure 4: Fast Function Block Product Term Assignment
June 1, 1996 (Version 1.0) 3-75
Table 1: Function Generator Logic Operations Therefore, the ALU can implement one additional layer of
logic without any speed penalty.
In arithmetic mode, the ALU block can be programmed to
generate the arithmetic sum or difference of the D1 and D2
inputs. Combined with the carry input from the next lower
macrocell, the ALU operates as a 1-bit full adder generating
a carry output to the next higher macrocell. The carry chain
propagates between adjacent macrocells and also crosses
the boundaries between FBs. This dedicated carry chain
overcomes the inherent speed and density problems of the
traditional CPLD architecture when trying to perform arith-
metic functions.
Carry Lookahead
Each FB provides a carry lookahead generator capable of
anticipating the carry across all nine macrocells. The carr y
lookahead generator reduces the ripple-carry dela y of wide
arithmetic functions such as add, subtract, and magnitude
compare to that of the first nine bits, plus the carry looka-
head delay of the higher-order FBs.
Macrocell Flip-Flop
The ALU block output drives the input of a programmable
D-type flip-flop. The flip-flop is triggered by the rising edge
of the clock input, but it can be configured as transparent,
I/O 
(see fig. 7)
Clock
Select Register
Trasparent
Control
Input-Pad
Register/Latch
(optional)
Pin
Feedback
Polarity
Local 
Feedback
OE Control
Global
Fast OE
Arithmetic 
Carry-Out to Next 
Macrocell
Shift-In
from Previous MC
Shift-Out
to Next MC
To 8 More
Macrocells
* OE is forced high when P-term is not used
RESET
SET
OE*
CLOCK
5
ALU
D1
D2
C
in
C
out
F
R
S
Q
D
MUX
Fast
Clocks
0 1
Arithmetic Carry-In from
Previous Macrocell
1 of 9 Macrocells
Feedback
Enable
Override
Feedback to UIM
Input to UIM
84
21
Inputs
from
UIM
3
from
Fast
Input
Pins
(FI)
AND Array
12 Sharable
P-Terms per
Function Block
5 Private
P-Terms per
Macrocell
X5485
Figure 5: High-Density Function Block and Macrocell Schematic
Function
D1:+: D2 D1:+: D2
D1 * D2 D1 * D2
D1 + D2 D1 + D2
D1 D2
D1 D2
D1 * D2 D1 * D2
D1 + D2 D1 + D2
X3206
Carry Input
D1
D2
Function
Generator To Macrocell
Flip-Flop
D1
Sum-of-
Products
D2
Sum-of-
Products
Arithmetic
Carry Control
Carry Output
0
1
Arithmetic Logic Unit (ALU)
Figure 6: ALU Schematic
XC7300 CMOS CPLD Family
3-76 June 1, 1996 (Version 1.0)
making the Q output identical to the D input, independent of
the clock, or as a conventional flip-flop.
The macrocell clock source is programmable and can be
one of the private product terms or one of two global Fast-
CLK signals (FCLK0 and FCLK1). Global FastCLK signals
are distributed to every macrocell flip-flop with shor t delay
and minimal skew.
The asynchronous Set and Reset product terms override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set.
In addition to driving the chip output buffer, the macrocell
output is routed back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output buff er and/or the feedback to the UIM.
If it is configured to control UIM feedback, the Output
Enable product term forces the UIM feedback line High
when the macrocell output is disabled.
Universal Interconnect Matrix
The UIM receives inputs from each macrocell output, I/O
pin, and dedicated input pin. Acting as fully connected
crossbar switch, the UIM generates 21 output signals to
each FB and 24 output signals to each FFB.
Each UIM input can be connected to any UIM output. The
UIM delay is constant, regardless of the routing distance,
fan-out, or fan-in.
When multiple UIM inputs are connected to the same out-
put, their wire-AND is formed by using internally available
inversions. This AND logic can also be used to implement
wide NAND, OR or NOR functions. This offers an additional
level of logic without any speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Programming several such macrocell outputs onto the
same UIM output emulates a 3-state bus line. If one of the
macrocell outputs is enabled, the UIM output assumes the
enabled output’s level.
Input/Output Blocks
Macrocells drive chip outputs directly through 3-state out-
put buffers, each individually controlled by the Output
Enable product term mentioned above. The macrocell out-
put can be inverted. An additional configuration option
allows the output to be disabled permanently. Two dedi-
cated FastOE inputs can also be configured to control any
of the chip outputs instead of, or in conjunction with, the
individual Output Enable product term. See Figure 7.
Feedback
to UIM
Macrocell
From FB
Macrocell
Register
From FB
Macrocell
Register
Fast OE0
I/O, FCLK/O, CKEN/O
and FOE/O
Pins Only
Q
D
CLK
Q
D
EN
FastCLK1
FastCLK2
To UIM
To Function Block
AND-Array (on
Fast Input
Pins Only)
Input and
I/O Pins Only
Input
Polarity
Output
Polarity
Pin
Driver
MUX
MUX
Global
Select
X5463
FastCLK0
CKEN0
CKEN1
Q
D
CLK
EN
Fast OE1
I/O Pin
Figure 7: Input/Output Schematic (except XC7318/XC7336 which do not include I/O flip-flops)
June 1, 1996 (Version 1.0) 3-77
Output buffers, except those connected to FFBs, can sink
12 mA when VCCIO = 5 V. FFB outputs can sink 24 mA
when VCCIO = 5 V.
Each signal input to the chip is connected to a programma-
ble input structure that can be configured as direct, latched,
or registered. The latch and flip-flop can use one of two
FastCLK signals as latch enab le or cloc k. The two FastCLK
signals are FCLK0 and a global choice of either FCLK1 or
FCLK2. Latches are transparent when FastCLK is High,
and flip-flops clock on the rising edge of FastCLK. The flip-
flop includes an active-low clock enable, which when High,
holds the present state of the flip-flop and inhibits response
to the input signal. The clock enable source is one of two
global Clock Enable signals (CE0 and CE1). An additional
configuration option is polarity inversion for each input sig-
nal.
3.3 V or 5 V Interface Configuration
XC7300 devices can be used in systems with two different
supply voltages: 3.3 V and 5 V. Each XC7300 device has
separate VCC connections to the internal logic and input
buff ers (VCCINT) and to the I/O drivers (VCCIO). VCCINT must
always be connected to a nominal 5 V supply, while VCCIO
may be connected to either 3.3 V or 5 V, depending on the
output interface requirement.
When VCCIO is connected to 5 V, the input thresholds are
TTL levels, compatible with 3.3 V and 5 V logic. The output
High levels are also TTL compatible. When VCCIO is con-
nected to 3.3 V, the input thresholds are still TTL le v els, and
the outputs pull up to the 3.3 V r ail. This makes the XC7300
family ideal for interfacing directly to 3.3 V components. In
addition, the output structure is designed so the I/O can
also safely interface to a mixed 3.3 V and 5 V bus.
Power-On Characteristics/Master
Reset
Each XC7300 device undergoes a short internal
initialization sequence upon device powerup. During this
time (tRESET), the outputs remain 3-stated while the device
is configured from its internal EPROM array and all
registers are initialized. If the MR pin is tied to VCCINT, the
initialization sequence is completely transparent to the user
and is completed in tRESET after VCCINT has reached 4.75
V. If MR is held low while the device is powering up, the
internal initialization sequence begins and outputs will
remain 3-stated until the sequence is complete and MR is
brought High. VCC rise must be monotonic to ensure the
initialization sequence is performed correctly.
For additional flexibility, the MR pin is provided so the
device can be reinitialized after power is applied. On the
falling edge of MR , all outputs become 3-stated and the ini-
tialization sequence begins. The outputs remain 3-stated
until the internal initialization sequence is complete and MR
is brought High. The minimum MR pulse with is tWMR. If MR
is brought high after tWMR, but before tRESET, the outputs
will become active after tRESET. It is essential that the MR
pin remain static during power on reset (tRESET).
During the initialization sequence, all input registers or
latches are preloaded High and all FB and FFB macrocell
registers are preloaded to a known state. For FFB macro-
cell registers where the Set/Reset product term is defined,
the preload is accomplished by asserting the product ter m
shor tly before the end of the initialization sequence. When
the Set/Reset product term is configured as Reset, the reg-
ister preload value is Low. When the Set/Reset product
term is configured as Set, the register preload value is
High. For FFB macrocell registers where the Set/Reset
product term is not used, the register preload value is High.
For FB macrocell registers, the preload value is defined by
a separate preload configuration bit, independent of the Set
and Reset product terms. The value of this preload config-
uration bit may be determined by the user. If unspecified,
the register preload value is Low.
Power Management
The XC7300 family f eatures a po wer-management scheme
permitting non-speed-cr itical paths of a design to be oper-
ated at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a small
portion is speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the beha vioral
description. To further reduce power dissipation, unused
FBs are turned off and unused macrocells in used FBs are
configured for low power operation.
Erasure Characteristics
In windowed pac kages, the EPROM arr ay can be erased b y
exposure to UV light with wavelengths of approximately
4000 Å. The recommended erasure time is appro ximately 1
hr . when the device is placed within 1 in. of an UV lamp with
12,000 µW/cm2 power rating. To prevent unintentional
exposure, place opaque labels over the device window.
When the device is exposed to high intensity UV light for
much longer periods, permanent damage can occur. The
maximum integrated dose the XC7300 CPLDs can be
exposed to without damage is 7000 W • s/cm2, or approxi-
mately one week at 12,000 µW/cm2.
Design Recommendations
For proper oper ation, all unused input and I/O pins m ust be
connected to a valid logic level (High or Low). The recom-
mended decoupling for all VCC pins should total 1 µF using
high-speed (tantalum or ceramic) capacitors.
XC7300 CMOS CPLD Family
3-78 June 1, 1996 (Version 1.0)
Use electrostatic discharge (ESD) handling procedures
with the XC7300 CPLDs to prevent damage to the device
during programming, assembly, and test.
Design Security
Each member of the XC7300 family has a multibit security
system that controls access to the configuration pro-
grammed into the device. This security scheme uses multi-
ple EPROM bits at various locations within the EPROM
array to offer a higher degree of design security than other
EPROM and fused-based devices. Programmed data
within EPROM cells is invisible–even when examined
under a microscope–and cannot be selectively er ased. The
EPROM security bits, and the device configuration data,
reset when the device is erased.
High-Volume Production
Programming
The XC7300 family is available as a factory programmed
product. For f actory programming procedures, contact your
local Xilinx representative.
XACT
step
Development System
The XC7300 CPLD family is fully supported by the Xilinx
XACT
step
development system. The designer can create
the design using ABEL, schematics, equations, VHDL or
other HDL languages in a variety of software front-end
tools. The XACT
step
development system can be used to
implement the design and generate a bitmap which can be
used to program the XC7300 devices.
Timing Model
Timing within the XC7300 family is accurately determined
using external timing parameters from the device data
sheet, a variety of CAE simulators , or with the timing model
shown in Figure 8.
The timing model is based on the fixed internal delays of
the XC7300 architecture which consists of four basic parts:
I/O Blocks , the UIM, FFBs and FBs. The timing model iden-
tifies the internal delay paths and their relationships to ac
characteristics. Using this model and the ac characteristics,
designers can calculate the timing information for a par tic-
ular device.
June 1, 1996 (Version 1.0) 3-79
Synchronous Switching Characteristics
tOUT
tOUT
tIN
tFOE
tFCLKI
tFSUI
tFCOI
tFPDI
tFHI
tFAOI
tSUI
tCOI
tPDI
tHI
tAOI
tSUIN
tHIN
tSUCEIN
tHCEIN
tCOIN
UIM
Delay
tUIM
tIN
FOE
I, I/O
CE
FAST
INPUT
FCLK
FFB Feedback
tFFD
FFB Logic
tFOGI P-Term
Assignment
tPTXI
P-Term OE
tOEI
P-Term Clock
tPCI
FB Logic
tLOGI
Carry Delay
tCARY8
High Density Function Block
High Density Function Block
X3208
Input Register
Figure 8: XC7300 Timing Model
X3494
tCWF tCWF
tSUIN
tSUCEIN tHIN
tHCEIN
tFCLKI
tCOIN tUIM
tIN tUIM
tLOGI
tFLOGI tSUI
tFSUI
tHI
tFHI
tCOI
tFCOI tOUT
tFOUT
FCLK Pin
Data/CE at Input
I/O Register
Input, I/O Register
to UIM
Fast Clock
Input Delay
Data at Input
I/O Pin
Data at Input
Register
Register to
Output Pin
XC7300 CMOS CPLD Family
3-80 June 1, 1996 (Version 1.0)
Combinational Switching Characteristics
Asynchronous Switching Characteristics
Input, I/O Pin
UIM Delay
Logic Delay
P-Term
Assignment
Delay
Transparent
Register
Delay
Output Buffer
tIN
tUIM
tLOGI
tFLOGI
tPTXI
tPDI
tFPDI
tOUT
tFOUT
X3339
Output Pin
X3580
tPCW tPCW
INPUT, I/O DELAY
UIM DELAY
CLOCK at
REGISTER
DATA from
LOGIC ARRAY
REGISTER to
UIM
REGISTER to
OUTPUT Pin
INPUT, I/O Pin
tIN
tUIM
tLOGI
tHI
tSUI
tCOI tUIM
tOUT
tAOI tUIM
tOUT
June 1, 1996 (Version 1.0) 3- 81
Features
• Ultra high-performance Complex Programmable Logic
Devices (CPLDs)
- 5 ns pin-to-pin speeds on all fast inputs
- Up to 167 MHz maximum clock frequency
• 100% PCI compliant
• High-drive 24 mA output
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• Multiple security bits for design protection
• Incorporates two PAL-like 24V9 Fast Function Blocks
• 0.8 µ CMOS EPROM technology
• Available in 44-pin PQFP and PLCC packages
General Description
The XC7318 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks interconnected by the 100%-
populated Universal Interconnect Matrix (UIM™). See
Figure 1 for the architecture o verview.
XC7318
18-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: XC7318 Architecture
12
AND
ARRAY
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
3
9
12
AND
ARRAY
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
3
9
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
29
30
33
34
35
36
37
38
39
UIM
I/FI/MR
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I
I
I
I
I
I
1
2
3
4
18
19
20
28
42
43
44
17
22
24
25
26
27
FOE1
9
FFB2
FFB1
17
11
9
PC44
PC44
39
40
41
42
12
13
14
22
36
37
38
11
16
18
19
20
21
PQ44 1
2
3
5
6
7
8
9
10
23
24
27
28
29
30
31
32
33
X5455
PQ44
FOE0
FCLK0
FCLK1
40
5
6
34
43
44
12
12
XC7318 18-Macrocell CMOS CPLD
3- 82 June 1, 1996 (Version 1.0)
Power Estimation
Figure 2 shows a typical power estimation for the XC7318
device, programmed as a 16-bit counter and operating at
the indicated clock frequency.
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
Figure 2: Typical ICC vs. Frequency for XC7318
X5693
Clock Frequency (MHz)
Typical ICC (mA)
Low Power
050 100
50
100
150
200
High Performance
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT
VCCIO Supply voltage relative to GND Commercial TA = 0oC to 70oC 4.75 5.25 V
VCCIO I/O supply voltage relative to GND 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50.0 ns
June 1, 1996 (Version 1.0) 3- 83
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as a 16-bit counter.
Power-up/Reset Timing Parameters
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 24 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 6.0 pF
CIN Input capacitance for global control pins
(FCLK0, FCLK1, FOE0, FOE1) VIN = GND
f = 1.0 MHz 8.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC2Supply current VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C90 Typ mA
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Figure 3: Global Reset Waveform
Output
tRESET
tWMR
MR
Hi-Z
X5349
XC7318 18-Macrocell CMOS CPLD
3- 84 June 1, 1996 (Version 1.0)
Fast Function Block (FFB) External AC Characteristics 1
Notes: 1. All appropriate ac specifications tested using Figure 5 as test load circuit.
2. Assumes four product terms per output.
3. Export Control Max. flip-flop toggle rate.
Symbol Parameter XC7318-5 XC7318-7 UnitsMin Max Min Max
tPD Fast input to output valid 25.0 7.5 ns
I/O or input to output valid 28.5 12.0 ns
tSU Fast input setup time before FCLK 4.5 5.0 ns
I/O or input setup time before FCLK 7.0 8.5 ns
tHFast, I/O or input hold time after FCLK 0 0 ns
tCO FCLK input to output valid 4.5 4.5 ns
tFOE FOE input to output valid 7.0 7.5 ns
tFOD FOE input to output disable 7.0 7.5 ns
fMAX Max count frequency 2, 3 167.0 125.0 MHz
tWLH Fast Clock pulse width (High or Low) 3.0 4.0 ns
Figure 4: Switching Waveform
tSU
tCO
tH
Fast Input
FCLK
Output
tFOD
tWH
FOE Pin
Output
tWL
FCLK
tSU
tCO
tH
Input or I/O
FCLK
Output X5695
tFOE
Figure 5: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3ns
VCCIO Level
5 V
3.3 V
VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
CL
35 pF
35 pF
X5222
R1
120 Ω
360 Ω
June 1, 1996 (Version 1.0) 3- 85
Timing Model
Timing within the XC7318 is accurately determined using
external timing parameters from the device data sheet,
using a variety of CAE simulators, or with the timing model
shown in Figure 6.
The timing model is based on the fixed internal delays of
the XC7318 architecture that consists of three basic par ts:
I/O Blocks, the UIM and Fast Function Blocks. The timing
model identifies the internal delay paths and their relation-
ships to ac characteristics. Using this model and the ac
characteristics, designers can easily calculate the timing
information for the XC7318.
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
Internal AC Characteristics
Figure 6: XC7318 Timing Model
tFOUT
tIN
tFOE
tFCLKI
tFSUI
tFCOI
tFPDI
tFHI
tFAOI
UIM
Delay
tUIM
tIN
FOE
I, I/O
FAST
INPUT
FCLK
FFB Feedback
tFFD
FFB Logic
tFLOGI P-Term
Assignment
tPTXI
Fast Function Block
X5221
Pin
Symbol Parameter XC7318-5 XC7318-7 Units
Min Max Min Max
tFLOGI FFB logic array delay 11.0 1.5 ns
tFLOGILP Low-power FFB logic array delay 12.0 3.5 ns
tFSUI FFB register setup time 2.5 1.5 ns
tFHI FFB register hold time 1.0 2.5 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 ns
tFAOI FFB register async. set delay 2.0 2.0 ns
tPTXI FFB p-term assignment delay 0.6 0.8 ns
tFFD FFB feedback delay 0.5 4.0 ns
Symbol Parameter XC7318-5 XC7318-7 Units
Min Max Min Max
tIN Input pad and buffer delay 1.5 2.5 ns
tFOUT FFB output buffer and pad delay 2.0 3.0 ns
tUIM Universal Interconnect Matrix delay 3.5 4.5 ns
tFCLKI Fast clock buffer delay 1.5 1.5 ns
XC7318 18-Macrocell CMOS CPLD
3- 86 June 1, 1996 (Version 1.0)
Combinational Switching Characteristics
Asynchronous Switching Characteristics
Input, I/O Pin
UIM Delay
Logic Delay
P-Term
Assignment
Delay
Transparent
Register
Delay
Output Buffer
tIN
tUIM
tLOGI
tFLOGI
tPTXI
tPDI
tFPDI
tOUT
tFOUT
X3339
Output Pin
X3580
tPCW tPCW
INPUT, I/O DELAY
UIM DELAY
CLOCK at
REGISTER
DATA from
LOGIC ARRAY
REGISTER to
UIM
REGISTER to
OUTPUT Pin
INPUT, I/O Pin
tIN
tUIM
tLOGI
tHI
tSUI
tCOI tUIM
tOUT
tAOI tUIM
tOUT
June 1, 1996 (Version 1.0) 3- 87
Synchronous Switching Characteristics
XC7318 Pinouts
PQ44 PC44 Input XC7318 Output PQ44 PC44 Input XC7318 Output
39 1 I/FI MR 17 23 GND
40 2 I/FI 18 24 I
41 3 I/FI 19 25 I
42 4 I/FI 20 26 I
43 5 FCLK0 21 27 I
44 6 FCLK1 22 28 I/FI
1 7 I/FO/FI MC1-1 23 29 I/FO MC2-9
2 8 I/FO MC1-2 24 30 I/FO MC2-8
3 9 I/FO MC1-3 25 31 GND
4 10 GND 26 32 VCCIO
5 11 I/FO MC1-4 27 33 I/FO MC2-7
6 12 I/FO MC1-5 28 34 I/FO MC2-6
7 13 I/FO MC1-6 29 35 I/FO MC2-5
8 14 I/FO MC1-7 30 36 I/FO MC2-4
9 15 I/FO MC1-8 31 37 I/FO MC2-3
10 16 I/FO MC1-9 32 38 I/FO MC2-2
11 17 I 33 39 FOE1/FO MC2-1
12 18 I/FI 34 40 FOE0
13 19 I/FI 35 41 VCCINT/VPP
14 20 I/FI 36 42 I/FI
15 21 VCCINT 37 43 I/FI
16 22 I 38 44 I/FI
X3494
tCWF tCWF
tSUIN
tSUCEIN tHIN
tHCEIN
tFCLKI
tCOIN tUIM
tIN tUIM
tLOGI
tFLOGI tSUI
tFSUI
tHI
tFHI
tCOI
tFCOI tOUT
tFOUT
FCLK Pin
Data/CE at Input
I/O Register
Input, I/O Register
to UIM
Fast Clock
Input Delay
Data at Input
I/O Pin
Data at Input
Register
Register to
Output Pin
XC7318 18-Macrocell CMOS CPLD
3- 88 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C
Pins 44
Type Plastic
PLCC Plastic
PQFP
Code PC44 PQ44
XC7318 –7 C C
–5 C C
XC7318 - 5 PC 44 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-7 7.5 ns pin-to-pin delay (commercial only)
-5 5 ns pin-to-pin delay (commercial only)
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier
PQ44 44-Pin Plastic Quad Flat Pack
Temperature Options
C Commercial 0oC to 70oC
June 1, 1996 (Version 1.0) 3- 89
Features
• Ultra high-performance Complex Programmable Logic
Devices (CPLDs)
- 5 ns pin-to-pin speeds on all fast inputs
- Up to 167 MHz maximum clock frequency
• New low power XC7336Q
• 100% PCI compliant
• High-drive 24 mA output
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• Multiple security bits for design protection
• Incorporates four PAL-like 24V9 Fast Function Blocks
• 0.8 µ CMOS EPROM technology
• Available in 44-pin VQFP, PQFP and PLCC/CLCC
packages
General Description
The XC7336 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of four PAL-like
24V9 Fast Function Blocks interconnected by the 100%-
populated Universal Interconnect Matrix (UIM™). See
Figure 1 for the architecture o verview.
The XC7336 is designed in 0.8 µ CMOS EPROM technol-
ogy, in speed grades ranging from 5 to 15 ns. The
XC7336Q is also av ailab le now, providing low er power con-
sumption in -10, -12 and -15 ns speed grades.
XC7336/XC7336Q
36-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: XC7336 Architecture
UIM
PC44
34
3
AND ARRAY
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
7
8
9
11
12
13
14
15
16
I/FO/FI
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
FFB1
9
9
12
19
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
FO/FOE1
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
AND ARRAY
3
FFB2
12
9
9
29
30
33
34
35
36
37
38
39
12
3
AND ARRAY
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
27
26
25
24
22
20
19
18
17
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO/FI
I/FO/FI
I/FO/FI
I/FO
FFB4
9
9
12
FO/FOE0
I/FO/FI
I/FO/FI
I/FO/FI/MR
I/FO/FI
I/FO/FI
I/FO/FI
FO/FCLK0
FO/FCLK1
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
3
FFB3
12
9
9
40
43
44
1
2
3
4
5
6
12
I/FI 4228 I/FI 15
PC44
X5452
12
12
12
12
12
12
PQ44
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
43
44
36
PQ44
1
2
3
5
6
7
8
9
10
21
20
19
18
16
14
13
12
11
22
XC7336/XC7336Q 36-Macrocell CMOS CPLD
3- 90 June 1, 1996 (Version 1.0)
Power Estimation
Figure 2 shows a typical power estimation for the XC7336
and the XC7336Q device, programmed as two 16-bit
counters and operating at the indicated clock frequency.
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
Figure 2: Typical ICC vs. Frequency for XC7336
X5085
Clock Frequency (MHz)
Typical ICC (mA)
050 100
50
100
150
200
High Performance
High Performance
Q devices
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +250 °C
Symbol Parameter Min Max Units
VCCINT
VCCIO
Supply voltage relative to GND Commercial TA = 0oC to 70oC 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40oC to 85oC 4.50 5.50 V
VCCIO I/O supply voltage relative to GND 3.0 3.60 V
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50 ns
June 1, 1996 (Version 1.0) 3- 91
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as two 16-bit counters.
Power-up/Reset Timing Parameters
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 24 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O
pins VIN = GND
f = 1.0 MHz 6.0 pF
CIN Input capacitance for global control
pins (FCLK0, FCLK1, FOE0, FOE1) VIN = GND
f = 1.0 MHz 8.0 pF
CIN Input capacitance for Fast Inputs VIN = GND
f = 1.0 MHz 12.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC2Supply current (Non Q) VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C
126 Typ mA
(Q) 55 Typ
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Figure 3: Global Reset Waveform
Output
tRESET
tWMR
MR
Hi-Z
X5349
XC7336/XC7336Q 36-Macrocell CMOS CPLD
3- 92 June 1, 1996 (Version 1.0)
Fast Function Block (FFB) External AC Characteristics 1
Notes: 1. All appropriate ac specifications tested using Figure 5 as test load circuit.
2. Assumes four product terms per output.
3. Export Control Max. flip-flop toggle rate.
Symbol Parameter XC7336-5 XC7336-7 XC7336-10 XC7336-12 XC7336-15 UnitsMin Max Min Max Min Max Min Max Min Max
tPD Fast input to output valid 2 5.0 7.5 10.0 12.0 15.0 ns
I/O or input to output valid 2 8.5 12.0 15.0 19.0 23.0 ns
tSU Fast input setup time before FCLK 4.5 5.0 5.0 6.0 7.0 ns
I/O or input setup time before FCLK 7.0 8.5 10.0 13.0 15.0 ns
tHFast, I/O or input hold time after FCLK 00000ns
t
CO FCLK input to output valid 4.5 4.5 8.0 9.0 12.0 ns
tFOE FOE input to output valid 7.0 7.5 10.0 12.0 15.0 ns
tFOD FOE input to output disable 7.0 7.5 10.0 12.0 15.0 ns
fMAX Max count frequency 2, 3 167.0 125.0 100.0 80.0 66.7 MHz
tWLH Fast Clock pulse width (High or Low) 3.0 4.0 5.0 5.5 6.0 ns
Symbol Parameter XC7336Q-10 XC7336Q-12 XC7336Q-15 UnitsMin Max Min Max Min Max
tPD Fast input to output valid 2 10.0 12.0 15.0 ns
I/O or input to output valid 2 15.0 19.0 23.0 ns
tSU Fast input setup time before FCLK 6.5 6.5 7.0 ns
I/O or input setup time before FCLK 11.5 13.5 15.0 ns
tHFast, I/O or input hold time after FCLK 0 0 0 ns
tCO FCLK input to output valid 6.5 8.5 12.0 ns
tFOE FOE input to output valid 10.0 12.0 15.0 ns
tFOD FOE input to output disable 10.0 12.0 15.0 ns
fMAX Max count frequency 2, 3 100.0 80.0 66.7 MHz
tWLH Fast Clock pulse width (High or Low) 5.0 5.5 6.0 ns
Figure 4: Switching Waveform
tSU
tCO
tH
Fast Input
FCLK
Output
tFOD
tWH
FOE Pin
Output
tWL
FCLK
tSU
tCO
tH
Input or I/O
FCLK
Output X5695
tFOE
June 1, 1996 (Version 1.0) 3- 93
Timing Model
Timing within the XC7336 is accurately determined using
external timing parameters from the device data sheet,
using a variety of CAE simulators, or with the timing model
shown in Figure 6.
The timing model is based on the fixed internal delays of
the XC7336 architecture that consists of three basic par ts:
I/O Blocks, the UIM and Fast Function Blocks. The timing
model identifies the internal delay paths and their relation-
ships to ac characteristics. Using this model and the ac
characteristics, designers can easily calculate the timing
information for the XC7336.
Figure 5: AC Load Circuit
Figure 6: XC7336 Timing Model
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3ns
VCCIO Level
5 V
3.3 V
VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
CL
35 pF
35 pF
X5222
R1
120 Ω
360 Ω
tFOUT
tIN
tFOE
tFCLKI
tFSUI
tFCOI
tFPDI
tFHI
tFAOI
UIM
Delay
tUIM
tIN
FOE
I, I/O
FAST
INPUT
FCLK
FFB Feedback
tFFD
FFB Logic
tFLOGI P-Term
Assignment
tPTXI
Fast Function Block
X5221
Pin
XC7336/XC7336Q 36-Macrocell CMOS CPLD
3- 94 June 1, 1996 (Version 1.0)
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Internal AC Characteristics
Symbol Parameter XC7336-5 XC7336-7 XC7336-10 XC7336-12 XC7336-15 UnitsMin Max Min Max Min Max Min Max Min Max
tFLOGI FFB logic array delay 11.0 1.5 1.5 2.0 2.0 ns
tFLOGILP Low-power FFB logic array delay 12.0 3.5 5.5 7.0 8.0 ns
tFSUI FFB register setup time 2.5 1.5 2.5 3.0 4.0 ns
tFHI FFB register hold time 1.0 2.5 2.5 3.0 3.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 0.5 1.0 1.0 ns
tFAOI FFB register async. set delay 2.0 2.0 2.5 3.0 4.0 ns
tPTXI FFB p-term assignment delay 0.6 0.8 1.0 1.2 1.5 ns
tFFD FFB feedback delay 0.5 4.0 5.0 6.5 8.0 ns
Symbol Parameter XC7336Q-10 XC7336Q-12 XC7336Q-15 UnitsMin Max Min Max Min Max
tFLOGI FFB logic array delay 13.0 3.0 2.0 ns
tFLOGILP Low-power FFB logic array delay 15.5 7.0 8.0 ns
tFSUI FFB register setup time 2.5 3.0 4.0 ns
tFHI FFB register hold time 2.5 3.0 3.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 1.0 1.0 ns
tFAOI FFB register async. set delay 2.5 3.0 4.0 ns
tPTXI FFB p-term assignment delay 1.0 1.2 1.5 ns
tFFD FFB feedback delay 5.0 6.5 8.0 ns
Symbol Parameter XC7336-5 XC7336-7 XC7336-10 XC7336-12 XC7336-15 UnitsMin Max Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 1.5 2.5 3.5 4.0 5.0 ns
tFOUT FFB output buffer and pad delay 2.0 3.0 4.5 5.0 7.0 ns
tUIM Universal Interconnect Matrix delay 3.5 4.5 5.0 7.0 8.0 ns
tFCLKI Fast clock buffer delay 1.5 1.5 2.5 3.0 4.0 ns
Symbol Parameter XC7336Q-10 XC7336Q-12 XC7336Q-15 UnitsMin Max Min Max Min Max
tIN Input pad and buffer delay 3.5 4.0 5.0 ns
tFOUT FFB output buffer and pad delay 3.0 4.5 7.0 ns
tUIM Universal Interconnect Matrix delay 5.0 7.0 8.0 ns
tFCLKI Fast clock buffer delay 2.5 3.0 4.0 ns
June 1, 1996 (Version 1.0) 3- 95
Combinational Switching Characteristics
Asynchronous Switching Characteristics
Input, I/O Pin
UIM Delay
Logic Delay
P-Term
Assignment
Delay
Transparent
Register
Delay
Output Buffer
tIN
tUIM
tLOGI
tFLOGI
tPTXI
tPDI
tFPDI
tOUT
tFOUT
X3339
Output Pin
X3580
tPCW tPCW
INPUT, I/O DELAY
UIM DELAY
CLOCK at
REGISTER
DATA from
LOGIC ARRAY
REGISTER to
UIM
REGISTER to
OUTPUT Pin
INPUT, I/O Pin
tIN
tUIM
tLOGI
tHI
tSUI
tCOI tUIM
tOUT
tAOI tUIM
tOUT
XC7336/XC7336Q 36-Macrocell CMOS CPLD
3- 96 June 1, 1996 (Version 1.0)
Synchronous Switching Characteristics
XC7336 Pinouts
VQ44/PQ44 PC44 Input XC7336 Output VQ44/PQ44 PC44 Input XC7336 Output
39 1 I/FO/FI MR MC3-6 17 23 GND
40 2 I/FO/FI MC3-5 18 24 I/FO MC4-4
41 3 I/FO/FI MC3-4 19 25 I/FO MC4-3
42 4 I/FO/FI MC3-3 20 26 I/FO MC4-2
43 5 FO/FCLK0 MC3-2 21 27 I/FO MC4-1
44 6 FO/FCLK1 MC3-1 22 28 I/FI
1 7 I/FO/FI MC1-1 23 29 I/FO MC2-9
2 8 I/FO MC1-2 24 30 I/FO MC2-8
3 9 I/FO MC1-3 25 31 GND
4 10 GND 26 32 VCCIO
511 I/FO MC1-4 27 33 I/FO MC2-7
6 12 I/FO MC1-5 28 34 I/FO MC2-6
7 13 I/FO MC1-6 29 35 I/FO MC2-5
8 14 I/FO MC1-7 30 36 I/FO MC2-4
9 15 I/FO MC1-8 31 37 I/FO MC2-3
10 16 I/FO MC1-9 32 38 I/FO MC2-2
11 17 I/FO MC4-9 33 39 FO/FOE1 MC2-1
12 18 I/FO/FI MC4-8 34 40 FO/FOE0 MC3-9
13 19 I/FO/FI MC4-7 35 41 VCCINT/VPP
14 20 I/FO/FI MC4-6 36 42 I/FI
15 21 VCCINT 37 43 I/FO/FI MC3-8
16 22 I/FO MC4-5 38 44 I/FO/FI MC3-7
X3494
tCWF tCWF
tSUIN
tSUCEIN tHIN
tHCEIN
tFCLKI
tCOIN tUIM
tIN tUIM
tLOGI
tFLOGI tSUI
tFSUI
tHI
tFHI
tCOI
tFCOI tOUT
tFOUT
FCLK Pin
Data/CE at Input
I/O Register
Input, I/O Register
to UIM
Fast Clock
Input Delay
Data at Input
I/O Pin
Data at Input
Register
Register to
Output Pin
June 1, 1996 (Version 1.0) 3- 97
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C
Pins 44
Type Plastic
PLCC Ceramic
CLCC Plastic
PQFP Plastic
VQFP
Code PC44 WC44 PQ44 VQ44
XC7336
–15 CI CI CI
–12 CI CI C
–10 CI CI C
–7CCC
–5CCC
XC7336Q –15 CI CI C C
–12 CI CI C C
–10CCCC
XC7336 Q - 5 PC 44 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Power Options
Q Low Power -10, -12, -15 speeds
Speed Options
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay (commercial only)
-5 5 ns pin-to-pin delay (commercial only)
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier
WC44 44-Pin Windowed Ceramic Leaded
Chip Carrier
PQ44 44-Pin Plastic Quad Flat Pack
VQ44 44-Pin Thin Quad Pack
Temperature Options
C Commercial0°C to 70°C
I Industrial–40°C to 85°C
Power Option
XC7336/XC7336Q 36-Macrocell CMOS CPLD
3- 98 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3- 99
Features
• High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
• 100% PCI compliant
• 18 outputs with 24 mA drive
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 61 MHz 18-bit accumulators
• Multiple independent clocks
• Up to 54 inputs programmable as direct, latched, or
registered
• Power management options
• Multiple security bits for design protection
• 54 macrocells with programmable I/O architecture
• Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 4 High-Density Function Blocks
• 0.8 µ CMOS EPROM technology
• Available in 44-pin and 68-pin PLCC and CLCC
packages
General Description
The XC7354 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and four High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIM™).
Power Management
The XC7354 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the beha vioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)=MCHP (3.0) + MCLP (2.6) +
MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical power calculation for the XC7354
device , programmed as three 16-bit counters and operating
at the indicated clock frequency.
XC7354
54-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: Typical ICC vs. Frequency for XC7354
X5286
Clock Frequency (MHz)
Typical ICC (mA)
Low Power
050 100
50
100
150
200
High Performance
XC7354 54-Macrocell CMOS CPLD
3- 100 June 1, 1996 (Version 1.0)
Figure 2: XC7354 Architecture
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
Serial Shift
Arithmetic Carry
MC4-9
MC4-8
MC4-7
MC4-6
MC4-5
MC4-4
MC4-3
MC4-2
MC4-1
AND ARRAY
2121
AND ARRAY
MC5-1
MC5-2
MC5-3
MC5-4
MC5-5
MC5-6
MC5-7
MC5-8
MC5-9
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB4FB5
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
AND ARRAY
3
3
2121
AND ARRAY AND ARRAY
MC6-1
MC6-2
MC6-3
MC6-4
MC6-5
MC6-6
MC6-7
MC6-8
MC6-9
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
Carry
Shift
Arithmetic
Serial
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/O/FI
I/O/FI
O/FCLK0
O/FCLK1
O/FCLK2
I/O/FI
I/O/FI
I/O/FI
I/O/FI
FB3
FFB2
FB6
FFB1
12
9
12
9
9 9
42
40
39
—
—
—
54
53
38
47
45
44
64
62
61
60
32
33
35
37
16
18
25
31
36
27
28
8
9
10
29
6
24
26
46
48
51
52
55
56
57
58
66
4
12
13
15
17
19
21
22
23
UIM
121212 6 6
68
1
2
3
5
11
67
65
43
I/FI
I/FI/MR
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
PC68
PC68
X5458
27
26
25
—
—
—
—
—
—
—
—
—
—
40
—
39
29
30
33
34
35
36
37
38
—
44
1
2
3
4
7
PC44
—
—
—
—
—
—
17
22
24
18
19
5
6
—
20
—
—
—
—
8
9
11
12
13
14
15
16
43
42
28
PC44
I/O/FI
I/O/FI
I/O/FI
O/FOE1
O/FOE0
O/CKEN1
O/CKEN0
18
18
24
18
June 1, 1996 (Version 1.0) 3- 101
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as three 16-bit counters.
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VCCIO I/O supply voltage relative to GND 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA (FO)
IOL = 12 mA (I/O)
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 8.0 pF
CIN Input capacitance for global control pins (FCLK0,
FCLK1, FCLK2, FOE0, FOE1) VIN = GND
f = 1.0 MHz 12.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC2Supply current (low power mode) VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C140 Typ mA
XC7354 54-Macrocell CMOS CPLD
3- 102 June 1, 1996 (Version 1.0)
Power-up/Reset Timing Parameters
Fast Function Block (FFB) External AC Characteristics3
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip-flop toggle rate.
High-Density Function Block (FB) External AC Characteristics
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15
Units
Min Max Min Max Min Max Min Max
fCF Max count frequency 1, 2, 4 125.0 100.0 80.0 66.7 MHz
tSUF Fast input setup time before FCLK ↑ 14.0 5.0 6.0 7.0 ns
tHF Fast input hold time after FCLK ↑0000ns
t
COF FCLK ↑ to output valid 5.5 8.0 9.0 12.0 ns
tPDFO Fast input to output valid 1, 2 7.5 10.0 12.0 15.0 ns
tPDFU I/O to output valid 1, 2 12.0 16.0 19.0 23.0 ns
tCWF Fast clock pulse width 4.0 5.0 5.5 6.0 ns
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15 UnitsMin Max Min Max Min Max Min Max
fCMax count frequency 1, 2 95.2 76.9 66.7 55.6 MHz
tSU I/O setup time before FCLK ↑ 1, 2 10.5 13.0 15.0 18.0 ns
tHI/O hold time after FCLK ↑0000ns
t
CO FCLK ↑ to output valid 7.0 10.0 12.0 15.0 ns
tPSU I/O setup time before p-term clock ↑ 24.0 6.0 7.0 9.0 ns
tPH I/O hold time after p-term clock ↑0000ns
t
PCO P-term clock ↑ to output valid 13.5 17.0 20.0 24.0 ns
tPD I/O to output valid 1, 2 16.5 22.0 27.0 32.0 ns
tCW Fast clock pulse width 4.0 5.0 5.5 6.0 ns
tPCW P-term clock pulse width 5.0 6.0 7.5 8.5 ns
June 1, 1996 (Version 1.0) 3- 103
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
High-Density Function Block (FB) Internal AC Characteristics
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15
Units
Min Max Min Max Min Max Min Max
tFLOGI FFB logic array delay 11.5 1.5 2.0 2.0 ns
tFLOGILP Low-power FFB logic array delay 13.5 5.5 7.0 8.0 ns
tFSUI FFB register setup time 1.5 2.5 3.0 4.0 ns
tFHI FFB register hold time 2.5 2.5 3.0 3.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 1.0 1.0 ns
tFAOI FFB register async. set delay 2.0 2.5 3.0 4.0 ns
tPTXI FFB p-term assignment delay 0.8 1.0 1.2 1.5 ns
tFFD FFB feedback delay 4.0 5.0 6.5 8.0 ns
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15 UnitsMin Max Min Max Min Max Min Max
tLOGI FB logic array delay 13.5 3.5 4.0 5.0 ns
tLOGILP Low power FB logic delay 17.0 7.5 9.0 11.0 ns
tSUI FB register setup time 1.5 2.5 3.0 4.0 ns
tHI FB register hold time 3.5 3.5 4.0 5.0 ns
tCOI FB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tPDI FB register pass through delay 1.5 2.5 4.0 4.0 ns
tAOI FB register async. set/reset delay 2.5 3.0 4.0 5.0 ns
tRA Set/reset recovery time before FCLK ↑13.5 16.0 18.0 21.0 ns
tHA Set/reset hold time after FCLK ↑0000ns
t
PRA Set/reset recovery time before p-term
clock ↑7.5 10.0 12.0 15.0 ns
tPHA Set/reset hold time after p-term clock ↑5.0 6.0 8.0 9.0 ns
tPCI FB p-term clock delay 1.0 0 0 0 ns
tOEI FB p-term output enable delay 3.0 4.0 5.0 7.0 ns
tCARY8 ALU carry delay within 1 FB 25.0 6.0 8.0 12.0 ns
tCARYFB Carry lookahead delay per additional
Functional Block 21.0 1.5 2.0 3.0 ns
XC7354 54-Macrocell CMOS CPLD
3- 104 June 1, 1996 (Version 1.0)
I/O Block External AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Internal AC Characteristics
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15 UnitsMin Max Min Max Min Max Min Max
fIN Max pipeline frequency (input register to FFB or
FB register) 195.2 76.9 66.7 55.6 MHz
tSUIN Input register/latch setup time before FCLK ↑4.0 5.0 6.0 7.0 ns
tHIN Input register/latch hold time after FCLK ↑0000ns
t
COIN FCLK ↑ to input register/latch output 2.5 3.5 4.0 5.0 ns
tCESUIN Clock enable setup time before FCLK ↑5.0 7.0 8.0 10.0 ns
tCEHIN Clock enable hold time after FCLK ↑0000ns
t
CWHIN FCLK pulse width high time 4.0 5.0 5.5 6.0 ns
tCWLIN FCLK pulse width low time 4.0 5.0 5.5 6.0 ns
Symbol Parameter
XC7354-7
(Com only) XC7354-10
(Com/Ind only) XC7354-12 XC7354-15 UnitsMin Max Min Max Min Max Min Max
tIN Input pad and buffer delay 2.5 3.5 4.0 5.0 ns
tFOUT FFB output buffer and pad delay 3.0 4.5 5.0 7.0 ns
tOUT FB output buffer and pad delay 4.5 6.5 8.0 10.0 ns
tUIM Universal Interconnect Matrix delay 4.5 6.0 7.0 8.0 ns
tFOE FOE input to output valid 7.5 10.0 12.0 15.0 ns
tFOD FOE input to output disable 7.5 10.0 12.0 15.0 ns
tFCLKI Fast clock buffer delay 1.5 2.5 3.0 4.0 ns
Figure 3: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
FO VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X3491
VCCIO
5.0 V
3.3 V
June 1, 1996 (Version 1.0) 3- 105
XC7354 Pinouts
PC68 PC44 Input XC7354 Output PC68 PC44 Input XC7354 Output
1 1 I/FI/ MR 35 – I/O MC5-3
2 2 I/FI 36 24 I/O/FI MC5-9
3 3 I/FI 37 – I/O MC5-4
4 – I/FO MC1-1 38 – I/O MC4-1
5 4 I/FI 39 25 I/O/FI MC4-7
6 – I/O/FI MC6-7 40 26 I/O/FI MC4-8
7 – GND 41 – GND
8 5 O/FCLK0 MC6-3 42 27 I/O/FI MC4-9
9 6 O/FCLK1 MC6-4 43 28 I/FI
10 – O/FCLK2 MC6-5 44 – I/O/FI MC3-7
11 7 I/FI 45 – I/O/FI MC3-8
12 8 I/FO MC1-2 46 29 I/FO MC2-9
13 9 I/FO MC1-3 47 – I/O/FI MC3-9
14 10 GND 48 30 I/FO MC2-8
15 11 I/FO MC1-4 49 31 GND
16 – I/O MC5-5 50 32 VCCIO
17 12 I/FO MC1-5 51 33 I/FO MC2-7
18 – I/O MC5-6 52 34 I/FO MC2-6
19 13 I/FO MC1-6 53 – I/O MC4-2
20 – VCCIO 54 – I/O MC4-3
21 14 I/FO MC1-7 55 35 I/FO MC2-5
22 15 I/FO MC1-8 56 36 I/FO MC2-4
23 16 I/FO MC1-9 57 37 I/FO MC2-3
24 – I/O/FI MC6-8 58 38 I/FO MC2-2
25 17 I/O/FI MC5-7 59 – VCCINT
26 – I/O/FI MC6-9 60 39 O/CKEN0 MC3-3
27 18 I/O/FI MC6-1 61 – O/CKEN1 MC3-4
28 19 I/O/FI MC6-2 62 40 O/FOE0 MC3-5
29 20 I/O/FI MC6-6 63 41 VCCINT/VPP
30 21 VCCINT 64 – O/FOE1 MC3-6
31 22 I/O/FI MC5-8 65 42 I/FI
32 – I/O MC5-1 66 – I/FO MC2-1
33 – I/O MC5-2 67 43 I/FI
34 23 GND 68 44 I/FI
XC7354 54-Macrocell CMOS CPLD
3- 106 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C M = Military = –55°C(A) to 125°C (C)
Pins 44 68
Type Plastic
PLCC Ceramic
CLCC Plastic
PLCC Ceramic
CLCC
Code PC44 WC44 PC68 WC68
XC7354
–15 CI CI CI CIM
–12 CI CI CI CIM
–10 CI CI CI CI
–7CCCC
XC7354 - 7 PC 68 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay (commercial and industrial only)
-7 7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier
WC44 44-Pin Windowed Ceramic Leaded Chip Carrier
PC68 68-Pin Plastic Leaded Chip Carrier
WC68 68-Pin Windowed Ceramic Leaded Chip Carrier
Temperature Options
C Commercial0°C to 70°C
I Industrial -40°C to 85°C
M Military -55°C (Ambient) to 125°C (Case)
June 1, 1996 (Version 1.0) 3- 107
Features
• High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
• 100% PCI compliant
• 18 outputs with 24 mA drive
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 61 MHz 18-bit accumulators
• Multiple independent clocks
• Up to 84 inputs programmable as direct, latched, or
registered
• Power management options
• Multiple security bits for design protection
• 72 macrocells with programmable I/O architecture
• Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 6 High-Density Function Blocks
• 0.8 µ CMOS EPROM technology
• A vailab le in 68-pin and 84-pin PLCC/CLCC and 100-pin
PQFP packages
General Description
The XC7372 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and six High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIM™). See Figure 2 for the architecture
overview.
Power Management
The XC7372 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the beha vioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)=MCHP (3.1) + MCLP (2.6) +
MC (0.012 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical power calculation for the XC7372
device, programmed as four 16-bit counters and operating
at the indicated clock frequency.
XC7372
72-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: Typical ICC vs. Frequency for XC7372
X5287
Clock Frequency (MHz)
Typical ICC (mA)
Low Power
050 100
100
200
300
400
High Performance
XC7372 72-Macrocell CMOS CPLD
3- 108 June 1, 1996 (Version 1.0)
Figure 2: XC7372 Architecture
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
63
62
61
58
51
52
59
57
56
MC4-9
MC4-8
MC4-7
MC4-6
MC4-5
MC4-4
MC4-3
MC4-2
MC4-1
AND ARRAY
2121
AND ARRAY
MC7-1
MC7-2
MC7-3
MC7-4
MC7-5
MC7-6
MC7-7
MC7-8
MC7-9
41
42
43
55
56
44
47
49
50
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB4FB7
FO
FO
FO
FO
FO
FO
FO
FO
FO
—
—
—
77
76
75
74
—
—
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
AND ARRAY
3
3
2121
AND ARRAY AND ARRAY
MC8-1
MC8-2
MC8-3
MC8-4
MC8-5
MC8-6
MC8-7
MC8-8
MC8-9
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
Carry
Shift
Arithmetic
Serial
26
30
31
32
34
35
37
38
39
36
45
24
25
29
48
61
21
27
FO
FO
FO
FO
FO
FO
FO
FO
FO
O
O
O/FCLK0
O/FCLK1
O/FCLK2
O
I/O/FI
I/O/FI
I/O/FI
FB3
FFB2
FB8
FFB1
12
9
12
9
9 9
65
66
67
68
69
70
71
72
—
121212 6 6
2
3
4
5
6
7
14
13
12
11
10
8
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
PC84
PQ100
I/O/FI
I/O/FI
I/OFI
O/FOE1
O/FOE0
O/CKEN1
O/CKEN0
O
O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
55
54
53
50
48
47
46
45
44
Serial Shift
Arithmetic Carry
MC5-9
MC5-8
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
AND ARRAY
2121
AND ARRAY
MC6-1
MC6-2
MC6-3
MC6-4
MC6-5
MC6-6
MC6-7
MC6-8
MC6-9
51
52
54
57
58
60
62
63
65
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB5FB6
—
—
—
—
—
—
48
47
46
—
—
—
—
62
61
60
—
—
51
52
53
54
55
56
57
58
—
2
3
4
5
6
—
PC68
X5464
45
44
43
42
40
39
38
37
36
—
—
—
—
—
21
22
23
24
—
—
8
9
10
—
—
—
—
—
11
12
13
15
16
17
18
19
68
67
66
65
64
—
PC68
25
26
27
28
29
31
32
33
35
21
27
21
27
UIM
89
88
87
84
73
74
85
83
80
94
82
9
6
5
3
1
81
75
91
92
93
95
96
97
98
99
4
16
17
18
19
20
22
PQ100
79
78
76
72
70
69
68
67
66
23
24
25
34
35
26
28
29
30
—
13
14
15
17
18
19
20
21
—
—
9
10
12
—
—
—
11
84
83
82
81
80
79
PC84
31
32
33
36
37
39
40
41
43
June 1, 1996 (Version 1.0) 3- 109
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as four 16-bit counters.
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT/
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VCCIO I/O supply voltage relative to GND 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA (FO)
IOL = 12 mA (I/O)
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 8.0 pF
CIN Input capacitance for global control pins
(FCLK0, FCLK1, FCLK2, FOE0, FOE1) VIN = GND
f = 1.0 MHz 12.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC2Supply current (low power mode) VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C187 Typ mA
XC7372 72-Macrocell CMOS CPLD
3- 110 June 1, 1996 (Version 1.0)
Power-up/Reset Timing Parameters
Fast Function Block (FFB) External AC Characteristics3
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip-flop toggle rate.
High-Density Function Block (FB) External AC Characteristics
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15
Units
Min Max Min Max Min Max Min Max
fCF Max count frequency 1, 2, 4 125.0 100.0 80.0 66.7 MHz
tSUF Fast input setup time before FCLK ↑ 14.0 5.0 6.0 7.0 ns
tHF Fast input hold time after FCLK ↑0000ns
t
COF FCLK ↑ to output valid 5.5 8.0 9.0 12.0 ns
tPDFO Fast input to output valid 1, 2 7.5 10.0 12.0 15.0 ns
tPDFU I/O to output valid 1, 2 14.0 17.0 20.0 24.0 ns
tCWF Fast clock pulse width (High or Low) 4.0 5.0 5.5 6.0 ns
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15 UnitsMin Max Min Max Min Max Min Max
fCMax count frequency 1, 2 95.2 71.4 62.5 52.6 MHz
tSU I/O setup time before FCLK ↑ 1, 2 12.5 14.0 16.0 19.0 ns
tHI/O hold time after FCLK ↑0000ns
t
CO FCLK ↑ to output valid 7.0 10.0 12.0 15.0 ns
tPSU I/O setup time before p-term clock ↑ 26.0 6.0 7.0 9.0 ns
tPH I/O hold time after p-term clock ↑0000ns
t
PCO P-term clock ↑ to output valid 13.5 18.0 21.0 25.0 ns
tPD I/O to output valid 1, 2 18.5 23.0 28.0 33.0 ns
tCW Fast clock pulse width 4.0 5.0 5.5 6.0 ns
tPCW P-term clock pulse width 5.0 6.0 7.5 8.5 ns
June 1, 1996 (Version 1.0) 3- 111
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
High-Density Function Block (FB) Internal AC Characteristics
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15
Units
Min Max Min Max Min Max Min Max
tFLOGI FFB logic array delay 11.5 1.5 2.0 2.0 ns
tFLOGILP Low-power FFB logic array delay 13.5 5.5 7.0 8.0 ns
tFSUI FFB register setup time 1.5 2.5 3.0 4.0 ns
tFHI FFB register hold time 2.5 2.5 3.0 3.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 1.0 1.0 ns
tFAOI FFB register async. set delay 2.0 2.5 3.0 4.0 ns
tPTXI FFB p-term assignment delay 0.8 1.0 1.2 1.5 ns
tFFD FFB feedback delay 4.0 5.0 6.5 8.0 ns
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15 UnitsMin Max Min Max Min Max Min Max
tLOGI FB logic array delay 13.5 3.5 4.0 5.0 ns
tLOGILP Low power FB logic delay 17.0 7.5 9.0 11.0 ns
tSUI FB register setup time 1.5 2.5 3.0 4.0 ns
tHI FB register hold time 3.5 3.5 4.0 5.0 ns
tCOI FB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tPDI FB register pass through delay 1.5 2.5 4.0 4.0 ns
tAOI FB register async. set/reset delay 2.5 3.0 4.0 5.0 ns
tRA Set/reset recovery time before FCLK ↑13.5 17.0 19.0 22.0 ns
tHA Set/reset hold time after FCLK ↑0000ns
t
PRA Set/reset recovery time before p-term
clock ↑7.5 10.0 12.0 15.0 ns
tPHA Set/reset hold time after p-term clock ↑5.0 6.0 8.0 9.0 ns
tPCI FB p-term clock delay 1.0 0 0 0 ns
tOEI FB p-term output enable delay 3.0 4.0 5.0 7.0 ns
tCARY8 ALU carry delay within 1 FB 25.0 6.0 8.0 12.0 ns
tCARYFB Carry lookahead delay per additional
Functional Block 21.0 1.5 2.0 3.0 ns
XC7372 72-Macrocell CMOS CPLD
3- 112 June 1, 1996 (Version 1.0)
I/O Block External AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Internal AC Characteristics
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15 UnitsMin Max Min Max Min Max Min Max
fIN Max pipeline frequency (input register to FFB or
FB register) 195.2 71.4 62.5 52.6 MHz
tSUIN Input register/latch setup time before FCLK ↑4.0 5.0 6.0 7.0 ns
tHIN Input register/latch hold time after FCLK ↑0000ns
t
COIN FCLK ↑ to input register/latch output 2.5 3.5 4.0 5.0 ns
tCESUIN Clock enable setup time before FCLK ↑5.0 7.0 8.0 10.0 ns
tCEHIN Clock enable hold time after FCLK ↑0000ns
t
CWHIN FCLK pulse width high time 4.0 5.0 5.5 6.0 ns
tCWLIN FCLK pulse width low time 4.0 5.0 5.5 6.0 ns
Symbol Parameter
XC7372-7
(Com only) XC7372-10
(Com/Ind only) XC7372-12 XC7372-15 UnitsMin Max Min Max Min Max Min Max
tIN Input pad and buffer delay 2.5 3.5 4.0 5.0 ns
tFOUT FFB output buffer and pad delay 3.0 4.5 5.0 7.0 ns
tOUT FB output buffer and pad delay 4.5 6.5 8.0 10.0 ns
tUIM Universal Interconnect Matrix delay 6.5 7.0 8.0 9.0 ns
tFOE FOE input to output valid 7.5 10.0 12.0 15.0 ns
tFOD FOE input to output disable 7.5 10.0 12.0 15.0 ns
tFCLKI Fast clock buffer delay 1.5 2.5 3.0 4.0 ns
Figure 3: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
FO VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X3491
VCCIO
5.0 V
3.3 V
June 1, 1996 (Version 1.0) 3- 113
XC7372 Pinouts
PQ100 PC84 PC68 Input XC7372 Output PQ100 PC84 PC68 Input XC7372 Output
15 1 1 MR 65 43 35 I/O/FI MC6-9
16 2 2 I/FI 66 44 36 I/O MC5-1
17 3 3 I/FI 67 45 37 I/O MC5-2
18 4 4 I/FI 68 46 38 I/O MC5-3
19 5 5 I/FI 69 47 39 I/O MC5-4
20 6 6 I/FI 70 48 40 I/O MC5-5
21 – – I/O/FI MC8-8 71 49 41 GND
22 7 – I/FI 72 50 42 I/O MC5-6
23 8 7 GND 73 51 – I/O MC4-5
24 9 8 O/FCLK0 MC8-3 74 52 – I/O MC4-4
25 10 9 O/FCLK1 MC8-4 75 – – O MC3-1
26 – – FO MC1-1 76 53 43 I/O/FI MC5-7
27 11 – I/O/FI MC8-9 77 – – GND
28 – – VCCIO 78 54 44 I/O/FI MC5-8
29 12 10 O/FCLK2 MC8-5 79 55 45 I/O/FI MC5-9
30 13 11 FO MC1-2 80 56 46 I/O MC4-1
31 14 12 FO MC1-3 81 – – O MC3-2
32 15 13 FO MC1-4 82 – – I/O/FI MC3-8
33 16 14 GND 83 57 47 I/O MC4-2
34 17 15 FO MC1-5 84 58 – I/O MC4-6
35 18 16 FO MC1-6 85 59 48 I/O MC4-3
36 – – O MC8-1 86 60 49 GND
37 19 17 FO MC1-7 87 61 – I/O/FI MC4-7
38 20 18 FO MC1-8 88 62 – I/O/FI MC4-8
39 21 19 FO MC1-9 89 63 – I/O/FI MC4-9
40 22 20 VCCIO 90 64 50 VCCIO
41 23 – I/O MC7-1 91 65 51 FO MC2-9
42 24 – I/O MC7-2 92 66 52 FO MC2-8
43 25 – I/O MC7-3 93 67 53 FO MC2-7
44 26 21 I/O MC7-6 94 – – I/O/FI MC3-9
45 – – O MC8-2 95 68 54 FO MC2-6
46 27 – GND 96 69 55 FO MC2-5
47 28 22 I/O/FI MC7-7 97 70 56 FO MC2-4
48 – – O MC8-6 98 71 57 FO MC2-3
49 29 23 I/O/FI MC7-8 99 72 58 FO MC2-2
50 30 24 I/O/FI MC7-9 100 73 59 VCCINT
51 31 25 I/O MC6-1 1 74 60 O/CKEN0 MC3-3
52 32 26 I/O MC6-2 2 – – GND
53 – – VCCIO 3 75 61 O/CKEN1 MC3-4
54 33 27 I/O MC6-3 4 – – FO MC2-1
55 34 – I/O MC7-4 5 76 62 O/FOE0 MC3-5
56 35 – I/O MC7-5 6 77 – O/FOE1 MC3-6
57 36 28 I/O MC6-4 7 78 63 VCCINT/
VPP
58 37 29 I/O MC6-5 8 79 – I/FI
59 38 30 VCCINT 9 – – I/O/FI MC3-7
60 39 31 I/O MC6-6 10 80 64 I/FI
61 – – I/O/FI MC8-7 11 81 65 I/FI
62 40 32 I/O/FI MC6-7 12 82 66 I/FI
63 41 33 I/O/FI MC6-8 13 83 67 I/FI
64 42 34 GND 14 84 68 I/FI
XC7372 72-Macrocell CMOS CPLD
3- 114 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C M = Military = –55°C(A) to 125°C (C)
Pins 68 84 100
Type Plastic
PLCC Ceramic
CLCC Plastic
PLCC Ceramic
CLCC Plastic
PQFP
Code PC68 WC68 PC84 WC84 PQ100
XC7372
–15 CI CIM CI CIM CI
–12 CI CIM CI CI CI
–10 CI CI CI CI CI
–7CCCCC
XC7372 - 7 PC 84 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay (commercial and industrial only)
-7 7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PC68 68-Pin Plastic Leaded Chip Carrier
WC68 68-Pin Windowed Ceramic Leaded Chip Carrier
PC84 84-Pin Plastic Leaded Chip Carrier
WC84 84-Pin Windowed Ceramic Leaded Chip Carrier
PQ100 100-Pin Plastic Quad Flat Pack
Temperature Options
C Commercial0°C to 70°C
I Industrial -40°C to 85°C
M Military -55°C (Ambient) to 125°C (Case)
June 1, 1996 (Version 1.0) 3- 115
Features
• High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
• 100% PCI compliant
• 18 outputs with 24 mA drive
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 56 MHz 18-bit accumulators
• Multiple independent clocks
• Up to 120 inputs programmable as direct, latched, or
registered
• Power management options
• Multiple security bits for design protection
• 108 macrocells with programmable I/O architecture
• Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 10 High-Density Function Blocks
• 0.8 µ CMOS EPROM technology
• Available in 84-pin and 84-pin PLCC/CLCC, 144-pin
PGA, 100-pin and 160-pin PQFP, and 225-pin BGA
packages
General Description
The XC73108 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and ten High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIM™).
Power Management
The XC73108 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the beha vioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)=MCHP (2.4) + MCLP (2.1) +
MC (0.015 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical pow er calculation for the XC73108
device , programmed as six 16-bit counters and operating at
the indicated clock frequency.
XC73108
108-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: Typical ICC vs. Frequency for XC73108
X5697
Clock Frequency (MHz)
Typical ICC (mA)
Low Power
050 100
100
200
300
400
High Performance
XC73108 108-Macrocell CMOS CPLD
3- 116 June 1, 1996 (Version 1.0)
Figure 2: XC73108 Architecture
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
Serial Shift
Arithmetic Carry
MC7-9
MC7-8
MC7-7
MC7-6
MC7-5
MC7-4
MC7-3
MC7-2
MC7-1
AND ARRAY
MC6-9
MC6-8
MC6-7
MC6-6
MC6-5
MC6-4
MC6-3
MC6-2
MC6-1
AND ARRAY
21
21
2121
AND ARRAY AND ARRAY
MC8-1
MC8-2
MC8-3
MC8-4
MC8-5
MC8-6
MC8-7
MC8-8
MC8-9
MC9-1
MC9-2
MC9-3
MC9-4
MC9-5
MC9-6
MC9-7
MC9-8
MC9-9
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB7
FB6
FB8
FB9
FO
FO
FO
FO
FO
FO
FO
FO
FO
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
AND ARRAY
3
3
2121
AND ARRAY AND ARRAY
MC12-1
MC12-2
MC12-3
MC12-4
MC12-5
MC12-6
MC12-7
MC12-8
MC12-9
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
Carry
Shift
Arithmetic
Serial
FO
FO
FO
FO
FO
FO
FO
FO
FO
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB3
FFB2
FB12
FFB1
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
O/FOE1
O/FOE0
O/CKEN1
O/CKEN0
O
O
MC5-9
MC5-8
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
AND ARRAY
MC4-9
MC4-8
MC4-7
MC4-6
MC4-5
MC4-4
MC4-3
MC4-2
MC4-1
AND ARRAY
21
21
2121
AND ARRAY AND ARRAY
MC10-1
MC10-2
MC10-3
MC10-4
MC10-5
MC10-6
MC10-7
MC10-8
MC10-9
MC11-1
MC11-2
MC11-3
MC11-4
MC11-5
MC11-6
MC11-7
MC11-8
MC11-9
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
O
O
O/FCLK0
O/FCLK1
O/FCLK2
O
I/O/FI
I/O/FI
I/O/FI
FB5
FB4
FB10
FB11
12
9
12
9
9 9
39
45
39
45
UIM
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
C8
A8
B8
C9
C14
D13
A10
B9
A13
B12
B13
B14
D14
E14
F13
G14
F15
G15
K15
L15
K13
L14
L13
P15
N13
R14
N11
R13
R11
R7
P10
N7
P6
R4
N5
R2
F1
G2
F2
C1
D2
C2
B2
E2
E3
A7
A6
B7
C6
B5
A3
C5
A2
B1
J1
K1
J2
K3
L2
N1
BG225/
PG144
R9
R10
P9
M14
N15
N10
R12
P12
P13
N12
P14
N14
M15
K14
J13
J15
H14
G13
N3
P4
P5
N6
P7
R6
P8
R8
N8
F14
E15
D15
E13
B15
A14
C11
A12
C13
B10
A5
A4
B4
B3
C3
C10
A11
B6
K2
L1
N2
M3
P3
P1
L3
M1
P2
H1
H2
G1
G3
E1
F3
BG225/
PG144
89
88
87
84
73
74
85
83
80
79
78
76
72
70
69
68
67
66
61
—
—
—
—
—
—
—
—
48
45
36
—
—
—
—
—
—
—
—
9
6
5
3
1
—
—
91
92
93
95
96
97
98
99
4
16
17
18
19
20
22
PQ100
41
42
43
55
56
44
47
49
50
51
52
54
57
58
60
62
63
65
—
—
—
—
—
—
—
—
75
—
—
—
—
—
—
81
82
94
—
—
24
25
29
—
—
21
27
26
30
31
32
34
35
37
38
39
14
13
12
11
10
8
PQ100
121212 6 6
62
63
64
86
88
68
71
73
75
77
79
82
90
92
95
97
98
101
105
107
109
112
114
123
125
128
116
130
147
151
153
155
158
129
133
145
25
27
33
35
42
34
32
29
37
36
44
47
49
54
56
58
59
60
19
18
17
15
13
11
PQ160
140
139
138
135
113
115
136
134
126
124
122
117
111
108
106
104
103
102
96
93
91
89
87
84
78
76
74
72
69
57
67
55
50
48
45
43
16
14
12
8
6
2
159
9
7
142
143
144
146
148
152
154
156
4
22
23
24
26
28
30
PQ160
X5454
63
62
61
58
51
52
59
57
56
55
54
53
50
48
47
46
45
44
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
77
76
75
74
—
—
65
66
67
68
69
70
71
72
—
2
3
4
5
6
7
PC84
23
24
25
34
35
26
28
29
30
31
32
33
36
37
39
40
41
43
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
10
12
—
—
—
11
—
13
14
15
17
18
19
20
21
84
83
82
81
80
79
PC84
June 1, 1996 (Version 1.0) 3- 117
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as six 16-bit counters.
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VCCIO I/O supply voltage relative to GND 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA (FO)
IOL = 12 mA (I/O)
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 8.0 pF
CIN Input capacitance for global control pins
(FCLK0, FCLK1, FCLK2, FOE0, FOE1) VIN = GND
f = 1.0 MHz 12.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 20.0 pF
ICC2Supply current (low power mode) VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C227 Typ mA
XC73108 108-Macrocell CMOS CPLD
3- 118 June 1, 1996 (Version 1.0)
Power-up/Reset Timing Parameters
Fast Function Block (FFB) External AC Characteristics3
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip-flop toggle rate.
High-Density Function Block (FB) External AC Characteristics
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
fCF Max count frequency 1, 2, 4 125.0 100.0 80.0 66.7 50.0 MHz
tSUF Fast input setup time before FCLK ↑ 14.0 5.0 6.0 7.0 10.0 ns
tHF Fast input hold time after FCLK ↑00000ns
t
COF FCLK ↑ to output valid 5.5 8.0 9.0 12.0 15.0 ns
tPDFO Fast input to output valid 1, 2 7.5 10.0 12.0 15.0 20.0 ns
tPDFU I/O to output valid 1, 2 13.5 19.0 22.0 27.0 35.0 ns
tCWF Fast clock pulse width (High or Low) 4.0 5.0 5.5 6.0 6.0 ns
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
fCMax count frequency 1, 2 83.3 62.5 55.6 45.5 35.7 MHz
tSU I/O setup time before FCLK ↑ 1, 2 12.0 16.0 18.0 22.0 28.0 ns
tHI/O hold time after FCLK ↑00000ns
t
CO FCLK ↑ to output valid 7.0 10.0 12.0 15.0 20.0 ns
tPSU I/O setup time before p-term clock ↑ 24.0 6.0 7.0 9.0 12.0 ns
tPH I/O hold time after p-term clock ↑00000ns
t
PCO P-term clock ↑ to output valid 15.0 20.0 23.0 28.0 36.0 ns
tPD I/O to output valid 1, 2 18.0 25.0 30.0 36.0 45.0 ns
tCW Fast clock pulse width 4.0 5.0 5.5 6.0 6.0 ns
tPCW P-term clock pulse width 5.0 6.0 7.5 8.5 12.0 ns
June 1, 1996 (Version 1.0) 3- 119
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
High-Density Function Block (FB) Internal AC Characteristics
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
tFLOGI FFB logic array delay 11.5 1.5 2.0 2.0 3.0 ns
tFLOGILP Low-power FFB logic array delay 13.5 5.5 7.0 8.0 11.0 ns
tFSUI FFB register setup time 1.5 2.5 3.0 4.0 6.0 ns
tFHI FFB register hold time 2.5 2.5 3.0 3.0 4.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 1.0 1.0 2.0 ns
tFAOI FFB register async. set delay 2.0 2.5 3.0 4.0 6.0 ns
tPTXI FFB p-term assignment delay 0.8 1.0 1.2 1.5 2.0 ns
tFFD FFB feedback delay 4.0 5.0 6.5 8.0 10.0 ns
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
tLOGI FB logic array delay 13.5 3.5 4.0 5.0 6.0 ns
tLOGILP Low power FB logic delay 17.0 7.5 9.0 11.0 14.0 ns
tSUI FB register setup time 1.5 2.5 3.0 4.0 6.0 ns
tHI FB register hold time 3.5 3.5 4.0 5.0 6.0 ns
tCOI FB register clock-to-output delay 1.0 1.0 1.0 1.0 1.0 ns
tPDI FB register pass through delay 1.5 2.5 4.0 4.0 4.0 ns
tAOI FB register async. set/reset delay 2.5 3.0 4.0 5.0 7.0 ns
tRA Set/reset recovery time before FCLK ↑15.0 19.0 21.0 25.0 31.0 ns
tHA Set/reset hold time after FCLK ↑00000ns
t
PRA Set/reset recovery time before p-term
clock ↑7.5 10.0 12.0 15.0 20.0 ns
tPHA Set/reset hold time after p-term clock ↑5.0 6.0 8.0 9.0 12.0 ns
tPCI FB p-term clock delay 1.0 0000ns
t
OEI FB p-term output enable delay 3.0 4.0 5.0 7.0 9.0 ns
tCARY8 ALU carry delay within 1 FB 25.0 6.0 8.0 12.0 15.0 ns
tCARYFB Carry lookahead delay per additional
Functional Block 21.0 1.5 2.0 3.0 4.0 ns
XC73108 108-Macrocell CMOS CPLD
3- 120 June 1, 1996 (Version 1.0)
I/O Block External AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Internal AC Characteristics
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
fIN Max pipeline frequency (input register
to FFB or FB register) 183.3 62.5 55.6 45.5 35.7 MHz
tSUIN Input register/latch setup time before
FCLK ↑4.0 5.0 6.0 7.0 10.0 ns
tHIN Input register/latch hold time after
FCLK ↑00000ns
t
COIN FCLK ↑ to input register/latch output 2.5 3.5 4.0 5.0 6.0 ns
tCESUIN Clock enable setup time before FCLK ↑5.0 7.0 8.0 10.0 12.0 ns
tCEHIN Clock enable hold time after FCLK ↑00000ns
t
CWHIN FCLK pulse width high time 4.0 5.0 5.5 6.0 6.0 ns
tCWLIN FCLK pulse width low time 4.0 5.0 5.5 6.0 6.0 ns
Symbol Parameter
XC73108-7
(Com only) XC73108-10
(Com only) XC73108-12
(Com/Ind only) XC73108-15 XC73108-20 UnitsMin Max Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 2.5 3.5 4.0 5.0 6.0 ns
tFOUT FFB output buffer and pad delay 3.0 4.5 5.0 7.0 9.0 ns
tOUT FB output buffer and pad delay 4.5 6.5 8.0 10.0 14.0 ns
tUIM Universal Interconnect Matrix delay 6.0 9.0 10.0 12.0 15.0 ns
tFOE FOE input to output valid 7.5 10.0 12.0 15.0 20.0 ns
tFOD FOE input to output disable 7.5 10.0 12.0 15.0 20.0 ns
tFCLKI Fast clock buffer delay 1.5 2.5 3.0 4.0 5.0 ns
Figure 3: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
FO VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X3491
VCCIO
5.0 V
3.3 V
June 1, 1996 (Version 1.0) 3- 121
XC73108 Pinouts
Note: With the XC73108 in the 225-pin ball grid array package, only 144 of the solder balls are connected, the remaining solder balls should be left unconnected.
PQ160 PG144
BG225 PQ100 PC84 Input XC73108 Output PQ160 PG144
BG225 PQ100 PC84 Input XC73108 Output
1 D3 – –V
CCIO 41 N4 28 –V
CCIO
2 C2 3 75 O/CKEN1 MC5-4 42 P3 29 12 O/FCLK2 MC10-5
3 – – – N/C 43 R2 – – I/O MC4-1
4 B1 4 – FO MC2-1 44 P4 30 13 FO MC1-2
5 – – – N/C 45 N5 – – I/O MC4-2
6 D2 5 76 O/FOE0 MC5-5 46 R3 – –V
CCINT
7 E3 – – O MC5-1 47 P5 31 14 FO MC1-3
8 C1 6 77 O/FOE1 MC5-6 48 R4 – – I/O MC4-3
9 E2 – – O MC5-2 49 N6 32 15 FO MC1-4
10 D1 7 78 VCCINT/VPP 50 P6 – – I/O MC4-4
11 F3 8 79 I/FI 51 R5 33 16 GND
12 F2 9 – I/O/FI MC5-7 52 – – – N/C
13 E1 10 80 I/FI 53 – – – N/C
14 G2 – – I/O/FI MC5-8 54 P7 34 17 FO MC1-5
15 G3 11 81 I/FI 55 N7 – – I/O MC4-5
16 F1 – – I/O/FI MC5-9 56 R6 35 18 FO MC1-6
17 G1 12 82 I/FI 57 R7 36 – I/O/FI MC4-7
18 H2 13 83 I/FI 58 P8 37 19 FO MC1-7
19 H1 14 84 I/FI 59 R8 38 20 FO MC1-8
20 H3 – – GND 60 N8 39 21 FO MC1-9
21 J3 15 1MR 61 N9 40 22 VCCIO
22 J1 16 2 I/FI 62 R9 41 23 I/O MC9-1
23 K1 17 3 I/FI 63 R10 42 24 I/O MC9-2
24 J2 18 4 I/FI 64 P9 43 25 I/O MC9-3
25 K2 – – O MC10-1 65 – – – N/C
26 K3 19 5 I/FI 66 – – – N/C
27 L1 – - O MC10-2 67 P10 – – I/O MC4-6
28 L2 20 6 I/FI 68 N10 44 26 I/O MC9-6
29 M1 21 – I/O/FI MC10-8 69 R11 45 – I/O/FI MC4-8
30 N1 22 7 I/FI 70 P11 46 27 GND
31 M2 23 8 GND 71 R12 47 28 I/O/FI MC9-7
32 L3 – – I/O/FI MC10-7 72 R13 48 – I/O/FI MC4-9
33 N2 24 9 O/FCLK0 MC10-3 73 P12 49 29 I/O/FI MC9-8
34 P1 – – O MC10-6 74 N11 – I/O MC3-1
35 M3 25 10 O/FCLK1 MC10-4 75 P13 50 30 I/O/FI MC9-9
36 N3 26 – FO MC1-1 76 R14 – – I/O MC3-2
37 P2 27 11 I/O/FI MC10-9 77 N12 51 31 I/O MC8-1
38 – – – N/C 78 N13 – – I/O MC3-3
39 – – – N/C 79 P14 52 32 I/O MC8-2
40 R1 – – GND 80 R15 – – GND
XC73108 108-Macrocell CMOS CPLD
3- 122 June 1, 1996 (Version 1.0)
XC73108 Pinouts (continued)
PQ160 PG144
BG225 PQ100 PC84 Input XC73108 Output PQ160 PG144
BG225 PQ100 PC84 Input XC73108 Output
81 M13 53 –V
CCIO 121 C12 – – VCCIO
82 N14 54 33 I/O MC8-3 122 B13 78 54 I/O/FI MC7-8
83 – – – N/C 123 A14 – – I/O MC12-6
84 P15 – – I/O MC3-4 124 B12 79 55 I/O/FI MC7-9
85 – – – N/C 125 C11 – – I/O/FI MC12-7
86 M14 55 34 I/O MC9-4 126 A13 80 56 I/O MC6-1
87 L13 – – I/O MC3-5 127 B11 – – GND
88 N15 56 35 I/O MC9-5 128 A12 – – I/O/FI MC12-8
89 L14 – – I/O MC3-6 129 C10 81 – I/O/FI MC11-7
90 M15 57 36 I/O MC8-4 130 B10 – – I/O MC11-1
91 K13 – – I/O/FI MC3-7 131 – – – N/C
92 K14 58 37 I/O MC8-5 132 – – – N/C
93 L15 – – I/O/FI MC3-8 133 A11 82 – I/O/FI MC11-8
94 J14 59 38 VCCINT 134 B9 83 57 I/O MC6-2
95 J13 60 39 I/O MC8-6 135 C9 84 58 I/O MC6-6
96 K15 61 – I/O/FI MC3-9 136 A10 85 59 I/O MC6-3
97 J15 62 40 I/O/FI MC8-7 137 A9 86 60 GND
98 H14 63 41 I/O/FI MC8-8 138 B8 87 61 I/O/FI MC6-7
99 H15 – – GND 139 A8 88 62 I/O/FI MC6-8
100 H13 64 42 GND 140 C8 89 63 I/O/FI MC6-9
101 G13 65 43 I/O/FI MC8-9 141 C7 90 64 VCCIO
102 G15 66 44 I/O MC7-1 142 A7 91 65 FO MC2-9
103 F15 67 45 I/O MC7-2 143 A6 92 66 FO MC2-8
104 G14 68 46 I/O MC7-3 144 B7 93 67 FO MC2-7
105 F14 – – I/O MC12-1 145 B6 94 – I/O/FI MC11-9
106 F13 69 47 I/O MC7-4 146 C6 95 68 FO MC2-6
107 E15 – – I/O MC12-2 147 A5 – – I/O MC11-2
108 E14 70 48 I/O MC7-5 148 B5 96 69 FO MC2-5
109 D15 – – I/O MC12-3 149 – – – N/C
110 C15 71 49 GND 150 – – – N/C
111 D14 72 50 I/O MC7-6 151 A4 – – I/O MC11-3
112 E13 – – I/O MC12-4 152 A3 97 70 FO MC2-4
113 C14 73 51 I/O MC6-5 153 B4 – – I/O MC11-4
114 B15 – – I/O MC12-5 154 C5 98 71 FO MC2-3
115 D13 74 52 I/O MC6-4 155 B3 – – I/O MC11-5
116 C13 75 – I/O/FI MC12-9 156 A2 99 72 FO MC2-2
117 B14 76 53 I/O/FI MC7-7 157 C4 100 73 VCCINT
118 – – – N/C 158 C3 – – I/O MC11-6
119 – – – N/C 159 B2 1 74 O/CKEN0 MC5-3
120 A15 77 – GND 160 A1 2 – GND
June 1, 1996 (Version 1.0) 3- 123
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C M = Military = –55°C(A) to 125°C (C)
Pins 84 100 144 160 225
Type Plastic
PLCC Ceramic
CLCC Plastic
PQFP Ceramic
PGA Plastic
PQFP Plastic
BGA
Code PC84 WC84 PQ100 PG144 PQ160 BG225
XC73108
–20 CI CI CI CIM CI CI
–15 CI CI CI CIM CI CI
–12 CI CI CI CI CI CI
–10CCCCCC
–7CCCCCC
XC73108 - 7 PC 84 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-20 20 ns pin-to-pin delay
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay (commercial and industrial only)
-7 7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PC84 84-Pin Plastic Leaded Chip Carrier
WC84 84-Pin Windowed Ceramic Leaded Chip Carrier
PQ100 100-Pin Plastic Quad Flat Pack
PG144 144-Pin Windowed Pin-Grid-Array
PQ160 160-Pin Plastic Quad Flat Pack
BG225 225-Pin Plastic Ball-Grid-Array
Temperature Options
C Commercial0°C to 70°C
I Industrial -40°C to 85°C
M Military -55°C (Ambient) to 125°C (Case)
XC73108 108-Macrocell CMOS CPLD
3- 124 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 3- 125
Features
• High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 100 MHz maximum clock frequency
• 100% PCI compliant
• 18 outputs with 24 mA drive
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• 100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 43 MHz 16-bit accumulators
• Multiple independent clocks
• Up to 132 inputs programmable as direct, latched, or
registered
• Power management options
• Multiple security bits for design protection
• 144 macrocells with programmable I/O architecture
• Advanced Dual-Block architecture
- 4 Fast Function Blocks
- 12 High-Density Function Blocks
• Programmable slew rate
• Programmable ground control
• 0.8 µ CMOS EPROM technology
• Available in 84-pin and 84-pin PLCC/CLCC, 144-pin
PGA, 100-pin and 160-pin PQFP, and 225 BGA
packages
General Description
The XC73144 is a high performance CPLD providing gen-
eral purpose logic integration. It consists of four PAL-like
24V9 Fast Function Blocks and twelve High Density Func-
tion Blocks interconnected b y the 100%-populated Univ ersal
Interconnect Matrix (UIM™).
Power Management
The XC73144 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the beha vioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)=MCHP (2.4) + MCLP (2.1) +
MC (0.015 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical pow er calculation for the XC73144
device , progr ammed as eight 16-bit counters and operating
at the indicated clock frequency.
XC73144
144-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
Figure 1: Typical ICC vs. Frequency for XC73144
X5768
Clock Frequency (MHz)
Typical ICC (mA)
050 100
100
200
300
400
Low Power
High Performance
500
XC73144 144-Macrocell CMOS CPLD
3- 126 June 1, 1996 (Version 1.0)
Figure 2: XC73144 Architecture
96
93
91
89
87
84
78
76
74
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
Serial Shift
Arithmetic Carry
MC10-9
MC10-8
MC10-7
MC10-6
MC10-5
MC10-4
MC10-3
MC10-2
MC10-1
AND ARRAY
MC9-9
MC9-8
MC9-7
MC9-6
MC9-5
MC9-4
MC9-3
MC9-2
MC9-1
AND ARRAY
21
21
2121
AND ARRAY AND ARRAY
MC11-1
MC11-2
MC11-3
MC11-4
MC11-5
MC11-6
MC11-7
MC11-8
MC11-9
MC12-1
MC12-2
MC12-3
MC12-4
MC12-5
MC12-6
MC12-7
MC12-8
MC12-9
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB10
FB9
FB11
FB12
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
MC5-9
MC5-8
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
AND ARRAY
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
AND ARRAY
3
3
2121
AND ARRAY AND ARRAY
MC16-1
MC16-2
MC16-3
MC16-4
MC16-5
MC16-6
MC16-7
MC16-8
MC16-9
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
Carry
Shift
Arithmetic
Serial
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
FB5
FFB2
FB16
FFB1
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
O/FOE1
O/FOE0
O/CKEN1
O/CKEN0
O
O
MC7-9
MC7-8
MC7-7
MC7-6
MC7-5
MC7-4
MC7-3
MC7-2
MC7-1
AND ARRAY
MC6-9
MC6-8
MC6-7
MC6-6
MC6-5
MC6-4
MC6-3
MC6-2
MC6-1
AND ARRAY
21
21
2121
AND ARRAY AND ARRAY
MC14-1
MC14-2
MC14-3
MC14-4
MC14-5
MC14-6
MC14-7
MC14-8
MC14-9
MC15-1
MC15-2
MC15-3
MC15-4
MC15-5
MC15-6
MC15-7
MC15-8
MC15-9
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
O
O
O/FCLK0
O/FCLK1
O/FCLK2
O
I/O/FI
I/O/FI
I/O/FI
FB7
FB6
FB14
FB15
12
9
12
9
9 9
42
54
42
54
UIM
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
I/FI
C8
A8
B8
C9
C14
D13
A10
B9
A13
B12
B13
B14
D14
E14
F13
G14
F15
G15
K15
L15
K13
L14
L13
P15
N13
R14
N11
R13
R11
R7
P10
N7
P6
R4
N5
R2
F1
G2
F2
C1
D2
C2
B2
E2
E3
A7
A6
B7
C6
B5
A3
C5
A2
B1
J1
K1
J2
K3
L2
N1
BG225
K9
R10
P9
M14
N15
N10
R12
P12
P13
N12
P14
N14
M15
K14
J13
J15
H14
G13
N3
P4
P5
N6
P7
R6
P8
R8
N8
F14
E15
D15
E13
B15
A14
C11
A12
C13
B10
A5
A4
B4
B3
C3
C10
A11
B6
K2
L1
N2
M3
P3
P1
L3
M1
P2
H1
H2
G1
G3
E1
F3
BG225
X5653
121212 6 6
62
63
64
86
88
68
71
73
75
77
79
82
90
92
95
97
98
101
105
107
109
112
114
123
125
128
116
130
147
151
153
155
158
129
133
145
25
27
33
35
42
34
32
29
37
36
44
47
49
54
56
58
59
60
19
18
17
15
13
11
PQ160
140
139
138
135
113
115
136
134
126
124
122
117
111
108
106
104
103
102
149
–
150
–
3
–
5
–
–
72
69
57
67
55
50
48
45
43
16
14
12
8
6
2
159
9
7
142
143
144
146
148
152
154
156
4
22
23
24
26
28
30
PQ160
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
3
3
AND ARRAY
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
FFB3FFB4
12
9
12
9
99
D5
D6
E5
E6
G4
E4
J4
F4
F5
N9
L4
M7
M5
L5
L6
M4
M6
M9
53
–
52
–
39
–
38
–
–
1818
I/O/FI
I/O/FI
I/O/FI
O
O
O
O
O
O
MC8-9
MC8-8
MC8-7
MC8-6
MC8-5
MC8-4
MC8-3
MC8-2
MC8-1
AND ARRAY
21
21
AND ARRAY
MC13-1
MC13-2
MC13-3
MC13-4
MC13-5
MC13-6
MC13-7
MC13-8
MC13-9
O
O
O
O
O
O
I/O/FI
I/O/FI
I/O/FI
FB8FB13 D7
D9
D12
E11
D10
E10
G12
F12
M10
L10
L12
K12
K11
L11
M11
J12
G12
–
–
–
–
–
65
66
83
85
132
131
119
118
–
–
–
–
–
June 1, 1996 (Version 1.0) 3- 127
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Notes: 1. Sample tested.
2. Measured with device programmed as eight 16-bit counters.
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VCCIO I/O supply voltage relative to GND 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
TIN Input signal transition time 50 ns
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 10 mA
VCC = Min 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
IOZ Output high-Z leakage current VCC = Max
VIN = GND or VCCIO ±10.0 µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 8.0 pF
CIN Input capacitance for global control pins
(FCLK0, FCLK1, FCLK2, FOE0, FOE1) VIN = GND
f = 1.0 MHz 12.0 pF
COUT1Output capacitance VIN = GND
f = 1.0 MHz 10.0 pF
ICC2Supply current (low power mode) VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C250 Typ mA
XC73144 144-Macrocell CMOS CPLD
3- 128 June 1, 1996 (Version 1.0)
Power-up/Reset Timing Parameters
Slew Rate and Programmable Ground Control
Due to the large number of high current drivers a vailab le on
the XC73144, two programmable signal management
features have been included – slew rate control (SRC) and
ground control (GC). Slew rate control is primarily for
external system benefit, to reduce ringing and other
coupling phenomenon. SRC permits designers to select
either 1 V/ns or 1.5 V/ns slew rate on a pin-by-pin basis for
any output or I/O signal. This can be done with PLUSASM
or schematically, as needed. The def ault slew rate is 1 V/ns.
To assign the pins with equations (PLUSASM), the
designer needs to only declare them as follows:
FAST ON <signal name list>
This will assign the signals in the list to hav e a 1.5 V/ns slew
rate. Omitting the signal name list will globally set all signals
to be 1.5 V/ns. Specific signals therefore can be declared
with 1 V/ns slew rate as follows:
FAST OFF <signal name list>
Schematic control of SRC is also straightforward. Again,
the default is 1 V/ns, but to assign specific pins fast, the
designer need only attach the “FAST” attribute to the I/O or
output buffer or the corresponding pin.
Programmab le ground control is useful f or internal chip sig-
nal management. The output buffers of the Fast Function
Blocks have an impedance of approximately 7 Ω when
switching high to low, where the High Density Function
Blocks impedance is around 14 Ω. Since this low imped-
ance is negligible compared to the impedance of the pin
inductance when output current transients occur, a reason-
able ground connection can be made by driving unused
output pins low and physically attaching them to external
ground. The XC73144 architecture permits the automatic
assignment of external ground signals to all macrocells that
are not declared as primar y outputs or I/Os. Note that the
logical function of the buried macrocell is fully preserved,
while its output driver is driving low and ph ysically attached
to ground. Should designers not wish to employ program-
mable ground control, they need only declare all such pins
as primar y I/Os whether they will be attached externally or
not.
Fast Function Block (FFB) External AC Characteristics3
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip-flop toggle rate.
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
tRESET Configuration completion time 80 160 µs
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
fCF Max count frequency 1, 2, 4 105.0 100.0 80.0 66.7 MHz
tSUF Fast input setup time before FCLK ↑ 14.0 5.0 6.0 7.0 ns
tHF Fast input hold time after FCLK ↑00 0 0ns
t
COF FCLK ↑ to output valid 5.5 7.0 9.0 12.0 ns
tPDFO Fast input to output valid 1, 2 7.5 9.0 12.0 15.0 ns
tPDFU I/O to output valid 1, 2 13.5 17.0 22.0 27.0 ns
tCWF Fast clock pulse width (High or Low) 4.0 5.0 5.5 6.0 ns
June 1, 1996 (Version 1.0) 3- 129
High-Density Function Block (FB) External AC Characteristics
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI.
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Fast Function Block (FFB) Internal AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
fCMax count frequency 1, 2 83.3 62.5 55.6 45.5 MHz
tSU I/O setup time before FCLK ↑ 1, 2 12.0 13.5 18.0 22.0 ns
tHI/O hold time after FCLK ↑00 0 0ns
t
CO FCLK ↑ to output valid 7.0 9.0 12.0 15.0 ns
tPSU I/O setup time before p-term clock ↑ 24.0 6.0 7.0 9.0 ns
tPH I/O hold time after p-term clock ↑00 0 0ns
t
PCO P-term clock ↑ to output valid 15.0 19.0 23.0 28.0 ns
tPD I/O to output valid 1, 2 18.0 22.0 30.0 36.0 ns
tCW Fast clock pulse width 4.0 5.0 5.5 6.0 ns
tPCW P-term clock pulse width 5.0 6.0 7.5 8.5 ns
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
tFLOGI FFB logic array delay 11.5 1.5 2.0 2.0 ns
tFLOGILP Low-power FFB logic array delay 13.5 5.5 7.0 8.0 ns
tFSUI FFB register setup time 1.5 2.5 3.0 4.0 ns
tFHI FFB register hold time 2.5 2.5 3.0 3.0 ns
tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tFPDI FFB register pass through delay 0.5 0.5 1.0 1.0 ns
tFAOI FFB register async. set delay 2.0 2.5 3.0 4.0 ns
tPTXI FFB p-term assignment delay 0.8 1.0 1.2 1.5 ns
tFFD FFB feedback delay 4.0 5.0 6.5 8.0 ns
XC73144 144-Macrocell CMOS CPLD
3- 130 June 1, 1996 (Version 1.0)
High-Density Function Block (FB) Internal AC Characteristics
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.
I/O Block External AC Characteristics
Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
tLOGI FB logic array delay 13.5 3.5 4.0 5.0 ns
tLOGILP Low power FB logic delay 17.0 7.5 9.0 11.0 ns
tSUI FB register setup time 1.5 2.5 3.0 4.0 ns
tHI FB register hold time 3.5 3.5 4.0 5.0 ns
tCOI FB register clock-to-output delay 1.0 1.0 1.0 1.0 ns
tPDI FB register pass through delay 1.5 2.5 4.0 4.0 ns
tAOI FB register async. set/reset delay 2.5 3.0 4.0 5.0 ns
tRA Set/reset recovery time before FCLK ↑15.0 19.0 21.0 25.0 ns
tHA Set/reset hold time after FCLK ↑00 0 0ns
t
PRA Set/reset recovery time before p-term clock ↑7.5 10.0 12.0 15.0 ns
tPHA Set/reset hold time after p-term clock ↑5.0 6.0 8.0 9.0 ns
tPCI FB p-term clock delay 1.0 0 0 0 ns
tOEI FB p-term output enable delay 3.0 4.0 5.0 7.0 ns
tCARY8 ALU carry delay within 1 FB 25.0 6.0 8.0 12.0 ns
tCARYFB Carry lookahead delay per additional
Functional Block 21.0 1.5 2.0 3.0 ns
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
fIN Max pipeline frequency (input register to FFB
or FB register) 183.3 62.5 55.6 45.5 MHz
tSUIN Input register/latch setup time before FCLK ↑4.0 5.0 6.0 7.0 ns
tHIN Input register/latch hold time after FCLK ↑00 0 0ns
t
COIN FCLK ↑ to input register/latch output 2.5 3.5 4.0 5.0 ns
tCESUIN Clock enable setup time before FCLK ↑5.0 7.0 8.0 10.0 ns
tCEHIN Clock enable hold time after FCLK ↑00 0 0ns
t
CWHIN FCLK pulse width high time 4.0 5.0 5.5 6.0 ns
tCWLIN FCLK pulse width low time 4.0 5.0 5.5 6.0 ns
June 1, 1996 (Version 1.0) 3- 131
Internal AC Characteristics
Symbol Parameter
XC73144-7
(Com Only) XC73144-10
(Com Only) XC73144-12
(Com/Ind Only) XC73144-15 UnitsMin Max Min Max Min Max Min Max
tIN Input pad and buffer delay 2.5 3.5 4.0 5.0 ns
tFOUT FFB output buffer and pad delay 3.0 4.5 5.0 7.0 ns
tOUT FB output buffer and pad delay 4.5 6.5 8.0 10.0 ns
tUIM Universal Interconnect Matrix delay 6.0 9.0 10.0 12.0 ns
tFOE FOE input to output valid 7.5 10.0 12.0 15.0 ns
tFOD FOE input to output disable 7.5 10.0 12.0 15.0 ns
tFCLKI Fast clock buffer delay 1.5 2.5 3.0 4.0 ns
Figure 3: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
FO VTEST
5.0 V
3.3 V
R1
160 Ω
260 Ω
R2
120 Ω
360 Ω
CL
35 pF
35 pF
X3491
VCCIO
5.0 V
3.3 V
XC73144 144-Macrocell CMOS CPLD
3- 132 June 1, 1996 (Version 1.0)
XC73144 Pinouts
BG225 PQ160 Input XC73144 Output BG225 PQ160 Input XC73144 Output
D3 1V
CCIO N4 41 VCCIO
E4 - I/FO MC3-4 P3 42 O/FCLK2 MC14-5
F4 - I/FO MC3-2 R2 43 I/O MC6-1
C2 2 O/CKEN1 MC7-4 P4 44 I/FO MC1-2
F5 - I/FO MC3-1 N5 45 I/O MC6-2
G4 3 I/FO MC3-5 R3 46 VCCINT
B1 4 I/FO MC2-1 M5 - I/FO MC4-4
J4 5 I/FO MC3-3 P5 47 I/FO MC1-3
D2 6 O/FOE0 MC7-5 R4 48 I/O MC6-3
E3 7 O MC7-1 L6 - I/FO MC4-6
C1 8 O/FOE1 MC7-6 M6 - I/FO MC4-8
E2 9 O MC7-2 N6 49 I/FO MC1-4
D1 10 VCCINT/VPP P6 50 I/O MC6-4
F3 11 I/FI R5 51 GND
F2 12 I/O/FI MC7-7 M7 52 I/FO MC4-7
E1 13 I/FI M9 53 I/FO MC4-9
G2 14 I/O/FI MC7-8 P7 54 I/FO MC1-5
G3 15 I/FI N7 55 I/O MC6-5
F1 16 I/O/FI MC7-9 R6 56 I/FO MC1-6
G1 17 I/FI R7 57 I/O/FI MC6-7
H2 18 I/FI P8 58 I/FO MC1-7
H1 19 I/FI R8 59 I/FO MC1-8
H3 20 GND N8 60 I/FO MC1-9
J3 21 I/FI MR N9 61 VCCIO
K5 -V
CCIO M10 - O MC13-1
J1 22 I/FI L10 - O MC13-2
K1 23 I/FI R9 62 I/O MC12-1
J2 24 I/FI R10 63 I/O MC12-2
K2 25 O MC14-1 P9 64 I/O MC12-3
K3 26 I/FI L11 65 O MC13-6
L1 27 O MC14-2 M11 66 I/O/FI MC13-7
L2 28 I/FI M12 - GND
M1 29 I/O/FI MC14-8 P10 67 I/O MC6-6
N1 30 I/FI N10 68 I/O MC12-6
M2 31 GND R11 69 I/O/FI MC6-8
L3 32 I/O/FI MC14-7 P11 70 GND
N2 33 O/FCLK0 MC14-3 R12 71 I/O/FI MC12-7
P1 34 O MC14-6 R13 72 I/O/FI MC6-9
M3 35 O/FCLK1 MC14-4 P12 73 I/O/FI MC12-8
N3 36 I/FO MC1-1 N11 74 I/O MC5-1
K4 - I/FO MC4-1 P13 75 I/O/FI MC12-9
L4 - I/FO MC4-2 R14 76 I/O MC5-2
P2 37 I/O/FI MC14-9 N12 77 I/O MC11-1
M4 38 I/FO MC4-3 N13 78 I/O MC5-3
L5 39 I/FO MC4-5 P14 79 I/O MC11-2
R1 40 GND R15 80 GND
June 1, 1996 (Version 1.0) 3- 133
XC73144 Pinouts (continued)
BG225 PQ160 Input XC73144 Output BG225 PQ160 Input XC73144 Output
M13 81 VCCIO C12 121 VCCIO
L12 - O MC13-3 B13 122 I/O/FI MC10-8
K12 - O MC13-4 A14 123 I/O MC16-6
N14 82 I/O MC11-3 B12 124 I/O/FI MC10-9
K11 - O MC13-5 C11 125 I/O/FI MC16-7
J12 83 I/O/FI MC13-8 A13 126 I/O MC9-1
P15 84 I/O MC5-4 D11 - O MC8-3
G12 85 I/O/FI MC13-9 B11 127 GND
M14 86 I/O MC12-4 A12 128 I/O/FI MC16-8
L13 87 I/O MC5-5 E10 - O MC8-4
N15 88 I/O MC12-5 D10 - O MC8-5
L14 89 I/O MC5-6 C10 129 I/O/FI MC15-7
M15 90 I/O MC11-4 B10 130 I/O MC15-1
K13 91 I/O/FI MC5-7 D9 131 I/O/FI MC8-8
K14 92 I/O MC11-5 D7 132 I/O/FI MC8-9
L15 93 I/O/FI MC5-8 A11 133 I/O/FI MC15-8
J14 94 VCCINT B9 134 I/O MC9-2
J13 95 I/O MC11-6 C9 135 I/O MC9-6
K15 96 I/O/FI MC5-9 A10 136 I/O MC9-3
J15 97 I/O/FI MC11-7 A9 137 GND
H14 98 I/O/FI MC11-8 B8 138 I/O/FI MC9-7
H15 99 GND A8 139 I/O/FI MC9-8
H13 100 GND C8 140 I/O/FI MC9-9
F11 -V
CCINT C7 141 VCCIO
G13 101 I/O MC11-9 A7 142 I/FO MC2-9
G15 102 I/O MC10-1 A6 143 I/FO MC2-8
F15 103 I/O MC10-2 B7 144 I/FO MC2-7
G14 104 I/O MC10-3 B6 145 I/O/FI MC15-9
F14 105 I/O MC16-1 C6 146 I/FO MC2-6
F13 106 I/O MC10-4 D6 - I/FO MC3-8
E15 107 I/O MC16-2 E6 - I/FO MC3-6
E14 108 I/O MC10-5 A5 147 I/O MC15-2
D15 109 I/O MC16-3 B5 148 I/FO MC2-5
C15 110 GND D5 149 I/FO MC3-9
D14 111 I/O MC10-6 E5 150 I/FO MC3-7
E13 112 I/O MC16-4 A4 151 I/O MC15-3
C14 113 I/O MC9-5 A3 152 I/FO MC2-4
B15 114 I/O MC16-5 B4 153 I/O MC15-4
D13 115 I/O MC9-4 C5 154 I/FO MC2-3
C13 116 I/OFI MC16-9 D4 - GND
F12 - O MC8-1 B3 155 I/O MC15-5
E12 - O MC8-2 A2 156 I/FO MC2-2
B14 117 I/O/FI MC10-7 C4 157 VCCINT
E11 118 O MC8-6 C3 158 I/O MC15-6
D12 119 I/O/FI MC8-7 B2 159 O/CKEN0 MC7-3
A15 120 GND A1 160 GND
XC73144 144-Macrocell CMOS CPLD
3- 134 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C
Pins 160 225
Type Plastic
PQFP Plastic
BGA
Code PQ160 BG225
XC73144
–15 CI CI
–12 CI CI
–10 C C
–7 C C
XC73144 - 7 PQ 160 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-15 15 ns pin-to-pin delay
-12 12 ns pin-to-pin delay
-10 10 ns pin-to-pin delay (commercial and industrial only)
-7 7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PQ160 160-Pin Plastic Quad Flat Pack
BG225 225-Pin Plastic Ball-Grid-Array
Temperature Options
C Commercial 0°C to 70°C
I Industrial -40°C to 85°C
June 1, 1996 (Version 1.0) 3-135
The following section includes typical characterization data
for the XC7354, XC7372 and XC73108. Frequently con-
sulted timing parameters were characterized under varia-
tions in temperature, v oltage and number of simultaneously
switching outputs. As demonstrated by the graphical data
presented, all products are well within published data sheet
limits for commercial temperature and voltage ranges.
Though this set of characterization data does not include
explicit information on the XC7318, XC7336 and XC73144,
all XC7300 products are designed using the same circuit
configurations, design rules and process technology.
Therefore, the XC7318, XC7336 and XC73144 timing
parameters are also safely guardbanded with respect to
their published data sheet limits.
XC7354
XC7300 Characterization Data
June 1, 1996 (Version 1.0)
tSU vs Voltage
XC7354-7 @ 25C
7
8
9
10
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7009
tSU vs Temperature
XC7354-7 @ 5 V
7
8
9
10
11
02570
Temperature
Time (ns)
X7010
tCO vs Voltage
XC7354-7 @ 25C 1 Output Switching
4
4.25
4.5
4.75
5
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7011
tCO vs Temperature
XC7354-7 @ 5 V 1 Output Switching
3
4
5
6
02570
Temperature
Time(ns)
X7012
tCO vs # Outputs Switching
XC7354-7 @ 25C
4
5
6
4 8 12 16 20
Outputs
Time(ns)
X7013
XC7300 Characterization Data
3-136 June 1, 1996 (Version 1.0)
XC7354 (continued)
tCOF vs Voltage
XC7354-7 @ 25C 1 Output Switching
4
4.25
4.5
4.75
5
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7014
tCOF vs Temperature
XC7354-7 @ 5 V 1 Output Switching
3
4
5
6
02570
Temperature
Time (ns)
X7015
tCOF vs # Outputs Switching
XC7354-7 @ 25C
4
5
6
4 8 12 16 20
Outputs
Time (ns)
X7016
tRA vs Voltage
XC7354-7 @ 25C
7
7.5
8
8.5
9
9.5
10
10.5
11
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7017
tRA vs Temperature
XC7354-7 @ 5 V 1 Output Switching
8
9
10
11
12
13
02570
Temperature
Time(ns)
X7018
tHA vs Voltage
XC7354-7 @ 25C
-14
-13
-12
-11
-10
-9
-8
-7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7019
tHA vs Temperature
XC7354 @ 5 V 1 Output Switching
-13
-12
-11
-10
-9
-8
02570
Temperature
Time (ns)
X7020
tPD vs Voltage
XC7354-7 @25C 1 Output Switching
10
11
12
13
14
15
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7021
June 1, 1996 (Version 1.0) 3-137
XC7354 (continued)
t
PD
vs Temperature
XC7354-7 @5 V 1 Output Switching
10
11
12
13
14
15
02570
Temperature
Time (ns)
X7022
tPD vs # Outputs Switching
XC7354-7 @25C 5 V
12
13
14
15
16
4 8 12 16 20
# Outputs
Time (ns)
X7023
tPDFO
vs Voltage
XC7354-7 @25C 1 Output Switching
3
4
5
6
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7024
tPDFO vs Temperature
XC7354-7 @5 V 1 Output Switching
2
3
4
5
02570
Temperature
Time (ns)
X7025
tPDFO
vs # Outputs Switching
XC7354-7 @25C 5 V
3
4
5
4 8 12 16 20
# Outputs
Time (ns)
X7026
tPDFU vs Voltage
XC7354-7 @25C 1 Output Switching
8
9
10
11
12
13
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7027
tPDFU vs Temperature
XC7354-7 @5 V 1 Output Switching
8
9
10
11
02570
Temperature
Time (ns)
X7028
tPDFU vs # Outputs Switching
XC7354-7 @25C 5 V
8
9
10
4 8 12 16 20
# Outputs
Time (ns)
X7029
XC7300 Characterization Data
3-138 June 1, 1996 (Version 1.0)
XC7372
tSU vs Voltage
XC7372-7 @ 25C
5
6
7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7030
tSU vs Temperature
XC7372-7 @ 5 V
5
6
7
8
02570
Temperature
Time (ns)
X7031
tCO vs Voltage
XC7372-7 @25C 1 Output Switching
4
5
6
7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7032
tCO vs Temperature
XC7372-7 @ 5 V 1 Output Switching
4
5
6
7
02570
Temperature
Time (ns)
X7033
tCO vs #Outputs Switching
XC7372-7 @ 25C
4
5
6
7
148121620
# Outputs
Time (ns)
X7034
tSUF vs Voltage
XC7372-15 @ 25C
5
6
7
8
4.75 V 5.00 V 5.25V
Voltage
Time (ns)
X7035
tCOF vs Voltage
XC7372-7 @25C 1 Output Switching
4
5
6
7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7036
tCOF vs #Outputs Switching
XC7372-7 @ 25C
4
5
6
7
1 4 8 12 16 20
# Outputs
Time (ns)
X7037
June 1, 1996 (Version 1.0) 3-139
XC7372 (continued)
tRA vs Voltage
XC7372-7 @25C
7
8
9
10
11
12
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7038
tRA vs Temperature
XC7372-7 @ 5 V 1 Output
8
9
10
11
12
13
02570
Temperature
Time (ns)
X7039
tHA vs Voltage
XC7372-7 @25C
-14
-13
-12
-11
-10
-9
-8
-7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7040
tHA vs Temperature
XC7372-7 @ 5V 1 Output Switching
-13
-12
-11
-10
-9
-8
02570
Temperature
Time (ns)
X7041
tPD vs Voltage
XC7372-7 @25C 1 Output Switching
12
13
14
15
16
17
4.75 5.00 5.25
Voltage
Time (ns)
X7002
tPD vs Temperature
XC7372-7 @5 V 1 Output Switching
12
13
14
15
16
17
02570
Temperature
Time (ns)
X7001
tPD vs # Outputs
XC7372-7 @25C 5V
14
15
16
17
18
19
20
4 8 12 16 20
# Outputs
Time (ns)
X7000
tPDFO vs Voltage
XC7372-7 @25C 1 Output Switching
5
6
7
8
9
10
4.75 V 5.00 V 5.25 V
Volts
Time (ns)
X7003
XC7300 Characterization Data
3-140 June 1, 1996 (Version 1.0)
XC7372 (continued)
tPDFO vs Temperature
XC7372-7 @5 V 1 Output Switching
5
6.02
7.04
02570
Temp
Time (ns)
X7004
tPDFO vs # Outputs
XC7372-7 @25C 5V
5
6
7
8
4 8 12 16 20
# Outputs
Time (ns)
X7005
tPDFU vs Voltage
XC7372-10 @25C 1 Output Switching
10
11
12
13
14
15
4.50 V 4.75 V 5.00 V 5.25 V
Volts
Time (ns)
X7006
tPDFU vs Temperature
XC7372-10 @5V 1 Output Switching
10
11
12
13
14
15
-400 257080
Temperature
Time (ns)
X7007
tPDFU vs # Outputs
XC7372-10 @25C 5V
10
11
12
13
14
15
4 8 12 16 20
# Outputs
Time (ns)
X7008
June 1, 1996 (Version 1.0) 3-141
XC73108
tSU vs Voltage
XC73108-7 @ 25C
7
8
9
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7042
tSU vs Temperature
XC73108-7 @ 5 V
7
8
9
10
02570
Temperature
Time (ns)
X7043
tCO vs Voltage
XC73108-7 @25C 1 Output Switching
3.5
3.75
4
4.25
4.5
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7044
tCO vs Temperature
XC73108-7 @ 5 V 1 Output Switching
3
4
5
6
02570
Temperature
Time (ns)
X7045
tCO vs #Outputs Switching
XC73108-7 @ 25C
4
5
4 8 12 16 20
# Outputs
Time (ns)
X7046
tSUF vs Voltage
XC73108-7 @ 25C
6
7
8
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7047
tCOF vs Voltage
XC73108-7 @25C 1 Output Switching
3.25
3.5
3.75
4
4.25
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7048
tCOF vs Temperature
XC73108-7 @ 5 V 1 Output
3
4
5
02570
Temperature
Time (ns)
X7049
XC7300 Characterization Data
3-142 June 1, 1996 (Version 1.0)
XC73108 (continued)
tCOF vs #Outputs Switching
XC73108-7 @ 25C
3.5
4.5
5.5
4 8 12 16 20
# Outputs
Time (ns)
X7050
tRA vs Voltage
XC73108-7 @25C
8
8.5
9
9.5
10
10.5
11
11.5
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7051
tRA vs Temperature
XC73108-7 @ 5 V 1 Output
9
10
11
12
13
14
02570
Temperature
Time (ns)
X7052
tHA vs Voltage
XC73108-7 @25C
-15
-14
-13
-12
-11
-10
-9
-8
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7053
tHA vs Temperature
XC73108-7 @ 5 V 1 Output Switching
-14
-13
-12
-11
-10
-9
02570
Temperature
Time (ns)
X7054
tPD vs Voltage
XC73108-7 @25C 1 Output Switching
13
14
15
16
17
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7055
tPD vs Temperature
XC73108-7 @5 V 1 Output Switching
12
13
14
15
16
17
18
02570
Temperature
Time (ns)
X7056
tPD vs # Outputs
XC73108-7 @25C 5 V
14
15
16
17
18
4 8 12 16 20
# Outputs
Time (ns)
X7057
June 1, 1996 (Version 1.0) 3-143
XC73108 (continued)
tPDFO vs Voltage
XC73108-7 @25C 1 Output Switching
4
5
6
7
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7058
tPDFO vs Temperature
XC73108-7 @5 V 1 Output Switching
3
4
5
6
7
02570
Temperature
Time (ns)
X7059
tPDFO vs # Outputs
XC73108-7 @25C 5 V
5
6
7
8 121620
# Outputs
Time (ns)
X7060
tPDFU vs Voltage
XC73108-7 @25C 1 Output Switching
8
9
10
11
12
13
4.75 V 5.00 V 5.25 V
Voltage
Time (ns)
X7061
tPDFU vs Temperature
XC73108-7 @5 V 1 Output Switching
9
10
11
12
13
02570
Temperature
Time (ns)
X7062
tPDFU vs # Outputs Switching
XC73108-7 @25C 5 V
9
10
11
12
13
4 8 12 16 20
# Outputs
Time (ns)
X7063
XC7300 Characterization Data
3-144 June 1, 1996 (Version 1.0)
3-145
XC7236A 36-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147
FBs and macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148
Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-149
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
3.3 V or 5 V Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150
Programming and Using the XC7236A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-151
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152
AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-153
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154
Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-155
Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-162
XC7272A 72-Macrocell CMOS CPLD
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Function Blocks and Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-165
Universal Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-166
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
Programming and Using the XC7272A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-167
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
DC Characteristics Over Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-168
AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-169
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170
Incremental Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-170
Power-up/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-171
Timing and Delay Path Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172
Timing and Delay Path Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172
XC7372 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-177
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
XC7200 Series Table of Contents
XC7200 Series Table of Contents
3-146
June 1, 1996 (Version 1.0) 3- 147
Features
• Second-Generation High Density Programmable Logic
Device
• UV-erasable CMOS EPROM technology
• 36 macrocells, grouped into four Function Blocks(FBs),
interconnected by a programmable Universal
Interconnect Matrix
• Each FB contains a programmable AND-array with 24
complementary inputs, providing up to 17 product terms
per macrocell
• Enhanced logic features:
- 2-input Arithmetic Logic Unit in each macrocell
- Dedicated fast carry network between macrocells
- Wide AND capability in the Universal Interconnect
Matrix
• Identical timing for all interconnect paths and for all
macrocell logic paths
• 36 signal pins
- 30 I/Os, 2 inputs, 4 outputs
• Each input is programmable
- Direct, latched, or registered
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ± 0.3 V
• Three high-speed, low-skew global clock inputs
• Available in 44-pin PLCC and CLCC packages
General Description
The XC7236A combines the classical features of the PAL-
like CPLD architecture with innovative systems-oriented
logic enhancements. This favors the implementation of fast
state machines, large synchronous counters and fast arith-
metic, as well as multi-level general-pur pose logic. Perfor-
mance, measured in achievable system clock rate and
critical delays, is not only predictable, but independent of
physical logic mapping, interconnect routing, and resource
utilization. Performance, therefore, remains invariant
between design iterations. The propagation delay through
interconnect and logic is constant for any function imple-
mented in any one of the output macrocells.
The functional versatility of the traditional programmable
logic arra y architecture is enhanced through additional gat-
ing and control functions available in an Arithmetic Logic
Unit (ALU) in each macrocell. Dedicated fast arithmetic
carry lines running directly between adjacent macrocells
and FBs suppor t fast adders, subtractors and comparators
of any length up to 36 bits.
This additional ALU in each macrocell can generate any
combinatorial function of two sums of products, and it can
generate and propagate arithmetic-carry signals between
adjacent macrocells and FBs.
The Universal Interconnect Matrix (UIM) facilitates unre-
stricted, fixed-delay interconnects from all device inputs
and macrocell outputs to any FB AND-array input. The UIM
can also perform a logical AND across any number of its
incoming signals on the way to any FB, adding another
level of logic without additional delay. This supports bidirec-
tional loadable synchronous counters of any size up to 36
bits, operating at the specified maximum device frequency
As a result of these logic enhancements, the XC7236A can
deliver high performance even in designs that combine
large numbers of product terms per output, or need more
layers of logic than AND-OR, or need a wide AND function
in some of the product terms, or perform wide arithmetic
functions.
Architectural Overview
Figure 1 shows the XC7236A structure. Four Function
Blocks(FBs) are all interconnected by a central UIM. Each
FB receives 21 signals from the UIM and each FB produces
nine signals back into the UIM. All device inputs are also
routed via the UIM to all FBs. Each FB contains nine output
macrocells that draw from a programmable AND array
driven by the 21 signals from the UIM. Most macrocells
drive a 3-state chip output. All feed back into the UIM.
XC7236A
36-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
XC7236A 36-Macrocell CMOS CPLD
3- 148 June 1, 1996 (Version 1.0)
FBs and macrocells
The XC7236A contains 36 macrocells with identical struc-
ture, grouped into four FBs of nine macrocells each.
Figure 2 shows the macrocell structure. Each macrocell is
driven by product terms derived from a progr ammable AND
array in the FB. The AND array in each FB receives 21 sig-
nals and their complements from the UIM. In three FBs, the
AND array receives three additional inputs and their com-
plements directly from FastInput (FI) pins, thus offering
faster logic paths.
Five product terms are private to each macrocell; an addi-
tional 12 product terms are shared among the nine macro-
cells in each FB. Four of the private product terms can be
selectively ORed together with up to four of the shared
product terms, and drive the D1 input to the ALU . The other
input, D2, to the ALU is driven by the OR of the fifth private
product term and up to eight of the remaining shared prod-
uct terms.
As a programmable option, four of the private product
terms can be used for other purposes. One of the private
product terms can be used as a dedicated clock for the flip-
flop in the macrocell. (See the subsequent description of
other clocking options.) Another one of the private product
terms can be the asynchronous active-High Reset of the
macrocell flip-flop, another one can be the asynchronous
active-High Set of the macrocell flip-flop, and another one
can be the Output Enable signal.
As a configuration option, the macrocell output can be fed
back and ORed into the D2 input to the ALU after being
ANDed with three of the shared product terms to implement
counters and toggle flip-flops.
The ALU has two programmable modes. In the logic mode,
it is a 2-input function generator, a 4-bit look-up table, that
can be programmed to generate an y Boolean function of its
two inputs. It can OR them, widening the OR function to 17
inputs; it can AND them, which means that one sum of
products can be used to mask the other; it can XOR them,
toggling the flip-flop or comparing the two sums of prod-
ucts. Either or both of the sum-of-product inputs to the ALU
can be inv erted and either or both can be ignored. The ALU
can implement one additional layer of logic without any
speed penalty.
In the arithmetic mode, the ALU block in each macrocell
can be programmed to generate the arithmetic sum or dif-
ference of tw o operands, combined with a carry signal com-
ing from the next lower macrocell. It also feeds a carry
output to the next higher macrocell. This carry propagation
chain crosses the boundaries between FBs. This dedicated
carry chain overcomes the inherent speed and density
problems of the traditional CPLD architecture when trying
to perform arithmetic functions.
The ALU output drives the D input of the macrocell flip-flop .
Each flip-flop has several programmable options. One
option is to eliminate the flip-flop by making it transparent,
which makes the Q output identical with the D input, inde-
pendent of the clock. Otherwise, the flip-flop operates in the
Figure 1: XC7236A Architecture
17
18
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
I/O
I/O
35
36
37
38
40
41
42
43
44
44
LCC
I/O/FI
I/O/FI
I/O/FI
I/O
I/O
I/O
I/O
FOE/O
I/O
24
25
26
27
28
30
31
32
33
Serial Shift
Arithmetic Carry
MC4-9
MC4-8
MC4-7
MC4-6
MC4-5
MC4-4
MC4-3
MC4-2
MC4-1
AND ARRAY
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
AND ARRAY
21
21
2121
UIM
AND ARRAY AND ARRAY
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
MC2-1
MC2-2
MC2-3
MC2-4
MC2-5
MC2-6
MC2-7
MC2-8
MC2-9
Carry
Shift
Arithmetic
Serial
2
3
4
5
6
8
9
10
11
44
LCC
13
14
15
16
18
19
20
21
22
I/O
I
I
I/O
I/O
I/O
FCLK0/O
FCLK1/O
FCLK2/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/FI
I/O/FI
I/O/FI
18
15
FB4
FB3
FB1
FB2
X3492
June 1, 1996 (Version 1.0) 3- 149
conventional manner, triggered by the rising edge on its
clock input.
The clock source is programmable and is either the dedi-
cated product term mentioned ear lier, or one of two global
FastCLK signals (FLCK0 or FLCK1) that are distributed
with short delay and minimal skew over the whole chip.
The asynchronous Set and Reset (Clear) inputs override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set. Upon power-
up, each macrocell flip-flop can be preloaded with either 0
or 1.
In addition to driving a chip output pin, the macrocell output
is also routed back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output pin driver and/or the feedback to the
UIM. If configured to control UIM feedback, when the OE
product-term is de-asserted, the UIM feedback line is
forced High and thus disabled.
Universal Interconnect Matrix
The UIM receives 68 inputs: 36 from the macrocell feed-
backs, 30 from bidirectional I/O pins, and 2 from dedicated
input pins. Acting as an unrestricted crossbar switch, the
UIM generates 84 output signals, 21 to each FB.
Any one of the 68 inputs can be programmed to be con-
nected to any number of the 84 outputs. The delay through
the array is constant, independent of the apparent routing
distance, the fan-out, fan-in, or routing complexity.
Routability is not an issue in that any UIM input can drive
any UIM output or multiple outputs without additional delay.
When multiple inputs are programmed to be connected to
the same output, this output becomes the AND of the input
signals if the levels are interpreted as active High. By
choosing the appropriate signal inversion at the input pin,
macrocell outputs and FB AND-array input, this AND-logic
can also be used to implement a NAND, OR, or NOR func-
tion. This offers an additional level of logic without any
speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Several such macrocell outputs programmed onto the
same UIM output emulate a 3-state bus line. If one of the
macrocell outputs is enabled, the UIM output assumes that
same level.
Figure 2: FB and macrocell Schematic
I/O 
(see fig.3)
Clock
Select Register
Trasparent
Control
Input-Pad
Register/Latch
(optional)
Pin
Feedback
Polarity
Local 
Feedback
OE Control
Global
Fast OE
Arithmetic 
Carry-Out to Next 
Macrocell
Shift-In
from Previous MC
Shift-Out
to Next MC
To 8 More
Macrocells
* OE is forced high when P-term is not used
RESET
SET
OE*
CLOCK
5
ALU
D1
D2
C
in
C
out
F
R
S
Q
D
MUX
Fast
Clocks
0 1
Arithmetic Carry-In from
Previous Macrocell
1 of 9 Macrocells
Feedback
Enable
Override
Feedback to UIM
Input to UIM
84
21
Inputs
from
UIM
3
from
Fast
Input
Pins
(FI)
AND Array
12 Sharable
P-Terms per
Function Block
5 Private
P-Terms per
Macrocell
X1829
XC7236A 36-Macrocell CMOS CPLD
3- 150 June 1, 1996 (Version 1.0)
Outputs
Thirty-four of the 36 macrocell drive chip outputs directly
through individually programmable inverters followed by 3-
state output buffers; each can be individually controlled by
the Output Enable product term mentioned abov e. An addi-
tional configuration option disables the output permanently.
One dedicated F astOE input also can be configured to con-
trol any of the chip outputs instead of , or in conjunction with,
the individual OE product term.
Inputs
Each signal input to the chip is programmable as either
direct, latched, or registered in a flip flop . The latch and flip-
flop can be programmed with either of two FastCLK signals
as latch enable or clock. The two FastCLK signals are
FCLK0 and a global choice of either FCLK1 or FCLK2.
Latches are transparent when FastCLK is High, and flip-
flops clock on the rising edge of FastCLK. Registered
inputs allow high system cloc k rates by pipelining the inputs
before the y incur the combinatorial dela y in the de vice , pro-
vided the one-clock-period pipeline latency is acceptable.
The direct, latched, or registered inputs then drive the UIM.
There is no propagation-delay difference between pure
inputs and I/O inputs.
3.3 V or 5 V Interface configuration
The XC7236A can be used in systems with two different
supply voltages, 5 V and 3.3 V. The device has separate
VCC connections to the internal logic and input buffers
(VCCINT) and to the I/O output drivers (VCCIO). VCCINT is
always connected to a nominal +5 V supply, but VCCIO may
be connected to either +5 V or +3.3 V, depending on the
output interface requirement.
When VCCIO is connected to +5 V, the input thresholds are
TTL levels, and thus compatible with 5 V or 3.3 V logic , and
the output high levels are compatible with 5 V systems.
When VCCIO is connected to 3.3 V, the input thresholds are
still TTL levels, and the outputs pull up to the 3.3 V rail. This
makes the XC7236A ideal for interfacing directly to 3.3 V
components. In addition, the output structure is designed
such that the I/O can also safely interface to a mixed 3.3-V
and 5-V bus.
Figure 3: Input/Output Schematic
Feedback
to UIM
Macrocell
OE P-Term
From
Macrocell
Register
Global
Fast OE
Pin
I/O. FCLK/O
and FOE/O
Pins Only
QD
CLK
QD
EN
To UIM
To Function Block
AND-Array (on
Fast Input
Pins Only)
Input and
I/O Pins Only
Input
Polarity
Output
Polarity
Pin
Driver
MUXMUX
FastCLK1
FastCLK2
Global
Select
X5338
FastCLK0
I/O Pin
June 1, 1996 (Version 1.0) 3- 151
Programming and Using the XC7236A
The features and capabilities described above are used by
the Xilinx development software to program the device
according to the specification given either through sche-
matic entry, or through a behavioral description expressed
in Boolean equations.
The user can specify a security bit that prevents any read-
ing of the programming bit map after the device has been
programmed and verified.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex format. Programming support is avail-
able from a number of programmer manufacturers. The
UIM connections and FB AND-arra y connections are made
directly by non-volatile EPROM cells. Other control bits are
read out of the EPROM array and stored into latches just
after power-up. This method, common among EPLD
devices, requires application of a master-reset signal
delayed at least until VCC has reached the required operat-
ing voltage. This can be achieved using a simple capacitor
and pull-up resistor on the MR pin (the RC product should
be larger than twice the VCC rise time). The power-up or
reset signal initiates a self-timed configuration period last-
ing about 350 µs (tRESET), during which all device outputs
remain disabled and programmed preload state values are
loaded into the macrocell registers.
Unused input and I/O pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current through
the input pad circuitry.
The recommended decoupling capacitance on the three
VCC pins should total 1 µF using high-speed (tantalum or
ceramic) capacitors.
Figure 4: Typical ICC vs. Frequency for XC7236A
configured as sixteen 4-bit counters
(VCC = +5.0 V, VIN = VCC or GND, all outputs open)
X3255
0 5 10 15 20 25 30 35 40
25
50
75
100
125
150
Frequency (MHz)
Supply Current (mA)
TA = -55°C
TA = 25°C
TA = 125°C
XC7236A 36-Macrocell CMOS CPLD
3- 152 June 1, 1996 (Version 1.0)
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT/
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VCCIO I/O supply voltage 3.3 V 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 VCC +0.5 V
VOOutput voltage 0 VCCIO V
Symbol Parameter Test Conditions Min Max Units
VOH
5 V TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
3.3 V High-level output voltage IOH = -3.2 mA
VCC = Min 2.4 V
VOL
5 V TTL Low-level output voltage IOL = 24 mA
VCC = Min 0.5 V
3.3 V Low-level output voltage IOL = 24 mA
VCC = Min 0.4 V
ICC Supply current VIN = 0 V
VCC = Max
f = 0 MHz 126 Typ mA
IIL Input leakage current VCC = Max
VIN = GND or VCCIO -10 +10 µA
IOZ Output high-Z leakage current VCC = Max
VO = GND or VCCIO -100 +100 µA
CIN Input capacitance (sample tested) VIN = GND
f = 1.0 MHz 10 pF
June 1, 1996 (Version 1.0) 3- 153
AC Timing Requirements
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
2. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements.
Symbol Parameter Fig. XC7236A-25 XC7236A-20 XC7236A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
fCYC
(Note 1) Max sequential toggle frequency
(with feedback) using FastCLK 6 40 50 60 MHz
fCYC1
(Note 1) Max sequential toggle frequency
(with feedback) using a Product-Term Clock 6 40 50 60 MHz
fCYC4
(Note 2) Max macrocell toggle frequency
using local feedback and FastCLK 50 50 60 MHz
fCLK
(Note 2) Max macrocell register transmission frequency
(without feedback) using FastCLK 45 50 60 MHz
fCLK1
(Note 2) Max macrocell register transmission frequency
(without feedback) using a Product-Term Clock 42 50 60 MHz
fCLK2
(Note 2) Max input register transmission frequency
(without feedback) using FastCLK 50 50 60 MHz
fCLK3
(Note 1) Max input register to macrocell register pipeline
frequency using FastCLK 7 33 40 60 MHz
tWFastCLK pulse width (HIgh/Low) 11 10 8 6 ns
fTOG Export Control Max. flip-flop toggle rate 50 62 83 MHz
tW1 Product-term clock pulse width (active/inactive) 11 12 9 7 ns
tSU Input to macrocell register set-up time
before FastCLK 929 24 18 ns
t
HInput to macrocell register hold time
after FastCLK 9-7-4-4ns
t
SU1
(Note 1) Input to macrocell register set-up time
before Product-term clock 816 14 10 ns
t
H1 Input to macrocell register hold time
after Product-term clock 8000ns
t
SU2 Input to register/latch set-up time
before FastLCK 10 8 8 6 ns
tH2 Input to register/latch hold time
after FastLCK 10 0 0 0 ns
tSU5 FastInput to macrocell register set-up time
before FastCLK 20 18 15 ns
tH5 FastInput to macrocell register hold time
after FastCLK 000ns
t
WA Set/Reset pulse width (active) 11 12 12 10 ns
tRA Set/Reset input recovery set-up time
before FastCLK 11 30 25 20 ns
tHA Set/Reset input hold time
after FastCLK 11 -5 0 0 ns
tRA1 Set/Reset input recovery set-up time
before Product-term clock 11 15 15 12 ns
tHA1 Set/Reset input hold time
after Product-term clock 11 9 9 8 ns
tHRS Product-term clock width (active/inactive) 10 10 8 ns
XC7236A 36-Macrocell CMOS CPLD
3- 154 June 1, 1996 (Version 1.0)
Propagation Delays
Note: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
Incremental Parameters
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for an adder with
registered outputs.
3. Parameter tCOF2 is derived as the diff erence between the cloc k period for pipelining input-to-macrocell registers (1/fCLK3) and
the non-registered input set-up time (tSU).
4. Parameter tIN represents the delay from an input or I/O pin to a UIM-input (or from a FastCLK pin to the Fast CLK net); tOUT
represents the delay from a macrocell output (feedback point) to an output or I/O pin. Only the sum of tIN + tOUT can be
derived from measurements, e.g., tIN + tOUT = tSU + tCO - 1/fCYC.
Symbol Parameter Fig. XC7236A-25 XC7236A-20 XC7236A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
tCO FastCLK input to registered output delay 11 5 14 3 13 3 10 ns
tCO1 P-term clock input to registered output delay 11 10 30 5 24 5 20 ns
tAO Set/Reset input to registered output delay 11 10 40 5 32 5 25 ns
tPD
(Note 1) Input to non-registered output delay 11 10 40 5 32 5 25 ns
tOE Input to output enable 11 10 32 5 25 5 20 ns
tOD Input to output disable 11 10 32 5 25 5 20 ns
tPD5 FastInput to non-registered macrocell
output delay 1031525520ns
t
OE5 FastInput to output enable 5 23 3 20 3 15 ns
tOD5 FastInput to output disable 5 23 3 20 3 15 ns
tFOE FOE input to output enable 5 15 3 14 3 12 ns
tFOD FOD input to output disable 5 15 3 14 3 12 ns
Symbol Parameter Fig. XC7236A-25 XC7236A-20 XC7236A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
tPDT1
(Note 2) Arithmetic carry delay
between adjacent macrocells 12 1.2 1.2 1 ns
tPDT8
(Note 2) Arithmetic carry delay through 9 adjacent
macrocells in a FB 12 6 5 3 ns
tPDT9
(Note 2) Arithmetic carry delay through 10 macrocells
from macrocell #n to macrocell #n in next FB 12 9 6 4 ns
tCOF1 Incremental delay from UIM-input (for P-term
clock) to registered macrocell feedback 13 12 7 5 ns
tCOF2
(Note 3) Incremental delay from FastCLK net to
latched/registered UIM-input 13 1 1 1 ns
tPDF
(Note 1) Incremental delay from UIM-input to
non-registered macrocell feedback 13 22 14 10 ns
tAOF Incremental delay from UIM-input (Set/Reset) to
registered macrocell feedback 13 22 14 10 ns
tOEF
tODF
Incremental delay from UIM-input (used as out-
put-enable/disable) to macrocell feedback 13 14 7 5 ns
tIN + tOUT
(Note 4) Propagation delay
through unregistered input pad (to UIM)
plus output pad driver (from macrocell)
13 18 18 15 ns
June 1, 1996 (Version 1.0) 3- 155
Power-up/Reset Timing Parameters
Note: Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, VCC rise
must
be
monotonic. Following reset, the Clock, Reset and Set inputs must not be asserted until all applicable input and
feedback set-up times are met.
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
trVCC VCC rise time (if MR not used for power-up) 5 µs
tRESET Configuration completion time (to outputs operational) 350 1000 µs
Figure 5: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
OVTEST
5.0 V
3.3 V
R1
310 Ω
260 Ω
R2
195 Ω
360 Ω
CL
35 pF
35 pF
X3489
VCCIO
5.0 V
3.3 V
XC7236A 36-Macrocell CMOS CPLD
3- 156 June 1, 1996 (Version 1.0)
Timing and Delay Path Specifications
The delay path consists of three blocks that can be con-
nected in series:
• Input Buffer and associated latch or register
• Logic Resource (UIM, AND-array and macrocell)
• Three-state Output Buffer
All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regard-
less of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achiev-
able clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.
Timing and Delay Path Descriptions
Figure 6 defines the maximum clock frequency (with feed-
back). Any macrocell output can be fed back to the UIM as
an input for the next clock cycle. Figure 6 shows the rele-
vant delay path. The parameters fCYC and fCYC1 specify
the maximum operating frequency for FastCLK and prod-
uct-term clock operation respectively.
Figure 7 specifies the max operating frequency (fCLK3) for
pipelined operation between the input registers and the
macrocell registers, using FastCLK.
Figure 8 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register .
Figure 9 defines the set-up and hold times from the data
inputs to the FastCLK used by the output register.
Figure 10 defines the set-up and hold times from the data
input to the FastCLK used in an input register.
Figure 11 shows the waveforms for the macrocell and con-
trol paths
Figure 12 defines the carry propagation delays between
macrocells and between FBs. The par ameters describe the
delay from the C IN, D1 and D2 inputs of a macrocell ALU to
the CIN input of the adjacent macrocell ALU. These delays
must be added to the standard macrocell dela y path (tPD or
tSU) to determine the performance of an arithmetic func-
tion.
Figure 13 defines the incremental parameters for the stan-
dard macrocell logic paths. These incremental parameters
are used in conjunction with pin-to-pin parameters when
calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.
Figure 6: Delay Path Specification for fCYC and fCYC1
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
FASTCLK or
P-Term Clock
FASTCLK or
Product Term Clock
Output
Driver Output or
I/O Pin
Macrocell Register
Output
1/fCYC, 1/fCYC1
Macrocell
Register
D Q
X3279
June 1, 1996 (Version 1.0) 3- 157
Figure 7: Delay Path Specification for fCLK3
Figure 8: Delay Path Specification for fSU1 and fH1
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
FASTCLK
Output
Driver Output or
I/O Pin
Input-Pad
Register Output
Macrocell
Register
D Q
X3280
Input-Pad
Register
D Q
FASTCLK
Pin
1/fCLK3
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
Clock
Output
Output
Driver Output or
I/O Pin
Input or
I/O Pin
Macrocell
Register
D Q
X3281
tH1
tSU1
Data
Input or
I/O Pin
XC7236A 36-Macrocell CMOS CPLD
3- 158 June 1, 1996 (Version 1.0)
Figure 9: Delay Path Specification for fSU and fH
Figure 10: Delay Path Specification for fSU2 and fH2
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
Output
Driver Output or
I/O Pin
Macrocell
Register
D Q
X3282
FASTCLK
Pin
FASTCLK
Input
Input or
I/O Pin
- tH
tSU
Data
Input or
I/O Pin
UIM
Input or
I/O Pin
Input-Pad
Register
D Q
X3283
FASTCLK
Pin
FASTCLK
Pin
tH2
tSU2
Data
June 1, 1996 (Version 1.0) 3- 159
Figure 11: Principal Pin-to-Pin Measurements
Figure 12: Arithmetic Timing Parameters
tH2*
Active
tSU2*
tH2*
tSU2*
tWL tWH
tW1 tW1
tH
tH1
tSU1
tSU
tCO1
tCO
tPD tOD tOE
tAO
tHA1 tRA1
tWA
tHA tRA
Inactive Active Inactive Active
ActiveActive Inactive
Active Inactive
Valid Disable Valid Enable Valid Reset/Set Reset/Set
De-Asserted
Registered
Inputs
FastCLK
Input Used
as Clock
Unlatched
Inputs
Non-Registered
Outputs
Registered
Outputs
tSU2 and tH2 are measured with respect to the high-going
edge of FastCLK for registered inputs, and with respect to
the low-going edge of FastCLK for latched inputs. Only the
high going edge is used for clocking the macrocell registers.
*
X3284
Cin
D1, D2 F
Cin
D1, D2 F
Cout Macrocell
Register
Cin
D1, D2 F
Cout Macrocell
Register
Cin
D1, D2 F
Cout Macrocell
Register
A0
A1
A8
A9 S9
S8
S0
S1
UIM Function Block
ALU
ALU
ALU
ALU
MC2
MC9
MC1
MC1
tPDT1
tPDT1
tPDT8
tPDT9
tPDF
tIN tOUT
AND/OR
AND/OR
Function Block
X3287
Macrocell
Register
XC7236A 36-Macrocell CMOS CPLD
3- 160 June 1, 1996 (Version 1.0)
Figure 13: Incremental Timing Parameters
Input or
I/O Pin
D Q
D Q
D Q
C/E
FASTCLK
Pin X3288
tAOF
tCOF
tCOF2
tOUT
tOUT
tOUT
tIN
tIN
tIN
tIN
Output or
I/O Pin
Input or
I/O Pin
Input or
I/O Pin
Output or
I/O Pin
Output or
I/O Pin
tCOF1
AND-Array
ALU Logic
Macrocell
Register
UIM Function Block
tTPDF
AND-Array
ALU Logic
AND-Array
ALU Logic
R S
June 1, 1996 (Version 1.0) 3- 161
XC7372 Pinouts
Pin # Input Output
1 Master Reset VPP
2 Input MC2-1
3 Input
4 Input
5 Input MC2-4
6 Input MC2-5
7 GND
8 Input MC2-6
9 FastCLK0 MC2-7
10 FastCLK1 MC2-8
11 FastCLK2 MC2-9
12 VCCIO
13 Input MC1-1
14 Input MC1-2
15 Input MC1-3
16 Input MC1-4
17 GND
18 Input MC1-5
19 Input MC1-6
20 Input/FI MC1-7
21 Input/FI MC1-8
22 Input/FI MC1-9
Pin # Input Output
23 VCCIO
24 Input/FI MC4-9
25 Input/FI MC4-8
26 Input/FI MC4-7
27 Input MC4-6
28 Input MC4-5
29 GND
30 Input MC4-4
31 Input MC4-3
32 FastOE MC4-2
33 Input MC4-1
34 VCCINT
35 Input/FI MC3-9
36 Input/FI MC3-8
37 Input/FI MC3-7
38 Input MC3-6
39 GND
40 Input MC3-5
41 Input MC3-4
42 Input MC3-3
43 Input MC3-2
44 Input MC3-1
XC7236A 36-Macrocell CMOS CPLD
3- 162 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C M = Military = –55°C(A) to 125°C (C)
Pins 44
Type Plastic
PLCC Ceramic
CLCC
Code PC44 WC44
XC7236A –25 CI CIM
–20 CI CIM
–16 CI CI
XC7236A - 16 PC 44 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-25 25 ns (40 MHz) sequential cycle time
-20 20 ns (50 MHz) sequential cycle time
-16 16 ns (60 MHz) sequential cycle time (commercial/industrial only)
Packaging Options
PC44 44-Pin Plastic Leaded Chip Carrier
WC44 44-Pin Windowed Ceramic Leaded Chip Carrier
Temperature Options
C Commercial0°C to 70°C
I Industrial -40°C to 85°C
M Military -55°C (Ambient) to 125°C (Case)
June 1, 1996 (Version 1.0) 3- 163
Features
• Second-Generation High Density Programmable Logic
Device
• UV-erasable CMOS EPROM technology
• 72 macrocells, grouped into eight Function Blocks
(FBs), interconnected by a programmable Universal
Interconnect Matrix
• Each FB contains a programmable AND-array with 21
complementary inputs, providing up to 16 product terms
per macrocell
• Enhanced logic features:
- 2-input Arithmetic Logic Unit in each macrocell
- Dedicated fast carry network between macrocells
- Wide AND capability in the Universal Interconnect
Matrix
• Identical timing for all interconnect paths and for all
macrocell logic paths
• 72 signal pins in the 84-pin packages
- 42 I/Os, 12 inputs, 18 outputs
• Each input is programmable
- Direct, latched, or registered
• I/O-pin is usable as input when macrocell is buried
• Two high-speed, low-skew global clock inputs
• A vailable in 68-pin and 84-pin PLCC/CLCC , 84-pin PGA
packages
General Description
The XC7272A combines the classical features of the PAL-
like CPLD architecture with innovative systems-oriented
logic enhancements. This favors the implementation of fast
state machines, large synchronous counters and fast arith-
metic, as well as multi-level general-pur pose logic. Perfor-
mance, measured in achievable system clock rate and
critical delays, is not only predictable, but independent of
physical logic mapping, interconnect routing, and resource
utilization. Performance, therefore, remains invariant
between design iterations. The propagation delay through
interconnect and logic is constant for any function imple-
mented in any one of the output macrocells.
The functional versatility of the traditional programmable
logic arra y architecture is enhanced through additional gat-
ing and control functions available in an Arithmetic Logic
Unit (ALU) in each macrocell. Dedicated fast arithmetic
carry lines running directly between adjacent macrocells
and FBs suppor t fast adders, subtractors and comparators
of any length up to 72 bits.
This additional ALU in each macrocell can generate any
combinatorial function of two sums of products, and it can
generate and propagate arithmetic-carry signals between
adjacent macrocells and Functional Blocks.
The Universal Interconnect Matrix (UIM) facilitates unre-
stricted, fixed-delay interconnects from all device inputs
and macrocell outputs to any Function Block AND-array
input. The UIM can also perfor m a logical AND across any
number of its incoming signals on the wa y to any Functional
Block, adding another le v el of logic without additional delay.
This suppor ts bidirectional loadable synchronous counters
of any size up to 72 bits, operating at the specified maxi-
mum device frequency
As a result of these logic enhancements, the XC7272A can
deliver high performance even in designs that combine
large numbers of product terms per output, or need more
layers of logic than AND-OR, or need a wide AND function
in some of the product terms, or perform wide arithmetic
functions.
Architectural Overview
Figure 1 shows the XC7272A structure. Eight Function
Blocks(FBs) are all interconnected by a central UIM. Each
FB receives 21 signals from the UIM and each FB produces
nine signals back into the UIM. All device inputs are also
routed via the UIM to all FBs. Each FB contains nine output
macrocells that draw from a programmable AND array
driven by the 21 signals from the UIM. Most Macro-cells
drive a 3-state chip output. All feed back into the UIM.
XC7272A
72-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0) Product Specification
XC7272A 72-Macrocell CMOS CPLD
3- 164 June 1, 1996 (Version 1.0)
Figure 1: XC7272A Architecture
22
36
I/O
I/O
I/O
I/O
74
75
76
77
84
LCC
O
O
O
O
O
O
O
O
65
66
67
68
70
71
72
73
MC6-9
MC6-8
MC6-7
MC6-6
MC6-5
MC6-4
MC6-3
MC6-2
MC6-1
AND ARRAY
MC5-9
MC5-8
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
AND ARRAY
21
21
2121
UIM
AND ARRAY AND ARRAY
MC3-1
MC3-2
MC3-3
MC3-4
MC3-5
MC3-6
MC3-7
MC3-8
MC3-9
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
CarryArithmetic
12
11
10
9
84
LCC
21
20
19
18
16
15
14
13
I/O
I/O
FCLK/O
FCLK/O
O
O
O
O
O
O
O
O
36
20
FB6
FB5
FB3
FB4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
54
55
56
57
58
60
61
62
63
MC7-9
MC7-8
MC7-7
MC7-6
MC7-5
MC7-4
MC7-3
MC7-2
MC7-1
AND ARRAY
2121
AND ARRAY
MC2-1
MC2-2
MC2-3
MC2-4
MC2-5
MC2-6
MC2-7
MC2-8
MC2-9
32
31
30
29
28
26
25
24
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FB7FB2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
44
45
46
47
48
50
51
52
53
Arithmetic Carry
MC8-9
MC8-8
MC8-7
MC8-6
MC8-5
MC8-4
MC8-3
MC8-2
MC8-1
AND ARRAY
2121
AND ARRAY
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
42
41
40
39
38
36
35
34
33
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FB8FB1
X3493
I
I
I
I
I
I
I
I
I
I
II
I
7
6
5
4
3
2
84
83
82
81
80
79
[5]
[4]
[3]
*
*
[2]
*
*
[68]
[67]
[66]
[65]
12
* = Pin not present on 68 LCC
[10]
[9]
[8]
[7]
68
LCC
*
*
*
*
[14]
[13]
[12]
[11]
[26]
[25]
[24]
[23]
[22]
[20]
[19]
[18]
[17]
*
*
[34]
[33]
[32]
[30]
[29]
[28]
[27]
[60]
[61]
[62]
[63]
68
LCC
[55]
[56]
[57]
[58]
*
*
*
*
[44]
[45]
[46]
[47]
[48]
[50]
[51]
[52]
[53]
*
*
[36]
[37]
[38]
[40]
[41]
[42]
[43]
June 1, 1996 (Version 1.0) 3- 165
Function Blocks and Macrocells
The XC7272A contains 72 identical macrocells, grouped
into eight FBs of nine macrocells each. Each macrocell is
driven by product terms derived from the 21 inputs from the
UIM into the Function Block. Figure 2 shows the macrocell
structure.
Five product terms are private to each macrocell; an addi-
tional 12 product terms are shared among the nine macro-
cells in any Function Block. One private product term is a
dedicated clock for the flip-flop in the macrocell.
The remaining four priv ate product terms can be selectively
ORed together with up to three of the shared product
terms, to drive one input to an Arithmetic Logic Unit (ALU).
The other input to the ALU is driven by the OR of up-to-nine
product terms from the remaining shared product terms.
As a programmab le option, two of the private product terms
can be used for other purposes. One is the asynchronous
active-High Reset of the macrocell flip-flop, the other can
be either an asynchronous active-High Set of the macrocell
flip-flop, or provide an active-High Output-Enable signal
from any one of the Function Block inputs.
The ALU has two programmable modes. In the
logic mode,
it is a 2-input function generator, a 4-bit look-up table, that
can be programmed to generate an y Boolean function of its
two inputs. It can OR them, widening the OR function to 16
inputs; it can AND them, which means that one sum of
products can be used to mask the other; it can XOR them,
toggling the flip-flop or comparing the two sums of prod-
ucts. Either or both of the sum-of-product inputs to the ALU
can be inverted, and either or both can be ignored. The
ALU can implement one additional layer of logic without
any speed penalty.
In the
arithmetic mode,
the ALU block can be programmed
to generate the arithmetic sum or difference of two oper-
ands, combined with a carry signal coming from the lower
macrocell; it also feeds a carry output to the next higher
macrocell. This carry propagation chain crosses the bound-
aries between FBs, but it can also be configured as a 0 or 1
when it enters a Function Block.
This dedicated carry chain overcomes the inherent speed
and density problems of the traditional CPLD architecture,
when trying to perform arithmetic functions like add, sub-
tract, and magnitude compare.
Figure 2: Function Block and Macrocell Schematic
I/O Pad
Clock
Select Register
Trasparent
Control
Input-Pad
Register/Latch
(optional)
Pin
Arithmetic 
Carry-Out to Next 
Macrocell
To 8 More
Macrocells
* OE is forced high when P-term is not used
RESET
SET
OE*
CLOCK
5
ALU
D1
D2
C
in
C
out
F
R
S
Q
D
MUX
Fast
Clocks
0 1
Arithmetic Carry-In from
Previous Macrocell
1 of 9 Macrocells
Feedback to UIM
Input to UIM
93
21
Inputs
from
UIM
AND Array
12 Sharable
P-Terms per
Function Block
5 Private
P-Terms per
Macrocell
X5490
MUX
One Function Block
XC7272A 72-Macrocell CMOS CPLD
3- 166 June 1, 1996 (Version 1.0)
The ALU output drives the D input of the macrocell flip-flop .
Each flip-flop has several programmable options:
One option is to eliminate the flip-flop by making it transpar-
ent, which makes the Q output identical with the D input,
independent of the clock.
If this option is
not
programmed, the flip-flop operates in the
conventional manner, triggered by the rising edge on its
clock input.
The clock source is programmable: It is either the dedi-
cated product term mentioned above, or it is one of the tw o
global FastCLK signals that are distributed with short delay
and minimal skew over the whole chip.
The asynchronous Set and Reset (Clear) inputs override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set. Upon power-
up, each macrocell flip-flop can be preloaded with either 0
or 1.
In addition to driving the chip output buffer, the macrocell
output is also routed back as an input to the UIM. When the
Output Enable product term mentioned abov e is not active,
this feedback line is forced High and thus disabled.
Universal Interconnect Matrix
The UIM receives 126 inputs: 72 from the 72 macrocells , 42
from bidirectional I/O pins, and 12 from dedicated input
pins. Acting as an unrestricted crossbar switch, the UIM
generates 168 output signals, 21 to each Function Block.
Any one of the 126 inputs can be programmed to be con-
nected to any number of the 168 outputs. The delay
through the array is constant, independent of the apparent
routing distance, the fan-out, fan-in, or routing complexity.
Routability is not an issue: Any UIM input can drive an y UIM
output, even multiple outputs, and the delay is constant.
When multiple inputs are programmed to be connected to
the same output, this output becomes the AND of the input
signals if the levels are interpreted as active High. By
choosing the appropriate signal inversion in the macrocell
outputs and the Function Block AND-array input, this AND-
logic can also be used to implement a NAND, OR, or NOR
function, thus offering an additional level of logic without
any speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Several such macrocell outputs programmed onto the
same UIM output emulate a 3-state bus line. If one of the
macrocell outputs is enabled, the UIM output assumes that
same level.
Figure 3: Input/Output Schematic
Feedback
to UIM
Macrocell
OE P-Term
From
Macrocell
Register I/O Pin
Output I/O
and FCLK/O
Pins Only
QD
CLK
QD
EN
To UIM
Input and
I/O Pins Only
Pin
Driver
MUXMUX
X5339
FastCLK1
FastCLK0
June 1, 1996 (Version 1.0) 3- 167
Outputs
Sixty of the 72 macrocells drive chip outputs directly
through 3-state output buffers, each individually controlled
by the Output Enable product term mentioned above. For
bidirectional I/O pins, an additional programmable cell can
optionally disable the output permanently. The buried flip-
flop is then still available for inter nal feedback, and the pin
can still be used as a separate input
Inputs
Each signal input to the chip is programmable as either
direct, latched, or registered in a flip-flop . The latch and flip-
flop can be programmed with either of the two FastCLK sig-
nals as latch enable or cloc k. The latch is tr ansparent when
FastCLK is High, and the flip-flop clocks on the rising edge
of FastCLK. Registered inputs allow high system clock
rates by pipelining the inputs bef ore they incur the combina-
torial delay in the device, in cases where a pipeline cycle is
acceptable.
The direct, latched, or registered inputs then drive the UIM.
There is no propagation-delay difference between pure
inputs and I/O inputs.
Programming and Using the
XC7272A
The features and capabilities described above are used by
the Xilinx XACT
step
development software to program the
device according to the specification given either through
schematic entry, or through a behavioral description
expressed in Boolean equations.
The user can specify a security bit that prevents any read-
ing of the programming bit map after the device has been
programmed and verified.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex or JEDEC f ormat. Progr amming support
is available from a number of programmer manufacturers.
The UIM connections and Function Block AND-array con-
nections are made directly by non-volatile EPROM cells.
Other control bits are read out of the EPROM array and
stored into latches just after power-up. This method, com-
mon among CPLD devices, requires either a very fast VCC
rise time (<5 µs) or the application of a master-reset signal
delay ed at least until VCC has reached the required operat-
ing voltage. The latter can be achieved using a simple
capacitor and pull-up resistor on the MR pin (the RC prod-
uct should be larger than twice the VCC rise time). The
power-up or reset signal initiates a self-timed configuration
period lasting about 350 µs (tRESET), during which all
device outputs remain disabled and programmed preload
state values are loaded into the macrocell registers.
Unused input and I/O pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current through
the input-pad circuitry.
The recommended decoupling capacitance on the three
VCC pins should total 1 µF using high-speed (tantalum or
ceramic) capacitors.
Figure 4: Typical ICC vs. Frequency for XC7272A configured as sixteen 4-bit counters
(VCC = +5.0 V, VIN = VCC or GND, all outputs open)
X3254
0 5 10 15 20 25 30 35 40
50
100
150
200
250
300
350
Count Frequency (MHz)
Supply Current (mA)
TA = -55°C
TA = 25°C
TA = 125°C
XC7272A 72-Macrocell CMOS CPLD
3- 168 June 1, 1996 (Version 1.0)
Absolute Maximum Ratings
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to VCC +0.5 V
VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to 7.0 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
Symbol Parameter Min Max Units
VCCINT/
VCCIO
Supply voltage relative to GND Commercial TA = 0°C to 70°C 4.75 5.25 V
Supply voltage relative to GND Industrial TA = –40°C to 85°C 4.5 5.5 V
Supply voltage relative to GND Military TA = –55°C to TC + 125°C 4.5 5.5 V
VIH High-level input voltage 2.0 VCC +0.5 V
VIL Low-level input voltage 0 0.8 V
Symbol Parameter Test Conditions Min Max Units
VOH TTL High-level output voltage IOH = -4.0 mA
VCC = Min 2.4 V
VOL TTL Low-level output voltage IOL = 8 mA
VCC = Min 0.5 V
ICC Supply current VIN = 0 V
VCC = Max
f = 0 MHz 222 Typ mA
IIL Input leakage current -10 +10 µA
IOZ Output high-Z leakage current -100 +100 µA
CIN Input capacitance (sample tested) 10 pF
June 1, 1996 (Version 1.0) 3- 169
AC Timing Requirements
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
2. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements.
Symbol Parameter Fig. XC7272A-25 XC7272A-20 XC7272A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
fCYC
(Note 1) Max sequential toggle frequency
(with feedback) using FastCLK 40 50 55 MHz
fCYC1
(Note 1) Max sequential toggle frequency
(with feedback) using a Product-Term Clock 40 50 55 MHz
fCLK
(Note 2) Max macrocell register transmission frequency
(without feedback) using FastCLK 40 50 55 MHz
fCLK1
(Note 2) Max macrocell register transmission frequency
(without feedback) using a Product-Term Clock 40 50 55 MHz
fCLK2
(Note 2) Max input register transmission frequency
(without feedback) using FastCLK 67 67 67 MHz
fCLK3
(Note 1) Max input register to macrocell register pipeline
frequency using FastCLK 7 40 50 60 MHz
tWL FastCLK Low pulse width 11 7.5 7.5 6 ns
tWH FastCLK High pulse width 11 7.5 7.5 6 ns
fTOG Export Control Max. flip-flop toggle rate 67 67 83 MHz
tW1 Product-term clock pulse width (active/inactive) 11 10 9 7 ns
tSU Input to macrocell register set-up time
before FastCLK 924 19 15 ns
t
HInput to macrocell register hold time
after FastCLK 9-7-4-4ns
t
SU1
(Note 1) Input to macrocell register set-up time
before Product-term clock 810 8 6 ns
t
H1 Input to macrocell register hold time
after Product-term clock 8000ns
t
SU2 Input to register/latch set-up time
before FastLCK 10 8 8 6 ns
tH2 Input to register/latch hold time
after FastLCK 10 0 0 0 ns
tWA Set/Reset pulse width 11 12 10 8 ns
tRA Set/Reset input recovery set-up time
before FastCLK 11 20 20 16 ns
tHA Set/Reset input hold time
after FastCLK 11 -5 -3 -3 ns
tRA1 Set/Reset input recovery set-up time
before Product-term clock 11 6 5 4 ns
tHA1 Set/Reset input hold time
after Product-term clock 11 9 8 6 ns
tHRS Set/Reset input hold time
after Reset/Set inactive 10 8 6 ns
XC7272A 72-Macrocell CMOS CPLD
3- 170 June 1, 1996 (Version 1.0)
Propagation Delays
Note: 1. Specifications account for logic paths which use the maximum number of available product terms and the ALU.
Incremental Parameters
Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for an adder with
registered outputs.
3. Parameter tCOF2 is derived as the diff erence between the cloc k period for pipelining input-to-macrocell registers (1/fCLK3) and
the non-registered input set-up time (tSU).
4. Parameter tIN represents the delay from an input or I/O pin to a UIM-input (or from a FastCLK pin to the Fast CLK net); tOUT
represents the delay from a macrocell output (feedback point) to an output or I/O pin. Only the sum of tIN + tOUT can be
derived from measurements, e.g., tIN + tOUT = tSU + tCO - 1/fCYC.
Symbol Parameter Fig. XC7272A-25 XC7272A-20 XC7272A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
tCO FastCLK input to registered output delay 11 5 16 3 14 3 12 ns
tCO1 P-term clock input to registered output delay 11 10 30 6 25 6 21 ns
tAO Set/Reset input to registered output delay 11 13 40 8 32 8 25 ns
tPDD
(Note 1) Input to non-registered output delay 11 13 40 8 32 8 25 ns
tOE Input to output enable 11 11 32 7 25 7 22 ns
tOD Input to output disable 11 32 7 25 7 22 ns
Symbol Parameter Fig. XC7272A-25 XC7272A-20 XC7272A-16
(Com/Ind only)
Units
Min Max Min Max Min Max
tPDT1
(Note 2) Arithmetic carry delay
between adjacent macrocells 12 1.6 1.2 1 ns
tPDT8
(Note 2) Arithmetic carry delay through 9 adjacent
macrocells in a FB 12 10 8 6 ns
tPDT9
(Note 2) Arithmetic carry delay through 10 macrocells
from macrocell #n to macrocell #n in next FB 12 14 12 10 ns
tCOF Incremental delay from FastCLK net to registered
output feedback 13 1 1 1 ns
tCOF1 Incremental delay from UIM-input (for P-term
clock) to registered macrocell feedback 13 1.5 12 10 ns
tCOF2
(Note 3) Incremental delay from FastCLK net to
latched/registered UIM-input 13 1 1 1 ns
tPDF
(Note 1) Incremental delay from UIM-input to
non-registered macrocell feedback 13 25 19 14 ns
tAOF Incremental delay from UIM-input (Set/Reset) to
registered macrocell feedback 13 25 19 14 ns
tOEF
tODF
Incremental delay from UIM-input (used as out-
put-enable/disable) to macrocell feedback 13 17 12 11 ns
tIN + tOUT
(Note 4) Propagation delay
through unregistered input pad (to UIM)
plus output pad driver (from macrocell)
13 15 13 11 ns
June 1, 1996 (Version 1.0) 3- 171
Power-up/Reset Timing Parameters
Symbol Parameter Min Typ Max Units
tWMR Master Reset input Low pulse width 100 ns
trVCC VCC rise time (if MR not used for power-up) 5 µs
tRESET Configuration completion time (to outputs operational) 350 1000 µs
Figure 5: AC Load Circuit
R1
VTEST
Test Point
CL
R2
Device Output
Device Imput
Rise and Fall
Times < 3 ns
Output Type
OVTEST
5.0 V R1
450 ΩR2
245 ΩCL
35 pF
VCCIO
5.0 V
X3490
XC7272A 72-Macrocell CMOS CPLD
3- 172 June 1, 1996 (Version 1.0)
Timing and Delay Path Specifications
The delay path consists of three blocks that can be con-
nected in series:
• Input Buffer and associated latch or register
• Logic Resource (UIM, AND-array and macrocell)
• Three-state Output Buffer
All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regard-
less of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achiev-
able clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.
Timing and Delay Path Descriptions
Figure 6 defines the maximum clock frequency (with feed-
back). Any macrocell output can be fed back to the UIM as
an input for the next clock cycle. Figure 6 shows the rele-
vant delay path. The parameters fCYC and fCYC1 specify
the maximum operating frequency for FastCLK and prod-
uct-term clock operation respectively.
Figure 7 specifies the max operating frequency (fCLK3) for
pipelined operation between the input registers and the
macrocell registers, using FastCLK.
Figure 8 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register .
Figure 9 defines the set-up and hold times from the data
inputs to the FastCLK used by the output register.
Figure 10 defines the set-up and hold times from the data
input to the FastCLK used in an input register.
Figure 11 shows the waveforms for the macrocell and con-
trol paths
Figure 12 defines the carry propagation delays between
macrocells and between FBs. The par ameters describe the
delay from the C IN, D1 and D2 inputs of a macrocell ALU to
the CIN input of the adjacent macrocell ALU. These delays
must be added to the standard macrocell dela y path (tPD or
tSU) to determine the performance of an arithmetic func-
tion.
Figure 13 defines the incremental parameters for the stan-
dard macrocell logic paths. These incremental parameters
are used in conjunction with pin-to-pin parameters when
calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.
Figure 6: Delay Path Specification for fCYC and fCYC1
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
FASTCLK or
P-Term Clock
FASTCLK or
Product Term Clock
Output
Driver Output or
I/O Pin
Macrocell Register
Output
1/fCYC, 1/fCYC1
Macrocell
Register
D Q
X3279
June 1, 1996 (Version 1.0) 3- 173
Figure 7: Delay Path Specification for fCLK3
Figure 8: Delay Path Specification for fSU1 and fH1
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
FASTCLK
Output
Driver Output or
I/O Pin
Input-Pad
Register Output
Macrocell
Register
D Q
X3280
Input-Pad
Register
D Q
FASTCLK
Pin
1/fCLK3
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
Clock
Output
Output
Driver Output or
I/O Pin
Input or
I/O Pin
Macrocell
Register
D Q
X3281
tH1
tSU1
Data
Input or
I/O Pin
XC7272A 72-Macrocell CMOS CPLD
3- 174 June 1, 1996 (Version 1.0)
Figure 9: Delay Path Specification for fSU and fH
Figure 10: Delay Path Specification for fSU2 and fH2
Input or
I/O Pin
UIM Function Block
AND-Array,
ALU Logic
Output
Driver Output or
I/O Pin
Macrocell
Register
D Q
X3282
FASTCLK
Pin
FASTCLK
Input
Input or
I/O Pin
- tH
tSU
Data
Input or
I/O Pin
UIM
Input or
I/O Pin
Input-Pad
Register
D Q
X3283
FASTCLK
Pin
FASTCLK
Pin
tH2
tSU2
Data
June 1, 1996 (Version 1.0) 3- 175
Figure 11: Principal Pin-to-Pin Measurements
Figure 12: Arithmetic Timing Parameters
tH2*
Active
tSU2*
tH2*
tSU2*
tWL tWH
tW1 tW1
tH
tH1
tSU1
tSU
tCO1
tCO
tPD tOD tOE
tAO
tHA1 tRA1
tWA
tHA tRA
Inactive Active Inactive Active
ActiveActive Inactive
Active Inactive
Valid Disable Valid Enable Valid Reset/Set Reset/Set
De-Asserted
Registered
Inputs
FastCLK
Input Used
as Clock
Unlatched
Inputs
Non-Registered
Outputs
Registered
Outputs
tSU2 and tH2 are measured with respect to the high-going
edge of FastCLK for registered inputs, and with respect to
the low-going edge of FastCLK for latched inputs. Only the
high going edge is used for clocking the macrocell registers.
*
X3284
Cin
D1, D2 F
Cin
D1, D2 F
Cout Macrocell
Register
Cin
D1, D2 F
Cout Macrocell
Register
Cin
D1, D2 F
Cout Macrocell
Register
A0
A1
A8
A9 S9
S8
S0
S1
UIM Function Block
ALU
ALU
ALU
ALU
MC2
MC9
MC1
MC1
tPDT1
tPDT1
tPDT8
tPDT9
tPDF
tIN tOUT
AND/OR
AND/OR
Function Block
X3287
Macrocell
Register
XC7272A 72-Macrocell CMOS CPLD
3- 176 June 1, 1996 (Version 1.0)
Figure 13: Incremental Timing Parameters
Input or
I/O Pin
D Q
D Q
D Q
C/E
FASTCLK
Pin X3288
tAOF
tCOF
tCOF2
tOUT
tOUT
tOUT
tIN
tIN
tIN
tIN
Output or
I/O Pin
Input or
I/O Pin
Input or
I/O Pin
Output or
I/O Pin
Output or
I/O Pin
tCOF1
AND-Array
ALU Logic
Macrocell
Register
UIM Function Block
tTPDF
AND-Array
ALU Logic
AND-Array
ALU Logic
R S
June 1, 1996 (Version 1.0) 3- 177
XC7372 Pinouts
PC68 in XC7272A out PC84 PG84
1 Master Reset 1 F-9
2 Input 2 F-11
- Input 3 E-11
- Input 4 E-10
3 Input 5 E-9
4 Input 6 D-11
5 Input 7 D-10
6GND 8 C-11
7 Fast CLK0 MC4-4 9 B-11
8 Fast CLK1 MC4-3 10 C-10
9 Input MC4-2 11 A-11
10 Input MC4-1 12 B-10
11 MC3-8 13 B-9
12 MC3-7 14 A-10
13 MC3-6 15 A-9
14 MC3-5 16 B-8
15 GND 17 A-8
- MC3-4 18 B-6
- MC3-3 19 B-7
- MC3-2 20 A-7
- MC3-1 21 C-7
16 Vcc 22 C-6
17 Input MC2-9 23 A-6
18 Input MC2-8 24 A-5
19 Input MC2-7 25 B-5
20 Input MC2-6 26 C-5
21 GND 27 A-4
22 Input MC2-5 28 B-4
23 Input MC2-4 29 A-3
24 Input MC2-3 30 A-2
25 Input MC2-2 31 B-3
26 Input MC2-1 32 A-1
27 Input MC1-9 33 B-2
28 Input MC1-8 34 C-2
29 Input MC1-7 35 B-1
30 Input MC1-6 36 C-1
31 GND 37 D-2
32 Input MC1-5 38 D-1
33 Input MC1-4 39 E-3
34 Input MC1-3 40 E-2
- Input MC1-2 41 E-1
- Input MC1-1 42 F-2
PC68 in XC7272A out PC84 PG84
35 Vcc 43 F-3
- Input MC8-9 44 G-3
- Input MC8-8 45 G-1
36 Input MC8-7 46 G-2
37 Input MC8-6 47 F-1
38 Input MC8-5 48 H-1
39 GND 49 H-2
40 Input MC8-4 50 J-1
41 Input MC8-3 51 K-1
42 Input MC8-2 52 J-2
43 Input MC8-1 53 L-1
44 Input MC7-9 54 K-2
45 Input MC7-8 55 K-3
46 Input MC7-7 56 L-2
47 Input MC7-6 57 L-3
48 Input MC7-5 58 K-4
49 GND 59 L-4
50 Input MC7-4 60 J-5
51 Input MC7-3 61 K-5
52 Input MC7-2 62 L-5
53 Input MC7-1 63 K-6
54 Vcc 64 J-6
55 MC6-8 65 J-7
56 MC6-7 66 L-7
57 MC6-6 67 K-7
58 MC6-5 68 L-6
59 GND 69 L-8
- MC6-4 70 K-8
- MC6-3 71 L-9
- MC6-2 72 L-10
- MC6-1 73 K-9
60 Input MC5-4 74 L-11
61 Input MC5-3 75 K-10
62 Input MC5-2 76 J-10
63 Input MC5-1 77 K-11
64 GND 78 J-11
65 Input 79 H-10
66 Input 80 H-11
67 Input 81 F-10
68 Input 82 G-10
- Input 83 G-11
- Input 84 G-9
XC7272A 72-Macrocell CMOS CPLD
3- 178 June 1, 1996 (Version 1.0)
Ordering Information
Component Availability
C = Commercial = 0° to +70°C I = Industrial = –40° to 85°C M = Military = –55°C(A) to 125°C (C)
Pins 68 84
Type Plastic
PLCC Ceramic
CLCC Plastic
PLCC Ceramic
CLCC Ceramic
PGA
Code PC68 WC68 PC84 WC84 PG84
XC7272A –25 CI CI CI CIM CI
–20 CI CI CI CIM CI
–16 CI CI CI CI CI
XC7272A - 16 PC 84 C
Speed Number of Pins
Temperature Range
P ackage Type
De vice Type
Speed Options
-25 25 ns (40 MHz) sequential cycle time
-20 20 ns (50 MHz) sequential cycle time
-16 16 ns (60 MHz) sequential cycle time (commercial/industrial only)
Packaging Options
PC68 68-Pin Plastic Leaded Chip Carrier
WC68 68-Pin Windowed Ceramic Leaded Chip Carrier
PC84 84-Pin Plastic Leaded Chip Carrier
WC84 84-Pin Windowed Ceramic Leaded Chip Carrier
PG84 84-Pin Ceramic Windowed Pin Grid Array
Temperature Options
C Commercial0°C to 70°C
I Industrial -40°C to 85°C
M Military -55°C (Ambient) to 125°C (Case)
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
SRAM-Based FPGA Products
SRAM-Based FPGA Products
XC4000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
XC4000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
XC5200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-179
XC5200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
XC5200L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
XC6200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-251
XC6200 Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253
XC3000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287
XC3000 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
XC3000A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
XC3000L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
XC3100A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
XC3100L Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
SRAM-Based FPGA Products Table
of Contents
4-1
XC4000 Series Field Programmable Gate Arrays
XC4000-Series Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Additional XC4000EX/XL Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
XC4000E and XC4000EX Families Compared to the XC4000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Improvements in XC4000E and XC4000EX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Additional Improvements in XC4000EX Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Configurable Logic Blocks (CLBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Function Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Latches (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Data Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Using Function Generators as RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Input/Output Blocks (IOBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
IOB Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Three-State Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Quad Lines (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Direct Interconnect (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Octal I/O Routing (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Global Nets and Buffers (XC4000EX only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
XC4000 Series Table of Contents
XC4000 Series Table of Contents
4-2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Avoiding Inadvertent Boundary Scan Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
Cyclic Redundancy Check (CRC) for Configuration and Readback. . . . . . . . . . . . . . . . . . . . . . 4-57
Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Configuration Memory Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62
Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Release of Global Set/Reset After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63
Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . 4-65
Readback with the XChecker Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68
Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72
Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
XC4000E Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . 4-83
XC4000E CLB Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
4-3
XC4000E CLB Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . . . . . 4-85
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines . . . . 4-86
XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic
Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . 4-88
XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs). . . . . . . . . . . . . . 4-90
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs) . . . . . . . . . . . 4-91
XC4000E IOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
XC4000E IOB Input Switching Characteristic Guidelines (continued) . . . . . . . . . . . . . . . . . . . . 4-93
XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
XC4000E IOB Output Switching Characteristic Guidelines (continued). . . . . . . . . . . . . . . . . . . 4-95
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . 4-96
XC4000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
XC4000EX Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
Pin Locations for XC4003E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
Pin Locations for XC4005E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98
Pin Locations for XC4006E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100
Pin Locations for XC4008E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-102
Pin Locations for XC4010E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104
Pin Locations for XC4013E/L Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107
Pin Locations for XC4020E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110
Pin Locations for XC4036EX/XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-118
Pin Locations for XC4044EX/XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-123
Pin Locations for XC4052XL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-128
Package-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133
PC84 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-133
PQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134
VQ100 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-135
PG120 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
TQ144 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-138
PG156 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-140
PQ160 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-142
TQ176 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
PG191 Package Pinouts (see PG223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-145
PG223 and PG191 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-149
BG225 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152
PQ240, HQ240 Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154
PG299 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-157
HQ304 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-160
BG352 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
PG411 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-166
BG432 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-170
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-174
User I/O Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-176
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-178
XC4000 Series Table of Contents
4-4
June 1, 1996 (Version 1.02) 4-5
XC4000-Series Features
Note: XC4000-Series devices described in this data sheet
include the XC4000E, XC4000EX, XC4000L, and
XC4000XL. This information does not apply to the older
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H.
For infor mation on these devices, see the Xilinx WEBLINX
at http://www.xilinx.com.
• Third Generation Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -3 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
• System Performance to 66 MHz
• Flexible Array Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output (4 mA per
XC4000L output)
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
• Backward Compatible with XC4000 Devices
•XACT
step
Development System runs on '386/'486/
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- RAM/ROM compiler
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000L: Low-Voltage Versions of XC4000E devices
• XC4000XL: Low-Voltage Versions of XC4000EX
devices
Additional XC4000EX/XL Features
• Highest Capacity — Over 130,000 Usable Gates
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed
• New Latch Capability in Configurable Logic Blocks
• Improv ed V ersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
• Flexible New High-Speed Clock Network
- 8 additional Early Buffers for shorter clock delays
- 4 additional FastCLKTM buffers for fastest clock input
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• High-Speed Parallel ExpressTM Configuration Mode
• Improved I/O Setup and Clock-to-Output with FastCLK
and Global Early Buffers
• 4 Additional Address Bits in Master Parallel
Configuration Mode
Introduction
XC4000-Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of eleven years of FPGA design experience and
feedbac k from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated soft-
ware to achieve fully automated implementation of com-
plex, high-density, high-performance designs.
The XC4000 Series currently has 19 members, as shown in
Table 1.
XC4000 Series
Field Programmable Gate Arrays
June 1, 1996 (Version 1.02) Product Specification
XC4000 Series Field Programmable Gate Arrays
4-6 June 1, 1996 (Version 1.02)
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note:
Throughout the functional descriptions in this docu-
ment, references to the XC4000E device family include the
XC4000L, and references to the XC4000EX device family
include the XC4000XL, unless explicitly stated otherwise.
References to the XC4000 Series include the XC4000E,
XC4000EX, XC4000L, and XC4000XL families. All func-
tionality in low-voltage families is the same as in the corre-
sponding 5-Volt family, except where numerical references
are made to timing, power, or current-sinking capability.
Description
XC4000-Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external ser ial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA from an external device
(slave, peripheral and Express modes).
XC4000-Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well be yond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000EX, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Table 2 shows density and performance for a few common
circuit functions that can be implemented in XC4000-Series
devices .
Table 1: XC4000-Series Field Programmable Gate Arrays
Device
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)* CLB
Matrix
Total
Logic
Blocks
Number
of
Flip-Flops
Max.
Decode
Inputs
per side Max.
User I/O
XC4003E 3,000 3,200 2,000 - 5,000 10 x 10 100 360 30 80
XC4005E/L 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112
XC4006E 6,000 8,192 4,000 - 12,000 16 x 16 256 768 48 128
XC4008E 8,000 10,368 6,000 - 15,000 18 x 18 324 936 54 144
XC4010E/L 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160
XC4013E/L 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192
XC4020E 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 84 224
XC4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256
XC4028EX/XL 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256
XC4036EX/XL 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 108 288
XC4044EX/XL 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 120 320
XC4052XL 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 132 352
XC4062XL 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 144 384
Larger Devices Available in the First Half of 1997
June 1, 1996 (Version 1.02) 4-7
Note: 1. Most functions are faster in XC4000EX due to faster carry logic, direct connects, and other additional interconnect.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys-
tem designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be recon-
figured dynamically to perform different functions at differ-
ent times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capab le of being reconfig-
ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli-
fies hardware design and debugging and shor tens product
time-to-market.
Table 2: Density and Performance for Several Common Circuit Functions in XC4000E1
Design Class Function CLBs Used XC4000E-3 XC4000E-2 Units
Memory
256 x 8 Single Port (read/modify/write) 72 63 80 MHz
32 x 16 bit FIFO
simultaneous read/write
MUXed read/write 48
32 63
63 80
80 MHz
MHz
Logic
9 bit Shift Register (with enable) 5 170 200 MHz
16 bit Pre-Scaled Counter 8 142 170 MHz
16 bit Loadable Counter 8 65 76 MHz
16 bit Accumulator 9 65 76 MHz
8 bit, 16 tap FIR Filter sample rate
parallel
serial 400
68 55
8.1 65
10 MHz
MHz
8 x 8 Parallel Multiplier
single stage, register to register 73 37 30 ns
16 bit Address Decoder (internal decode) 3 4.7 3.9 ns
9 bit Parity Checker 1 4.3 2.7 ns
XC4000 Series Field Programmable Gate Arrays
4-8 June 1, 1996 (Version 1.02)
XC4000E and XC4000EX Families
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000-Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000EX devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000EX devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
Most XC4000EX devices have no corresponding XC4000
devices , because of the larger CLB arra ys . The XC4028EX
has the same array size as the XC4025 and XC4025E, but
is not bitstream-compatible. However, the XC4025,
XC4025E, and XC4028EX are all pinout-compatible.
Improvements in XC4000E and XC4000EX
Increased System Speed
Delays in FPGA-based designs are layout dependent.
There is a rule of thumb designers can consider—the sys-
tem clock rate should not e xceed one third to one half of the
specified toggle rate. Critical portions of a design, such as
shift registers and simple counters, can run faster—appro x-
imately two thirds of the specified toggle rate.
XC4000E and XC4000EX devices can run at synchronous
system clock rates of up to 66 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in perf ormance
ov er the previous f amilies stems from improv ements in both
device processing and system architecture. XC4000-
Series devices use a sub-micron triple-lay er metal process .
In addition, many architectural improvements have been
made, as described below.
PCI Compliance
XC4000-Series -3 and faster speed grades are fully PCI
compliant. XC4000E and XC4000EX devices can be used
to implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (TBYP), have improved by as
much as 50% from XC4000 v alues. See “F ast Carry Logic”
on page 21 for more information.
Select-RAM Memory: Edge-Triggered, Synchronous
RAM Modes
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option conv erts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time ,
so that the RAM starts up with user-defined data.
H Function Generator
In XC4000-Series devices, the H function generator is
more versatile than in the XC4000. Its inputs can come not
only from the F and G function generators but also from up
to three of the four control input lines. The H function gen-
erator can thus be totally or partially independent of the
other two function generators, increasing the maximum
capacity of the device.
IOB Clock Enable
The two flip-flops in each IOB hav e a common cloc k enab le
input, which through configuration can be activ ated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This ne w feature makes the IOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like totem-
pole. This driver is an n-channel pull-up transistor, pulling
to a voltage one tr ansistor threshold below Vcc, just like the
XC4000 outputs. Alternatively, XC4000-Series devices can
be globally configured with CMOS outputs, with p-channel
pull-up transistors pulling to Vcc. Also , the configurab le pull-
up resistor in the XC4000 Series is a p-channel transistor
that pulls to Vcc, whereas in the XC4000 it is an n-channel
transistor that pulls to a voltage one transistor threshold
below Vcc.
Input Thresholds
The input thresholds can be globally configured for either
TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like
XC2000 and XC3000 inputs. The two global adjustments of
input threshold and output level are independent of each
other.
June 1, 1996 (Version 1.02) 4-9
Global Signal Access to Logic
There is additional access from global clocks to the F and G
function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
M2, have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be
left unconnected.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000-Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recom-
piled for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Additional Improvements in XC4000EX
Only
Increased Routing
New interconnect in the XC4000EX includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve
“Quad Lines” in each CLB ro w and column include optional
repowering buffers for maximum speed. Additional high-
performance routing near the IOBs enhances pin fle xibility.
Faster Input and Output
A fast, dedicated early cloc k sourced by global clock b uffers
is available for the IOBs. To ensure synchronization with
the regular global clocks , a F ast Capture latch driven b y the
early clock is available. The input data can be initially
loaded into the F ast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 24 for more information.
Latch Capability in CLBs
Storage elements in the XC4000EX CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
IOB Output MUX From Output Clock
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enab le as the output
to the pad. Thus, two diff erent data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an AND-
gate to implement a very fast pin-to-pin path. See “IOB
Output Signals” on page 27 for more information.
Express Configuration Mode
A new sla ve configuration mode accepts par allel data input.
Data is processed in parallel, rather than serialized inter-
nally. Therefore, the data rate is eight times that of the six
conventional configuration modes.
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000EX devices may
require a PROM that cannot be addressed by the eighteen
address bits supported in the XC4000E. The XC4000EX
family therefore extends the addressing in Master Parallel
configuration mode to 22 bits.
XC4000 Series Field Programmable Gate Arrays
4-10 June 1, 1996 (Version 1.02)
Table 3: CLB Count of Selected XC4000-Series Soft Macros
7400 Equivalents CLBs Barrel Shifters CLBs Multiplexers CLBs
‘138
‘139
‘147
‘148
‘150
‘151
‘152
‘153
‘154
‘157
‘158
‘160
‘161
‘162
‘163
‘164
‘165s
‘166
‘168
‘174
‘194
‘195
‘280
‘283
‘298
‘352
‘390
‘518
‘521
5
2
5
6
5
3
3
2
16
2
2
5
6
8
8
4
9
5
7
3
5
3
3
8
2
2
3
3
3
brlshft4
brlshft8 4
13 m2-1e
m4-1e
m8-1e
m16-1e
1
1
3
5
4-Bit Counters
cd4cd
cd4cle
cd4rle
cb4ce
cb4cle
cb4re
3
5
6
3
6
5
Registers
rd4r
rd8r
rd16r
2
4
8
8- and 16-Bit Counters Shift Registers
cb8ce
cb8re
cc16ce
cc16cle
cc16cled
6
10
9
9
21
sr8ce
sr16re 4
8
Decoders
d2-4e
d3-8e
d4-16e
2
4
16
Identity Comparators
comp4
comp8
comp16
1
2
5Explanation of counter nomenclature
cb = binary counter
cd = BCD counter
cc = cascadable binary counter
d = bidirectional
l = loadable
e = clock enable
r = synchronous reset
c = asynchronous clear
Magnitude Comparators
compm4
compm8
compm16
4
9
20
Explanation of RAM nomenclature
s = single-port edge-triggered
d = dual-port edge-triggered
no extension = level-sensitive
RAMs
ram16x4
ram16x4s
ram16x4d
2
2
4
June 1, 1996 (Version 1.02) 4-11
Detailed Functional Description
XC4000-Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000EX support system
clock rates of up to 66 MHz and internal performance in
excess of 150 MHz. Compared to older Xilinx FPGA fami-
lies, XC4000-Series devices are more powerful. The y offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
the user’s logic.
• IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
• Wide edge decoders are av ailable around the periphery
of each device.
• An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memor y cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Each of these av ailab le circuits is described in this section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. The number of CLBs needed to implement
selected soft macros is shown in Table 3.
Two 4-input function generators (F and G) off er unrestricted
versatility. Most combinator ial logic functions need four or
fe wer inputs . How ev er , a third function gener ator (H) is pro-
vided. The H function generator has three inputs. Either
zero, one, or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The
CLB can, therefore, implement certain functions of up to
nine variables, like parity check or expandable-identity
comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000EX devices; in
the XC4000EX they can optionally be configured as
latches. DIN can be used as a direct input to either of the
two storage elements . H1 can drive the other through the H
function generator. Function generator outputs can also
drive two outputs independent of the storage element out-
puts. This v ersatility increases logic capacity and simplifies
routing.
Thir teen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs
can optionally be the F’ and G’ functional generator out-
puts. Alternatively, one or both of these inputs can come
from outside the CLB (H2, H0). The third input must come
from outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’
or H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
• any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
• any single function of five variables
• any function of four variables together with some
functions of six variables
• some functions of up to nine variables.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
XC4000 Series Field Programmable Gate Arrays
4-12 June 1, 1996 (Version 1.02)
Implementing wide functions in a single bloc k reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and cloc k enab le (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 4.
Latches (XC4000EX only)
The CLB storage elements can also be configured as
latches. The two latches ha ve common cloc k (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 4.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. Howe ver, the clock is individually inv ertible f or each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
H'
F'
S/R
CONTROL
D
EC RD
Bypass
Bypass
SD YQ
XQ
Q
S/R
CONTROL
D
EC RD
SD Q
1
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1SR/H0EC
X6692
C1 • • • C4 4
Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown)
Table 4: CLB Storage Element Functionality
(active rising edge is shown)
Mode K EC SR D Q
Power-Up or
GSR XXXXSR
Flip-Flop XX1XSR
__/ 1* 0* D D
0X0*XQ
Latch 11*0*XQ
01*0*DD
Both X 0 0* X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
June 1, 1996 (Version 1.02) 4-13
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the eff ect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three set/
reset functions for any single flip-flop are controlled by the
same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 1)
sets or clears each storage element during power-up,
reconfiguration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GSR pin of the STARTUP symbol. (See Figure 2.) A
specific pin location can be assigned to this input using a
LOC attribute or property, just as with any other user-pro-
grammable pad. An inverter can optionally be inserted
after the input buffer to invert the sense of the Global Set/
Reset signal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is dr iven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) bloc k input. The flip-flops or latches driv e
the XQ and YQ CLB outputs.
Two fast feed-through paths are available, as shown in
Figure 1. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used
by the automated router to repower internal signals.
Control Signals
Multiplex ers in the CLB map the f our control inputs (C1 - C4
in Figure 1) into the four internal control signals (H1, DIN/
H2, SR/H0, and EC). Any of these inputs can drive any of
the four internal control signals.
When the logic function is enabled, the four inputs are:
• EC — Enable Clock
• SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
• DIN/H2 — Direct In or H function generator Input 2
• H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
• EC — Enable Clock
• WE — Write Enable
• D0 — Data Input to F and/or G function generator
• D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a pow erful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000EX only) is called LDCE.
In XC4000-Series devices, the flip flops can be used as
registers or shift registers without bloc king the function gen-
erators from perf orming a different, perhaps unrelated task.
This ability increases the functional capacity of the devices .
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Theref ore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
PAD
IBUF
GSR
GTS
CLK DONEIN
Q1Q4
Q2
Q3
STARTUP
X5260
Figure 2: Schematic Symbols for Global Set/Reset
XC4000 Series Field Programmable Gate Arrays
4-14 June 1, 1996 (Version 1.02)
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families), edge-
triggered, and dual-port edge-triggered. Depending on the
selected mode, a single CLB can be configured as either a
16x2, 32x1, or 16x1 bit array.
Suppor ted CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 5.
XC4000-Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000-Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time
is the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Arra y. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “
XC4000E Edge-Triggered and
Dual-Port RAM Capability,
” “
Implementing FIFOs in
XC4000E RAM,
” and “
Synchronous and Asynchronous
FIFO Designs
.” All three application notes apply to both
XC4000E and XC4000EX RAM.
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
• Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
• One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000-Series RAM may have either of
two timing modes:
• Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
• Lev el-Sensitiv e (Asynchronous): an external WE signal
acts as the write strobe.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
The number of read ports is also programmable:
• Single Port: each function generator has a common
read and write port
• Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 6.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Table 5: Supported RAM Modes
16
x
1
16
x
2
32
x
1
Edge-
Triggered
Timing
Level-
Sensitive
Timing
Single-Port √√√ √ √
Dual-Port √√
Table 6: RAM Mode Selection
Level-
Sensitive Edge-
Triggered
Dual-Port
Edge-
Triggered
Use for New
Designs? No Yes Yes
Size (16x1,
Registered) 1/2 CLB 1/2 CLB 1 CLB
Simultaneous
Read/Write No No Yes
Relative
Performance X2X
2X (4X
effective)
June 1, 1996 (Version 1.02) 4-15
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6752
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1D0EC
WRITE PULSE
MUX
4
4
Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6754
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1/A4D0
EC
EC
WRITE PULSE
MUX
4
4
H'
Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
XC4000 Series Field Programmable Gate Arrays
4-16 June 1, 1996 (Version 1.02)
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The DIN/
H2, H1, and SR/H0 lines become the two data inputs (D0,
D1) and the Write Enable (WE) input for the 16x2 memory.
When the 32x1 configuration is selected, D1 acts as the
fifth address bit and D0 is the data input.
The contents of the memory cell(s) being addressed are
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
tured in the CLB flip-flop(s).
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
tions of the CLB, with the e xception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000-Series edge-tr iggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enab led for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 5.
Complex timing relationships between address, data, and
write enable signals are not required, and the e xternal write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
nals. An inter nal wr ite pulse is generated that performs the
write. See Figure 3 and Figure 4 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, single-
port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 7.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It
uses the same CLB pin (K) used to clock the CLB flip-flops ,
but it can be independently inverted. Consequently, the
RAM output can optionally be registered within the same
CLB either by the same clock edge as the RAM, or by the
opposite edge of this clock. The sense of WCLK applies to
both function generators in the CLB when both are config-
ured as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessiv e current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Table 7: Single-Port Edge-Triggered RAM Signals
RAM Signal CLB Pin Function
D D0 or D1
(16x2, 16x1)
D0 (32x1)
Data In
A[3:0] F1-F4 or
G1-G4 Address
A[4] D1 (32x1) Address
WE WE Write Enable
WCLK K Clock
SPO
(Data Out) F’ or G’ Single Port Out
(Data Out)
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
TASS TAHS
TWSS
TWPS
TWHS
TWOS
TILO
TILO
Figure 5: Edge-Triggered RAM Write Timing
June 1, 1996 (Version 1.02) 4-17
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
por t and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 5.
Figure 6 shows a simple model of an XC4000-Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM arra y. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address f or the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Por t Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 8. See Figure 7 for a block diagram of a CLB config-
ured in this mode.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessiv e current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Table 8: Dual-Port Edge-Triggered RAM Signals
WE WE
DDQ
DQ
D
DPRA[3:0]
A[3:0]
AR[3:0]
AW[3:0]
WE
D
AR[3:0]
AW[3:0]
RAM16X1D Primitive
F Function Generator
G Function Generator
DPO (Dual Port Out)
Registered DPO
SPO (Single Port Out)
Registered SPO
WCLK
X6755
Figure 6: XC4000-Series Dual-Port RAM, Simple
Model
RAM Signal CLB Pin Function
D D0 Data In
A[3:0] F1-F4 Read Address for F,
Write Address for F and G
DPRA[3:0] G1-G4 Read Address for G
WE WE Write Enable
WCLK K Clock
SPO F’ Single Port Out
(addressed by A[3:0])
DPO G’ Dual Port Out
(addressed by
DPRA[3:0])
XC4000 Series Field Programmable Gate Arrays
4-18 June 1, 1996 (Version 1.02)
G'
G1 • • • G4
F1 • • • F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6748
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK) WRITE PULSE
MUX
4
4
C1 • • • C4 4
WE D1D0EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
June 1, 1996 (Version 1.02) 4-19
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000-Series backward-com-
patibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During the WE High pulse , changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines m ust be care-
fully verified to ensure that WE does not become active until
after the address lines hav e settled, and that WE goes inac-
tive before the address lines change again. The data must
be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X cloc k. If
a 2X clock is not available, the falling edge of the system
clock can be used. Howe v er , there are inherent risks in this
approach, since the WE pulse must be guar anteed inactiv e
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of lev el-sensitive RAMs. These application
notes include XAPP031, “
Using the XC4000 RAM Capabil-
ity
,” and XAPP042, “
High-Speed RAM Design in XC4000
.”
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
Figure 8 shows the write timing for level-sensitive, single-
port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 9.
Figure 9 and Figure 10 show b loc k diagr ams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000-
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide.
If not defined, all RAM contents are initialized to all zeros,
by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 9: Single-Port Level-Sensitive RAM Signals
RAM Signal CLB Pin Function
D D0 or D1 Data In
A[3:0] F1-F4 or
G1-G4 Address
WE WE Write Enable
O F’ or G’ Data Out
WC
T
ADDRESS
WRITE ENABLE
DATA IN
AS
TWP
T
DS
TDH
T
REQUIRED
AH
T
X6462
Figure 8: Level-Sensitive RAM Write Timing
XC4000 Series Field Programmable Gate Arrays
4-20 June 1, 1996 (Version 1.02)
Enable
G'
4
G1 • • • G4
F1 • • • F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6746
4
READ ADDRESS
MUX
Enable
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS
MUX
4
C1 • • • C4 4
WE D1D0EC
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6749
4
READ ADDRESS
MUX
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS
MUX
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4 4
F'
WE D1/A4D0EC
4
H'
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
June 1, 1996 (Version 1.02) 4-21
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This e xtra output is passed on to the function gen-
erator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous gener ations of FPGAs were not f ast enough or too
inefficient. High-speed address offset calculations in
microprocessor or graphics systems , and high-speed addi-
tion in digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitr y is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. (See Figure 11.) In order to improv e speed in the
high-capacity XC4000EX devices, which can potentially
have v ery long carry chains, the carry chain travels upward
only, as shown in Figure 12. This restriction should ha ve lit-
tle impact, because the smallest XC4000EX device, the
XC4028EX, can accommodate a 64-bit carry chain in a sin-
gle column. Additionally, standard interconnect can be
used to route a carry signal in the downward direction.
Figure 13 on page 22 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000EX is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 14 and Figure 15 on page 23 show the details of the
carry logic for the XC4000E and the XC4000EX respec-
tively. These diagrams show the contents of the box
labeled “CARRY LOGIC” in Figure 13. As shown, the
XC4000EX carry logic eliminated a multiplexer to reduce
delay on the pass-through carry chain. Additionally, the
multiple x er on the G4 path now has a memory-programma-
ble input, which permits G4 to directly connect to COUT.
G4 thus becomes an additional high-speed initialization
path for carry-in.
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “
Using the Dedicated Carry Logic in
XC4000
.” This discussion also applies to XC4000E
devices, and to XC4000EX devices when the minor logic
changes are taken into account.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
X6687
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 11: Available XC4000E Carry Propagation
Paths
X6610
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 12: Available XC4000EX Carry Propagation
Paths (dotted lines use general interconnect)
XC4000 Series Field Programmable Gate Arrays
4-22 June 1, 1996 (Version 1.02)
DQ
S/R
EC
YQ
Y
DIN
H
G
F
G
H
DQ
S/R
EC
XQ
DIN
H
G
F
H
X
H
F
G
G4
G3
G2
G1
F
F3
F2
F1
F4
F
CARRY
G
CARRY
CCDOWN
CARRY
LOGIC
D
CC UP K S/R EC
H1
X6699
OUT
IN
OUT IN
IN
COUT0
Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX)
June 1, 1996 (Version 1.02) 4-23
Figure 14: Detail of XC4000E Dedicated Carry Logic
01
01
M
M
0
1
01
M
0
1
M
10
M
M0
3
M
1
M
I
G1
G4
F2
F1
F3
COUT
G2
G3
F4
CINUP
CIN DOWN
X2000
TO
FUNCTION
GENERATORS
M
M
M
COUT0
Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences fr om XC4000E carry logic)
M
M
M
M
M
01
01
0
1
1
0
1
0
3
1
0
M
M
M
M
M
F4
G3
G2
G1
G4
F2
F1
F3
M
TO
FUNCTION
GENERATORS
COUT
COUT0
CIN UP X6701
XC4000 Series Field Programmable Gate Arrays
4-24 June 1, 1996 (Version 1.02)
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 16 shows a simplified block diagram of the
XC4000E IOB. A more complete diagram of the XC4000E
IOB can be found in Figure 42 on page 51, in the “Boundary
Scan” section. Figure 42 includes the boundary scan logic
in the IOB.
Figure 17 shows a simplified block diagram of the
XC4000EX IOB. The XC4000EX IOB contains some spe-
cial features not included in the XC4000E IOB. These fea-
tures are highlighted in Figure 17, and discussed
throughout this section. When XC4000EX special features
are discussed, they are clearly identified in the text. Any
feature not so identified is present in both XC4000E and
XC4000EX devices.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 16 and Figure 17,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an edge-
triggered flip-flop or a level-sensitive latch.
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising
edge triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inv erted cloc ks are av ailable , and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the
XACT Libr aries
Guide
.
The inputs can be globally configured for either TTL (1.2V,
default) or CMOS thresholds, using an option in the Make-
Bits program. There is a slight hysteresis of about 300mV.
The output levels are also configurable; the two global
adjustments of input threshold and output level are inde-
pendent.
Inputs of the low-voltage devices
must
be configured as
CMOS at all times. The y can be driven b y the outputs of all
5-Volt XC4000-Series devices, pro vided that the 5-Volt out-
puts are in TTL mode. They can also be driven by any TTL
output that does not exceed 3.7 V. 5-Volt XC3000-family
device outputs, for example, are TTL-compatible, but since
the output voltage can e xceed 3.7 V, they cannot be used to
drive an XC4000L or XC4000XL input.
The inputs of XC4000-Series 5-Volt devices can be driven
by the outputs of an y 3.3-Volt device , if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000-Series device inputs are
shown in Table 10.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000-Series CLB. It cannot be inverted within
the IOB.
The storage element behavior is shown in Table 11.
Table 11: Input Register Functionality
(active rising edge is shown)
1. Acceptable for XC4000XL if the designated 5-Volt
supply pad (VTT) is tied to 5V.
T ab le 10: Supported Sources f or XC4000-Series Device
Inputs
Source
XC4000-Series Inputs
3.3 V,
CMOS 5 V,
TTL 5 V,
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs √√
Unreli-
able
Data
XC4000-Series, Vcc = 5 V,
TTL outputs √√
Any device, Vcc = 5 V,
TTL outputs (Voh ≤ 3.7 V) √√
Any device, Vcc = 5 V,
CMOS outputs Danger1√√
Mode Clock Clock
Enable DQ
Power-Up or
GSR XXXSR
Flip-Flop __/ 1* D D
0XXQ
Latch 1 1* X Q
01*DD
Both X 0 X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
June 1, 1996 (Version 1.02) 4-25
Q
Flip-
Flop/
Latch
D
D
CE
CE
Q
Out
T
Output
Clock
I
Input
Clock
Clock
Enable
Delay
Pad
Flip-Flop
Slew Rate
Control
Output
Buffer
Input
Buffer
Passive
Pull-Up/
Pull-Down
2
I1
X6704
Figure 16: Simplified Block Diagram of XC4000E IOB
Q
Flip-Flop/
Latch
Fast
Capture
Latch
D
Q
Latch
D
G
D
0
1
CE
CE
Q
Out
T
Output Clock
I
Input Clock
Clock Enable
Pad
Flip-Flop
Slew Rate
Control
Output
Buffer
Output MUX
Input
Buffer
Passive
Pull-Up/
Pull-Down
2
I1
X5984
Delay Delay
Figure 17: Simplified Block Diagram of XC4000EX IOB (shaded areas indicate differences from XC4000E)
XC4000 Series Field Programmable Gate Arrays
4-26 June 1, 1996 (Version 1.02)
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the
device clock pin to the clock input of the IOB must, there-
fore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
specified setup time might, therefore, result in a negative
setup time at the device pins, i.e., a positive hold-time
requirement.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.
The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guar antees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See “Global Nets
and Buffers (XC4000E only)” on page 41 for a description
of the global clock buffers in the XC4000E.) For a shor ter
input register setup time, with non-zero hold, attach a
NODELAY attribute or property to the flip-flop.
The XC4000EX IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired dela y are
shown in Table 12. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to an y of
the XC4000EX clock buffers, including the Global Low-
Skew buffers. MEDDELAY ensures no hold time with
respect to the Global Early and FastCLK buffers. Inputs
with NODELAY may have a positive hold time with respect
to all clock buffers, including the FastCLK buffers. For a
description of each of these buffers, see “Global Nets and
Buffers (XC4000EX only)” on page 43.
Table 12: XC4000EX IOB Input Delay Element
Additional Input Latch for Fast Capture (XC4000EX
only)
The XC4000EX IOB has an additional optional latch on the
input. This latch, as shown in Figure 17, is clocked by the
output clock — the clock used for the output flip-flop —
rather than the input clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To use this Fast Capture technique, drive the output clock
pin (the F ast Capture latching signal) from the output of one
of the Global Early or FastCLK buffers supplied in the
XC4000EX. The second storage element should be
clocked by a Global Low-Skew buffer, to synchronize the
incoming data to the internal logic. (See Figure 18.) These
special buffers are described in “Global Nets and Buffers
(XC4000EX only)” on page 43.
The Fast Capture latch is designed primarily for use with a
Global Early buffer. For Fast Capture, a single clock signal
is routed through both a Global Early buffer and a Global
Low-Skew buffer. (The two buffers share an input pad.)
The Fast Capture latch is clocked by the Global Early
buffer, and the standard IOB flip-flop or latch is clocked by
the Global Low-Sk ew b uff er . This mode is the saf est w a y to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There
is no external skew between clock pads to create potential
problems.
Alternatively, a FastCLK b uffer can be used to minimize the
setup time of device inputs , if a positiv e hold time is accept-
able. Use the FastCLK buffer to clock the Fast Capture
latch, and a slower clock buffer to clock the standard IOB
flip-flop or latch. Either the Global Early buff er or the Global
Low-Skew buffer can be used for the second storage ele-
Value When to Use
full delay
(default, no
attribute added)
Zero Hold with respect to Global Low-
Skew Buffer, Global Early Buffer, or
FastCLK Buffer
MEDDELAY Zero Hold with respect to Global Early
Buffer or FastCLK Buffer
NODELAY Short Setup, positive Hold time
IPAD
IPAD
IPAD
IPAD
IPAD
BUFGE
BUFFCLK
BUFGLS
BUFGLS NODELAY
G
G
CE
CE
DQ
GF
DQ
GF
to internal
logic
to internal
logic
ILDFFDX
ILDFFDX
X6705
Figure 18: Examples Using XC4000EX Fast
Capture Latch
June 1, 1996 (Version 1.02) 4-27
ment, but whichever one is used should be the same clock
as the related internal logic. Since the FastCLK pads are
different from the Global Early and Global Low-Ske w pads,
care must be taken to ensure that skew external to the
device does not create internal timing difficulties.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILDFFDX or ILDFLDX. ILDFFDX
is a transparent-Low Fast Capture latch followed by an
active-High input flip-flop. ILDFLDX is a transparent-Low
Fast Capture latch followed by a transparent-High input
latch. An y of the clock inputs can be in v erted bef ore driving
the library element, and the inverter is absorbed into the
IOB. If a single BUFG output is used to drive both clock
inputs, the software automatically runs the clock through
both a Global Low-Skew buffer and a Global Early buffer,
and clocks the Fast Capture latch appropriately.
Figure 17 on page 25 also shows a two-tap delay on the
input. By def ault, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buff er is driving the clock,
and selects MEDDELAY to ensure a zero hold time. This
default can be overridden to remove the delay, if FastClk is
used, by attaching a NODELAY attribute or property to the
ILDFFD or ILDFLD latch. Select the desired delay based
on the discussion in the previous subsection.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and can pass directly to the pad or be stored in an edge-
triggered flip-flop. The functionality of this flip-flop is sho wn
in Table 13.
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently
configured for each IOB.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected exter-
nally to sink up to 24 mA. (XC4000L and XC4000XL out-
puts can sink up to 4 mA, and two adjacent XC4000L and
XC4000XL outputs can sink up to 8 mA.) The XC4000E
and XC4000EX FPGAs can thus directly drive buses on a
printed circuit board.
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-
up transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally con-
figured as CMOS drivers, with p-channel pull-up tr ansistors
pulling to Vcc. This MakeBits option applies to all outputs
on the device. It is not individually programmable.
Outputs of low-voltage devices
must
be configured as
CMOS at all times. They can drive the inputs of any 5-Volt
device with TTL-compatible thresholds.
Any XC4000-Series 5-Volt device with its outputs config-
ured in TTL mode can drive the inputs of any typical 3.3-
Volt device.
Supported destinations for XC4000-Series device outputs
are shown in Table 14.
Table 14: Supported Destinations for XC4000-Series
Outputs
1. Only if destination device has 5-V tolerant inputs
Table 13: Output Flip-Flop Functionality (active rising
edge is shown)
Mode Clock Clock
Enable T D Q
Power-Up
or GSR X X 0* X SR
Flip-Flop
X00*XQ
__/ 1* 0* D D
XX1XZ
0X0*XQ
Legend:
X
__/
SR
0*
1*
Z
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
Destination
XC4000-Series
Outputs
3.3 V,
CMOS 5 V,
TTL 5 V,
CMOS
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs √√some1
Any device, Vcc = 5 V,
TTL-threshold inputs √√√
Any device, Vcc = 5 V,
CMOS-threshold inputs Unreliable
Data √
XC4000 Series Field Programmable Gate Arrays
4-28 June 1, 1996 (Version 1.02)
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 19.)
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attr ibute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair . For XC4000EX devices , additional internal P o wer/
Ground pin pairs are connected to special Power and
Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For sle w-rate limited outputs this total is tw o times larger for
each device type: 400 pF for XC4000E de vices and 600 pF
for XC4000EX devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns dura-
tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic.
This restriction is common to all high-speed digital ICs, and
is not particular to Xilinx or the XC4000 Series.
XC4000-Series devices have a feature called “Soft Start-
up,” designed to reduce ground bounce when all outputs
are turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
star ts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activ ation
of the I/O, the slew rate of the individual outputs is deter-
mined by the individual configuration option for each IOB.
Global Three-State
A separate Global 3-State line (not shown in Figure 16 or
Figure 17) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is e x ecuting an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad.
An inverter can optionally be inserted after the input buffer
to inv ert the sense of the Global 3-State signal. Using GTS
is similar to GSR. See Figure 2 on page 13 for details.
Alternatively, GTS can be driven from any internal node.
Output Multiplexer/2-Input Function Generator
(XC4000EX only)
As shown in Figure 17 on page 25, the output path in the
XC4000EX IOB contains an additional multiple xer not a vail-
able in the XC4000E IOB . The multiple x er can also be con-
figured as a 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate , or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these func-
tions is shown in the upper gray area of Figure 17.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effec-
tively doub ling the n umber of de vice outputs without requir-
ing a larger, more expensive package.
When the MUX is configured as a 2-input function genera-
tor, logic can be implemented within the IOB itself. Com-
bined with either a FastCLK or Global Early buffer, this
arrangement allows very high-speed gating of a single sig-
nal. For example, a wide decoder can be implemented in
CLBs, and its output gated with a Read or Write Strobe
driven by a FastCLK buffer, as shown in Figure 20. The
critical-path pin-to-pin delay of this circuit is less than 6
nanoseconds. (This value may not be achievable in
XC4000XL devices.)
As shown in Figure 17, the IOB input pins Out, Output
Clock, and Cloc k Enab le ha v e different delays and diff erent
flexibilities regarding polarity. Additionally, Output Clock
sources are more limited than the other inputs. Therefore,
the Xilinx software does not move logic into the IOB func-
tion generators unless explicitly directed to do so.
X6702
OPAD
OBUFT
Figure 19: Open-Drain Output
IPAD
FOPAD
FAST
BUFFCLK
OAND2
from
internal
logic
X6698
Figure 20: Fast Pin-to-Pin Path in XC4000E
June 1, 1996 (Version 1.02) 4-29
The user can specify that the IOB function generator be
used, by placing special library symbols beginning with the
letter “O .” For e xample, a 2-input AND-gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
labelled “F” for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function gener ator. Two examples are sho wn in
Figure 21.
Other IOB Options
There are a number of other programmable options in the
XC4000-Series IOB.
Pull-up and Pull-down Resistors
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-do wn resistor is an n-channel transis-
tor that pulls to Ground.
The value of these resistors is 50 kΩ − 100 kΩ. This high
value makes them unsuitable as wired-AND pull-up resis-
tors.
The pull-up resistors for most user-prog rammab le IOBs are
active during the configuration process. See Table 24 on
page 78 for a list of pins with pull-ups activ e bef ore and dur-
ing configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active . Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an exter nal source. To activate the internal pull-
up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Independent Clocks
Separate clock signals are pro vided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the IOB, generating either falling-edge or ris-
ing-edge triggered flip-flops. The clock inputs for each IOB
are independent, except that in the XC4000EX, the Fast
Capture latch shares an IOB input with the output clock pin.
Early Clock for IOBs (XC4000EX only)
Special early clocks are available for IOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buff ers , b ut are separ ately buffered. They hav e fewer loads
and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
early clock allows fast capture of input data, and fast cloc k-
to-output on output data. The Global Early buffers that
drive these clocks are described in “Global Nets and Buff-
ers (XC4000EX only)” on page 43.
Fast Clock for IOBs (XC4000EX only)
Very fast clocks driven by FastCLK buffers are also avail-
able f or IOBs. These cloc ks are sourced by semi-dedicated
pads—the pads can be used as general I/O if not used to
drive FastCLK buffers. There are two FastCLK buffers on
the left edge, and two on the right edge of the de vice . The y
provide the fastest method of reaching the IOB clock pins.
The F astCLK b uff er can drive either the IOB output cloc k or
the IOB input clock, or both. These b uff ers allow the f astest
possible setup times and clock-to-output times. The Fast-
CLK buffers are described in “Global Nets and Buffers
(XC4000EX only)” on page 43.
Global Set/Reset
As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
or clear on reset and after configuration. Other than the
global GSR net, no user-controlled set/reset signal is avail-
able to the I/O flip-flops. The choice of set or clear applies
to both the initial state of the flip-flop and the response to
the Global Set/Reset pulse. See “Global Set/Reset” on
page 13 for a description of how to use GSR.
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in “Boundary Scan” on
page 50.
Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 34.) These 3-state buffers
can be used to drive signals onto the nearest horizontal
longlines abov e and belo w the CLB . The y can therefore be
used to implement multiple xed or bidirectional b uses on the
horizontal longlines, saving logic resources. Programma-
ble pull-up resistors attached to these longlines help to
implement a wide wired-AND function.
OAND2
F
X6598
D0
S0
D1 O
OMUX2
X6599
Figure 21: Output AND and MUX Symbols in
XC4000EX IOB
XC4000 Series Field Programmable Gate Arrays
4-30 June 1, 1996 (Version 1.02)
The buffer enable is an active-High 3-state (i.e. an active-
Low enable), as shown in Table 15.
Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array.
(See Figure 33 on page 39.)
The horizontal longlines driven by the 3-state b uffers ha ve a
weak keeper at each end. This circuit prevents undefined
floating lev els . Howe v er , it is o v erridden by any driv er , e v en
a pull-up resistor.
Special longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby IOBs
or from internal longlines. These longlines form the wide
edge decoders discussed in “Wide Edge Decoders” on
page 31.
Three-State Buffer Modes
The 3-state buffers can be configured in three modes:
• Standard 3-state buffer
• Wired-AND with input on the I pin
• Wired OR-AND
Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the O pin.
The T pin is an active-High 3-state (i.e. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.
Wired-AND with Input on the I Pin
The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.
WAND4, WAND8, and WAND16 are also available. See
the
XACT Libraries Guide
for further information.
The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the O pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
Wired OR-AND
The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an open-
drain 2-input OR gate. The two input pins are functionally
equivalent. Attach the two inputs to the I0 and I1 pins and
tie the output to the O pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.
Three-State Buffer Examples
Figure 22 shows how to use the 3-state buffers to imple-
ment a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
Figure 23 shows how to use the 3-state buffers to imple-
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 15.
Table 15: Three-State Buffer Functionality
IN T OUT
X1Z
IN0IN
P
U
L
L
U
P
Z = DA ● DB ● (DC+DD) ● (DE+DF)
DE
DF
DC
DD
DB
DAWAND1 WAND1 W0R2AND W0R2AND
X6465
Figure 22: Open-Drain Buffers Implement a Wired-AND Function
DN
DC
DB
DA
ABCN
Z = DA • A + DB • B + DC • C + DN • N
~100 kΩ
"Weak Keeper"
X6466
BUFT BUFT BUFT BUFT
Figure 23: 3-State Buffers Implement a Multiplexer
June 1, 1996 (Version 1.02) 4-31
Wide Edge Decoders
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is
wider than the function generator inputs, FPGAs need
multi-level decoding and are thus slower than PALs.
XC4000-Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for m uch wider decoders, especially f or
address decoding in large microprocessor systems.
An XC4000-Series FPGA has four programmable decod-
ers located on each edge of the device . The inputs to each
decoder are any of the IOB I1 signals on that edge plus one
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three v ariab les or their compli-
ments., as shown in Figure 24. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028EX and 132 on the XC4052EX. The decoders ma y
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on
the same chip edge as the decoder. Very large PALs can
be emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resor ted to exter-
nal PALs for simple but fast decoding functions. Now, the
dedicated decoders in the XC4000-Series device can
implement these functions fast and efficiently.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
W AND symbol. Tie the outputs together and attach a PUL-
LUP symbol. Location attributes or properties such as L
(left edge) or TR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
On-Chip Oscillator
XC4000-Series devices include an internal oscillator. This
oscillator is used to clock the po w er-on time-out, for config-
uration memory clearing, and as the source of CCLK in
Master configuration modes. The oscillator runs at a nom-
inal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz. (The oscillator operates more slowly at lower volt-
ages. The output frequency may be reduced by as much
as 10% for low-voltage devices.)
The oscillator output is optionally available after configura-
tion. Any two of four resynchronized taps of a built-in
divider are also available. These taps are at the fourth,
ninth, fourteenth and nineteenth bits of the divider. There-
fore, if the primar y oscillator output is running at the nomi-
nal 8 MHz, the user has access to an 8 MHz clock, plus an y
two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower
for lo w-voltage de vices). These frequencies can vary b y as
much as -50% or +25%.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code (see
Figure 25).
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.
IOB
IOB
BA
INTERCONNECT
( C) .....
(A • B • C) .....
(A • B • C) .....
(A • B • C) .....
.I1.I1
X2627
C
Figure 24: XC4000-Series Edge Decoding Example
F16K
F500K
F8M
F490
F15
X6703
OSC4
Figure 25: XC4000-Series Oscillator Symbol
XC4000 Series Field Programmable Gate Arrays
4-32 June 1, 1996 (Version 1.02)
Programmable Interconnect
All internal connections are composed of metal segments
with programmab le switching points and s witching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.
The XC4000E and XC4000EX share a basic interconnect
structure. XC4000EX devices, however, have additional
routing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices.
All XC4000EX-specific routing resources are clearly identi-
fied throughout this section. Any resources not identified
as XC4000EX-specific are present in all XC4000-Series
devices.
This section describes the varied routing resources avail-
able in XC4000-Series devices. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the
design.
Interconnect Overview
There are several types of interconnect.
• CLB routing is associated with each row and column of
the CLB array.
• IOB routing forms a ring (called a VersaRing) around
the outside of the CLB array. It connects the I/O with
the internal logic blocks.
• Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the de vice with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Five interconnect types are distinguished by the relative
length of their segments: single-length lines , doub le-length
lines, quad and octal lines (XC4000EX only), and longlines.
In the XC4000EX, direct connects allow fast data flow
between adjacent CLBs, and between IOBs and CLBs.
Extra routing is included in the IOB pad ring. The
XC4000EX also includes a ring of octal interconnect lines
near the IOBs to improve pin-swapping and routing to
locked pins.
XC4000E devices include tw o types of global b uffers, while
XC4000EX devices have three different types. These glo-
bal buffers have different proper ties, and are intended for
different purposes. They are discussed in detail later in this
section.
CLB Routing Connections
A high-level diagram of the routing resources associated
with one CLB is shown in Figure 26. The shaded arrows
represent routing present only in XC4000EX devices.
Table 16 shows how much routing of each type is available
in XC4000E and XC4000EX CLB arrays. Clearly, very
large designs, or designs with a great deal of interconnect,
will route more easily in the XC4000EX. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
Figure 27 on page 34 is a detailed diagram of both the
XC4000E and the XC4000EX CLB, with associated rout-
ing. The shaded square is the programmable switch
matrix, present in both the XC4000E and the XC4000EX.
The L-shaped shaded area is present only in XC4000EX
devices. As shown in the figure, the XC4000EX block is
essentially an XC4000E block with additional routing.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement and routing algorithms. Inputs, out-
puts, and function generators can freely swap positions
within a CLB to avoid routing congestion during the place-
ment and routing operation.
Table 16: Routing per CLB in XC4000-Series Devices
XC4000E XC4000EX
Vertical Horizontal Vertical Horizontal
Singles 8 8 8 8
Doubles 4 4 4 4
Quads 0 0 12 12
Longlines 6 6 10 6
Direct
Connects 0022
Globals 4 0 8 0
Carry Logic 2 0 1 0
Total 24 18 45 32
June 1, 1996 (Version 1.02) 4-33
x5994
Quad
Quad
Single
Double
Long
Direct
Connect
Long
CLB
Long Global
Clock Long Double Single Global
Clock Carry
Chain Direct
Connect
Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only)
XC4000 Series Field Programmable Gate Arrays
4-34 June 1, 1996 (Version 1.02)
F1
C1
G1
F2 C2 G2
F3
C3
G3
F4 C4 G4
K
X
Y
XQ
YQ
LONG
SINGLE
DOUBLE
LONG
GLOBAL
QUAD
LONG
SINGLE
DOUBLE
LONG
LONG
DOUBLE
DOUBLE
QUAD
GLOBAL
Common to XC4000E and XC4000EX
XC4000EX only
Programmable Switch Matrix
CLB
DIRECT
FEEDBACK
DIRECT
FEEDBACK
Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB
June 1, 1996 (Version 1.02) 4-35
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections betw een the lines
(see Figure 28).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the s witch-
ing matrices that are located in every row and a column of
CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 29. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Theref ore, the y are not suitable f or rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: the y run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices stag-
gered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 29).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility. Doub le-length lines are connected by w ay
of the programmab le switch matrices. Routing connectivity
is shown in Figure 27.
Six Pass Transistors
Per Switch Matrix
Interconnect Point
Singles
Double
Double
Singles
Double
Double
X6600
Figure 28: Programmable Switch Matrix (PSM)
CLB
PSM PSM
PSMPSM
CLB CLB
CLB CLB CLB
CLB CLB CLB
Doubles
Singles
Doubles
X6601
Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs)
XC4000 Series Field Programmable Gate Arrays
4-36 June 1, 1996 (Version 1.02)
Quad Lines (XC4000EX only)
XC4000EX devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as dia-
monds in Figure 27 on page 34). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices stag-
gered, so that each line goes through a buffered switch
matrix at every fourth CLB location in that row or column.
(See Figure 30.)
The buffered switch matrixes have four pins, one on each
edge. All of the pins are bidirectional. Any pin can drive
any or all of the other pins.
Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 28, with the addition of a program-
mable buffer. There can be up to two independent inputs
and up to two independent outputs. Only one of the inde-
pendent inputs can be buffered.
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded sig-
nal is typically buffered, while a lightly loaded one is not.
One scenario is to alternate buffers and pass transistors.
This allows both vertical and horizontal quad lines to be
buffered at alternating buffered switch matrices.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals f or long distances across the de vice.
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
X6602
Figure 30: Quad Lines (XC4000EX only)
June 1, 1996 (Version 1.02) 4-37
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000EX
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high fan-
out nets.
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore imple-
ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See “Three-State Buffers” on
page 29 for more details.)
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000EX) pull-up resistors. To acti-
vate these resistors, attach a PULLUP symbol to the long-
line net. The softw are automatically activates the appropri-
ate number of pull-ups. There is also a weak keeper at
each end of these two horizontal longlines. This circuit pre-
vents undefined floating le v els. Howe v er , it is ov erridden by
any driver, even a pull-up resistor.
Each XC4000E longline has a programmab le splitter switch
at its center, as does each XC4000EX longline driven by
TBUFs. This s witch can separ ate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000EX longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000EX lon-
gline performance does not deteriorate with the larger arra y
sizes. If the longline is split, the resulting par tial longlines
are independent.
Routing connectivity of the longlines is shown in Figure 27
on page 34.
Direct Interconnect (XC4000EX only)
The XC4000EX offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 31. Signals routed on
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the
right and bottom edges of the array has a direct path to the
nearest two IOBs, since there are tw o IOBs for each ro w or
column of CLBs.
The place and route software uses direct interconnect
whenev er possible , to maximize routing resources and min-
imize interconnect delays.
CLB
IOB
X6603
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
CLB
~
~~
~~
~~
~
~
~~
~
~
~~
~
~
~~
~
Figure 31: XC4000EX Direct Interconnect
XC4000 Series Field Programmable Gate Arrays
4-38 June 1, 1996 (Version 1.02)
I/O Routing
XC4000-Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The
VersaRing facilitates pin-swapping and redesign without
affecting board layout. Included are eight double-length
lines spanning two CLBs (four IOBs), and four longlines.
Global lines and Wide Edge Decoder lines are provided.
XC4000EX devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure 32. The shaded arrows represent routing present
only in XC4000EX devices.
Figure 33 is a detailed diagram of the XC4000E and
XC4000EX VersaRing. The area shown includes tw o IOBs.
There are two IOBs per CLB row or column, therefore this
diagram corresponds to the CLB routing diagram shown in
Figure 27 on page 34. The shaded areas represent routing
and routing connections present only in XC4000EX
devices.
X5995
Direct
Connect Edge
DecodeDouble Long Global
Clock Octal
Quad
Single
Double
Long
Direct
Connect
Long
INTERCONNECT
IOB
WED
WED
WED
IOB
Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge)
WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000EX only)
June 1, 1996 (Version 1.02) 4-39
T
O
C
L
B
A
R
R
A
Y
IK
OK
I1
CE
I2
DECODER
TO
OCTAL
EDGE
DECODE
QUAD
LONG
SINGLE
DOUBLE
LONG
LONG
DOUBLE
DOUBLE
GLOBAL
IK
OK
I1
CE
I2
TO
DECODER DECODER
Common to XC4000E and XC4000EX
XC4000EX only
IOB
IOB
DIRECT
Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series IOB (Left Edge)
XC4000 Series Field Programmable Gate Arrays
4-40 June 1, 1996 (Version 1.02)
Octal I/O Routing (XC4000EX only)
Between the XC4000EX CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 34.)
These routing tracks are called octals , because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buff-
ers are staggered, so each line goes through a buffer at
every eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure 34.
IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Segment with nearest buffer
connects to segment with furthest buffer
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
X6607
Figure 34: XC4000EX Octal I/O Routing
June 1, 1996 (Version 1.02) 4-41
Global Nets and Buffers
Both the XC4000E and the XC4000EX hav e dedicated glo-
bal networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
described in detail in the following sections. The text
descriptions and diagrams are summarized in Table 17.
The table shows which CLB and IOB clock pins can be
sourced by which global buffers.
In both XC4000E and XC4000EX devices, placement of a
library symbol called BUFG results in the software choos-
ing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.
Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are
in addition to the vertical longlines used for standard inter-
connect. The four global lines can be driven by either of
two types of global buffers. The clock pins of every CLB
and IOB can also be sourced from local interconnect.
Two different types of clock buffers are available in the
XC4000E:
• Primary Global Buffers (BUFGP)
• Secondary Global Buffers (BUFGS)
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
The Primary Global buffers must be driven by the semi-
dedicated pads. The Secondary Global buffers can be
sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Pr i-
mary Global buffer, or by any of the Secondary Global buff-
ers, as shown in Figure 35. Each corner of the device has
one Primary buffer and one Secondary buffer.
IOBs along the left and right edges have f our v ertical global
longlines. Top and bottom IOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specified for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code. If desired, attach a LOC
attribute or proper ty to direct placement to the designated
location. For e xample, attach a LOC=L attrib ute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
L = Left, R = Right, T = Top, B = Bottom
Table 17: Clock Pin Access
XC4000E XC4000EX Local
Inter-
connect
BUFGP BUFGS BUFGLS L & R
BUFGE T & B
BUFGE BUFFCL
K
All CLBs in Quadrant √√√√√ √
All CLBs in Device √√√ √
IOBs on Adjacent Vertical
Half Edge √√√√√√√
IOBs on Adjacent Vertical
Full Edge √√√√ √
IOBs on Adjacent Horizontal
Half Edge (Direct) √ √
IOBs on Adjacent Horizontal
Half Edge (through CLB globals) √√√√√ √
IOBs on Adjacent Horizontal
Full Edge (through CLB globals) √√√ √
XC4000 Series Field Programmable Gate Arrays
4-42 June 1, 1996 (Version 1.02)
X4 X4
X6604
X4
4
One BUFGP
per Global Line
One BUFGP
per Global Line
Any BUFGS Any BUFGS
BUFGP
PGCK4 SGCK4
PGCK3
SGCK3
BUFGS
BUFGP
BUFGS
IOB
IOB
IOBIOBIOBIOB
IOBIOBIOB
IOB
IOB
BUFGS
BUFGS
BUFGP
BUFGP
SGCK1
PGCK1
SGCK2 PGCK2
IOB
X4 locals
localslocals
locals
locals
locals
locals
locals
locals
locals
locals
locals
4
44
CLB
CLB
locals locals
CLB
CLB
locals locals
Figure 35: XC4000E Global Net Distribution
X4
4
IOB
CLOCKS
CLB CLOCKS
(PER COLUMN)
CLB CLOCKS
(PER COLUMN)
CLB CLOCKS
(PER COLUMN)
CLB CLOCKS
(PER COLUMN)
locals
locals
locals
locals
locals
BUFGLS locals
BUFGLS
BUFGLS
BUFGLS BUFGLS
BUFGE
BUFGE
BUFGE
BUFGE
BUFGE
BUFGE
BUFGE BUFGE
BUFGLS BUFGLS
IOB IOB IOB IOB
IOB IOB IOB IOB
BUFGLS BUFGLS
BUFGLS BUFGLS
GCK8 GCK7
GCK1 GCK6
BUFFCLK BUFFCLK
BUFFCLK
FCLK1 FCLK4
FCLK2
BUFFCLK
FCLK3
GCK2 GCK5
GCK3 GCK4
IOB
IOB
IOB
IOB
locals
BUFGLS
locals BUFGLS
locals
locals
BUFGLS locals
BUFGLS
IOB
CLOCKS
IOB
CLOCKS
IOB
CLOCKS
4
X8
X8
X4
X6694
8
8
8 8
8BUFGLS
locals
8
8 8
8 8
8
8
8
8
CLB
CLB
CLB
CLB
locals
locals
locals
locals
locals
locals
locals
locals
X8
X8
X8
X8
Figure 36: XC4000EX Global Net Distribution
June 1, 1996 (Version 1.02) 4-43
Global Nets and Buffers (XC4000EX only)
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to
the vertical longlines used for standard interconnect. The
global lines are broken in the center of the array, to allow
faster distribution and to minimize skew across the whole
array. Each half-column global line has its own buffered
multiple xer , as sho wn in Figure 36. The top and bottom glo-
bal lines cannot be connected across the center of the
device, as this connection might introduce unacceptable
skew. The top and bottom halves of the global lines must
be separately driven — although they can be driven by the
same global buffer.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
single, double, and quad lines at the top, bottom, half, and
quarter points. Consequently, the number of different
clocks that can be used simultaneously in an XC4000EX
device is very large.
There are four global lines feeding the IOBs at the left edge
of the device. IOBs along the right edge have eight global
lines. There is a single global line along the top and bottom
edges with access to the IOBs. All IOB global lines are bro-
ken at the center. They cannot be connected across the
center of the device, as this connection might introduce
unacceptable skew.
IOB global lines can be driven from any of three types of
global buffers, or from local interconnect. Alternatively, top
and bottom IOBs can be clock ed from the global lines in the
adjacent CLB column.
Three different types of clock buffers are available in the
XC4000EX:
• Global Low-Skew Buffers (BUFGLS)
• Global Early Buffers (BUFGE)
• FastCLK Buffers (BUFFCLK)
Global Low-Skew Buffers are the standard clock buffers.
They should be used f or most internal clocking, whene ver a
large portion of the device must be driven.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster I/O interface.
FastCLK buffers are specifically designed to provide the
fastest possible I/O clock. They have only the standard
input access to CLBs, through local interconnect.
Figure 36 is a conceptual diagram of the global net struc-
ture in the XC4000EX.
Global Early buffers and Global Low-Skew buffers share a
single pad. Therefore, the same IPAD symbol can drive
one buffer of each type, in parallel. This configuration is
particularly useful when using the Fast Capture latches, as
described in “IOB Input Signals” on page 24. Paired Global
Early and Global Low-Ske w buffers share a common input;
they cannot be driven by two different signals.
Choosing an XC4000EX Clock Buffer
The clocking structure of the XC4000EX provides a large
variety of features. However, it can be simple to use, with-
out understanding all the details. The software automati-
cally handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, r ather than a specific
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided f or those users who w ant a finer level of
control over their designs.
If fine control is desired, use the following summary and
Table 17 on page 41 to choose an appropriate clock buffer.
• The simplest thing to do is to use a Global Low-Skew
buffer.
• If a faster clock path is needed, try a BUFG. The
software will first try to use a Global Low-Ske w Buffer. If
timing requirements are not met, a faster buffer will
automatically be used.
• If a single quadrant of the chip is sufficient for the
clock ed logic, and the timing requires a f aster clock than
the Global Low-Skew buffer, use a Global Early buffer.
• In special cases, where both external and internal
timing have been carefully studied, a FastCLK buffer
can be used, for the fastest possible I/O clock path.
Global Low-Skew Buffers
Each corner of the XC4000EX device has two Global Low-
Skew buffers. Any of the eight Global Low-Skew buffers
can drive any of the eight vertical Global lines in a column
of CLBs. In addition, any of the buffers can driv e any of the
four v ertical lines accessing the IOBs on the left edge of the
device, and any of the eight vertical lines accessing the
IOBs on the right edge of the device. (See Figure 37 on
page 44.)
IOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
as in the XC4000E. Any Global Low-Skew buffer can,
therefore, access every IOB and CLB in the device.
The Global Low-Sk e w buffers can be driv en b y either semi-
dedicated pads or internal logic.
To use a Global Low-Skew buffer, place a BUFGLS ele-
ment in a schematic or in HDL code. If desired, attach a
LOC attribute or proper ty to direct placement to the desig-
nated location. For example, attach a LOC=T attribute or
property to direct that a BUFGLS be placed in one of the
two Global Low-Sk ew b uff ers on the top edge of the de vice,
or a LOC=TR to indicate the Global Low-Sk ew buff er on the
top edge of the device, on the right.
XC4000 Series Field Programmable Gate Arrays
4-44 June 1, 1996 (Version 1.02)
Global Early Buffers
Each corner of the XC4000EX device has two Global Early
buffers. The primary purpose of the Global Early buffers is
to provide an earlier clock access than the potentially
heavily-loaded Global Low-Skew buffers. A clock source
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo-
bal Low-Skew buffer clock edge, due to the lighter loading.
Global Early buff ers also f acilitate the f ast capture of de vice
inputs, using the Fast Capture latches described in “IOB
Input Signals” on page 24. For Fast Capture, take a single
clock signal, and route it through both a Global Early buffer
and a Global Low-Skew buffer. (The two buffers share an
input pad.) Use the Global Early buffer to clock the Fast
Capture latch, and the Global Low-Sk ew b uffer to clock the
normal input flip-flop or latch, as shown in Figure 18 on
page 26.
The Global Early buff ers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early
clock in the output flip-flop IOB must be taken into consid-
eration when calculating the internal clock speed for the
design.
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the
top and bottom. Refer to Figure 38, Figure 39, and
Figure 36 on page 42 while reading the following explana-
tion.
Each Global Early buffer can access the eight vertical Glo-
bal lines for all CLBs in the quadrant. Therefore, only one-
fourth of the CLB clock pins can be accessed. This restric-
tion is in large par t responsible for the faster speed of the
buffers, relative to the Global Low-Skew buffers.
The left-side Global Early buffers can each drive two of the
four v ertical lines accessing the IOBs on the entire left edge
of the device. The right-side Global Early buffers can each
drive two of the eight vertical lines accessing the IOBs on
the entire right edge of the device. (See Figure 38.)
Each left and right Global Early buffer can also drive half of
the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
the Global Early buffers.
The top and bottom Global Early buffers can drive half of
the IOBs along either the left or right edge of the device, as
shown in Figure 39. They can only access the top and bot-
tom IOBs via the CLB global lines.
16
25
3
8
4
7
CLB CLB
CLBCLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB IOB
IOBIOB
X6753
Figure 37: Any BUFGLS (GCK1 - GCK8) Can
Drive Any or All Clock Inputs on the Device
16
25
3
8
4
7
CLB CLB
CLBCLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB IOB
IOBIOB
X6751
Figure 38: Left and Right BUFGEs Can Drive An y or
All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK3 and GCK4 are similar.)
16
25
3
8
4
7
CLB CLB
CLBCLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB IOB
IOBIOB
X6747
Figure 39: Top and Bottom BUFGEs Can Drive Any
or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)
June 1, 1996 (Version 1.02) 4-45
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. The y share pads with the Glo-
bal Low-Sk ew b uffers, so a single net can drive both global
buffers, as described above.
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or proper ty to direct placement to the designated
location. For example, attach a LOC=T attribute or prop-
erty to direct that a BUFGE be placed in one of the two Glo-
bal Early buffers on the top edge of the device, or a
LOC=TR to indicate the Global Early buff er on the top edge
of the device, on the right.
FastCLK Buffers
The fastest way to bring a clock into the XC4000EX device
is through a FastCLK buffer. Two FastCLK buffers are
present on the left edge, and two on the right edge, of the
XC4000EX die. There are no F astCLK b uff ers on the top or
bottom edges.
One purpose of the FastCLK b uffers is to create a very fast
pin-to-pin path by using the IOB 2-input function generator
in conjunction with the FastCLK. Drive the F input of the
IOB function generator with the FastCLK buffer output, as
described in “IOB Output Signals” on page 27.
Alternatively, a FastCLK b uffer can be used to minimize the
setup time of device inputs , if a positiv e hold time is accept-
able. Use the FastCLK buffer to clock the Fast Capture
latch, and a slower clock buffer to clock the standard IOB
flip-flop or latch. Either the Global Early buff er or the Global
Low-Skew buffer can be used for the second storage ele-
ment, but whichever one is used should be the same clock
as the related internal logic. Since the FastCLK pads are
different from the Global Early and Global Low-Ske w pads,
care must be taken to ensure that skew external to the
device does not create internal timing difficulties.
The FastCLK buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, a fast clock
in the output flip-flop IOB must be taken into consideration
when calculating the internal clock speed for the design.
The FastCLK b uffers are limited to accessing IOBs on one-
half of the die edge only, as shown in Figure 40 and
Figure 36 on page 42. They can each drive two of the four
vertical lines accessing the IOBs on the left edge of the
device , or tw o of the eight vertical lines accessing the IOBs
on the right edge of the device. They can only access the
CLB array through single- and double-length lines.
The FastCLK b uffers must be driv en by the semi-dedicated
IOBs. They are not accessible from internal nets. Other
than the FastCLK feature, these IOBs are identical to all
other IOBs.
To use a FastCLK buffer, place a BUFFCLK element in a
schematic or in HDL code. If desired, attach a LOC
attribute or proper ty to direct placement to the designated
location. For example, attach a LOC=LB attribute or prop-
erty to direct that a BUFFCLK be placed on the left edge of
the device at the bottom, or use LOC=L to indicate either of
the buffers on the left edge.
The input to the BUFFCLK symbol must be driven by a
input pad symbol, such as IPAD, or by an input flip-flop or
latch, such as INFF, ILD, ILDFFDX, or ILDFLDX.
14
23
CLB CLB
CLBCLB
I
O
B
I
O
B
I
O
B
I
O
B
IOB IOB
IOBIOB
X6745
Figure 40: Each BUFFCLK Can Drive Any or
All Clock Inputs in Same Half-Edge (FCLK1 is shown.
FCLK2, FCLK3 and FCLK4 are similar.)
XC4000 Series Field Programmable Gate Arrays
4-46 June 1, 1996 (Version 1.02)
Power Distribution
Power f or the FPGA is distrib uted through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 41. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
Typically, a 0.1 µF capacitor connected near the Vcc and
Ground pins of the package will provide adequate decou-
pling.
Output buffers capable of driving/sinking the specified 12
mA (XC4000E) or 24 mA (XC4000EX) loads under speci-
fied worst-case conditions may be capable of driving/sink-
ing up to 10 times as much current under best case
conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buff ers near the Ground pads . The I/O Bloc k
output buff ers hav e a slew-rate limited mode (def ault) which
should be used where output rise and fall times are not
speed-critical.
Pin Descriptions
There are three types of pins in the XC4000-Series
devices:
• Permanently dedicated pins
• User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used f or the
configuration process are 3-stated with a 50 kΩ - 100 kΩ
pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 50 kΩ - 100 kΩ pull-up resistor.
XC4000-Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global Set/
Reset net, GSR. See “Global Set/Reset” on page 13 for
more information on GSR.
XC4000-Series devices have no Powerdown control input,
as the XC3000 and XC2000 families do. The XC3000/
XC2000 P owerdo wn control also 3-stated all of the device I/
O pins. For XC4000-Series de vices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See “IOB Output
Signals” on page 27 for more information on GTS.
Device pins for XC4000-Series devices are described in
Table 18. Pin functions during configuration for each of the
seven configuration modes are summar ized in Table 24 on
page 78, in the “Configuration Timing” section.
GND
Ground and
Vcc Ring for
I/O Drivers
Vcc
GND
Vcc
Logic
Power Grid
X5422
Figure 41: XC4000-Series Power Distribution
June 1, 1996 (Version 1.02) 4-47
Table 18: Pin Descriptions
Pin Name
I/O
During
Config.
I/O
After
Config. Pin Description
Permanently Dedicated Pins
VCC I I Eight or more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 µF capacitor to Ground.
GND I I Eight or more (depending on package type) connections to Ground. All must be con-
nected.
CCLK I or O I
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
can be selected as the Readback Clock. There is no CCLK High time restriction on
XC4000-Series devices, except during Readback. See “Violating the Maximum High
and Low Time Specification for the Readback Clock” on page 65 for an explanation of
this exception.
DONE I/O O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-
puts.
The optional pull-up resistor is selected as an option in MakeBits, the XACT
step
pro-
gram that creates the configuration bitstream. The resistor is included by default.
PROGRAM II
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
RDY/BUSY O I/O
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
RCLK O I/O
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000EX) is preceded by a rising edge on RCLK, a redundant output signal. RCLK
is useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
M0, M1, M2 I I (M0),
O (M1),
I (M2)
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 kΩ is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
XC4000 Series Field Programmable Gate Arrays
4-48 June 1, 1996 (Version 1.02)
TDO O O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
TDI, TCK,
TMS II/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
HDC O I/O High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
LDC O I/O Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
INIT I/O I/O
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
PGCK1 -
PGCK4
(XC4000E
only)
Weak
Pull-up I or I/O
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primar y Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
SGCK1 -
SGCK4
(XC4000E
only)
Weak
Pull-up I or I/O
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
GCK1 -
GCK8
(XC4000EX
only)
Weak
Pull-up I or I/O
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
must share an input signal. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
FCLK1 -
FCLK4
(XC4000EX
only)
Weak
Pull-up I or I/O
Four FCLK inputs can each drive a FastCLK buffer. The FastCLK buffers cannot be
driven from internal logic. If not used to drive a global buffer, any of these pins is a user-
programmable I/O.
Any input pad symbol connected directly to the input of a BUFFCLK symbol is automat-
ically placed on one of these pins.
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O
After
Config. Pin Description
June 1, 1996 (Version 1.02) 4-49
CS0, CS1,
WS, RS I I/O
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
and drives D0 - D6 High.
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
A0 - A17 O I/O During Master Parallel configuration, these 18 output pins address the configuration
EPROM. After configuration, they are user-programmable I/O pins.
A18 - A21
(XC4000EX
only) O I/O During Master Parallel configuration with an XC4000EX master, these 4 output pins add
4 more bits to address the configuration EPROM. After configuration, they are user-pro-
grammable I/O pins.
D0 - D7 I I/O During Master Parallel and Peripheral configuration, these eight input pins receive con-
figuration data. After configuration, they are user-programmable I/O pins.
DIN I I/O During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
DOUT O I/O
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DIN input.
In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
I/O Weak
Pull-up I/O These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (50 kΩ - 100 kΩ) that defines the logic level as High.
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O
After
Config. Pin Description
XC4000 Series Field Programmable Gate Arrays
4-50 June 1, 1996 (Version 1.02)
Boundary Scan
The ‘bed of nails’ has been the tr aditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti-
cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE Boundary Scan Stan-
dard 1149.1 was developed to facilitate board-level testing
of electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan-compatible IC. IEEE 1149.1-compati-
ble devices may be serial daisy-chained together, con-
nected in parallel, or a combination of the two.
The XC4000 Series implements IEEE 1149.1-compatible
BYPASS, PRELOAD/SAMPLE and EXTEST boundary
scan instructions. When the boundary scan configuration
option is selected, three normal user I/O pins become ded-
icated inputs for these functions. Another user output pin
becomes the dedicated boundary scan output. The details
of how to enable this circuitry are covered later in this sec-
tion.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driv-
ing of their outputs and to examine their inputs. This
method is an improvement over bed-of-nails testing. It
av oids the need to ov er-drive device outputs , and it reduces
the user interface to four pins. An optional fifth pin, a reset
for the control logic, is described in the standard but is not
implemented in Xilinx devices.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state state machine, an instruction
register and a number of data registers. The functional
details can be found in the IEEE 1149.1 specification and
are also discussed in the Xilinx application note XAPP 017:
"
Boundary Scan in XC4000 Devices
."
Figure 42 shows a simplified block diagram of the
XC4000E Input/Output Block with boundary scan imple-
mented. XC4000EX boundary scan logic is identical.
Figure 43 on page 52 is a diagram of the XC4000-Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Por t controller, and
the Instruction Register with decodes.
XC4000-Series devices can also be configured through the
boundary scan logic. See “Configuration Through the
Boundary Scan Pins” on page 64.
Data Registers
The primary data register is the boundary scan register.
For each IOB pin in the FPGA, bonded or not, it includes
three bits for In, Out and 3-State Control. Non-IOB pins
have appropriate partial bit population for In or Out only.
PROGRAM, CCLK and DONE are not included in the
boundary scan register. Each EXTEST CAPTURE-DR
state captures all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instruc-
tions, two corresponding pins (BSCAN.TDO1 and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
Instruction Set
The XC4000-Series boundary scan instruction set also
includes instructions to configure the device and read bac k
the configuration data. The instruction set is coded as
shown in Table 19.
Table 19: Boundary Scan Instructions
Instruction
I2 I1 I0 Test
Selected TDO Source I/O Data
Source
0 0 0 EXTEST DR DR
0 0 1 SAMPLE/
PRELOAD DR Pin/Logic
0 1 0 USER 1 BSCAN.
TDO1 User Logic
0 1 1 USER 2 BSCAN.
TDO2 User Logic
1 0 0 READBACK Readback
Data Pin/Logic
1 0 1 CONFIGURE DOUT Disabled
1 1 0 Reserved — —
1 1 1 BYPASS Bypass
Register —
June 1, 1996 (Version 1.02) 4-51
D
EC
Q
M
M
QL
rd
M
DELAY
M M
M M
Input Clock IK
I - capture
I - update
GLOBAL
S/R
FLIP-FLOP/LATCH
INVERT
S/R
Input Data 1 I1
Input Data 2 I2
X5792
PAD
VCC
SLEW
RATE PULL
UP
M
OUT
SEL
D
EC
Q
rd
M
M
M
INVERT
OUTPUT
M
M
INVERT
S/R
Ouput Clock OK
Clock Enable
Ouput Data O
O - update
Q - capture
O - capture
Boundary
Scan
MEXTEST
TS - update
TS - capture
3-State TS
sd
sd
TS INV
OUTPUT
TS/OE
PULL
DOWN
INPUT
Boundary
Scan
Boundary
Scan
Figure 42: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000EX Boundary Scan Logic is Identical.
XC4000 Series Field Programmable Gate Arrays
4-52 June 1, 1996 (Version 1.02)
D Q
D Q
D Q
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
BYPASS
REGISTER
IOB IOB
TDO
TDI
IOB IOB IOB
M
U
X
TDO
TDI
IOB
IOB
IOB
IOB
IOB
IOB
IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB IOB IOB IOB IOB
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DQ
LE
sd
sd
LE
DQ
DQ
DQ
1
0
1
0
1
0
1
0
DQ
LE
sd
sd
LE
DQ
sd
LE
DQ
IOB
D Q
D Q
1
0
1
0DQ
LE
sd
sd
LE
DQ
1
0
DATA IN
IOB.T
IOB.Q
IOB.I
IOB.Q
IOB.T
IOB.I
IOB.O
SHIFT/
CAPTURE CLOCK DATA
REGISTER
DATAOUT UPDATE EXTEST
X1523
INSTRUCTION REGISTER
INSTRUCTION REGISTER
BYPASS
REGISTER
Figure 43: XC4000-Series Boundary Scan Logic
June 1, 1996 (Version 1.02) 4-53
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only M0 and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the output-
only M1 pin contributes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are pr imarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in XDE or
Epic), star ting in the upper right chip cor ner, the boundary
scan data-register bits are ordered as shown in Figure 44.
The device-specific pinout tables for the XC4000 Series
include the boundary scan locations for each IOB pin.
BSDL (Boundary Scan Description Language) files for
XC4000-Series devices are available on the Xilinx BBS.
Including Boundary Scan in a Schematic
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 45.
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest wa y to pre v ent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
Avoiding Inadvertent Boundary Scan
Activation
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
• TMS: Tie High to put the Test Access Port controller
in a benign RESET state
• TCK: Tie High or Low—don't toggle this clock input.
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “
Boundary Scan in
XC4000E Devices
.“
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD
(TDI end)
X6075
Figure 44: Boundary Scan Bit Sequence
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
X2675
Figure 45: Boundary Scan Schematic Example
XC4000 Series Field Programmable Gate Arrays
4-54 June 1, 1996 (Version 1.02)
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
XC4000-Series devices use sev eral hundred bits of config-
uration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls either a function look-up table bit, a multi-
plexer input, or an interconnect pass transistor . The XACT-
step
development system translates the design into a
netlist file. It automatically partitions, places and routes the
logic and generates the configuration data in PR OM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
can be used as an output. The XACT
step
development
system does not use these resources unless they are
explicitly specified in the design entry. This is done b y plac-
ing a special pad symbol called MD2, MD1, or MD0 instead
of the input or output pad symbol.
In XC4000-Series devices, the mode pins have weak pull-
up resistors during configuration. With all three mode pins
High, Slav e Serial mode is selected, which is the most pop-
ular configuration mode. Therefore, for the most common
configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k Ω.) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 4.7 kΩ is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Configuration Modes
XC4000E devices have six configuration modes.
XC4000EX devices have the same six modes, plus an
additional configuration mode. These modes are selected
by a 3-bit input code applied to the M2, M1, and M0 inputs .
There are three self-loading Master modes, two Peripheral
modes, and a Serial Slave mode, which is used primarily
for daisy-chained devices. The seventh mode, called
Express mode, is an additional slave mode that allows
high-speed parallel configuration of the high-capacity
XC4000EX devices. The coding for mode selection is
shown in Table 20.
Note: * Peripheral Synchronous can be considered byte-
wide Slave Parallel
A detailed description of each configuration mode, with tim-
ing information, is included later in this data sheet. Dur ing
configuration, some of the I/O pins are used temporarily f or
the configuration process. All pins used during configura-
tion are shown in Table 24 on page 78.
Master Modes
The three Master modes use an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential sla ve
devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receiv e byte parallel data.
The data is internally ser ialized into the FPGA data-frame
format. The up and down selection generates starting
addresses at either zero or 3FFFF, for compatibility with dif-
ferent microprocessor addressing conventions. The Master
Serial mode generates CCLK and receives the configura-
tion data in serial form from a Xilinx serial-configuration
PROM.
CCLK speed is selectable as either 1 MHz (default) or 8
MHz (up to 10% lower for low-voltage devices). Configura-
tion always starts at the default slow frequency, then can
switch to the higher frequency during the first frame. Fre-
quency tolerance is -50% to +25%.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
nal. In Asynchronous Peripheral mode , the internal oscilla-
tor generates a CCLK burst signal that serializes the byte-
wide data. CCLK can also drive slave devices. In the syn-
Table 20: Configuration Modes
Mode M2 M1 M0 CCLK Data
Master Serial 0 0 0 output Bit-Serial
Slave Serial 1 1 1 input Bit-Serial
Master
Parallel Up 1 0 0 output Byte-Wide,
increment
from 00000
Master
Parallel Down 1 1 0 output Byte-Wide,
decrement
from 3FFFF
Peripheral
Synchronous* 0 1 1 input Byte-Wide
Peripheral
Asynchronous 1 0 1 output Byte-Wide
Express
(XC4000EX
only)
0 1 0 input Byte-Wide
Reserved 0 0 1 — —
June 1, 1996 (Version 1.02) 4-55
chronous mode, an e xternally supplied clock input to CCLK
serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a “daisy chain,” and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in par allel, as shown in Figure 55 on page 68.
Connect the DOUT of each device to the DIN of the next.
The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configura-
tion bit is received. Figure 49 on page 61 shows the star t-
up timing for an XC4000-Series device.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The MakePROM program
must be used to combine the bitstreams for a daisy-
chained configuration.
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, there-
fore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
chain contains XC4000-Series devices, the master nor-
mally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 49 on page 61.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, the y all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 49. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000-
Series device, not reaching F means that readback cannot
be initiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, mak e sure that the y occur at the
proper time and the finish point F is reached. Timing is con-
trolled using MakeBits options.
XC3000 Master with an XC4000-Series Slave
Some designers want to use an inexpensive lead device in
peripheral mode and hav e the more precious I/O pins of the
XC4000-Series devices all a v ailab le f or user I/O . Figure 46
provides a solution for that case.
This solution requires one CLB, one IOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be config-
ured with late Internal Reset, which is the default option.
One CLB and one IOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC4000-Series devices. When the lead device
removes the internal RESET signal, the 2-bit shift register
responds to its clock input and generates an active Low
output signal for the duration of the subsequent clock
period. An external connection between this output and
CCLK thus creates the extra CCLK pulse.
Express Mode (XC4000EX only)
Express mode is similar to Slave Serial mode, except the
data is presented in parallel format, and is clocked into the
target device a b yte at a time rather than a bit at a time. The
data is loaded in parallel into eight different columns: it is
not internally serialized. Eight bits of configuration data are
loaded with ever y CCLK cycle, therefore this configuration
Output
Connected
to CCLK
OE/T
0
1
1
0
0
.
.
0
0
1
1
1
.
.
Reset
X5223
etc
Active Low Output
Active High Output
Figure 46: CCLK Generation for XC3000 Master
Driving an XC4000-Series Slave
XC4000 Series Field Programmable Gate Arrays
4-56 June 1, 1996 (Version 1.02)
mode runs at eight times the data rate of the other six
modes. A length count is not used in Express mode.
Express mode must be specified as an option to the Make-
Bits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six config-
uration modes.
Multiple slave devices with identical configurations can be
wired with parallel D0-D7 inputs. In this way, multiple
devices can be configured simultaneously.
Pseudo Daisy Chain
Multiple devices with different configurations can be con-
nected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bit-
stream is used to configure the chain of Express mode
devices, but the input data bus must drive D0-D7 of each
device. Tie High the CS1 pin of the first device to be con-
figured. Connect the DOUT pin of each FPGA to the CS1
pin of the next device in the chain. The D0-D7 inputs are
wired to each device in parallel. The DONE pins are wired
together, with one or more internal DONE pull-ups acti-
vated. Alternatively, a 4.7 kΩ external resistor can be used,
if desired. (See Figure 63 on page 76.)
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All XC4000EX devices in Express mode are synchronized
to the DONE pin. User I/O for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by MakeBits options.) Since the
DONE pin is open-drain and does not drive a High value,
tying the DONE pins of all devices together prevents all
devices in the chain from going High until the last device in
the chain has completed its configuration cycle.
Because only XC4000EX and XC5200 devices support
Express mode, only these devices can be used to form an
Express mode daisy chain. XC5200 devices used in a
combined daisy chain with XC4000EX devices should be
configured as synchronized to DONE (MakeBits option
CCLK_SYNC or UCLK_SYNC), and their DONE pins wired
together with those of the XC4000EX devices.
Setting CCLK Frequency
For Master modes , CCLK can be gener ated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz (up to 10% low er f or low-
voltage de vices). In f ast CCLK mode, the frequency r anges
from 4 MHz to 10 MHz (up to 10% lower for low-voltage
devices). The frequency is selected b y an option when run-
ning MakeBits , the bitstream generation software tool. If an
XC4000-Series Master is driving an XC3000- or XC2000-
family sla ve , slow CCLK mode must be used. Slow mode is
the default.
Data Stream Format
The data stream (“bitstream”) format is identical f or all con-
figuration modes, with the exception of Express mode. In
Express mode, the device becomes active when DONE
goes High, therefore no length count is required. Addition-
ally, CRC error checking is not supported in Express mode.
The data stream formats are shown in Table 21. Express
mode data is shown with D0 at the left and D7 at the right.
For all other modes, bit-serial data is read from left to right,
and byte-parallel data is effectively assembled from this
serial bitstream, with the first bit in each byte assigned to
D0.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Express
mode). This header is followed by the actual configuration
data in frames. The length and number of frames depends
on the device type (see Table 22 and Table 23). Each
frame begins with a start field and ends with an error check.
In all modes except Express mode, a postamble code is
required to signal the end of data for a single device. In all
cases, additional start-up bytes of data are required to pro-
vide four clocks for the startup sequence at the end of con-
figuration. Long daisy chains require additional startup
bytes to shift the last data through the chain. All startup
bytes are don’t-cares; these bytes are not included in bit-
streams created by the Xilinx software.
Table 21: XC4000-Series Data Stream Formats
LEGEND:
Data Type Express Mode
(D0-D7) All Other
Modes (D0...)
Fill Byte 11111111b 11111111b
Preamble Code 11110010b 0010b
Length Count FFFFFFh COUNT(23:0)
Fill Bits — 1111b
Start Field 11010010b 0b
Data Frame DATA(n-1:0) DATA(n-1:0)
CRC or Constant
Field Check 11010010b xxxx (CRC)
or 0110b
Extend Write Cycle FFFFFFFFFFh —
Postamble — 01111111b
Start-Up Bytes xxxxxxxxh xxh
Unshaded Once per bitstream
Light Once per data frame
Dark Once per device
June 1, 1996 (Version 1.02) 4-57
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
The MakeBits softw are creates the configuration bitstream.
In Express mode, only non-CRC error checking is sup-
por ted. In all other modes, MakeBits allows a selection of
CRC or non-CRC error checking. The non-CRC error
checking tests for a designated end-of-frame field for each
frame. For CRC error chec king, Mak eBits calculates a run-
ning CRC and inser ts a unique four-bit par tial check at the
end of each frame. The 11-bit CRC chec k of the last fr ame
of an FPGA includes the last seven data bits.
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect INIT and initializ e a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits . The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 21. If a frame data
error is detected during the loading of the FPGA, the con-
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a W ait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 47. The checksum consists of the 11 most signif-
icant bits of the 16-bit code. A change in the checksum
indicates a change in the Readback bitstream. A compari-
son to a previous checksum is meaningful only if the read-
back data is independent of the current device state. CLB
outputs should not be included (Read Capture MakeBits
option not used), and if RAM is present, the RAM content
must be unchanged.
Statistically, one error out of 2048 might go undetected.
Table 22: XC4000E Program Data
Device XC4003E XC4005E/L XC4006E XC4008E XC4010E/L XC4013E/L XC4020E XC4025E
Max Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000
CLBs
(Row x Col.) 100
(10 x 10) 196
(14 x 14) 256
(16 x 16) 324
(18 x 18) 400
(20 x 20) 576
(24 x 24) 784
(28 x 28) 1,024
(32 x 32)
IOBs 80 112 128 144 160 192 224 256
Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560
Horizontal
Longlines 20 28 32 36 40 48 56 64
TBUFs per
Longline 12 16 18 20 22 26 30 34
Bits per Frame 126 166 186 206 226 266 306 346
Frames 428 572 644 716 788 932 1,076 1,220
Program Data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128
PROM Size
(bits) 53,976 95,000 119,832 147,544 178,136 247,960 329,304 422,168
XC4000 Series Field Programmable Gate Arrays
4-58 June 1, 1996 (Version 1.02)
Notes: 1. Bits per Frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits
Number of Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
3. Express mode bitfiles are slightly larger (see Table 21).
Table 23: XC4000EX Program Data
Device XC4028EX/XL XC4036EX/XL XC4044EX/XL XC4052XL XC4062XL
Max Logic Gates 28,000 36,000 44,000 52,000 62,000
CLBs
(Row x Col.) 1,024
(32 x 32) 1,296
(36 x 36) 1,600
(40 x 40) 1,936
(44 x 44) 2,304
(48 x 48)
IOBs 256 288 320 352 384
Flip-Flops 2,560 3,168 3,840 4,576 5,376
Horizontal Longlines 192 216 240 264 288
TBUFs per Longline 34 38 42 46 50
Bits per Frame 421 469 517 565 613
Frames 1587 1775 1963 2151 2,339
Program Data 668,127 832,483 1,014,879 1,215,323 1,433,807
PROM Size (bits) 668,167 832,523 1,014,919 1,215,363 1,433,847
0
X2
2345678910111213 141
X15 X16
15
SERIAL DATA IN
10 151413121110 9 8 7 651111
CRC – CHECKSUM
LAST DATA FRAME
START BIT
X1789
Polynomial: X16 + X15 + X2 + 1
Readback Data Stream
Figure 47: Circuit for Generating CRC-16
June 1, 1996 (Version 1.02) 4-59
Configuration Sequence
There are four major steps in the XC4000-Series pow er-up
configuration sequence.
• Configuration Memory Clear
• Initialization
• Configuration
• Start-Up
The full process is illustrated in Figure 48.
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PR OGRAM pin
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutiv ely initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is
asserted, the logic initiates one additional clearing of the
configuration frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC ,
INIT and DONE provide status outputs f or the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of pow er .
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250 µs (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac-
tive INIT. Two internal clocks after the INIT pin is recogniz ed
as High, the FPGA samples the three mode lines to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
INIT
High? if
Master
Sample
Mode Lines
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
VCC
>3.5 V
No
Yes
Yes
No
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3 µs per Frame
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Master CCLK
Goes Active
F
Pull INIT Low
and Stop
X6076
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration Memory
Once More
LDC Output = L, HDC Output = H
Boundary Scan
Instructions
Available:
I/O Active
Keep Clearing
Configuration Memory
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms PROGRAM
= Low
No
Yes
Yes
Figure 48: Power-up Configuration Sequence
XC4000 Series Field Programmable Gate Arrays
4-60 June 1, 1996 (Version 1.02)
Configuration
The 0010 preamble code, included for all modes except
Express mode, indicates that the following 24 bits repre-
sent the length count. The length count is the total n umber
of configuration clocks needed to load the complete config-
uration data. (Four additional configuration clocks are
required to complete the configuration process, as dis-
cussed below.) After the preamble and the length count
hav e been passed through to all de vices in the daisy chain,
DOUT is held High to prev ent frame start bits from reaching
any daisy-chained devices. In Express mode, the length
count bits are ignored, and DOUT is held Low, to disable
the next device in the pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configu-
ration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device. In Express mode, when the first
device is fully prog r ammed, DOUT goes High to enab le the
next device in the chain.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 48 on page 59.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PRO-
GRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The
XC4000-Series PROGRAM pin has a permanent weak
pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low exter-
nally, the device determines its configuration mode by cap-
turing its mode pins, and is ready to star t the configuration
process. A master device waits up to an additional 250 µs
to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
Start-Up
Star t-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must mak e sure that the
user-logic ‘wakes up’ gracefully, that the outputs become
active without causing contention with the configur ation sig-
nals, and that the internal flip-flops are released from the
global Reset or Set at the right time.
Figure 49 describes start-up timing for the three Xilinx fam-
ilies in detail. Express mode configuration always uses
either CCLK_SYNC or UCLK_SYNC timing, the other con-
figuration modes can use any of the f our timing sequences .
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional flexibility. The three
events — DONE going High, the inter nal Set/Reset being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected b y means of soft-
ware options in MakeBits, the bitstream generation soft-
ware.
The default option, and the most pr actical one , is f or DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 49, but the
designer can modify it to meet particular requirements.
Normally , the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
June 1, 1996 (Version 1.02) 4-61
XC4000E/EX
UCLK_SYNC
XC4000E/EX
UCLK_NOSYNC
XC4000E/EX
CCLK_SYNC
XC4000E/EX
CCLK_NOSYNC
XC3000
XC2000
CCLK
GSR Active
UCLK Period
DONE IN
DONE IN
Di Di+1 Di+2
Di Di+1 Di+2
U2 U3 U4
U2 U3 U4
U2 U3 U4C1
Synchronization
Uncertainty
Di Di+1
Di Di+1
DONE
I/O
GSR Active
DONE
I/O
GSR Active
DONE
C1 C2
C1 U2
C3 C4
C2 C3 C4
C2 C3 C4
I/O
GSR Active
DONE
I/O
DONE
Global Reset
I/O
DONE
Global Reset
I/O
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
CCLK Period
Length Count Match
F
F
F
F
F
F
X6700
C1, C2 or C3
Figure 49: Start-up Timing
XC4000 Series Field Programmable Gate Arrays
4-62 June 1, 1996 (Version 1.02)
The XC4000 Series offers another start-up clocking option,
UCLK_NOSYNC. The three events described above need
not be triggered by CCLK. They can, as a configuration
option, be triggered by a user clock. This means that the
device can wake up in synchronism with the user system.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device , the chip
could reach a point where the configuration of the de vice is
complete and the Done pin is asser ted, but the outputs do
not become active . The solution is either to recreate the bit-
stream specifying the star t-up clock as CCLK, or to supply
the appropriate user clock.
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a flip-flop Q0, shown in
Figure 50. Q0 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
• The release of the open-drain DONE output
• The change of configuration-related pins to the user
function, activating all IOBs.
• The termination of the global Set/Reset initialization of
all CLB and IOB storage elements.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the star t-up register. This is
called “Start-up Timing Synchronous to Done In” and is
selected by the CCLK_SYNC and UCLK_SYNC MakeBits
options.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is
selected by the CCLK_NOSYNC and UCLK_NOSYNC
MakeBits options.
As a configuration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3 pro-
vide the timing. Heavy lines in Figure 49 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
DONE Goes High to Signal End of Configuration
In all configuration modes except Express mode, XC4000-
Series devices read the e xpected length count from the bit-
stream and store it in an internal register. The length count
varies according to the number of devices and the compo-
sition of the daisy chain. Each device also counts the num-
ber of CCLKs during configuration.
Two conditions have to be met in order for the DONE pin to
go high:
• the chip's internal memory must be full, and
• the configuration length count must be met,
exactly
.
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take se v eral seconds [224 ∗ CCLK period] —
which is sometimes interpreted as the device not configur-
ing at all.
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value. The
XACT User Guide
includes detailed information about man-
ually altering the length count.
In Express mode, there is no length count. The DONE pin
for each de vice goes High when the device has received its
quota of configuration data. Wiring the DONE pins of sev-
eral devices together delays star t-up of all devices until all
are fully configured.
June 1, 1996 (Version 1.02) 4-63
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by MakeBits, the bitstream generation software.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay from
DONE High to active user I/O is controlled by a MakeBits
option.
Release of Global Set/Reset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The dela y from DONE High
to GSR inactive is controlled by a MakeBits option.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 49 on page 61. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
DONE
*
*
*
*
**
QS
R
1
0
0
1
1
0
1
0
1
0
0
1
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
Q2
Q3 Q1/Q4
DONE
IN
STARTUP
Q0 Q1 Q2 Q3 Q4
M
M
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
K
SQ
K
DQ
K
DQ
K
DQ
K
DQ
FULL
LENGTH COUNT
CLEAR MEMORY
CCLK
STARTUP.CLK
USER NET
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS" X1528
Figure 50: Start-up Logic
XC4000 Series Field Programmable Gate Arrays
4-64 June 1, 1996 (Version 1.02)
Configuration Through the Boundary Scan
Pins
XC4000-Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:
• Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Lo w for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configur ation if
a resistor is used to hold INIT Low.
• Issue the CONFIG command to the TMS input
• Wait for INIT to go High
• Sequence the boundary scan Test Access Port to the
SHIFT-DR state
• Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, ref er to the Xilinx application
note XAPP017, “
Boundary Scan in XC4000 Devices
.” This
application note also applies to XC4000E and XC4000EX
devices.
Readback
The user can read back the content of configuration mem-
ory and the level of certain inter nal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Note that in XC4000-Series devices, configuration data is
not
inverted with respect to configuration as it is in XC2000
and XC3000 families.
Readback of Express mode bitstreams results in data that
does not resemble the original bitstream, because the bit-
stream format differs from other modes.
XC4000-Series Readback does not use any dedicated
pins, b ut uses four internal nets (RDBK.TRIG, RDBK.D ATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
BACK library symbol and attach the appropr iate pad sym-
bols, as shown in Figure 51.
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
READBACK
DATA
RIP
TRIG
CLK READ_DATA
OBUF MD1
MD0 READ_TRIGGER
IBUF X1786
IF UNCONNECTED,
DEFAULT IS CCLK
Figure 51: Readback Schematic Example
June 1, 1996 (Version 1.02) 4-65
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with MakeBits, the bitstream
generation software.
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the f our CLB outputs, the IOB output flip-flops and
the input signals I1 and I2. Note that while the bits describ-
ing configuration (interconnect, function generators, and
RAM content) are
not
inv erted, the CLB and IOB output sig-
nals
are
inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
If the RAM capability of the CLBs is used, RAM data are
available in readback, since they directly overwrite the F
and G function-table configuration of the CLB.
RDBK.TRIG is located in the lower-left corner of the device ,
as shown in Figure 52.
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
readback cloc k per configuration fr ame) ma y be required to
re-initialize the control logic. The status of readbac k is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited f or security reasons, the readback control
nets are simply not connected.
RDBK.CLK is located in the lower right chip corner, as
shown in Figure 52.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. F or example , if a processor is controlling readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transf er mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep
track of the position within a data frame, and disable inter-
rupts before frame boundaries. Frame lengths and data
formats are listed in Table 21, Table 22 and Table 23.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
I/O I/O I/Ordbk
PROGRAMMABLE
INTERCONNECT
rdclk
I/O I/O
X1787
TRIG
DATA
RIP
I
Figure 52: READBACK Symbol in Graphical Editor
XC4000 Series Field Programmable Gate Arrays
4-66 June 1, 1996 (Version 1.02)
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that f eeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter . The ne xt data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In MakeBits, the user can specify Fast ConfigRate, which,
starting se veral bits into the first fr ame, increases the CCLK
frequency by a factor of eight. The value increases from
between 0.5 and 1.25 MHz, to a value between 4 and 10
MHz. (For low-voltage devices, the frequency can be up to
10% lower.) Be sure that the serial PROM and slaves are
fast enough to support this data rate. XC2000, XC3000/A,
and XC3100A devices do not support the Fast ConfigRate
option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a per manently High user output after con-
figuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.
Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).
XC4000E/EX
MASTER
SERIAL XC4000E/EX,
XC5200
SLAVE
XC3100A
SLAVE
XC1700D
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2M0 M1
DOUT
CCLK CLK
VCC
+5 V
DATA
CE CEO
VPP
RESET/OE DONE
DIN
LDC
INIT INIT
DONE
PROGRAM PROGRAM
D/P INIT
RESET
CCLK
DIN
CCLK
DINDOUT DOUT
M2
M0 M1 M1 PWRDN
M0
M2
(Low Reset Option Used)
4.7 KΩ
4.7 KΩ
4.7 KΩ4.7 KΩ4.7 KΩ
4.7 KΩ
4.7 KΩ
VCC
X6608
N/C
N/C
Figure 53: Master Serial Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-67
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 54: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1TDSCK
2TCKDS
n n + 1 n + 2
n – 3 n – 2 n – 1 n
X3223
Description Symbol Min Max Units
CCLK DIN setup 1 TDSCK 20 ns
DIN hold 2 TCKDS 0ns
XC4000 Series Field Programmable Gate Arrays
4-68 June 1, 1996 (Version 1.02)
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be av ailable at the DIN input of the lead FPGA a short setup
time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Slav e Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Sla ve Serial is the def ault mode if the mode
pins are left unconnected, as they hav e w eak pull-up resis-
tors during configuration.
XC4000E/EX
MASTER
SERIAL XC4000E/EX,
XC5200
SLAVE
XC3100A
SLAVE
XC1700D
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2M0 M1
DOUT
CCLK CLK
VCC
+5 V
DATA
CE CEO
VPP
RESET/OE DONE
DIN
LDC
INIT INIT
DONE
PROGRAM PROGRAM
D/P INIT
RESET
CCLK
DIN
CCLK
DINDOUT DOUT
M2
M0 M1 M1 PWRDN
M0
M2
(Low Reset Option Used)
4.7 KΩ
4.7 KΩ
4.7 KΩ4.7 KΩ4.7 KΩ
4.7 KΩ
4.7 KΩ
VCC
X6608
N/C
N/C
Figure 55: Slave Serial Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-69
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 56: Slave Serial Mode Programming Switching Characteristics
4TCCH
Bit n Bit n + 1
Bit nBit n - 1
3TCCO
5TCCL
2TCCD
1TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description Symbol Min Max Units
CCLK
DIN setup 1 TDCC 20 ns
DIN hold 2 TCCD 0ns
DIN to DOUT 3 TCCO 30 ns
High time 4 TCCH 45 ns
Low time 5 TCCL 45 ns
Frequency FCC 10 MHz
XC4000 Series Field Programmable Gate Arrays
4-70 June 1, 1996 (Version 1.02)
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre-
menting the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data—and all data that over-
flows the lead device—on its DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while oth-
ers must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the mem-
ory.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, M0). The EPROM addresses start at
00000 and increment.
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
M0 M1
DOUT
VCC
M2
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
PROGRAM
CCLK
DIN
M0 M1 M2
DOUT
PROGRAM
EPROM
(8K x 8)
(OR LARGER)
A10
A11
A12
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
DONE
D6
D5
D4
D3
D2
D1
D0
N/C
N/C
CE
OE
XC4000E/EX
SLAVE
8
DATA BUS
CCLK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INIT
INIT
. . .
. . .
. . . USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
DONE
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
A16 . . .
A17 . . .
HIGH 
or 
LOW
X6697
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
4.7KΩ
4.7KΩ
NOTE:M0 can be shorted
to Ground if not used
as I/O.
Figure 57: Master Parallel Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-71
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 58: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2TDRC
Address for Byte n + 1
D7D6
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1TRAC
7 CCLKs CCLK
3TRCD
Byte n - 1 X6078
Description Symbol Min Max Units
RCLK Delay to Address valid 1 TRAC 0 200 ns
Data setup time 2 TDRC 60 ns
Data hold time 3 TRCD 0ns
XC4000 Series Field Programmable Gate Arrays
4-72 June 1, 1996 (Version 1.02)
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first b yte of par allel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous P eripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, b ut it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisy-
chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
X5996
CONTROL
SIGNALS
DATA BUS
PROGRAM
DOUT
M0 M1 M2
D
0-7
INIT DONE
PROGRAM
4.7 kΩ
4.7 kΩ
4.7 kΩ
RDY/BUSY
V
CC
OPTIONAL
DAISY-CHAINED
FPGAs
NOTE:
M2 can be shorted to Ground
if not used as I/O
CCLK
CLOCK
PROGRAM
DOUT
XC4000E/EX
SLAVE
XC4000E/EX
SYNCHRO-
NOUS
PERIPHERAL
M0 M1
N/C
8
M2
DIN
INIT DONE
CCLK
N/C
Figure 59: Synchronous Peripheral Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-73
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 60: Synchronous Peripheral Mode Programming Switching Characteristics
0
DOUT
CCLK
1 2 34567
BYTE
0BYTE
1
BYTE 0 OUT BYTE 1 OUT
RDY/BUSY
INIT
1
0
X6096
Description Symbol Min Max Units
CCLK
INIT (High) setup time TIC 5µs
D0 - D7 setup time TDC 60 ns
D0 - D7 hold time TCD 0ns
CCLK High time TCCH 50 ns
CCLK Low time TCCL 60 ns
CCLK Frequency FCC 8 MHz
XC4000 Series Field Programmable Gate Arrays
4-74 June 1, 1996 (Version 1.02)
Asynchronous Peripheral Mode
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CS0 being Lo w and RS
and CS1 being High to accept byte-wide data from a micro-
processor bus . In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its DOUT pin. The RDY/
BUSY output from the lead FPGA acts as a handshake sig-
nal to the microprocessor. RDY/BUSY goes Low when a
byte has been received, and goes High again when the
byte-wide input buffer has transferred its information into
the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the RDY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until RDY/BUSY is High again for one CCLK period. Note
that RDY/BUSY is pulled High with a high-impedance pull-
up prior to INIT going High.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new
byte w as received, the BUSY signal lasts f or only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Note that after the last byte has been entered, only se ven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
The READY/BUSY handshake can be ignored if the delay
from any one Wr ite to the end of the next Write is guaran-
teed to be longer than 10 CCLK periods.
Status Read
The logic AND condition of the CS0, CS1and RS inputs
puts the device status on the Data bus.
• D7 High indicates Ready
• D7 Low indicates Busy
• D0 through D6 go unconditionally High
It is mandatory that the whole start-up sequence be started
and completed by one b yte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not com-
pleted all the wa y to the finish (point F in Figure 49 on page
61).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by MakeBits and
MakePROM, ensures that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, D7 represents the
RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
ADDRESS
BUS
DATA
BUS
ADDRESS
DECODE
LOGIC
CS0
...
RDY/BUSY
WS
PROGRAM
D0–7 CCLK
DOUT DIN
M2
M0 M1
N/C N/C N/C
RS
CS1
CONTROL
SIGNALS INIT
REPROGRAM
OPTIONAL
DAISY-CHAINED
FPGAs
VCC
DONE
8
X6696
4.7 kΩ
4.7 kΩ4.7 kΩ
4.7 kΩ
XC4000E/EX
ASYNCHRO-
NOUS
PERIPHERAL
PROGRAM
CCLK
DOUT
M2
M0 M1
INIT
DONE
XC4000E/EX
SLAVE
Figure 61: Asynchronous Peripheral Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-75
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the ne w b yte of data depends on the completion of previous b yte processing
and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-b uff ered parallel-to-serial conv erter is not yet ready to receive ne w data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram sho ws v ery relaxed requirements . Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics
Previous Byte D6 D7 D0 D1 D2
1TCA
2TDC
4
TWTRB
3TCD
6TBUSY
READY
BUSY
RS, CS0
WS, CS1
D7
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Write to LCA Read Status
X6097
74
Description Symbol Min Max Units
Write
Effective Write time
(CS0, WS=Low; RS, CS1=High) 1T
CA 100 ns
DIN setup time 2 TDC 60 ns
DIN hold time 3 TCD 0ns
RDY
RDY/BUSY delay after end of
Write or Read 4T
WTRB 60 ns
RDY/BUSY active after beginning
of Read 760ns
RDY/BUSY Low output (Note 4) 6 TBUSY 2 9 CCLK
periods
XC4000 Series Field Programmable Gate Arrays
4-76 June 1, 1996 (Version 1.02)
Express Mode (XC4000EX only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers. A CCLK frequency of 1 MHz
is equivalent to a 8 MHz serial rate, because eight bits of
configuration data are loaded per CCLK cycle. Express
mode does not support CRC error checking, but does sup-
port constant-field error checking.
In Express mode, an external signal drives the CCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subse-
quent data bytes are clocked in on each consecutive rising
CCLK edge.
Express mode is only supported by the XC4000EX and
XC5200 families. It may not be used, therefore, when an
XC4000EX or XC5200 device is daisy-chained with
devices from other Xilinx families.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float-
ing, since there is an internal pullup). Frame data is
accepted only when CS1 is High and the device’s configu-
ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-
nized as High, and remains Low until the device’s configu-
ration memory is full. DOUT is then pulled High to signal
the next de vice in the chain to accept the configuration data
on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deacti-
vate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the cur-
rent from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using a Make-
Bits option.
XC4000EX devices in Express mode are always synchro-
nized to DONE. The device becomes active after DONE
goes High. DONE is an open-dr ain output. With the DONE
pins tied together, therefore, the external DONE signal
stays lo w until all de vices are configured, then all de vices in
the daisy chain become active sim ultaneously. If the DONE
pin of a device is left unconnected, the device becomes
active as soon as that device has been configured.
XC5200 devices in the chain should be configured as syn-
chronized to DONE (MakeBits option CCLK_SYNC or
UCLK_SYNC), and their DONE pins wired together with
those of the XC4000EX devices.
Express mode must be specified as an option to the Make-
Bits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six config-
uration modes.
Express mode is selected by a <010> on the mode pins
(M2, M1, M0).
INIT
CCLK CCLK
XC4000EX/
XC5200
M0 M1 M2
CS1
D0-D7
DATA BUS
PROGRAM
INIT
CCLK
PROGRAM
INIT
DOUT
DONEDONE
DOUT
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
Optional
Daisy-Chained
XC4000EX/
XC5200
M0 M1
V
CC
V
CC
4.7KΩ
4.7KΩ
M2
CS1
D0-D7
PROGRAM
X6611
8
8
8
Figure 63: Express Mode Circuit Diagram
June 1, 1996 (Version 1.02) 4-77
Description Symbol Min Max Units
CCLK
INIT (High) setup time TIC -µs
D0 - D7 setup time TDC -ns
D0 - D7 hold time TCD 0ns
CCLK High time TCCH -ns
CCLK Low time TCCL -ns
CCLK Frequency FCC - MHz
Preliminary
X6710
BYTE
0
CCLK
FPGA Filled
1
2
3
INIT
TDC
TCD
TIC
D0-D7
DOUT
RDY/BUSY
CS1
BYTE
1BYTE
2BYTE
3
Internal INIT
Note: If not driven by the preceding DOUT, CS1
must
remain High until the device is fully configured.
Figure 64: Express Mode Programming Switching Characteristics
XC4000 Series Field Programmable Gate Arrays
4-78 June 1, 1996 (Version 1.02)
* XC4000EX only
Notes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
Table 24: Pin Functions During Configuration
CONFIGURATION MODE <M2:M1:M0>
SLAVE
SERIAL
<1:1:1>
MASTER
SERIAL
<0:0:0>
SYNCH.
PERIPH-
ERAL
<0:1:1>
ASYNCH.
PERIPH-
ERAL
<1:0:1>
MASTER
PARALLEL
DOWN
<1:1:0>
MASTER
PARALLEL UP
<1:0:0> EXPRESS
<0:1:0> USER
OPERATION
M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) M2(LOW) (I) (I)
M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) (O)
M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) M0(HIGH) (I) (I)
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT INIT INIT INIT INIT INIT INIT I/O
DONE DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I)
RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/O
RS (I) I/O
CS0 (I) I/O
DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O
DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/O
DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/O
DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/O
DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/O
DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/O
DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O
TDI TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS TMS-I/O
TDO TDO TDO TDO TDO TDO TDO TDO-(O)
WS (I) A0 A0 I/O
A1 A1 PGCK4-GCK6-I/O
CS1 A2 A2 I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 SGCK1-GCK7-I/O
A16 A16 PGCK1-GCK8-I/O
A17 A17 I/O
A18* A18* I/O
A19* A19* I/O
A20* A20* I/O
A21* A21* I/O
ALL OTHERS
June 1, 1996 (Version 1.02) 4-79
Configuration Switching Characteristics
Master Modes
Slave and Peripheral Modes
VALID
PROGRAM
INIT
Vcc
PI
T
POR
T
ICCK
TCCLK
T
CCLK OUTPUT or INPUT
M0, M1, M2 DONE RESPONSE
<300 ns
<300 ns
>300 ns
RE-PROGRAM
X1532 (Required)
I/O
Description Symbol Min Max Units
Power-On Reset M0 = High TPOR 10 40 ms
M0 = Low TPOR 40 130 ms
Program Latency TPI 30 200 µs per
CLB column
CCLK (output) Delay TICCK 40 250 µs
CCLK (output) Period, slow TCCLK 640 2000 ns
CCLK (output) Period, fast TCCLK 80 250 ns
Description Symbol Min Max Units
Power-On Reset TPOR 10 33 ms
Program Latency TPI 30 200 µs per
CLB column
CCLK (input) Delay (required) TICCK 4µs
CCLK (input) Period (required) TCCLK 100 ns
XC4000 Series Field Programmable Gate Arrays
4-80 June 1, 1996 (Version 1.02)
XC4000E Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1
XC4000E Operating Conditions
Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
Note 2: Typical value only. Not tested or characterized.
XC4000E DC Characteristics Over Operating Conditions
Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with a MakeBits Tie option.
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Symbol Description Min Max Units
VCC Supply voltage relative to GND, TJ = -0 °C to +85°C Commercial 4.75 5.25 V
Supply voltage relative to GND, TJ = -40°C to +100°C Industrial 4.5 5.5 V
Supply voltage relative to GND, TC = -55°C to +125°C Military 4.5 5.5 V
VIH High-level input voltage TTL inputs 2.0 VCC V
CMOS inputs 70% 100% VCC
VIL Low-level input voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% VCC
TIN Input signal transition time (Note 2) 250 ns
Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -4.0mA, VCC min TTL outputs 2.4 V
High-level output voltage @ IOH = -1.0mA, VCC min CMOS outputs VCC-0.5 V
VOL Low-level output voltage @ IOL = 12.0mA, VCC min
(Note 1) TTL outputs 0.4 V
CMOS outputs 0.4 V
ICCO Quiescent FPGA supply current (Note 2) TTL input levels 10 mA
CMOS input levels 1 mA
ILInput or output leakage current -10 +10 µA
CIN Input capacitance (sample tested) PQFP and MQFP
packages 10 pF
Other packages 16 pF
IRIN Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 0.25 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA
June 1, 1996 (Version 1.02) 4-81
XC4000E Absolute Maximum Ratings
Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage relative to GND (Note 1) -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output (Note 1) -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction temperature Ceramic packages +150 °C
Plastic packages +125 °C
Speed Grade -4 -3 -2 Units
Description Symbol Device Max Max Max
From pad through
Primary buffer,
to any clock K
TPG XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
7.0
7.0
7.5
8.0
11.0
11.5
12.0
12.5
4.7
4.7
5.3
6.1
6.3
6.8
7.0
7.2
4.0
4.0
4.5
5.2
5.4
5.8
6.2
6.3
ns
ns
ns
ns
ns
ns
ns
ns
From pad through
Secondary buffer,
to any clock K
TSG XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
7.5
7.5
8.0
8.5
11.5
12.0
12.5
13.0
5.2
5.2
5.8
6.6
6.8
7.3
7.5
7.7
4.4
4.4
4.9
5.6
5.8
6.2
6.6
6.8
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY ADVANCE
XC4000 Series Field Programmable Gate Arrays
4-82 June 1, 1996 (Version 1.02)
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
Note 2: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (TOPF or TOPS), as listed under “IOB Switching Characteristic Guidelines.”
Speed Grade -4 -3 -2 Units
Description Symbol Device Max Max Max
Full length, both pull-ups,
inputs from IOB I-pins TWAF XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.2
9.5
12.0
12.5
15.0
16.0
17.0
18.0
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
4.3
5.1
6.2
7.0
8.1
9.9
12.5
15.2
ns
ns
ns
ns
ns
ns
ns
ns
Full length, both pull-ups,
inputs from internal logic TWAFL XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
6.0
6.8
7.9
8.8
9.7
11.7
14.0
17.0
ns
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up,
inputs from IOB I-pins TWAO XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
10.5
10.5
13.5
14.0
16.0
17.0
18.0
19.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
5.1
6.0
6.8
7.9
8.8
10.8
13.5
15.8
ns
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up,
inputs from internal logic TWAOL XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
6.8
7.7
8.5
9.4
10.2
11.9
14.3
16.7
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-83
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
Note 2: This v alue includes a minim um load. The value reported by LCA2XNF -S is increased to allow for potentially hea vy loading,
therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination.
Speed Grade -4 -3 -2 Units
Description Symbol Device Max Max Max
TBUF driving a Horizontal Longline
(LL):
I going High or Low to LL going High or
Low, while T is Low.
Buffer is constantly active.
(Note1)
TIO1 XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
4.2
5.0
5.9
6.3
6.4
7.2
8.2
9.1
3.4
4.0
4.7
5.0
5.1
5.7
6.6
7.3
ns
ns
ns
ns
ns
ns
ns
ns
I going Low to LL going from resistive
pull-up High to active Low.
TBUF configured as open-drain.
(Note1)
TIO2 XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
6.0
7.8
8.1
10.5
11.0
12.0
12.0
4.2
5.3
6.4
6.8
6.9
7.7
8.7
9.6
3.6
4.5
5.4
5.8
5.9
6.5
7.4
8.2
ns
ns
ns
ns
ns
ns
ns
ns
T going Low to LL going from resistive
pull-up or floating High to active Low.
TBUF configured as open-drain or active
buffer with I = Low.
(Note1)
TON XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
7.0
7.5
8.0
8.5
8.7
11.0
11.0
4.6
6.0
6.7
7.1
7.3
7.5
8.4
8.4
3.9
5.4
5.7
6.0
6.2
6.4
7.1
7.1
ns
ns
ns
ns
ns
ns
ns
ns
T going High to TBUF going inactive,
not driving LL TOFF All devices 1.8 1.5 1.3 ns
T going High to LL going from Low to
High, pulled up by a single resistor.
(Note 2)
TPUS XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
20.0
23.0
25.0
27.0
29.0
32.0
35.0
42.0
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
11.9
13.6
15.3
17.0
18.7
22.1
27.6
33.2
ns
ns
ns
ns
ns
ns
ns
ns
T going High to LL going from Low to
High, pulled up by two resistors.
(Note1)
TPUF XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.0
10.0
11.5
12.5
13.5
15.0
16.0
18.0
7.0
8.0
9.0
10.0
11.0
13.0
14.8
16.5
6.0
6.8
7.7
8.5
9.4
11.0
12.6
14.0
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY ADVANCE
XC4000 Series Field Programmable Gate Arrays
4-84 June 1, 1996 (Version 1.02)
XC4000E CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via SR through H’ to X/Y outputs
C inputs via H’ to X/Y outputs
C inputs via DIN through H’ to X/Y outputs
TILO
TIHO
THH0O
THH1O
THH2O
2.7
4.7
4.1
3.7
4.5
2.0
4.3
3.3
3.6
3.6
1.6
2.7
2.4
2.2
2.6
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to
X/Y outputs
CIN to COUT, bypass function generators
TOPCY
TASCY
TINCY
TSUM
TBYP
3.2
5.5
1.7
3.8
1.0
2.6
4.4
1.7
3.3
0.7
2.1
3.7
1.4
2.6
0.6
Sequential Delays
Clock K to outputs Q TCKO 3.7 2.8 2.8
Setup Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H0 through H’
C inputs via H1 through H’
C inputs via H2 through H’
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F’/G’
CIN input via F’/G’ and H’
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
4.0
6.1
4.5
5.0
4.8
3.0
4.0
4.2
3.0
4.6
3.6
4.1
3.8
2.4
3.0
4.0
2.4
3.9
3.5
3.3
3.7
2.0
2.6
4.0
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-85
XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Notes: 1. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
2. Export Control Max. flip-flop toggle rate.
Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H0 through H’
C inputs via H1 through H’
C inputs via H2 through H’
C inputs via DIN
C inputs via EC
C inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clock
Clock High time
Clock Low time TCH
TCL
4.5
4.5 4.0
4.0 4.0
4.0
Set/Reset Direct
Width (High)
Delay from C inputs via S/R,
going High to Q
TRPW
TRIO
5.5 6.5 4.0 4.0 4.0 4.0
Master Set/Reset (Note 1)
Width (High or Low)
Delay from Global Set/Reset net to Q
Global Set/Reset inactive to first
active clock K edge
TMRW
TMRQ
TMRK
13.0 23.0 11.5 18.7 11.5 17.4
Toggle Frequency2 (MHz) FTOG 111 125 125
PRELIMINARY ADVANCE
XC4000 Series Field Programmable Gate Arrays
4-86 June 1, 1996 (Version 1.02)
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time
(clock K period)
Clock K pulse width
(active edge)
Address setup time
before clock K
Address hold time
after clock K
DIN setup time
before clock K
DIN hold time
after clock K
WE setup time
before clock K
WE hold time
after clock K
Data valid
after clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
TWCS
TWCTS
TWPS
TWPTS
TASS
TASTS
TAHS
TAHTS
TDSS
TDSTS
TDHS
TDHTS
TWSS
TWSTS
TWHS
TWHTS
TWOS
TWOTS
15.0
15.0
7.5
7.5
2.8
2.8
0
0
3.5
2.5
0
0
2.2
2.2
0
0
1 ms
1 ms
10.3
11.6
14.4
14.4
7.2
7.2
2.4
2.4
0
0
3.2
1.9
0
0
2.0
2.0
0
0
1 ms
1 ms
8.8
10.3
11.6
11.6
5.8
5.8
2.0
2.0
0
0
2.7
1.7
0
0
1.6
1.6
0
0
1 ms
1 ms
6.3
7.4
PRELIMINARY ADVANCE
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
TASS TAHS
TWSS
TWPS
TWHS
TWOS
TILO
TILO
June 1, 1996 (Version 1.02) 4-87
XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic
Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note: Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing.
Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time
(clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
15.0
7.5
2.8
0
2.2
0
2.2
0.3
1 ms
10.0
14.4
7.2
2.5
0
1.9
0
2.0
0
1 ms
7.8
11.6
5.8
2.1
0
1.6
0
1.6
0
1 ms
6.2
PRELIMINARY ADVANCE
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
TASDS TAHDS
TWSDS
TWPDS
TWHDS
X6474
DATA OUT OLD NEW
T
WODS
T
ILO
T
ILO
XC4000 Series Field Programmable Gate Arrays
4-88 June 1, 1996 (Version 1.02)
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time
Write Enable pulse width
(High)
Address setup time
before WE
Address hold time
after end of WE
DIN setup time
before end of WE
DIN hold time
after end of WE
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
TWC
TWCT
TWP
TWPT
TAS
TAST
TAH
TAHT
TDS
TDST
TDH
TDHT
8.0
8.0
4.0
4.0
2.0
2.0
2.5
2.0
4.0
5.0
2.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
2.2
2.2
2.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
0.8
0.8
2.0
2.0
Read Operation
Address read cycle time
Data valid after address
change (no Write Enable)
16x2
32x1
16x2
32x1
TRC
TRCT
TILO
TIHO
4.5
6.5 2.7
4.7
3.1
5.5 2.0
4.3
2.6
3.8 1.6
2.7
Read Operation, Clocking
Data into Flip-Flop
Address setup time
before clock K 16x2
32x1 TICK
TIHCK
4.0
6.1 3.0
4.6 2.4
3.9
Read During Write
Data valid after WE goes
active (DIN stable
before WE)
Data valid after DIN
(DIN changes during WE)
16x2
32x1
16x2
32x1
TWO
TWOT
TDO
TDOT
10.0
12.0
9.0
11.0
6.0
7.3
6.6
7.6
4.9
5.6
5.8
6.2
Read During Write, Clock-
ing Data into Flip-Flop
WE setup time
before clock K
Data setup time
before clock K
16x2
32x1
16x2
32x1
TWCK
TWCKT
TDCK
TDCKT
8.0
9.6
7.0
8.0
6.0
6.8
5.2
6.2
5.1
5.8
4.4
5.3
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-89
XC4000E CLB Level-Sensitive RAM Timing Characteristics
WC
T
ILO
T
CKO
T
DO
T
DH
T
WO
T
CKO
T
WCK
T
DCK
T
ICK
TCH
T
WO
T
WP
T
VALID
VALID
(OLD)
VALID
(OLD)
VALID
(PREVIOUS)
VALID
(NEW)
VALID
(NEW)
VALID
ADDRESS
X,Y OUTPUTS
CLOCK
XQ, YQ OUTPUTS
WRITE ENABLE
X, Y OUTPUTS
X, Y OUTPUTS
XQ, YQ OUTPUTS
WRITE ENABLE
DATA IN
CLOCK
DATA IN
(stable during WE)
DATA IN
(changing during WE)
READ WITHOUT WRITE
READ, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE
WRITE ENABLE
DATA IN
WRITE AS
TWP
T
DS
TDH
T
REQUIRED
AH
T
WP
T
OLD NEW
VALID VALID
X2640
XC4000 Series Field Programmable Gate Arrays
4-90 June 1, 1996 (Version 1.02)
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL Inputs)
All values listed belo w are tested directly, and guaranteed over the operating conditions. The same par ameters can also be
derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method.
When there is a discrepancy between the two methods , the values listed below should be used, and the deriv ed values m ust
be ignored. All values are expressed in units of nanoseconds.
Speed Grade -4 -3 -2
Description Symbol Device
Global Clock to Output
(fast) using OFF TICKOF
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.5
14.0
14.5
15.0
16.0
16.5
17.0
17.0
10.2
10.7
10.7
10.8
10.9
11.0
11.0
12.6
8.7
9.1
9.1
9.2
9.3
9.4
9.4
10.7
Global Clock to Output
(slew-limited) using OFF TICKO
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
16.5
18.0
18.5
19.0
20.0
20.5
21.0
21.0
14.0
14.7
14.7
14.8
14.9
15.0
15.1
15.3
11.5
12.0
12.0
12.1
12.2
12.8
12.8
13.0
Input Setup Time, using IFF
(no delay) TPSUF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
2.5
2.0
1.9
1.4
1.0
0.5
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
Input Hold Time, using IFF
(no delay) TPHF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
4.6
5.0
6.0
6.0
7.0
7.5
8.0
4.0
4.5
4.7
5.1
5.5
6.5
6.7
7.0
4.0
4.5
4.7
5.1
5.5
5.5
5.7
5.9
Input Setup Time, using IFF
(with delay) TPSU
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
8.5
8.5
8.5
8.5
8.5
8.5
9.5
9.5
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.6
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.5
Input Hold Time, using IFF
(with delay) TPH
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFF = Output Flip-Flop IFF = Input Flip-Flop or Latch PRELIMINARY ADVANCE
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
TPG
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
June 1, 1996 (Version 1.02) 4-91
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, CMOS Inputs)
All values listed belo w are tested directly, and guaranteed over the operating conditions. The same par ameters can also be
derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method.
When there is a discrepancy between the two methods , the values listed below should be used, and the deriv ed values m ust
be ignored. All values are expressed in units of nanoseconds.
Speed Grade -4 -3 -2
Description Symbol Device
Global Clock to Output
(fast) using OFF TCICKOF
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Global Clock to Output
(slew-limited) using OFF TCICKO
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Input Setup Time, using IFF
(no delay) TCPSUF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Input Hold Time, using IFF
(no delay) TCPHF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Input Setup Time, using IFF
(with delay) TCPSU
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
Input Hold Time, using IFF
(with delay) TCPH
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
OFF = Output Flip-Flop IFF = Input Flip-Flop or Latch PRELIMINARY ADVANCE
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
TPG
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
XC4000 Series Field Programmable Gate Arrays
4-92 June 1, 1996 (Version 1.02)
XC4000E IOB Input Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Speed Grade -4 -3 -2
Description Symbol Device Min Max Min Max Min Max
Propagation Delays
(TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch,
no delay
with delay
TPID
TPLI
TPDLI
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.0
4.8
10.4
10.8
10.8
10.8
11.0
11.4
13.8
13.8
2.5
3.6
9.3
9.6
10.2
10.6
10.8
11.2
12.4
13.7
2.0
3.6
7.0
7.3
7.8
8.1
8.2
8.5
9.5
9.5
(CMOS Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch,
no delay
with delay
TPIDC
TPLIC
TPDLIC
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
8.8
16.5
16.5
16.8
17.3
17.5
18.0
20.8
20.8
4.1
6.8
12.4
13.2
13.4
13.8
14.0
14.4
15.6
15.6
3.7
6.2
11.0
11.9
12.1
12.4
12.6
13.0
14.0
14.0
(TTL or CMOS)
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2
(latch enable, active Low)
TIKRI
TIKLI
All devices
All devices
5.6
6.2
2.8
4.0
2.8
3.9
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
Clock Enable (EC) to Clock (IK),
no delay
with delay
TIKPI
TIKPID
TIKEC
TIKECD
All devices
All devices
All devices
All devices
0
0
1.5
0
0
0
1.5
0
0
0
0.9
0
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-93
XC4000E IOB Input Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Speed Grade -4 -3 -2
Description Symbol Device Min Max Min Max Min Max
Setup Times (TTL Inputs)
Pad to Clock (IK), no delay
with delay TPICK
TPICKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
10.9
10.9
10.9
11.1
11.3
11.8
14.0
14.0
2.6
8.2
8.7
9.2
9.6
9.8
10.2
11.4
11.4
1.7
5.5
5.5
6.6
6.9
7.0
7.3
8.2
8.2
(CMOS Inputs)
Pad to Clock (IK), no delay
with delay TPICKC
TPICKDC
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
6.0
12.0
12.0
12.3
12.8
13.0
13.5
16.0
16.0
3.3
8.8
9.7
9.9
10.3
10.5
10.9
12.1
12.1
2.4
6.2
6.2
7.3
7.6
7.7
8.0
8.9
8.9
(TTL or CMOS)
Clock Enable (EC) to Clock
(IK), no delay
with delay TECIK
TECIKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.5
10.4
10.4
10.4
10.4
10.7
11.1
14.0
14.0
2.5
8.1
8.5
9.1
9.5
9.7
10.1
11.3
11.3
2.0
5.6
5.6
6.9
7.2
7.3
7.6
8.5
8.5
Global Set/Reset (Note 3)
Delay from GSR net
through Q to I1, I2
GSR width
GSR inactive to first active
Clock (IK) edge
TRRI
TMRW
TMRI
13.0
12.0
11.5
7.8
11.5
6.8
PRELIMINARY ADVANCE
XC4000 Series Field Programmable Gate Arrays
4-94 June 1, 1996 (Version 1.02)
XC4000E IOB Output Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are appro ximately tw o times longer than fast output rise/fall times . For the effect of capacitiv e loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Propagation Delays
(TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
TTSONF
TTSONS
7.5
11.5
8.0
12.0
5.0
9.7
13.7
6.5
9.5
5.5
8.5
4.2
8.1
11.1
4.5
7.0
4.8
7.3
3.8
7.3
9.8
Propagation Delays
(CMOS Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
TOKPOFC
TOKPOSC
TOPFC
TOPSC
TTSHZC
TTSONFC
TTSONSC
9.5
13.5
10.0
14.0
5.2
9.1
13.1
7.8
11.6
9.7
13.4
4.3
7.6
11.4
7.0
10.4
8.7
12.1
3.9
6.8
10.2
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-95
XC4000E IOB Output Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are appro ximately tw o times longer than fast output rise/fall times . For the effect of capacitiv e loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Setup and Hold
Output (O) to clock (OK)
setup time
Output (O) to clock (OK)
hold time
Clock Enable (EC) to
clock (OK) setup
Clock Enable (EC) to
clock (OK) hold
TOOK
TOKO
TECOK
TOKEC
5.0
0
4.8
1.2
4.6
0
3.5
1.2
3.8
0
2.5
0.5
Clock
Clock High
Clock Low TCH
TCL
4.5
4.5 4.0
4.0 4.0
4.0
Global Set/Reset (Note 3)
Delay from GSR net to Pad
GSR width
GSR inactive to first active
clock (OK) edge
TRPO
TMRW
TMRO
13.0 15.0 11.5 11.8 11.5 8.7
PRELIMINARY ADVANCE
XC4000 Series Field Programmable Gate Arrays
4-96 June 1, 1996 (Version 1.02)
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All de vices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The follo wing guidelines reflect worst-case v alues ov er the recommended operating conditions . They are e xpressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are appro ximately tw o times longer than fast output rise/fall times . For the effect of capacitiv e loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
XC4000L Switching Characteristics
XC4000L timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.
XC4000EX Switching Characteristics
XC4000EX timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.
XC4000XL Switching Characteristics
XC4000XL timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.
Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Setup and Hold
Input (TDI) to clock (TCK)
setup time
Input (TDI) to clock (TCK)
hold time
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time
TTDITCK
TTCKTDI
TTMSTCK
TTCKTMS
Propagation Delay
Clock (TCK) to Pad (TDO) TTCKPO
Clock
Clock (TCK) High
Clock (TCK) Low TTCKH
TTCKL
Power-On Reset
JTAG operation after valid
Vcc TRJTAG
PRELIMINARY ADVANCE
June 1, 1996 (Version 1.02) 4-97
Device-Specific Pinout Tables
Pin Locations for XC4003E Devices
4/2/96
Additional No Connect (N.C.) Connections on PG120 P ac kage
2/28/96
XC4003E
Pad Name PC
84 PQ
100 VQ
100 PG
120 Bndry
Scan
VCC P2 P92 P89 G3 -
I/O (A8) P3 P93 P90 G1 32
I/O (A9) P4 P94 P91 F1 35
I/O - P95 P92 E1 38
I/O - P96 P93 F2 41
I/O (A10) P5 P97 P94 F3 44
I/O (A11) P6 P98 P95 D1 47
I/O (A12) P7 P99 P96 C1 50
I/O (A13) P8 P100 P97 D2 53
I/O (A14) P9 P1 P98 C2 56
I/O, SGCK1 (A15) P10 P2 P99 D3 59
VCC P11 P3 P100 C3 -
GND P12 P4 P1 C4 -
I/O, PGCK1 (A16) P13 P5 P2 B2 62
I/O (A17) P14 P6 P3 B3 65
I/O, TDI P15 P7 P4 C5 68
I/O, TCK P16 P8 P5 B4 71
I/O, TMS P17 P9 P6 B5 74
I/O P18 P10 P7 A4 77
I/O - - - C6 80
I/O - P11 P8 A5 83
I/O P19 P12 P9 B6 86
I/O P20 P13 P10 A6 89
GND P21 P14 P11 B7 -
VCC P22 P15 P12 C7 -
I/O P23 P16 P13 A7 92
I/O P24 P17 P14 A8 95
I/O - P18 P15 A9 98
I/O - - - B8 101
I/O P25 P19 P16 C8 104
I/O P26 P20 P17 A10 107
I/O P27 P21 P18 B9 110
I/O - P22 P19 A11 113
I/O P28 P23 P20 C9 116
I/O, SCGK2 P29 P24 P21 A12 119
O (M1) P30 P25 P22 B11 122
GND P31 P26 P23 C10 -
I (M0) P32 P27 P24 C11 125
VCC P33 P28 P25 D11 -
I (M2) P34 P29 P26 B12 126
I/O, PGCK2 P35 P30 P27 C12 127
I/O (HDC) P36 P31 P28 A13 130
I/O - P32 P29 D12 133
I/O (LDC) P37 P33 P30 C13 136
I/O P38 P34 P31 E12 139
I/O P39 P35 P32 D13 142
I/O - P36 P33 F11 145
I/O - P37 P34 E13 148
I/O P40 P38 P35 F12 151
I/O (INIT) P41 P39 P36 F13 154
VCC P42 P40 P37 G12 -
GND P43 P41 P38 G11 -
I/O P44 P42 P39 G13 157
I/O P45 P43 P40 H13 160
I/O - P44 P41 J13 163
I/O - P45 P42 H12 166
I/O P46 P46 P43 H11 169
I/O P47 P47 P44 K13 172
I/O P48 P48 P45 J12 175
I/O P49 P49 P46 L13 178
I/O P50 P50 P47 M13 181
I/O, SGCK3 P51 P51 P48 L12 184
GND P52 P52 P49 K11 -
DONE P53 P53 P50 L11 -
VCC P54 P54 P51 L10 -
PROGRAM P55 P55 P52 M12 -
I/O (D7) P56 P56 P53 M11 187
I/O, PGCK3 P57 P57 P54 N13 190
I/O (D6) P58 P58 P55 M10 193
I/O - P59 P56 N11 196
I/O (D5) P59 P60 P57 M9 199
I/O (CS0) P60 P61 P58 N10 202
I/O - P62 P59 L8 205
I/O - P63 P60 N9 208
I/O (D4) P61 P64 P61 M8 211
I/O P62 P65 P62 N8 214
VCC P63 P66 P63 M7 -
GND P64 P67 P64 L7 -
I/O (D3) P65 P68 P65 N7 217
I/O (RS) P66 P69 P66 N6 220
I/O - P70 P67 N5 223
I/O - - - M6 226
I/O (D2) P67 P71 P68 L6 229
I/O P68 P72 P69 N4 232
I/O (D1) P69 P73 P70 M5 235
I/O (RCLK,
RDY/BUSY) P70 P74 P71 N3 238
I/O (D0, DIN) P71 P75 P72 N2 241
I/O, SGCK4
(DOUT) P72 P76 P73 M3 244
CCLK P73 P77 P74 L4 -
VCC P74 P78 P75 L3 -
O, TDO P75 P79 P76 M2 0
GND P76 P80 P77 K3 -
I/O (A0, WS) P77 P81 P78 L2 2
I/O, PGCK4 (A1) P78 P82 P79 N1 5
I/O (CS1, A2) P79 P83 P80 K2 8
I/O (A3) P80 P84 P81 L1 11
I/O (A4) P81 P85 P82 J2 14
I/O (A5) P82 P86 P83 K1 17
I/O - P87 P84 H3 20
I/O - P88 P85 J1 23
I/O (A6) P83 P89 P86 H2 26
I/O (A7) P84 P90 P87 H1 29
GND P1 P91 P88 G2 -
PG120 PG120 PG120 PG120
A1 B13 J11 M4
A2 E2 K12 N12
A3 E3 L5
B1 E11 L9
B10 J3 M1
XC4003E
Pad Name PC
84 PQ
100 VQ
100 PG
120 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-98 June 1, 1996 (Version 1.02)
Pin Locations for XC4005E/L Devices
XC4005
E/L
Pad Name
PC
84 PQ
100 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
VCC P2 P92 P128 H3 P142 P183 -
I/O (A8) P3 P93 P129 H1 P143 P184 44
I/O (A9) P4 P94 P130 G1 P144 P185 47
I/O - P95 P131 G2 P145 P186 50
I/O - P96 P132 G3 P146 P187 53
I/O (A10) P5 P97 P133 F1 P147 P190 56
I/O (A11) P6 P98 P134 F2 P148 P191 59
I/O - - P135 E1 P149 P192 62
I/O - - P136 E2 P150 P193 65
GND - - P137 F3 P151 P194 -
I/O (A12) P7 P99 P138 E3 P154 P199 68
I/O (A13) P8 P100 P139 C1 P155 P200 71
I/O - - P140 C2 P156 P201 74
I/O - - P141 D3 P157 P202 77
I/O (A14) P9 P1 P142 B1 P158 P203 80
I/O,
SGCK1
(A15)
P10 P2 P143 B2 P159 P204 83
VCC P11 P3 P144 C3 P160 P205 -
GND P12 P4 P1 C4 P1 P2 -
I/O,
PGCK1
(A16)
P13 P5 P2 B3 P2 P4 86
I/O (A17) P14 P6 P3 A1 P3 P5 89
I/O - - P4 A2 P4 P6 92
I/O - - P5 C5 P5 P7 95
I/O, TDI P15 P7 P6 B4 P6 P8 98
I/O, TCK P16 P8 P7 A3 P7 P9 101
GND - - P8 C6 P10 P14 -
I/O - - P9 B5 P11 P15 104
I/O - - P10 B6 P12 P16 107
I/O, TMS P17 P9 P11 A5 P13 P17 110
I/O P18 P10 P12 C7 P14 P18 113
I/O - - P13 B7 P15 P21 116
I/O - P11 P14 A6 P16 P22 119
I/O P19 P12 P15 A7 P17 P23 122
I/O P20 P13 P16 A8 P18 P24 125
GND P21 P14 P17 C8 P19 P25 -
VCC P22 P15 P18 B8 P20 P26 -
I/O P23 P16 P19 C9 P21 P27 128
I/O P24 P17 P20 B9 P22 P28 131
I/O - P18 P21 A9 P23 P29 134
I/O - - P22 B10 P24 P30 137
I/O P25 P19 P23 C10 P25 P33 140
I/O P26 P20 P24 A10 P26 P34 143
I/O - - P25 A11 P27 P35 146
I/O - - P26 B11 P28 P36 149
GND - - P27 C11 P29 P37 -
I/O P27 P21 P28 B12 P32 P42 152
I/O - P22 P29 A13 P33 P43 155
I/O - - P30 A14 P34 P44 158
I/O - - P31 C12 P35 P45 161
I/O P28 P23 P32 B13 P36 P46 164
I/O,
SCGK2 P29 P24 P33 B14 P37 P47 167
O (M1) P30 P25 P34 A15 P38 P48 170
GND P31 P26 P35 C13 P39 P49 -
I (M0) P32 P27 P36 A16 P40 P50 173
VCC P33 P28 P37 C14 P41 P55 -
I (M2) P34 P29 P38 B15 P42 P56 174
I/O,
PGCK2 P35 P30 P39 B16 P43 P57 175
I/O (HDC) P36 P31 P40 D14 P44 P58 178
I/O - - P41 C15 P45 P59 181
I/O - - P42 D15 P46 P60 184
I/O - P32 P43 E14 P47 P61 187
I/O (LDC) P37 P33 P44 C16 P48 P62 190
GND - - P45 F14 P51 P67 -
I/O - - P46 F15 P52 P68 193
I/O - - P47 E16 P53 P69 196
I/O P38 P34 P48 F16 P54 P70 199
I/O P39 P35 P49 G14 P55 P71 202
I/O - P36 P50 G15 P56 P74 205
I/O - P37 P51 G16 P57 P75 208
I/O P40 P38 P52 H16 P58 P76 211
I/O (INIT) P41 P39 P53 H15 P59 P77 214
VCC P42 P40 P54 H14 P60 P78 -
GND P43 P41 P55 J14 P61 P79 -
I/O P44 P42 P56 J15 P62 P80 217
I/O P45 P43 P57 J16 P63 P81 220
I/O - P44 P58 K16 P64 P82 223
I/O - P45 P59 K15 P65 P83 226
I/O P46 P46 P60 K14 P66 P86 229
I/O P47 P47 P61 L16 P67 P87 232
I/O - - P62 M16 P68 P88 235
I/O - - P63 L15 P69 P89 238
GND - - P64 L14 P70 P90 -
I/O P48 P48 P65 P16 P73 P95 241
I/O P49 P49 P66 M14 P74 P96 244
I/O - - P67 N15 P75 P97 247
I/O - - P68 P15 P76 P98 250
I/O P50 P50 P69 N14 P77 P99 253
I/O,
SGCK3 P51 P51 P70 R16 P78 P100 256
GND P52 P52 P71 P14 P79 P101 -
XC4005
E/L
Pad Name
PC
84 PQ
100 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
June 1, 1996 (Version 1.02) 4-99
4/2/96
Additional No Connect (N.C.) Connections on TQ144,
PG156, PQ160 & PQ208 Packages
3/12/96
DONE P53 P53 P72 R15 P80 P103 -
VCC P54 P54 P73 P13 P81 P106 -
PRO-
GRAM P55 P55 P74 R14 P82 P108 -
I/O (D7) P56 P56 P75 T16 P83 P109 259
I/O,
PGCK3 P57 P57 P76 T15 P84 P110 262
I/O - - P77 R13 P85 P111 265
I/O - - P78 P12 P86 P112 268
I/O (D6) P58 P58 P79 T14 P87 P113 271
I/O - P59 P80 T13 P88 P114 274
GND - - P81 P11 P91 P119 -
I/O - - P82 R11 P92 P120 277
I/O - - P83 T11 P93 P121 280
I/O (D5) P59 P60 P84 T10 P94 P122 283
I/O (CS0) P60 P61 P85 P10 P95 P123 286
I/O - P62 P86 R10 P96 P126 289
I/O - P63 P87 T9 P97 P127 292
I/O (D4) P61 P64 P88 R9 P98 P128 295
I/O P62 P65 P89 P9 P99 P129 298
VCC P63 P66 P90 R8 P100 P130 -
GND P64 P67 P91 P8 P101 P131 -
I/O (D3) P65 P68 P92 T8 P102 P132 301
I/O (RS) P66 P69 P93 T7 P103 P133 304
I/O - P70 P94 T6 P104 P134 307
I/O - - P95 R7 P105 P135 310
I/O (D2) P67 P71 P96 P7 P106 P138 313
I/O P68 P72 P97 T5 P107 P139 316
I/O - - P98 R6 P108 P140 319
I/O - - P99 T4 P109 P141 322
GND - - P100 P6 P110 P142 -
I/O (D1) P69 P73 P101 T3 P113 P147 325
I/O (RCLK,
RDY/
BUSY)
P70 P74 P102 P5 P114 P148 328
I/O - - P103 R4 P115 P149 331
I/O - - P104 R3 P116 P150 334
I/O
(D0, DIN) P71 P75 P105 P4 P117 P151 337
I/O,
SGCK4
(DOUT)
P72 P76 P106 T2 P118 P152 340
CCLK P73 P77 P107 R2 P119 P153 -
VCC P74 P78 P108 P3 P120 P154 -
O, TDO P75 P79 P109 T1 P121 P159 0
GND P76 P80 P110 N3 P122 P160 -
I/O
(A0, WS) P77 P81 P111 R1 P123 P161 2
XC4005
E/L
Pad Name
PC
84 PQ
100 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
I/O,
PGCK4
(A1)
P78 P82 P112 P2 P124 P162 5
I/O - - P113 N2 P125 P163 8
I/O - - P114 M3 P126 P164 11
I/O
(CS1, A2) P79 P83 P115 P1 P127 P165 14
I/O (A3) P80 P84 P116 N1 P128 P166 17
GND - - P118 L3 P131 P171 -
I/O - - P119 L2 P132 P172 20
I/O - - P120 L1 P133 P173 23
I/O (A4) P81 P85 P121 K3 P134 P174 26
I/O (A5) P82 P86 P122 K2 P135 P175 29
I/O - P87 P123 K1 P137 P178 32
I/O - P88 P124 J1 P138 P179 35
I/O (A6) P83 P89 P125 J2 P139 P180 38
I/O (A7) P84 P90 P126 J3 P140 P181 41
GND P1 P91 P127 H2 P141 P182 -
TQ144 PG156 PQ160 PQ208
P117 A4 P8 P1
A12 P9 P3
D1 P30 P10-P13
D2 P31 P19-P20
D16 P49 P31-P32
E15 P50 P38-P41
M1 P71 P51-P54
M2 P72 P63-P66
M15 P89 P72-P73
N16 P90 P84-P85
R5 P111 P91-P94
R12 P112 P102
T12 P129 P104-P105
P130 P107
P136 P115-P118
P152 P124-P125
P153 P136-P137
P143-P146
P155-P158
P167-P170
P176-P177
P188-P189
P195-P198
P206-P208
XC4005
E/L
Pad Name
PC
84 PQ
100 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-100 June 1, 1996 (Version 1.02)
Pin Locations for XC4006E Devices
XC4006E
Pad Name PC
84 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
VCC P2 P128 H3 P142 P183 -
I/O (A8) P3 P129 H1 P143 P184 50
I/O (A9) P4 P130 G1 P144 P185 53
I/O - P131 G2 P145 P186 56
I/O - P132 G3 P146 P187 59
I/O (A10) P5 P133 F1 P147 P190 62
I/O (A11) P6 P134 F2 P148 P191 65
I/O - P135 E1 P149 P192 68
I/O - P136 E2 P150 P193 71
GND - P137 F3 P151 P194 -
I/O - - D1 P152 P197 74
I/O - - D2 P153 P198 77
I/O (A12) P7 P138 E3 P154 P199 80
I/O (A13) P8 P139 C1 P155 P200 83
I/O - P140 C2 P156 P201 86
I/O - P141 D3 P157 P202 89
I/O (A14) P9 P142 B1 P158 P203 92
I/O, SGCK1 (A15) P10 P143 B2 P159 P204 95
VCC P11 P144 C3 P160 P205 -
GND P12 P1 C4 P1 P2 -
I/O, PGCK1 (A16) P13 P2 B3 P2 P4 98
I/O (A17) P14 P3 A1 P3 P5 101
I/O - P4A2P4P6 104
I/O - P5 C5 P5 P7 107
I/O, TDI P15 P6 B4 P6 P8 110
I/O, TCK P16 P7 A3 P7 P9 113
I/O - - A4 P8 P10 116
I/O - - - P9 P11 119
GND - P8 C6 P10 P14 -
I/O - P9 B5 P11 P15 122
I/O - P10 B6 P12 P16 125
I/O, TMS P17 P11 A5 P13 P17 128
I/O P18 P12 C7 P14 P18 131
I/O - P13 B7 P15 P21 134
I/O - P14 A6 P16 P22 137
I/O P19 P15 A7 P17 P23 140
I/O P20 P16 A8 P18 P24 143
GND P21 P17 C8 P19 P25 -
VCC P22 P18 B8 P20 P26 -
I/O P23 P19 C9 P21 P27 146
I/O P24 P20 B9 P22 P28 149
I/O - P21 A9 P23 P29 152
I/O - P22 B10 P24 P30 155
I/O P25 P23 C10 P25 P33 158
I/O P26 P24 A10 P26 P34 161
I/O - P25 A11 P27 P35 164
I/O - P26 B11 P28 P36 167
GND - P27 C11 P29 P37 -
I/O - - A12 P30 P40 170
I/O - - - P31 P41 173
I/O P27 P28 B12 P32 P42 176
I/O - P29 A13 P33 P43 179
I/O - P30 A14 P34 P44 182
I/O - P31 C12 P35 P45 185
I/O P28 P32 B13 P36 P46 188
I/O, SCGK2 P29 P33 B14 P37 P47 191
O (M1) P30 P34 A15 P38 P48 194
GND P31 P35 C13 P39 P49 -
I (M0) P32 P36 A16 P40 P50 197
VCC P33 P37 C14 P41 P55 -
I (M2) P34 P38 B15 P42 P56 198
I/O, PGCK2 P35 P39 B16 P43 P57 199
I/O (HDC) P36 P40 D14 P44 P58 202
I/O - P41 C15 P45 P59 205
I/O - P42 D15 P46 P60 208
I/O - P43 E14 P47 P61 211
I/O (LDC) P37 P44 C16 P48 P62 214
I/O - - E15 P49 P63 217
I/O - - D16 P50 P64 220
GND - P45 F14 P51 P67 -
I/O - P46 F15 P52 P68 223
I/O - P47 E16 P53 P69 226
I/O P38 P48 F16 P54 P70 229
I/O P39 P49 G14 P55 P71 232
I/O - P50 G15 P56 P74 235
I/O - P51 G16 P57 P75 238
I/O P40 P52 H16 P58 P76 241
I/O (INIT) P41 P53 H15 P59 P77 244
VCC P42 P54 H14 P60 P78 -
GND P43 P55 J14 P61 P79 -
I/O P44 P56 J15 P62 P80 247
I/O P45 P57 J16 P63 P81 250
I/O - P58 K16 P64 P82 253
I/O - P59 K15 P65 P83 256
I/O P46 P60 K14 P66 P86 259
I/O P47 P61 L16 P67 P87 262
I/O - P62 M16 P68 P88 265
I/O - P63 L15 P69 P89 268
GND - P64 L14 P70 P90 -
I/O - - N16 P71 P93 271
I/O - - M15 P72 P94 274
I/O P48 P65 P16 P73 P95 277
I/O P49 P66 M14 P74 P96 280
I/O - P67 N15 P75 P97 283
I/O - P68 P15 P76 P98 286
I/O P50 P69 N14 P77 P99 289
I/O, SGCK3 P51 P70 R16 P78 P100 292
GND P52 P71 P14 P79 P101 -
DONE P53 P72 R15 P80 P103 -
VCC P54 P73 P13 P81 P106 -
PROGRAM P55 P74 R14 P82 P108 -
XC4006E
Pad Name PC
84 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
June 1, 1996 (Version 1.02) 4-101
4/2/96
Additional No Connect (N.C.) Connections on PQ160 &
PQ208 Packages
2/28/96
I/O (D7) P56 P75 T16 P83 P109 295
I/O, PGCK3 P57 P76 T15 P84 P110 298
I/O - P77 R13 P85 P111 301
I/O - P78 P12 P86 P112 304
I/O (D6) P58 P79 T14 P87 P113 307
I/O - P80 T13 P88 P114 310
I/O - - R12 P89 P115 313
I/O - - T12 P90 P116 316
GND - P81 P11 P91 P119 -
I/O - P82 R11 P92 P120 319
I/O - P83 T11 P93 P121 322
I/O (D5) P59 P84 T10 P94 P122 325
I/O (CS0) P60 P85 P10 P95 P123 328
I/O - P86 R10 P96 P126 331
I/O - P87 T9 P97 P127 334
I/O (D4) P61 P88 R9 P98 P128 337
I/O P62 P89 P9 P99 P129 340
VCC P63 P90 R8 P100 P130 -
GND P64 P91 P8 P101 P131 -
I/O (D3) P65 P92 T8 P102 P132 343
I/O (RS) P66 P93 T7 P103 P133 346
I/O - P94 T6 P104 P134 349
I/O - P95 R7 P105 P135 352
I/O (D2) P67 P96 P7 P106 P138 355
I/O P68 P97 T5 P107 P139 358
I/O - P98 R6 P108 P140 361
I/O - P99 T4 P109 P141 364
GND - P100 P6 P110 P142 -
I/O - - R5 P111 P145 367
I/O - - - P112 P146 370
I/O (D1) P69 P101 T3 P113 P147 373
I/O (RCLK,
RDY/BUSY) P70 P102 P5 P114 P148 376
I/O - P103 R4 P115 P149 379
I/O - P104 R3 P116 P150 382
I/O (D0, DIN) P71 P105 P4 P117 P151 385
I/O, SGCK4
(DOUT) P72 P106 T2 P118 P152 388
CCLK P73 P107 R2 P119 P153 -
VCC P74 P108 P3 P120 P154 -
O, TDO P75 P109 T1 P121 P159 0
GND P76 P110 N3 P122 P160 -
I/O (A0, WS) P77 P111 R1 P123 P161 2
I/O, PGCK4 (A1) P78 P112 P2 P124 P162 5
I/O - P113 N2 P125 P163 8
I/O - P114 M3 P126 P164 11
I/O (CS1, A2) P79 P115 P1 P127 P165 14
I/O (A3) P80 P116 N1 P128 P166 17
I/O - P117 M2 P129 P167 20
I/O - - M1 P130 P168 23
GND - P118 L3 P131 P171 -
I/O - P119 L2 P132 P172 26
XC4006E
Pad Name PC
84 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan I/O - P120 L1 P133 P173 29
I/O (A4) P81 P121 K3 P134 P174 32
I/O (A5) P82 P122 K2 P135 P175 35
I/O - P123 K1 P137 P178 38
I/O - P124 J1 P138 P179 41
I/O (A6) P83 P125 J2 P139 P180 44
I/O (A7) P84 P126 J3 P140 P181 47
GND P1 P127 H2 P141 P182 -
PQ160 PQ208
P136 P1
P3
P12-P13
P19-20
P31-P32
P38-P39
P51-P54
P65-P66
P72-P73
P84-P85
P91-P92
P102
P104-P105
P107
P117-P118
P124-P125
P136-P137
P143-P144
P155-P158
P169-P170
P176-P177
P188-P189
P195-P196
P206-P208
XC4006E
Pad Name PC
84 TQ
144 PG
156 PQ
160 PQ
208 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-102 June 1, 1996 (Version 1.02)
Pin Locations for XC4008E Devices
XC4008E Pad Name PC
84 PQ
160 PG
191 PQ
208 Bndry
Scan
VCC P2 P142 J4 P183 -
I/O (A8) P3 P143 J3 P184 56
I/O (A9) P4 P144 J2 P185 59
I/O - P145 J1 P186 62
I/O - P146 H1 P187 65
I/O - - H2 P188 68
I/O - - H3 P189 71
I/O (A10) P5 P147 G1 P190 74
I/O (A11) P6 P148 G2 P191 77
I/O - P149 F1 P192 80
I/O - P150 E1 P193 83
GND - P151 G3 P194 -
I/O - P152 C1 P197 86
I/O - P153 E2 P198 89
I/O (A12) P7 P154 F3 P199 92
I/O (A13) P8 P155 D2 P200 95
I/O - P156 B1 P201 98
I/O - P157 E3 P202 101
I/O (A14) P9 P158 C2 P203 104
I/O, SGCK1 (A15) P10 P159 B2 P204 107
VCC P11 P160 D3 P205 -
GND P12 P1 D4 P2 -
I/O, PGCK1 (A16) P13 P2 C3 P4 110
I/O (A17) P14 P3 C4 P5 113
I/O - P4 B3 P6 116
I/O - P5 C5 P7 119
I/O, TDI P15 P6 A2 P8 122
I/O, TCK P16 P7 B4 P9 125
I/O - P8 C6 P10 128
I/O - P9 A3 P11 131
GND - P10 C7 P14 -
I/O - P11 A4 P15 134
I/O - P12 A5 P16 137
I/O, TMS P17 P13 B7 P17 140
I/O P18 P14 A6 P18 143
I/O - - C8 P19 146
I/O - - A7 P20 149
I/O - P15 B8 P21 152
I/O - P16 A8 P22 155
I/O P19 P17 B9 P23 158
I/O P20 P18 C9 P24 161
GND P21 P19 D9 P25 -
VCC P22 P20 D10 P26 -
I/O P23 P21 C10 P27 164
I/O P24 P22 B10 P28 167
I/O - P23 A9 P29 170
I/O - P24 A10 P30 173
I/O - - A11 P31 176
I/O - - C11 P32 179
I/O P25 P25 B11 P33 182
I/O P26 P26 A12 P34 185
I/O - P27 B12 P35 188
I/O - P28 A13 P36 191
GND - P29 C12 P37 -
I/O - P30 A15 P40 194
I/O - P31 C13 P41 197
I/O P27 P32 B14 P42 200
I/O - P33 A16 P43 203
I/O - P34 B15 P44 206
I/O - P35 C14 P45 209
I/O P28 P36 A17 P46 212
I/O, SCGK2 P29 P37 B16 P47 215
O (M1) P30 P38 C15 P48 218
GND P31 P39 D15 P49 -
I (M0) P32 P40 A18 P50 221
VCC P33 P41 D16 P55 -
I (M2) P34 P42 C16 P56 222
I/O, PGCK2 P35 P43 B17 P57 223
I/O (HDC) P36 P44 E16 P58 226
I/O - P45 C17 P59 229
I/O - P46 D17 P60 232
I/O - P47 B18 P61 235
I/O (LDC) P37 P48 E17 P62 238
I/O - P49 F16 P63 241
I/O - P50 C18 P64 244
GND - P51 G16 P67 -
I/O - P52 E18 P68 247
I/O - P53 F18 P69 250
I/O P38 P54 G17 P70 253
I/O P39 P55 G18 P71 256
I/O - - H16 P72 259
I/O - - H17 P73 262
I/O - P56 H18 P74 265
I/O - P57 J18 P75 268
I/O P40 P58 J17 P76 271
I/O (INIT) P41 P59 J16 P77 274
VCC P42 P60 J15 P78 -
GND P43 P61 K15 P79 -
I/O P44 P62 K16 P80 277
I/O P45 P63 K17 P81 280
I/O - P64 K18 P82 283
I/O - P65 L18 P83 286
I/O - - L17 P84 289
I/O - - L16 P85 292
I/O P46 P66 M18 P86 295
I/O P47 P67 M17 P87 298
I/O - P68 N18 P88 301
I/O - P69 P18 P89 304
GND - P70 M16 P90 -
I/O - P71 T18 P93 307
I/O - P72 P17 P94 310
I/O P48 P73 N16 P95 313
XC4008E Pad Name PC
84 PQ
160 PG
191 PQ
208 Bndry
Scan
June 1, 1996 (Version 1.02) 4-103
4/2/96
Additional No Connect (N.C.) Connections on PG191 &
PQ208 Packages
2/28/96
I/O P49 P74 T17 P96 316
I/O - P75 R17 P97 319
I/O - P76 P16 P98 322
I/O P50 P77 U18 P99 325
I/O, SGCK3 P51 P78 T16 P100 328
GND P52 P79 R16 P101 -
DONE P53 P80 U17 P103 -
VCC P54 P81 R15 P106 -
PROGRAM P55 P82 V18 P108 -
I/O (D7) P56 P83 T15 P109 331
I/O, PGCK3 P57 P84 U16 P110 334
I/O - P85 T14 P111 337
I/O - P86 U15 P112 340
I/O (D6) P58 P87 V17 P113 343
I/O - P88 V16 P114 346
I/O - P89 T13 P115 349
I/O - P90 U14 P116 352
GND - P91 T12 P119 -
I/O - P92 U13 P120 355
I/O - P93 V13 P121 358
I/O (D5) P59 P94 U12 P122 361
I/O (CS0) P60 P95 V12 P123 364
I/O - - T11 P124 367
I/O - - U11 P125 370
I/O - P96 V11 P126 373
I/O - P97 V10 P127 376
I/O (D4) P61 P98 U10 P128 379
I/O P62 P99 T10 P129 382
VCC P63 P100 R10 P130 -
GND P64 P101 R9 P131 -
I/O (D3) P65 P102 T9 P132 385
I/O (RS) P66 P103 U9 P133 388
I/O - P104 V9 P134 391
I/O - P105 V8 P135 394
I/O - - U8 P136 397
I/O - - T8 P137 400
I/O (D2) P67 P106 V7 P138 403
I/O P68 P107 U7 P139 406
I/O - P108 V6 P140 409
I/O - P109 U6 P141 412
GND - P110 T7 P142 -
I/O - P111 U5 P145 415
I/O - P112 T6 P146 418
I/O (D1) P69 P113 V3 P147 421
I/O
(RCLK, RDY/BUSY) P70 P114 V2 P148 424
I/O - P115 U4 P149 427
I/O - P116 T5 P150 430
I/O (D0, DIN) P71 P117 U3 P151 433
I/O, SGCK4 (DOUT) P72 P118 T4 P152 436
CCLK P73 P119 V1 P153 -
VCC P74 P120 R4 P154 -
XC4008E Pad Name PC
84 PQ
160 PG
191 PQ
208 Bndry
Scan O, TDO P75 P121 U2 P159 0
GND P76 P122 R3 P160 -
I/O (A0, WS) P77 P123 T3 P161 2
I/O, PGCK4 (A1) P78 P124 U1 P162 5
I/O - P125 P3 P163 8
I/O - P126 R2 P164 11
I/O (CS1, A2) P79 P127 T2 P165 14
I/O (A3) P80 P128 N3 P166 17
I/O - P129 P2 P167 20
I/O - P130 T1 P168 23
GND - P131 M3 P171 -
I/O - P132 P1 P172 26
I/O - P133 N1 P173 29
I/O (A4) P81 P134 M2 P174 32
I/O (A5) P82 P135 M1 P175 35
I/O - - L3 P176 38
I/O - P136 L2 P177 41
I/O - P137 L1 P178 44
I/O - P138 K1 P179 47
I/O (A6) P83 P139 K2 P180 50
I/O (A7) P84 P140 K3 P181 53
GND P1 P141 K4 P182 -
PG191 PQ208 PQ208
A14 P1 P107
B5 P3 P117
B6 P12 P118
B13 P13 P143
D1 P38 P144
D18 P39 P155
F2 P51 P156
F17 P52 P157
N2 P53 P158
N17 P54 P169
R1 P65 P170
R18 P66 P195
V4 P91 P196
V5 P92 P206
V14 P102 P207
V15 P104 P208
P105
XC4008E Pad Name PC
84 PQ
160 PG
191 PQ
208 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-104 June 1, 1996 (Version 1.02)
Pin Locations for XC4010E/L Devices
XC4010E/L
Pad Name PC
84 PQ
160 TQ
176 PG
191
PQ/
HQ
208
BG
225 Bndry
Scan
VCC P2 P142 P155 J4 P183 D8 -
I/O (A8) P3 P143 P156 J3 P184 E8 62
I/O (A9) P4 P144 P157 J2 P185 B7 65
I/O - P145 P158 J1 P186 A7 68
I/O - P146 P159 H1 P187 C7 71
I/O - - P160 H2 P188 D7 74
I/O - - P161 H3 P189 E7 77
I/O (A10) P5 P147 P162 G1 P190 A6 80
I/O (A11) P6 P148 P163 G2 P191 B6 83
I/O - P149 P164 F1 P192 A5 86
I/O - P150 P165 E1 P193 B5 89
GND - P151 P166 G3 P194 GND* -
I/O - - - F2 P195 D6 92
I/O - - P167 D1 P196 C5 95
I/O - P152 P168 C1 P197 A4 98
I/O - P153 P169 E2 P198 E6 101
I/O (A12) P7 P154 P170 F3 P199 B4 104
I/O (A13) P8 P155 P171 D2 P200 D5 107
I/O - P156 P172 B1 P201 B3 110
I/O - P157 P173 E3 P202 F6 113
I/O (A14) P9 P158 P174 C2 P203 A2 116
I/O, SGCK1
(A15) P10 P159 P175 B2 P204 C3 119
VCC P11 P160 P176 D3 P205 B2 -
GND P12 P1 P1 D4 P2 A1 -
I/O, PGCK1
(A16) P13 P2 P2 C3 P4 D4 122
I/O (A17) P14 P3 P3 C4 P5 B1 125
I/O - P4P4B3P6C2 128
I/O - P5 P5 C5 P7 E5 131
I/O, TDI P15 P6 P6 A2 P8 D3 134
I/O, TCK P16 P7 P7 B4 P9 C1 137
I/O - P8 P8 C6 P10 D2 140
I/O - P9 P9 A3 P11 G6 143
I/O - - - B5 P12 E4 146
I/O - - - B6 P13 D1 149
GND - P10 P10 C7 P14 GND* -
I/O - P11 P11 A4 P15 F5 152
I/O - P12 P12 A5 P16 E1 155
I/O, TMS P17 P13 P13 B7 P17 F4 158
I/O P18 P14 P14 A6 P18 F3 161
I/O - - P15 C8 P19 G4 164
I/O - - P16 A7 P20 G3 167
I/O - P15 P17 B8 P21 G2 170
I/O - P16 P18 A8 P22 G1 173
I/O P19 P17 P19 B9 P23 G5 176
I/O P20 P18 P20 C9 P24 H3 179
GND P21 P19 P21 D9 P25 H2 -
VCC P22 P20 P22 D10 P26 H1 -
I/O P23 P21 P23 C10 P27 H4 182
I/O P24 P22 P24 B10 P28 H5 185
I/O - P23 P25 A9 P29 J2 188
I/O - P24 P26 A10 P30 J1 191
I/O - - P27 A11 P31 J3 194
I/O - - P28 C11 P32 J4 197
I/O P25 P25 P29 B11 P33 K2 200
I/O P26 P26 P30 A12 P34 K3 203
I/O - P27 P31 B12 P35 J6 206
I/O - P28 P32 A13 P36 L1 209
GND - P29 P33 C12 P37 GND* -
I/O - - - B13 P38 L3 212
I/O - - - A14 P39 M1 215
I/O - P30 P34 A15 P40 K5 218
I/O - P31 P35 C13 P41 M2 221
I/O P27 P32 P36 B14 P42 L4 224
I/O - P33 P37 A16 P43 N1 227
I/O - P34 P38 B15 P44 M3 230
I/O - P35 P39 C14 P45 N2 233
I/O P28 P36 P40 A17 P46 K6 236
I/O, SCGK2 P29 P37 P41 B16 P47 P1 239
O (M1) P30 P38 P42 C15 P48 N3 242
GND P31 P39 P43 D15 P49 GND* -
I (M0) P32 P40 P44 A18 P50 P2 245
VCC P33 P41 P45 D16 P55 R1 -
I (M2) P34 P42 P46 C16 P56 M4 246
I/O, PGCK2 P35 P43 P47 B17 P57 R2 247
I/O (HDC) P36 P44 P48 E16 P58 P3 250
I/O - P45 P49 C17 P59 L5 253
I/O - P46 P50 D17 P60 N4 256
I/O - P47 P51 B18 P61 R3 259
I/O (LDC) P37 P48 P52 E17 P62 P4 262
I/O - P49 P53 F16 P63 K7 265
I/O - P50 P54 C18 P64 M5 268
I/O - - - D18 P65 R4 271
I/O - - - F17 P66 N5 274
GND - P51 P55 G16 P67 GND* -
I/O - P52 P56 E18 P68 R5 277
I/O - P53 P57 F18 P69 M6 280
I/O P38 P54 P58 G17 P70 N6 283
I/O P39 P55 P59 G18 P71 P6 286
I/O - - P60 H16 P72 R6 289
XC4010E/L
Pad Name PC
84 PQ
160 TQ
176 PG
191
PQ/
HQ
208
BG
225 Bndry
Scan
June 1, 1996 (Version 1.02) 4-105
I/O - - P61 H17 P73 M7 292
I/O - P56 P62 H18 P74 R7 295
I/O - P57 P63 J18 P75 L7 298
I/O P40 P58 P64 J17 P76 N8 301
I/O (INIT) P41 P59 P65 J16 P77 P8 304
VCC P42 P60 P66 J15 P78 R8 -
GND P43 P61 P67 K15 P79 M8 -
I/O P44 P62 P68 K16 P80 L8 307
I/O P45 P63 P69 K17 P81 P9 310
I/O - P64 P70 K18 P82 R9 313
I/O - P65 P71 L18 P83 N9 316
I/O - - P72 L17 P84 M9 319
I/O - - P73 L16 P85 L9 322
I/O P46 P66 P74 M18 P86 N10 325
I/O P47 P67 P75 M17 P87 K9 328
I/O - P68 P76 N18 P88 R11 331
I/O - P69 P77 P18 P89 P11 334
GND - P70 P78 M16 P90 GND* -
I/O - - - N17 P91 R12 337
I/O - - - R18 P92 L10 340
I/O - P71 P79 T18 P93 P12 343
I/O - P72 P80 P17 P94 M11 346
I/O P48 P73 P81 N16 P95 R13 349
I/O P49 P74 P82 T17 P96 N12 352
I/O - P75 P83 R17 P97 P13 355
I/O - P76 P84 P16 P98 K10 358
I/O P50 P77 P85 U18 P99 R14 361
I/O, SGCK3 P51 P78 P86 T16 P100 N13 364
GND P52 P79 P87 R16 P101 GND* -
DONE P53 P80 P88 U17 P103 P14 -
VCC P54 P81 P89 R15 P106 R15 -
PROGRAM P55 P82 P90 V18 P108 M12 -
I/O (D7) P56 P83 P91 T15 P109 P15 367
I/O, PGCK3 P57 P84 P92 U16 P110 N14 370
I/O - P85 P93 T14 P111 L11 373
I/O - P86 P94 U15 P112 M13 376
I/O (D6) P58 P87 P95 V17 P113 J10 379
I/O - P88 P96 V16 P114 L12 382
I/O - P89 P97 T13 P115 M15 385
I/O - P90 P98 U14 P116 L13 388
I/O - - - V15 P117 L14 391
I/O - - - V14 P118 K11 394
GND - P91 P99 T12 P119 GND* -
I/O - P92 P100 U13 P120 K13 397
I/O - P93 P101 V13 P121 K14 400
I/O (D5) P59 P94 P102 U12 P122 K15 403
XC4010E/L
Pad Name PC
84 PQ
160 TQ
176 PG
191
PQ/
HQ
208
BG
225 Bndry
Scan
I/O (CS0) P60 P95 P103 V12 P123 J12 406
I/O - - P104 T11 P124 J13 409
I/O - - P105 U11 P125 J14 412
I/O - P96 P106 V11 P126 J15 415
I/O - P97 P107 V10 P127 J11 418
I/O (D4) P61 P98 P108 U10 P128 H13 421
I/O P62 P99 P109 T10 P129 H14 424
VCC P63 P100 P110 R10 P130 H15 -
GND P64 P101 P111 R9 P131 GND* -
I/O (D3) P65 P102 P112 T9 P132 H12 427
I/O (RS) P66 P103 P113 U9 P133 H11 430
I/O - P104 P114 V9 P134 G14 433
I/O - P105 P115 V8 P135 G15 436
I/O - - P116 U8 P136 G13 439
I/O - - P117 T8 P137 G12 442
I/O (D2) P67 P106 P118 V7 P138 G11 445
I/O P68 P107 P119 U7 P139 F15 448
I/O - P108 P120 V6 P140 F14 451
I/O - P109 P121 U6 P141 F13 454
GND - P110 P122 T7 P142 GND* -
I/O - - - V5 P143 E13 457
I/O - - - V4 P144 D15 460
I/O - P111 P123 U5 P145 F11 463
I/O - P112 P124 T6 P146 D14 466
I/O (D1) P69 P113 P125 V3 P147 E12 469
I/O (RCLK,
RDY/
BUSY)
P70 P114 P126 V2 P148 C15 472
I/O - P115 P127 U4 P149 D13 475
I/O - P116 P128 T5 P150 C14 478
I/O
(D0, DIN) P71 P117 P129 U3 P151 F10 481
I/O, SGCK4
(DOUT) P72 P118 P130 T4 P152 B15 484
CCLK P73 P119 P131 V1 P153 C13 -
VCC P74 P120 P132 R4 P154 B14 -
O, TDO P75 P121 P133 U2 P159 A15 0
GND P76 P122 P134 R3 P160 D12 -
I/O
(A0, WS)P77 P123 P135 T3 P161 A14 2
I/O, PGCK4
(A1) P78 P124 P136 U1 P162 B13 5
I/O - P125 P137 P3 P163 E11 8
I/O - P126 P138 R2 P164 C12 11
I/O
(CS1, A2) P79 P127 P139 T2 P165 A13 14
I/O (A3) P80 P128 P140 N3 P166 B12 17
XC4010E/L
Pad Name PC
84 PQ
160 TQ
176 PG
191
PQ/
HQ
208
BG
225 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-106 June 1, 1996 (Version 1.02)
4/2/96
* Pads labelled GND* are internally bonded to a Ground
plane within the BG225 package. They have no direct con-
nection to any package pin.
Additional Ground (GND) Connections on BG225
Package
2/28/96
Note: The package pins in this table are bonded to an
internal Ground plane within the BG225 package. They
should all be externally connected to Ground.
Additional No Connect (N.C.) Connections on PQ/
HQ208 & BG225 Packages
3/12/96
I/O - P129 P141 P2 P167 A12 20
I/O - P130 P142 T1 P168 C11 23
I/O - - - R1 P169 B11 26
I/O - - - N2 P170 E10 29
GND - P131 P143 M3 P171 GND* -
I/O - P132 P144 P1 P172 A11 32
I/O - P133 P145 N1 P173 D10 35
I/O (A4) P81 P134 P146 M2 P174 A10 38
I/O (A5) P82 P135 P147 M1 P175 D9 41
I/O - - P148 L3 P176 C9 44
I/O - P136 P149 L2 P177 B9 47
I/O - P137 P150 L1 P178 A9 50
I/O - P138 P151 K1 P179 E9 53
I/O (A6) P83 P139 P152 K2 P180 C8 56
I/O (A7) P84 P140 P153 K3 P181 B8 59
GND P1 P141 P154 K4 P182 A8 -
GND
F8
G7
G8
G9
H6
H7
H8
H9
H10
J7
J8
J9
K8
XC4010E/L
Pad Name PC
84 PQ
160 TQ
176 PG
191
PQ/
HQ
208
BG
225 Bndry
Scan PQ/HQ208 BG225
P1 A3
P3 B10
P51 C4
P52 C6
P53 C10
P54 D11
P102 E2
P104 E3
P105 E14
P107 E15
P155 F1
P156 F2
P157 F7
P158 F9
P206 F12
P207 G10
P208 J5
K1
K4
K12
L2
L6
L15
M10
M14
N7
N11
N15
P5
P7
P10
R10
June 1, 1996 (Version 1.02) 4-107
Pin Locations for XC4013E/L Devices
XC4013E/L
Pad Name PQ
160
PQ/
HQ
208
PG
223 BG
225
PQ/
HQ
240
Bndry
Scan
VCC P142 P183 J4 D8 P212 -
I/O (A8) P143 P184 J3 E8 P213 74
I/O (A9) P144 P185 J2 B7 P214 77
I/O P145 P186 J1 A7 P215 80
I/O P146 P187 H1 C7 P216 83
I/O - P188 H2 D7 P217 86
I/O - P189 H3 E7 P218 89
I/O (A10) P147 P190 G1 A6 P220 92
I/O (A11) P148 P191 G2 B6 P221 95
VCC - - - VCC* P222 -
I/O - - H4 C6 P223 98
I/O - - G4 F7 P224 101
I/O P149 P192 F1 A5 P225 104
I/O P150 P193 E1 B5 P226 107
GND P151 P194 G3 GND* P227 -
I/O - P195 F2 D6 P228 110
I/O - P196 D1 C5 P229 113
I/O P152 P197 C1 A4 P230 116
I/O P153 P198 E2 E6 P231 119
I/O (A12) P154 P199 F3 B4 P232 122
I/O (A13) P155 P200 D2 D5 P233 125
I/O - - F4 A3 P234 128
I/O - - E4 C4 P235 131
I/O P156 P201 B1 B3 P236 134
I/O P157 P202 E3 F6 P237 137
I/O (A14) P158 P203 C2 A2 P238 140
I/O, SGCK1
(A15) P159 P204 B2 C3 P239 143
VCC P160 P205 D3 B2 P240 -
GND P1 P2 D4 A1 P1 -
I/O, PGCK1
(A16) P2 P4 C3 D4 P2 146
I/O (A17) P3 P5 C4 B1 P3 149
I/O P4 P6 B3 C2 P4 152
I/O P5 P7 C5 E5 P5 155
I/O, TDI P6 P8 A2 D3 P6 158
I/O, TCK P7 P9 B4 C1 P7 161
I/O P8 P10 C6 D2 P8 164
I/O P9 P11 A3 G6 P9 167
I/O - P12 B5 E4 P10 170
I/O - P13 B6 D1 P11 173
I/O - - D5 E3 P12 176
I/O - - D6 E2 P13 179
GND P10 P14 C7 GND* P14 -
I/O P11 P15 A4 F5 P15 182
I/O P12 P16 A5 E1 P16 185
I/O, TMS P13 P17 B7 F4 P17 188
I/O P14 P18 A6 F3 P18 191
VCC - - - VCC* P19 -
I/O - - D7 F2 P20 194
I/O - - D8 F1 P21 197
I/O - P19 C8 G4 P23 200
I/O - P20 A7 G3 P24 203
I/O P15 P21 B8 G2 P25 206
I/O P16 P22 A8 G1 P26 209
I/O P17 P23 B9 G5 P27 212
I/O P18 P24 C9 H3 P28 215
GND P19 P25 D9 H2 P29 -
VCC P20 P26 D10 H1 P30 -
I/O P21 P27 C10 H4 P31 218
I/O P22 P28 B10 H5 P32 221
I/O P23 P29 A9 J2 P33 224
I/O P24 P30 A10 J1 P34 227
I/O - P31 A11 J3 P35 230
I/O - P32 C11 J4 P36 233
I/O - - D11 J5 P38 236
I/O - - D12 K1 P39 239
VCC - - - VCC* P40 -
I/O P25 P33 B11 K2 P41 242
I/O P26 P34 A12 K3 P42 245
I/O P27 P35 B12 J6 P43 248
I/O P28 P36 A13 L1 P44 251
GND P29 P37 C12 GND* P45 -
I/O - - D13 L2 P46 254
I/O - - D14 K4 P47 257
I/O - P38 B13 L3 P48 260
I/O - P39 A14 M1 P49 263
I/O P30 P40 A15 K5 P50 266
I/O P31 P41 C13 M2 P51 269
I/O P32 P42 B14 L4 P52 272
I/O P33 P43 A16 N1 P53 275
I/O P34 P44 B15 M3 P54 278
I/O P35 P45 C14 N2 P55 281
I/O P36 P46 A17 K6 P56 284
I/O, SCGK2 P37 P47 B16 P1 P57 287
O (M1) P38 P48 C15 N3 P58 290
GND P39 P49 D15 GND* P59 -
I (M0) P40 P50 A18 P2 P60 293
VCC P41 P55 D16 R1 P61 -
I (M2) P42 P56 C16 M4 P62 294
I/O, PGCK2 P43 P57 B17 R2 P63 295
I/O (HDC) P44 P58 E16 P3 P64 298
I/O P45 P59 C17 L5 P65 301
I/O P46 P60 D17 N4 P66 304
I/O P47 P61 B18 R3 P67 307
I/O (LDC) P48 P62 E17 P4 P68 310
I/O P49 P63 F16 K7 P69 313
I/O P50 P64 C18 M5 P70 316
I/O - P65 D18 R4 P71 319
XC4013E/L
Pad Name PQ
160
PQ/
HQ
208
PG
223 BG
225
PQ/
HQ
240
Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-108 June 1, 1996 (Version 1.02)
I/O - P66 F17 N5 P72 322
I/O - - E15 P5 P73 325
I/O - - F15 L6 P74 328
GND P51 P67 G16 GND* P75 -
I/O P52 P68 E18 R5 P76 331
I/O P53 P69 F18 M6 P77 334
I/O P54 P70 G17 N6 P78 337
I/O P55 P71 G18 P6 P79 340
VCC - - - VCC* P80 -
I/O - P72 H16 R6 P81 343
I/O - P73 H17 M7 P82 346
I/O - - G15 N7 P84 349
I/O - - H15 P7 P85 352
I/O P56 P74 H18 R7 P86 355
I/O P57 P75 J18 L7 P87 358
I/O P58 P76 J17 N8 P88 361
I/O (INIT) P59 P77 J16 P8 P89 364
VCC P60 P78 J15 R8 P90 -
GND P61 P79 K15 M8 P91 -
I/O P62 P80 K16 L8 P92 367
I/O P63 P81 K17 P9 P93 370
I/O P64 P82 K18 R9 P94 373
I/O P65 P83 L18 N9 P95 376
I/O - P84 L17 M9 P96 379
I/O - P85 L16 L9 P97 382
I/O - - L15 R10 P99 385
I/O - - M15 P10 P100 388
VCC - - - VCC* P101 -
I/O P66 P86 M18 N10 P102 391
I/O P67 P87 M17 K9 P103 394
I/O P68 P88 N18 R11 P104 397
I/O P69 P89 P18 P11 P105 400
GND P70 P90 M16 GND* P106 -
I/O - - N15 M10 P107 403
I/O - - P15 N11 P108 406
I/O - P91 N17 R12 P109 409
I/O - P92 R18 L10 P110 412
I/O P71 P93 T18 P12 P111 415
I/O P72 P94 P17 M11 P112 418
I/O P73 P95 N16 R13 P113 421
I/O P74 P96 T17 N12 P114 424
I/O P75 P97 R17 P13 P115 427
I/O P76 P98 P16 K10 P116 430
I/O P77 P99 U18 R14 P117 433
I/O, SGCK3 P78 P100 T16 N13 P118 436
GND P79 P101 R16 GND* P119 -
DONE P80 P103 U17 P14 P120 -
VCC P81 P106 R15 R15 P121 -
PROGRAM P82 P108 V18 M12 P122 -
I/O (D7) P83 P109 T15 P15 P123 439
XC4013E/L
Pad Name PQ
160
PQ/
HQ
208
PG
223 BG
225
PQ/
HQ
240
Bndry
Scan
I/O, PGCK3 P84 P110 U16 N14 P124 442
I/O P85 P111 T14 L11 P125 445
I/O P86 P112 U15 M13 P126 448
I/O - - R14 N15 P127 451
I/O - - R13 M14 P128 454
I/O (D6) P87 P113 V17 J10 P129 457
I/O P88 P114 V16 L12 P130 460
I/O P89 P115 T13 M15 P131 463
I/O P90 P116 U14 L13 P132 466
I/O - P117 V15 L14 P133 469
I/O - P118 V14 K11 P134 472
GND P91 P119 T12 GND* P135 -
I/O - - R12 L15 P136 475
I/O - - R11 K12 P137 478
I/O P92 P120 U13 K13 P138 481
I/O P93 P121 V13 K14 P139 484
VCC - - - VCC* P140 -
I/O (D5) P94 P122 U12 K15 P141 487
I/O (CS0) P95 P123 V12 J12 P142 490
I/O - P124 T11 J13 P144 493
I/O - P125 U11 J14 P145 496
I/O P96 P126 V11 J15 P146 499
I/O P97 P127 V10 J11 P147 502
I/O (D4) P98 P128 U10 H13 P148 505
I/O P99 P129 T10 H14 P149 508
VCC P100 P130 R10 H15 P150 -
GND P101 P131 R9 GND* P151 -
I/O (D3) P102 P132 T9 H12 P152 511
I/O (RS) P103 P133 U9 H11 P153 514
I/O P104 P134 V9 G14 P154 517
I/O P105 P135 V8 G15 P155 520
I/O - P136 U8 G13 P156 523
I/O - P137 T8 G12 P157 526
I/O (D2) P106 P138 V7 G11 P159 529
I/O P107 P139 U7 F15 P160 532
VCC - - - VCC* P161 -
I/O P108 P140 V6 F14 P162 535
I/O P109 P141 U6 F13 P163 538
I/O - - R8 G10 P164 541
I/O - - R7 E15 P165 544
GND P110 P142 T7 GND* P166 -
I/O - - R6 E14 P167 547
I/O - - R5 F12 P168 550
I/O - P143 V5 E13 P169 553
I/O - P144 V4 D15 P170 556
I/O P111 P145 U5 F11 P171 559
I/O P112 P146 T6 D14 P172 562
I/O (D1) P113 P147 V3 E12 P173 565
I/O (RCLK,
RDY/BUSY) P114 P148 V2 C15 P174 568
I/O P115 P149 U4 D13 P175 571
XC4013E/L
Pad Name PQ
160
PQ/
HQ
208
PG
223 BG
225
PQ/
HQ
240
Bndry
Scan
June 1, 1996 (Version 1.02) 4-109
4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the BG225 package. They have no direct con-
nection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the BG225 package. They have no direct connection
to any package pin.
Additional Ground (GND) Connections on BG225
Packages
3/11/96
The BG225 package pins in this table are bonded to an in-
ternal Ground plane on the XC4013E/L die. They must all
be externally connected to Ground.
Additional No Connect (N.C.) Connections on PQ/
HQ208 & PQ/HQ240 Packages
3/20/96
‡ Pins marked with this symbol are reserved for Ground
connections on future revisions of the device. These pins
do not physically connect to anything on the current device
revision. However, they should be externally connected to
Ground, if possible.
I/O P116 P150 T5 C14 P176 574
I/O
(D0, DIN) P117 P151 U3 F10 P177 577
I/O, SGCK4
(DOUT) P118 P152 T4 B15 P178 580
CCLK P119 P153 V1 C13 P179 -
VCC P120 P154 R4 B14 P180 -
O, TDO P121 P159 U2 A15 P181 0
GND P122 P160 R3 D12 P182 -
I/O
(A0, WS)P123 P161 T3 A14 P183 2
I/O, PGCK4
(A1) P124 P162 U1 B13 P184 5
I/O P125 P163 P3 E11 P185 8
I/O P126 P164 R2 C12 P186 11
I/O
(CS1, A2) P127 P165 T2 A13 P187 14
I/O (A3) P128 P166 N3 B12 P188 17
I/O - - P4 F9 P189 20
I/O - - N4 D11 P190 23
I/O P129 P167 P2 A12 P191 26
I/O P130 P168 T1 C11 P192 29
I/O - P169 R1 B11 P193 32
I/O - P170 N2 E10 P194 35
GND P131 P171 M3 GND* P196 -
I/O P132 P172 P1 A11 P197 38
I/O P133 P173 N1 D10 P198 41
I/O - - M4 C10 P199 44
I/O - - L4 B10 P200 47
VCC - - - VCC* P201 -
I/O (A4) P134 P174 M2 A10 P202 50
I/O (A5) P135 P175 M1 D9 P203 53
I/O - P176 L3 C9 P205 56
I/O P136 P177 L2 B9 P206 59
I/O P137 P178 L1 A9 P207 62
I/O P138 P179 K1 E9 P208 65
I/O (A6) P139 P180 K2 C8 P209 68
I/O (A7) P140 P181 K3 B8 P210 71
GND P141 P182 K4 A8 P211 -
XC4013E/L
Pad Name PQ
160
PQ/
HQ
208
PG
223 BG
225
PQ/
HQ
240
Bndry
Scan BG225 BG225
K8 H9
J7 H10
J8 G7
J9 G8
H6 G9
H7 F8
H8
PQ/HQ208 PQ/HQ240
P1 P22 ‡
P3 P37 ‡
P51 P83 ‡
P52 P98 ‡
P53 P143 ‡
P54 P158 ‡
P102 P195
P104 P204 ‡
P105 P219 ‡
P107
P155
P156
P157
P158
P206
P207
P208
XC4000 Series Field Programmable Gate Arrays
4-110 June 1, 1996 (Version 1.02)
Pin Locations for XC4020E Devices
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan
VCC P183 J4 P212 -
I/O (A8) P184 J3 P213 86
I/O (A9) P185 J2 P214 89
I/O P186 J1 P215 92
I/O P187 H1 P216 95
I/O P188 H2 P217 98
I/O P189 H3 P218 101
I/O (A10) P190 G1 P220 104
I/O (A11) P191 G2 P221 107
I/O - - - 110
I/O - - - 113
VCC - - P222 -
I/O - H4 P223 116
I/O - G4 P224 119
I/O P192 F1 P225 122
I/O P193 E1 P226 125
GND P194 G3 P227 -
I/O P195 F2 P228 128
I/O P196 D1 P229 131
I/O P197 C1 P230 134
I/O P198 E2 P231 137
I/O (A12) P199 F3 P232 140
I/O (A13) P200 D2 P233 143
I/O - - - 146
I/O - - - 149
I/O - F4 P234 152
I/O - E4 P235 155
I/O P201 B1 P236 158
I/O P202 E3 P237 161
I/O (A14) P203 C2 P238 164
I/O, SGCK1 (A15) P204 B2 P239 167
VCC P205 D3 P240 -
GND P2 D4 P1 -
I/O, PGCK1 (A16) P4 C3 P2 170
I/O (A17) P5 C4 P3 173
I/O P6 B3 P4 176
I/O P7 C5 P5 179
I/O, TDI P8 A2 P6 182
I/O, TCK P9 B4 P7 185
I/O - - - 188
I/O - - - 191
I/O P10 C6 P8 194
I/O P11 A3 P9 197
I/O P12 B5 P10 200
I/O P13 B6 P11 203
I/O - D5 P12 206
I/O - D6 P13 209
GND P14 C7 P14 -
I/O P15 A4 P15 212
I/O P16 A5 P16 215
I/O, TMS P17 B7 P17 218
I/O P18 A6 P18 221
VCC - - P19 -
I/O - D7 P20 224
I/O - D8 P21 227
I/O - - - 230
I/O - - - 233
I/O P19 C8 P23 236
I/O P20 A7 P24 239
I/O P21 B8 P25 242
I/O P22 A8 P26 245
I/O P23 B9 P27 248
I/O P24 C9 P28 251
GND P25 D9 P29 -
VCC P26 D10 P30 -
I/O P27 C10 P31 254
I/O P28 B10 P32 257
I/O P29 A9 P33 260
I/O P30 A10 P34 263
I/O P31 A11 P35 266
I/O P32 C11 P36 269
I/O - - - 272
I/O - - - 275
I/O - D11 P38 278
I/O - D12 P39 281
VCC - - P40 -
I/O P33 B11 P41 284
I/O P34 A12 P42 287
I/O P35 B12 P43 290
I/O P36 A13 P44 293
GND P37 C12 P45 -
I/O - D13 P46 296
I/O - D14 P47 299
I/O P38 B13 P48 302
I/O P39 A14 P49 305
I/O P40 A15 P50 308
I/O P41 C13 P51 311
I/O - - - 314
I/O - - - 317
I/O P42 B14 P52 320
I/O P43 A16 P53 323
I/O P44 B15 P54 326
I/O P45 C14 P55 329
I/O P46 A17 P56 332
I/O, SCGK2 P47 B16 P57 335
O (M1) P48 C15 P58 338
GND P49 D15 P59 -
I (M0) P50 A18 P60 341
VCC P55 D16 P61 -
I (M2) P56 C16 P62 342
I/O, PGCK2 P57 B17 P63 343
I/O (HDC) P58 E16 P64 346
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan
June 1, 1996 (Version 1.02) 4-111
I/O P59 C17 P65 349
I/O P60 D17 P66 352
I/O P61 B18 P67 355
I/O (LDC) P62 E17 P68 358
I/O - - - 361
I/O - - - 364
I/O P63 F16 P69 367
I/O P64 C18 P70 370
I/O P65 D18 P71 373
I/O P66 F17 P72 376
I/O - E15 P73 379
I/O - F15 P74 382
GND P67 G16 P75 -
I/O P68 E18 P76 385
I/O P69 F18 P77 388
I/O P70 G17 P78 391
I/O P71 G18 P79 394
VCC - - P80 -
I/O P72 H16 P81 397
I/O P73 H17 P82 400
I/O - - - 403
I/O - - - 406
I/O - G15 P84 409
I/O - H15 P85 412
I/O P74 H18 P86 415
I/O P75 J18 P87 418
I/O P76 J17 P88 421
I/O (INIT) P77 J16 P89 424
VCC P78 J15 P90 -
GND P79 K15 P91 -
I/O P80 K16 P92 427
I/O P81 K17 P93 430
I/O P82 K18 P94 433
I/O P83 L18 P95 436
I/O P84 L17 P96 439
I/O P85 L16 P97 442
I/O - - - 445
I/O - - - 448
I/O - L15 P99 451
I/O - M15 P100 454
VCC - - P101 -
I/O P86 M18 P102 457
I/O P87 M17 P103 460
I/O P88 N18 P104 463
I/O P89 P18 P105 466
GND P90 M16 P106 -
I/O - N15 P107 469
I/O - P15 P108 472
I/O P91 N17 P109 475
I/O P92 R18 P110 478
I/O P93 T18 P111 481
I/O P94 P17 P112 484
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan I/O - - - 487
I/O - - - 490
I/O P95 N16 P113 493
I/O P96 T17 P114 496
I/O P97 R17 P115 499
I/O P98 P16 P116 502
I/O P99 U18 P117 505
I/O, SGCK3 P100 T16 P118 508
GND P101 R16 P119 -
DONE P103 U17 P120 -
VCC P106 R15 P121 -
PROGRAM P108 V18 P122 -
I/O (D7) P109 T15 P123 511
I/O, PGCK3 P110 U16 P124 514
I/O P111 T14 P125 517
I/O P112 U15 P126 520
I/O - R14 P127 523
I/O - R13 P128 526
I/O - - - 529
I/O - - - 532
I/O (D6) P113 V17 P129 535
I/O P114 V16 P130 538
I/O P115 T13 P131 541
I/O P116 U14 P132 544
I/O P117 V15 P133 547
I/O P118 V14 P134 550
GND P119 T12 P135 -
I/O - R12 P136 553
I/O - R11 P137 556
I/O P120 U13 P138 559
I/O P121 V13 P139 562
VCC - - P140 -
I/O (D5) P122 U12 P141 565
I/O (CS0) P123 V12 P142 568
I/O - - - 571
I/O - - - 574
I/O P124 T11 P144 577
I/O P125 U11 P145 580
I/O P126 V11 P146 583
I/O P127 V10 P147 586
I/O (D4) P128 U10 P148 589
I/O P129 T10 P149 592
VCC P130 R10 P150 -
GND P131 R9 P151 -
I/O (D3) P132 T9 P152 595
I/O (RS) P133 U9 P153 598
I/O P134 V9 P154 601
I/O P135 V8 P155 604
I/O P136 U8 P156 607
I/O P137 T8 P157 610
I/O - - - 613
I/O - - - 616
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-112 June 1, 1996 (Version 1.02)
4/2/96
Additional No Connect (N.C.) Connections on HQ208 &
HQ240 Packages
3/20/96
‡ Pins marked with this symbol are reserved for Ground
connections on future revisions of the device. These pins
do not physically connect to anything on the current device
revision. However, they should be externally connected to
Ground, if possible.
I/O (D2) P138 V7 P159 619
I/O P139 U7 P160 622
VCC - - P161 -
I/O P140 V6 P162 625
I/O P141 U6 P163 628
I/O - R8 P164 631
I/O - R7 P165 634
GND P142 T7 P166 -
I/O - R6 P167 637
I/O - R5 P168 640
I/O P143 V5 P169 643
I/O P144 V4 P170 646
I/O P145 U5 P171 649
I/O P146 T6 P172 652
I/O (D1) P147 V3 P173 655
I/O (RCLK, RDY/BUSY) P148 V2 P174 658
I/O - - - 661
I/O - - - 664
I/O P149 U4 P175 667
I/O P150 T5 P176 670
I/O (D0, DIN) P151 U3 P177 673
I/O, SGCK4 (DOUT) P152 T4 P178 676
CCLK P153 V1 P179 -
VCC P154 R4 P180 -
O, TDO P159 U2 P181 0
GND P160 R3 P182 -
I/O (A0, WS) P161 T3 P183 2
I/O, PGCK4 (A1) P162 U1 P184 5
I/O P163 P3 P185 8
I/O P164 R2 P186 11
I/O (CS1, A2) P165 T2 P187 14
I/O (A3) P166 N3 P188 17
I/O - - - 20
I/O - - - 23
I/O - P4 P189 26
I/O - N4 P190 29
I/O P167 P2 P191 32
I/O P168 T1 P192 35
I/O P169 R1 P193 38
I/O P170 N2 P194 41
GND P171 M3 P196 -
I/O P172 P1 P197 44
I/O P173 N1 P198 47
I/O - M4 P199 50
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan I/O - L4 P200 53
VCC - - P201 -
I/O - - - 56
I/O - - - 59
I/O (A4) P174 M2 P202 62
I/O (A5) P175 M1 P203 65
I/O P176 L3 P205 68
I/O P177 L2 P206 71
I/O P178 L1 P207 74
I/O P179 K1 P208 77
I/O (A6) P180 K2 P209 80
I/O (A7) P181 K3 P210 83
GND P182 K4 P211 -
HQ208 HQ240
P1 P22 ‡
P3 P37 ‡
P51 P83 ‡
P52 P98 ‡
P53 P143 ‡
P54 P158 ‡
P102 P195
P104 P204 ‡
P105 P219 ‡
P107
P155
P156
P157
P158
P206
P207
P208
XC4020E Pad Name HQ
208 PG
223 HQ
240 Bndry
Scan
June 1, 1996 (Version 1.02) 4-113
Pin Locations for XC4025E, XC4028EX, &
XC4028XL Devices
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
VCC P183 J4 P212 K1 P38 VCC* -
I/O (A8) P184 J3 P213 K2 P37 D14 98
I/O (A9) P185 J2 P214 K3 P36 C14 101
I/O (A19) P186 J1 P215 K5 P35 A15 104
I/O (A18) P187 H1 P216 K4 P34 B15 107
I/O P188 H2 P217 J1 P33 C15 110
I/O P189 H3 P218 J2 P32 D15 113
I/O (A10) P190 G1 P220 H1 P31 A16 116
I/O (A11) P191 G2 P221 J3 P30 B16 119
GND -----GND* -
I/O - - - J4 P29 C16 122
I/O - - - J5 P28 B17 125
I/O - - - H2 P27 C17 128
I/O - - - G1 P26 B18 131
VCC - - P222 E1 P25 VCC* -
I/O - H4 P223 H3 P23 C18 134
I/O - G4 P224 G2 P22 D17 137
I/O P192 F1 P225 H4 P21 A20 140
I/O P193 E1 P226 F2 P20 B19 143
GND P194 G3 P227 F1 P19 GND* -
I/O - - - H5 P18 C19 146
I/O - - - G3 P17 D18 149
I/O P195 F2 P228 D1 P16 A21 152
I/O P196 D1 P229 G4 P15 B20 155
I/O P197 C1 P230 E2 P14 C20 158
I/O P198 E2 P231 F3 P13 B21 161
I/O (A12) P199 F3 P232 G5 P12 B22 164
I/O (A13) P200 D2 P233 C1 P10 C21 167
GND -----GND* -
VCC -----VCC* -
I/O - - - F4 P9 D20 170
I/O - - - E3 P8 A23 173
I/O - F4 P234 D2 P7 D21 176
I/O - E4 P235 C2 P6 C22 179
I/O P201 B1 P236 F5 P5 B24 182
I/O P202 E3 P237 E4 P4 C23 185
I/O (A14) P203 C2 P238 D3 P3 D22 188
I/O, SGCK1,
GCK8 (A15) P204 B2 P239 C3 P2 C24 191
VCC P205 D3 P240 A2 P1 VCC* -
GND P2 D4 P1 B1 P304 GND* -
I/O, PGCK1,
GCK1 (A16) P4 C3 P2 D4 P303 D23 194
I/O (A17) P5 C4 P3 B2 P302 C25 197
I/O P6 B3 P4 B3 P301 D24 200
I/O P7 C5 P5 E6 P300 E23 203
I/O, TDI P8 A2 P6 D5 P299 C26 206
I/O, TCK P9 B4 P7 C4 P298 E24 209
I/O - - - A3 P297 F24 212
I/O - - - D6 P296 E25 215
VCC -----VCC* -
GND -----GND* -
I/O P10 C6 P8 E7 P295 D26 218
I/O P11 A3 P9 B4 P294 G24 221
I/O P12 B5 P10 C5 P293 F25 224
I/O P13 B6 P11 A4 P292 F26 227
I/O - D5 P12 D7 P291 H23 230
I/O - D6 P13 C6 P290 H24 233
I/O - - - E8 P289 G25 236
I/O - - - B5 P288 G26 239
GND P14 C7 P14 A5 P287 GND* -
I/O, FCLK1 P15 A4 P15 B6 P286 J23 242
I/O P16 A5 P16 D8 P285 J24 245
I/O, TMS P17 B7 P17 C7 P284 H25 248
I/O P18 A6 P18 B7 P283 K23 251
VCC - - P19 A6 P282 VCC* -
I/O - D7 P20 C8 P280 K24 254
I/O - D8 P21 E9 P279 J25 257
I/O - - - A7 P278 L24 260
I/O - - - D9 P277 K25 263
GND‡ - - P22 - - GND* -
I/O - - - B8 P276 L25 266
I/O - - - A8 P275 L26 269
I/O P19 C8 P23 C9 P274 M23 272
I/O P20 A7 P24 B9 P273 M24 275
I/O P21 B8 P25 E10 P272 M25 278
I/O P22 A8 P26 A9 P271 M26 281
I/O P23 B9 P27 D10 P270 N24 284
I/O P24 C9 P28 C10 P269 N25 287
GND P25 D9 P29 A10 P268 GND* -
VCC P26 D10 P30 A11 P267 VCC* -
I/O P27 C10 P31 B10 P266 N26 290
I/O P28 B10 P32 B11 P265 P25 293
I/O P29 A9 P33 C11 P264 P23 296
I/O P30 A10 P34 E11 P263 P24 299
I/O P31 A11 P35 D11 P262 R26 302
I/O P32 C11 P36 A12 P261 R25 305
I/O - - - B12 P260 R24 308
I/O - - - A13 P259 R23 311
GND‡ - - P37 - - GND* -
I/O - - - C12 P258 T26 314
I/O - - - D12 P257 T25 317
I/O - D11 P38 E12 P256 T23 320
I/O - D12 P39 B13 P255 V26 323
VCC - - P40 A16 P253 VCC* -
I/O P33 B11 P41 A14 P252 U24 326
I/O P34 A12 P42 C13 P251 V25 329
I/O P35 B12 P43 B14 P250 V24 332
I/O, FCLK2 P36 A13 P44 D13 P249 U23 335
GND P37 C12 P45 A15 P248 GND* -
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-114 June 1, 1996 (Version 1.02)
I/O - - - B15 P247 Y26 338
I/O - - - E13 P246 W25 341
I/O - D13 P46 C14 P245 W24 344
I/O - D14 P47 A17 P244 V23 347
I/O P38 B13 P48 D14 P243 AA26 350
I/O P39 A14 P49 B16 P242 Y25 353
I/O P40 A15 P50 C15 P241 Y24 356
I/O P41 C13 P51 E14 P240 AA25 359
GND -----GND* -
VCC -----VCC* -
I/O - - - A18 P239 AB25 362
I/O - - - D15 P238 AA24 365
I/O P42 B14 P52 C16 P237 Y23 368
I/O P43 A16 P53 B17 P236 AC26 371
I/O P44 B15 P54 B18 P235 AA23 374
I/O P45 C14 P55 E15 P234 AB24 377
I/O P46 A17 P56 D16 P233 AD25 380
I/O, SGCK2,
GCK2 P47 B16 P57 C17 P232 AC24 383
O (M1) P48 C15 P58 A20 P231 AB23 386
GND P49 D15 P59 A19 P230 GND* -
I (M0) P50 A18 P60 C18 P229 AD24 389
VCC P55 D16 P61 B20 P228 VCC* -
I (M2) P56 C16 P62 D17 P227 AC23 390
I/O, PGCK2,
GCK3 P57 B17 P63 B19 P226 AE24 391
I/O (HDC) P58 E16 P64 C19 P225 AD23 394
I/O P59 C17 P65 F16 P224 AC22 397
I/O P60 D17 P66 E17 P223 AF24 400
I/O P61 B18 P67 D18 P222 AD22 403
I/O (LDC) P62 E17 P68 C20 P221 AE23 406
I/O - - - F17 P220 AE22 409
I/O - - - G16 P219 AF23 412
VCC -----VCC* -
GND -----GND* -
I/O P63 F16 P69 D19 P218 AD20 415
I/O P64 C18 P70 E18 P217 AE21 418
I/O P65 D18 P71 D20 P216 AF21 421
I/O P66 F17 P72 G17 P215 AC19 424
I/O - E15 P73 F18 P214 AD19 427
I/O - F15 P74 H16 P213 AE20 430
I/O - - - E19 P212 AF20 433
I/O - - - F19 P211 AC18 436
GND P67 G16 P75 E20 P210 GND* -
I/O P68 E18 P76 H17 P209 AD18 439
I/O P69 F18 P77 G18 P208 AE19 442
I/O P70 G17 P78 G19 P207 AC17 445
I/O P71 G18 P79 H18 P206 AD17 448
VCC - - P80 F20 P204 VCC* -
I/O P72 H16 P81 J16 P203 AE18 451
I/O P73 H17 P82 G20 P202 AF18 454
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
I/O - - - J17 P201 AE17 457
I/O - - - H19 P200 AE16 460
GND‡ - - P83 - - GND* -
I/O - - - H20 P199 AF16 463
I/O - - - J18 P198 AC15 466
I/O - G15 P84 J19 P197 AD15 469
I/O - H15 P85 K16 P196 AE15 472
I/O P74 H18 P86 J20 P195 AF15 475
I/O P75 J18 P87 K17 P194 AD14 478
I/O P76 J17 P88 K18 P193 AE14 481
I/O (INIT) P77 J16 P89 K19 P192 AF14 484
VCC P78 J15 P90 L20 P191 VCC* -
GND P79 K15 P91 K20 P190 GND* -
I/O P80 K16 P92 L19 P189 AE13 487
I/O P81 K17 P93 L18 P188 AC13 490
I/O P82 K18 P94 L16 P187 AD13 493
I/O P83 L18 P95 L17 P186 AF12 496
I/O P84 L17 P96 M20 P185 AE12 499
I/O P85 L16 P97 M19 P184 AD12 502
I/O - - - N20 P183 AC12 505
I/O - - - M18 P182 AF11 508
GND‡ - - P98 - - GND* -
I/O - - - M17 P181 AE11 511
I/O - - - M16 P180 AD11 514
I/O - L15 P99 N19 P179 AF9 517
I/O - M15 P100 P20 P178 AD10 520
VCC - - P101 T20 P177 VCC* -
I/O P86 M18 P102 N18 P175 AE9 523
I/O P87 M17 P103 P19 P174 AD9 526
I/O P88 N18 P104 N17 P173 AC10 529
I/O P89 P18 P105 R19 P172 AF7 532
GND P90 M16 P106 R20 P171 GND* -
I/O - - - N16 P170 AE8 535
I/O - - - P18 P169 AD8 538
I/O - N15 P107 U20 P168 AC9 541
I/O - P15 P108 P17 P167 AF6 544
I/O P91 N17 P109 T19 P166 AE7 547
I/O P92 R18 P110 R18 P165 AD7 550
I/O P93 T18 P111 P16 P164 AE6 553
I/O P94 P17 P112 V20 P163 AE5 556
GND -----GND* -
VCC -----VCC* -
I/O - - - R17 P162 AD6 559
I/O - - - T18 P161 AC7 562
I/O P95 N16 P113 U19 P160 AF4 565
I/O P96 T17 P114 V19 P159 AF3 568
I/O P97 R17 P115 R16 P158 AD5 571
I/O P98 P16 P116 T17 P157 AE3 574
I/O P99 U18 P117 U18 P156 AD4 577
I/O, SGCK3,
GCK4 P100 T16 P118 X20 P155 AC5 580
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
June 1, 1996 (Version 1.02) 4-115
GND P101 R16 P119 W20 P154 GND* -
DONE P103 U17 P120 V18 P153 AD3 -
VCC P106 R15 P121 X19 P152 VCC* -
PROGRAM P108 V18 P122 U17 P151 AC4 -
I/O (D7) P109 T15 P123 W19 P150 AD2 583
I/O, PGCK3,
GCK5 P110 U16 P124 W18 P149 AC3 586
I/O P111 T14 P125 T15 P148 AB4 589
I/O P112 U15 P126 U16 P147 AD1 592
I/O - R14 P127 V17 P146 AA4 595
I/O - R13 P128 X18 P145 AA3 598
I/O - - - U15 P144 AB2 601
I/O - - - T14 P143 AC1 604
VCC -----VCC* -
GND -----GND* -
I/O (D6) P113 V17 P129 W17 P142 Y3 607
I/O P114 V16 P130 V16 P141 AA2 610
I/O P115 T13 P131 X17 P140 AA1 613
I/O P116 U14 P132 U14 P139 W4 616
I/O P117 V15 P133 V15 P138 W3 619
I/O P118 V14 P134 T13 P137 Y2 622
I/O - - - W16 P136 Y1 625
I/O - - - W15 P135 V4 628
GND P119 T12 P135 X16 P134 GND* -
I/O - R12 P136 U13 P133 V3 631
I/O - R11 P137 V14 P132 W2 634
I/O, FCLK3 P120 U13 P138 W14 P131 U4 637
I/O P121 V13 P139 V13 P130 U3 640
VCC - - P140 X15 P129 VCC* -
I/O (D5) P122 U12 P141 T12 P127 V2 643
I/O (CS0) P123 V12 P142 X14 P126 V1 646
GND‡ - - P143 - - - -
I/O - - - U12 P125 U2 649
I/O - - - W13 P124 T2 652
GND -----GND* -
I/O - - - X13 P123 T1 655
I/O - - - V12 P122 R4 658
I/O P124 T11 P144 W12 P121 R3 661
I/O P125 U11 P145 T11 P120 R2 664
I/O P126 V11 P146 X12 P119 R1 667
I/O P127 V10 P147 U11 P118 P3 670
I/O (D4) P128 U10 P148 V11 P117 P2 673
I/O P129 T10 P149 W11 P116 P1 676
VCC P130 R10 P150 X10 P115 VCC* -
GND P131 R9 P151 X11 P114 GND* -
I/O (D3) P132 T9 P152 W10 P113 N2 679
I/O (RS) P133 U9 P153 V10 P112 N4 682
I/O P134 V9 P154 T10 P111 N3 685
I/O P135 V8 P155 U10 P110 M1 688
I/O P136 U8 P156 X9 P109 M2 691
I/O P137 T8 P157 W9 P108 M3 694
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
I/O - - - X8 P107 M4 697
I/O - - - V9 P106 L1 700
GND‡ - - P158 - - GND* -
I/O - - - U9 P105 L2 703
I/O - - - T9 P104 L3 706
I/O (D2) P138 V7 P159 W8 P103 J1 709
I/O P139 U7 P160 X7 P102 K3 712
VCC - - P161 X5 P101 VCC* -
I/O P140 V6 P162 V8 P99 J2 715
I/O, FCLK4 P141 U6 P163 W7 P98 J3 718
I/O - R8 P164 U8 P97 K4 721
I/O - R7 P165 W6 P96 G1 724
GND P142 T7 P166 X6 P95 GND* -
I/O - - - T8 P94 H2 727
I/O - - - V7 P93 H3 730
I/O - R6 P167 X4 P92 J4 733
I/O - R5 P168 U7 P91 F1 736
I/O P143 V5 P169 W5 P90 G2 739
I/O P144 V4 P170 V6 P89 G3 742
I/O P145 U5 P171 T7 P88 F2 745
I/O P146 T6 P172 X3 P87 E2 748
GND -----GND* -
VCC -----VCC* -
I/O (D1) P147 V3 P173 U6 P86 F3 751
I/O (RCLK,
RDY/BUSY) P148 V2 P174 V5 P85 G4 754
I/O - - - W4 P84 D2 757
I/O - - - W3 P83 F4 760
I/O P149 U4 P175 T6 P82 E3 763
I/O P150 T5 P176 U5 P81 C2 766
I/O
(D0, DIN) P151 U3 P177 V4 P80 D3 769
I/O, SGCK4,
GCK6
(DOUT)
P152 T4 P178 X1 P79 E4 772
CCLK P153 V1 P179 V3 P78 C3 -
VCC P154 R4 P180 W1 P77 VCC* -
O, TDO P159 U2 P181 U4 P76 D4 0
GND P160 R3 P182 X2 P75 GND* -
I/O (A0, WS) P161 T3 P183 W2 P74 B3 2
I/O, PGCK4,
GCK7 (A1) P162 U1 P184 V2 P73 C4 5
I/O P163 P3 P185 R5 P72 D5 8
I/O P164 R2 P186 T4 P71 A3 11
I/O
(CS1, A2) P165 T2 P187 U3 P70 D6 14
I/O (A3) P166 N3 P188 V1 P69 C6 17
I/O - - - R4 P68 B5 20
I/O - - - P5 P67 A4 23
VCC -----VCC* -
GND -----GND* -
I/O - P4 P189 U2 P66 C7 26
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-116 June 1, 1996 (Version 1.02)
4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the BG352 package. They have no direct con-
nection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the BG352 package. They have no direct connection
to any package pin.
Pads labelled GND‡ should be connected to Ground if pos-
sible; however, they can be left unconnected if necessary
for compatibility with other devices.
Additional No Connect (N.C.) Connections on HQ208
Package
3/15/96
Additional Ground (GND) Connections on HQ240
Package
3/21/96
The Ground (GND) package pins in the above table should
be externally connected to Ground if possible; however,
they can be left unconnected if necessary for compatibility
with other devices.
Additional No Connect (N.C.) Connections on HQ304
Package
3/21/96
Note: In XC4025 (no extension) devices in the HQ304
package, P101 is a No Connect (N.C.) pin. P101 is Vcc in
XC4025E/L and XC4028EX/XL devices. Where necessary
for compatibility, this pin can be left unconnected.
I/O - N4 P190 T3 P65 B6 29
I/O P167 P2 P191 U1 P64 A6 32
I/O P168 T1 P192 P4 P63 D8 35
I/O P169 R1 P193 R3 P62 B7 38
I/O P170 N2 P194 N5 P61 A7 41
I/O - - P195 T2 P60 D9 44
I/O - - - R2 P59 C9 47
GND P171 M3 P196 T1 P58 GND* -
I/O P172 P1 P197 N4 P57 B8 50
I/O P173 N1 P198 P3 P56 D10 53
I/O - M4 P199 P2 P55 C10 56
I/O - L4 P200 N3 P54 B9 59
VCC - - P201 R1 P52 VCC* -
I/O - - - M5 P51 A9 62
I/O - - - P1 P50 D11 65
I/O - - - M4 P49 B11 68
I/O - - - N2 P48 A11 71
GND -----GND* -
I/O (A4) P174 M2 P202 N1 P47 D12 74
I/O (A5) P175 M1 P203 M3 P46 C12 77
I/O P176 L3 P205 M2 P45 B12 80
I/O P177 L2 P206 L5 P44 A12 83
I/O (A21) P178 L1 P207 M1 P43 C13 86
I/O (A20) P179 K1 P208 L4 P42 B13 89
I/O (A6) P180 K2 P209 L3 P41 A13 92
I/O (A7) P181 K3 P210 L2 P40 B14 95
GND P182 K4 P211 L1 P39 GND* -
XC4025E,
/28EX/XL
Pad Name
HQ
208 PG
223 HQ
240 PG
299 HQ
304 BG
352 Bndry
Scan
N.C. N.C.
P1 P107
P3 P155
P51 P156
P52 P157
P53 P158
P54 P206
P102 P207
P104 P208
P105
GND
P204
P219
N.C.
P11
P24
P53
P100
P128
P176
P205
P254
P281
June 1, 1996 (Version 1.02) 4-117
Additional No Connect, Vcc & Ground Connections on
BG352 Package
3/21/96
N.C. VCC GND
A18 A10 A1
A24 A17 A2
B4 B2 A5
B10 B25 A8
B23 D7 A14
C1 D13 A19
C5 D19 A22
C8 G23 A25
C11 H4 A26
D1 K1 B1
D16 K26 B26
D25 N23 E1
F23 P4 E26
J26 U1 H1
K2 U26 H26
L4 W23 N1
L23 Y4 P26
T3 AC8 W1
T4 AC14 W26
T24 AC20 AB1
U25 AE2 AB26
AB3 AE25 AE1
AC2 AF10 AE26
AC6 AF17 AF1
AC11 AF2
AC16 AF5
AC21 AF8
AC25 AF13
AD16 AF19
AD21 AF22
AD26 AF25
AE4 AF26
AE10
XC4000 Series Field Programmable Gate Arrays
4-118 June 1, 1996 (Version 1.02)
Pin Locations for XC4036EX/XL Devices
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan
GND P304 GND* GND* -
I/O, GCK1 (A16) P303 H8 D29 218
I/O (A17) P302 F6 C30 221
I/O P301 B4 E28 224
I/O P300 D4 E29 227
I/O, TDI P299 B2 D30 230
I/O, TCK P298 G9 D31 233
I/O - F8 E30 236
I/O - C5 E31 239
I/O P297 A7 G28 242
I/O P296 A5 G29 245
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P295 B8 H28 248
I/O P294 C9 H29 251
I/O P293 E9 G30 254
I/O P292 F12 H30 257
I/O P291 D10 J28 260
I/O P290 B10 J29 263
I/O P289 F10 H31 266
I/O P288 F14 J30 269
GND P287 GND* GND* -
I/O, FCLK1 P286 C11 K28 272
I/O P285 B12 K29 275
I/O, TMS P284 E11 K30 278
I/O P283 E15 K31 281
VCC P282 VCC* VCC* -
I/O P280 F16 L29 284
I/O P279 C13 L30 287
I/O - B14 M29 290
I/O - E17 M31 293
I/O P278 E13 N31 296
I/O P277 A15 N28 299
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P276 B16 P30 302
I/O P275 D16 P28 305
I/O P274 D18 P29 308
I/O P273 A17 R31 311
I/O P272 E19 R30 314
I/O P271 B18 R28 317
I/O P270 C17 R29 320
I/O P269 C19 T31 323
GND P268 GND* GND* -
VCC P267 VCC* VCC* -
I/O P266 F20 T30 326
I/O P265 B20 T29 329
I/O P264 C21 U31 332
I/O P263 B22 U30 335
I/O P262 E21 U28 338
I/O P261 D22 U29 341
I/O P260 A23 V30 344
I/O P259 B24 V29 347
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P258 A25 W30 350
I/O P257 D24 W29 353
I/O - B26 Y30 356
I/O - A27 Y29 359
I/O P256 C27 Y28 362
I/O P255 F24 AA30 365
VCC P253 VCC* VCC* -
I/O P252 E25 AA29 368
I/O P251 E27 AB31 371
I/O P250 B28 AB30 374
I/O, FCLK2 P249 C29 AB29 377
GND P248 GND* GND* -
I/O P247 F26 AB28 380
I/O P246 D28 AC30 383
I/O P245 B30 AC29 386
I/O P244 E29 AC28 389
I/O P243 F28 AD29 392
I/O P242 F30 AD28 395
I/O P241 C31 AE30 398
I/O P240 E31 AE29 401
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P239 B32 AF31 404
I/O P238 A33 AE28 407
I/O P237 A35 AG31 410
I/O P236 F32 AF28 413
I/O - C35 AG30 416
I/O - B38 AG29 419
I/O P235 E33 AH31 422
I/O P234 G31 AG28 425
I/O P233 H32 AH30 428
I/O, GCK2 P232 B36 AJ30 431
O (M1) P231 A39 AH29 434
GND P230 GND* GND* -
I (M0) P229 E35 AH28 437
VCC P228 VCC* VCC* -
I (M2) P227 G33 AJ28 438
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan
June 1, 1996 (Version 1.02) 4-119
I/O, GCK3 P226 D36 AK29 439
I/O (HDC) P225 C37 AH27 442
I/O P224 F34 AK28 445
I/O P223 J33 AJ27 448
I/O P222 D38 AL28 451
I/O (LDC) P221 G35 AH26 454
I/O - E39 AL27 457
I/O - K34 AH25 460
I/O P220 F38 AK26 463
I/O P219 G37 AL26 466
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P218 H38 AH24 469
I/O P217 J37 AJ25 472
I/O P216 G39 AK25 475
I/O P215 M34 AJ24 478
I/O P214 N35 AL24 481
I/O P213 P34 AH22 484
I/O P212 J35 AJ23 487
I/O P211 L37 AK23 490
GND P210 GND* GND* -
I/O P209 M38 AJ22 493
I/O P208 R35 AK22 496
I/O P207 H36 AL22 499
I/O P206 T34 AJ21 502
VCC P204 VCC* VCC* -
I/O P203 N37 AH20 505
I/O P202 N39 AK21 508
I/O - U35 AK20 511
I/O - R39 AJ19 514
I/O P201 M36 AL20 517
I/O P200 V34 AH18 520
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P199 R37 AK19 523
I/O P198 T38 AJ18 526
I/O P197 T36 AL19 529
I/O P196 V36 AK18 532
I/O P195 U37 AH17 535
I/O P194 U39 AJ17 538
I/O P193 V38 AJ16 541
I/O (INIT) P192 W37 AK16 544
VCC P191 VCC* VCC* -
GND P190 GND* GND* -
I/O P189 Y34 AL16 547
I/O P188 AC37 AH15 550
I/O P187 AB38 AK15 553
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan I/O P186 AD36 AJ14 556
I/O P185 AA35 AH14 559
I/O P184 AE37 AK14 562
I/O P183 AB36 AL13 565
I/O P182 AD38 AK13 568
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P181 AB34 AJ13 571
I/O P180 AE39 AH13 574
I/O - AM36 AL12 577
I/O - AC35 AK12 580
I/O P179 AG39 AH12 583
I/O P178 AG37 AJ11 586
VCC P177 VCC* VCC* -
I/O P175 AD34 AL10 589
I/O P174 AN39 AK10 592
I/O P173 AE35 AJ10 595
I/O P172 AH38 AK9 598
GND P171 GND* GND* -
I/O P170 AJ37 AL8 601
I/O P169 AG35 AH10 604
I/O P168 AF34 AJ9 607
I/O P167 AH36 AK8 610
I/O P166 AK36 AK7 613
I/O P165 AM34 AL6 616
I/O P164 AH34 AJ7 619
I/O P163 AJ35 AH8 622
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P162 AL37 AK6 625
I/O P161 AT38 AL5 628
I/O P160 AM38 AH7 631
I/O P159 AN37 AJ6 634
I/O - AK34 AK5 637
I/O - AR39 AL4 640
I/O P158 AN35 AK4 643
I/O P157 AL33 AH5 646
I/O P156 AV38 AK3 649
I/O, GCK4 P155 AT36 AJ4 652
GND P154 GND* GND* -
DONE P153 AR35 AH4 -
VCC P152 VCC* VCC* -
PROGRAM P151 AN33 AH3 -
I/O (D7) P150 AM32 AJ2 655
I/O, GCK5 P149 AP34 AG4 658
I/O P148 AW39 AG3 661
I/O P147 AN31 AH2 664
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-120 June 1, 1996 (Version 1.02)
I/O - AV36 AH1 667
I/O - AR33 AF4 670
I/O P146 AP32 AF3 673
I/O P145 AU35 AG2 676
I/O P144 AW33 AE3 679
I/O P143 AU33 AF2 682
VCC - VCC* VCC* -
GND - GND* GND* -
I/O (D6) P142 AV32 AF1 685
I/O P141 AU31 AD4 688
I/O P140 AR31 AD3 691
I/O P139 AP28 AE2 694
I/O P138 AT32 AC3 697
I/O P137 AV30 AD1 700
I/O P136 AR29 AC2 703
I/O P135 AP26 AB4 706
GND P134 GND* GND* -
I/O P133 AU29 AB3 709
I/O P132 AV28 AB2 712
I/O, FCLK3 P131 AT28 AB1 715
I/O P130 AR25 AA3 718
VCC P129 VCC* VCC* -
I/O (D5) P127 AP24 AA2 721
I/O (CS0) P126 AU27 Y2 724
I/O - AR27 Y4 727
I/O - AW27 Y3 730
I/O P125 AT24 W4 733
I/O P124 AR23 W3 736
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P123 AP22 V4 739
I/O P122 AV24 V3 742
I/O P121 AU23 U1 745
I/O P120 AT22 U2 748
I/O P119 AR21 U4 751
I/O P118 AV22 U3 754
I/O (D4) P117 AP20 T1 757
I/O P116 AU21 T2 760
VCC P115 VCC* VCC* -
GND P114 GND* GND* -
I/O (D3) P113 AU19 T3 763
I/O (RS) P112 AV20 R1 766
I/O P111 AV18 R2 769
I/O P110 AR19 R4 772
I/O P109 AT18 R3 775
I/O P108 AW17 P2 778
I/O P107 AV16 P3 781
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan I/O P106 AP18 P4 784
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P105 AR17 N3 787
I/O P104 AT16 N4 790
I/O - AV14 M1 793
I/O - AW13 M2 796
I/O (D2) P103 AR15 L2 799
I/O P102 AP16 L3 802
VCC P101 VCC* VCC* -
I/O P99 AV12 K1 805
I/O, FCLK4 P98 AR13 K2 808
I/O P97 AU11 K3 811
I/O P96 AT12 K4 814
GND P95 GND* GND* -
I/O P94 AP14 J2 817
I/O P93 AR11 J3 820
I/O P92 AV10 J4 823
I/O P91 AT8 H1 826
I/O P90 AT10 H2 829
I/O P89 AP10 H3 832
I/O P88 AP12 H4 835
I/O P87 AR9 G2 838
GND - GND* GND* -
VCC - VCC* VCC* -
I/O (D1) P86 AU7 G4 841
I/O (RCLK,
RDY/BUSY) P85 AW7 F2 844
I/O - AW5 F3 847
I/O - AV6 E1 850
I/O P84 AR7 E3 853
I/O P83 AV4 D1 856
I/O P82 AN9 E4 859
I/O P81 AW1 D2 862
I/O (D0, DIN) P80 AP6 C2 865
I/O, GCK6 (DOUT) P79 AU3 D3 868
CCLK P78 AR5 D4 -
VCC P77 VCC* VCC* -
O, TDO P76 AN7 C4 0
GND P75 GND* GND* -
I/O (A0, WS) P74 AT4 B3 2
I/O, GCK7 (A1) P73 AV2 D5 5
I/O P72 AM8 B4 8
I/O P71 AL7 C5 11
I/O - AR3 B5 14
I/O - AR1 C6 17
I/O (CS1, A2) P70 AK6 A5 20
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan
June 1, 1996 (Version 1.02) 4-121
4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the associated package. They have no direct con-
nection to any package pin.
I/O (A3) P69 AN3 D7 23
I/O P68 AM6 B6 26
I/O P67 AM2 A6 29
VCC - VCC* VCC* -
GND - GND* GND* -
I/O P66 AL3 D8 32
I/O P65 AH6 C7 35
I/O P64 AP2 B7 38
I/O P63 AK4 D9 41
I/O P62 AG5 D10 44
I/O P61 AF6 C9 47
I/O P60 AL5 B9 50
I/O P59 AJ3 C10 53
GND P58 GND* GND* -
I/O P57 AH2 B10 56
I/O P56 AE5 A10 59
I/O P55 AM4 C11 62
I/O P54 AD6 D12 65
VCC P52 VCC* VCC* -
I/O P51 AG3 B11 68
I/O P50 AG1 C12 71
I/O - AC5 C13 74
I/O - AE1 A12 77
I/O P49 AH4 D14 80
I/O P48 AB6 B13 83
GND - GND* GND* -
VCC - VCC* VCC* -
I/O (A4) P47 AD2 C14 86
I/O (A5) P46 AB4 A13 89
I/O P45 AE3 B14 92
I/O P44 AC1 D15 95
I/O (A21) P43 AD4 C15 98
I/O (A20) P42 AA5 B15 101
I/O (A6) P41 AA3 B16 104
I/O (A7) P40 Y6 A16 107
GND P39 GND* GND* -
VCC P38 VCC* VCC* -
I/O (A8) P37 W3 D17 110
I/O (A9) P36 Y2 A17 113
I/O (A19) P35 V4 C18 116
I/O (A18) P34 T2 D18 119
I/O P33 U1 B18 122
I/O P32 V6 A19 125
I/O (A10) P31 U3 B19 128
I/O (A11) P30 R1 C19 131
VCC - VCC* VCC* -
GND - GND* GND* -
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan I/O P29 U5 D19 134
I/O P28 T4 A20 137
I/O - P2 B20 140
I/O - N1 C20 143
I/O P27 R5 C21 146
I/O P26 M2 A22 149
VCC P25 VCC* VCC* -
I/O P23 L3 B22 152
I/O P22 T6 C22 155
I/O P21 N5 B23 158
I/O P20 M4 A24 161
GND P19 GND* GND* -
I/O P18 K2 D22 164
I/O P17 K4 C23 167
I/O P16 P6 B24 170
I/O P15 M6 C24 173
I/O P14 J3 A26 176
I/O P13 H2 C25 179
I/O (A12) P12 H4 D24 182
I/O (A13) P10 G3 B26 185
GND - GND* GND* -
VCC - VCC* VCC* -
I/O P9 K6 A27 188
I/O P8 G1 D25 191
I/O - E1 C26 194
I/O - E3 B27 197
I/O P7 J7 C27 200
I/O P6 H6 B28 203
I/O P5 C3 D27 206
I/O P4 D2 B29 209
I/O (A14) P3 E5 C28 212
I/O, GCK8 (A15) P2 G7 D28 215
VCC P1 VCC* VCC* -
XC4036EX/XL
Pad Name HQ304 PG411 BG432 Bndry
Scan
XC4000 Series Field Programmable Gate Arrays
4-122 June 1, 1996 (Version 1.02)
Additional No Connect (N.C.) Connections on HQ304
Package
3/22/96
Additional No Connect, Vcc & Ground Connections on
PG411 Package
3/26/96
Additional No Connect, Vcc & Ground Connections on
BG432 Package
3/22/96
N.C. N.C.
P11 P176
P24 P205
P53 P254
P100 P281
P128
N.C. N.C. VCC GND
A13 AA37 A3 A9
B6 AB2 A11 A19
B34 AC3 A21 A29
C7 AC39 A31 A37
C15 AF2 C39 C1
C23 AF38 D6 D14
C25 AJ5 F36 D20
C33 AK2 J1 D26
D8 AK38 L39 D34
D12 AL35 W1 F4
D30 AN1 AA39 J39
D32 AN5 AJ1 L1
E7 AP8 AL39 P4
E23 AP30 AP4 P36
E37 AP38 AT34 W39
F2 AR37 AU1 Y4
F18 AT2 AW9 Y36
F22 AT30 AW19 AA1
G5 AU5 AW29 AF4
H34 AU9 AW37 AF36
J5 AU13 AJ39
K36 AU15 AL1
K38 AU17 AP36
L5 AU25 AT6
L35 AU37 AT14
N3 AV8 AT20
P38 AV26 AT26
R3 AV34 AU39
V2 AW15 AW3
W5 AW23 AW11
W35 AW25 AW21
Y38 AW35 AW31
N.C. N.C. VCC GND
A4 AG1 A1 A2
A8 AH6 A11 A3
A15 AH9 A21 A7
A28 AH19 A31 A9
B8 AH23 C3 A14
B12 AJ5 C29 A18
B17 AJ8 D11 A23
B21 AJ12 D21 A25
B25 AJ15 L1 A29
C8 AJ20 L4 A30
C16 AJ26 L28 B1
C17 AK11 L31 B2
D6 AK17 AA1 B30
D13 AK24 AA4 B31
D20 AK27 AA28 C1
D23 AL15 AA31 C31
D26 AL17 AH11 D16
E2 AH21 G1
F1 AJ3 G31
F4 AJ29 J1
F28 AL1 J31
F29 AL11 P1
F30 AL21 P31
F31 AL31 T4
G3 T28
M3 V1
M4 V31
M28 AC1
M30 AC31
N1 AE1
N2 AE31
N29 AH16
N30 AJ1
V2 AJ31
V28 AK1
W1 AK2
W2 AK30
W28 AK31
W31 AL2
Y1 AL3
Y31 AL7
AC4 AL9
AD2 AL14
AD30 AL18
AD31 AL23
AE4 AL25
AF29 AL29
AF30 AL30
June 1, 1996 (Version 1.02) 4-123
Pin Locations for XC4044EX/XL Devices
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
GND GND* GND* -
I/O, GCK1 (A16) H8 D29 242
I/O (A17) F6 C30 245
I/O B4 E28 248
I/O D4 E29 251
I/O, TDI B2 D30 254
I/O, TCK G9 D31 257
I/O F8 E30 260
I/O C5 E31 263
I/O A7 G28 266
I/O A5 G29 269
VCC VCC* VCC* -
GND GND* GND* -
I/O C7 F30 272
I/O D8 F31 275
I/O B8 H28 278
I/O C9 H29 281
I/O E9 G30 284
I/O F12 H30 287
I/O D10 J28 290
I/O B10 J29 293
I/O F10 H31 296
I/O F14 J30 299
GND GND* GND* -
I/O, FCLK1 C11 K28 302
I/O B12 K29 305
I/O, TMS E11 K30 308
I/O E15 K31 311
VCC VCC* VCC* -
I/O F16 L29 314
I/O C13 L30 317
I/O B14 M29 320
I/O E17 M31 323
I/O E13 N31 326
I/O A15 N28 329
GND GND* GND* -
VCC VCC* VCC* -
I/O F18 N29 332
I/O C15 N30 335
I/O B16 P30 338
I/O D16 P28 341
I/O D18 P29 344
I/O A17 R31 347
I/O E19 R30 350
I/O B18 R28 353
I/O C17 R29 356
I/O C19 T31 359
GND GND* GND* -
VCC VCC* VCC* -
I/O F20 T30 362
I/O B20 T29 365
I/O C21 U31 368
I/O B22 U30 371
I/O E21 U28 374
I/O D22 U29 377
I/O A23 V30 380
I/O B24 V29 383
I/O C23 V28 386
I/O F22 W31 389
VCC VCC* VCC* -
GND GND* GND* -
I/O A25 W30 392
I/O D24 W29 395
I/O B26 Y30 398
I/O A27 Y29 401
I/O C27 Y28 404
I/O F24 AA30 407
VCC VCC* VCC* -
I/O E25 AA29 410
I/O E27 AB31 413
I/O B28 AB30 416
I/O, FCLK2 C29 AB29 419
GND GND* GND* -
I/O F26 AB28 422
I/O D28 AC30 425
I/O B30 AC29 428
I/O E29 AC28 431
I/O D30 AD31 434
I/O D32 AD30 437
I/O F28 AD29 440
I/O F30 AD28 443
I/O C31 AE30 446
I/O E31 AE29 449
GND GND* GND* -
VCC VCC* VCC* -
I/O B32 AF31 452
I/O A33 AE28 455
I/O A35 AG31 458
I/O F32 AF28 461
I/O C35 AG30 464
I/O B38 AG29 467
I/O E33 AH31 470
I/O G31 AG28 473
I/O H32 AH30 476
I/O, GCK2 B36 AJ30 479
O (M1) A39 AH29 482
GND GND* GND* -
I (M0) E35 AH28 485
VCC VCC* VCC* -
I (M2) G33 AJ28 486
I/O, GCK3 D36 AK29 487
I/O (HDC) C37 AH27 490
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
XC4000 Series Field Programmable Gate Arrays
4-124 June 1, 1996 (Version 1.02)
I/O F34 AK28 493
I/O J33 AJ27 496
I/O D38 AL28 499
I/O (LDC) G35 AH26 502
I/O E39 AL27 505
I/O K34 AH25 508
I/O F38 AK26 511
I/O G37 AL26 514
VCC VCC* VCC* -
GND GND* GND* -
I/O H38 AH24 517
I/O J37 AJ25 520
I/O G39 AK25 523
I/O M34 AJ24 526
I/O K36 AH23 529
I/O K38 AK24 532
I/O N35 AL24 535
I/O P34 AH22 538
I/O J35 AJ23 541
I/O L37 AK23 544
GND GND* GND* -
I/O M38 AJ22 547
I/O R35 AK22 550
I/O H36 AL22 553
I/O T34 AJ21 556
VCC VCC* VCC* -
I/O N37 AH20 559
I/O N39 AK21 562
I/O U35 AK20 565
I/O R39 AJ19 568
I/O M36 AL20 571
I/O V34 AH18 574
GND GND* GND* -
VCC VCC* VCC* -
I/O R37 AK19 577
I/O T38 AJ18 580
I/O T36 AL19 583
I/O V36 AK18 586
I/O U37 AH17 589
I/O U39 AJ17 592
I/O W35 AK17 595
I/O AC39 AL17 598
I/O V38 AJ16 601
I/O (INIT) W37 AK16 604
VCC VCC* VCC* -
GND GND* GND* -
I/O Y34 AL16 607
I/O AC37 AH15 610
I/O Y38 AL15 613
I/O AA37 AJ15 616
I/O AB38 AK15 619
I/O AD36 AJ14 622
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
I/O AA35 AH14 625
I/O AE37 AK14 628
I/O AB36 AL13 631
I/O AD38 AK13 634
VCC VCC* VCC* -
GND GND* GND* -
I/O AB34 AJ13 637
I/O AE39 AH13 640
I/O AM36 AL12 643
I/O AC35 AK12 646
I/O AG39 AH12 649
I/O AG37 AJ11 652
VCC VCC* VCC* -
I/O AD34 AL10 655
I/O AN39 AK10 658
I/O AE35 AJ10 661
I/O AH38 AK9 664
GND GND* GND* -
I/O AJ37 AL8 667
I/O AG35 AH10 670
I/O AF34 AJ9 673
I/O AH36 AK8 676
I/O AK38 AJ8 679
I/O AP38 AH9 682
I/O AK36 AK7 685
I/O AM34 AL6 688
I/O AH34 AJ7 691
I/O AJ35 AH8 694
GND GND* GND* -
VCC VCC* VCC* -
I/O AL37 AK6 697
I/O AT38 AL5 700
I/O AM38 AH7 703
I/O AN37 AJ6 706
I/O AK34 AK5 709
I/O AR39 AL4 712
I/O AN35 AK4 715
I/O AL33 AH5 718
I/O AV38 AK3 721
I/O, GCK4 AT36 AJ4 724
GND GND* GND* -
DONE AR35 AH4 -
VCC VCC* VCC* -
PROGRAM AN33 AH3 -
I/O (D7) AM32 AJ2 727
I/O, GCK5 AP34 AG4 730
I/O AW39 AG3 733
I/O AN31 AH2 736
I/O AV36 AH1 739
I/O AR33 AF4 742
I/O AP32 AF3 745
I/O AU35 AG2 748
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
June 1, 1996 (Version 1.02) 4-125
I/O AW33 AE3 751
I/O AU33 AF2 754
VCC VCC* VCC* -
GND GND* GND* -
I/O (D6) AV32 AF1 757
I/O AU31 AD4 760
I/O AR31 AD3 763
I/O AP28 AE2 766
I/O AP30 AD2 769
I/O AT30 AC4 772
I/O AT32 AC3 775
I/O AV30 AD1 778
I/O AR29 AC2 781
I/O AP26 AB4 784
GND GND* GND* -
I/O AU29 AB3 787
I/O AV28 AB2 790
I/O, FCLK3 AT28 AB1 793
I/O AR25 AA3 796
VCC VCC* VCC* -
I/O (D5) AP24 AA2 799
I/O (CS0) AU27 Y2 802
I/O AR27 Y4 805
I/O AW27 Y3 808
I/O AT24 W4 811
I/O AR23 W3 814
GND GND* GND* -
VCC VCC* VCC* -
I/O AW25 W2 817
I/O AW23 V2 820
I/O AP22 V4 823
I/O AV24 V3 826
I/O AU23 U1 829
I/O AT22 U2 832
I/O AR21 U4 835
I/O AV22 U3 838
I/O (D4) AP20 T1 841
I/O AU21 T2 844
VCC VCC* VCC* -
GND GND* GND* -
I/O (D3) AU19 T3 847
I/O (RS) AV20 R1 850
I/O AV18 R2 853
I/O AR19 R4 856
I/O AT18 R3 859
I/O AW17 P2 862
I/O AV16 P3 865
I/O AP18 P4 868
I/O AU17 N1 871
I/O AW15 N2 874
VCC VCC* VCC* -
GND GND* GND* -
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
I/O AR17 N3 877
I/O AT16 N4 880
I/O AV14 M1 883
I/O AW13 M2 886
I/O (D2) AR15 L2 889
I/O AP16 L3 892
VCC VCC* VCC* -
I/O AV12 K1 895
I/O, FCLK4 AR13 K2 898
I/O AU11 K3 901
I/O AT12 K4 904
GND GND* GND* -
I/O AP14 J2 907
I/O AR11 J3 910
I/O AV10 J4 913
I/O AT8 H1 916
I/O AT10 H2 919
I/O AP10 H3 922
I/O AP12 H4 925
I/O AR9 G2 928
I/O AU9 G3 931
I/O AV8 F1 934
GND GND* GND* -
VCC VCC* VCC* -
I/O (D1) AU7 G4 937
I/O (RCLK,
RDY/BUSY) AW7 F2 940
I/O AW5 F3 943
I/O AV6 E1 946
I/O AR7 E3 949
I/O AV4 D1 952
I/O AN9 E4 955
I/O AW1 D2 958
I/O (D0, DIN) AP6 C2 961
I/O, GCK6
(DOUT) AU3 D3 964
CCLK AR5 D4 -
VCC VCC* VCC* -
O, TDO AN7 C4 0
GND GND* GND* -
I/O (A0, WS) AT4 B3 2
I/O, GCK7 (A1) AV2 D5 5
I/O AM8 B4 8
I/O AL7 C5 11
I/O AR3 B5 14
I/O AR1 C6 17
I/O (CS1, A2) AK6 A5 20
I/O (A3) AN3 D7 23
I/O AM6 B6 26
I/O AM2 A6 29
VCC VCC* VCC* -
GND GND* GND* -
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
XC4000 Series Field Programmable Gate Arrays
4-126 June 1, 1996 (Version 1.02)
4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the associated package. They have no direct con-
nection to any package pin.
I/O AL3 D8 32
I/O AH6 C7 35
I/O AP2 B7 38
I/O AK4 D9 41
I/O AN1 B8 44
I/O AK2 A8 47
I/O AG5 D10 50
I/O AF6 C9 53
I/O AL5 B9 56
I/O AJ3 C10 59
GND GND* GND* -
I/O AH2 B10 62
I/O AE5 A10 65
I/O AM4 C11 68
I/O AD6 D12 71
VCC VCC* VCC* -
I/O AG3 B11 74
I/O AG1 C12 77
I/O AC5 C13 80
I/O AE1 A12 83
I/O AH4 D14 86
I/O AB6 B13 89
GND GND* GND* -
VCC VCC* VCC* -
I/O (A4) AD2 C14 92
I/O (A5) AB4 A13 95
I/O AE3 B14 98
I/O AC1 D15 101
I/O (A21) AD4 C15 104
I/O (A20) AA5 B15 107
I/O AB2 A15 110
I/O AC3 C16 113
I/O (A6) AA3 B16 116
I/O (A7) Y6 A16 119
GND GND* GND* -
VCC VCC* VCC* -
I/O (A8) W3 D17 122
I/O (A9) Y2 A17 125
I/O V2 C17 128
I/O W5 B17 131
I/O (A19) V4 C18 134
I/O (A18) T2 D18 137
I/O U1 B18 140
I/O V6 A19 143
I/O (A10) U3 B19 146
I/O (A11) R1 C19 149
VCC VCC* VCC* -
GND GND* GND* -
I/O U5 D19 152
I/O T4 A20 155
I/O P2 B20 158
I/O N1 C20 161
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
I/O R5 C21 164
I/O M2 A22 167
VCC VCC* VCC* -
I/O L3 B22 170
I/O T6 C22 173
I/O N5 B23 176
I/O M4 A24 179
GND GND* GND* -
I/O K2 D22 182
I/O K4 C23 185
I/O P6 B24 188
I/O M6 C24 191
I/O L5 D23 194
I/O J5 B25 197
I/O J3 A26 200
I/O H2 C25 203
I/O (A12) H4 D24 206
I/O (A13) G3 B26 209
GND GND* GND* -
VCC VCC* VCC* -
I/O K6 A27 212
I/O G1 D25 215
I/O E1 C26 218
I/O E3 B27 221
I/O J7 C27 224
I/O H6 B28 227
I/O C3 D27 230
I/O D2 B29 233
I/O (A14) E5 C28 236
I/O, GCK8 (A15) G7 D28 239
VCC VCC* VCC* -
XC4044EX/XL
Pad Name PG411 BG432 Bndry Scan
June 1, 1996 (Version 1.02) 4-127
Additional No Connect, Vcc & Ground Connections on
PG411 Package
3/22/96
Additional No Connect, Vcc & Ground Connections on
BG432 Package
3/26/96
N.C. VCC GND
A13 A3 A9
B6 A11 A19
B34 A21 A29
C25 A31 A37
C33 C39 C1
D12 D6 D14
E7 F36 D20
E23 J1 D26
E37 L39 D34
F2 W1 F4
G5 AA39 J39
H34 AJ1 L1
L35 AL39 P4
N3 AP4 P36
P38 AT34 W39
R3 AU1 Y4
AF2 AW9 Y36
AF38 AW19 AA1
AJ5 AW29 AF4
AL35 AW37 AF36
AN5 AJ39
AP8 AL1
AR37 AP36
AT2 AT6
AU5 AT14
AU13 AT20
AU15 AT26
AU25 AU39
AU37 AW3
AV26 AW11
AV34 AW21
AW35 AW31
N.C. VCC GND
A4 A1 A2
A28 A11 A3
B12 A21 A7
B21 A31 A9
C8 C3 A14
D6 C29 A18
D13 D11 A23
D20 D21 A25
D26 L1 A29
E2 L4 A30
F4 L28 B1
F28 L31 B2
F29 AA1 B30
M3 AA4 B31
M4 AA28 C1
M28 AA31 C31
M30 AH11 D16
W1 AH21 G1
W28 AJ3 G31
Y1 AJ29 J1
Y31 AL1 J31
AE4 AL11 P1
AF29 AL21 P31
AF30 AL31 T4
AG1 T28
AH6 V1
AH19 V31
AJ5 AC1
AJ12 AC31
AJ20 AE1
AJ26 AE31
AK11 AH16
AK27 AJ1
AJ31
AK1
AK2
AK30
AK31
AL2
AL3
AL7
AL9
AL14
AL18
AL23
AL25
AL29
AL30
XC4000 Series Field Programmable Gate Arrays
4-128 June 1, 1996 (Version 1.02)
Pin Locations for XC4052XL Devices
XC4052XL Pad Name BG432 Bndry Scan
GND GND* -
I/O, GCK1 (A16) D29 266
I/O (A17) C30 269
I/O E28 272
I/O E29 275
I/O, TDI D30 278
I/O, TCK D31 281
GND GND* -
I/O F28 284
I/O F29 287
I/O E30 290
I/O E31 293
I/O G28 296
I/O G29 299
VCC VCC* -
GND GND* -
I/O F30 302
I/O F31 305
I/O H28 308
I/O H29 311
I/O G30 314
I/O H30 317
GND GND* -
I/O J28 320
I/O J29 323
I/O H31 326
I/O J30 329
GND GND* -
I/O, FCLK1 K28 332
I/O K29 335
I/O, TMS K30 338
I/O K31 341
VCC VCC* -
I/O L29 344
I/O L30 347
GND GND* -
I/O M30 350
I/O M28 353
I/O M29 356
I/O M31 359
I/O N31 362
I/O N28 365
GND GND* -
VCC VCC* -
I/O N29 368
I/O N30 371
I/O P30 374
I/O P28 377
I/O P29 380
I/O R31 383
GND GND* -
I/O R30 386
I/O R28 389
I/O R29 392
I/O T31 395
GND GND* -
VCC VCC* -
I/O T30 398
I/O T29 401
I/O U31 404
I/O U30 407
GND GND* -
I/O U28 410
I/O U29 413
I/O V30 416
I/O V29 419
I/O V28 422
I/O W31 425
VCC VCC* -
GND GND* -
I/O W30 428
I/O W29 431
I/O W28 434
I/O Y31 437
I/O Y30 440
I/O Y29 443
GND GND* -
I/O Y28 446
I/O AA30 449
VCC VCC* -
I/O AA29 452
I/O AB31 455
I/O AB30 458
I/O, FCLK2 AB29 461
GND GND* -
I/O AB28 464
I/O AC30 467
I/O AC29 470
I/O AC28 473
GND GND* -
I/O AD31 476
I/O AD30 479
I/O AD29 482
I/O AD28 485
I/O AE30 488
I/O AE29 491
GND GND* -
VCC VCC* -
I/O AF31 494
I/O AE28 497
I/O AF30 500
I/O AF29 503
I/O AG31 506
XC4052XL Pad Name BG432 Bndry Scan
June 1, 1996 (Version 1.02) 4-129
I/O AF28 509
GND GND* -
I/O AG30 512
I/O AG29 515
I/O AH31 518
I/O AG28 521
I/O AH30 524
I/O, GCK2 AJ30 527
O (M1) AH29 530
GND GND* -
I (M0) AH28 533
VCC VCC* -
I (M2) AJ28 534
I/O, GCK3 AK29 535
I/O (HDC) AH27 538
I/O AK28 541
I/O AJ27 544
I/O AL28 547
I/O (LDC) AH26 550
GND GND* -
I/O AK27 553
I/O AJ26 556
I/O AL27 559
I/O AH25 562
I/O AK26 565
I/O AL26 568
VCC VCC* -
GND GND* -
I/O AH24 571
I/O AJ25 574
I/O AK25 577
I/O AJ24 580
I/O AH23 583
I/O AK24 586
GND GND* -
I/O AL24 589
I/O AH22 592
I/O AJ23 595
I/O AK23 598
GND GND* -
I/O AJ22 601
I/O AK22 604
I/O AL22 607
I/O AJ21 610
VCC VCC* -
I/O AH20 613
I/O AK21 616
GND GND* -
I/O AJ20 619
I/O AH19 622
I/O AK20 625
I/O AJ19 628
XC4052XL Pad Name BG432 Bndry Scan I/O AL20 631
I/O AH18 634
GND GND* -
VCC VCC* -
I/O AK19 637
I/O AJ18 640
I/O AL19 643
I/O AK18 646
I/O AH17 649
I/O AJ17 652
GND GND* -
I/O AK17 655
I/O AL17 658
I/O AJ16 661
I/O (INIT) AK16 664
VCC VCC* -
GND GND* -
I/O AL16 667
I/O AH15 670
I/O AL15 673
I/O AJ15 676
GND GND* -
I/O AK15 679
I/O AJ14 682
I/O AH14 685
I/O AK14 688
I/O AL13 691
I/O AK13 694
VCC VCC* -
GND GND* 697
I/O AJ13 700
I/O AH13 703
I/O AL12 706
I/O AK12 709
I/O AJ12 712
I/O AK11 715
GND GND* -
I/O AH12 718
I/O AJ11 721
VCC VCC* -
I/O AL10 724
I/O AK10 727
I/O AJ10 730
I/O AK9 733
GND GND* -
I/O AL8 736
I/O AH10 739
I/O AJ9 742
I/O AK8 745
GND GND* -
I/O AJ8 748
I/O AH9 751
XC4052XL Pad Name BG432 Bndry Scan
XC4000 Series Field Programmable Gate Arrays
4-130 June 1, 1996 (Version 1.02)
I/O AK7 754
I/O AL6 757
I/O AJ7 760
I/O AH8 763
GND GND* -
VCC VCC* -
I/O AK6 766
I/O AL5 769
I/O AH7 772
I/O AJ6 775
I/O AK5 778
I/O AL4 781
GND GND* -
I/O AH6 784
I/O AJ5 787
I/O AK4 790
I/O AH5 793
I/O AK3 796
I/O, GCK4 AJ4 799
GND GND* -
DONE AH4 -
VCC VCC* -
PROGRAM AH3 -
I/O (D7) AJ2 802
I/O, GCK5 AG4 805
I/O AG3 808
I/O AH2 811
I/O AH1 814
I/O AF4 817
GND GND* -
I/O AF3 820
I/O AG2 823
I/O AG1 826
I/O AE4 829
I/O AE3 832
I/O AF2 835
VCC VCC* -
GND GND* -
I/O (D6) AF1 838
I/O AD4 841
I/O AD3 844
I/O AE2 847
I/O AD2 850
I/O AC4 853
GND GND* -
I/O AC3 856
I/O AD1 859
I/O AC2 862
I/O AB4 865
GND GND* -
I/O AB3 868
I/O AB2 871
XC4052XL Pad Name BG432 Bndry Scan I/O, FCLK3 AB1 874
I/O AA3 877
VCC VCC* -
I/O (D5) AA2 880
I/O (CS0) Y2 883
GND GND* -
I/O Y4 886
I/O Y3 889
I/O Y1 892
I/O W1 895
I/O W4 898
I/O W3 901
GND GND* -
VCC VCC* -
I/O W2 904
I/O V2 907
I/O V4 910
I/O V3 913
I/O U1 916
I/O U2 919
GND GND* -
I/O U4 922
I/O U3 925
I/O (D4) T1 928
I/O T2 931
VCC VCC* -
GND GND* -
I/O (D3) T3 934
I/O (RS) R1 937
I/O R2 940
I/O R4 943
GND GND* -
I/O R3 946
I/O P2 949
I/O P3 952
I/O P4 955
I/O N1 958
I/O N2 961
VCC VCC* -
GND GND* -
I/O N3 964
I/O N4 967
I/O M1 970
I/O M2 973
I/O M3 976
I/O M4 979
GND GND* -
I/O (D2) L2 982
I/O L3 985
VCC VCC* -
I/O K1 988
I/O, FCLK4 K2 991
XC4052XL Pad Name BG432 Bndry Scan
June 1, 1996 (Version 1.02) 4-131
I/O K3 994
I/O K4 997
GND GND* -
I/O J2 1000
I/O J3 1003
I/O J4 1006
I/O H1 1009
GND GND* -
I/O H2 1012
I/O H3 1015
I/O H4 1018
I/O G2 1021
I/O G3 1024
I/O F1 1027
GND GND* -
VCC VCC* -
I/O (D1) G4 1030
I/O (RCLK, RDY/BUSY) F2 1033
I/O F3 1036
I/O E1 1039
I/O F4 1042
I/O E2 1045
GND GND* -
I/O E3 1048
I/O D1 1051
I/O E4 1054
I/O D2 1057
I/O (D0, DIN) C2 1060
I/O, GCK6 (DOUT) D3 1063
CCLK D4 -
VCC VCC* -
O, TDO C4 0
GND GND* -
I/O (A0, WS)B32
I/O, GCK7 (A1) D5 5
I/O B4 8
I/O C5 11
I/O A4 14
I/O D6 17
GND GND* -
I/O B5 20
I/O C6 23
I/O (CS1, A2) A5 26
I/O (A3) D7 29
I/O B6 32
I/O A6 35
VCC VCC* -
GND GND* -
I/O D8 38
I/O C7 41
I/O B7 44
I/O D9 47
XC4052XL Pad Name BG432 Bndry Scan I/O B8 50
I/O A8 53
GND GND* -
I/O D10 56
I/O C9 59
I/O B9 62
I/O C10 65
GND GND* -
I/O B10 68
I/O A10 71
I/O C11 74
I/O D12 77
VCC VCC* -
I/O B11 80
I/O C12 83
GND GND* -
I/O D13 86
I/O B12 89
I/O C13 92
I/O A12 95
I/O D14 98
I/O B13 101
GND GND* -
VCC VCC* -
I/O (A4) C14 104
I/O (A5) A13 107
I/O B14 110
I/O D15 113
I/O (A21) C15 116
I/O (A20) B15 119
GND GND* -
I/O A15 122
I/O C16 125
I/O (A6) B16 128
I/O (A7) A16 131
GND GND* -
VCC VCC* -
I/O (A8) D17 134
I/O (A9) A17 137
I/O C17 140
I/O B17 143
GND GND* -
I/O (A19) C18 146
I/O (A18) D18 149
I/O B18 152
I/O A19 155
I/O (A10) B19 158
I/O (A11) C19 161
VCC VCC* -
GND GND* -
I/O D19 164
I/O A20 167
XC4052XL Pad Name BG432 Bndry Scan
XC4000 Series Field Programmable Gate Arrays
4-132 June 1, 1996 (Version 1.02)
4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the associated package. They have no direct con-
nection to any package pin.
Additional No Connect, Vcc & Ground Connections on
BG432 Package
3/22/96
I/O B20 170
I/O C20 173
I/O B21 176
I/O D20 179
GND GND* -
I/O C21 182
I/O A22 185
VCC VCC* -
I/O B22 188
I/O C22 191
I/O B23 194
I/O A24 197
GND GND* -
I/O D22 200
I/O C23 203
I/O B24 206
I/O C24 209
GND GND* -
I/O D23 212
I/O B25 215
I/O A26 218
I/O C25 221
I/O (A12) D24 224
I/O (A13) B26 227
GND GND* -
VCC VCC* -
I/O A27 230
I/O D25 233
I/O C26 236
I/O B27 239
I/O A28 242
I/O D26 245
GND GND* -
I/O C27 248
I/O B28 251
I/O D27 254
I/O B29 257
I/O (A14) C28 260
I/O, GCK8 (A15) D28 263
VCC VCC* -
XC4052XL Pad Name BG432 Bndry Scan
N.C. VCC GND
C8 A1 A2
A11 A3
A21 A7
A31 A9
C3 A14
C29 A18
D11 A23
D21 A25
L1 A29
L4 A30
L28 B1
L31 B2
AA1 B30
AA4 B31
AA28 C1
AA31 C31
AH11 D16
AH21 G1
AJ3 G31
AJ29 J1
AL1 J31
AL11 P1
AL21 P31
AL31 T4
T28
V1
V31
AC1
AC31
AE1
AE31
AH16
AJ1
AJ31
AK1
AK2
AK30
AK31
AL2
AL3
AL7
AL9
AL14
AL18
AL23
AL25
AL29
AL30
June 1, 1996 (Version 1.02) 4-133
Package-Specific Pinout Tables
PC84 Package Pinouts
2/28/96
Pin XC4003E XC4005E
XC4005L XC4006E XC4008E XC4010E
XC4010L
P1 GND GND GND GND GND
P2 VCC VCC VCC VCC VCC
P3 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P4 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P5 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10)
P6 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11)
P7 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
P8 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13)
P9 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P10 I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
P11 VCC VCC VCC VCC VCC
P12 GND GND GND GND GND
P13 I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
P14 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17)
P15 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
P16 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK
P17 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS
P18 I/O I/O I/O I/O I/O
P19 I/O I/O I/O I/O I/O
P20 I/O I/O I/O I/O I/O
P21 GND GND GND GND GND
P22 VCC VCC VCC VCC VCC
P23 I/O I/O I/O I/O I/O
P24 I/O I/O I/O I/O I/O
P25 I/O I/O I/O I/O I/O
P26 I/O I/O I/O I/O I/O
P27 I/O I/O I/O I/O I/O
P28 I/O I/O I/O I/O I/O
P29 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2
P30 O (M1) O (M1) O (M1) O (M1) O (M1)
P31 GND GND GND GND GND
P32 I (M0) I (M0) I (M0) I (M0) I (M0)
P33 VCC VCC VCC VCC VCC
P34 I (M2) I (M2) I (M2) I (M2) I (M2)
P35 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2
P36 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
P37 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
P38 I/O I/O I/O I/O I/O
P39 I/O I/O I/O I/O I/O
P40 I/O I/O I/O I/O I/O
P41 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)
P42 VCC VCC VCC VCC VCC
P43 GND GND GND GND GND
P44 I/O I/O I/O I/O I/O
P45 I/O I/O I/O I/O I/O
P46 I/O I/O I/O I/O I/O
P47 I/O I/O I/O I/O I/O
P48 I/O I/O I/O I/O I/O
P49 I/O I/O I/O I/O I/O
P50 I/O I/O I/O I/O I/O
P51 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3
P52 GND GND GND GND GND
P53 DONE DONE DONE DONE DONE
P54 VCC VCC VCC VCC VCC
P55 PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM
P56 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P57 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3
P58 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P59 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P60 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
P61 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P62 I/O I/O I/O I/O I/O
P63 VCC VCC VCC VCC VCC
P64 GND GND GND GND GND
P65 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P66 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P67 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P68 I/O I/O I/O I/O I/O
P69 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P70 I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
P71 I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN)
P72 I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
P73 CCLK CCLK CCLK CCLK CCLK
P74 VCC VCC VCC VCC VCC
P75 O, TDO O, TDO O, TDO O, TDO O, TDO
P76 GND GND GND GND GND
P77 I/O
(A0, WS)I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS)
P78 I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
P79 I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2)
P80 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P81 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P82 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P83 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
P84 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
Pin XC4003E XC4005E
XC4005L XC4006E XC4008E XC4010E
XC4010L
XC4000 Series Field Programmable Gate Arrays
4-134 June 1, 1996 (Version 1.02)
PQ100 Package Pinouts
2/28/96
PQ100 Pin XC4003E XC4005E
P1 I/O (A14) I/O (A14)
P2 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
P3 VCC VCC
P4 GND GND
P5 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
P6 I/O (A17) I/O (A17)
P7 I/O, TDI I/O, TDI
P8 I/O, TCK I/O, TCK
P9 I/O, TMS I/O, TMS
P10 I/O I/O
P11 I/O I/O
P12 I/O I/O
P13 I/O I/O
P14 GND GND
P15 VCC VCC
P16 I/O I/O
P17 I/O I/O
P18 I/O I/O
P19 I/O I/O
P20 I/O I/O
P21 I/O I/O
P22 I/O I/O
P23 I/O I/O
P24 I/O, SCGK2 I/O, SCGK2
P25 O (M1) O (M1)
P26 GND GND
P27 I (M0) I (M0)
P28 VCC VCC
P29 I (M2) I (M2)
P30 I/O, PGCK2 I/O, PGCK2
P31 I/O (HDC) I/O (HDC)
P32 I/O I/O
P33 I/O (LDC) I/O (LDC)
P34 I/O I/O
P35 I/O I/O
P36 I/O I/O
P37 I/O I/O
P38 I/O I/O
P39 I/O (INIT) I/O (INIT)
P40 VCC VCC
P41 GND GND
P42 I/O I/O
P43 I/O I/O
P44 I/O I/O
P45 I/O I/O
P46 I/O I/O
P47 I/O I/O
P48 I/O I/O
P49 I/O I/O
P50 I/O I/O
P51 I/O, SGCK3 I/O, SGCK3
P52 GND GND
P53 DONE DONE
P54 VCC VCC
P55 PROGRAM PROGRAM
P56 I/O (D7) I/O (D7)
P57 I/O, PGCK3 I/O, PGCK3
P58 I/O (D6) I/O (D6)
P59 I/O I/O
P60 I/O (D5) I/O (D5)
P61 I/O (CS0) I/O (CS0)
P62 I/O I/O
P63 I/O I/O
P64 I/O (D4) I/O (D4)
P65 I/O I/O
P66 VCC VCC
P67 GND GND
P68 I/O (D3) I/O (D3)
P69 I/O (RS) I/O (RS)
P70 I/O I/O
P71 I/O (D2) I/O (D2)
P72 I/O I/O
P73 I/O (D1) I/O (D1)
P74 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
P75 I/O (D0, DIN) I/O (D0, DIN)
P76 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
P77 CCLK CCLK
P78 VCC VCC
P79 O, TDO O, TDO
P80 GND GND
P81 I/O (A0, WS) I/O (A0, WS)
P82 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
P83 I/O (CS1, A2) I/O (CS1, A2)
P84 I/O (A3) I/O (A3)
P85 I/O (A4) I/O (A4)
P86 I/O (A5) I/O (A5)
P87 I/O I/O
P88 I/O I/O
P89 I/O (A6) I/O (A6)
P90 I/O (A7) I/O (A7)
P91 GND GND
P92 VCC VCC
P93 I/O (A8) I/O (A8)
P94 I/O (A9) I/O (A9)
P95 I/O I/O
P96 I/O I/O
P97 I/O (A10) I/O (A10)
P98 I/O (A11) I/O (A11)
P99 I/O (A12) I/O (A12)
P100 I/O (A13) I/O (A13)
PQ100 Pin XC4003E XC4005E
June 1, 1996 (Version 1.02) 4-135
VQ100 Package Pinouts
2/28/96
VQ100 Pin XC4003E
P1 GND
P2 I/O, PGCK1 (A16)
P3 I/O (A17)
P4 I/O, TDI
P5 I/O, TCK
P6 I/O, TMS
P7 I/O
P8 I/O
P9 I/O
P10 I/O
P11 GND
P12 VCC
P13 I/O
P14 I/O
P15 I/O
P16 I/O
P17 I/O
P18 I/O
P19 I/O
P20 I/O
P21 I/O, SCGK2
P22 O (M1)
P23 GND
P24 I (M0)
P25 VCC
P26 I (M2)
P27 I/O, PGCK2
P28 I/O (HDC)
P29 I/O
P30 I/O (LDC)
P31 I/O
P32 I/O
P33 I/O
P34 I/O
P35 I/O
P36 I/O (INIT)
P37 VCC
P38 GND
P39 I/O
P40 I/O
P41 I/O
P42 I/O
P43 I/O
P44 I/O
P45 I/O
P46 I/O
P47 I/O
P48 I/O, SGCK3
P49 GND
P50 DONE
P51 VCC
P52 PROGRAM
P53 I/O (D7)
P54 I/O, PGCK3
P55 I/O (D6)
P56 I/O
P57 I/O (D5)
P58 I/O (CS0)
P59 I/O
P60 I/O
P61 I/O (D4)
P62 I/O
P63 VCC
P64 GND
P65 I/O (D3)
P66 I/O (RS)
P67 I/O
P68 I/O (D2)
P69 I/O
P70 I/O (D1)
P71 I/O (RCLK, RDY/BUSY)
P72 I/O (D0, DIN)
P73 I/O, SGCK4 (DOUT)
P74 CCLK
P75 VCC
P76 O, TDO
P77 GND
P78 I/O (A0, WS)
P79 I/O, PGCK4 (A1)
P80 I/O (CS1, A2)
P81 I/O (A3)
P82 I/O (A4)
P83 I/O (A5)
P84 I/O
P85 I/O
P86 I/O (A6)
P87 I/O (A7)
P88 GND
P89 VCC
P90 I/O (A8)
P91 I/O (A9)
P92 I/O
P93 I/O
P94 I/O (A10)
P95 I/O (A11)
P96 I/O (A12)
P97 I/O (A13)
P98 I/O (A14)
P99 I/O, SGCK1 (A15)
P100 VCC
VQ100 Pin XC4003E
XC4000 Series Field Programmable Gate Arrays
4-136 June 1, 1996 (Version 1.02)
PG120 Package Pinouts
PG120 Pin XC4003E
N13 I/O, PGCK3
N12 N.C.
N11 I/O
N10 I/O (CS0)
N9 I/O
N8 I/O
N7 I/O (D3)
N6 I/O (RS)
N5 I/O
N4 I/O
N3 I/O (RCLK, RDY/BUSY)
N2 I/O (D0, DIN)
N1 I/O, PGCK4 (A1)
M13 I/O
M12 PROGRAM
M11 I/O (D7)
M10 I/O (D6)
M9 I/O (D5)
M8 I/O (D4)
M7 VCC
M6 I/O
M5 I/O (D1)
M4 N.C.
M3 I/O, SGCK4 (DOUT)
M2 O, TDO
M1 N.C.
L13 I/O
L12 I/O, SGCK3
L11 DONE
L10 VCC
L9 N.C.
L8 I/O
L7 GND
L6 I/O (D2)
L5 N.C.
L4 CCLK
L3 VCC
L2 I/O (A0, WS)
L1 I/O (A3)
K13 I/O
K12 N.C.
K11 GND
K3 GND
K2 I/O (CS1, A2)
K1 I/O (A5)
J13 I/O
J12 I/O
J11 N.C.
J3 N.C.
J2 I/O (A4)
J1 I/O
H13 I/O
H12 I/O
H11 I/O
H3 I/O
H2 I/O (A6)
H1 I/O (A7)
G13 I/O
G12 VCC
G11 GND
G3 VCC
G2 GND
G1 I/O (A8)
F13 I/O (INIT)
F12 I/O
F11 I/O
F3 I/O (A10)
F2 I/O
F1 I/O (A9)
E13 I/O
E12 I/O
E11 N.C.
E3 N.C.
E2 N.C.
E1 I/O
D13 I/O
D12 I/O
D11 VCC
D3 I/O, SGCK1 (A15)
D2 I/O (A13)
D1 I/O (A11)
C13 I/O (LDC)
C12 I/O, PGCK2
C11 I (M0)
C10 GND
C9 I/O
C8 I/O
C7 VCC
C6 I/O
C5 I/O, TDI
C4 GND
C3 VCC
C2 I/O (A14)
C1 I/O (A12)
PG120 Pin XC4003E
June 1, 1996 (Version 1.02) 4-137
3/13/96
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
B13 N.C.
B12 I (M2)
B11 O (M1)
B10 N.C.
B9 I/O
B8 I/O
B7 GND
B6 I/O
B5 I/O, TMS
B4 I/O, TCK
B3 I/O (A17)
B2 I/O, PGCK1 (A16)
B1 N.C.
A13 I/O (HDC)
A12 I/O, SCGK2
A11 I/O
PG120 Pin XC4003E A10 I/O
A9 I/O
A8 I/O
A7 I/O
A6 I/O
A5 I/O
A4 I/O
A3 N.C.
A2 N.C.
A1 N.C.
PG120 Pin XC4003E
XC4000 Series Field Programmable Gate Arrays
4-138 June 1, 1996 (Version 1.02)
TQ144 Package Pinouts
TQ144 Pin XC4005E XC4006E
P1 GND GND
P2 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
P3 I/O (A17) I/O (A17)
P4 I/O I/O
P5 I/O I/O
P6 I/O, TDI I/O, TDI
P7 I/O, TCK I/O, TCK
P8 GND GND
P9 I/O I/O
P10 I/O I/O
P11 I/O, TMS I/O, TMS
P12 I/O I/O
P13 I/O I/O
P14 I/O I/O
P15 I/O I/O
P16 I/O I/O
P17 GND GND
P18 VCC VCC
P19 I/O I/O
P20 I/O I/O
P21 I/O I/O
P22 I/O I/O
P23 I/O I/O
P24 I/O I/O
P25 I/O I/O
P26 I/O I/O
P27 GND GND
P28 I/O I/O
P29 I/O I/O
P30 I/O I/O
P31 I/O I/O
P32 I/O I/O
P33 I/O, SCGK2 I/O, SCGK2
P34 O (M1) O (M1)
P35 GND GND
P36 I (M0) I (M0)
P37 VCC VCC
P38 I (M2) I (M2)
P39 I/O, PGCK2 I/O, PGCK2
P40 I/O (HDC) I/O (HDC)
P41 I/O I/O
P42 I/O I/O
P43 I/O I/O
P44 I/O (LDC) I/O (LDC)
P45 GND GND
P46 I/O I/O
P47 I/O I/O
P48 I/O I/O
P49 I/O I/O
P50 I/O I/O
P51 I/O I/O
P52 I/O I/O
P53 I/O (INIT) I/O (INIT)
P54 VCC VCC
P55 GND GND
P56 I/O I/O
P57 I/O I/O
P58 I/O I/O
P59 I/O I/O
P60 I/O I/O
P61 I/O I/O
P62 I/O I/O
P63 I/O I/O
P64 GND GND
P65 I/O I/O
P66 I/O I/O
P67 I/O I/O
P68 I/O I/O
P69 I/O I/O
P70 I/O, SGCK3 I/O, SGCK3
P71 GND GND
P72 DONE DONE
P73 VCC VCC
P74 PROGRAM PROGRAM
P75 I/O (D7) I/O (D7)
P76 I/O, PGCK3 I/O, PGCK3
P77 I/O I/O
P78 I/O I/O
P79 I/O (D6) I/O (D6)
P80 I/O I/O
P81 GND GND
P82 I/O I/O
P83 I/O I/O
P84 I/O (D5) I/O (D5)
P85 I/O (CS0) I/O (CS0)
P86 I/O I/O
P87 I/O I/O
P88 I/O (D4) I/O (D4)
P89 I/O I/O
P90 VCC VCC
P91 GND GND
P92 I/O (D3) I/O (D3)
P93 I/O (RS) I/O (RS)
P94 I/O I/O
TQ144 Pin XC4005E XC4006E
June 1, 1996 (Version 1.02) 4-139
2/28/96
Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by dif-
ferent devices.
P95 I/O I/O
P96 I/O (D2) I/O (D2)
P97 I/O I/O
P98 I/O I/O
P99 I/O I/O
P100 GND GND
P101 I/O (D1) I/O (D1)
P102 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
P103 I/O I/O
P104 I/O I/O
P105 I/O (D0, DIN) I/O (D0, DIN)
P106 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
P107 CCLK CCLK
P108 VCC VCC
P109 O, TDO O, TDO
P110 GND GND
P111 I/O (A0, WS) I/O (A0, WS)
P112 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
P113 I/O I/O
P114 I/O I/O
P115 I/O (CS1, A2) I/O (CS1, A2)
P116 I/O (A3) I/O (A3)
P117 N.C. I/O
P118 GND GND
P119 I/O I/O
P120 I/O I/O
P121 I/O (A4) I/O (A4)
P122 I/O (A5) I/O (A5)
P123 I/O I/O
P124 I/O I/O
P125 I/O (A6) I/O (A6)
P126 I/O (A7) I/O (A7)
P127 GND GND
P128 VCC VCC
P129 I/O (A8) I/O (A8)
P130 I/O (A9) I/O (A9)
P131 I/O I/O
P132 I/O I/O
P133 I/O (A10) I/O (A10)
P134 I/O (A11) I/O (A11)
P135 I/O I/O
P136 I/O I/O
P137 GND GND
P138 I/O (A12) I/O (A12)
P139 I/O (A13) I/O (A13)
P140 I/O I/O
P141 I/O I/O
TQ144 Pin XC4005E XC4006E P142 I/O (A14) I/O (A14)
P143 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
P144 VCC VCC
TQ144 Pin XC4005E XC4006E
XC4000 Series Field Programmable Gate Arrays
4-140 June 1, 1996 (Version 1.02)
PG156 Package Pinouts
PG156 Pin XC4005E XC4006E
T1 O, TDO O, TDO
T2 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
T3 I/O (D1) I/O (D1)
T4 I/O I/O
T5 I/O I/O
T6 I/O I/O
T7 I/O (RS) I/O (RS)
T8 I/O (D3) I/O (D3)
T9 I/O I/O
T10 I/O (D5) I/O (D5)
T11 I/O I/O
T12 N.C. I/O
T13 I/O I/O
T14 I/O (D6) I/O (D6)
T15 I/O, PGCK3 I/O, PGCK3
T16 I/O (D7) I/O (D7)
R1 I/O (A0, WS) I/O (A0, WS)
R2 CCLK CCLK
R3 I/O I/O
R4 I/O I/O
R5 N.C. I/O
R6 I/O I/O
R7 I/O I/O
R8 VCC VCC
R9 I/O (D4) I/O (D4)
R10 I/O I/O
R11 I/O I/O
R12 N.C. I/O
R13 I/O I/O
R14 PROGRAM PROGRAM
R15 DONE DONE
R16 I/O, SGCK3 I/O, SGCK3
P1 I/O (CS1, A2) I/O (CS1, A2)
P2 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
P3 VCC VCC
P4 I/O (D0, DIN) I/O (D0, DIN)
P5 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
P6 GND GND
P7 I/O (D2) I/O (D2)
P8 GND GND
P9 I/O I/O
P10 I/O (CS0) I/O (CS0)
P11 GND GND
P12 I/O I/O
P13 VCC VCC
P14 GND GND
P15 I/O I/O
P16 I/O I/O
N1 I/O (A3) I/O (A3)
N2 I/O I/O
N3 GND GND
N14 I/O I/O
N15 I/O I/O
N16 N.C. I/O
M1 N.C. I/O
M2 N.C. I/O
M3 I/O I/O
M14 I/O I/O
M15 N.C. I/O
M16 I/O I/O
L1 I/O I/O
L2 I/O I/O
L3 GND GND
L14 GND GND
L15 I/O I/O
L16 I/O I/O
K1 I/O I/O
K2 I/O (A5) I/O (A5)
K3 I/O (A4) I/O (A4)
K14 I/O I/O
K15 I/O I/O
K16 I/O I/O
J1 I/O I/O
J2 I/O (A6) I/O (A6)
J3 I/O (A7) I/O (A7)
J14 GND GND
J15 I/O I/O
J16 I/O I/O
H1 I/O (A8) I/O (A8)
H2 GND GND
H3 VCC VCC
H14 VCC VCC
H15 I/O (INIT) I/O (INIT)
H16 I/O I/O
G1 I/O (A9) I/O (A9)
G2 I/O I/O
G3 I/O I/O
G14 I/O I/O
G15 I/O I/O
G16 I/O I/O
F1 I/O (A10) I/O (A10)
F2 I/O (A11) I/O (A11)
F3 GND GND
PG156 Pin XC4005E XC4006E
June 1, 1996 (Version 1.02) 4-141
2/28/96
Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by dif-
ferent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
F14 GND GND
F15 I/O I/O
F16 I/O I/O
E1 I/O I/O
E2 I/O I/O
E3 I/O (A12) I/O (A12)
E14 I/O I/O
E15 N.C. I/O
E16 I/O I/O
D1 N.C. I/O
D2 N.C. I/O
D3 I/O I/O
D14 I/O (HDC) I/O (HDC)
D15 I/O I/O
D16 N.C. I/O
C1 I/O (A13) I/O (A13)
C2 I/O I/O
C3 VCC VCC
C4 GND GND
C5 I/O I/O
C6 GND GND
C7 I/O I/O
C8 GND GND
C9 I/O I/O
C10 I/O I/O
C11 GND GND
C12 I/O I/O
C13 GND GND
C14 VCC VCC
C15 I/O I/O
C16 I/O (LDC) I/O (LDC)
B1 I/O (A14) I/O (A14)
B2 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
B3 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
B4 I/O, TDI I/O, TDI
B5 I/O I/O
B6 I/O I/O
B7 I/O I/O
B8 VCC VCC
B9 I/O I/O
B10 I/O I/O
B11 I/O I/O
B12 I/O I/O
B13 I/O I/O
B14 I/O, SCGK2 I/O, SCGK2
B15 I (M2) I (M2)
B16 I/O, PGCK2 I/O, PGCK2
A1 I/O (A17) I/O (A17)
PG156 Pin XC4005E XC4006E A2 I/O I/O
A3 I/O, TCK I/O, TCK
A4 N.C. I/O
A5 I/O, TMS I/O, TMS
A6 I/O I/O
A7 I/O I/O
A8 I/O I/O
A9 I/O I/O
A10 I/O I/O
A11 I/O I/O
A12 N.C. I/O
A13 I/O I/O
A14 I/O I/O
A15 O (M1) O (M1)
A16 I (M0) I (M0)
PG156 Pin XC4005E XC4006E
XC4000 Series Field Programmable Gate Arrays
4-142 June 1, 1996 (Version 1.02)
PQ160 Package Pinouts
PQ
160
Pin XC4005E XC4006E XC4008E XC4010E XC4013E
P1 GND GND GND GND GND
P2 I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
P3 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17)
P4 I/O I/O I/O I/O I/O
P5 I/O I/O I/O I/O I/O
P6 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
P7 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK
P8 N.C. I/O I/O I/O I/O
P9 N.C. I/O I/O I/O I/O
P10 GND GND GND GND GND
P11 I/O I/O I/O I/O I/O
P12 I/O I/O I/O I/O I/O
P13 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS
P14 I/O I/O I/O I/O I/O
P15 I/O I/O I/O I/O I/O
P16 I/O I/O I/O I/O I/O
P17 I/O I/O I/O I/O I/O
P18 I/O I/O I/O I/O I/O
P19 GND GND GND GND GND
P20 VCC VCC VCC VCC VCC
P21 I/O I/O I/O I/O I/O
P22 I/O I/O I/O I/O I/O
P23 I/O I/O I/O I/O I/O
P24 I/O I/O I/O I/O I/O
P25 I/O I/O I/O I/O I/O
P26 I/O I/O I/O I/O I/O
P27 I/O I/O I/O I/O I/O
P28 I/O I/O I/O I/O I/O
P29 GND GND GND GND GND
P30 N.C. I/O I/O I/O I/O
P31 N.C. I/O I/O I/O I/O
P32 I/O I/O I/O I/O I/O
P33 I/O I/O I/O I/O I/O
P34 I/O I/O I/O I/O I/O
P35 I/O I/O I/O I/O I/O
P36 I/O I/O I/O I/O I/O
P37 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2
P38 O (M1) O (M1) O (M1) O (M1) O (M1)
P39 GND GND GND GND GND
P40 I (M0) I (M0) I (M0) I (M0) I (M0)
P41 VCC VCC VCC VCC VCC
P42 I (M2) I (M2) I (M2) I (M2) I (M2)
P43 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2
P44 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
P45 I/O I/O I/O I/O I/O
P46 I/O I/O I/O I/O I/O
P47 I/O I/O I/O I/O I/O
P48 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
P49 N.C. I/O I/O I/O I/O
P50 N.C. I/O I/O I/O I/O
P51 GND GND GND GND GND
P52 I/O I/O I/O I/O I/O
P53 I/O I/O I/O I/O I/O
P54 I/O I/O I/O I/O I/O
P55 I/O I/O I/O I/O I/O
P56 I/O I/O I/O I/O I/O
P57 I/O I/O I/O I/O I/O
P58 I/O I/O I/O I/O I/O
P59 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)
P60 VCC VCC VCC VCC VCC
P61 GND GND GND GND GND
P62 I/O I/O I/O I/O I/O
P63 I/O I/O I/O I/O I/O
P64 I/O I/O I/O I/O I/O
P65 I/O I/O I/O I/O I/O
P66 I/O I/O I/O I/O I/O
P67 I/O I/O I/O I/O I/O
P68 I/O I/O I/O I/O I/O
P69 I/O I/O I/O I/O I/O
P70 GND GND GND GND GND
P71 N.C. I/O I/O I/O I/O
P72 N.C. I/O I/O I/O I/O
P73 I/O I/O I/O I/O I/O
P74 I/O I/O I/O I/O I/O
P75 I/O I/O I/O I/O I/O
P76 I/O I/O I/O I/O I/O
P77 I/O I/O I/O I/O I/O
P78 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3
P79 GND GND GND GND GND
P80 DONE DONE DONE DONE DONE
P81 VCC VCC VCC VCC VCC
P82 PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM
P83 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P84 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3
P85 I/O I/O I/O I/O I/O
P86 I/O I/O I/O I/O I/O
P87 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P88 I/O I/O I/O I/O I/O
P89 N.C. I/O I/O I/O I/O
P90 N.C. I/O I/O I/O I/O
P91 GND GND GND GND GND
P92 I/O I/O I/O I/O I/O
P93 I/O I/O I/O I/O I/O
P94 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P95 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
PQ
160
Pin XC4005E XC4006E XC4008E XC4010E XC4013E
June 1, 1996 (Version 1.02) 4-143
2/28/96
Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by dif-
ferent devices.
P96 I/O I/O I/O I/O I/O
P97 I/O I/O I/O I/O I/O
P98 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P99 I/O I/O I/O I/O I/O
P100 VCC VCC VCC VCC VCC
P101 GND GND GND GND GND
P102 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P103 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P104 I/O I/O I/O I/O I/O
P105 I/O I/O I/O I/O I/O
P106 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P107 I/O I/O I/O I/O I/O
P108 I/O I/O I/O I/O I/O
P109 I/O I/O I/O I/O I/O
P110 GND GND GND GND GND
P111 N.C. I/O I/O I/O I/O
P112 N.C. I/O I/O I/O I/O
P113 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P114 I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
I/O (RCLK,
RDY/
BUSY)
P115 I/O I/O I/O I/O I/O
P116 I/O I/O I/O I/O I/O
P117 I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN)
P118 I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
P119 CCLK CCLK CCLK CCLK CCLK
P120 VCC VCC VCC VCC VCC
P121 O, TDO O, TDO O, TDO O, TDO O, TDO
P122 GND GND GND GND GND
P123 I/O
(A0, WS)I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS)
P124 I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
P125 I/O I/O I/O I/O I/O
P126 I/O I/O I/O I/O I/O
P127 I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2) I/O
(CS1, A2)
P128 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P129 N.C. I/O I/O I/O I/O
P130 N.C. I/O I/O I/O I/O
P131 GND GND GND GND GND
P132 I/O I/O I/O I/O I/O
P133 I/O I/O I/O I/O I/O
P134 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P135 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P136 N.C. N.C. I/O I/O I/O
P137 I/O I/O I/O I/O I/O
P138 I/O I/O I/O I/O I/O
P139 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
PQ
160
Pin XC4005E XC4006E XC4008E XC4010E XC4013E
P140 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
P141 GND GND GND GND GND
P142 VCC VCC VCC VCC VCC
P143 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P144 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P145 I/O I/O I/O I/O I/O
P146 I/O I/O I/O I/O I/O
P147 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10)
P148 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11)
P149 I/O I/O I/O I/O I/O
P150 I/O I/O I/O I/O I/O
P151 GND GND GND GND GND
P152 N.C. I/O I/O I/O I/O
P153 N.C. I/O I/O I/O I/O
P154 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
P155 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13)
P156 I/O I/O I/O I/O I/O
P157 I/O I/O I/O I/O I/O
P158 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P159 I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
P160 VCC VCC VCC VCC VCC
PQ
160
Pin XC4005E XC4006E XC4008E XC4010E XC4013E
XC4000 Series Field Programmable Gate Arrays
4-144 June 1, 1996 (Version 1.02)
TQ176 Package Pinouts
TQ176 Pin XC4010L
P1 GND
P2 I/O, PGCK1 (A16)
P3 I/O (A17)
P4 I/O
P5 I/O
P6 I/O, TDI
P7 I/O, TCK
P8 I/O
P9 I/O
P10 GND
P11 I/O
P12 I/O
P13 I/O, TMS
P14 I/O
P15 I/O
P16 I/O
P17 I/O
P18 I/O
P19 I/O
P20 I/O
P21 GND
P22 VCC
P23 I/O
P24 I/O
P25 I/O
P26 I/O
P27 I/O
P28 I/O
P29 I/O
P30 I/O
P31 I/O
P32 I/O
P33 GND
P34 I/O
P35 I/O
P36 I/O
P37 I/O
P38 I/O
P39 I/O
P40 I/O
P41 I/O, SCGK2
P42 O (M1)
P43 GND
P44 I (M0)
P45 VCC
P46 I (M2)
P47 I/O, PGCK2
P48 I/O (HDC)
P49 I/O
P50 I/O
P51 I/O
P52 I/O (LDC)
P53 I/O
P54 I/O
P55 GND
P56 I/O
P57 I/O
P58 I/O
P59 I/O
P60 I/O
P61 I/O
P62 I/O
P63 I/O
P64 I/O
P65 I/O (INIT)
P66 VCC
P67 GND
P68 I/O
P69 I/O
P70 I/O
P71 I/O
P72 I/O
P73 I/O
P74 I/O
P75 I/O
P76 I/O
P77 I/O
P78 GND
P79 I/O
P80 I/O
P81 I/O
P82 I/O
P83 I/O
P84 I/O
P85 I/O
P86 I/O, SGCK3
P87 GND
P88 DONE
P89 VCC
P90 PROGRAM
P91 I/O (D7)
P92 I/O, PGCK3
P93 I/O
P94 I/O
TQ176 Pin XC4010L
June 1, 1996 (Version 1.02) 4-145
3/15/96
PG191 Package Pinouts (see PG223)
The PG191 package pinout has been combined with the
PG223 in a single table, because of their physical compat-
ibility. The PG191 has the same dimensions as the PG223,
but has 32 fewer pins on the inner ring.
P95 I/O (D6)
P96 I/O
P97 I/O
P98 I/O
P99 GND
P100 I/O
P101 I/O
P102 I/O (D5)
P103 I/O (CS0)
P104 I/O
P105 I/O
P106 I/O
P107 I/O
P108 I/O (D4)
P109 I/O
P110 VCC
P111 GND
P112 I/O (D3)
P113 I/O (RS)
P114 I/O
P115 I/O
P116 I/O
P117 I/O
P118 I/O (D2)
P119 I/O
P120 I/O
P121 I/O
P122 GND
P123 I/O
P124 I/O
P125 I/O (D1)
P126 I/O (RCLK, RDY/BUSY)
P127 I/O
P128 I/O
P129 I/O (D0, DIN)
P130 I/O, SGCK4 (DOUT)
P131 CCLK
P132 VCC
P133 O, TDO
P134 GND
P135 I/O (A0, WS)
P136 I/O, PGCK4 (A1)
P137 I/O
P138 I/O
P139 I/O (CS1, A2)
P140 I/O (A3)
P141 I/O
P142 I/O
TQ176 Pin XC4010L P143 GND
P144 I/O
P145 I/O
P146 I/O (A4)
P147 I/O (A5)
P148 I/O
P149 I/O
P150 I/O
P151 I/O
P152 I/O (A6)
P153 I/O (A7)
P154 GND
P155 VCC
P156 I/O (A8)
P157 I/O (A9)
P158 I/O
P159 I/O
P160 I/O
P161 I/O
P162 I/O (A10)
P163 I/O (A11)
P164 I/O
P165 I/O
P166 GND
P167 I/O
P168 I/O
P169 I/O
P170 I/O (A12)
P171 I/O (A13)
P172 I/O
P173 I/O
P174 I/O (A14)
P175 I/O, SGCK1 (A15)
P176 VCC
TQ176 Pin XC4010L
XC4000 Series Field Programmable Gate Arrays
4-146 June 1, 1996 (Version 1.02)
PQ208, HQ208 Package Pinouts
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL
P1 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P2 GND GND GND GND GND GND GND
P3 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P4 I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
GCK1
(A16)
P5 I/O
(A17) I/O
(A17) I/O
(A17) I/O
(A17) I/O
(A17) I/O
(A17) I/O
(A17)
P6 I/O I/O I/O I/O I/O I/O I/O
P7 I/O I/O I/O I/O I/O I/O I/O
P8 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
P9 I/O,
TCK I/O,
TCK I/O,
TCK I/O,
TCK I/O,
TCK I/O,
TCK I/O,
TCK
P10 N.C. I/O I/O I/O I/O I/O I/O
P11 N.C. I/O I/O I/O I/O I/O I/O
P12 N.C. N.C. N.C. I/O I/O I/O I/O
P13 N.C. N.C. N.C. I/O I/O I/O I/O
P14 GND GND GND GND GND GND GND
P15 I/O I/O I/O I/O I/O I/O I/O,
FCLK1
P16 I/O I/O I/O I/O I/O I/O I/O
P17 I/O,
TMS I/O,
TMS I/O,
TMS I/O,
TMS I/O,
TMS I/O,
TMS I/O,
TMS
P18 I/O I/O I/O I/O I/O I/O I/O
P19 N.C. N.C. I/O I/O I/O I/O I/O
P20 N.C. N.C. I/O I/O I/O I/O I/O
P21 I/O I/O I/O I/O I/O I/O I/O
P22 I/O I/O I/O I/O I/O I/O I/O
P23 I/O I/O I/O I/O I/O I/O I/O
P24 I/O I/O I/O I/O I/O I/O I/O
P25 GND GND GND GND GND GND GND
P26 VCC VCC VCC VCC VCC VCC VCC
P27 I/O I/O I/O I/O I/O I/O I/O
P28 I/O I/O I/O I/O I/O I/O I/O
P29 I/O I/O I/O I/O I/O I/O I/O
P30 I/O I/O I/O I/O I/O I/O I/O
P31 N.C. N.C. I/O I/O I/O I/O I/O
P32 N.C. N.C. I/O I/O I/O I/O I/O
P33 I/O I/O I/O I/O I/O I/O I/O
P34 I/O I/O I/O I/O I/O I/O I/O
P35 I/O I/O I/O I/O I/O I/O I/O
P36 I/O I/O I/O I/O I/O I/O I/O,
FCLK2
P37 GND GND GND GND GND GND GND
P38 N.C. N.C. N.C. I/O I/O I/O I/O
P39 N.C. N.C. N.C. I/O I/O I/O I/O
P40 N.C. I/O I/O I/O I/O I/O I/O
P41 N.C. I/O I/O I/O I/O I/O I/O
P42 I/O I/O I/O I/O I/O I/O I/O
P43 I/O I/O I/O I/O I/O I/O I/O
P44 I/O I/O I/O I/O I/O I/O I/O
P45 I/O I/O I/O I/O I/O I/O I/O
P46 I/O I/O I/O I/O I/O I/O I/O
P47 I/O,
SGCK2 I/O,
SGCK2 I/O,
SGCK2 I/O,
SGCK2 I/O,
SGCK2 I/O,
SGCK2 I/O,
GCK2
P48 O (M1) O (M1) O (M1) O (M1) O (M1) O (M1) O (M1)
P49 GND GND GND GND GND GND GND
P50 I (M0) I (M0) I (M0) I (M0) I (M0) I (M0) I (M0)
P51 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P52 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P53 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P54 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P55 VCC VCC VCC VCC VCC VCC VCC
P56 I (M2) I (M2) I (M2) I (M2) I (M2) I (M2) I (M2)
P57 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
GCK3
P58 I/O
(HDC) I/O
(HDC) I/O
(HDC) I/O
(HDC) I/O
(HDC) I/O
(HDC) I/O
(HDC)
P59 I/O I/O I/O I/O I/O I/O I/O
P60 I/O I/O I/O I/O I/O I/O I/O
P61 I/O I/O I/O I/O I/O I/O I/O
P62 I/O
(LDC)I/O
(LDC) I/O
(LDC) I/O
(LDC) I/O
(LDC) I/O
(LDC) I/O
(LDC)
P63 N.C. I/O I/O I/O I/O I/O I/O
P64 N.C. I/O I/O I/O I/O I/O I/O
P65 N.C. N.C. N.C. I/O I/O I/O I/O
P66 N.C. N.C. N.C. I/O I/O I/O I/O
P67 GND GND GND GND GND GND GND
P68 I/O I/O I/O I/O I/O I/O I/O
P69 I/O I/O I/O I/O I/O I/O I/O
P70 I/O I/O I/O I/O I/O I/O I/O
P71 I/O I/O I/O I/O I/O I/O I/O
P72 N.C. N.C. I/O I/O I/O I/O I/O
P73 N.C. N.C. I/O I/O I/O I/O I/O
P74 I/O I/O I/O I/O I/O I/O I/O
P75 I/O I/O I/O I/O I/O I/O I/O
P76 I/O I/O I/O I/O I/O I/O I/O
P77 I/O
(INIT)I/O
(INIT) I/O
(INIT) I/O
(INIT) I/O
(INIT) I/O
(INIT) I/O
(INIT)
P78 VCC VCC VCC VCC VCC VCC VCC
P79 GND GND GND GND GND GND GND
P80 I/O I/O I/O I/O I/O I/O I/O
P81 I/O I/O I/O I/O I/O I/O I/O
P82 I/O I/O I/O I/O I/O I/O I/O
P83 I/O I/O I/O I/O I/O I/O I/O
P84 N.C. N.C. I/O I/O I/O I/O I/O
P85 N.C. N.C. I/O I/O I/O I/O I/O
P86 I/O I/O I/O I/O I/O I/O I/O
P87 I/O I/O I/O I/O I/O I/O I/O
P88 I/O I/O I/O I/O I/O I/O I/O
P89 I/O I/O I/O I/O I/O I/O I/O
P90 GND GND GND GND GND GND GND
P91 N.C. N.C. N.C. I/O I/O I/O I/O
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL
June 1, 1996 (Version 1.02) 4-147
P92 N.C. N.C. N.C. I/O I/O I/O I/O
P93 N.C. I/O I/O I/O I/O I/O I/O
P94 N.C. I/O I/O I/O I/O I/O I/O
P95 I/O I/O I/O I/O I/O I/O I/O
P96 I/O I/O I/O I/O I/O I/O I/O
P97 I/O I/O I/O I/O I/O I/O I/O
P98 I/O I/O I/O I/O I/O I/O I/O
P99 I/O I/O I/O I/O I/O I/O I/O
P100 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
GCK4
P101 GND GND GND GND GND GND GND
P102 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P103 DONE DONE DONE DONE DONE DONE DONE
P104 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P105 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P106 VCC VCC VCC VCC VCC VCC VCC
P107 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P108 PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM
P109 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P110 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
GCK5
P111 I/O I/O I/O I/O I/O I/O I/O
P112 I/O I/O I/O I/O I/O I/O I/O
P113 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P114 I/O I/O I/O I/O I/O I/O I/O
P115 N.C. I/O I/O I/O I/O I/O I/O
P116 N.C. I/O I/O I/O I/O I/O I/O
P117 N.C. N.C. N.C. I/O I/O I/O I/O
P118 N.C. N.C. N.C. I/O I/O I/O I/O
P119 GND GND GND GND GND GND GND
P120 I/O I/O I/O I/O I/O I/O I/O,
FCLK3
P121 I/O I/O I/O I/O I/O I/O I/O
P122 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P123 I/O
(CS0)I/O
(CS0) I/O
(CS0) I/O
(CS0) I/O
(CS0) I/O
(CS0) I/O
(CS0)
P124 N.C. N.C. I/O I/O I/O I/O I/O
P125 N.C. N.C. I/O I/O I/O I/O I/O
P126 I/O I/O I/O I/O I/O I/O I/O
P127 I/O I/O I/O I/O I/O I/O I/O
P128 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P129 I/O I/O I/O I/O I/O I/O I/O
P130 VCC VCC VCC VCC VCC VCC VCC
P131 GND GND GND GND GND GND GND
P132 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P133 I/O
(RS)I/O
(RS) I/O
(RS) I/O
(RS) I/O
(RS) I/O
(RS) I/O
(RS)
P134 I/O I/O I/O I/O I/O I/O I/O
P135 I/O I/O I/O I/O I/O I/O I/O
P136 N.C. N.C. I/O I/O I/O I/O I/O
P137 N.C. N.C. I/O I/O I/O I/O I/O
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL P138 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P139 I/O I/O I/O I/O I/O I/O I/O
P140 I/O I/O I/O I/O I/O I/O I/O
P141 I/O I/O I/O I/O I/O I/O I/O,
FCLK4
P142 GND GND GND GND GND GND GND
P143 N.C. N.C. N.C. I/O I/O I/O I/O
P144 N.C. N.C. N.C. I/O I/O I/O I/O
P145 N.C. I/O I/O I/O I/O I/O I/O
P146 N.C. I/O I/O I/O I/O I/O I/O
P147 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P148 I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
P149 I/O I/O I/O I/O I/O I/O I/O
P150 I/O I/O I/O I/O I/O I/O I/O
P151 I/O
(D0,
DIN)
I/O
(D0,
DIN)
I/O
(D0,
DIN)
I/O
(D0,
DIN)
I/O
(D0,
DIN)
I/O
(D0,
DIN)
I/O
(D0,
DIN)
P152 I/O,
SGCK
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
GCK6
(DOUT)
P153 CCLK CCLK CCLK CCLK CCLK CCLK CCLK
P154 VCC VCC VCC VCC VCC VCC VCC
P155 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P156 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P157 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P158 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P159 O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO
P160 GND GND GND GND GND GND GND
P161 I/O
(A0,
WS)
I/O
(A0,
WS)
I/O
(A0,
WS)
I/O
(A0,
WS)
I/O
(A0,
WS)
I/O
(A0,
WS)
I/O
(A0,
WS)
P162 I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
GCK7
(A1)
P163 I/O I/O I/O I/O I/O I/O I/O
P164 I/O I/O I/O I/O I/O I/O I/O
P165 I/O
(CS1,
A2)
I/O
(CS1,
A2)
I/O
(CS1,
A2)
I/O
(CS1,
A2)
I/O
(CS1,
A2)
I/O
(CS1,
A2)
I/O
(CS1,
A2)
P166 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P167 N.C. I/O I/O I/O I/O I/O I/O
P168 N.C. I/O I/O I/O I/O I/O I/O
P169 N.C. N.C. N.C. I/O I/O I/O I/O
P170 N.C. N.C. N.C. I/O I/O I/O I/O
P171 GND GND GND GND GND GND GND
P172 I/O I/O I/O I/O I/O I/O I/O
P173 I/O I/O I/O I/O I/O I/O I/O
P174 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P175 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P176 N.C. N.C. I/O I/O I/O I/O I/O
P177 N.C. N.C. I/O I/O I/O I/O I/O
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL
XC4000 Series Field Programmable Gate Arrays
4-148 June 1, 1996 (Version 1.02)
3/13/96
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
P178 I/O I/O I/O I/O I/O I/O I/O
(A21)
P179 I/O I/O I/O I/O I/O I/O I/O
(A20)
P180 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
P181 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
P182 GND GND GND GND GND GND GND
P183 VCC VCC VCC VCC VCC VCC VCC
P184 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P185 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P186 I/O I/O I/O I/O I/O I/O I/O
(A19)
P187 I/O I/O I/O I/O I/O I/O I/O
(A18)
P188 N.C. N.C. I/O I/O I/O I/O I/O
P189 N.C. N.C. I/O I/O I/O I/O I/O
P190 I/O
(A10) I/O
(A10) I/O
(A10) I/O
(A10) I/O
(A10) I/O
(A10) I/O
(A10)
P191 I/O
(A11) I/O
(A11) I/O
(A11) I/O
(A11) I/O
(A11) I/O
(A11) I/O
(A11)
P192 I/O I/O I/O I/O I/O I/O I/O
P193 I/O I/O I/O I/O I/O I/O I/O
P194 GND GND GND GND GND GND GND
P195 N.C. N.C. N.C. I/O I/O I/O I/O
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL P196 N.C. N.C. N.C. I/O I/O I/O I/O
P197 N.C. I/O I/O I/O I/O I/O I/O
P198 N.C. I/O I/O I/O I/O I/O I/O
P199 I/O
(A12) I/O
(A12) I/O
(A12) I/O
(A12) I/O
(A12) I/O
(A12) I/O
(A12)
P200 I/O
(A13) I/O
(A13) I/O
(A13) I/O
(A13) I/O
(A13) I/O
(A13) I/O
(A13)
P201 I/O I/O I/O I/O I/O I/O I/O
P202 I/O I/O I/O I/O I/O I/O I/O
P203 I/O
(A14) I/O
(A14) I/O
(A14) I/O
(A14) I/O
(A14) I/O
(A14) I/O
(A14)
P204 I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
GCK8
(A15)
P205 VCC VCC VCC VCC VCC VCC VCC
P206 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P207 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P208 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
PQ
208
Pin
XC
4005
E/L
XC
4006
E
XC
4008
E
XC
4010
E/L
XC
4013
E/L
XC
4020
E
XC
4028
EX/XL
June 1, 1996 (Version 1.02) 4-149
PG223 and PG191 Package Pinouts
These two packages have been combined into a single ta-
ble because of their physical compatibility. The PG191 has
the same dimensions as the PG223, but has 32 fewer pins
on the inner ring.
PG
223
Pin
PG
191
Pin
XC4008E
PG191 XC4010E
PG191 XC4013E
PG223 XC4020E
PG223 XC4025E
PG223
V1 V1 CCLK CCLK CCLK CCLK CCLK
V2 V2 I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
V3 V3 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
V4 V4 N.C. I/O I/O I/O I/O
V5 V5 N.C. I/O I/O I/O I/O
V6 V6 I/O I/O I/O I/O I/O
V7 V7 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
V8 V8 I/O I/O I/O I/O I/O
V9 V9 I/O I/O I/O I/O I/O
V10 V10 I/O I/O I/O I/O I/O
V11 V11 I/O I/O I/O I/O I/O
V12 V12 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
V13 V13 I/O I/O I/O I/O I/O
V14 V14 N.C. I/O I/O I/O I/O
V15 V15 N.C. I/O I/O I/O I/O
V16 V16 I/O I/O I/O I/O I/O
V17 V17 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
V18 V18 PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM
U1 U1 I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
U2 U2 O, TDO O, TDO O, TDO O, TDO O, TDO
U3 U3 I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN)
U4 U4 I/O I/O I/O I/O I/O
U5 U5 I/O I/O I/O I/O I/O
U6 U6 I/O I/O I/O I/O I/O
U7 U7 I/O I/O I/O I/O I/O
U8 U8 I/O I/O I/O I/O I/O
U9 U9 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS)
U10 U10 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
U11 U11 I/O I/O I/O I/O I/O
U12 U12 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
U13 U13 I/O I/O I/O I/O I/O
U14 U14 I/O I/O I/O I/O I/O
U15 U15 I/O I/O I/O I/O I/O
U16 U16 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3
U17 U17 DONE DONE DONE DONE DONE
U18 U18 I/O I/O I/O I/O I/O
T1 T1 I/O I/O I/O I/O I/O
T2 T2 I/O
(CS1,A2) I/O
(CS1,A2) I/O
(CS1,A2) I/O
(CS1,A2) I/O
(CS1,A2)
T3 T3 I/O
(A0, WS)I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS)
T4 T4 I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
T5 T5 I/O I/O I/O I/O I/O
T6 T6 I/O I/O I/O I/O I/O
T7 T7 GND GND GND GND GND
T8 T8 I/O I/O I/O I/O I/O
T9 T9 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
T10 T10 I/O I/O I/O I/O I/O
T11 T11 I/O I/O I/O I/O I/O
T12 T12 GND GND GND GND GND
T13 T13 I/O I/O I/O I/O I/O
T14 T14 I/O I/O I/O I/O I/O
T15 T15 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
T16 T16 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3
T17 T17 I/O I/O I/O I/O I/O
T18 T18 I/O I/O I/O I/O I/O
R1 R1 N.C. I/O I/O I/O I/O
R2 R2 I/O I/O I/O I/O I/O
R3 R3 GND GND GND GND GND
R4 R4 VCC VCC VCC VCC VCC
R5 I/O I/O I/O
R6 I/O I/O I/O
R7 I/O I/O I/O
R8 I/O I/O I/O
R9 R9 GND GND GND GND GND
R10 R10 VCC VCC VCC VCC VCC
R11 I/O I/O I/O
R12 I/O I/O I/O
R13 I/O I/O I/O
R14 I/O I/O I/O
R15 R15 VCC VCC VCC VCC VCC
R16 R16 GND GND GND GND GND
R17 R17 I/O I/O I/O I/O I/O
R18 R18 N.C. I/O I/O I/O I/O
P1 P1 I/O I/O I/O I/O I/O
P2 P2 I/O I/O I/O I/O I/O
P3 P3 I/O I/O I/O I/O I/O
P4 I/O I/O I/O
P15 I/O I/O I/O
P16 P16 I/O I/O I/O I/O I/O
P17 P17 I/O I/O I/O I/O I/O
P18 P18 I/O I/O I/O I/O I/O
N1 N1 I/O I/O I/O I/O I/O
N2 N2 N.C. I/O I/O I/O I/O
N3 N3 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
N4 I/O I/O I/O
N15 I/O I/O I/O
N16 N16 I/O I/O I/O I/O I/O
PG
223
Pin
PG
191
Pin
XC4008E
PG191 XC4010E
PG191 XC4013E
PG223 XC4020E
PG223 XC4025E
PG223
XC4000 Series Field Programmable Gate Arrays
4-150 June 1, 1996 (Version 1.02)
N17 N17 N.C. I/O I/O I/O I/O
N18 N18 I/O I/O I/O I/O I/O
M1 M1 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
M2 M2 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
M3 M3 GND GND GND GND GND
M4 I/O I/O I/O
M15 I/O I/O I/O
M16 M16 GND GND GND GND GND
M17 M17 I/O I/O I/O I/O I/O
M18 M18 I/O I/O I/O I/O I/O
L1 L1 I/O I/O I/O I/O I/O
L2 L2 I/O I/O I/O I/O I/O
L3 L3 I/O I/O I/O I/O I/O
L4 I/O I/O I/O
L15 I/O I/O I/O
L16 L16 I/O I/O I/O I/O I/O
L17 L17 I/O I/O I/O I/O I/O
L18 L18 I/O I/O I/O I/O I/O
K1 K1 I/O I/O I/O I/O I/O
K2 K2 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
K3 K3 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
K4 K4 GND GND GND GND GND
K15 K15 GND GND GND GND GND
K16 K16 I/O I/O I/O I/O I/O
K17 K17 I/O I/O I/O I/O I/O
K18 K18 I/O I/O I/O I/O I/O
J1 J1 I/O I/O I/O I/O I/O
J2 J2 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9)
J3 J3 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8)
J4 J4 VCC VCC VCC VCC VCC
J15 J15 VCC VCC VCC VCC VCC
J16 J16 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)
J17 J17 I/O I/O I/O I/O I/O
J18 J18 I/O I/O I/O I/O I/O
H1 H1 I/O I/O I/O I/O I/O
H2 H2 I/O I/O I/O I/O I/O
H3 H3 I/O I/O I/O I/O I/O
H4 I/O I/O I/O
H15 I/O I/O I/O
H16 H16 I/O I/O I/O I/O I/O
H17 H17 I/O I/O I/O I/O I/O
H18 H18 I/O I/O I/O I/O I/O
G1 G1 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10)
G2 G2 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11)
G3 G3 GND GND GND GND GND
G4 I/O I/O I/O
G15 I/O I/O I/O
G16 G16 GND GND GND GND GND
G17 G17 I/O I/O I/O I/O I/O
G18 G18 I/O I/O I/O I/O I/O
F1 F1 I/O I/O I/O I/O I/O
PG
223
Pin
PG
191
Pin
XC4008E
PG191 XC4010E
PG191 XC4013E
PG223 XC4020E
PG223 XC4025E
PG223
F2 F2 N.C. I/O I/O I/O I/O
F3 F3 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
F4 I/O I/O I/O
F15 I/O I/O I/O
F16 F16 I/O I/O I/O I/O I/O
F17 F17 N.C. I/O I/O I/O I/O
F18 F18 I/O I/O I/O I/O I/O
E1 E1 I/O I/O I/O I/O I/O
E2 E2 I/O I/O I/O I/O I/O
E3 E3 I/O I/O I/O I/O I/O
E4 I/O I/O I/O
E15 I/O I/O I/O
E16 E16 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
E17 E17 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
E18 E18 I/O I/O I/O I/O I/O
D1 D1 N.C. I/O I/O I/O I/O
D2 D2 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13)
D3 D3 VCC VCC VCC VCC VCC
D4 D4 GND GND GND GND GND
D5 I/O I/O I/O
D6 I/O I/O I/O
D7 I/O I/O I/O
D8 I/O I/O I/O
D9 D9 GND GND GND GND GND
D10 D10 VCC VCC VCC VCC VCC
D11 I/O I/O I/O
D12 I/O I/O I/O
D13 I/O I/O I/O
D14 I/O I/O I/O
D15 D15 GND GND GND GND GND
D16 D16 VCC VCC VCC VCC VCC
D17 D17 I/O I/O I/O I/O I/O
D18 D18 N.C. I/O I/O I/O I/O
C1 C1 I/O I/O I/O I/O I/O
C2 C2 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
C3 C3 I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
C4 C4 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17)
C5 C5 I/O I/O I/O I/O I/O
C6 C6 I/O I/O I/O I/O I/O
C7 C7 GND GND GND GND GND
C8 C8 I/O I/O I/O I/O I/O
C9 C9 I/O I/O I/O I/O I/O
C10 C10 I/O I/O I/O I/O I/O
C11 C11 I/O I/O I/O I/O I/O
C12 C12 GND GND GND GND GND
C13 C13 I/O I/O I/O I/O I/O
C14 C14 I/O I/O I/O I/O I/O
C15 C15 O (M1) O (M1) O (M1) O (M1) O (M1)
C16 C16 I (M2) I (M2) I (M2) I (M2) I (M2)
PG
223
Pin
PG
191
Pin
XC4008E
PG191 XC4010E
PG191 XC4013E
PG223 XC4020E
PG223 XC4025E
PG223
June 1, 1996 (Version 1.02) 4-151
2/28/96
Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by dif-
ferent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
C17 C17 I/O I/O I/O I/O I/O
C18 C18 I/O I/O I/O I/O I/O
B1 B1 I/O I/O I/O I/O I/O
B2 B2 I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
B3 B3 I/O I/O I/O I/O I/O
B4 B4 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK
B5 B5 N.C. I/O I/O I/O I/O
B6 B6 N.C. I/O I/O I/O I/O
B7 B7 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS
B8 B8 I/O I/O I/O I/O I/O
B9 B9 I/O I/O I/O I/O I/O
B10 B10 I/O I/O I/O I/O I/O
B11 B11 I/O I/O I/O I/O I/O
B12 B12 I/O I/O I/O I/O I/O
B13 B13 N.C. I/O I/O I/O I/O
B14 B14 I/O I/O I/O I/O I/O
B15 B15 I/O I/O I/O I/O I/O
B16 B16 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2 I/O,
SCGK2
B17 B17 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2
B18 B18 I/O I/O I/O I/O I/O
A2 A2 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
A3 A3 I/O I/O I/O I/O I/O
A4 A4 I/O I/O I/O I/O I/O
A5 A5 I/O I/O I/O I/O I/O
A6 A6 I/O I/O I/O I/O I/O
A7 A7 I/O I/O I/O I/O I/O
A8 A8 I/O I/O I/O I/O I/O
A9 A9 I/O I/O I/O I/O I/O
A10 A10 I/O I/O I/O I/O I/O
A11 A11 I/O I/O I/O I/O I/O
A12 A12 I/O I/O I/O I/O I/O
A13 A13 I/O I/O I/O I/O I/O
A14 A14 N.C. I/O I/O I/O I/O
A15 A15 I/O I/O I/O I/O I/O
A16 A16 I/O I/O I/O I/O I/O
A17 A17 I/O I/O I/O I/O I/O
A18 A18 I (M0) I (M0) I (M0) I (M0) I (M0)
PG
223
Pin
PG
191
Pin
XC4008E
PG191 XC4010E
PG191 XC4013E
PG223 XC4020E
PG223 XC4025E
PG223
XC4000 Series Field Programmable Gate Arrays
4-152 June 1, 1996 (Version 1.02)
BG225 Package Pinouts
BG225 Pin XC4010E XC4013E/L
R1 VCC VCC
R2 I/O, PGCK2 I/O, PGCK2
R3 I/O I/O
R4 I/O I/O
R5 I/O I/O
R6 I/O I/O
R7 I/O I/O
R8 VCC VCC
R9 I/O I/O
R10 N.C. I/O
R11 I/O I/O
R12 I/O I/O
R13 I/O I/O
R14 I/O I/O
R15 VCC VCC
P1 I/O, SCGK2 I/O, SCGK2
P2 I (M0) I (M0)
P3 I/O (HDC) I/O (HDC)
P4 I/O (LDC) I/O (LDC)
P5 N.C. I/O
P6 I/O I/O
P7 N.C. I/O
P8 I/O (INIT) I/O (INIT)
P9 I/O I/O
P10 N.C. I/O
P11 I/O I/O
P12 I/O I/O
P13 I/O I/O
P14 DONE DONE
P15 I/O (D7) I/O (D7)
N1 I/O I/O
N2 I/O I/O
N3 O (M1) O (M1)
N4 I/O I/O
N5 I/O I/O
N6 I/O I/O
N7 N.C. I/O
N8 I/O I/O
N9 I/O I/O
N10 I/O I/O
N11 N.C. I/O
N12 I/O I/O
N13 I/O, SGCK3 I/O, SGCK3
N14 I/O, PGCK3 I/O, PGCK3
N15 N.C. I/O
M1 I/O I/O
M2 I/O I/O
M3 I/O I/O
M4 I (M2) I (M2)
M5 I/O I/O
M6 I/O I/O
M7 I/O I/O
M8 GND GND
M9 I/O I/O
M10 N.C. I/O
M11 I/O I/O
M12 PROGRAM PROGRAM
M13 I/O I/O
M14 N.C. I/O
M15 I/O I/O
L1 I/O I/O
L2 N.C. I/O
L3 I/O I/O
L4 I/O I/O
L5 I/O I/O
L6 N.C. I/O
L7 I/O I/O
L8 I/O I/O
L9 I/O I/O
L10 I/O I/O
L11 I/O I/O
L12 I/O I/O
L13 I/O I/O
L14 I/O I/O
L15 N.C. I/O
K1 N.C. I/O
K2 I/O I/O
K3 I/O I/O
K4 N.C. I/O
K5 I/O I/O
K6 I/O I/O
K7 I/O I/O
K8 GND GND
K9 I/O I/O
K10 I/O I/O
K11 I/O I/O
K12 N.C. I/O
K13 I/O I/O
K14 I/O I/O
K15 I/O (D5) I/O (D5)
J1 I/O I/O
J2 I/O I/O
J3 I/O I/O
J4 I/O I/O
J5 N.C. I/O
J6 I/O I/O
J7 GND GND
J8 GND GND
J9 GND GND
J10 I/O (D6) I/O (D6)
J11 I/O I/O
J12 I/O (CS0) I/O (CS0)
J13 I/O I/O
J14 I/O I/O
J15 I/O I/O
H1 VCC VCC
H2 GND GND
H3 I/O I/O
H4 I/O I/O
H5 I/O I/O
H6 GND GND
H7 GND GND
H8 GND GND
H9 GND GND
H10 GND GND
H11 I/O (RS) I/O (RS)
H12 I/O (D3) I/O (D3)
H13 I/O (D4) I/O (D4)
BG225 Pin XC4010E XC4013E/L
June 1, 1996 (Version 1.02) 4-153
2/28/96
Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by dif-
ferent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
H14 I/O I/O
H15 VCC VCC
G1 I/O I/O
G2 I/O I/O
G3 I/O I/O
G4 I/O I/O
G5 I/O I/O
G6 I/O I/O
G7 GND GND
G8 GND GND
G9 GND GND
G10 N.C. I/O
G11 I/O (D2) I/O (D2)
G12 I/O I/O
G13 I/O I/O
G14 I/O I/O
G15 I/O I/O
F1 N.C. I/O
F2 N.C. I/O
F3 I/O I/O
F4 I/O, TMS I/O, TMS
F5 I/O I/O
F6 I/O I/O
F7 N.C. I/O
F8 GND GND
F9 N.C. I/O
F10 I/O (D0, DIN) I/O (D0, DIN)
F11 I/O I/O
F12 N.C. I/O
F13 I/O I/O
F14 I/O I/O
F15 I/O I/O
E1 I/O I/O
E2 N.C. I/O
E3 N.C. I/O
E4 I/O I/O
E5 I/O I/O
E6 I/O I/O
E7 I/O I/O
E8 I/O (A8) I/O (A8)
E9 I/O I/O
E10 I/O I/O
E11 I/O I/O
E12 I/O (D1) I/O (D1)
E13 I/O I/O
E14 N.C. I/O
E15 N.C. I/O
D1 I/O I/O
D2 I/O I/O
D3 I/O, TDI I/O, TDI
D4 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
D5 I/O (A13) I/O (A13)
D6 I/O I/O
D7 I/O I/O
D8 VCC VCC
D9 I/O (A5) I/O (A5)
D10 I/O I/O
D11 N.C. I/O
D12 GND GND
D13 I/O I/O
BG225 Pin XC4010E XC4013E/L D14 I/O I/O
D15 I/O I/O
C1 I/O, TCK I/O, TCK
C2 I/O I/O
C3 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
C4 N.C. I/O
C5 I/O I/O
C6 N.C. I/O
C7 I/O I/O
C8 I/O (A6) I/O (A6)
C9 I/O I/O
C10 N.C. I/O
C11 I/O I/O
C12 I/O I/O
C13 CCLK CCLK
C14 I/O I/O
C15 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
B1 I/O (A17) I/O (A17)
B2 VCC VCC
B3 I/O I/O
B4 I/O (A12) I/O (A12)
B5 I/O I/O
B6 I/O (A11) I/O (A11)
B7 I/O (A9) I/O (A9)
B8 I/O (A7) I/O (A7)
B9 I/O I/O
B10 N.C. I/O
B11 I/O I/O
B12 I/O (A3) I/O (A3)
B13 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
B14 VCC VCC
B15 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
A1 GND GND
A2 I/O (A14) I/O (A14)
A3 N.C. I/O
A4 I/O I/O
A5 I/O I/O
A6 I/O (A10) I/O (A10)
A7 I/O I/O
A8 GND GND
A9 I/O I/O
A10 I/O (A4) I/O (A4)
A11 I/O I/O
A12 I/O I/O
A13 I/O (CS1, A2) I/O (CS1, A2)
A14 I/O (A0, WS) I/O (A0, WS)
A15 O, TDO O, TDO
BG225 Pin XC4010E XC4013E/L
XC4000 Series Field Programmable Gate Arrays
4-154 June 1, 1996 (Version 1.02)
PQ240, HQ240 Package Pinouts
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL
P1 GND GND GND GND
P2 I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
PGCK1
(A16)
I/O,
GCK1
(A16)
P3 I/O (A17) I/O (A17) I/O (A17) I/O (A17)
P4 I/O I/O I/O I/O
P5 I/O I/O I/O I/O
P6 I/O, TDI I/O, TDI I/O, TDI I/O, TDI
P7 I/O, TCK I/O, TCK I/O, TCK I/O, TCK
P8 I/O I/O I/O I/O
P9 I/O I/O I/O I/O
P10 I/O I/O I/O I/O
P11 I/O I/O I/O I/O
P12 I/O I/O I/O I/O
P13 I/O I/O I/O I/O
P14 GND GND GND GND
P15 I/O I/O I/O I/O, FCLK1
P16 I/O I/O I/O I/O
P17 I/O, TMS I/O, TMS I/O, TMS I/O, TMS
P18 I/O I/O I/O I/O
P19 VCC VCC VCC VCC
P20 I/O I/O I/O I/O
P21 I/O I/O I/O I/O
P22 N.C.‡ N.C.‡ N.C.‡ GND‡
P23 I/O I/O I/O I/O
P24 I/O I/O I/O I/O
P25 I/O I/O I/O I/O
P26 I/O I/O I/O I/O
P27 I/O I/O I/O I/O
P28 I/O I/O I/O I/O
P29 GND GND GND GND
P30 VCC VCC VCC VCC
P31 I/O I/O I/O I/O
P32 I/O I/O I/O I/O
P33 I/O I/O I/O I/O
P34 I/O I/O I/O I/O
P35 I/O I/O I/O I/O
P36 I/O I/O I/O I/O
P37 N.C.‡ N.C.‡ N.C.‡ GND‡
P38 I/O I/O I/O I/O
P39 I/O I/O I/O I/O
P40 VCC VCC VCC VCC
P41 I/O I/O I/O I/O
P42 I/O I/O I/O I/O
P43 I/O I/O I/O I/O
P44 I/O I/O I/O I/O, FCLK2
P45 GND GND GND GND
P46 I/O I/O I/O I/O
P47 I/O I/O I/O I/O
P48 I/O I/O I/O I/O
P49 I/O I/O I/O I/O
P50 I/O I/O I/O I/O
P51 I/O I/O I/O I/O
P52 I/O I/O I/O I/O
P53 I/O I/O I/O I/O
P54 I/O I/O I/O I/O
P55 I/O I/O I/O I/O
P56 I/O I/O I/O I/O
P57 I/O,
SGCK2 I/O,
SGCK2 I/O,
SGCK2 I/O,
GCK2
P58 O (M1) O (M1) O (M1) O (M1)
P59 GND GND GND GND
P60 I (M0) I (M0) I (M0) I (M0)
P61 VCC VCC VCC VCC
P62 I (M2) I (M2) I (M2) I (M2)
P63 I/O,
PGCK2 I/O,
PGCK2 I/O,
PGCK2 I/O,
GCK3
P64 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
P65 I/O I/O I/O I/O
P66 I/O I/O I/O I/O
P67 I/O I/O I/O I/O
P68 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
P69 I/O I/O I/O I/O
P70 I/O I/O I/O I/O
P71 I/O I/O I/O I/O
P72 I/O I/O I/O I/O
P73 I/O I/O I/O I/O
P74 I/O I/O I/O I/O
P75 GND GND GND GND
P76 I/O I/O I/O I/O
P77 I/O I/O I/O I/O
P78 I/O I/O I/O I/O
P79 I/O I/O I/O I/O
P80 VCC VCC VCC VCC
P81 I/O I/O I/O I/O
P82 I/O I/O I/O I/O
P83 N.C.‡ N.C.‡ N.C.‡ GND‡
P84 I/O I/O I/O I/O
P85 I/O I/O I/O I/O
P86 I/O I/O I/O I/O
P87 I/O I/O I/O I/O
P88 I/O I/O I/O I/O
P89 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL
June 1, 1996 (Version 1.02) 4-155
P90 VCC VCC VCC VCC
P91 GND GND GND GND
P92 I/O I/O I/O I/O
P93 I/O I/O I/O I/O
P94 I/O I/O I/O I/O
P95 I/O I/O I/O I/O
P96 I/O I/O I/O I/O
P97 I/O I/O I/O I/O
P98 N.C.‡ N.C.‡ N.C.‡ GND‡
P99 I/O I/O I/O I/O
P100 I/O I/O I/O I/O
P101 VCC VCC VCC VCC
P102 I/O I/O I/O I/O
P103 I/O I/O I/O I/O
P104 I/O I/O I/O I/O
P105 I/O I/O I/O I/O
P106 GND GND GND GND
P107 I/O I/O I/O I/O
P108 I/O I/O I/O I/O
P109 I/O I/O I/O I/O
P110 I/O I/O I/O I/O
P111 I/O I/O I/O I/O
P112 I/O I/O I/O I/O
P113 I/O I/O I/O I/O
P114 I/O I/O I/O I/O
P115 I/O I/O I/O I/O
P116 I/O I/O I/O I/O
P117 I/O I/O I/O I/O
P118 I/O,
SGCK3 I/O,
SGCK3 I/O,
SGCK3 I/O,
GCK4
P119 GND GND GND GND
P120 DONE DONE DONE DONE
P121 VCC VCC VCC VCC
P122 PRO-
GRAM PRO-
GRAM PRO-
GRAM PRO-
GRAM
P123 I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P124 I/O,
PGCK3 I/O,
PGCK3 I/O,
PGCK3 I/O,
GCK5
P125 I/O I/O I/O I/O
P126 I/O I/O I/O I/O
P127 I/O I/O I/O I/O
P128 I/O I/O I/O I/O
P129 I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P130 I/O I/O I/O I/O
P131 I/O I/O I/O I/O
P132 I/O I/O I/O I/O
P133 I/O I/O I/O I/O
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL P134 I/O I/O I/O I/O
P135 GND GND GND GND
P136 I/O I/O I/O I/O
P137 I/O I/O I/O I/O
P138 I/O I/O I/O I/O, FCLK3
P139 I/O I/O I/O I/O
P140 VCC VCC VCC VCC
P141 I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P142 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
P143 N.C.‡ N.C.‡ N.C.‡ GND‡
P144 I/O I/O I/O I/O
P145 I/O I/O I/O I/O
P146 I/O I/O I/O I/O
P147 I/O I/O I/O I/O
P148 I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P149 I/O I/O I/O I/O
P150 VCC VCC VCC VCC
P151 GND GND GND GND
P152 I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P153 I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P154 I/O I/O I/O I/O
P155 I/O I/O I/O I/O
P156 I/O I/O I/O I/O
P157 I/O I/O I/O I/O
P158 N.C.‡ N.C.‡ N.C.‡ GND‡
P159 I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P160 I/O I/O I/O I/O
P161 VCC VCC VCC VCC
P162 I/O I/O I/O I/O
P163 I/O I/O I/O I/O, FCLK4
P164 I/O I/O I/O I/O
P165 I/O I/O I/O I/O
P166 GND GND GND GND
P167 I/O I/O I/O I/O
P168 I/O I/O I/O I/O
P169 I/O I/O I/O I/O
P170 I/O I/O I/O I/O
P171 I/O I/O I/O I/O
P172 I/O I/O I/O I/O
P173 I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P174 I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
I/O
(RCLK,
RDY/
BUSY)
P175 I/O I/O I/O I/O
P176 I/O I/O I/O I/O
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL
XC4000 Series Field Programmable Gate Arrays
4-156 June 1, 1996 (Version 1.02)
3/11/96
‡ Pins labelled GND‡ should be connected to Ground if
possible; however, they can be left unconnected if neces-
sary for compatibility with other devices. Pins labelled
N.C.‡ are reserved for Ground connections on future revi-
sions of the device. These pins do not physically connect
to anything on the current device revision. However, they
should be externally connected to Ground if possible.
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
P177 I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN) I/O
(D0, DIN)
P178 I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
SGCK4
(DOUT)
I/O,
GCK6
(DOUT)
P179 CCLK CCLK CCLK CCLK
P180 VCC VCC VCC VCC
P181 O, TDO O, TDO O, TDO O, TDO
P182 GND GND GND GND
P183 I/O
(A0, WS)I/O
(A0, WS) I/O
(A0, WS) I/O
(A0, WS)
P184 I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
PGCK4
(A1)
I/O,
GCK7
(A1)
P185 I/O I/O I/O I/O
P186 I/O I/O I/O I/O
P187 I/O (CS1,
A2) I/O (CS1,
A2) I/O (CS1,
A2) I/O (CS1,
A2)
P188 I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P189 I/O I/O I/O I/O
P190 I/O I/O I/O I/O
P191 I/O I/O I/O I/O
P192 I/O I/O I/O I/O
P193 I/O I/O I/O I/O
P194 I/O I/O I/O I/O
P195 N.C. N.C. I/O I/O
P196 GND GND GND GND
P197 I/O I/O I/O I/O
P198 I/O I/O I/O I/O
P199 I/O I/O I/O I/O
P200 I/O I/O I/O I/O
P201 VCC VCC VCC VCC
P202 I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P203 I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P204 N.C.‡ N.C.‡ N.C.‡ GND‡
P205 I/O I/O I/O I/O
P206 I/O I/O I/O I/O
P207 I/O I/O I/O I/O (A21)
P208 I/O I/O I/O I/O (A20)
P209 I/O (A6) I/O (A6) I/O (A6) I/O (A6)
P210 I/O (A7) I/O (A7) I/O (A7) I/O (A7)
P211 GND GND GND GND
P212 VCC VCC VCC VCC
P213 I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P214 I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P215 I/O I/O I/O I/O (A19)
P216 I/O I/O I/O I/O (A18)
P217 I/O I/O I/O I/O
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL P218 I/O I/O I/O I/O
P219 N.C.‡ N.C.‡ N.C.‡ GND‡
P220 I/O (A10) I/O (A10) I/O (A10) I/O (A10)
P221 I/O (A11) I/O (A11) I/O (A11) I/O (A11)
P222 VCC VCC VCC VCC
P223 I/O I/O I/O I/O
P224 I/O I/O I/O I/O
P225 I/O I/O I/O I/O
P226 I/O I/O I/O I/O
P227 GND GND GND GND
P228 I/O I/O I/O I/O
P229 I/O I/O I/O I/O
P230 I/O I/O I/O I/O
P231 I/O I/O I/O I/O
P232 I/O (A12) I/O (A12) I/O (A12) I/O (A12)
P233 I/O (A13) I/O (A13) I/O (A13) I/O (A13)
P234 I/O I/O I/O I/O
P235 I/O I/O I/O I/O
P236 I/O I/O I/O I/O
P237 I/O I/O I/O I/O
P238 I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P239 I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
SGCK1
(A15)
I/O,
GCK8
(A15)
P240 VCC VCC VCC VCC
PQ240/
HQ240 Pin XC4013E
XC4013L XC4020E XC4025E XC4028EX
XC4028XL
June 1, 1996 (Version 1.02) 4-157
PG299 Package Pinouts
PG299 Pin XC4025E XC4028EX/XL
X1 I/O, SGCK4 (DOUT) I/O, GCK6 (DOUT)
X2 GND GND
X3 I/O I/O
X4 I/O I/O
X5 VCC VCC
X6 GND GND
X7 I/O I/O
X8 I/O I/O
X9 I/O I/O
X10 VCC VCC
X11 GND GND
X12 I/O I/O
X13 I/O I/O
X14 I/O (CS0) I/O (CS0)
X15 VCC VCC
X16 GND GND
X17 I/O I/O
X18 I/O I/O
X19 VCC VCC
X20 I/O, SGCK3 I/O, GCK4
W1 VCC VCC
W2 I/O (A0, WS) I/O (A0, WS)
W3 I/O I/O
W4 I/O I/O
W5 I/O I/O
W6 I/O I/O
W7 I/O I/O, FCLK4
W8 I/O (D2) I/O (D2)
W9 I/O I/O
W10 I/O (D3) I/O (D3)
W11 I/O I/O
W12 I/O I/O
W13 I/O I/O
W14 I/O I/O, FCLK3
W15 I/O I/O
W16 I/O I/O
W17 I/O (D6) I/O (D6)
W18 I/O, PGCK3 I/O, GCK5
W19 I/O (D7) I/O (D7)
W20 GND GND
V1 I/O (A3) I/O (A3)
V2 I/O, PGCK4 (A1) I/O, GCK7 (A1)
V3 CCLK CCLK
V4 I/O (D0, DIN) I/O (D0, DIN)
V5 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
V6 I/O I/O
V7 I/O I/O
V8 I/O I/O
V9 I/O I/O
V10 I/O (RS) I/O (RS)
V11 I/O (D4) I/O (D4)
V12 I/O I/O
V13 I/O I/O
V14 I/O I/O
V15 I/O I/O
V16 I/O I/O
V17 I/O I/O
V18 DONE DONE
V19 I/O I/O
V20 I/O I/O
U1 I/O I/O
U2 I/O I/O
U3 I/O (CS1, A2) I/O (CS1, A2)
U4 O, TDO O, TDO
U5 I/O I/O
U6 I/O (D1) I/O (D1)
U7 I/O I/O
U8 I/O I/O
U9 I/O I/O
U10 I/O I/O
U11 I/O I/O
U12 I/O I/O
U13 I/O I/O
U14 I/O I/O
U15 I/O I/O
U16 I/O I/O
U17 PROGRAM PROGRAM
U18 I/O I/O
U19 I/O I/O
U20 I/O I/O
T1 GND GND
T2 I/O I/O
T3 I/O I/O
T4 I/O I/O
T5 GND GND
T6 I/O I/O
T7 I/O I/O
T8 I/O I/O
T9 I/O I/O
T10 I/O I/O
T11 I/O I/O
T12 I/O (D5) I/O (D5)
T13 I/O I/O
T14 I/O I/O
T15 I/O I/O
T16 VCC VCC
T17 I/O I/O
T18 I/O I/O
T19 I/O I/O
T20 VCC VCC
R1 VCC VCC
R2 I/O I/O
PG299 Pin XC4025E XC4028EX/XL
XC4000 Series Field Programmable Gate Arrays
4-158 June 1, 1996 (Version 1.02)
R3 I/O I/O
R4 I/O I/O
R5 I/O I/O
R16 I/O I/O
R17 I/O I/O
R18 I/O I/O
R19 I/O I/O
R20 GND GND
P1 I/O I/O
P2 I/O I/O
P3 I/O I/O
P4 I/O I/O
P5 I/O I/O
P16 I/O I/O
P17 I/O I/O
P18 I/O I/O
P19 I/O I/O
P20 I/O I/O
N1 I/O (A4) I/O (A4)
N2 I/O I/O
N3 I/O I/O
N4 I/O I/O
N5 I/O I/O
N16 I/O I/O
N17 I/O I/O
N18 I/O I/O
N19 I/O I/O
N20 I/O I/O
M1 I/O I/O (A21)
M2 I/O I/O
M3 I/O (A5) I/O (A5)
M4 I/O I/O
M5 I/O I/O
M16 I/O I/O
M17 I/O I/O
M18 I/O I/O
M19 I/O I/O
M20 I/O I/O
L1 GND GND
L2 I/O (A7) I/O (A7)
L3 I/O (A6) I/O (A6)
L4 I/O I/O (A20)
L5 I/O I/O
L16 I/O I/O
L17 I/O I/O
L18 I/O I/O
L19 I/O I/O
L20 VCC VCC
K1 VCC VCC
K2 I/O (A8) I/O (A8)
K3 I/O (A9) I/O (A9)
K4 I/O I/O (A18)
PG299 Pin XC4025E XC4028EX/XL K5 I/O I/O (A19)
K16 I/O I/O
K17 I/O I/O
K18 I/O I/O
K19 I/O (INIT) I/O (INIT)
K20 GND GND
J1 I/O I/O
J2 I/O I/O
J3 I/O (A11) I/O (A11)
J4 I/O I/O
J5 I/O I/O
J16 I/O I/O
J17 I/O I/O
J18 I/O I/O
J19 I/O I/O
J20 I/O I/O
H1 I/O (A10) I/O (A10)
H2 I/O I/O
H3 I/O I/O
H4 I/O I/O
H5 I/O I/O
H16 I/O I/O
H17 I/O I/O
H18 I/O I/O
H19 I/O I/O
H20 I/O I/O
G1 I/O I/O
G2 I/O I/O
G3 I/O I/O
G4 I/O I/O
G5 I/O (A12) I/O (A12)
G16 I/O I/O
G17 I/O I/O
G18 I/O I/O
G19 I/O I/O
G20 I/O I/O
F1 GND GND
F2 I/O I/O
F3 I/O I/O
F4 I/O I/O
F5 I/O I/O
F16 I/O I/O
F17 I/O I/O
F18 I/O I/O
F19 I/O I/O
F20 VCC VCC
E1 VCC VCC
E2 I/O I/O
E3 I/O I/O
E4 I/O I/O
E5 VCC VCC
E6 I/O I/O
PG299 Pin XC4025E XC4028EX/XL
June 1, 1996 (Version 1.02) 4-159
3/18/96
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
E7 I/O I/O
E8 I/O I/O
E9 I/O I/O
E10 I/O I/O
E11 I/O I/O
E12 I/O I/O
E13 I/O I/O
E14 I/O I/O
E15 I/O I/O
E16 GND GND
E17 I/O I/O
E18 I/O I/O
E19 I/O I/O
E20 GND GND
D1 I/O I/O
D2 I/O I/O
D3 I/O (A14) I/O (A14)
D4 I/O, PGCK1 (A16) I/O, GCK1 (A16)
D5 I/O, TDI I/O, TDI
D6 I/O I/O
D7 I/O I/O
D8 I/O I/O
D9 I/O I/O
D10 I/O I/O
D11 I/O I/O
D12 I/O I/O
D13 I/O I/O, FCLK2
D14 I/O I/O
D15 I/O I/O
D16 I/O I/O
D17 I (M2) I (M2)
D18 I/O I/O
D19 I/O I/O
D20 I/O I/O
C1 I/O (A13) I/O (A13)
C2 I/O I/O
C3 I/O, SGCK1 (A15) I/O, GCK8 (A15)
C4 I/O, TCK I/O, TCK
C5 I/O I/O
C6 I/O I/O
C7 I/O, TMS I/O, TMS
C8 I/O I/O
C9 I/O I/O
C10 I/O I/O
C11 I/O I/O
C12 I/O I/O
C13 I/O I/O
C14 I/O I/O
C15 I/O I/O
C16 I/O I/O
C17 I/O, SGCK2 I/O, GCK2
C18 I (M0) I (M0)
PG299 Pin XC4025E XC4028EX/XL C19 I/O (HDC) I/O (HDC)
C20 I/O (LDC) I/O (LDC)
B1 GND GND
B2 I/O (A17) I/O (A17)
B3 I/O I/O
B4 I/O I/O
B5 I/O I/O
B6 I/O I/O, FCLK1
B7 I/O I/O
B8 I/O I/O
B9 I/O I/O
B10 I/O I/O
B11 I/O I/O
B12 I/O I/O
B13 I/O I/O
B14 I/O I/O
B15 I/O I/O
B16 I/O I/O
B17 I/O I/O
B18 I/O I/O
B19 I/O, PGCK2 I/O, GCK3
B20 VCC VCC
A2 VCC VCC
A3 I/O I/O
A4 I/O I/O
A5 GND GND
A6 VCC VCC
A7 I/O I/O
A8 I/O I/O
A9 I/O I/O
A10 GND GND
A11 VCC VCC
A12 I/O I/O
A13 I/O I/O
A14 I/O I/O
A15 GND GND
A16 VCC VCC
A17 I/O I/O
A18 I/O I/O
A19 GND GND
A20 O (M1) O (M1)
PG299 Pin XC4025E XC4028EX/XL
XC4000 Series Field Programmable Gate Arrays
4-160 June 1, 1996 (Version 1.02)
HQ304 Package Pinouts
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL
P1 VCC VCC VCC
P2 I/O, SGCK1 (A15) I/O, GCK8
(A15) I/O, GCK8
(A15)
P3 I/O (A14) I/O (A14) I/O (A14)
P4 I/O I/O I/O
P5 I/O I/O I/O
P6 I/O I/O I/O
P7 I/O I/O I/O
P8 I/O I/O I/O
P9 I/O I/O I/O
P10 I/O (A13) I/O (A13) I/O (A13)
P11 N.C. N.C. N.C.
P12 I/O (A12) I/O (A12) I/O (A12)
P13 I/O I/O I/O
P14 I/O I/O I/O
P15 I/O I/O I/O
P16 I/O I/O I/O
P17 I/O I/O I/O
P18 I/O I/O I/O
P19 GND GND GND
P20 I/O I/O I/O
P21 I/O I/O I/O
P22 I/O I/O I/O
P23 I/O I/O I/O
P24 N.C. N.C. N.C.
P25 VCC VCC VCC
P26 I/O I/O I/O
P27 I/O I/O I/O
P28 I/O I/O I/O
P29 I/O I/O I/O
P30 I/O (A11) I/O (A11) I/O (A11)
P31 I/O (A10) I/O (A10) I/O (A10)
P32 I/O I/O I/O
P33 I/O I/O I/O
P34 I/O I/O (A18) I/O (A18)
P35 I/O I/O (A19) I/O (A19)
P36 I/O (A9) I/O (A9) I/O (A9)
P37 I/O (A8) I/O (A8) I/O (A8)
P38 VCC VCC VCC
P39 GND GND GND
P40 I/O (A7) I/O (A7) I/O (A7)
P41 I/O (A6) I/O (A6) I/O (A6)
P42 I/O I/O (A20) I/O (A20)
P43 I/O I/O (A21) I/O (A21)
P44 I/O I/O I/O
P45 I/O I/O I/O
P46 I/O (A5) I/O (A5) I/O (A5)
P47 I/O (A4) I/O (A4) I/O (A4)
P48 I/O I/O I/O
P49 I/O I/O I/O
P50 I/O I/O I/O
P51 I/O I/O I/O
P52 VCC VCC VCC
P53 N.C. N.C. N.C.
P54 I/O I/O I/O
P55 I/O I/O I/O
P56 I/O I/O I/O
P57 I/O I/O I/O
P58 GND GND GND
P59 I/O I/O I/O
P60 I/O I/O I/O
P61 I/O I/O I/O
P62 I/O I/O I/O
P63 I/O I/O I/O
P64 I/O I/O I/O
P65 I/O I/O I/O
P66 I/O I/O I/O
P67 I/O I/O I/O
P68 I/O I/O I/O
P69 I/O (A3) I/O (A3) I/O (A3)
P70 I/O (CS1, A2) I/O (CS1, A2) I/O (CS1, A2)
P71 I/O I/O I/O
P72 I/O I/O I/O
P73 I/O, PGCK4 (A1) I/O, GCK7 (A1) I/O, GCK7 (A1)
P74 I/O (A0, WS) I/O (A0, WS) I/O (A0, WS)
P75 GND GND GND
P76 O, TDO O, TDO O, TDO
P77 VCC VCC VCC
P78 CCLK CCLK CCLK
P79 I/O, SGCK4
(DOUT) I/O, GCK6
(DOUT) I/O, GCK6
(DOUT)
P80 I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN)
P81 I/O I/O I/O
P82 I/O I/O I/O
P83 I/O I/O I/O
P84 I/O I/O I/O
P85 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
P86 I/O (D1) I/O (D1) I/O (D1)
P87 I/O I/O I/O
P88 I/O I/O I/O
P89 I/O I/O I/O
P90 I/O I/O I/O
P91 I/O I/O I/O
P92 I/O I/O I/O
P93 I/O I/O I/O
P94 I/O I/O I/O
P95 GND GND GND
P96 I/O I/O I/O
P97 I/O I/O I/O
P98 I/O I/O, FCLK4 I/O, FCLK4
P99 I/O I/O I/O
P100 N.C. N.C. N.C.
P101 VCC VCC VCC
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL
June 1, 1996 (Version 1.02) 4-161
P102 I/O I/O I/O
P103 I/O (D2) I/O (D2) I/O (D2)
P104 I/O I/O I/O
P105 I/O I/O I/O
P106 I/O I/O I/O
P107 I/O I/O I/O
P108 I/O I/O I/O
P109 I/O I/O I/O
P110 I/O I/O I/O
P111 I/O I/O I/O
P112 I/O (RS) I/O (RS) I/O (RS)
P113 I/O (D3) I/O (D3) I/O (D3)
P114 GND GND GND
P115 VCC VCC VCC
P116 I/O I/O I/O
P117 I/O (D4) I/O (D4) I/O (D4)
P118 I/O I/O I/O
P119 I/O I/O I/O
P120 I/O I/O I/O
P121 I/O I/O I/O
P122 I/O I/O I/O
P123 I/O I/O I/O
P124 I/O I/O I/O
P125 I/O I/O I/O
P126 I/O (CS0) I/O (CS0) I/O (CS0)
P127 I/O (D5) I/O (D5) I/O (D5)
P128 N.C. N.C. N.C.
P129 VCC VCC VCC
P130 I/O I/O I/O
P131 I/O I/O, FCLK3 I/O, FCLK3
P132 I/O I/O I/O
P133 I/O I/O I/O
P134 GND GND GND
P135 I/O I/O I/O
P136 I/O I/O I/O
P137 I/O I/O I/O
P138 I/O I/O I/O
P139 I/O I/O I/O
P140 I/O I/O I/O
P141 I/O I/O I/O
P142 I/O (D6) I/O (D6) I/O (D6)
P143 I/O I/O I/O
P144 I/O I/O I/O
P145 I/O I/O I/O
P146 I/O I/O I/O
P147 I/O I/O I/O
P148 I/O I/O I/O
P149 I/O, PGCK3 I/O, GCK5 I/O, GCK5
P150 I/O (D7) I/O (D7) I/O (D7)
P151 PROGRAM PROGRAM PROGRAM
P152 VCC VCC VCC
P153 DONE DONE DONE
P154 GND GND GND
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL P155 I/O, SGCK3 I/O, GCK4 I/O, GCK4
P156 I/O I/O I/O
P157 I/O I/O I/O
P158 I/O I/O I/O
P159 I/O I/O I/O
P160 I/O I/O I/O
P161 I/O I/O I/O
P162 I/O I/O I/O
P163 I/O I/O I/O
P164 I/O I/O I/O
P165 I/O I/O I/O
P166 I/O I/O I/O
P167 I/O I/O I/O
P168 I/O I/O I/O
P169 I/O I/O I/O
P170 I/O I/O I/O
P171 GND GND GND
P172 I/O I/O I/O
P173 I/O I/O I/O
P174 I/O I/O I/O
P175 I/O I/O I/O
P176 N.C. N.C. N.C.
P177 VCC VCC VCC
P178 I/O I/O I/O
P179 I/O I/O I/O
P180 I/O I/O I/O
P181 I/O I/O I/O
P182 I/O I/O I/O
P183 I/O I/O I/O
P184 I/O I/O I/O
P185 I/O I/O I/O
P186 I/O I/O I/O
P187 I/O I/O I/O
P188 I/O I/O I/O
P189 I/O I/O I/O
P190 GND GND GND
P191 VCC VCC VCC
P192 I/O (INIT) I/O (INIT) I/O (INIT)
P193 I/O I/O I/O
P194 I/O I/O I/O
P195 I/O I/O I/O
P196 I/O I/O I/O
P197 I/O I/O I/O
P198 I/O I/O I/O
P199 I/O I/O I/O
P200 I/O I/O I/O
P201 I/O I/O I/O
P202 I/O I/O I/O
P203 I/O I/O I/O
P204 VCC VCC VCC
P205 N.C. N.C. N.C.
P206 I/O I/O I/O
P207 I/O I/O I/O
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL
XC4000 Series Field Programmable Gate Arrays
4-162 June 1, 1996 (Version 1.02)
3/20/96
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
P208 I/O I/O I/O
P209 I/O I/O I/O
P210 GND GND GND
P211 I/O I/O I/O
P212 I/O I/O I/O
P213 I/O I/O I/O
P214 I/O I/O I/O
P215 I/O I/O I/O
P216 I/O I/O I/O
P217 I/O I/O I/O
P218 I/O I/O I/O
P219 I/O I/O I/O
P220 I/O I/O I/O
P221 I/O (LDC) I/O (LDC) I/O (LDC)
P222 I/O I/O I/O
P223 I/O I/O I/O
P224 I/O I/O I/O
P225 I/O (HDC) I/O (HDC) I/O (HDC)
P226 I/O, PGCK2 I/O, GCK3 I/O, GCK3
P227 I (M2) I (M2) I (M2)
P228 VCC VCC VCC
P229 I (M0) I (M0) I (M0)
P230 GND GND GND
P231 O (M1) O (M1) O (M1)
P232 I/O, SGCK2 I/O, GCK2 I/O, GCK2
P233 I/O I/O I/O
P234 I/O I/O I/O
P235 I/O I/O I/O
P236 I/O I/O I/O
P237 I/O I/O I/O
P238 I/O I/O I/O
P239 I/O I/O I/O
P240 I/O I/O I/O
P241 I/O I/O I/O
P242 I/O I/O I/O
P243 I/O I/O I/O
P244 I/O I/O I/O
P245 I/O I/O I/O
P246 I/O I/O I/O
P247 I/O I/O I/O
P248 GND GND GND
P249 I/O I/O, FCLK2 I/O, FCLK2
P250 I/O I/O I/O
P251 I/O I/O I/O
P252 I/O I/O I/O
P253 VCC VCC VCC
P254 N.C. N.C. N.C.
P255 I/O I/O I/O
P256 I/O I/O I/O
P257 I/O I/O I/O
P258 I/O I/O I/O
P259 I/O I/O I/O
P260 I/O I/O I/O
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL P261 I/O I/O I/O
P262 I/O I/O I/O
P263 I/O I/O I/O
P264 I/O I/O I/O
P265 I/O I/O I/O
P266 I/O I/O I/O
P267 VCC VCC VCC
P268 GND GND GND
P269 I/O I/O I/O
P270 I/O I/O I/O
P271 I/O I/O I/O
P272 I/O I/O I/O
P273 I/O I/O I/O
P274 I/O I/O I/O
P275 I/O I/O I/O
P276 I/O I/O I/O
P277 I/O I/O I/O
P278 I/O I/O I/O
P279 I/O I/O I/O
P280 I/O I/O I/O
P281 N.C. N.C. N.C.
P282 VCC VCC VCC
P283 I/O I/O I/O
P284 I/O, TMS I/O, TMS I/O, TMS
P285 I/O I/O I/O
P286 I/O I/O, FCLK1 I/O, FCLK1
P287 GND GND GND
P288 I/O I/O I/O
P289 I/O I/O I/O
P290 I/O I/O I/O
P291 I/O I/O I/O
P292 I/O I/O I/O
P293 I/O I/O I/O
P294 I/O I/O I/O
P295 I/O I/O I/O
P296 I/O I/O I/O
P297 I/O I/O I/O
P298 I/O, TCK I/O, TCK I/O, TCK
P299 I/O, TDI I/O, TDI I/O, TDI
P300 I/O I/O I/O
P301 I/O I/O I/O
P302 I/O (A17) I/O (A17) I/O (A17)
P303 I/O, PGCK1
(A16) I/O, GCK1
(A16) I/O, GCK1
(A16)
P304 GND GND GND
HQ304
Pin XC4025E XC4028EX
XC4028XL XC4036EX
XC4036XL
June 1, 1996 (Version 1.02) 4-163
BG352 Package Pinouts
BG352 Pin XC4028EX/XL
AF1 GND
AF2 GND
AF3 I/O
AF4 I/O
AF5 GND
AF6 I/O
AF7 I/O
AF8 GND
AF9 I/O
AF10 VCC
AF11 I/O
AF12 I/O
AF13 GND
AF14 I/O (INIT)
AF15 I/O
AF16 I/O
AF17 VCC
AF18 I/O
AF19 GND
AF20 I/O
AF21 I/O
AF22 GND
AF23 I/O
AF24 I/O
AF25 GND
AF26 GND
AE1 GND
AE2 VCC
AE3 I/O
AE4 N.C.
AE5 I/O
AE6 I/O
AE7 I/O
AE8 I/O
AE9 I/O
AE10 N.C.
AE11 I/O
AE12 I/O
AE13 I/O
AE14 I/O
AE15 I/O
AE16 I/O
AE17 I/O
AE18 I/O
AE19 I/O
AE20 I/O
AE21 I/O
AE22 I/O
AE23 I/O (LDC)
AE24 I/O, GCK3
AE25 VCC
AE26 GND
AD1 I/O
AD2 I/O (D7)
AD3 DONE
AD4 I/O
AD5 I/O
AD6 I/O
AD7 I/O
AD8 I/O
AD9 I/O
AD10 I/O
AD11 I/O
AD12 I/O
AD13 I/O
AD14 I/O
AD15 I/O
AD16 N.C.
AD17 I/O
AD18 I/O
AD19 I/O
AD20 I/O
AD21 N.C.
AD22 I/O
AD23 I/O (HDC)
AD24 I (M0)
AD25 I/O
AD26 N.C.
AC1 I/O
AC2 N.C.
AC3 I/O, GCK5
AC4 PROGRAM
AC5 I/O, GCK4
AC6 N.C.
AC7 I/O
AC8 VCC
AC9 I/O
AC10 I/O
AC11 N.C.
AC12 I/O
AC13 I/O
AC14 VCC
AC15 I/O
AC16 N.C.
AC17 I/O
AC18 I/O
AC19 I/O
AC20 VCC
AC21 N.C.
AC22 I/O
AC23 I (M2)
AC24 I/O, GCK2
AC25 N.C.
AC26 I/O
AB1 GND
AB2 I/O
AB3 N.C.
AB4 I/O
AB23 O (M1)
AB24 I/O
AB25 I/O
AB26 GND
AA1 I/O
AA2 I/O
AA3 I/O
AA4 I/O
AA23 I/O
AA24 I/O
BG352 Pin XC4028EX/XL
XC4000 Series Field Programmable Gate Arrays
4-164 June 1, 1996 (Version 1.02)
AA25 I/O
AA26 I/O
Y1 I/O
Y2 I/O
Y3 I/O (D6)
Y4 VCC
Y23 I/O
Y24 I/O
Y25 I/O
Y26 I/O
W1 GND
W2 I/O
W3 I/O
W4 I/O
W23 VCC
W24 I/O
W25 I/O
W26 GND
V1 I/O (CS0)
V2 I/O (D5)
V3 I/O
V4 I/O
V23 I/O
V24 I/O
V25 I/O
V26 I/O
U1 VCC
U2 I/O
U3 I/O
U4 I/O, FCLK3
U23 I/O, FCLK2
U24 I/O
U25 N.C.
U26 VCC
T1 I/O
T2 I/O
T3 N.C.
T4 N.C.
T23 I/O
T24 N.C.
T25 I/O
T26 I/O
R1 I/O
R2 I/O
R3 I/O
R4 I/O
R23 I/O
R24 I/O
R25 I/O
R26 I/O
P1 I/O
P2 I/O (D4)
P3 I/O
P4 VCC
P23 I/O
P24 I/O
P25 I/O
P26 GND
N1 GND
N2 I/O (D3)
BG352 Pin XC4028EX/XL N3 I/O
N4 I/O (RS)
N23 VCC
N24 I/O
N25 I/O
N26 I/O
M1 I/O
M2 I/O
M3 I/O
M4 I/O
M23 I/O
M24 I/O
M25 I/O
M26 I/O
L1 I/O
L2 I/O
L3 I/O
L4 N.C.
L23 N.C.
L24 I/O
L25 I/O
L26 I/O
K1 VCC
K2 N.C.
K3 I/O
K4 I/O
K23 I/O
K24 I/O
K25 I/O
K26 VCC
J1 I/O (D2)
J2 I/O
J3 I/O, FCLK4
J4 I/O
J23 I/O, FCLK1
J24 I/O
J25 I/O
J26 N.C.
H1 GND
H2 I/O
H3 I/O
H4 VCC
H23 I/O
H24 I/O
H25 I/O, TMS
H26 GND
G1 I/O
G2 I/O
G3 I/O
G4 I/O (RCLK, RDY/BUSY)
G23 VCC
G24 I/O
G25 I/O
G26 I/O
F1 I/O
F2 I/O
F3 I/O (D1)
F4 I/O
F23 N.C.
F24 I/O
BG352 Pin XC4028EX/XL
June 1, 1996 (Version 1.02) 4-165
2/28/96
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
F25 I/O
F26 I/O
E1 GND
E2 I/O
E3 I/O
E4 I/O, GCK6 (DOUT)
E23 I/O
E24 I/O, TCK
E25 I/O
E26 GND
D1 N.C.
D2 I/O
D3 I/O (D0, DIN)
D4 O (TDO)
D5 I/O
D6 I/O (CS1, A2)
D7 VCC
D8 I/O
D9 I/O
D10 I/O
D11 I/O
D12 I/O (A4)
D13 VCC
D14 I/O (A8)
D15 I/O
D16 N.C.
D17 I/O
D18 I/O
D19 VCC
D20 I/O
D21 I/O
D22 I/O (A14)
D23 I/O, GCK1 (A16)
D24 I/O
D25 N.C.
D26 I/O
C1 N.C.
C2 I/O
C3 CCLK
C4 I/O, GCK7 (A1)
C5 N.C.
C6 I/O (A3)
C7 I/O
C8 N.C.
C9 I/O
C10 I/O
C11 N.C.
C12 I/O (A5)
C13 I/O (A21)
C14 I/O (A9)
C15 I/O
C16 I/O
C17 I/O
C18 I/O
C19 I/O
C20 I/O
C21 I/O (A13)
C22 I/O
C23 I/O
C24 I/O, GCK8 (A15)
BG352 Pin XC4028EX/XL C25 I/O (A17)
C26 I/O, TDI
B1 GND
B2 VCC
B3 I/O (A0, WS)
B4 N.C.
B5 I/O
B6 I/O
B7 I/O
B8 I/O
B9 I/O
B10 N.C.
B11 I/O
B12 I/O
B13 I/O (A20)
B14 I/O (A7)
B15 I/O (A18)
B16 I/O (A11)
B17 I/O
B18 I/O
B19 I/O
B20 I/O
B21 I/O
B22 I/O (A12)
B23 N.C.
B24 I/O
B25 VCC
B26 GND
A1 GND
A2 GND
A3 I/O
A4 I/O
A5 GND
A6 I/O
A7 I/O
A8 GND
A9 I/O
A10 VCC
A11 I/O
A12 I/O
A13 I/O (A6)
A14 GND
A15 I/O (A19)
A16 I/O (A10)
A17 VCC
A18 N.C.
A19 GND
A20 I/O
A21 I/O
A22 GND
A23 I/O
A24 N.C.
A25 GND
A26 GND
BG352 Pin XC4028EX/XL
XC4000 Series Field Programmable Gate Arrays
4-166 June 1, 1996 (Version 1.02)
PG411 Package Pinouts
PG411 Pin XC4036EX/XL XC4044EX/XL
AW1 I/O I/O
AW3 GND GND
AW5 I/O I/O
AW7 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
AW9 VCC VCC
AW11 GND GND
AW13 I/O I/O
AW15 N.C. I/O
AW17 I/O I/O
AW19 VCC VCC
AW21 GND GND
AW23 N.C. I/O
AW25 N.C. I/O
AW27 I/O I/O
AW29 VCC VCC
AW31 GND GND
AW33 I/O I/O
AW35 N.C. N.C.
AW37 VCC VCC
AW39 I/O I/O
AV2 I/O, GCK7 (A1) I/O, GCK7 (A1)
AV4 I/O I/O
AV6 I/O I/O
AV8 N.C. I/O
AV10 I/O I/O
AV12 I/O I/O
AV14 I/O I/O
AV16 I/O I/O
AV18 I/O I/O
AV20 I/O (RS) I/O (RS)
AV22 I/O I/O
AV24 I/O I/O
AV26 N.C. N.C.
AV28 I/O I/O
AV30 I/O I/O
AV32 I/O (D6) I/O (D6)
AV34 N.C. N.C.
AV36 I/O I/O
AV38 I/O I/O
AU1 VCC VCC
AU3 I/O, GCK6 (DOUT) I/O, GCK6 (DOUT)
AU5 N.C. N.C.
AU7 I/O (D1) I/O (D1)
AU9 N.C. I/O
AU11 I/O I/O
AU13 N.C. N.C.
AU15 N.C. N.C.
AU17 N.C. I/O
AU19 I/O (D3) I/O (D3)
AU21 I/O I/O
AU23 I/O I/O
AU25 N.C. N.C.
AU27 I/O (CS0) I/O (CS0)
AU29 I/O I/O
AU31 I/O I/O
AU33 I/O I/O
AU35 I/O I/O
AU37 N.C. N.C.
AU39 GND GND
AT2 N.C. N.C.
AT4 I/O (A0, WS) I/O (A0, WS)
AT6 GND GND
AT8 I/O I/O
AT10 I/O I/O
AT12 I/O I/O
AT14 GND GND
AT16 I/O I/O
AT18 I/O I/O
AT20 GND GND
AT22 I/O I/O
AT24 I/O I/O
AT26 GND GND
AT28 I/O, FCLK3 I/O, FCLK3
AT30 N.C. I/O
AT32 I/O I/O
AT34 VCC VCC
AT36 I/O, GCK4 I/O, GCK4
AT38 I/O I/O
AR1 I/O I/O
AR3 I/O I/O
AR5 CCLK CCLK
AR7 I/O I/O
AR9 I/O I/O
AR11 I/O I/O
AR13 I/O, FCLK4 I/O, FCLK4
AR15 I/O (D2) I/O (D2)
AR17 I/O I/O
AR19 I/O I/O
AR21 I/O I/O
AR23 I/O I/O
AR25 I/O I/O
AR27 I/O I/O
AR29 I/O I/O
AR31 I/O I/O
AR33 I/O I/O
AR35 DONE DONE
AR37 N.C. N.C.
AR39 I/O I/O
AP2 I/O I/O
AP4 VCC VCC
AP6 I/O (D0, DIN) I/O (D0, DIN)
AP8 N.C. N.C.
AP10 I/O I/O
AP12 I/O I/O
PG411 Pin XC4036EX/XL XC4044EX/XL
June 1, 1996 (Version 1.02) 4-167
AP14 I/O I/O
AP16 I/O I/O
AP18 I/O I/O
AP20 I/O (D4) I/O (D4)
AP22 I/O I/O
AP24 I/O (D5) I/O (D5)
AP26 I/O I/O
AP28 I/O I/O
AP30 N.C. I/O
AP32 I/O I/O
AP34 I/O, GCK5 I/O, GCK5
AP36 GND GND
AP38 N.C. I/O
AN1 N.C. I/O
AN3 I/O (A3) I/O (A3)
AN5 N.C. N.C.
AN7 O, TDO O, TDO
AN9 I/O I/O
AN31 I/O I/O
AN33 PROGRAM PROGRAM
AN35 I/O I/O
AN37 I/O I/O
AN39 I/O I/O
AM2 I/O I/O
AM4 I/O I/O
AM6 I/O I/O
AM8 I/O I/O
AM32 I/O (D7) I/O (D7)
AM34 I/O I/O
AM36 I/O I/O
AM38 I/O I/O
AL1 GND GND
AL3 I/O I/O
AL5 I/O I/O
AL7 I/O I/O
AL33 I/O I/O
AL35 N.C. N.C.
AL37 I/O I/O
AL39 VCC VCC
AK2 N.C. I/O
AK4 I/O I/O
AK6 I/O (CS1, A2) I/O (CS1, A2)
AK34 I/O I/O
AK36 I/O I/O
AK38 N.C. I/O
AJ1 VCC VCC
AJ3 I/O I/O
AJ5 N.C. N.C.
AJ35 I/O I/O
AJ37 I/O I/O
AJ39 GND GND
AH2 I/O I/O
AH4 I/O I/O
PG411 Pin XC4036EX/XL XC4044EX/XL AH6 I/O I/O
AH34 I/O I/O
AH36 I/O I/O
AH38 I/O I/O
AG1 I/O I/O
AG3 I/O I/O
AG5 I/O I/O
AG35 I/O I/O
AG37 I/O I/O
AG39 I/O I/O
AF2 N.C. N.C.
AF4 GND GND
AF6 I/O I/O
AF34 I/O I/O
AF36 GND GND
AF38 N.C. N.C.
AE1 I/O I/O
AE3 I/O I/O
AE5 I/O I/O
AE35 I/O I/O
AE37 I/O I/O
AE39 I/O I/O
AD2 I/O (A4) I/O (A4)
AD4 I/O (A21) I/O (A21)
AD6 I/O I/O
AD34 I/O I/O
AD36 I/O I/O
AD38 I/O I/O
AC1 I/O I/O
AC3 N.C. I/O
AC5 I/O I/O
AC35 I/O I/O
AC37 I/O I/O
AC39 N.C. I/O
AB2 N.C. I/O
AB4 I/O (A5) I/O (A5)
AB6 I/O I/O
AB34 I/O I/O
AB36 I/O I/O
AB38 I/O I/O
AA1 GND GND
AA3 I/O (A6) I/O (A6)
AA5 I/O (A20) I/O (A20)
AA35 I/O I/O
AA37 N.C. I/O
AA39 VCC VCC
Y2 I/O (A9) I/O (A9)
Y4 GND GND
Y6 I/O (A7) I/O (A7)
Y34 I/O I/O
Y36 GND GND
Y38 N.C. I/O
W1 VCC VCC
PG411 Pin XC4036EX/XL XC4044EX/XL
XC4000 Series Field Programmable Gate Arrays
4-168 June 1, 1996 (Version 1.02)
W3 I/O (A8) I/O (A8)
W5 N.C. I/O
W35 N.C. I/O
W37 I/O (INIT) I/O (INIT)
W39 GND GND
V2 N.C. I/O
V4 I/O (A19) I/O (A19)
V6 I/O I/O
V34 I/O I/O
V36 I/O I/O
V38 I/O I/O
U1 I/O I/O
U3 I/O (A10) I/O (A10)
U5 I/O I/O
U35 I/O I/O
U37 I/O I/O
U39 I/O I/O
T2 I/O (A18) I/O (A18)
T4 I/O I/O
T6 I/O I/O
T34 I/O I/O
T36 I/O I/O
T38 I/O I/O
R1 I/O (A11) I/O (A11)
R3 N.C. N.C.
R5 I/O I/O
R35 I/O I/O
R37 I/O I/O
R39 I/O I/O
P2 I/O I/O
P4 GND GND
P6 I/O I/O
P34 I/O I/O
P36 GND GND
P38 N.C. N.C.
N1 I/O I/O
N3 N.C. N.C.
N5 I/O I/O
N35 I/O I/O
N37 I/O I/O
N39 I/O I/O
M2 I/O I/O
M4 I/O I/O
M6 I/O I/O
M34 I/O I/O
M36 I/O I/O
M38 I/O I/O
L1 GND GND
L3 I/O I/O
L5 N.C. I/O
L35 N.C. N.C.
L37 I/O I/O
L39 VCC VCC
PG411 Pin XC4036EX/XL XC4044EX/XL K2 I/O I/O
K4 I/O I/O
K6 I/O I/O
K34 I/O I/O
K36 N.C. I/O
K38 N.C. I/O
J1 VCC VCC
J3 I/O I/O
J5 N.C. I/O
J7 I/O I/O
J33 I/O I/O
J35 I/O I/O
J37 I/O I/O
J39 GND GND
H2 I/O I/O
H4 I/O (A12) I/O (A12)
H6 I/O I/O
H8 I/O, GCK1 (A16) I/O, GCK1 (A16)
H32 I/O I/O
H34 N.C. N.C.
H36 I/O I/O
H38 I/O I/O
G1 I/O I/O
G3 I/O (A13) I/O (A13)
G5 N.C. N.C.
G7 I/O, GCK8 (A15) I/O, GCK8 (A15)
G9 I/O, TCK I/O, TCK
G31 I/O I/O
G33 I (M2) I (M2)
G35 I/O (LDC) I/O (LDC)
G37 I/O I/O
G39 I/O I/O
F2 N.C. N.C.
F4 GND GND
F6 I/O (A17) i/O (A17)
F8 I/O I/O
F10 I/O I/O
F12 I/O I/O
F14 I/O I/O
F16 I/O I/O
F18 N.C. I/O
F20 I/O I/O
F22 N.C. I/O
F24 I/O I/O
F26 I/O I/O
F28 I/O I/O
F30 I/O I/O
F32 I/O I/O
F34 I/O I/O
F36 VCC VCC
F38 I/O I/O
E1 I/O I/O
E3 I/O I/O
PG411 Pin XC4036EX/XL XC4044EX/XL
June 1, 1996 (Version 1.02) 4-169
3/26/96
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
E5 I/O (A14) I/O (A14)
E7 N.C. N.C.
E9 I/O I/O
E11 I/O, TMS I/O, TMS
E13 I/O I/O
E15 I/O I/O
E17 I/O I/O
E19 I/O I/O
E21 I/O I/O
E23 N.C. N.C.
E25 I/O I/O
E27 I/O I/O
E29 I/O I/O
E31 I/O I/O
E33 I/O I/O
E35 I (M0) I (M0)
E37 N.C. N.C.
E39 I/O I/O
D2 I/O I/O
D4 I/O I/O
D6 VCC VCC
D8 N.C. I/O
D10 I/O I/O
D12 N.C. N.C.
D14 GND GND
D16 I/O I/O
D18 I/O I/O
D20 GND GND
D22 I/O I/O
D24 I/O I/O
D26 GND GND
D28 I/O I/O
D30 N.C. I/O
D32 N.C. I/O
D34 GND GND
D36 I/O, GCK3 I/O, GCK3
D38 I/O I/O
C1 GND GND
C3 I/O I/O
C5 I/O I/O
C7 N.C. I/O
C9 I/O I/O
C11 I/O, FCLK1 I/O, FCLK1
C13 I/O I/O
C15 N.C. I/O
C17 I/O I/O
C19 I/O I/O
C21 I/O I/O
C23 N.C. I/O
C25 N.C. N.C.
C27 I/O I/O
C29 I/O, FCLK2 I/O, FCLK2
C31 I/O I/O
PG411 Pin XC4036EX/XL XC4044EX/XL C33 N.C. N.C.
C35 I/O I/O
C37 I/O (HDC) I/O (HDC)
C39 VCC VCC
B2 I/O, TDI I/O, TDI
B4 I/O I/O
B6 N.C. N.C.
B8 I/O I/O
B10 I/O I/O
B12 I/O I/O
B14 I/O I/O
B16 I/O I/O
B18 I/O I/O
B20 I/O I/O
B22 I/O I/O
B24 I/O I/O
B26 I/O I/O
B28 I/O I/O
B30 I/O I/O
B32 I/O I/O
B34 N.C. N.C.
B36 I/O, GCK2 I/O, GCK2
B38 I/O I/O
A3 VCC VCC
A5 I/O I/O
A7 I/O I/O
A9 GND GND
A11 VCC VCC
A13 N.C. N.C.
A15 I/O I/O
A17 I/O I/O
A19 GND GND
A21 VCC VCC
A23 I/O I/O
A25 I/O I/O
A27 I/O I/O
A29 GND GND
A31 VCC VCC
A33 I/O I/O
A35 I/O I/O
A37 GND GND
A39 O (M1) O (M1)
PG411 Pin XC4036EX/XL XC4044EX/XL
XC4000 Series Field Programmable Gate Arrays
4-170 June 1, 1996 (Version 1.02)
BG432 Package Pinouts
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
AL1 VCC VCC VCC
AL2 GND GND GND
AL3 GND GND GND
AL4 I/O I/O I/O
AL5 I/O I/O I/O
AL6 I/O I/O I/O
AL7 GND GND GND
AL8 I/O I/O I/O
AL9 GND GND GND
AL10 I/O I/O I/O
AL11 VCC VCC VCC
AL12 I/O I/O I/O
AL13 I/O I/O I/O
AL14 GND GND GND
AL15 N.C. I/O I/O
AL16 I/O I/O I/O
AL17 N.C. I/O I/O
AL18 GND GND GND
AL19 I/O I/O I/O
AL20 I/O I/O I/O
AL21 VCC VCC VCC
AL22 I/O I/O I/O
AL23 GND GND GND
AL24 I/O I/O I/O
AL25 GND GND GND
AL26 I/O I/O I/O
AL27 I/O I/O I/O
AL28 I/O I/O I/O
AL29 GND GND GND
AL30 GND GND GND
AL31 VCC VCC VCC
AK1 GND GND GND
AK2 GND GND GND
AK3 I/O I/O I/O
AK4 I/O I/O I/O
AK5 I/O I/O I/O
AK6 I/O I/O I/O
AK7 I/O I/O I/O
AK8 I/O I/O I/O
AK9 I/O I/O I/O
AK10 I/O I/O I/O
AK11 N.C. N.C. I/O
AK12 I/O I/O I/O
AK13 I/O I/O I/O
AK14 I/0 I/O I/O
AK15 I/O I/O I/O
AK16 I/O (INIT) I/O (INIT) I/O (INIT)
AK17 N.C. I/O I/O
AK18 I/O I/O I/O
AK19 I/O I/O I/O
AK20 I/O I/O I/O
AK21 I/O I/O I/O
AK22 I/O I/O I/O
AK23 I/O I/O I/O
AK24 N.C. I/O I/O
AK25 I/O I/O I/O
AK26 I/O I/O I/O
AK27 N.C. N.C. I/O
AK28 I/O I/O I/O
AK29 I/O, GCK3 I/O, GCK3 I/O, GCK3
AK30 GND GND GND
AK31 GND GND GND
AJ1 GND GND GND
AJ2 I/O (D7) I/O (D7) I/O (D7)
AJ3 VCC VCC VCC
AJ4 I/O, GCK4 I/O, GCK4 I/O, GCK4
AJ5 N.C. N.C. I/O
AJ6 I/O I/O I/O
AJ7 I/O I/O I/O
AJ8 N.C. I/O I/O
AJ9 I/O I/O I/O
AJ10 I/O I/O I/O
AJ11 I/O I/O I/O
AJ12 N.C. N.C. I/O
AJ13 I/O I/O I/O
AJ14 I/O I/O I/O
AJ15 N.C. I/O I/O
AJ16 I/O I/O I/O
AJ17 I/O I/O I/O
AJ18 I/O I/O I/O
AJ19 I/O I/O I/O
AJ20 N.C. N.C. I/O
AJ21 I/O I/O I/O
AJ22 I/O I/O I/O
AJ23 I/O I/O I/O
AJ24 I/O I/O I/O
AJ25 I/O I/O I/O
AJ26 N.C. N.C. I/O
AJ27 I/O I/O I/O
AJ28 I (M2) I (M2) I (M2)
AJ29 VCC VCC VCC
AJ30 I/O, GCK2 I/O, GCK2 I/O, GCK2
AJ31 GND GND GND
AH1 I/O I/O I/O
AH2 I/O I/O I/O
AH3 PROGRAM PROGRAM PROGRAM
AH4 DONE DONE DONE
AH5 I/O I/O I/O
AH6 N.C. N.C. I/O
AH7 I/O I/O I/O
AH8 I/O I/O I/O
AH9 N.C. I/O I/O
AH10 I/O I/O I/O
AH11 VCC VCC VCC
AH12 I/O I/O I/O
AH13 I/O I/O I/O
AH14 I/O I/O I/O
AH15 I/O I/O I/O
AH16 GND GND GND
AH17 I/O I/O I/O
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
June 1, 1996 (Version 1.02) 4-171
AH18 I/O I/O I/O
AH19 N.C. N.C. I/O
AH20 I/O I/O I/O
AH21 VCC VCC VCC
AH22 I/O I/O I/O
AH23 N.C. I/O I/O
AH24 I/O I/O I/O
AH25 I/O I/O I/O
AH26 I/O (LDC) I/O (LDC) I/O (LDC)
AH27 I/O (HDC) I/O (HDC) I/O (HDC)
AH28 I (M0) I (M0) I (M0)
AH29 O (M1) O (M1) O (M1)
AH30 I/O I/O I/O
AH31 I/O I/O I/O
AG1 N.C. N.C. I/O
AG2 I/O I/O I/O
AG3 I/O I/O I/O
AG4 I/O, GCK5 I/O, GCK5 I/O, GCK5
AG28 I/O I/O I/O
AG29 I/O I/O I/O
AG30 I/O I/O I/O
AG31 I/O I/O I/O
AF1 I/O (D6) I/O (D6) I/O (D6)
AF2 I/O I/O I/O
AF3 I/O I/O I/O
AF4 I/O I/O I/O
AF28 I/O I/O I/O
AF29 N.C. N.C. I/O
AF30 N.C. N.C. I/O
AF31 I/O I/O I/O
AE1 GND GND GND
AE2 I/O I/O I/O
AE3 I/O I/O I/O
AE4 N.C. N.C. I/O
AE28 I/O I/O I/O
AE29 I/O I/O I/O
AE30 I/O I/O I/O
AE31 GND GND GND
AD1 I/O I/O I/O
AD2 N.C. I/O I/O
AD3 I/O I/O I/O
AD4 I/O I/O I/O
AD28 I/O I/O I/O
AD29 I/O I/O I/O
AD30 N.C. I/O I/O
AD31 N.C. I/O I/O
AC1 GND GND GND
AC2 I/O I/O I/O
AC3 I/O I/O I/O
AC4 N.C. I/O I/O
AC28 I/O I/O I/O
AC29 I/O I/O I/O
AC30 I/O I/O I/O
AC31 GND GND GND
AB1 I/O, FCLK3 I/O, FCLK3 I/O, FCLK3
AB2 I/O I/O I/O
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
AB3 I/O I/O I/O
AB4 I/O I/O I/O
AB28 I/O I/O I/O
AB29 I/O, FCLK2 I/O, FCLK2 I/O, FCLK2
AB30 I/O I/O I/O
AB31 I/O I/O I/O
AA1 VCC VCC VCC
AA2 I/O (D5) I/O (D5) I/O (D5)
AA3 I/O I/O I/O
AA4 VCC VCC VCC
AA28 VCC VCC VCC
AA29 I/O I/O I/O
AA30 I/O I/O I/O
AA31 VCC VCC VCC
Y1 N.C. N.C. I/O
Y2 I/O (CS0) I/O (CS0) I/O (CS0)
Y3 I/O I/O I/O
Y4 I/O I/O I/O
Y28 I/O I/O I/O
Y29 I/O I/O I/O
Y30 I/O I/O I/O
Y31 N.C. N.C. I/O
W1 N.C. N.C. I/O
W2 N.C. I/O I/O
W3 I/O I/O I/O
W4 I/O I/O I/O
W28 N.C. N.C. I/O
W29 I/O I/O I/O
W30 I/O I/O I/O
W31 N.C. I/O I/O
V1 GND GND GND
V2 N.C. I/O I/O
V3 I/O I/O I/O
V4 I/O I/O I/O
V28 N.C. I/O I/O
V29 I/O I/O I/O
V30 I/O I/O I/O
V31 GND GND GND
U1 I/O I/O I/O
U2 I/O I/O I/O
U3 I/O I/O I/O
U4 I/O I/O I/O
U28 I/O I/O I/O
U29 I/O I/O I/O
U30 I/O I/O I/O
U31 I/O I/O I/O
T1 I/O (D4) I/O (D4) I/O (D4)
T2 I/O I/O I/O
T3 I/O (D3) I/O (D3) I/O (D3)
T4 GND GND GND
T28 GND GND GND
T29 I/O I/O I/O
T30 I/O I/O I/O
T31 I/O I/O I/O
R1 I/O (RS) I/O (RS) I/O (RS)
R2 I/O I/O I/O
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
XC4000 Series Field Programmable Gate Arrays
4-172 June 1, 1996 (Version 1.02)
R3 I/O I/O I/O
R4 I/O I/O I/O
R28 I/O I/O I/O
R29 I/O I/O I/O
R30 I/O I/O I/O
R31 I/O I/O I/O
P1 GND GND GND
P2 I/O I/O I/O
P3 I/O I/O I/O
P4 I/O I/O I/O
P28 I/O I/O I/O
P29 I/O I/O I/O
P30 I/O I/O I/O
P31 GND GND GND
N1 N.C. I/O I/O
N2 N.C. I/O I/O
N3 I/O I/O I/O
N4 I/O I/O I/O
N28 I/O I/O I/O
N29 N.C. I/O I/O
N30 N.C. I/O I/O
N31 I/O I/O I/O
M1 I/O I/O I/O
M2 I/O I/O I/O
M3 N.C. N.C. I/O
M4 N.C. N.C. I/O
M28 N.C. N.C. I/O
M29 I/O I/O I/O
M30 N.C. N.C. I/O
M31 I/O I/O I/O
L1 VCC VCC VCC
L2 I/O (D2) I/O (D2) I/O (D2)
L3 I/O I/O I/O
L4 VCC VCC VCC
L28 VCC VCC VCC
L29 I/O I/O I/O
L30 I/O I/O I/O
L31 VCC VCC VCC
K1 I/O I/O I/O
K2 I/O, FCLK4 I/O, FCLK4 I/O, FCLK4
K3 I/O I/O I/O
K4 I/O I/O I/O
K28 I/O, FCLK1 I/O, FCLK1 I/O, FCLK1
K29 I/O I/O I/O
K30 I/O, TMS I/O, TMS I/O, TMS
K31 I/O I/O I/O
J1 GND GND GND
J2 I/O I/O I/O
J3 I/O I/O I/O
J4 I/O I/O I/O
J28 I/O I/O I/O
J29 I/O I/O I/O
J30 I/O I/O I/O
J31 GND GND GND
H1 I/O I/O I/O
H2 I/O I/O I/O
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
H3 I/O I/O I/O
H4 I/O I/O I/O
H28 I/O I/O I/O
H29 I/O I/O I/O
H30 I/O I/O I/O
H31 I/O I/O I/O
G1 GND GND GND
G2 I/O I/O I/O
G3 N.C. I/O I/O
G4 I/O (D1) I/O (D1) I/O (D1)
G28 I/O I/O I/O
G29 I/O I/O I/O
G30 I/O I/O I/O
G31 GND GND GND
F1 N.C. I/O I/O
F2 I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY) I/O (RCLK,
RDY/BUSY)
F3 I/O I/O I/O
F4 N.C. N.C. I/O
F28 N.C. N.C. I/O
F29 N.C. N.C. I/O
F30 N.C. I/O I/O
F31 N.C. I/O I/O
E1 I/O I/O I/O
E2 N.C. N.C. I/O
E3 I/O I/O I/O
E4 I/O I/O I/O
E28 I/O I/O I/O
E29 I/O I/O I/O
E30 I/O I/O I/O
E31 I/O I/O I/O
D1 I/O I/O I/O
D2 I/O I/O I/O
D3 I/O, GCK6
(DOUT) I/O, GCK6
(DOUT) I/O, GCK6
(DOUT)
D4 CCLK CCLK CCLK
D5 I/O, GCK7 (A1) I/O, GCK7 (A1) I/O, GCK7 (A1)
D6 N.C. N.C. I/O
D7 I/O (A3) I/O (A3) I/O (A3)
D8 I/O I/O I/O
D9 I/O I/O I/O
D10 I/O I/O I/O
D11 VCC VCC VCC
D12 I/O I/O I/O
D13 N.C. N.C. I/O
D14 I/O I/O I/O
D15 I/O I/O I/O
D16 GND GND GND
D17 I/O (A8) I/O (A8) I/O (A8)
D18 I/O (A18) I/O (A18) I/O (A18)
D19 I/O I/O I/O
D20 N.C. N.C. I/O
D21 VCC VCC VCC
D22 I/O I/O I/O
D23 N.C. I/O I/O
D24 I/O (A12) I/O (A12) I/O (A12)
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
June 1, 1996 (Version 1.02) 4-173
3/26/96
Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
ent devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
D25 I/O I/O I/O
D26 N.C. N.C. I/O
D27 I/O I/O I/O
D28 I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK8 (A15)
D29 I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, GCK1 (A16)
D30 I/O, TDI I/O, TDI I/O, TDI
D31 I/O, TCK I/O, TCK I/O, TCK
C1 GND GND GND
C2 I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN)
C3 VCC VCC VCC
C4 O, TDO O, TDO O, TDO
C5 I/O I/O I/O
C6 I/O I/O I/O
C7 I/O I/O I/O
C8 N.C. N.C. N.C.
C9 I/O I/O I/O
C10 I/O I/O I/O
C11 I/O I/O I/O
C12 I/O I/O I/O
C13 I/O I/O I/O
C14 I/O (A4) I/O (A4) I/O (A4)
C15 I/O (A21) I/O (A21) I/O (A21)
C16 N.C. I/O I/O
C17 N.C. I/O I/O
C18 I/O (A19) I/O (A19) I/O (A19)
C19 I/O (A11) I/O (A11) I/O (A11)
C20 I/O I/O I/O
C21 I/O I/O I/O
C22 I/O I/O I/O
C23 I/O I/O I/O
C24 I/O I/O I/O
C25 I/O I/O I/O
C26 I/O I/O I/O
C27 I/O I/O I/O
C28 I/O (A14) I/O (A14) I/O (A14)
C29 VCC VCC VCC
C30 I/O (A17) I/O (A17) I/O (A17)
C31 GND GND GND
B1 GND GND GND
B2 GND GND GND
B3 I/O (A0, WS) I/O (A0, WS) I/O (A0, WS)
B4 I/O I/O I/O
B5 I/O I/O I/O
B6 I/O I/O I/O
B7 I/O I/O I/O
B8 N.C. I/O I/O
B9 I/O I/O I/O
B10 I/O I/O I/O
B11 I/O I/O I/O
B12 N.C. N.C. I/O
B13 I/O I/O I/O
B14 I/O I/O I/O
B15 I/O (A20) I/O (A20) I/O (A20)
B16 I/O (A6) I/O (A6) I/O (A6)
B17 N.C. I/O I/O
B18 I/O I/O I/O
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
B19 I/O (A10) I/O (A10) I/O (A10)
B20 I/O I/O I/O
B21 N.C. N.C. I/O
B22 I/O I/O I/O
B23 I/O I/O I/O
B24 I/O I/O I/O
B25 N.C. I/O I/O
B26 I/O (A13) I/O (A13) I/O (A13)
B27 I/O I/O I/O
B28 I/O I/O I/O
B29 I/O I/O I/O
B30 GND GND GND
B31 GND GND GND
A1 VCC VCC VCC
A2 GND GND GND
A3 GND GND GND
A4 N.C. N.C. I/O
A5 I/O (CS1, A2) I/O (CS1, A2) I/O (CS1, A2)
A6 I/O I/O I/O
A7 GND GND GND
A8 N.C. I/O I/O
A9 GND GND GND
A10 I/O I/O I/O
A11 VCC VCC VCC
A12 I/O I/O I/O
A13 I/O (A5) I/O (A5) I/O (A5)
A14 GND GND GND
A15 N.C. I/O I/O
A16 I/O (A7) I/O (A7) I/O (A7)
A17 I/O (A9) I/O (A9) I/O (A9)
A18 GND GND GND
A19 I/O I/O I/O
A20 I/O I/O I/O
A21 VCC VCC VCC
A22 I/O I/O I/O
A23 GND GND GND
A24 I/O I/O I/O
A25 GND GND GND
A26 I/O I/O I/O
A27 I/O I/O I/O
A28 N.C. N.C. I/O
A29 GND GND GND
A30 GND GND GND
A31 VCC VCC VCC
BG432 Pin XC4036EX
XC4036XL XC4044EX
XC4044XL XC4052XL
XC4000 Series Field Programmable Gate Arrays
4-174 June 1, 1996 (Version 1.02)
Product Availability
Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office
for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the
specifications.
C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.
Table 25: Component Availability Chart for XC4000E FPGAs
Speed
Grade PC
84 PQ
100 VQ
100 PG
120 TQ
144 PG
156 PQ
160 CB
164 PG
191 CB
196 PQ
208 HQ
208 PG
223 BG
225 CB
228 PQ
240 HQ
240 PG
299 HQ
304
XC
4003E -4 C I C I C I C I
-3 CCCC
-2 CCCC
XC
4005E
-4 C I C I C I C I
M B C I M B C I
-3 C C CCC C
-2 C C CCC C
XC
4006E -4 C I C I C I C I C I
-3 C CCC C
-2 C CCC C
XC
4008E -4 C I C I C I C I
-3 C C C C
-2 C C C C
XC
4010E
-4 C I C I C I
MB MB C I C I C I
-3 C C C CC C
-2 C C C CC C
XC
4013E
-4 C I C I C I C I
M B C I M B C I C I
-3 C CCCC CC
-2 C CCCC CC
XC
4020E
-4 C I C I C I
-3 CC C
-2 CC C
XC
4025E
-4 C I M B C I C I
M B C I
-3 CCCC
-2 CCCC
June 1, 1996 (Version 1.02) 4-175
C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.
C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.
Speed grades for the XC4000XL have not yet been determined.
Table 26: Component Availability Chart for XC4000EX FPGAs
Speed
Grade HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432
XC4028EX -4 C I C I C I C I C I
-3CCCCC
XC4036EX -4 C I C I C I
-3 CCC
XC4044EX -4 C I C I
-3 CC
Table 27: Component Availability Chart for XC4000L and XC4000XL FPGAs
Speed
Grade PC
84 TQ
176 PQ
208 HQ
208 BG
225 PQ
240 HQ
240 PG
299 HQ
304 BG
352 PG
411 BG
432 PG
475
XC4005L -6 C C
-5 C C
-4
XC4010L -6CCC
-5CCC
-4
XC4013L -6 C CC
-5 C CC
-4
XC4028XL CCCCC
XC4036XL CCC
XC4044XL CC
XC4052XL CC
XC4062XL C
XC4000 Series Field Programmable Gate Arrays
4-176 June 1, 1996 (Version 1.02)
User I/O Per Package
Maximum available user I/O for each device/package combination is shown in Table 28 - Table 30.
Pinout tables f or XC4000-Series de vices f ollow. Pinout data is off ered in tw o f orms, as de vice-specific and package-specific
tables. Device-specific tables include all packages for each XC4000-Series device. They follow the pad locations around
the die, and include boundary scan register locations. Pac kage-specific tables include all XC4000-Series devices available
in a given package. These tables are especially useful in determining which pads should be avoided, in case of a future
transition to a different device in the same package.
All pinouts defined at the time of publication are included in these tab les . Additional information may be a v ailab le . Call your
local sales office or see the Xilinx WEBLINX at http://www.xilinx.com for the latest information.
Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)
Table 28: Maximum User I/O for XC4000E Device/Package Combinations
No. of
Pins Package
(Code) XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E
Maximum User I/O 80 112 128 144 160 192 224 256
84 PLCC (PC) 61 61 61 61 61
100 PQFP (PQ) 77 77
VQFP (VQ) 77
120 PGA (PG) 80
144 TQFP (TQ) 112 113
156 PGA (PG) 112 125
160 PQFP (PQ) 112 128 129 129 129
164 CBFP (CB) 112
191 PGA (PG) 144 160
196 CBFP (CB) 160
208 PQFP (PQ) 112 128 144 160 160
HQFP (HQ) 160 160 160
223 PGA (PG) 192 192 192
225 BGA (BG) 160 192
228 CBFP (CB) 192 192
240 PQFP (PQ) 192
HQFP (HQ) 192 193 193
299 PGA (PG) 256
304 HQFP (HQ) 256
June 1, 1996 (Version 1.02) 4-177
Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)
Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)
Table 29: Maximum User I/O for XC4000EX Device/Package Combinations
No. of Pins Package (Code) XC4028EX XC4036EX XC4044EX
Maximum User I/O 256 288 320
208 HQFP (HQ) 160
240 HQFP (HQ) 193
299 PGA (PG) 256
304 HQFP (HQ) 256 256
352 BGA (BG) 256
411 PGA (PG) 288 320
432 BGA (BG) 288 320
Table 30: Maximum User I/O for XC4000L and XC4000XL Device/Package Combinations
No. of
Pins Package
(Code) XC4005L XC4010L XC4013L XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL
Maximum User I/O 112 160 192 256 288 320 352 384
84 PLCC (PC) 61 61
176 TQFP (TQ) 153
208 PQFP (PQ) 112 160 160
208 HQFP (HQ) 160
225 BGA (BG) 192
240 PQFP (PQ) 192
240 HQFP (HQ) 193
299 PGA (PG) 256
304 HQFP (HQ) 256 256
352 BGA (BG) 256
411 PGA (PG) 288 320 352
432 BGA (BG) 288 320 352
475 PGA (PG) 384
XC4000 Series Field Programmable Gate Arrays
4-178 June 1, 1996 (Version 1.02)
Ordering Information
XC4013E-3HQ240C
Device Type
Speed Grade
-6
-5
-4
-3
-2 Number of Pins
Package Type
Temperature Range
C = Commercial (TJ = 0 to +85°C)
I = Industrial (TJ = -40 to +100°C)
M = Military (TC = -55 to+125°C)
PC = Plastic Lead Chip Carrier
PQ = Plastic Quad Flat Pack
VQ = Very Thin Quad Flat Pack
TQ = Thin Quad Flat Pack
BG = Ball Grid Array
PG = Ceramic Pin Grid Array
HQ = High Heat Dissipation Quad Flat Pack
MQ = Metal Quad Flat Pack
CB = Top Brazed Ceramic Quad Flat Pack
X6750
Example:
4-179
XC5200 Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-181
XC5200 Family Compared to XC4000 and XC3000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-182
Configurable Logic Block (CLB) Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-182
Input/Output Block (IOB) Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-183
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-184
VersaBlock: Abundant Local Routing Plus Versatile Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-184
VersaRing I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
General Routing Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-185
Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-186
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-186
Design Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
CLB Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
5-Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-188
Carry Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-189
Cascade Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-190
3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Global Reset (GR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-191
VersaBlock Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
Local Interconnect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
Direct Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-192
General Routing Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Single- and Double-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
Global Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194
VersaRing Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-197
Unrestricted User-Programmable I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-198
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Daisy Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-199
Express Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-200
Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-200
Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Power-On Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
XC5200 Series Table of Contents
XC5200 Series Table of Contents
4-180
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Start-Up and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-203
Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204
Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
Slave and Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-205
XC5200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-206
XC5200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-207
XC5200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-207
XC5200 Longline Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-208
XC5200 CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-209
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . 4-210
XC5200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-211
XC5200 CLB-to-Pad Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-212
Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-223
Pin Locations for XC5202 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-223
Pin Locations for XC5204 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-226
Pin Locations for XC5206 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-230
Pin Locations for XC5210 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-235
Pin Locations for XC5215 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
User I/O Per Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-248
XC5200L Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-249
XC5200L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
XC5200L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-250
June 1, 1996 (Version 4.0) 4-181
Features
• High-density family of Field-Programmable Gate Arrays
(FPGAs)
• Design- and process-optimized for low cost
- 0.6-µm three-layer metal (TLM) process
• System performance up to 50 MHz
• SRAM-based, in-system reprogrammable architecture
• Flexible architecture with abundant routing resources
- VersaBlock™ logic module
- VersaRing™ I/O interface
- Dedicated cell-feedthrough path
- Hierarchical interconnect structure
- Extensive registers/latches
- Dedicated carry logic for arithmetic functions
- Cascade chain for wide input functions
- Dedicated IEEE 1149.1 boundary-scan logic
- Internal 3-state bussing capability
- Four global low-skew clock or signal distribution nets
- Globally selectable CMOS or TTL input thresholds
- Output slew-rate control
- 8-mA sink current per output
• Configured by loading binary file
- Unlimited reprogrammability
- Seven programming modes, including high-speed
Express™ mode
• 100% factory tested
• 100% footprint compatibility for common packages
• Fully supported by XACT
step
™ Development System
- Includes complete support for XACT-Performance™,
X-BLOX™, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
- Wide selection of PC and workstation platforms
- Interfaces to more than 100 third-party CAE tools
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for three-layer
metal (TLM) technology and a 0.6-µm CMOS SRAM pro-
cess, dramatic advances have been made in silicon effi-
ciency. These advances position the XC5200 family as a
cost-effective, high-volume alternative to gate arrays.
Building on experiences gained with three previous suc-
cessful SRAM FPGA families, the XC5200 family brings a
robust feature set to high-density programmable logic
design. The VersaBlock logic module, the VersaRing I/O
interface, and a rich hierarchy of interconnect resources
combine to enhance design flexibility and reduce time-to-
market.
Complete support for the XC5200 family is delivered
through the familiar XACT
step
software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and syn-
thesis. Designers utilizing logic synthesis can use their
existing tools to design with the XC5200 devices.
XC5200
Field Programmable Gate Arrays
June 1, 1996 (Version 4.0) Preliminary Product Specification
Table 1: Initial XC5200 Field-Programmable Gate Array Family Members
Device XC5202 XC5204 XC5206 XC5210 XC5215
Max Logic Gates 3,000 6,000 10,000 16,000 23,000
Typical Gate Range 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 10,000 - 16,000 15,000 - 23,000
VersaBlock Array 8 x 8 10 x 12 14 x 14 18 x 18 22 x 22
Number of CLBs 64 120 196 324 484
Number of Flip-Flops 256 480 784 1,296 1,936
Number of I/Os 84 124 148 196 244
TBUFs per Horizontal Longline 10 14 16 20 24
XC5200 Field Programmable Gate Arrays
4-182 June 1, 1996 (Version 4.0)
XC5200 Family Compared to XC4000
and XC3000 Series
For readers already familiar with the XC4000 and XC3000
gate array series, this section describes significant differ-
ences between them and the XC5200 family. Unless other-
wise indicated, comparisons refer to both XC4000 and
XC3000 devices.
Configurable Logic Block (CLB) Resources
Each XC5200 CLB contains four independent 4-input func-
tion generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The output from the
function generator in each LC can be brought out as a CLB
output and/or drive the D input of the register. A pair of LCs
can be combined to form a 5-input function generator.
There are four direct feedthrough paths for each XC5200
CLB, one per LC . These paths pro vide extra data input lines
or serve as additional local routes without consuming any
logic resources.
The registers in each XC5200 LC are optionally config-
urable as edge-triggered D-type flip-flops or as transparent
level-sensitive latches.
The XC5200 CLB includes dedicated carry logic that pro-
vides fast arithmetic carry capability. The dedicated carry
logic may also be used to cascade function generators for
implementing wide arithmetic functions.
XC4000 family:
XC5200 devices have no wide edge
decoders.
XC4000 family:
XC5200 dedicated carry logic differs from
that of the XC4000 family in that the sum is gener ated in an
additional function generator in the adjacent column. An
XC5200 device thus uses twice as many function genera-
tors for adders, subtracters, accumulators, and some
counters. Note, however, that a loadable up/down counter
requires the same number of function generators in both
families.
XC4000 family:
XC5200 lookup tables cannot be used as
RAM.
Table 2: Four Generations of Xilinx Field-Programmable Gate Array Families
Parameter XC5200 XC4000 XC3000A/XC3100A XC2000
Function generators per CLB 4 3 2 2
Logic inputs per CLB 20 9 5 4
Logic outputs per CLB 12 4 2 2
Low-skew global buffers 4 8 2 2
Single-length lines 10 8 5 4
Double-length lines 4 4 0 0
Longlines 8 6 3 2
Direct connects 8 0 2 2
VersaRing yes no no no
User RAM no yes no no
Dedicated decoders no yes no no
Cascade chain yes no no no
Fast carry logic yes yes no no
Internal 3-state drivers yes yes yes no
IEEE boundary scan yes yes no no
Output slew-rate control yes yes yes no
Power-down option no no yes yes
Crystal oscillator circuit no no yes yes
June 1, 1996 (Version 4.0) 4-183
Input/Output Block (IOB) Resources
The XC5200 family maintains footprint compatibility with
the XC4000 family, but not with the XC3000 family.
The XC5200 IOB does not include flip-flops or latches. The
XC5200 family provides direct connections from each IOB
to the registers in the adjacent CLB in order to emulate IOB
registers.
The XC5200 IOB provides a programmable delay element
to control input set-up time. This element can be used to
avoid potential hold-time problems.
Each XC5200 IOB is capable of 8-mA source and sink cur-
rents.
IEEE 1149.1-type boundary scan is supported in each
XC5200 IOB.
XC3000 family:
Each XC5200 IOB has access to tristat-
able Longlines by means of its own 3-state buffer (TBUF).
Routing Resources
The XC5200 family pro vides a fle xib le coupling of logic and
local routing resources called the VersaBlock. The XC5200
VersaBlock element includes the CLB , a Local Interconnect
Matrix (LIM), and direct connects to neighboring Vers-
aBlocks.
Each XC5200 VersaBlock element has complete intra-CLB
routing, the LIM, and offers four direct routing connections
to each of the four neighboring CLBs. Any function genera-
tor or flip-flop thus has unrestricted connectivity to 19 other
function generators or flip-flops: three in its own CLB, and
16 in the adjacent CLBs. These direct connects do not
compete with the general routing resources (see Table 2).
There is a special routing resource, the VersaRing,
between the outer edge of the core CLB array and the ring
of IOBs, providing added routability to the I/O. This feature
is particularly important for designs that require a fixed
pinout prior to completion.
The XC5200 provides four global buffers for clocking or
high-fanout control signals. Each buffer may be sourced by
means of its dedicated pad or from any internal source.
Each XC5200 TBUF can drive up to two horizontal Lon-
glines.
There are no internal pull-ups for XC5200 Longlines.
Configuration and Readback
XC4000 family:
The XC5200 family provides a global
reset but not a global set.
XC5200 devices use a different configuration process than
that of the XC3000 family, but use the same process as the
XC4000 family. The rest of this discussion compares
XC5200 features with those of the XC3000 family only.
Although their configuration processes differ, XC5200
devices may be used in daisy chains with XC3000 devices.
The XC5200 PROGRAM pin is a single-function input pin
that overrides all other inputs.
The XC5200 INIT pin also acts as a Configuration Error
output.
XC5200 devices support two additional programming
modes: Peripheral Synchronous and the new high-speed
Express mode.
XC5200 start-up can be synchronized to any user clock by
means of a configuration option.
The XC5200 family does not support Power-down, but
offers a Global 3-state input that does not reset any flip-
flops.
The XC5200 family does not provide an on-chip crystal
oscillator amplifier, but it does provide an internal oscillator
from which a variety of frequencies up to 16 MHz are avail-
able.
Readback in the XC5200 family either ignores the flip-flop
content, thereby a voiding the need f or masking, or it takes a
snapshot of all flip-flops at the start of Readback.
Readback in the XC5200 family has the same polarity as
Configuration, and can be aborted.
XC5200 Field Programmable Gate Arrays
4-184 June 1, 1996 (Version 4.0)
Architectural Overview
Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs, program-
mable logic b loc ks , and prog r ammab le interconnect. Unlike
other FPGAs, however, the logic and local routing
resources of the XC5200 family are combined in flexible
VersaBlocks. General-purpose routing connects to the
VersaBlock through the General Routing Matrix (GRM).
VersaBlock: Abundant Local Routing Plus
Versatile Logic
The basic logic element in each VersaBlock structure is the
Logic Cell, shown in Figure 2. Each LC contains a 4-input
function generator (F), a storage device (FD), and control
logic. There are five independent inputs and three outputs
to each LC. The independence of the inputs and outputs
allows the software to maximize the resource utilization
within each LC. Each Logic Cell also contains a direct
feedthrough path that does not sacrifice the use of either
the function generator or the register; this feature is a first
for FPGAs . The storage de vice is configur able as either a D
flip-flop or a latch. The control logic consists of carry logic
for fast implementation of arithmetic functions, which can
also be configured as a cascade chain allowing decode of
very wide input functions.
The XC5200 CLB consists of four LCs, as shown in
Figure 3. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The chal-
lenge of FPGA implementation software has always been
to maximize the usage of logic resources. The XC5200
family addresses this issue by surrounding each CLB with
two types of local interconnect — the Local Interconnect
Matrix (LIM) and direct connects. These two interconnect
resources, combined with the CLB, form the VersaBlock,
represented in Figure 4.
The LIM provides 100% connectivity of the inputs and out-
puts of each LC in a given CLB. The benefit of the LIM is
that no general routing resources are required to connect
feedback paths within a CLB. The LIM connects to the
GRM via 24 bidirectional nodes.
The direct connects allow immediate connections to
neighboring CLBs, once again without using any of the
general interconnect. These two layers of local routing
resource improve the granularity of the architecture,
effectively making the XC5200 family a “sea of logic cells.”
Each VersaBlock has four 3-state buffers that share a
common enable line and directly drive horizontal Longlines ,
creating robust on-chip bussing capability. The VersaBlock
allows fast, local implementation of logic functions,
effectively implementing user designs in a hierarchical
fashion. These resources also minimize local routing
congestion and improve the efficiency of the general
interconnect, which is used for connecting larger groups of
logic. It is this combination of both fine-grain and coarse-
grain architecture attributes that maximize logic utilization
in the XC5200 family. This symmetrical structure takes full
advantage of the third metal layer, freeing the placement
software to pack user logic optimally with minimal routing
restrictions.
Figure 1: XC5200 Architectural Overview
X4955
GRM
Input/Output Blocks (IOBs)
Versa-
Block
GRM
Versa-
Block
VersaRing
VersaRing
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
VersaRing
VersaRing
Figure 2: XC5200 Logic Cell (Four LCs per CLB)
X4956
F4
F3 F
FD
F2
F1
DQ
X
DO
DI
CO
CI CE CK CLR
June 1, 1996 (Version 4.0) 4-185
VersaRing I/O Interface
The interface between the IOBs and core logic has been
redesigned in the XC5200 family. The IOBs are completely
decoupled from the core logic. The XC5200 IOBs contain
dedicated boundary-scan logic for added board-level test-
ability, but do not include input or output registers. This
approach allows a maximum number of IOBs to be placed
around the device, improving the I/O-to-gate ratio and
decreasing the cost per I/O. A “freeway” of interconnect
cells surrounding the device forms the VersaRing, which
provides connections from the IOBs to the internal logic
These incremental routing resources provide abundant
connections from each IOB to the nearest VersaBlock, in
addition to Longline connections surrounding the device.
The VersaRing eliminates the historic trade-off between
high logic utilization and pin placement flexibility. These
incremental edge resources give users increased flexibility
in preassigning (i.e., locking) I/O pins before completing
their logic designs. This ability accelerates time-to-market,
since PCBs and other system components can be manu-
factured concurrent with the logic design.
General Routing Matrix
The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight cou-
pling to the logic resources contained in the VersaBlocks.
Advanced simulation tools were used during the develop-
ment of the XC5200 architecture to determine the optimal
lev el of routing resources required. The XC5200 family con-
tains six levels of interconnect hierarchy — a series of sin-
gle-length lines, double-length lines, and Longlines all
routed through the GRM. The direct connects, LIM, and
logic-cell feedthrough are contained within each Vers-
aBlock. Throughout the XC5200 interconnect, an efficient
multiplexing scheme, in combination with three layer metal
(TLM), was used to improve the overall efficiency of silicon
usage.
Performance Overview
The XC5200 family has been benchmarked with many
designs running synchronous clock rates up to 50 MHz.
The performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the intercon-
nect routing. Table 3 shows some perf ormance numbers for
representative circuits. A rough estimate of timing can be
made by assuming 6 ns per logic level, which includes
direct-connect routing delays. More accurate estimations
can be made using the information in the Switching Char-
acteristic Guideline section.
Figure 3: Configurable Logic Block
Figure 4: VersaBlock
X4957
F4
F3 F
FD
LC3
LC2
LC1
LC0
F2
F1
DQ
X
DO
DI
CO
F4
F3 F
FD
F2
F1
DQ
X
DO
DI
F4
F3 F
FD
F2
F1
DQ
X
DO
DI
F4
F3 F
FD
F2
F1
DQ
X
DO
DI
CI CE CK CLR
LC0
X5707
CLB
Direct Connects
TS
GRM
LIM
4
4
4
4
4
LC3
LC2
LC1
LC0
44
44
24
24
XC5200 Field Programmable Gate Arrays
4-186 June 1, 1996 (Version 4.0)
Development System
The powerful features of the XC5200 device family require
an equally powerful, yet easy-to-use, set of development
tools. Xilinx provides an enhanced version of the Xilinx
Automatic CAE Tools (XACT
step
), optimized for the
XC5200 family.
As with other logic technologies, the basic methodology for
XC5200 FPGA design consists of three interrelated
steps: design entry, implementation, and verification. Pop-
ular generic tools are used for entry and simulation (for
example, Viewlogic Systems’s Viewdraw schematic editor
and Viewsim simulator), but architecture-specific tools are
needed for implementation.
Several advanced features of the XACT
step
system facili-
tate XC5200 FPGA design. RPMs — schematic-based
macros with relative location constraints to guide their
placement within the FPGA — help to ensure an optimized
implementation for common logic functions. An abundance
of local routing permits RPMs to be contained within a sin-
gle VersaBlock or to span across multiple VersaBlocks.
XACT-P erf ormance allows designers to enter the exact per-
formance requirements during design entry, at the sche-
matic level, to guide PPR.
Design Entry
Designs can be entered graphically, using schematic-cap-
ture software, or in any of sev eral text-based f ormats (such
as Boolean equations, state-machine descriptions, and
high-level design languages).
Xilinx and third-par ty CAE vendors have developed library
and interface products compatible with a wide variety of
design-entry and simulation environments. A standard
interface-file specification, Xilinx Netlist File (XNF), is pro-
vided to simplify file transfers into and out of the XACT
step
development system.
Xilinx offers XACT
step
development system interfaces to
the following design environments:
• Xilinx Foundation Series
• Viewlogic Systems (Viewdraw, Viewsim)
• Mentor Graphics V8 (NETED, QuickSim, Design
Architect, QuickSim II)
• OrCAD (SDT, VST)
• Synopsys (Design Compiler, FPGA Compiler)
• Xilinx-ABEL (State Machine module generator)
• X-BLOX (Graphical Mode Generator)
Many other en vironments are supported by third-party ven-
dors. Currently, more than 100 packages are supported.
The unified schematic library for the XC5200 FPGA reflects
the wide variety of logic functions that can be implemented
in these versatile devices. The library contains over 400
primitives and macros, ranging from 2-input AND gates to
16-bit accumulators, and includes arithmetic functions,
comparators, counters , data registers, decoders, encoders ,
I/O functions, latches, Boolean functions , m ultiplex ers , shift
registers, and barrel shifters.
Designing with macros is as easy as designing with stan-
dard SSI/MSI functions. The “soft macro” library contains
detailed descriptions of common logic functions, but does
not contain any partitioning or routing information. The per-
formance of these macros depends, therefore, on how the
PPR software processes the design. RPMs, on the other
hand, do contain predetermined partitioning and relative
placement information, resulting in an optimized implemen-
tation for these functions . Users can create their o wn library
elements — either soft macros or RPMs — based on the
macros and primitives of the standard library.
The X-BLOX design language is a graphics-based high-
level description language (HDL) that allows designers to
use a schematic editor to enter designs as a set of generic
modules. The X-BLOX compiler synthesizes and optimizes
the modules for the target device architecture, automati-
cally choosing the appropriate architectural resources for
each function.
The XACT
step
design environment supports hierarchical
design entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic in each block. The implementation tools automatically
combine the hierarchical elements of a design. Different
Table 3: Performance for Several Common Circuit Functions
Function XC5200 Speed Grade
-6 -5 -4 -3
16-bit Decoder from Input Pad 9 ns 8 ns 7 ns 6 ns
24-bit Accumulator 32 MHz 39 MHz 45 MHz 50 MHz
16-to-1 Multiplexer 16 ns 13 ns 11 ns 9 ns
16-bit Unidirectional Loadable Counter 40 MHz 50 MHz 59 MHz 65 MHz
16-bit U/D Counter 40 MHz 50 MHz 59 MHz 65 MHz
16-bit Adder 24 ns 20 ns 17 ns 15 ns
24-bit Loadable U/D Counter 36 MHz 42 MHz 48 MHz 52 MHz
Preliminary Advance
June 1, 1996 (Version 4.0) 4-187
hierarchical elements can be specified with diff erent design
entry tools, allowing the use of the most convenient entry
method for each portion of the design.
Design Implementation
The design implementation tools satisfy the requirements
for an automated design process. Logic par titioning, block
placement, and signal routing are performed by the PPR
program. The partitioner takes the logic from the entered
design and maps the logic into the architectural resources
of the FPGA (such as the logic blocks, I/O blocks, and 3-
state buffers). The placer then determines the best loca-
tions for the b loc ks, depending on their connectivity and the
required performance. The router finally connects the
placed blocks together.
The PPR algorithms support fully automatic implementa-
tion of most designs. Howev er, for demanding applications,
the user may exercise various degrees of control over the
automated implementation process. Optionally, user-desig-
nated par titioning, placement, and routing information can
be specified as part of the design-entry process. The imple-
mentation of highly structured designs can benefit greatly
from the basic floorplanning techniques familiar to design-
ers of large gate arrays.
The PPR program includes XACT-Performance, a feature
that allows designers to specify the timing requirements
along entire paths during design entry. Timing path analysis
routines in PPR then recognize and accommodate the
user-specified requirements. Timing requirements can be
entered on the schematic in a form directly relating to the
system requirements (such as the targeted minimum clock
frequency, or the maximum allowable delay on the data
path between two registers). So, while the timing of each
individual net is not predictable, the overall performance of
the system along entire signal paths is automatically tai-
lored to match user-generated specifications.
Design Verification
The high dev elopment cost associated with common mask-
programmed gate arrays necessitates extensive sim ulation
to verify a design. Due to the custom nature of mask ed gate
arrays, mistakes or last-minute design changes cannot be
tolerated. A gate-array designer must simulate and test all
logic using simulation software. Simulation describes what
happens in a system under worst-case situations. Howe v er ,
simulation can be tedious and slow, and simulation vectors
must be generated. A few seconds of system time can tak e
weeks to simulate.
Programmable-gate-array users, however, can use in-cir-
cuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogrammable, designs can
be verified in real time without the need for e xtensive simu-
lation vectors.
The XACT
step
development system supports both simula-
tion and in-circuit debugging techniques. For simulation,
the system extracts the post-layout timing information from
the design database. This data can then be sent to the sim-
ulator to verify timing-critical portions of the design data-
base using XDELAY, the Xilinx static timing analyzer tool.
Back-annotation — the process of mapping the timing inf or-
mation back into the signal names and symbols of the
schematic — eases the debugging effort.
For in-circuit debugging, the XACT
step
development sys-
tem includes a serial download and readback cable
(XChecker) that connects the FPGA in the system to the
PC or workstation through an RS232 serial port. The engi-
neer can download a design or a design revision into the
system for testing. The designer can also single-step the
logic, read the contents of the numerous flip-flops on the
device, and observe internal logic levels. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.
XC5200 Field Programmable Gate Arrays
4-188 June 1, 1996 (Version 4.0)
Detailed Functional Description
CLB Logic
Figure 3 shows the logic in the XC5200 CLB, which con-
sists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a D-
Type flip-flop or latch with common clock, cloc k enable , and
clear, but individually selectable clock polarity. Additional
logic features provided in the CLB are:
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Each flip-flop can be programmed individually as either
a transparent, level-sensitive latch or a D flip-flop.
• Four 3-state buffers with a shared Output Enable.
• Two 4-input LUTs can be combined to form an
independent 5-input LUT.
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
Figure 5: Two LUTs in Parallel Combined to Create a 5-input Function
out
QQout
DO
Q
D
FD
X
FD
CO
DI
X
CLR LC0
CKCE
5-Input Function
D
DO
F5_MUX
DI
F
F4
F3
F2
F1
F4
F3
F2
F1
I1
I2
I3
I4
I5
CI
F
LC1
X5710
June 1, 1996 (Version 4.0) 4-189
Carry Function
The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carr y multiplexer (CY_MUX) sym-
bol on a schematic is used to indicate the XC5200 carry
logic. This symbol represents the dedicated 2:1 multiplexer
in each LC that performs the one-bit high-speed carry prop-
agate per logic cell (four bits per CLB).
While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic func-
tion. Figure 6 represents an example of an adder function.
The carry propagate is performed on the CLB shown,
which also generates the half-sum f or the f our-bit adder. An
adjacent CLB is responsible for XORing the half-sum with
the corresponding carry-out. Thus an adder or counter
requires two LCs per bit. Notice that the carry chain
requires an initialization stage, which the XC5200 family
accomplishes using the carry initialize (CY_INIT) macro
and one additional LC.
The XC5200 library contains a set of RPMs and ar ithmetic
functions designed to take advantage of the dedicated
carry logic. Using and modifying these macros makes it
much easier to implement customized RPMs, freeing the
designer from the need to become an expert on architec-
tures.
Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
XOR
XOR
XOR
XOR
F=0
DI
DI
DI
DI
FD
FD
FD
FD
carry out
carry3
DO
D
X
LC3
DO
DQ
LC2
X
CI
carry in
CY_MUX
CY_MUX
CY_MUX
CY_MUX
CY_MUX
X
DO
DO DO
DO
LC1
LC0
CKCE CLR
D
D
Q
Q
X
Q
half sum0
carry0
half sum2
half sum1
carry1
carry2
half sum3
CO
A3
or
B3
A3 and B3
to any two
A2 and B2
to any two
A2
or
B2
A1
or
B1
A1 and B1
to any two
A0
or
B0
A0 and B0
to any two
0
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
XOR
XOR
XOR
XOR
DI
DI
DI
DI
FD
FD
DO
FD
FD
D
X
LC3
DO
DQ
LC2
X
CI
X
LC1
LC0
CK
CE CLR
D
D
Q
Q
X
Q
sum0
sum2
sum1
sum3
CO
Initialization of
carry chain (One Logic Cell) X5709
XC5200 Field Programmable Gate Arrays
4-190 June 1, 1996 (Version 4.0)
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be con-
figured to take advantage of these four cascaded
CY_MUXes. Note that AND and OR cascading are specific
cases of a general decode. In AND cascading all bits are
decoded equal to logic one, while in OR cascading all bits
are decoded equal to logic zero. The flexibility of the LUT
achieves this result.
Figure 7: XC5200 CY_MUX Used for Decoder Cascade Logic
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
AND
AND
F=0
DI
DI
DI
DI
FD
FD
FD
cascade out
out
DO
D
X
LC3
DO
DO
DO
DQ
LC2
X
CI cascade in
CY_MUX
CY_MUX
CY_MUX
CY_MUX
CY_MUX
FD
X
LC1
Initialization of
carry chain (One Logic Cell)
LC0
CK
CE CLR
D
D
Q
Q
X
Q
CO
AND
AND
X5708
June 1, 1996 (Version 4.0) 4-191
3-State Buffers
The XC5200 family has four dedicated TBUFs per CLB.
The four buffers are individually configurable through four
configuration bits to operate as simple non-in verting buff ers
or in 3-state mode. When in 3-state mode the CLB’s output
enable (TS) control signal drives the enable to all four buff-
ers (see Figure 8). Each TB UF can drive up to tw o horizon-
tal Longlines.
Oscillator
The XC5200 oscillator (OSC52) divides the internal 16-
MHz clock or a user clock that is connected to the “C” pin.
The user then has the choice of dividing by 4, 16, 64, or 256
for the “OSC1” output and dividing by 2, 8, 32, 128, 1024,
4096, 16384, or 65536 for the “OSC2” output. The division
is specified via a “DIVIDEn_BY=x” attribute on the symbol,
where n=1 for OSC1, or n=2 for OSC2. The OSC5 macro is
used where an internal oscillator is required. The CK_DIV
macro is applicable when a user clock input is specified
(see Figure 9).
Global Reset (GR)
On start-up , all XC5200 internal flip-flops are reset, using a
global reset (GR) signal. The user can assign the pin loca-
tion for the GR signal and use it to reset asynchronously all
of the flip-flops in the design without using general routing
resources. The user can also assign a positive or negative
polarity to GR.
Boundary Scan
XC5200 devices support all the mandator y boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP can also support two USERCODE
instructions.
Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
after configuration provides flexibility for interconnect test-
ing.
Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused out-
puts in IOBs used as unidirectional input pins. This tech-
nique partially compensates for the lack of INTEST
support.
The public boundary-scan instructions are always a v ailab le
prior to configuration. After configur ation, the public instruc-
tions and any USERCODE instructions are only av ailable if
specified in the design. While SAMPLE and BYPASS are
available during configuration, it is recommended that
boundary-scan operations not be performed during this
transitory period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the FPGA
device, and to read back the configuration data.
All of the XC4000 boundary-scan modes are suppor ted in
the XC5200 family. Three additional outputs for the User
Register are provided (Reset, Update, and Shift), repre-
senting the decoding of the corresponding state of the
boundary-scan internal state machine.
Figure 8: XC5200 3-State Buffer
Figure 9: XC5200 Oscillator Macros
CLB
TS
LC3
LC2
LC1
LC0
CLB
Horizontal
Longlines
X5706
OSC5 OSC1
OSC2
CK_DIV OSC1
OSC2
CLK
XC5200 Field Programmable Gate Arrays
4-192 June 1, 1996 (Version 4.0)
VersaBlock Routing
Local Interconnect Matrix
The GRM connects to the VersaBlock via 24 bidirectional
por ts (M0-M23). Excluding direct connections, global nets,
and 3-statable Longlines , all VersaBlock inputs and outputs
connect to the GRM via these 24 ports. F our 3-statable uni-
directional signals (TQ0-TQ3) drive out of the VersaBlock
directly onto the horizontal Longlines. Two horizontal global
nets (GH0 and GH1) and two v ertical global nets (GV0 and
GV1) connect directly to ev ery CLB clock pin; the y can con-
nect to other CLB inputs via the GRM. Each CLB also has
four unidirectional direct connects to each of its four neigh-
boring CLBs. These direct connects can also feed directly
back to the CLB (see Figure 10).
In addition, each CLB has 16 direct inputs, four direct con-
nections from each of the neighboring CLBs. These direct
connections provide high-speed local routing that b ypasses
the GRM.
The 13 CLB outputs (12 LC outputs plus a V cc/GND signal)
connect to the eight VersaBlock outputs via the output mul-
tiplexers, which consist of eight fully populated 13-to-1 mul-
tiplexers. Of the eight VersaBlock outputs, f our signals drive
each neighboring CLB directly, and provide a direct feed-
back path to the input multiplexers. The four remaining
multiplexer outputs can drive the GRM through four TBUFs
(TQ0-TQ3). All eight multiplexer outputs can connect to the
GRM through the bidirectional M0-M23 signals. All eight
signals also connect to the input multiplexers and are
potential inputs to that CLB.
CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers
(GH0, GH1, GV0, and GV1), and the four signals from the
CLB output multiple xers. Unlik e the output multiplexers, the
input multiple x ers are not fully populated; i.e., only a subset
of the available signals can be connected to a given CLB
input. The flexibility of LUT input swapping and LUT map-
ping compensates for this limitation. For example, if a 2-
input NAND gate is required, it can be mapped into any of
the four LUTs, and use any two of the four inputs to the
LUT.
Direct Connects
The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB’s input and
output multiplexer array, and thus bypass the programma-
ble routing matrix altogether. These lines are intended to
increase the routing channel utilization where possible,
while simultaneously reducing the delay incurred in speed-
critical connections.
The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce set-up time, clock-to-out, and combinational
propagation delay.
The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro per-
formance, and leaves the other routing channels intact for
improved routing. Direct connects can also route through a
CLB using one of the four cell-feedthrough paths.
June 1, 1996 (Version 4.0) 4-193
Figure 10: VersaBlock Details
4
4
4
4
5
5
5
5
3
3
3
3
24
To GRM
M0-M23
CLB
CLK
Direct North
Direct to
East
To
Longlines
and GRM
TQ0-TQ3
Global Nets
Feedback
Direct West
Direct South
CE
CLR CIN
COUT
VCC /GND 
TS
4
4
North 4
8
South 4
East 4
West 4
LC3
LC2
LC1
LC0
Output
Multiplexers
Input
Multiplexers 84
4
4
X5724
XC5200 Field Programmable Gate Arrays
4-194 June 1, 1996 (Version 4.0)
General Routing Matrix
The General Routing Matrix, shown in Figure 11, provides
flexible bidirectional connections to the Local Interconnect
Matrix through a hierarchy of different-length metal seg-
ments in both the horizontal and vertical directions. A pro-
grammable interconnect point (PIP) establishes an
electrical connection between two wire segments. The PIP,
consisting of a pass transistor switch controlled by a mem-
ory element, provides bidirectional (in some cases, unidi-
rectional) connection between two adjoining wires. A
collection of PIPs inside the General Routing Matrix and in
the Local Interconnect Matrix provides connectivity
between various types of metal segments. A hierarchy of
PIPs and associated routing segments combine to provide
a powerful interconnect hierarchy:
• Forty bidirectional single-length segments per CLB
provide ten routing channels to each of the four
neighboring CLBs in four directions.
• Sixteen bidirectional double-length segments per CLB
provide four routing channels to each of four other (non-
neighboring) CLBs in four directions.
• Eight horizontal and eight vertical bidirectional Longline
segments span the width and height of the chip,
respectively.
• Two low-skew horizontal and vertical unidirectional
global-line segments span each row and column of the
chip, respectively.
Single- and Double-Length Lines
The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The double-
length lines hop across ev ery other CLB to reduce the prop-
agation delays in speed-critical nets. Regenerating the sig-
nal strength is recommended after traversing three or four
such segments. XACT
step
place-and-route software auto-
matically connects buffers in the path of the signal as nec-
essary. Single- and double-length lines cannot drive onto
Longlines and global lines; Longlines and global lines can,
however, drive onto single- and double-length lines. As a
general rule, Longline and global-line connections to the
programmable routing matrix are unidirectional, with the
signal direction from these lines toward the routing matrix.
Longlines
Longlines are used for high-f an-out signals , 3-state busses ,
low-skew nets, and faraway destinations. Row and column
splitter PIPs in the middle of the arra y eff ectiv ely double the
total number of Longlines by electrically dividing them into
two separated half-lines. The horizontal Longlines are
driven by the 3-state b uff ers in each CLB, and are driv en by
similar buffers at the periphery of the array from the Ver-
saRing I/O Interface.
Bus-oriented microprocessor designs are accommodated
by using horizontal Longlines in conjunction with the 3-state
buffers in the CLB and in the VersaRing. Additionally, pro-
grammab le k eeper cells at the periphery can be enabled to
retain the last valid logic level on the Longlines when all
buffers are in 3-state mode.
Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not possible.
Again, as a general rule, long- and global-line connections
to the General Routing Matrix are unidirectional, with the
signal direction from these lines toward the routing matrix.
The XC5200 family has no pull-ups on the ends of the Lon-
glines sourced by TBUFs. Consequently, wired functions
(i.e., WAND and WORAND) and wide multiplexing func-
tions requiring pull-ups for undefined states (i.e., bus appli-
cations) must be implemented in a diff erent wa y. In the case
of the wired functions, the same functionality can be
achieved by taking advantage of the carry/cascade logic
described above, implementing a wide logic function in
place of the wired function. In the case of 3-state bus appli-
cations, the user must insure that all states of the m ultiplex-
ing function are defined. This process is as simple as
adding an additional TBUF to drive the bus High when the
previously undefined states are activated.
Global Lines
Global buff ers in Xilinx FPGAs are special b uff ers that drive
a dedicated routing network called Global Lines, as shown
in Figure 12. This network is intended for high-fan-out
clocks or other control signals , to maximize speed and min-
imize skewing while distributing the signal to many loads.
The XC5200 family has a total of four global buffers (B UFG
symbol in the library), each with its own dedicated routing
channel. Two are distributed vertically and two horizontally
throughout the FPGA.
June 1, 1996 (Version 4.0) 4-195
Figure 11: XC5200 Interconnect Structure
X4963
Versa-
Block
GRM
Single-length Lines
Double-length Lines
Direct Connects
Longlines and Global Lines
1
Six Levels of Routing Hierarchy
1
2
3
4
5
2
3
4
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Versa-
Block
GRM
Local Interconnect Matrix
Logic Cell Feedthrough
Path (Contained within each
Logic Cell)
LIM5
6
CLB
Direct Connects
TS
LIM
4
4
4
4
4
LC3
LC2
LC1
LC0
44
44
24
24
6
GRM
XC5200 Field Programmable Gate Arrays
4-196 June 1, 1996 (Version 4.0)
The global lines provide direct input only to the CLB clock
pins. The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.
Four cloc k input pads at the corners of the chip, as shown in
Figure 12, provide a high-speed, low-sk e w clock network to
each of the four global-line buffers. In addition to the dedi-
cated pad, the global lines can be sourced by internal logic.
PIPs from several routing channels within the VersaRing
can also be configured to drive the global-line buffers.
VersaRing Input/Output Interface
The VersaRing, shown in Figure 13, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The Ver-
saRing decouples the pad ring’ s pitch from the core’s pitch.
Each VersaRing Cell provides up to four pad-cell connec-
tions on one side, and connects directly to the CLB ports on
the other side. Depending on placement and pad-cell pitch,
any number of pad cells to a maximum of four can be con-
nected to a VersaRing cell.
Input/Output Pad
The I/O pad, shown in Figure 14, consists of an input b uff er
and an output buffer. The output driver is an 8-mA full-rail
CMOS buffer with 3-state control. Two slew-rate control
modes are suppor ted to minimize bus transients. Both the
output buffer and the 3-state control are invertible.
The input buff er has globally selected CMOS and TTL input
thresholds. The input buff er is in v ertib le and also provides a
programmab le dela y line to assure reliable chip-to-chip set-
up and hold times. Minimum ESD protection is 3 KV using
the Human Body Model.
Figure 12: Global Lines
GCK1 GCK4
GCK3
GCK2
X5704
Figure 13: VersaRing I/O Interface
Figure 14: XC5200 I/O Block
8
8
GRM
VersaBlock
8
VersaRing
2
4
8
8
4
4
4
10
2
GRM
VersaBlock
8
2
2
2
2
2
2
8
10 Interconnect
Interconnect
Pad
Pad
Pad
Pad
Pad
Pad
Pad
Pad
X5705
I
O
OE
PAD
Vcc
X4964
June 1, 1996 (Version 4.0) 4-197
Pin Descriptions
Permanently Dedicated Pins
Vcc
Eight or more (depending on package type) connections to
the nominal +5-V supply voltage. All must be connected.
GND
Eight or more (depending on package type) connections to
ground. All must be connected.
CCLK
During configuration, Configuration Clock is an output of
the FPGA in master modes or Asynchronous Peripheral
mode, but is an input to the FPGA in Slave Serial mode,
Synchronous Peripheral mode, and Express mode.
After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.
DONE
This is a bidirectional signal with optional pull-up resistor.
As an output, it indicates the completion of the configura-
tion process. The configuration program determines the
exact timing, the clock source for the Low-to-High transi-
tion, and enable of the pull-up resistor.
As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of out-
puts.
PROGRAM
This is an active-Low input, held Low during configuration,
that forces the FPGA to clear its configuration memory.
When PROGRAM goes High, the FPGA executes a com-
plete clear cycle, before it goes into a WAIT state and
releases INIT. After configuration, it has an optional pull-up
resistor.
User I/O Pins That Can Have Special
Functions
RDY/BUSY
During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the FPGA
device. The same status is also available on D7 in Asyn-
chronous P eripheral mode , if a read operation is perf ormed
when the device is selected. After configuration, this is a
user-programmable I/O pin.
RCLK
During Master Parallel configuration, each change on the
A0-17 outputs is preceded by a rising edge on RCLK, a
redundant output signal. After configuration, this is a user-
programmable I/O pin.
M0, M1, M2
As mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.
After configuration, M0, M1, and M2 become user-pro-
grammable I/O.
TDO
If boundary scan is used, this is the Test Data Output.
If boundary scan is not used, this pin becomes user-pro-
grammable I/O.
TDI, TCK, TMS
If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs, respectively, coming
directly from the pads, b ypassing the IOBs. These pins can
also be used as inputs to the CLB logic after configuration
is completed.
If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is com-
pleted. These pins become user-programmable I/O.
HDC
High During Configuration is driven High until configuration
is completed. It is available as a control output indicating
that configuration is not yet completed. After configuration,
this is a user-programmable I/O pin.
LDC
Low During Configuration is driven Low until configuration
completes. It is available as a control output indicating that
configuration is not yet completed. After configuration, this
is a user-programmable I/O pin.
INIT
Before and during configuration, this is a bidirectional sig-
nal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low dur-
ing the power stabilization and internal clearing of the con-
figuration memory. As an activ e-Low input, it can be used to
hold the FPGA device in the internal WAIT state before the
star t of configuration. Master-mode devices stay in a WAIT
state an additional 50 to 250 µs after INIT has gone High.
During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable I/O pin.
GCK1 - GCK4
Four Global Inputs each drive a dedicated internal global
net with shor t delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmab le I/O pin.
XC5200 Field Programmable Gate Arrays
4-198 June 1, 1996 (Version 4.0)
CS0, CS1, WS, RS
These four inputs are used in peripheral modes . The chip is
selected when CS0 is Low and CS1 is High. While the chip
is selected, a Low on Write Strobe (WS) loads the data
present on the D0 - D7 inputs into the internal data buffer; a
Low on Read Strobe (RS) changes D7 into a status
output: High if Ready, Low if Busy, and D0…D6 are active
High. WS and RS should be mutually exclusive, but if both
are Low simultaneously, the Write Strobe overrides. After
configuration, these are user-programmable I/O pins. In
Express mode, CS1 is also used as a serial-enable signal
for daisy chaining.
A0 - A17
During Master Par allel mode , these 18 output pins address
the configuration EPROM. After configuration, these are
user-programmable I/O pins.
D0 - D7
During Master Parallel, peripheral, and Express configura-
tion modes, these eight input pins receive configuration
data. After configuration, they are user-programmable I/O
pins.
DIN
During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.
During parallel configuration modes, this is the D0 input.
After configuration, DIN is a user-programmable I/O pin.
DOUT
During configuration in any non-Express mode, this is the
serial configuration data output that can drive the DIN of
daisy-chained slave FPGA devices. DOUT data changes
on the falling edge of CCLK. After configuration, DOUT is a
user-programmable I/O pin.
In Express mode, this is the enable output that can drive
CS1 of daisy-chained FPGA devices.
Unrestricted User-Programmable I/O Pins
I/O
A pin that can be configured to be input and/or output after
configuration is completed. Before configuration is com-
pleted, these pins have an internal high-impedance pull-up
resistor that defines the logical level as High.
June 1, 1996 (Version 4.0) 4-199
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. Each
configuration bit defines the state of a static memory cell
that controls either a function LUT bit, a multiple xer input, or
an interconnect pass transistor. The XACT
step
develop-
ment system translates the design into a netlist file. It auto-
matically partitions, places, and routes the logic and
generates the configuration data in PROM format.
Modes
The XC5200 family has seven modes of configuration,
selected by a 3-bit input code applied to the FPGA mode
pins (M0, M1, and M2). There are three self-clocking Mas-
ter modes, two Peripheral modes, a Slav e serial mode, and
a new high-speed Slave parallel mode called the Express.
See Table 4.
Brief descriptions of the seven modes are provided below.
Master Modes
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses, and
receive byte parallel data, which is internally serialized into
the FPGA data-frame format. The up and down selection
generates starting addresses at either zero or 3FFFF, to be
compatible with different microprocessor addressing con-
ventions. The Master Serial Mode generates CCLK and
receives the configuration data in serial form from a Xilinx
serial-configuration PROM.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the b yte-wide
data. In the synchronous mode, an externally supplied
clock input to CCLK serializes the data.
Slave Serial Mode
In the Slave Serial mode, the FPGA device receiv es serial-
configuration data on the rising edge of CCLK and, after
loading its configuration, passes additional data out, resyn-
chronized on the next falling edge of CCLK. Multiple slave
devices with identical configurations can be wired with par-
allel DIN inputs so that the devices can be configured
simultaneously.
Daisy Chaining
Multiple devices may be daisy-chained together so that
they ma y be progr ammed using a single bitstream. The first
device in the chain may be set to operate in any mode; all
other devices in the chain must be set to operate in Slave
Serial mode. Express-mode daisy chains are the only
exception: every device in such a chain must be set to
operate in Express mode.
All CCLK pins are tied together, and the data chain passes
from DOUT to DIN of successive devices along the chain.
Table 4: Configuration Modes
Mode M2 M1 M0 CCLK Data
Master Serial 0 0 0 output Bit-Serial
Slave Serial 1 1 1 input Bit-Serial
Master Parallel up 1 0 0 output Byte-Wide, 00000 ↑
Master Parallel down 1 1 0 output Byte-Wide, 3FFFF ↓
Peripheral Synchronous * 0 1 1 input Byte-Wide
Peripheral Asynchronous 1 0 1 output Byte-Wide
Express 0 1 0 input Byte-Wide
Reserved 0 0 1 — —
* Peripheral Synchronous can be considered byte-wide Slave Parallel
XC5200 Field Programmable Gate Arrays
4-200 June 1, 1996 (Version 4.0)
Express Mode
The Express mode (see Figure 15) is similar to the Slave
serial mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An external
source is used to drive CCLK while byte-wide data is
loaded directly into the configuration data shift registers. In
this mode the XC5200 family is capable of supporting a
CCLK frequency of 10 MHz, which is equivalent to an 80-
MHz serial rate, because eight bits of configuration data are
being loaded per CCLK cycle. An XC5210 in the Express
mode, for instance, can be configured in about 2 ms. The
Express mode does not support CRC error checking, but
does support constant-field error checking.
In the Express configuration mode, an external signal
drives the CCLK input(s) of the FPGA device(s). The first
byte of parallel configuration data must be available at the
D inputs of the FPGA devices a short set-up time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge. See
Figure 16.
Bitstream generation currently generates a bitstream suffi-
cient to program in all configuration modes e xcept Express .
Extra CCLK cycles are necessary to complete the configu-
ration, since in this mode data is read at a rate of eight bits
per CCLK cycle instead of one bit per cycle. Nor mally the
entire start-up sequence requires a number of bits that is
equal to the number of CCLK cycles needed. An additional
five CCLKs (equiv alent to 40 e xtra bits) will guar antee com-
pletion of configuration, regardless of the start-up options
chosen.
The Express mode is supported by the XC5200 and
XC4000EX families. It may be used, if XC5200 and
XC4000EX devices are daisy-chained.
If the first device is configured in the Express mode, addi-
tional devices may be daisy-chained only if every device in
the chain is also configured in the Express mode. CCLK
pins are tied together and D7-D0 pins are tied together for
all devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float-
ing, since there is an internal pull-up). The status pin DOUT
is pulled LOW two internal-oscillator cycles (nominally
1 MHz) after INIT is recognized as High, and remains Low
until the device’s configuration memory is full. Then DOUT
is pulled High to signal the next device in the chain to
accept the configuration data on the D7-D0 bus . All devices
receive and recogniz e the six b ytes of preamb le and length
count, irrespective of the level on CS1; but subsequent
frame data is accepted only when CS1 is High and the
device’s configuration memory is not already full.
Format
Table 5 describes the XC5200 configuration data stream.
Table 6 describes the internal configuration data structure.
Figure 15: Express Mode
INIT
CCLK CCLK
XC5200
M0 M1 M2
CS1
D0-D7
DATA BUS
PROGRAM
INIT
CCLK
PROGRAM
INIT
DOUT
DOUT
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
Optional
Daisy-Chained
XC5200
M0 M1
+5V
5K
+5V
M2
CS1
D0-D7
PROGRAM
X5086
8
8
8
June 1, 1996 (Version 4.0) 4-201
Figure 16: Express Mode Programming Switching Characteristics
X5087
BYTE
0
CCLK
FPGA Filled
1
2
3
INIT
TDC
TCD
TIC
D0-D7
Serial Data Out
(DOUT)
RDY/BUSY
CS1
BYTE
1BYTE
2BYTE
3
Internal INIT
Description Symbol Min Max Units
CCLK INIT (High) Setup time required 1 TIC 5µs
DIN Setup time required 2 TDC 30 ns
DIN Hold time required 3 TCD 0ns
CCLK High time TCCH 30 ns
CCLK Low time TCCL 30 ns
CCLK Frequency FCC 10 MHz
XC5200 Field Programmable Gate Arrays
4-202 June 1, 1996 (Version 4.0)
Table 5: XC5200 Bitstream Format
Data Type Value Occurrences
Fill Byte 11111111 Once per bit-
stream
Preamble 11110010
Length Counter COUNT(23:0)
Fill Byte 11111111
Start Byte 11111110 Once per data
frame
Data Frame * DATA(N-1:0)
Cyclic Redundancy Check or
Constant Field Check CRC(3:0) or
0110
Fill Nibble 1111
Extend Write Cycle FFFFFF
Postamble 11111110 Once per de-
vice
Fill Bytes (30) FFFF…FF
Start-Up Byte FF Once per bit-
stream
Table 6: Internal Configuration Data Structure
Device VersaBlock
Array
PROM
Size
(bits)
Xilinx
Serial Prom
Needed
XC5202 8 x 8 42,416 XC1765D
XC5204 10 x 12 70,704 XC17128D
XC5206 14 x 14 106,288 XC17128D
XC5210 18 x 18 165,488 XC17256D
XC5215 22 x 22 237,744 XC17256D
Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for
the bottom + 4 splitter bits + 8 start bits + 4 error chec k bits + 4 fill
bits * + 24 extended write bits
= (34 x number of Rows) + 100
* In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4
Number of Frames = (12 x number of Columns) + 7 for the left
edge + 8 for the right edge + 1 splitter bit
= (12 x number of Columns) + 16
Program Data = (Bits per F rame x Number of F r ames) + 48 header
bits + 8 postamble bits + 240 fill bits + 8 start-up bits
= (Bits per Frame x Number of Frames) + 304
PROM Size = Program Data
Figure 17: Configuration Sequence
INIT
High? if
Master
Sample
Mode Lines
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
VCC
3V
No
Yes
Yes
No
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3 µs per Frame
Master CCLK
Goes Active after
50 to 250 µs
F
Pull INIT Low
and Stop
X6037
EXTEST*
SAMPLE/PRELOAD*
BYPASS
CONFIGURE*
(*only when PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration
Memory
LDC Output = L, HDC Output = H
Boundary Scan
Instructions
Available:
I/O Active
Generate
One Time-Out Pulse
of 4 ms PROGRAM
= Low
No
Yes
Yes
June 1, 1996 (Version 4.0) 4-203
Configuration Sequence
Figure 17 illustrates the XC5200 configuration sequence.
This section describes the configuration sequence in detail.
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When VCC reaches the voltage at which portions
of the FPGA begin to operate (i.e., performs a write-and-
read test of a sample pair of configuration memory bits), the
programmable I/O buffers are 3-stated with active high-
impedance pull-up resistors. A time-out delay — nominally
4 ms — is initiated to allow the pow er-supply v oltage to sta-
bilize. For correct operation the power supply must reach
VCC(min) by the end of the time-out, and m ust not dip below
it thereafter.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have com-
pleted initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper oper-
ation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
During all three phases — Power-on, Initialization, and
Configuration — DONE is held Low; HDC, LDC, and INIT
are active; DOUT is driven; and all I/O b uffers are disabled.
Initialization
This phase clears the configuration memory and estab-
lishes the configuration mode.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An open-
drain bidirectional signal, INIT, is released when the config-
uration memory is completely cleared. The device then
tests for the absence of an e xternal active-lo w lev el on INIT.
The mode lines are sampled two internal clock cycles later
(nominally 2 µs).
The master device waits an additional 32 µs to 256 µs
(nominally 64-128 µs) to provide adequate time f or all of the
slav e de vices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.
Configuration
The length counter begins counting immediately upon entry
into the configuration state. In slave-mode operation it is
impor tant to wait at least two cycles of the internal 1-MHz
clock oscillator after INIT is recognized before toggling
CCLK and feeding the serial bitstream. Configuration will
not begin until the internal configuration logic reset is
released, which happens two cycles after INIT goes High.
A master device’s configuration is delayed from 32 to 256
µs to ensure proper operation with any sla ve de vices driven
by the master device.
A preamble field at the beginning of the configuration data
stream indicates that the next 24 bits represent the length
count. The length count equals the total n umber of configu-
ration bits needed to load the complete configuration data
to all daisy-chained devices. Once the preamble and
length-count values have been passed through to the next
device in the daisy-chain, DOUT is held High to prevent
start bits from reaching any daisy-chained devices. After
fully configuring itself, the device passes serial data to
downstream daisy-chained devices via DOUT until the full
length count is reached.
Errors in the configuration bitstream are check ed at the end
of a frame of data. The de vice does not check the preamb le
or length count for errors. In a daisy-chained configuration,
configuration data f or downstream devices are not checked
for errors. If an error is detected after reading a frame, the
ERR pin (also known as INIT) is immediately pulled Low
and all configuration activity ceases. However, a master or
Peripheral Asynchronous device will continue outputting a
configuration clock and incrementing the PROM address
indefinitely ev en though it will ne ver complete configuration.
A reprogram or power-on must be applied to remove the
device from this state.
Start-Up and Operation
The XC5200 start-up sequence is identical to that of the
XC4000 family. Each of these events may occur in any
order: (a) DONE is pulled High; and/or (b) user I/Os
become active; and/or (c) Inter nal Reset is deactivated. As
a configuration option, the three e vents ma y be triggered by
a user clock rather than b y CCLK, or the start-up sequence
may be delayed by externally holding the DONE pin Low.
In any mode, the clock cycles of the start-up sequence are
not included in the length count. The length of the bitstream
is greater than the length count.
XC5200 Field Programmable Gate Arrays
4-204 June 1, 1996 (Version 4.0)
Pin Functions During Configuration
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 100-kW pull-up
resistor.
CONFIGURATION MODE: <M2:M1:M0> USER
OPERATION
SLAVE
<1:1:1> MASTER-SER
<0:0:0> SYN.PERIPH
<0:1:1> ASYN.PERIPH
<1:0:1> MASTER-HIGH
<1:1:0> MASTER-LOW
<1:0:0> EXPRESS
<0:1:0>
A16 A16 GCK1-I/O
A17 A17 I/O
TDI TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS TMS-I/O
I/O
M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) M1 (HIGH) (I) I/O
M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (LOW) (I) M0 (LOW) (I) I/O
M2 (HIGH) (I) M2 (LOW) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (LOW) (I) I/O
GCK2-I/O
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT-ERROR * INIT-ERROR * INIT-ERROR * INIT-ERROR * INIT-ERROR * INIT-ERROR * INIT-ERROR * I/O
I/O
DONE DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O
GCK3-I/O
DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/O
DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/O
CSO (I) I/O
DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/O
DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/O
RS (I) I/O
DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/O
DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O
RDY/BUSY RDY/BUSY RCLK RCLK I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT DOUT I/O
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I)
TDO TDO TDO TDO TDO TDO TDO TDO-I/O
WS (I) A0 A0 I/O
A1 A1 GCK4-I/O
CS1 (I) A2 A2 CS1 (I) I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 I/O
ALL OTHERS
* INIT is an open-drain output during configuration (I) Represents an input (O) Represents an output
June 1, 1996 (Version 4.0) 4-205
Configuration Switching Characteristics
Master Modes
Description Symbol Min Max Units
Power-On-Reset TPOR 215 ms
Program Latency TPI 670µs per CLB column
CCLK (output) Delay
period (slow)
period (fast)
TICCK
TCCLK
TCCLK
40
640
100
375
3000
375
µs
ns
ns
Slave and Peripheral Modes
Description Symbol Min Max Units
Power-On-Reset TPOR 215 ms
Program Latency TPI 670µs per CLB column
CCLK (input) Delay (required)
period (required) TICCK
TCCLK
5
100 µs
ns
Note: At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until
VCC is valid.
VALID
PROGRAM
INIT
Vcc
PI
T
POR
T
ICCK
TCCLK
T
CCLK OUTPUT or INPUT
M0, M1, M2 DONE RESPONSE
<300 ns
<300 ns
>300 ns
RE-PROGRAM
X1532 (Required)
I/O
XC5200 Field Programmable Gate Arrays
4-206 June 1, 1996 (Version 4.0)
XC5200 Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1
XC5200 Operating Conditions
XC5200 DC Characteristics Over Operating Conditions
1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.
Symbol Description Min Max Units
VCC Supply voltage relative to GNDCommercial:0°C to 85°C junction 4.75 5.25 V
Supply voltage relative to GNDIndustrial:-40°C to 100°C junction 4.5 5.5 V
VIHT High-level input voltage — TTL configuration 2.0 VCC V
VILT Low-level input voltage — TTL configuration 0 0.8 V
VIHC High-level input voltage — CMOS configuration 70% 100% VCC
VILC Low-level input voltage — CMOS configuration 0 20% VCC
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -8.0 mA, VCC min 3.86 V
VOL Low-level output voltage @ IOL = 8.0 mA, VCC max (Note 1) 0.4 V
ICCO Quiescent FPGA supply current (Note 1) 15 mA
IIL Leakage current -10 +10 µA
CIN Input capacitance (sample tested) 15 pF
IRIN Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 0.25 mA
Note: 1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a
MakeBits tie option.
June 1, 1996 (Version 4.0) 4-207
XC5200 Absolute Maximum Ratings
XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT
step
timing calculator
and used in the simulator.
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction temperature in plastic packages +125 °C
Junction temperature in ceramic packages +150 °C
Note: Stresses bey ond those listed under Absolute Maximum Ratings ma y cause permanent damage to the device . These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for e xtended periods of time may aff ect
device reliability.
Speed Grade -6 -5 -4 -3
Description Symbol Device Max
(ns) Max
(ns) Max
(ns) Max
(ns)
Global Signal Distribution
From pad through global buffer, to any clock (CK) TBUFG XC5202 9.1 8.5
XC5204 9.3 8.7
XC5206 9.4 8.8
XC5210 9.4 8.8 8.5 8.3
XC5215 10.5 9.9
PRELIMINARY ADVANCE
Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
XC5200 Field Programmable Gate Arrays
4-208 June 1, 1996 (Version 4.0)
XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT
step
timing calculator
and used in the simulator.
Speed Grade -6 -5 -4 -3
Description Symbol Device Max
(ns) Max
(ns) Max
(ns) Max
(ns)
TBUF driving a Longline
I to Longline, while TS is Low; i.e., buffer is constantly
active TIO XC5202 6.0 3.8
XC5204 6.4 4.1
XC5206 6.6 4.2
XC5210 6.6 4.2 3.3 3.2
XC5215 7.3 4.6
TS going Low to Longline going from floating High or
Low to active Low or High TON XC5202 7.8 5.6
XC5204 8.3 5.9
XC5206 8.4 6.0
XC5210 8.4 6.0 5.0 4.7
XC5215 8.9 6.3
TS going High to TBUF going inactive, not driving
Longline TOFF XC52xx 3.0 2.8
PRELIMINARY ADVANCE
Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
TS
IO
TBUF
June 1, 1996 (Version 4.0) 4-209
XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT
step
timing calculator
and used in the simulator.
Speed Grade -6 -5 -4 -3
Description Symbol Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
Combinatorial Delays
F inputs to X output TILO 5.6 4.6 3.8 3.0
DI inputs to DO output (Logic-Cell
Feedthrough) TIDO 4.3 3.5 2.8 2.2
F inputs via F5_MUX to DO output TIMO 7.2 5.8 5.0 4.2
Carry Delays
Incremental delay per bit TCY 0.7 0.6 0.5 0.5
Carry-in overhead from DI TCYDI 1.8 1.6 1.5 1.3
Carry-in overhead from F TCYL 3.7 3.2 2.9 2.3
Carry-out overhead to DO TCYO 4.0 3.2 2.5 2.0
Sequential Delays
Clock (CK) to out (Q) (Flip-Flop) TCKO 5.8 4.9 4.0 3.5
Gate (Latch enable) going active to out (Q) TGO 9.2 7.4 5.9 4.7
Set-up Time Before Clock (CK)
F inputs TICK 2.3 1.8 1.4 1.0
F inputs via F5_MUX TMICK 3.8 3.0 2.5 2.1
DI input TDICK 0.8 0.5 0.4 0.3
CE input TEICK 1.6 1.2 0.9 0.7
Hold Times After Clock (CK)
F inputs TCKI 0000
F inputs via F5_MUX TCKMI 0000
DI input TCKDI 0000
CE input TCKEI 0000
Clock Widths
Clock High Time TCH 6.0 6.0 6.0 6.0
Clock Low Time TCL 6.0 6.0 6.0 6.0
Export Control Max. flip-flop toggle rate (MHz) FTOG 83 83 83 83
Reset Delays
Width (High) TCLRW 6.0 6.0 6.0 6.0
Delay from CLR to Q (Flip-Flop) TCLR 7.7 6.3 5.1 4.0
Delay from CLR to Q (Latch) TCLRL 6.5 5.2 4.2 3.2
Global Reset Delays (see Note 2)
Width (High) TGCLRW 6.0 6.0 6.0 6.0
Delay from internal GCLR to Q TGCLR 14.7 12.1 9.1 8.0
PRELIMINARY ADVANCE
Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die.
2. Timing is based upon the XC5215 device. For other devices, see XACT
step
Timing Calculator .
XC5200 Field Programmable Gate Arrays
4-210 June 1, 1996 (Version 4.0)
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The XACT
step
delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Speed Grade -6 -5 -4 -3
Description Symbol Device Max
(ns) Max
(ns) Max
(ns) Max
(ns)
Global Clock to Output Pad (fast) TICKOF
(Max)
XC5202 16.9 15.1
XC5204 17.1 15.3
XC5206 17.2 15.4
XC5210 17.2 15.4 14.2 13.0
XC5215 19.0 17.0
Global Clock to Output Pad (slew-limited) TICKO
(Max)
XC5202 21.4 18.7
XC5204 21.6 18.9
XC5206 21.7 19.0
XC5210 21.7 19.0 17.3 17.0
XC5215 24.3 21.2
Input Set-up Time (no delay) to CLB Flip-Flop TPSUF
(Min)
XC5202 2.5 1.8
XC5204 2.3 1.6
XC5206 2.2 1.5
XC5210 2.2 1.5 1.2 0.8
XC5215 0.5 0
Input Hold Time (no delay) to CLB Flip-Flop TPHF
(Min)
XC5202 3.2 2.7
XC5204 3.4 2.9
XC5206 3.5 3.0
XC5210 3.5 3.0 2.8 2.6
XC5215 4.4 3.9
Input Set-up Time (with delay) to CLB Flip-Flop TPSU
(Min)
XC5202 8.8 7.7
XC5204 8.6 7.5
XC5206 8.5 7.4
XC5210 8.5 7.4 6.0 5.0
XC5215 6.8 5.7
Input Hold Time (with delay) to CLB Flip-Flop TPH
(Min)
XC52xx 0000
PRELIMINARY ADVANCE
Note: 1. These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be used to
assure that direct connects are used.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
3. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.
Global Clock-to-Output Delay
FD .
.
.
.
TBUFG
Direct
Connect IOB
CLB
Global Clock-to-Output Delay
FD .
.
.
.
TBUFG
Direct
Connect IOB
CLB
Input
Set-up
& Hold
Time
FD
TBUFG
IOB Direct
Connect CLB
Input
Set-up
& Hold
Time
FD
TBUFG
IOB Direct
Connect CLB
Input
Set-up
& Hold
Time
FD
TBUFG
IOB Direct
Connect CLB
Input
Set-up
& Hold
Time
FD
TBUFG
IOB Direct
Connect CLB
June 1, 1996 (Version 4.0) 4-211
XC5200 IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT
step
timing calculator
and used in the simulator.
Speed Grade -6 -5 -4 -3
Description Symbol Max
(ns) Max
(ns) Max
(ns) Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay) TPI 5.7 5.0 4.8 4.0
Pad to I (with delay) TPID 11.4 10.2 10.2 9.4
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast) TOPF 4.6 4.5 4.5 4.2
Output (O) to Pad (slew-limited) TOPS 9.5 8.4 8.0 7.5
From clock (CK) to output pad (fast), using direct connect between Q
and output (O) TOKPOF 10.1 9.3 8.3 7.1
From clock (CK) to output pad (slew-limited), using direct connect be-
tween Q and output (O) TOKPOS 14.9 13.1 11.8 11.0
3-state to Pad active (fast) TTSONF 5.6 5.2 4.9 4.0
3-state to Pad active (slew-limited) TTSONS 10.4 9.0 8.3 7.8
Internal GTS to Pad active (see Note 3) TGTS 17.7 15.9 14.7 14.0
PRELIMINARY ADVANCE
Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see
pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.
2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon the XC5210 device. For other devices, see XACT
step
Timing Calculator .
XC5200 Field Programmable Gate Arrays
4-212 June 1, 1996 (Version 4.0)
XC5200 CLB-to-Pad Diagrams
R2C8
R3C8
R4C8
R5C8
R6C8
R7C8
R8C8
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
CLB, identified by R#C# = row and column numbers
I/O Pad
R#C#
KEY:
Top
Bottom
RightLeft
R8C2 R8C3 R8C4 R8C5 R8C6 R8C7
Figure 18: XC5202 CLB-to-Pad Relationship
June 1, 1996 (Version 4.0) 4-213
Note: Pad numbers (1, 2, …, 84) refer to die pads, not external device pins.
See the XC5202 pinout table beginning on page 223.
Figure 19: XC5202 CLB-to-Pad Relationship (Detail)
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
R8C2
R8C3
R8C4
R8C5
R8C6
R8C7
R8C8
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
R2C8
R3C8
R4C8
R5C8
R6C8
R7C8
R8C8
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
74
R1C1 R8C1 R1C8
Left Bottom Right Top
XC5200 Field Programmable Gate Arrays
4-214 June 1, 1996 (Version 4.0)
Figure 20: XC5204 CLB-to-Pad Relationship
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
CLB, identified by R#C# = row and column numbers
I/O Pad
R#C#
KEY:
Top
Bottom
RightLeft
R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10 R10C11
R2C12
R3C12
R4C12
R5C12
R6C12
R7C12
R8C12
R9C12
R10C12
June 1, 1996 (Version 4.0) 4-215
Note: Pad numbers (1, 2, …, 124) refer to die pads, not external device pins.
See the XC5204 pinout table beginning on page 226.
Figure 21: XC5204 CLB-to-Pad Relationship (Detail)
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
R10C2
R10C3
R10C4
R10C5
R10C6
R10C7
R10C8
R10C9
R10C10
R10C11
R10C12
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
R2C12
R3C12
R4C12
R5C12
R6C12
R7C12
R8C12
R9C12
R10C12
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10
R1C11
R1C12
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
R1C1 R10C1 R1C12
Left Bottom Right Top
XC5200 Field Programmable Gate Arrays
4-216 June 1, 1996 (Version 4.0)
Figure 22: XC5206 CLB-to-Pad Relationship
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
R11C1
R12C1
R13C1
R14C1
CLB, identified by R#C# = row and column numbers
I/O Pad
R#C#
KEY:
Top
Bottom
RightLeft
R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14
R2C14
R3C14
R4C14
R5C14
R6C14
R7C14
R8C14
R9C14
R10C14
R11C14
R12C14
R13C14
June 1, 1996 (Version 4.0) 4-217
Note: Pad numbers (1, 2, …, 148) refer to die pads, not external device pins.
See the XC5206 pinout table beginning on page 230.
Figure 23: XC5206 CLB-to-Pad Relationship (Detail)
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
R11C1
R12C1
R13C1
R14C1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
R14C2
R14C3
R14C4
R14C5
R14C6
R14C7
R14C8
R14C9
R14C10
R14C11
R14C12
R14C13
R14C14
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
R2C14
R3C14
R4C14
R5C14
R6C14
R7C14
R8C14
R9C14
R10C14
R11C14
R12C14
R13C14
R14C14
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10
R1C11
R1C12
R1C13
R1C14
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
R1C1 R14C1 R1C14
Left Bottom Right Top
XC5200 Field Programmable Gate Arrays
4-218 June 1, 1996 (Version 4.0)
Figure 24: XC5210 CLB-to-Pad Relationship
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10 R1C11 R1C12 R1C13 R1C14
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
R11C1
R12C1
R13C1
R14C1
R1C15 R1C16 R1C17 R1C18
R15C1
R16C1
R17C1
R18C1
R2C18
R3C18
R4C18
R5C18
R6C18
R7C18
R8C18
R9C18
R10C18
R11C18
R12C18
R13C18
R14C18
R15C18
R16C18
R17C18
R18C18R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17
CLB, identified by R#C# = row and column numbers
I/O Pad
R#C#
KEY:
Top
Bottom
RightLeft
June 1, 1996 (Version 4.0) 4-219
Note: Pad numbers (1, 2, …, 196) refer to die pads, not external device pins.
See the XC5210 pinout table beginning on page 235.
Figure 25: XC5210 CLB-to-Pad Relationship (Detail)
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
R11C1
R12C1
R13C1
R14C1
R15C1
R16C1
R17C1
R18C1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
R18C2
R18C3
R18C4
R18C5
R18C6
R18C7
R18C8
R18C9
R18C10
R18C11
R18C12
R18C13
R18C14
R18C15
R18C16
R18C17
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
R2C18
R3C18
R4C18
R5C18
R6C18
R7C18
R8C18
R9C18
R10C18
R11C18
R12C18
R13C18
R14C18
R15C18
R16C18
R17C18
R18C18
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10
R1C11
R1C12
R1C13
R1C14
R1C15
R1C16
R1C17
R1C18
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
R1C1 R18C1
R18C18
R1C18
Left Bottom Right Top
XC5200 Field Programmable Gate Arrays
4-220 June 1, 1996 (Version 4.0)
Figure 26: XC5215 CLB-to-Pad Relationship
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C15 R1C16 R1C17 R1C18
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R15C1
R16C1
R17C1
R18C1
R1C19 R1C20 R1C21 R1C22
R19C1
R20C1
R21C1
R22C1
R2C22
R3C22
R4C22
R5C22
R6C22
R7C22
R8C22
R15C22
R16C22
R17C22
R18C22
R19C22
R20C22
R21C22
R22C22R22C2 R22C3 R22C4 R22C5 R22C6 R22C7 R22C8 R22C15 R22C16 R22C17 R22C18 R22C19 R22C20 R22C21
CLB, identified by R#C# = row and column numbers
I/O Pad
R#C#
KEY:
Top
Bottom
RightLeft
June 1, 1996 (Version 4.0) 4-221
Note: Pad numbers (31, 32, …, 153) refer to die pads, not external device pins.
See the XC5215 pinout table beginning on page 241.
Figure 27: XC5215 CLB-to-Pad Relationship (Left/Bottom Detail)
R13C1
R14C1
R15C1
R16C1
R17C1
R18C1
R19C1
R20C1
R21C1
R22C1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
R12C1 93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
R22C2
R22C3
R22C4
R22C5
R22C6
R22C7
R22C8
R22C9
R22C10
R22C11
R22C1 124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
R22C13
R22C14
R22C15
R22C16
R22C17
R22C18
R22C19
R22C20
R22C21
R22C22
R22C12
Bottom
R2C1
R3C1
R4C1
R5C1
R6C1
R7C1
R8C1
R9C1
R10C1
R11C1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
R1C1
Left
XC5200 Field Programmable Gate Arrays
4-222 June 1, 1996 (Version 4.0)
Note: Pad numbers (1, 2, …, 244) refer to die pads, not external device pins.
See the XC5215 pinout table beginning on page 241.
Figure 28: XC5215 CLB-to-Pad Relationship (Right/Top Detail)
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
R2C22
R3C22
R4C22
R5C22
R6C22
R7C22
R8C22
R9C22
R10C22
R11C22
R1C22 183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
R13C22
R14C22
R15C22
R16C22
R17C22
R18C22
R19C22
R20C22
R21C22
R22C22
R12C22
Right
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10
R1C11
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
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R1C12
R1C13
R1C14
R1C15
R1C16
R1C17
R1C18
R1C19
R1C20
R1C21
R1C22
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June 1, 1996 (Version 4.0) 4-223
Device-Specific Pinout Tables
Pin Locations for XC5202 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order
VCC 2 92 89 128 H3 -
1. I/O (A8) 3 93 90 129 H1 51
2. I/O (A9) 4 94 91 130 G1 54
3. I/O - 95 92 131 G2 57
4. I/O - 96 93 132 G3 63
5. I/O (A10) 5 97 94 133 F1 66
6. I/O (A11) 6 98 95 134 F2 69
- - - - 135* - -
- - - - 136* - -
GND - - - 137 F3 -
7. I/O (A12) 7 99 96 138 E3 78
8. I/O (A13) 8 100 97 139 C1 81
- - - - 140* - -
- - - - 141* - -
9. I/O (A14) 9 1 98 142 B1 90
10. I/O (A15) 10 2 99 143 B2 93
VCC 11 3 100 144 C3 -
GND 12 4 1 1 C4 -
11. GCK1 (A16, I/O) 13 5 2 2 B3 102
12. I/O (A17) 14 6 3 3 A1 105
- ---4*- -
- ---5*- -
13. I/O (TDI) 15 7 4 6 B4 111
14. I/O (TCK) 16 8 5 7 A3 114
GND - - - 8 C6 -
- ---9*- -
- ---10*- -
15. I/O (TMS) 17 9 6 11 A5 117
16. I/O 18 10 7 12 C7 123
17. I/O - - - 13 B7 126
18. I/O - 11 8 14 A6 129
19. I/O 19 12 9 15 A7 135
20. I/O 20 13 10 16 A8 138
GND 21 14 11 17 C8 -
VCC 22 15 12 18 B8 -
21. I/O 23 16 13 19 C9 141
22. I/O 24 17 14 20 B9 147
23. I/O - 18 15 21 A9 150
24. I/O - - - 22 B10 153
25. I/O 25 19 16 23 C10 159
26. I/O 26 20 17 24 A10 162
- ---25*- -
- ---26*- -
GND - - - 27 C11 -
27. I/O 27 21 18 28 B12 165
28. I/O - 22 19 29 A13 171
- ---30*- -
- ---31*- -
29. I/O 28 23 20 32 B13 174
XC5200 Field Programmable Gate Arrays
4-224 June 1, 1996 (Version 4.0)
30. I/O 29 24 21 33 B14 177
31. M1 (I/O) 30 25 22 34 A15 186
GND 31 26 23 35 C13 -
32. M0 (I/O) 32 27 24 36 A16 189
VCC 33 28 25 37 C14 -
33. M2 (I/O) 34 29 26 38 B15 192
34. GCK2 (I/O) 35 30 27 39 B16 195
35. I/O (HDC) 36 31 28 40 D14 204
- ---41*- -
- ---42*- -
36. I/O - 32 29 43 E14 207
37. I/O (LDC) 37 33 30 44 C16 210
GND - - - 45 F14 -
- ---46*- -
- ---47*- -
38. I/O 38 34 31 48 F16 216
39. I/O 39 35 32 49 G14 219
40. I/O - 36 33 50 G15 222
41. I/O - 37 34 51 G16 228
42. I/O 40 38 35 52 H16 231
43. I/O (ERR, INIT)41393653H15 234
VCC 42 40 37 54 H14 -
GND 43 41 38 55 J14 -
44. I/O 44 42 39 56 J15 240
45. I/O 45 43 40 57 J16 243
46. I/O - 44 41 58 K16 246
47. I/O - 45 42 59 K15 252
48. I/O 46 46 43 60 K14 255
49. I/O 47 47 44 61 L16 258
- ---62*- -
- ---63*- -
GND - - - 64 L14 -
50. I/O 48 48 45 65 P16 264
51. I/O 49 49 46 66 M14 267
- ---67*- -
- ---68*- -
52. I/O 50 50 47 69 N14 276
53. I/O 51 51 48 70 R16 279
GND 52 52 49 71 P14 -
DONE 53 53 50 72 R15 -
VCC 54 54 51 73 P13 -
PROG 55 55 52 74 R14 -
54. I/O (D7) 56 56 53 75 T16 288
55. GCK3 (I/O) 57 57 54 76 T15 291
- ---77*- -
- ---78*- -
56. I/O (D6) 58 58 55 79 T14 300
57. I/O - 59 56 80 T13 303
GND - - - 81 P11 -
- ---82*- -
Pin Locations for XC5202 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-225
Notes: * Indicates unconnected package pins.
† leading numbers refer to bonded pad, shown in Figure 18 or Figure 19.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
- ---83*- -
58. I/O (D5) 59 60 57 84 T10 306
59. I/O (CS0) 60615885P10 312
60. I/O - 62 59 86 R10 315
61. I/O - 63 60 87 T9 318
62. I/O (D4) 61 64 61 88 R9 324
63. I/O 62 65 62 89 P9 327
VCC 63 66 63 90 R8 -
GND 64 67 64 91 P8 -
64. I/O (D3) 65 68 65 92 T8 336
65. I/O (RS) 66696693T7 339
66. I/O - 70 67 94 T6 342
67. I/O - - - 95 R7 348
68. I/O (D2) 67 71 68 96 P7 351
69. I/O 68 72 69 97 T5 360
- ---98*- -
- ---99*- -
GND - - - 100 P6 -
70. I/O (D1) 69 73 70 101 T3 363
71. I/O (RCLK-BUSY/
RDY) 70 74 71 102 P5 366
- - - - 103* - -
- - - - 104* - -
72. I/O (D0, DIN) 71 75 72 105 P4 372
73. I/O (DOUT) 72 76 73 106 T2 375
CCLK 73 77 74 107 R2 -
VCC 74 78 75 108 P3 -
74. I/O (TDO) 75 79 76 109 T1 0
GND 76 80 77 110 N3 -
75. I/O (A0, WS) 77 81 78 111 R1 9
76. GCK4 (A1, I/O) 78 82 79 112 P2 15
- - - - 113* - -
- - - - 114* - -
77. I/O (A2, CS1) 79 83 80 115 P1 18
78. I/O (A3) 80 84 81 116 N1 21
- - - - 117* - -
GND - - - 118 L3 -
- - - - 119* - -
- - - - 120* - -
79. I/O (A4) 81 85 82 121 K3 27
80. I/O (A5) 82 86 83 122 K2 30
81. I/O - 87 84 123 K1 33
82. I/O - 88 85 124 J1 39
83. I/O (A6) 83 89 86 125 J2 42
84. I/O (A7) 84 90 87 126 J3 45
GND 1 91 88 127 H2 -
Pin Locations for XC5202 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-226 June 1, 1996 (Version 4.0)
Pin Locations for XC5204 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order
VCC 2 92 89 128 H3 142 -
1. I/O (A8) 3 93 90 129 H1 143 78
2. I/O (A9) 4 94 91 130 G1 144 81
3. I/O - 95 92 131 G2 145 87
4. I/O - 96 93 132 G3 146 90
5. I/O (A10) 5 97 94 133 F1 147 93
6. I/O (A11) 6 98 95 134 F2 148 99
7. I/O - - - 135 E1 149 102
8. I/O - - - 136 E2 150 105
GND - - - 137 F3 151 -
9.I/O ----D1152 111
10.I/O ----D2153 114
11. I/O (A12) 7 99 96 138 E3 154 117
12. I/O (A13) 8 100 97 139 C1 155 123
13. I/O - - - 140 C2 156 126
14. I/O - - - 141 D3 157 129
15. I/O (A14) 9 1 98 142 B1 158 138
16. I/O (A15) 10 2 99 143 B2 159 141
VCC 11 3 100 144 C3 160 -
GND 12 4 1 1 C4 1 -
17. GCK1 (A16, I/O) 13 5 2 2 B3 2 150
18. I/O (A17) 14 6 3 3 A1 3 153
19. I/O - - - 4 A2 4 159
20. I/O - - - 5 C5 5 162
21. I/O (TDI) 15 7 4 6 B4 6 165
22. I/O (TCK) 16 8 5 7 A3 7 171
- -----8* -
- -----9* -
GND - - - 8 C6 10 -
23. I/O - - - 9 B5 11 174
24. I/O - - - 10 B6 12 177
25. I/O (TMS) 17 9 6 11 A5 13 180
26. I/O 18 10 7 12 C7 14 183
27. I/O - - - 13 B7 15 186
28. I/O - 11 8 14 A6 16 189
29. I/O 19 12 9 15 A7 17 195
30. I/O 20 13 10 16 A8 18 198
GND 21 14 11 17 C8 19 -
VCC 22 15 12 18 B8 20 -
31. I/O 23 16 13 19 C9 21 201
32. I/O 24 17 14 20 B9 22 207
33. I/O - 18 15 21 A9 23 210
34. I/O - - - 22 B10 24 213
35. I/O 25 19 16 23 C10 25 219
36. I/O 26 20 17 24 A10 26 222
37. I/O - - - 25 A11 27 225
38. I/O - - - 26 B11 28 231
GND - - - 27 C11 29 -
- -----30* -
- -----31* -
June 1, 1996 (Version 4.0) 4-227
39. I/O 27 21 18 28 B12 32 234
40. I/O - 22 19 29 A13 33 237
41. I/O - - - 30 A14 34 240
42. I/O - - - 31 C12 35 243
43. I/O 28 23 20 32 B13 36 246
44. I/O 29 24 21 33 B14 37 249
45. M1 (I/O) 30 25 22 34 A15 38 258
GND 31 26 23 35 C13 39 -
46. M0 (I/O) 32 27 24 36 A16 40 261
VCC 33 28 25 37 C14 41 -
47. M2 (I/O) 34 29 26 38 B15 42 264
48. GCK2 (I/O) 35 30 27 39 B16 43 267
49. I/O (HDC) 36 31 28 40 D14 44 276
50. I/O - - - 41 C15 45 279
51. I/O - - - 42 D15 46 282
52. I/O - 32 29 43 E14 47 288
53. I/O (LDC) 37 33 30 44 C16 48 291
54.I/O ----E1549 294
55.I/O ----D1650 300
GND - - - 45 F14 51 -
56. I/O - - - 46 F15 52 303
57. I/O - - - 47 E16 53 306
58. I/O 38 34 31 48 F16 54 312
59. I/O 39 35 32 49 G14 55 315
60. I/O - 36 33 50 G15 56 318
61. I/O - 37 34 51 G16 57 324
62. I/O 40 38 35 52 H16 58 327
63. I/O (ERR, INIT) 41 39 36 53 H15 59 330
VCC 42 40 37 54 H14 60 -
GND 43 41 38 55 J14 61 -
64. I/O 44 42 39 56 J15 62 336
65. I/O 45 43 40 57 J16 63 339
66. I/O - 44 41 58 K16 64 348
67. I/O - 45 42 59 K15 65 351
68. I/O 46 46 43 60 K14 66 354
69. I/O 47 47 44 61 L16 67 360
70. I/O - - - 62 M16 68 363
71. I/O - - - 63 L15 69 366
GND - - - 64 L14 70 -
72.I/O ----N1671 372
73.I/O ----M1572 375
74. I/O 48 48 45 65 P16 73 378
75. I/O 49 49 46 66 M14 74 384
76. I/O - - - 67 N15 75 387
77. I/O - - - 68 P15 76 390
78. I/O 50 50 47 69 N14 77 396
79. I/O 51 51 48 70 R16 78 399
GND 52 52 49 71 P14 79 -
DONE 53 53 50 72 R15 80 -
VCC 54 54 51 73 P13 81 -
PROG 55 55 52 74 R14 82 -
Pin Locations for XC5204 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-228 June 1, 1996 (Version 4.0)
80. I/O (D7) 56 56 53 75 T16 83 408
81. GCK3 (I/O) 57 57 54 76 T15 84 411
82. I/O - - - 77 R13 85 420
83. I/O - - - 78 P12 86 423
84. I/O (D6) 58 58 55 79 T14 87 426
85. I/O - 59 56 80 T13 88 432
- -----89* -
- -----90* -
GND - - - 81 P11 91 -
86. I/O - - - 82 R11 92 435
87. I/O - - - 83 T11 93 438
88. I/O (D5) 59 60 57 84 T10 94 444
89. I/O (CS0) 60 61 58 85 P10 95 447
90. I/O - 62 59 86 R10 96 450
91. I/O - 63 60 87 T9 97 456
92. I/O (D4) 61 64 61 88 R9 98 459
93. I/O 62 65 62 89 P9 99 462
VCC 63 66 63 90 R8 100 -
GND 64 67 64 91 P8 101 -
94. I/O (D3) 65 68 65 92 T8 102 468
95. I/O (RS) 66696693T7103 471
96. I/O - 70 67 94 T6 104 474
97. I/O - - - 95 R7 105 480
98. I/O (D2) 67 71 68 96 P7 106 483
99. I/O 68 72 69 97 T5 107 486
100. I/O - - - 98 R6 108 492
101. I/O - - - 99 T4 109 495
GND - - - 100 P6 110 -
- -----111* -
- -----112* -
102. I/O (D1) 69 73 70 101 T3 113 498
103. I/O (RCLK-BUSY/RDY) 70 74 71 102 P5 114 504
104. I/O - - - 103 R4 115 507
105. I/O - - - 104 R3 116 510
106. I/O (D0, DIN) 71 75 72 105 P4 117 516
107. I/O (DOUT) 72 76 73 106 T2 118 519
CCLK 73 77 74 107 R2 119 -
VCC 74 78 75 108 P3 120 -
108. I/O (TDO) 75 79 76 109 T1 121 0
GND 76 80 77 110 N3 122 -
109. I/O (A0, WS) 77 81 78 111 R1 123 9
110. GCK4 (A1, I/O) 78 82 79 112 P2 124 15
111. I/O - - - 113 N2 125 18
112. I/O - - - 114 M3 126 21
113. I/O (A2, CS1) 79 83 80 115 P1 127 27
114. I/O (A3) 80 84 81 116 N1 128 30
115. I/O - - - 117 M2 129 33
116. I/O ----M1130 39
GND - - - 118 L3 131 -
117. I/O - - - 119 L2 132 42
118. I/O - - - 120 L1 133 45
Pin Locations for XC5204 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-229
Notes: * Indicates unconnected package pins.
† leading numbers refer to bonded pad, shown in Figure 20 or Figure 21.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
119. I/O (A4) 81 85 82 121 K3 134 51
120. I/O (A5) 82 86 83 122 K2 135 54
- -----136* -
121. I/O - 87 84 123 K1 137 57
122. I/O - 88 85 124 J1 138 63
123. I/O (A6) 83 89 86 125 J2 139 66
124. I/O (A7) 84 90 87 126 J3 140 69
GND 1 91 88 127 H2 141 -
Pin Locations for XC5204 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-230 June 1, 1996 (Version 4.0)
Pin Locations for XC5206 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
VCC 2 92 89 128 142 155 J4 183 -
1. I/O (A8) 3 93 90 129 143 156 J3 184 87
2. I/O (A9) 4 94 91 130 144 157 J2 185 90
3. I/O - 95 92 131 145 158 J1 186 93
4. I/O - 96 93 132 146 159 H1 187 99
5.I/O - ----160H2188 102
6.I/O - ----161H3189 105
7. I/O (A10) 5 97 94 133 147 162 G1 190 111
8. I/O (A11) 6 98 95 134 148 163 G2 191 114
9. I/O - - - 135 149 164 F1 192 117
10. I/O - - - 136 150 165 E1 193 123
GND - - - 137 151 166 G3 194 -
- - ------195* -
- - ----167* - 196* -
11. I/O - - - - 152 168 C1 197 126
12. I/O - - - - 153 169 E2 198 129
13. I/O (A12) 7 99 96 138 154 170 F3 199 138
14. I/O (A13) 8 100 97 139 155 171 D2 200 141
15. I/O - - - 140 156 172 B1 201 150
16. I/O - - - 141 157 173 E3 202 153
17. I/O (A14) 9 1 98 142 158 174 C2 203 162
18. I/O (A15) 10 2 99 143 159 175 B2 204 165
VCC 11 3 100 144 160 176 D3 205 -
- - ------206* -
- - ------207* -
- - ------208* -
- - ------1* -
GND 1241111D42 -
- - ------3* -
19. GCK1 (A16, I/O) 13 52222C34 174
20. I/O (A17) 14 63333C45 177
21. I/O - - - 4 4 4 B3 6 183
22. I/O - - - 5 5 5 C5 7 186
23. I/O (TDI) 15 74666A28 189
24. I/O (TCK) 16 85777B49 195
25. I/O - - - - 8 8 C6 10 198
26. I/O - - - - 9 9 A3 11 201
- - ------12* -
- - ------13* -
GND - - - 8 10 10 C7 14 -
27. I/O - - - 9 11 11 A4 15 207
28. I/O - - - 10 12 12 A5 16 210
29. I/O (TMS) 17 9 6 11 13 13 B7 17 213
30. I/O 18 10 7 12 14 14 A6 18 219
31.I/O - ----15C819 222
32.I/O - ----16A720 225
33. I/O - - - 13 15 17 B8 21 234
34. I/O - 11 8 14 16 18 A8 22 237
35. I/O 19 12 9 15 17 19 B9 23 246
36. I/O 20 13 10 16 18 20 C9 24 249
June 1, 1996 (Version 4.0) 4-231
GND 21 14 11 17 19 21 D9 25 -
VCC 22 15 12 18 20 22 D10 26 -
37. I/O 23 16 13 19 21 23 C10 27 255
38. I/O 24 17 14 20 22 24 B10 28 258
39. I/O - 18 15 21 23 25 A9 29 261
40. I/O - - - 22 24 26 A10 30 267
41.I/O - ----27A1131 270
42.I/O - ----28C1132 273
43. I/O 25 19 16 23 25 29 B11 33 279
44. I/O 26 20 17 24 26 30 A12 34 282
45. I/O - - - 25 27 31 B12 35 285
46. I/O - - - 26 28 32 A13 36 291
GND - - - 27 29 33 C12 37 -
- - ------38* -
- - ------39* -
47. I/O - - - - 30 34 A15 40 294
48. I/O - - - - 31 35 C13 41 297
49. I/O 27 21 18 28 32 36 B14 42 303
50. I/O - 22 19 29 33 37 A16 43 306
51. I/O - - - 30 34 38 B15 44 309
52. I/O - - - 31 35 39 C14 45 315
53. I/O 28 23 20 32 36 40 A17 46 318
54. I/O 29 24 21 33 37 41 B16 47 321
55. M1 (I/O) 30 25 22 34 38 42 C15 48 330
GND 31 26 23 35 39 43 D15 49 -
56. M0 (I/O) 32 27 24 36 40 44 A18 50 333
- - ------51* -
- - ------52* -
- - ------53* -
- - ------54* -
VCC 33 28 25 37 41 45 D16 55 -
57. M2 (I/O) 34 29 26 38 42 46 C16 56 336
58. GCK2 (I/O) 35 30 27 39 43 47 B17 57 339
59. I/O (HDC) 36 31 28 40 44 48 E16 58 348
60. I/O - - - 41 45 49 C17 59 351
61. I/O - - - 42 46 50 D17 60 354
62. I/O - 32 29 43 47 51 B18 61 360
63. I/O (LDC) 37 33 30 44 48 52 E17 62 363
64. I/O - - - - 49 53 F16 63 372
65. I/O - - - - 50 54 C18 64 375
- - ------65* -
- - ------66* -
GND - - - 45 51 55 G16 67 -
66. I/O - - - 46 52 56 E18 68 378
67. I/O - - - 47 53 57 F18 69 384
68. I/O 38 34 31 48 54 58 G17 70 387
69. I/O 39 35 32 49 55 59 G18 71 390
70.I/O - ----60H1672 396
71.I/O - ----61H1773 399
72. I/O - 36 33 50 56 62 H18 74 402
73. I/O - 37 34 51 57 63 J18 75 408
Pin Locations for XC5206 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-232 June 1, 1996 (Version 4.0)
74. I/O 40 38 35 52 58 64 J17 76 411
75. I/O (ERR, INIT)41 3936535965J1677 414
VCC 42 40 37 54 60 66 J15 78 -
GND 43 41 38 55 61 67 K15 79 -
76. I/O 44 42 39 56 62 68 K16 80 420
77. I/O 45 43 40 57 63 69 K17 81 423
78. I/O - 44 41 58 64 70 K18 82 426
79. I/O - 45 42 59 65 71 L18 83 432
80.I/O - ----72L1784 435
81.I/O - ----73L1685 438
82. I/O 46 46 43 60 66 74 M18 86 444
83. I/O 47 47 44 61 67 75 M17 87 447
84. I/O - - - 62 68 76 N18 88 450
85. I/O - - - 63 69 77 P18 89 456
GND - - - 64 70 78 M16 90 -
- - ------91* -
- - ------92* -
86. I/O - - - - 71 79 T18 93 459
87. I/O - - - - 72 80 P17 94 468
88. I/O 48 48 45 65 73 81 N16 95 471
89. I/O 49 49 46 66 74 82 T17 96 480
90. I/O - - - 67 75 83 R17 97 483
91. I/O - - - 68 76 84 P16 98 486
92. I/O 50 50 47 69 77 85 U18 99 492
93. I/O 51 51 48 70 78 86 T16 100 495
GND 52 52 49 71 79 87 R16 101 -
- - ------102* -
DONE 53 53 50 72 80 88 U17 103 -
- - ------104* -
- - ------105* -
VCC 54 54 51 73 81 89 R15 106 -
- - ------107* -
PROG 55 55 52 74 82 90 V18 108 -
94. I/O (D7) 56 56 53 75 83 91 T15 109 504
95. GCK3 (I/O) 57 57 54 76 84 92 U16 110 507
96. I/O - - - 77 85 93 T14 111 516
97. I/O - - - 78 86 94 U15 112 519
98. I/O (D6) 58 58 55 79 87 95 V17 113 522
99. I/O - 59 56 80 88 96 V16 114 528
100. I/O - - - - 89 97 T13 115 531
101. I/O - - - - 90 98 U14 116 534
- - ------117* -
- - ------118* -
GND - - - 81 91 99 T12 119 -
102. I/O - - - 82 92 100 U13 120 540
103. I/O - - - 83 93 101 V13 121 543
104. I/O (D5) 59 60 57 84 94 102 U12 122 552
105. I/O (CS0) 60 61 58 85 95 103 V12 123 555
106. I/O - ----104T11124 558
107. I/O - ----105U11125 564
108. I/O - 62 59 86 96 106 V11 126 567
Pin Locations for XC5206 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-233
109. I/O - 63 60 87 97 107 V10 127 570
110. I/O (D4) 61 64 61 88 98 108 U10 128 576
111. I/O 62 65 62 89 99 109 T10 129 579
VCC 63 66 63 90 100 110 R10 130 -
GND 64 67 64 91 101 111 R9 131 -
112. I/O (D3) 65 68 65 92 102 112 T9 132 588
113. I/O (RS) 66 69 66 93 103 113 U9 133 591
114. I/O - 70 67 94 104 114 V9 134 600
115. I/O - - - 95 105 115 V8 135 603
116. I/O - ----116U8136 612
117. I/O - ----117T8137 615
118. I/O (D2) 67 71 68 96 106 118 V7 138 618
119. I/O 68 72 69 97 107 119 U7 139 624
120. I/O - - - 98 108 120 V6 140 627
121. I/O - - - 99 109 121 U6 141 630
GND - - - 100 110 122 T7 142 -
- - ------143* -
- - ------144* -
122. I/O - - - - 111 123 U5 145 636
123. I/O - - - - 112 124 T6 146 639
124. I/O (D1) 69 73 70 101 113 125 V3 147 642
125. I/O (RCLK-
BUSY/RDY) 70 74 71 102 114 126 V2 148 648
126. I/O - - - 103 115 127 U4 149 651
127. I/O - - - 104 116 128 T5 150 654
128. I/O (D0, DIN) 71 75 72 105 117 129 U3 151 660
129. I/O (DOUT) 72 76 73 106 118 130 T4 152 663
CCLK 73 77 74 107 119 131 V1 153 -
VCC 74 78 75 108 120 132 R4 154 -
- - ------155* -
- - ------156* -
- - ------157* -
- - ------158* -
130. I/O (TDO) 75 79 76 109 121 133 U2 159 -
GND 76 80 77 110 122 134 R3 160 -
131. I/O (A0, WS) 77 81 78 111 123 135 T3 161 9
132. GCK4 (A1, I/O) 78 82 79 112 124 136 U1 162 15
133. I/O - - - 113 125 137 P3 163 18
134. I/O - - - 114 126 138 R2 164 21
135. I/O (A2, CS1) 79 83 80 115 127 139 T2 165 27
136. I/O (A3) 80 84 81 116 128 140 N3 166 30
137. I/O - - - 117 129 141 P2 167 33
138. I/O - - - - 130 142 T1 168 42
- - ------169* -
- - ------170* -
GND - - - 118 131 143 M3 171 -
139. I/O - - - 119 132 144 P1 172 45
140. I/O - - - 120 133 145 N1 173 51
141. I/O (A4) 81 85 82 121 134 146 M2 174 54
142. I/O (A5) 82 86 83 122 135 147 M1 175 57
143. I/O - ----148L3176 63
Pin Locations for XC5206 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-234 June 1, 1996 (Version 4.0)
Notes: * Indicates unconnected package pins.
† leading numbers refer to bonded pad, shown in Figure 22 or Figure 23.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
144. I/O - - - - 136 149 L2 177 66
145. I/O - 87 84 123 137 150 L1 178 69
146. I/O - 88 85 124 138 151 K1 179 75
147. I/O (A6) 83 89 86 125 139 152 K2 180 78
148. I/O (A7) 84 90 87 126 140 153 K3 181 81
GND 1 91 88 127 141 154 K4 182 -
Pin Locations for XC5206 Devices
Pin Description †PC84 PQ100 VQ100 TQ144 PQ160 TQ176 PG191 PQ208 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-235
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
VCC 2 128 142 155 183 J4 D8 212 -
1. I/O (A8) 3 129 143 156 184 J3 E8 213 111
2. I/O (A9) 4 130 144 157 185 J2 B7 214 114
3. I/O - 131 145 158 186 J1 A7 215 117
4. I/O - 132 146 159 187 H1 C7 216 123
5. I/O - - - 160 188 H2 D7 217 126
6. I/O - - - 161 189 H3 E7 218 129
- -------219* -
7. I/O (A10) 5 133 147 162 190 G1 A6 220 135
8. I/O (A11) 6 134 148 163 191 G2 B6 221 138
VCC ------VCC** 222 -
9.I/O -----H4C6223 141
10.I/O -----G4F7224 150
11. I/O - 135 149 164 192 F1 A5 225 153
12. I/O - 136 150 165 193 E1 B5 226 162
GND - 137 151 166 194 G3 GND** 227 -
13. I/O - - - - 195 F2 D6 228 165
14. I/O - - - 167 196 D1 C5 229 171
15. I/O - - 152 168 197 C1 A4 230 174
16. I/O - - 153 169 198 E2 E6 231 177
17. I/O (A12) 7 138 154 170 199 F3 B4 232 183
18. I/O (A13) 8 139 155 171 200 D2 D5 233 186
19.I/O -----F4A3234 189
20.I/O -----E4C4235 195
21. I/O - 140 156 172 201 B1 B3 236 198
22. I/O - 141 157 173 202 E3 F6 237 201
23. I/O (A14) 9 142 158 174 203 C2 A2 238 210
24. I/O (A15) 10 143 159 175 204 B2 C3 239 213
VCC 11 144 160 176 205 D3 VCC** 240 -
- - - - - 206* - - - -
- - - - - 207* - - - -
- - - - - 208* - - - -
- ----1*--- -
GND 121112D4GND** 1 -
- ----3*--- -
25. GCK1 (A16, I/O) 13 2224C3D42 222
26. I/O (A17) 14 3335C4B13 225
27. I/O - 4446B3C24 231
28. I/O - 5557C5E55 234
29. I/O (TDI) 15 6668A2D36 237
30. I/O (TCK) 16 7779B4C17 243
31. I/O - - 8 8 10 C6 D2 8 246
32. I/O - - 9 9 11 A3 G6 9 249
33. I/O - - - - 12 B5 E4 10 255
34. I/O - - - - 13 B6 D1 11 258
35. I/O - ----D5E312 261
36. I/O - ----D6E213 267
GND - 8 10 10 14 C7 GND** 14 -
37. I/O - 9 11 11 15 A4 F5 15 270
XC5200 Field Programmable Gate Arrays
4-236 June 1, 1996 (Version 4.0)
38. I/O - 10 12 12 16 A5 E1 16 273
39. I/O (TMS) 17 11 13 13 17 B7 F4 17 279
40. I/O 18 12 14 14 18 A6 F3 18 282
VCC ------VCC** 19 -
41. I/O - ----D7F220 285
42. I/O - ----D8F121 291
- -------22* -
43. I/O - - - 15 19 C8 G4 23 294
44. I/O - - - 16 20 A7 G3 24 297
45. I/O - 13 15 17 21 B8 G2 25 306
46. I/O - 14 16 18 22 A8 G1 26 309
47. I/O 19 15 17 19 23 B9 G5 27 318
48. I/O 20 16 18 20 24 C9 H3 28 321
GND 21 17 19 21 25 D9 GND** 29 -
VCC 22 18 20 22 26 D10 VCC** 30 -
49. I/O 23 19 21 23 27 C10 H4 31 327
50. I/O 24 20 22 24 28 B10 H5 32 330
51. I/O - 21 23 25 29 A9 J2 33 333
52. I/O - 22 24 26 30 A10 J1 34 339
53. I/O - - - 27 31 A11 J3 35 342
54. I/O - - - 28 32 C11 J4 36 345
- -------37* -
55. I/O - ----D11J538 351
56. I/O - ----D12K139 354
VCC ------VCC** 40 -
57. I/O 25 23 25 29 33 B11 K2 41 357
58. I/O 26 24 26 30 34 A12 K3 42 363
59. I/O - 25 27 31 35 B12 J6 43 366
60. I/O - 26 28 32 36 A13 L1 44 369
GND - 27 29 33 37 C12 GND** 45 -
61. I/O - ----D13L246 375
62. I/O - ----D14K447 378
63. I/O - - - - 38 B13 L3 48 381
64. I/O - - - - 39 A14 M1 49 387
65. I/O - - 30 34 40 A15 K5 50 390
66. I/O - - 31 35 41 C13 M2 51 393
67. I/O 27 28 32 36 42 B14 L4 52 399
68. I/O - 29 33 37 43 A16 N1 53 402
69. I/O - 30 34 38 44 B15 M3 54 405
70. I/O - 31 35 39 45 C14 N2 55 411
71. I/O 28 32 36 40 46 A17 K6 56 414
72. I/O 29 33 37 41 47 B16 P1 57 417
73. M1 (I/O) 30 34 38 42 48 C15 N3 58 426
GND 31 35 39 43 49 D15 GND** 59 -
74. M0 (I/O) 32 36 40 44 50 A18 P2 60 429
- - - - - 51* - - - -
- - - - - 52* - - - -
- - - - - 53* - - - -
- - - - - 54* - - - -
VCC 33 37 41 45 55 D16 VCC** 61 -
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
June 1, 1996 (Version 4.0) 4-237
75. M2 (I/O) 34 38 42 46 56 C16 M4 62 432
76. GCK2 (I/O) 35 39 43 47 57 B17 R2 63 435
77. I/O (HDC) 36 40 44 48 58 E16 P3 64 444
78. I/O - 41 45 49 59 C17 L5 65 447
79. I/O - 42 46 50 60 D17 N4 66 450
80. I/O - 43 47 51 61 B18 R3 67 456
81. I/O (LDC) 37 44 48 52 62 E17 P4 68 459
82. I/O - - 49 53 63 F16 K7 69 462
83. I/O - - 50 54 64 C18 M5 70 468
84. I/O - - - - 65 D18 R4 71 471
85. I/O - - - - 66 F17 N5 72 474
86. I/O - ----E15P573 480
87. I/O - ----F15L674 483
GND - 45 51 55 67 G16 GND** 75 -
88. I/O - 46 52 56 68 E18 R5 76 486
89. I/O - 47 53 57 69 F18 M6 77 492
90. I/O 38 48 54 58 70 G17 N6 78 495
91. I/O 39 49 55 59 71 G18 P6 79 504
VCC ------VCC** 80 -
92. I/O - - - 60 72 H16 R6 81 507
93. I/O - - - 61 73 H17 M7 82 510
- -------83* -
94. I/O - ----G15N784 516
95. I/O - ----H15P785 519
96. I/O - 50 56 62 74 H18 R7 86 522
97. I/O - 51 57 63 75 J18 L7 87 528
98. I/O 40 52 58 64 76 J17 N8 88 531
99. I/O (ERR, INIT) 41 53 59 65 77 J16 P8 89 534
VCC 42 54 60 66 78 J15 VCC** 90 -
GND 43 55 61 67 79 K15 GND** 91 -
100. I/O 44 56 62 68 80 K16 L8 92 540
101. I/O 45 57 63 69 81 K17 P9 93 543
102. I/O - 58 64 70 82 K18 R9 94 546
103. I/O - 59 65 71 83 L18 N9 95 552
104. I/O - - - 72 84 L17 M9 96 555
105. I/O - - - 73 85 L16 L9 97 558
- -------98* -
106. I/O - ----L15R1099 564
107. I/O - ----M15P10100 567
VCC ------VCC** 101 -
108. I/O 46 60 66 74 86 M18 N10 102 570
109. I/O 47 61 67 75 87 M17 K9 103 576
110. I/O - 62 68 76 88 N18 R11 104 579
111. I/O - 63 69 77 89 P18 P11 105 588
GND - 64 70 78 90 M16 GND** 106 -
112. I/O - ----N15M10107 591
113. I/O - ----P15N11108 600
114. I/O - - - - 91 N17 R12 109 603
115. I/O - - - - 92 R18 L10 110 606
116. I/O - - 71 79 93 T18 P12 111 612
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
XC5200 Field Programmable Gate Arrays
4-238 June 1, 1996 (Version 4.0)
117. I/O - - 72 80 94 P17 M11 112 615
118. I/O 48 65 73 81 95 N16 R13 113 618
119. I/O 49 66 74 82 96 T17 N12 114 624
120. I/O - 67 75 83 97 R17 P13 115 627
121. I/O - 68 76 84 98 P16 K10 116 630
122. I/O 50 69 77 85 99 U18 R14 117 636
123. I/O 51 70 78 86 100 T16 N13 118 639
GND 52 71 79 87 101 R16 GND** 119 -
- - - - - 102* - - - -
DONE 53 72 80 88 103 U17 P14 120 -
- - - - - 104* - - - -
- - - - - 105* - - - -
VCC 54 73 81 89 106 R15 VCC** 121 -
- - - - - 107* - - - -
PROG 55 74 82 90 108 V18 M12 122 -
124. I/O (D7) 56 75 83 91 109 T15 P15 123 648
125. GCK3 (I/O) 57 76 84 92 110 U16 N14 124 651
126. I/O - 77 85 93 111 T14 L11 125 660
127. I/O - 78 86 94 112 U15 M13 126 663
128. I/O - ----R14N15127 666
129. I/O - ----R13M14128 672
130. I/O (D6) 58 79 87 95 113 V17 J10 129 675
131. I/O - 80 88 96 114 V16 L12 130 678
132. I/O - - 89 97 115 T13 M15 131 684
133. I/O - - 90 98 116 U14 L13 132 687
134. I/O - - - - 117 V15 L14 133 690
135. I/O - - - - 118 V14 K11 134 696
GND - 81 91 99 119 T12 GND** 135 -
136. I/O - ----R12L15136 699
137. I/O - ----R11K12137 708
138. I/O - 82 92 100 120 U13 K13 138 711
139. I/O - 83 93 101 121 V13 K14 139 714
VCC ------VCC** 140 -
140. I/O (D5) 59 84 94 102 122 U12 K15 141 720
141. I/O (CS0) 60 85 95 103 123 V12 J12 142 723
- -------143* -
142. I/O - - - 104 124 T11 J13 144 726
143. I/O - - - 105 125 U11 J14 145 732
144. I/O - 86 96 106 126 V11 J15 146 735
145. I/O - 87 97 107 127 V10 J11 147 738
146. I/O (D4) 61 88 98 108 128 U10 H13 148 744
147. I/O 62 89 99 109 129 T10 H14 149 747
VCC 63 90 100 110 130 R10 VCC** 150 -
GND 64 91 101 111 131 R9 GND** 151 -
148. I/O (D3) 65 92 102 112 132 T9 H12 152 756
149. I/O (RS) 66 93 103 113 133 U9 H11 153 759
150. I/O - 94 104 114 134 V9 G14 154 768
151. I/O - 95 105 115 135 V8 G15 155 771
152. I/O - - - 116 136 U8 G13 156 780
153. I/O - - - 117 137 T8 G12 157 783
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
June 1, 1996 (Version 4.0) 4-239
- -------158* -
154. I/O (D2) 67 96 106 118 138 V7 G11 159 786
155. I/O 68 97 107 119 139 U7 F15 160 792
VCC ------VCC** 161 -
156. I/O - 98 108 120 140 V6 F14 162 795
157. I/O - 99 109 121 141 U6 F13 163 798
158. I/O - ----R8G10164 804
159. I/O - ----R7E15165 807
GND - 100 110 122 142 T7 GND** 166 -
160. I/O - ----R6E14167 810
161. I/O - ----R5F12168 816
162. I/O - - - - 143 V5 E13 169 819
163. I/O - - - - 144 V4 D15 170 822
164. I/O - - 111 123 145 U5 F11 171 828
165. I/O - - 112 124 146 T6 D14 172 831
166. I/O (D1) 69 101 113 125 147 V3 E12 173 834
167. I/O (RCLK-BUSY/RDY) 70 102 114 126 148 V2 C15 174 840
168. I/O - 103 115 127 149 U4 D13 175 843
169. I/O - 104 116 128 150 T5 C14 176 846
170. I/O (D0, DIN) 71 105 117 129 151 U3 F10 177 855
171. I/O (DOUT) 72 106 118 130 152 T4 B15 178 858
CCLK 73 107 119 131 153 V1 C13 179 -
VCC 74 108 120 132 154 R4 VCC** 180 -
- - - - - 155* - - - -
- - - - - 156* - - - -
- - - - - 157* - - - -
- - - - - 158* - - - -
172. I/O (TDO) 75 109 121 133 159 U2 A15 181 -
GND 76 110 122 134 160 R3 GND** 182 -
173. I/O (A0, WS) 77 111 123 135 161 T3 A14 183 9
174. GCK4 (A1, I/O) 78 112 124 136 162 U1 B13 184 15
175. I/O - 113 125 137 163 P3 E11 185 18
176. I/O - 114 126 138 164 R2 C12 186 21
177. I/O (CS1, A2) 79 115 127 139 165 T2 A13 187 27
178. I/O (A3) 80 116 128 140 166 N3 B12 188 30
179. I/O - ----P4F9189 33
180. I/O - ----N4D11190 39
181. I/O - 117 129 141 167 P2 A12 191 42
182. I/O - - 130 142 168 T1 C11 192 45
183. I/O - - - - 169 R1 B11 193 51
184. I/O - - - - 170 N2 E10 194 54
- ------GND** 195* -
GND - 118 131 143 171 M3 - 196 -
185. I/O - 119 132 144 172 P1 A11 197 57
186. I/O - 120 133 145 173 N1 D10 198 66
187. I/O - ----M4C10199 69
188. I/O - ----L4B10200 75
VCC ------VCC** 201 -
189. I/O (A4) 81 121 134 146 174 M2 A10 202 78
190. I/O (A5) 82 122 135 147 175 M1 D9 203 81
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
XC5200 Field Programmable Gate Arrays
4-240 June 1, 1996 (Version 4.0)
Notes: * Indicates unconnected package pins.
† leading numbers refer to bonded pad, shown in Figure 24 or Figure 25.
** Pins labeled VCC** are internally bonded to a VCC plane within the BG225 package . The external pins are: B2, D8, H15, R8,
B14, E1, and R15.
Pins labeled GND** are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7,
G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
- -------204* -
191. I/O - - - 148 176 L3 C9 205 87
192. I/O - - 136 149 177 L2 B9 206 90
193. I/O - 123 137 150 178 L1 A9 207 93
194. I/O - 124 138 151 179 K1 E9 208 99
195. I/O (A6) 83 125 139 152 180 K2 C8 209 102
196. I/O (A7) 84 126 140 153 181 K3 B8 210 105
GND 1 127 141 154 182 K4 GND** 211 -
Pin Locations for XC5210 Devices
Pin Description
†PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240 Boundary Scan
Order
June 1, 1996 (Version 4.0) 4-241
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
VCC 142 183 212 K1 38 VCC** VCC** -
1. I/O (A8) 143 184 213 K2 37 E8 D14 138
2. I/O (A9) 144 185 214 K3 36 B7 C14 141
3. I/O 145 186 215 K5 35 A7 A15 147
4. I/O 146 187 216 K4 34 C7 B15 150
5. I/O - 188 217 J1 33 D7 C15 153
6. I/O - 189 218 J2 32 E7 D15 159
- - - 219* ---- -
7. I/O (A10) 147 190 220 H1 31 A6 A16 162
8. I/O (A11) 148 191 221 J3 30 B6 B16 165
- - - - - 29* - - -
- - - - - 28* - - -
9. I/O - - - H2 27 - C17 171
10. I/O - - - G1 26 - B18 174
VCC - - 222 E1 25 VCC** VCC** -
- - - - - 24* - - -
11. I/O - - 223 H3 23 C6 C18 177
12. I/O - - 224 G2 22 F7 D17 183
13. I/O 149 192 225 H4 21 A5 A20 186
14. I/O 150 193 226 F2 20 B5 B19 189
GND 151 194 227 F1 19 GND** GND** -
15. I/O - - - H5 18 - C19 195
16. I/O - - - G3 17 - D18 198
17. I/O - 195 228 D1 16 D6 A21 201
18. I/O - 196 229 G4 15 C5 B20 207
19. I/O 152 197 230 E2 14 A4 C20 210
20. I/O 153 198 231 F3 13 E6 B21 213
21. I/O (A12) 154 199 232 G5 12 B4 B22 219
- - - - - 11* - - -
22. I/O (A13) 155 200 233 C1 10 D5 C21 222
23. I/O - - - F4 9 - D20 225
24. I/O - - - E3 8 - A23 234
25. I/O - - 234 D2 7 A3 D21 237
26. I/O - - 235 C2 6 C4 C22 243
27. I/O 156 201 236 F5 5 B3 B24 246
28. I/O 157 202 237 E4 4 F6 C23 249
29. I/O (A14) 158 203 238 D3 3 A2 D22 258
30. I/O (A15) 159 204 239 C3 2 C3 C24 261
VCC 160 205 240 A2 1 VCC** VCC** -
- - 206* ----- -
- - 207* ----- -
- - 208* ----- -
- - 1*----- -
GND 1 2 1 B1 304 GND** GND** -
- - 3*----- -
31. GCK1 (A16, I/O) 2 4 2 D4 303 D4 D23 270
32. I/O (A17) 3 5 3 B2 302 B1 C25 273
33. I/O 4 6 4 B3 301 C2 D24 279
34. I/O 5 7 5 E6 300 E5 E23 282
35. I/O (TDI) 6 8 6 D5 299 D3 C26 285
XC5200 Field Programmable Gate Arrays
4-242 June 1, 1996 (Version 4.0)
36. I/O (TCK) 7 9 7 C4 298 C1 E24 294
37. I/O - - - A3 297 - F24 297
38. I/O - - - D6 296 - E25 303
39. I/O 8 10 8 E7 295 D2 D26 306
40. I/O 9 11 9 B4 294 G6 G24 309
41. I/O - 12 10 C5 293 E4 F25 315
42. I/O - 13 11 A4 292 D1 F26 318
43. I/O - - 12 D7 291 E3 H23 321
44. I/O - - 13 C6 290 E2 H24 327
45. I/O - - - E8 289 - G25 330
46. I/O - - - B5 288 - G26 333
GND 10 14 14 A5 287 GND** GND** -
47. I/O 11 15 15 B6 286 F5 J23 339
48. I/O 12 16 16 D8 285 E1 J24 342
49. I/O (TMS) 13 17 17 C7 284 F4 H25 345
50. I/O 14 18 18 B7 283 F3 K23 351
VCC - - 19 A6 282 VCC** VCC** -
- - - - - 281* - - -
51. I/O - - 20 C8 280 F2 L24 354
52. I/O - - 21 E9 279 F1 K25 357
- - -22*---- -
- - - - - 278* - - -
- - - - - 277* - - -
53. I/O - - - B8 276 - L25 363
54. I/O - - - A8 275 - L26 366
55. I/O - 19 23 C9 274 G4 M23 369
56. I/O - 20 24 B9 273 G3 M24 375
57. I/O 15 21 25 E10 272 G2 M25 378
58. I/O 16 22 26 A9 271 G1 M26 381
59. I/O 17 23 27 D10 270 G5 N24 390
60. I/O 18 24 28 C10 269 H3 N25 393
GND 19 25 29 A10 268 GND** GND** -
VCC 20 26 30 A11 267 VCC** VCC** -
61. I/O 21 27 31 B10 266 H4 N26 399
62. I/O 22 28 32 B11 265 H5 P25 402
63. I/O 23 29 33 C11 264 J2 P23 405
64. I/O 24 30 34 E11 263 J1 P24 411
65. I/O - 31 35 D11 262 J3 R26 414
66. I/O - 32 36 A12 261 J4 R25 417
67. I/O - - - B12 260 - R24 423
68. I/O - - - A13 259 - R23 426
- - -37*---- -
- - - - - 258* - - -
- - - - - 257* - - -
69. I/O - - 38 E12 256 J5 T26 429
70. I/O - - 39 B13 255 K1 T25 435
- - - - - 254* - - -
VCC - - 40 A16 253 VCC** VCC** -
71. I/O 25 33 41 A14 252 K2 U24 438
72. I/O 26 34 42 C13 251 K3 V25 441
73. I/O 27 35 43 B14 250 J6 V24 447
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-243
74. I/O 28 36 44 D13 249 L1 U23 450
GND 29 37 45 A15 248 GND** GND** -
75. I/O - - - B15 247 - Y26 453
76. I/O - - - E13 246 - W25 459
77. I/O - - 46 C14 245 L2 W24 462
78. I/O - - 47 A17 244 K4 V23 465
79. I/O - 38 48 D14 243 L3 AA26 471
80. I/O - 39 49 B16 242 M1 Y25 474
81. I/O 30 40 50 C15 241 K5 Y24 477
82. I/O 31 41 51 E14 240 M2 AA25 483
83. I/O - - - A18 239 - AB25 486
84. I/O - - - D15 238 - AA24 489
85. I/O 32 42 52 C16 237 L4 Y23 495
86. I/O 33 43 53 B17 236 N1 AC26 498
87. I/O 34 44 54 B18 235 M3 AA23 501
88. I/O 35 45 55 E15 234 N2 AB24 507
89. I/O 36 46 56 D16 233 K6 AD25 510
90. I/O 37 47 57 C17 232 P1 AC24 513
91. M1 (I/O) 38 48 58 A20 231 N3 AB23 522
GND 39 49 59 A19 230 GND** GND** -
92. M0 (I/O) 40 50 60 C18 229 P2 AD24 525
- -51*----- -
- -52*----- -
- -53*----- -
- -54*----- -
VCC 41 55 61 B20 228 VCC** VCC** -
93. M2 (I/O) 42 56 62 D17 227 M4 AC23 528
94. GCK2 (I/O) 43 57 63 B19 226 R2 AE24 531
95. I/O (HDC) 44 58 64 C19 225 P3 AD23 540
96. I/O 45 59 65 F16 224 L5 AC22 543
97. I/O 46 60 66 E17 223 N4 AF24 546
98. I/O 47 61 67 D18 222 R3 AD22 552
99. I/O (LDC) 48 62 68 C20 221 P4 AE23 555
100. I/O - - - F17 220 - AE22 558
101. I/O - - - G16 219 - AF23 564
102. I/O 49 63 69 D19 218 K7 AD20 567
103. I/O 50 64 70 E18 217 M5 AE21 570
104. I/O - 65 71 D20 216 R4 AF21 576
105. I/O - 66 72 G17 215 N5 AC19 579
106. I/O - - 73 F18 214 P5 AD19 582
107. I/O - - 74 H16 213 L6 AE20 588
108. I/O - - - E19 212 - AF20 591
109. I/O - - - F19 211 - AC18 594
GND 51 67 75 E20 210 GND** GND** -
110. I/O 52 68 76 H17 209 R5 AD18 600
111. I/O 53 69 77 G18 208 M6 AE19 603
112. I/O 54 70 78 G19 207 N6 AC17 606
113. I/O 55 71 79 H18 206 P6 AD17 612
- - - - - 205* - - -
VCC - - 80 F20 204 VCC** VCC** -
114. I/O - 72 81 J16 203 R6 AE17 615
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-244 June 1, 1996 (Version 4.0)
115. I/O - 73 82 G20 202 M7 AE16 618
- - -83*---- -
- - - - - 201* - - -
- - - - - 200* - - -
116. I/O - - - H20 199 - AF16 624
117. I/O - - - J18 198 - AC15 627
118. I/O - - 84 J19 197 N7 AD15 630
119. I/O - - 85 K16 196 P7 AE15 636
120. I/O 56 74 86 J20 195 R7 AF15 639
121. I/O 57 75 87 K17 194 L7 AD14 642
122. I/O 58 76 88 K18 193 N8 AE14 648
123. I/O (ERR, INIT) 59 77 89 K19 192 P8 AF14 651
VCC 60 78 90 L20 191 VCC** VCC** -
GND 61 79 91 K20 190 GND** GND** -
124. I/O 62 80 92 L19 189 L8 AE13 660
125. I/O 63 81 93 L18 188 P9 AC13 663
126. I/O 64 82 94 L16 187 R9 AD13 672
127. I/O 65 83 95 L17 186 N9 AF12 675
128. I/O - 84 96 M20 185 M9 AE12 678
129. I/O - 85 97 M19 184 L9 AD12 684
130. I/O - - - N20 183 - AC12 687
131. I/O - - - M18 182 - AF11 690
- - -98*---- -
- - - - - 181* - - -
- - - - - 180* - - -
132. I/O - - 99 N19 179 R10 AE11 696
133. I/O - - 100 P20 178 P10 AD11 699
VCC - - 101 T20 177 VCC** VCC** -
- - - - - 176* - - -
134. I/O 66 86 102 N18 175 N10 AE9 702
135. I/O 67 87 103 P19 174 K9 AD9 708
136. I/O 68 88 104 N17 173 R11 AC10 711
137. I/O 69 89 105 R19 172 P11 AF7 714
GND 70 90 106 R20 171 GND** GND** -
138. I/O - - - N16 170 - AE8 720
139. I/O - - - P18 169 - AD8 723
140. I/O - - 107 U20 168 M10 AC9 726
141. I/O - - 108 P17 167 N11 AF6 732
142. I/O - 91 109 T19 166 R12 AE7 735
143. I/O - 92 110 R18 165 L10 AD7 738
144. I/O 71 93 111 P16 164 P12 AE6 744
145. I/O 72 94 112 V20 163 M11 AE5 747
146. I/O - - - R17 162 - AD6 750
147. I/O - - - T18 161 - AC7 756
148. I/O 73 95 113 U19 160 R13 AF4 759
149. I/O 74 96 114 V19 159 N12 AF3 768
150. I/O 75 97 115 R16 158 P13 AD5 771
151. I/O 76 98 116 T17 157 K10 AE3 774
152. I/O 77 99 117 U18 156 R14 AD4 780
153. I/O 78 100 118 X20 155 N13 AC5 783
GND 79 101 119 W20 154 GND** GND** -
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-245
- - 102* ----- -
DONE 80 103 120 V18 153 P14 AD3 -
- - 104* ----- -
- - 105* ----- -
VCC 81 106 121 X19 152 VCC** VCC** -
- - 107* ----- -
PROG 82 108 122 U17 151 M12 AC4 -
154. I/O (D7) 83 109 123 W19 150 P15 AD2 792
155. GCK3 (I/O) 84 110 124 W18 149 N14 AC3 795
156. I/O 85 111 125 T15 148 L11 AB4 804
157. I/O 86 112 126 U16 147 M13 AD1 807
158. I/O - - 127 V17 146 N15 AA4 810
159. I/O - - 128 X18 145 M14 AA3 816
160. I/O - - - U15 144 - AB2 819
161. I/O - - - T14 143 - AC1 828
162. I/O (D6) 87 113 129 W17 142 J10 Y3 831
163. I/O 88 114 130 V16 141 L12 AA2 834
164. I/O 89 115 131 X17 140 M15 AA1 840
165. I/O 90 116 132 U14 139 L13 W4 843
166. I/O - 117 133 V15 138 L14 W3 846
167. I/O - 118 134 T13 137 K11 Y2 852
168. I/O - - - W16 136 - Y1 855
169. I/O - - - W15 135 - V4 858
GND 91 119 135 X16 134 GND** GND** -
170. I/O - - 136 U13 133 L15 V3 864
171. I/O - - 137 V14 132 K12 W2 867
172. I/O 92 120 138 W14 131 K13 U4 870
173. I/O 93 121 139 V13 130 K14 U3 876
VCC - - 140 X15 129 VCC** VCC** -
- - - - - 128* - - -
174. I/O (D5) 94 122 141 T12 127 K15 V2 879
175. I/O (CS0) 95 123 142 X14 126 J12 V1 882
- - - 143* ---- -
- - - - - 125* - - -
- - - - - 124* - - -
176. I/O - - - X13 123 - T1 888
177. I/O - - - V12 122 - R4 891
178. I/O - 124 144 W12 121 J13 R3 894
179. I/O - 125 145 T11 120 J14 R2 900
180. I/O 96 126 146 X12 119 J15 R1 903
181. I/O 97 127 147 U11 118 J11 P3 906
182. I/O (D4) 98 128 148 V11 117 H13 P2 912
183. I/O 99 129 149 W11 116 H14 P1 915
VCC 100 130 150 X10 115 VCC** VCC** -
GND 101 131 151 X11 114 GND** GND** -
184. I/O (D3) 102 132 152 W10 113 H12 N2 924
185. I/O (RS) 103 133 153 V10 112 H11 N4 927
186. I/O 104 134 154 T10 111 G14 N3 936
187. I/O 105 135 155 U10 110 G15 M1 939
188. I/O - 136 156 X9 109 G13 M2 942
189. I/O - 137 157 W9 108 G12 M3 948
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-246 June 1, 1996 (Version 4.0)
190. I/O - - - X8 107 - M4 951
191. I/O - - - V9 106 - L1 954
- - - 158* ---- -
- - - - - 105* - - -
- - - - - 104* - - -
192. I/O (D2) 106 138 159 W8 103 G11 J1 960
193. I/O 107 139 160 X7 102 F15 K3 963
VCC - - 161 X5 101 VCC** VCC**
- - - - - 100* - -
194. I/O 108 140 162 V8 99 F14 J2 966
195. I/O 109 141 163 W7 98 F13 J3 972
196. I/O - - 164 U8 97 G10 K4 975
197. I/O - - 165 W6 96 E15 G1 978
GND 110 142 166 X6 95 GND** GND**
198. I/O - - - T8 94 - H2 984
199. I/O - - - V7 93 - H3 987
200. I/O - - 167 X4 92 E14 J4 990
201. I/O - - 168 U7 91 F12 F1 996
202. I/O - 143 169 W5 90 E13 G2 999
203. I/O - 144 170 V6 89 D15 G3 1002
204. I/O 111 145 171 T7 88 F11 F2 1008
205. I/O 112 146 172 X3 87 D14 E2 1011
206. I/O (D1) 113 147 173 U6 86 E12 F3 1014
207. I/O (RCLK-BUSY/RDY) 114 148 174 V5 85 C15 G4 1020
208. I/O - - - W4 84 - D2 1023
209. I/O - - - W3 83 - F4 1032
210. I/O 115 149 175 T6 82 D13 E3 1035
211. I/O 116 150 176 U5 81 C14 C2 1038
212. I/O (D0, DIN) 117 151 177 V4 80 F10 D3 1044
213. I/O (DOUT) 118 152 178 X1 79 B15 E4 1047
CCLK 119 153 179 V3 78 C13 C3 -
VCC 120 154 180 W1 77 VCC** VCC** -
- - 155* ----- -
- - 156* ----- -
- - 157* ----- -
- - 158* ----- -
214. I/O (TDO) 121 159 181 U4 76 A15 D4 0
GND 122 160 182 X2 75 GND** GND** -
215. I/O (A0, WS) 123 161 183 W2 74 A14 B3 9
216. GCK4 (A1, I/O) 124 162 184 V2 73 B13 C4 15
217. I/O 125 163 185 R5 72 E11 D5 18
218. I/O 126 164 186 T4 71 C12 A3 21
219. I/O (A2, CS1) 127 165 187 U3 70 A13 D6 27
220. I/O (A3) 128 166 188 V1 69 B12 C6 30
221. I/O - - - R4 68 - B5 33
222. I/O - - - P5 67 - A4 39
223. I/O - - 189 U2 66 F9 C7 42
224. I/O - - 190 T3 65 D11 B6 45
225. I/O 129 167 191 U1 64 A12 A6 51
226. I/O 130 168 192 P4 63 C11 D8 54
227. I/O - 169 193 R3 62 B11 B7 57
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
June 1, 1996 (Version 4.0) 4-247
Notes: * Indicates unconnected package pins.
† leading numbers refer to bonded pad, shown in Figure 26, Figure 27 or Figure 28.
** Pins labeled VCC** are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, E1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7,
G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GND** are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for
the BG225 are: A1, D12, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352
are: A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
228. I/O - 170 194 N5 61 E10 A7 63
229. I/O - - 195 T2 60 - D9 66
230. I/O - - - R2 59 - C9 69
GND 131 171 196 T1 58 GND** GND** -
231. I/O 132 172 197 N4 57 A11 B8 75
232. I/O 133 173 198 P3 56 D10 D10 78
233. I/O - - 199 P2 55 C10 C10 81
234. I/O - - 200 N3 54 B10 B9 87
- - - - - 53* - - -
VCC - - 201 R1 52 VCC** VCC** -
235. I/O - - - M5 51 - B11 90
236. I/O - - - P1 50 - A11 93
- - - - - 49* - - -
- - - - - 48* - - -
237. I/O (A4) 134 174 202 N1 47 A10 D12 99
238. I/O (A5) 135 175 203 M3 46 D9 C12 102
- - - 204* ---- -
239. I/O - 176 205 M2 45 C9 B12 105
240. I/O 136 177 206 L5 44 B9 A12 111
241. I/O 137 178 207 M1 43 A9 C13 114
242. I/O 138 179 208 L4 42 E9 B13 117
243. I/O (A6) 139 180 209 L3 41 C8 A13 126
244. I/O (A7) 140 181 210 L2 40 B8 B14 129
GND 141 182 211 L1 39 GND** GND** -
Pin Locations for XC5215 Devices
Pin Description †PQ160 HQ208 HQ240 PG299 HQ304 BG225 BG352 Boundary Scan Order
XC5200 Field Programmable Gate Arrays
4-248 June 1, 1996 (Version 4.0)
Product Availability
Notes: Parentheses indicate future product plans C = Commercial TJ = 0° to +85°C I= Industrial TJ = -40°C to +100°C
User I/O Per Package
Ordering Information
PINS 84 100 100 144 156 160 176 191 208 208 223 225 240 240 299 304 352
TYPE Plast.
PLCC Plast.
PQFP Plast.
VQFP Plast.
TQFP Ceram.
PGA Plast.
PQFP Plast.
TQFP Ceram.
PGA High-
Perf.
QFP
Plast.
PQFP Ceram.
PGA Plast.
BGA High-
Perf.
QFP
Plast.
PQFP Ceram.
PGA High-
Perf.
QFP
Plast.
BGA
CODE PC84 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 HQ304 BG352
XC5202 -6 CI CI CI CI CI
-5 CI CI CI CI CI
-4 (CI) (CI) (CI) (CI) (CI)
-3 (CI) (CI) (CI) (CI) (CI)
XC5204 -6 CI CI CI CI CI CI
-5 CI CI CI CI CI CI
-4 (CI) (CI) (CI) (CI) (CI) (CI)
-3 (CI) (CI) (CI) (CI) (CI) (CI)
XC5206 -6 CI CI CI CI CI CI CI CI
-5 CI CI CI CI CI CI CI CI
-4 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI)
-3 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI)
XC5210 -6 CI CI CI CI CI CI CI CI
-5 CI CI CI CI CI CI CI CI
-4 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI)
-3 (CI) (CI) (CI) (CI) (CI) (CI) (CI) (CI)
XC5215 -6 CI CI CI CI CI CI CI
-5 CI CI CI CI CI CI CI
-4 (CI) (C) (CI) (CI) (CI) (CI) (CI)
-3 (CI) (C) (CI) (CI) (CI) (CI) (CI)
Device Max
I/O
Package Type
PC84 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 HQ304 BG352
XC5202 84 65 81 81 84 84
XC5204 124 65 81 81 117 124 124
XC5206 148 65 81 81 117 133 148 148 148
XC5210 196 65 117 133 149 164 196 196 196
XC5215 244 133 164 196 197 244 244 244
XC5210-6PQ208C
Package Type
Number of Pins
Temperature Range
Speed Grade
Device Type
Example:
June 1, 1996 (Version 1.0) 4- 249
s
Features
• High-density family of Field-Prog rammab le Gate Arr a ys
(FPGAs)
• JEDEC-compliant 3.3 V version of XC5200 FPGA
family
• Design- and process-optimized for low cost
- 0.5-µm three-layer metal (TLM) process
• SRAM-based, in-system reprogrammable architecture
• Flexible architecture with abundant routing resources
- VersaBlock™ logic module
- VersaRing™ I/O interface
- Dedicated cell-feedthrough path
- Hierarchical interconnect structure
- Extensive registers/latches
- Dedicated carry logic for arithmetic functions
- Cascade chain for wide input functions
- Dedicated IEEE 1149.1 boundary-scan logic
- Internal 3-state bussing capability
- Four global low-skew clock or signal distribution nets
- Output slew-rate control
- 4-mA sink current per output
• Configured by loading binary file
- Unlimited reprogrammability
- Seven programming modes, including high-speed
Express™ mode
• 100% factory tested
• 100% architecture, pin-out and bit-stream compatible
with XC5200 families
• 100% footprint compatibility for common packages
• 5 V tolerant inputs
• Fully supported by XACT
step
™ Development System
- Includes complete support for XA CT-Perf ormance™,
X-BLOX™, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
- Wide selection of PC and workstation platforms
- Interfaces to more than 100 third-party CAE tools
Description
The XC5200L Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200L architecture f or three-la y er
metal technology and 0.5-µm CMOS SRAM process, dra-
matic advances have been made in silicon efficiency.
These advances position the XC5200L family as a cost-
effective, high-volume alternative to gate arrays.
Building on experiences gained with three previous suc-
cessful SRAM FPGA families , the XC5200L family brings a
robust feature set to high-density programmable logic
design. The VersaBlock logic module, the VersaRing I/O
interface, and a rich hierarchy of interconnect resources
combine to enhance design flexibility and reduce time-to-
market.
Complete support for the XC5200L family is delivered
through the familiar XACT
step
software environment. The
XC5200L family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and syn-
thesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200L devices.
XC5200L
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0) Advance Product Specification
Table 1: Initial XC5200L Field-Programmable Gate Array Family Members
Device XC5202L XC5206L XC5215L
Max Logic Gates 3,000 10,000 23,000
Typical Gate Range 2,000 - 3,000 6,000 - 10,000 15,000 - 23,000
VersaBlock Array 8 x 8 14 x 14 22 x 22
Number of CLBs 64 196 484
Number of Flip-Flops 256 784 1,936
Number of I/Os 84 148 244
TBUFs per Horizontal Longline 10 16 24
XC5200L Field Programmable Gate Arrays
4- 250 June 1, 1996 (Version 1.0)
XC5200L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents . To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC5200L Operating Conditions
XC5200L DC Characteristics Over Operating Conditions
XC5200L Absolute Maximum Ratings
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial: TJ=0°C to 85°C junction 3.0 3.6 V
VIH High-level input voltage—CMOS configuration 2.0 5.0 V
VIL Low-level input voltage—CMOS configuration -0.3 0.8 V
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -4 mA, VCC min 2.4 V
VOL Low-level output voltage @ IOL = 4 mA, VCC max (Note 1) 0.4 V
ICCO Quiescent FPGA supply current (Note 2) N/A mA
IIL Leakage current -10 +10 µA
CIN Input capacitance (sample tested) 15 pF
IRIN Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 0.25 mA
Notes: 1. With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
2. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a
MakeBits tie option.
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction temperature in plastic packages +125 °C
Junction temperature in ceramic packages +150 °C
Note:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
4-251
XC6200 Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-253
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Logical and Physical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Cells, Blocks and Tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-254
Routing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-256
Magic Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Global Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Function Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-257
Cell Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-258
Routing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-259
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
Clear Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
Input/Output Blocks (IOBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-261
I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-263
Designing with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Board Design with XC6200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Logic Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-265
Software Design with XC6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-267
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-267
Map Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-268
Wildcard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-270
Serial Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-271
Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-272
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-273
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-274
XC6200 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-275
XC6200 Power-on/Reset Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Serial Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Cell Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-276
XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) . . . . . . . . . . . . . . . . . . . . . . . . 4-277
XC6200 IOB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-277
XC6200 Internal Routing Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-278
XC6200 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-278
XC6200 Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-282
XC6216 Pinouts - West Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-282
XC6216 Pinouts - South Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-283
XC6216 Pinouts - East Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-284
XC6216 Pinouts - North Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-285
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-286
XC6200 Series Table of Contents
XC6200 Series Table of Contents
4-252
June 1, 1996 (Version 1.0) 4- 253
Features
• Advanced Processor-Compatible Architecture
- FastMAP™ interface allows direct processor read/
write access to all internal registers in user design
with no logic overhead
- All user registers and SRAM control store memory
mapped onto processor address space
- Programmable data bus width (8, 16, 32-bits)
- Easily interfaced to most microcontrollers and
microprocessors
• High-Performance Sea-of-Gates FPGA
- Up to 16K configurable cells
- Abundant registers, gates and routing resources
- Extremely high gate count for structured logic or
datapath designs
• High Capacity Distributed RAM
- High speed SRAM control store
- 2 bytes of synchronous RAM per cell
• High Speed Flexible Interconnect Architecture
- Low delay hierarchical routing scheme gives large
number of fast ‘longlines’ (Fastlanes)
- Any cell can be connected to any other
- Suited to both structured synchronous cell data path
type designs or irregular random logic
- Completely flexible clocks and clears for registers
- 4 Global low-skew signals
• >110MHz flip-flop toggle rates
• Extremely Flexible Cell Architecture
- Over 50 distinct logic functions per cell
- One register and gate/multiplexer possible for
every
cell
• Advanced Dynamic Reconfiguration Capability
- High speed reconfiguration via parallel CPU
interface
- Unlimited reprogrammability
- Full or partial reconfiguration/context switching
possible
- Ideal for custom computing applications
• Flexible Pin Configuration
- All User I/O’s programmable as in, out, bidirect, tri-
state or open drain.
- Configurable pull-up/down resistors
- CMOS or TTL logic levels
- 8, 16, 32-bit CPU interface
• Testability
- Pre-tested volume part
- JTAG capability with library macrocells
•XACT
step
Series 6000 Development System
- Implement designs using familiar tools lik e Vie wlogic
and Synopsys
- Use PC or Unix workstation platforms
- Fully automatic mapping, placement and routing
- Interactive Physical Editor for design optimization
- Large Xilinx parts library for schematic capture
- VHDL synthesis
Notes: 1. Planned Product
XC6200
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0) Advance Product Specification
Table 1: The XC6200 Family of Field-Programmable Gate Arrays
Device XC6209 1XC6216 XC6236 1XC6264 1
Max Logic Gates 13,000 24,000 55,000 100,000
Typical Gate Range 9,000 - 13,000 16,000 - 24,000 36,000 - 55,000 64,000 - 100,000
Number of Cells 2304 4096 9216 16384
Max. No. Registers 2304 4096 9216 16384
Number IOB’s 192 256 384 512
Cell Rows x Columns 48x48 64x64 96x96 128x128
Max. RAM (bits) 36K 65K 147K 262K
XC6200 Field Programmable Gate Arrays
4- 254 June 1, 1996 (Version 1.0)
Description
The XC6200 family is a ne w type of high perf ormance Field
Programmable Gate Array (FPGA) from Xilinx.
The XC6200 series is a family of fine-grain, sea-of-gates
FPGAs. These de vices are designed to operate in close co-
operation with a microprocessor or microcontroller to pro-
vide an implementation of functions normally placed on an
ASIC. These include interfaces to external hardware and
peripherals, glue logic and custom coprocessors, including
bit level and systolic operations unsuited for standard pro-
cessors.
XC6200 FPGAs can provide e xtremely high gate counts f or
data path or regular array type designs. In these cases the
actual gate count may be considerably higher than those
given in Table 1.
An XC6200 part is composed of a large array of simple,
configurable cells. Each basic cell contains a computation
unit capable of simultaneously implementing one of a set of
logic level functions
and
a routing area through which inter-
cell communication can take place. The structure is simple,
symmetrical, hierarchical and regular, allowing novice
users to quickly make efficient use of the resources avail-
able.
The nearest-neighbor interconnect of the cells is supple-
mented with wires of length 4, 16 and chip-length (CL)
cells, called F astLane-4, 16 and CL respectiv ely, which pro-
vide low-delay paths for longer connections. In addition
there are four global input signals which pro vide a low-sk ew
distribution path f or critical high-fan-out nets such as cloc ks
and initialization signals.
An XC6200 part is configured by the content of an integral,
highly stable six-transistor SRAM control store. This allows
XC6200 parts to be quickly reconfigured an unlimited n um-
ber of times. The SRAM control store can be mapped into
the address space of a host processor and additional sup-
por t logic is provided to allow rapid reconfiguration of all or
par t of the device. In addition, the outputs of function units
within the device can be read by a processor through the
RAM interface . A host processor can read or write registers
within logic implemented on the device. Data transfers can
be 8, 16 or 32 bits wide, e v en when register bits are distrib-
uted over a column of cells. These capabilities allow
XC6200 FPGAs to support virtualised hardware in which
circuits running on the FPGA can be saved (`swapped out’)
to allow the FPGA resources to be assigned to a different
task, then restored (`swapped in’) at a later time with the
correct internal state in their registers. Sections of the
device can be reconfigured without disturbing circuits run-
ning in other sections. Thus an XC6200 FPGA in a copro-
cessor application can be time-shared by several
processes running on the host computer.
Design entry and verification are carried out with Xilinx
XACT
step
Series 6000 software using industry-standard
schematic capture, synthesis and simulation packages
such as Vie wlogic , Synopsys and Mentor Graphics . A com-
prehensive library of parts, ranging from simple gate primi-
tives to complex macro-functions, exists to make this an
easy task.
Below the top le v el design tools, the XC6200 product f amily
is supported by a n umber of CAD tools ranging from simple
symbolic editors to sophisticated cell-compilation tools.
These tools will ensure that the captured design is laid out
efficiently with no user intervention. Node delays can then
be back-annotated to the top le v el logic simulator. The tools
also allow for manual intervention in the layout process, if
desired. Incremental design is also supported: if a design is
laid out and subsequently changed, only the modified bloc k
has to be re-laid out.
The functions available within each cell provide a good tar-
get for logic synthesis programs. The simple cell architec-
ture allows arbitrary user logic designs to be mapped onto
a number of cells, rather than having to split the design up
into medium-complexity mini-functions for mapping to a
larger configurable logic block. Because each cell can be
configured as a register, designs containing far more regis-
ters than would be possible with a larger configur ab le b loc k
are achievable.
Detailed Functional Description
Logical and Physical Organization
The XC6200 architecture may be viewed as a hierarchy. At
the lowest level lies a large array of basic cells (Figure 1).
This is the ‘sea-of-gates’. Each cell is individually program-
mable to implement a D-type register and a 2-input logic
function such as a multiple xer or gate . Any cell ma y also be
configured to implement a purely combinatorial function,
with no register. This is illustrated in Figure 7.
Cells, Blocks and Tiles
First generation fine-grain architectures implemented only
nearest-neighbor interconnection and had no hierarchical
routing (Figure 1). The XC6200 architecture is a second
generation fine-grain architecture, employing a hierarchical
cellular array structure. Neighbor-connected cells are
grouped into Blocks of 4x4 cells (Figure 2) that themselves
form a cellular array, communicating with neighboring 4x4
cell Blocks. A 4x4 array of these 4x4 Blocks forms a 16x16
cell Tile (Figure 3). In the XC6216 part, a 4x4 array of these
16x16 Tiles forms the central 64x64 cell arra y which is then
surrounded by I/O pads (Figure 4).
June 1, 1996 (Version 1.0) 4- 255
Figure 1: Nearest-Neighbor Interconnect Array Structure
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
Figure 2: XC6200 4x4 Cell Block
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
N4
S4
E4
W4
Length 4 Fastlanes
Figure 3: XC6200 16x16 Cell Tile
4x44x4 4x4
4x44x4 4x4
4x44x4 4x4 4x4
4x44x4 4x4 4x4
N16
S16
E16
W16
Four Length 16 Fastlanes
(Remainder hidden for clarity)
Figure 4: XC6216 Device
16x16
Each Arrow = Sixteen Chip-Length Fastlanes
16x16 16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
64 User IOBs (1 per border cells)
(Only 1 shown for clarity)
XC6200 Field Programmable Gate Arrays
4- 256 June 1, 1996 (Version 1.0)
Routing Resources
Each level of hierarchy (basic cells, 4x4 cell Blocks, 16x16
cell Tiles, 64x64, etc.) has its own associated routing
resources. Basic cells can route to their nearest neighbors
or through the neighbor cell to its neighbor. Note that cells
used for interconnect in this manner can still be used to pro-
vide a logic function. Wires of length four are provided to
allow 4x4 cell blocks to route across themselves without
using basic cell resources. Similarly 16x16 cell tiles provide
additional wires of length 16 cells and the 64x64 array pro-
vides wires of length 64. Larger XC6200 products extend
this process to 256x256 cell blocks and so on, scaling by a
factor of 4 at each hierarchical le vel as required. Intermedi-
ate array sizes (e.g. 96x96) are created by adding more
16x16 tiles. Switches at the edge of the blocks and tiles
provide for connections between the various levels of inter-
connect at the same position in the array (e.g. connecting
length 4 wires to neighbor wires).
The longer wires provided at each hierarchical level are
termed ‘Fastlanes’ because it is convenient to visualize the
structure in three dimensions with routing at each hierarchi-
cal lev el being conceptually abo v e that in low er hierarchical
levels, with the cellular array as the base layer. The length-
4 F astlanes are driven b y special routing multiplex ers within
the cells at 4x4 block boundaries. All routing wires are
directional. The y are alwa ys labelled according to the signal
travel direction. For example, S4 is a length-4 Fastlane
heading from North to South. In Figures 2, 3 and 4 each
individual cell has a length 4, 16 and CL Fastlane above it.
However only a small number are shown for clarity.
The benefit of the additional wiring resources provided at
each level of the hierarchy is that wiring delays in the
XC6200 architecture scale logarithmically with distance in
cell units rather than linearly as is the case with the first
generation neighbor interconnect architectures. Since 4x4
cell bloc k boundaries lie on unit cell boundaries, the switch-
ing function provided at 4x4 cell boundaries is a superset of
that provided at unit cell boundaries. i.e it provides for
neighbor interconnect between the adjacent cells as well as
additional switching options using the length 4 wires. Simi-
larly, the switching unit on 16x16 cell tile boundaries pro-
vides a superset of the permutations available from that on
the 4x4 cell block boundaries. Further switching units are
also provided on the 64x64 cell boundaries to provide the
length CL Fastlanes.
Figure 5: XC6200 Basic Cell
Function
Unit
N S E WN4 E4W4S4
N
S
E
W
N4
E4
W4
S4
N
S
E
W
N4
E4
W4
S4
X3
X1 X2
F
SEWF
Sout
N
S
W
F
Wout N
S
E
F
Eout
NEWF
Nout
SS4
E4
N
W4
N4
E
W
Clk
Clr
CLR
CLK
X2 X3
MAGIC
June 1, 1996 (Version 1.0) 4- 257
Magic Wires
The majority of interconnections are routed using the near-
est-neighbor and Fastlane wires described above. Each
cell has a further output (labelled ‘Magic’) which provides
an additional routing resource. A cell’s Magic output is not
always available for routing. Its availability is dependent on
the logic function implemented inside the cell. More infor-
mation on the physical nature of the Magic wires is given in
the section “Function Unit” on page 257.
Each cell’s Magic output is routed to two distinct 4x4 block
boundary switches. The Magic wire can be driven by N, S,
E or W from adjacent cells or from the N4, S4, E4 or W4
Fastlanes passing over the cell. This makes it particularly
useful for corner-turning (all other routing resources are
straight).
The Magic wires are illustrated in Figure 8.
Global Wires
The XC6200 architecture permits registers within a user
design to be clocked by different clocks and cleared by dif-
ferent asynchronous clears . Clocks and Clears ma y be pro-
vided by any user I/O pin or generated from user logic
internally . In line with good synchronous digital design prac-
tices, it is recommended that a single global Clock and
Clear are used. This minimizes the likelihood of timing
problems and gives more reliable simulations.
Four Global wires (G1, G2, GClk and GClr) are pro vided f or
low skew, low delay signals. These wires are intended for
global Clock and Clear or other high f an-out signals and are
distributed throughout the array in a low skew pattern. A
global signal can reach the function block inputs of any cell
on the arra y passing through very fe w routing s witches. The
four Globals are very similar. It would be possible to use
GClk as a global Clear signal, however for minimum delay,
it is recommended that GClk be used for global clocks and
GClr for global clears. GClk and GClr can reach the inputs
of any register in the array, passing through only a single
routing switch. G1 and G2 may be used for secondary glo-
bal clocks or clears. G1 and G2 have a slightly larger delay
than GClk and GClr.
Function Unit
Figure 5 shows the basic XC6200 cell in detail. The inputs
from neighboring cells are labelled N, S, E, W and those
from length 4 wires N4, S4, E4, W4 according to their signal
direction. Additional inputs include Clock and Asynchro-
nous Clear for the Function Unit D-type register. The output
from the cell function unit, which implements the gates and
registers required by the user’s design, is labelled F. The
Magic output is used for routing as described earlier. The
multiplexers within the cell are controlled by bits within the
configuration memory. As can be seen from Figure 5, the
basic cells in the array have inputs from the length 4 wires
associated with 4x4 cell blocks as well as their nearest
neighbor cells. The function unit design allows the cells to
efficiently support D-type registers with Asynchronous
Clear and 2:1 multiple xers, as well as all Boolean functions
of two v ariables (
A
and
B
) chosen from the inputs to the cell
(N,S,E,W,N4,S4,E4,W4) (Table 2). Figure 7 shows the
schematic representations of the basic cell functions possi-
ble . The Magic routing output can only be used if the signal
to be routed can be placed on X2 or X3.
Figure 6: XC6200 Function Unit
X2 Y2
X3 Y3
X1
1
0RP Mux
DQ
Clk
Clr
CS Mux
F
XC6200 Field Programmable Gate Arrays
4- 258 June 1, 1996 (Version 1.0)
Figure 6 shows the implementation of the XC6200 function
unit. The design uses the fact that any function of two Bool-
ean variables can be computed by a 2:1 multiplexer if suit-
able values chosen from the input variables and their
complements are placed on its inputs. The Y2 and Y3 mul-
tiplexers provide for this conditional inversion of the inputs.
The CS multiplexer selects a combinatorial or sequential
output. The RP m ultiplexer allows the contents of the regis-
ter to be ‘protected’. If register protection is enabled then
only the programming interface can write to the register. It
will not change when the X inputs to the function unit
change,
even if it is clocked or cleared
. This feature is use-
ful in designs containing control registers which are only to
be written by an external microprocessor. The control
inputs of all the multiplexers, except the one switched by
X1, come from configuration memory bits.
Cell Logic Functions
Each cell can be configured as any two-input gate function,
any flavor of 2:1 multiplexer, constant 0 or 1, single input
functions (buffer or inverter) or any of these in addition to a
D-type register. This is illustrated in Figure 7. The gate
names given correspond to standard Xilinx library part
names for these primitives. Although three inputs are
shown entering the combinatorial ‘cloud’, dual and single
input functions are also possible (e.g. inverter + register or
register alone.) The buffer symbol is available in the CAD
libraries, however the place and route software will gener-
ally optimize this out as there is no requirement for the
designer to buffer signals with this architecture. This is
because signals are regularly buff ered by routing m ultiple x-
ers. Symmetrical functions are also possible but not shown
in Figure 7; e.g.
A•B
(AND2B1) is shown b ut
A•B
(AND2B2)
is not. This is because
A
and
B
are assigned to user signals
by the logic mapping softw are to provide the required func-
tion. Thus, a multiplexer with inversion on the SEL input is
unnecessary because the mapping software can simply
swap the signal assignments for
A
and
B
.
The sources of the X1, X2 and X3 input multiple xers are set
automatically by CAD software during the logic mapping
phase. Table 2 shows the assignments for all the cell multi-
plexers to compute the various logic gate functions. A
NAND2B1 is equivalent to an OR2B1 with the inputs
swapped and a NOR2B1 is equivalent to an AND2B1 with
the inputs swapped; therefore, these gates are not listed in
Table 2.
If the register within a cell is not used in the design then a
special ‘f ast’ version of most gates can be configured, using
the register to provide a constant 1 or 0. For example a fast
AND gate (
A•B
) can be configured by setting the register to
0 during configuration and assigning Q to Y3.
A
is routed to
X1 and
B
to X2. X2 is assigned to Y2. When
A
changes to
Figure 7: Cell Logic Functions
ZERO
ONE
BUF
A
INV
A
A
BAND2
A
BAND2B1
A
BNAND2
A
BNAND2B1
A
BOR2
A
BOR2B1
A
BNOR2
A
BNOR2B1
A
BXOR2
A
BXNOR2
A
B
SEL
A
B
SEL
A
B
SEL
A
B
SEL
DQ
CLK
CLR
A
BDQ
CLK
CLR
A
F F DQ
CLK
CLR
AF
M2_1
M2_1B1A
M2_1B1B
M2_1B2
SEL SEL SEL
A
B
SEL
F
June 1, 1996 (Version 1.0) 4- 259
0, Y3 is selected and F is forced low as soon as the X1-con-
trolled multiplexer switches. In the nor mal AND gate, there
would be an additional delay as
A
propagated through the
Y3 multiplexer. Fast or normal gates may be specified by
the designer but, for optimal layout density, this is best left
to the logic mapping software.
The multiplexer functions have a straightforward mapping
with fixed assignments to X1,X2 and X3, and Y2 and Y3
providing input inversions as required.
Routing Switches
As described earlier, each cell within a 4x4 block is able to
drive its output to its nearest neighbors to the N,S,E and W.
In addition to this, cells at 4x4 block boundaries are also
able to drive their outputs onto length-4 Fastlanes. Special
switch units are provided around each 4x4 block boundary
to facilitate these connections . This is illustr ated in Figure 8.
These switches also allo w higher le vels of hier archical rout-
ing (e.g. length – 16 and CL Fastlanes) to be connected to
length-4 Fastlanes.
Figure 8 also shows the connections for each cell’s Magic
output. Each Magic output is routed to two destinations for
increased routing flexibility. The two connections are
labelled M and MA. The Magic wires allow cell outputs to
jump to the edge of the 4x4 bloc k and hence onto F astlanes
or into the next 4x4 block. They are also a particular ly effi-
cient way of making large busses turn corners.
N,S,E and W switches are similar, however the N switches
contain additional multiplexers to drive the register Clock
lines. The contents of the boundary switches are shown in
Figure 9 through Figure 12. The multiplexers driving the
NOut, SOut, EOut and WOut lines are actually imple-
mented within the cell adjacent to the switch. These multi-
plexers take the place of the neighbor multiple xers found in
the basic cell (see Figure 5). Boundar y cells contain addi-
tional RAM bits to control the larger multiplexers. An addi-
tional output is available from these multiplexers. This
output reflects the output that would have come from the
cell’s neighbor multiplexer had it been a basic non-bound-
ary cell. To distinguish this from the output of the boundar y
switch (NOut, SOut, EOut or WOut), it is suffixed with a ‘C’
(Cell); e.g. NC for an Nswitch. NC will be one of NIn, E, W,
Table 2: Function Derivation
Function X1 X2 X3 Y2 Y3 RP CS Q
0 (Fast) XXXXXQS0
0 AAAX2
X3XCX
1 (Fast) XXXXXQS1
1 A A A X2 X3 XCX
BUF (Fast) A X X Q Q QC1
BUF X A A X2 X3 X C X
INV (Fast) A X X Q Q QC0
INV X A A X2 X3 XCX
A•B (Fast) A B X X2 Q Q C 0
A•B A B A X2 X3 X C X
A•B (Fast) A X B Q X3 Q C 0
A•B A A B X2 X3XCX
A
•B (Fast) A B X X2 QQC1
A
•B ABAX2X3 XCX
A+B (Fast) A X B Q X3 Q C 1
A+B A A B X2 X3 X C X
A+B (Fast) A B X X2 Q Q C 1
A+B A B A X2 X3 XCX
A+B (Fast) A X B Q X3 QC0
A+B AABX2X3 XCX
A⊕B ABBX2
X3XCX
A
⊕BA B B X2 X3 XCX
M2_1 SEL A B X2 X3 X C X
M2_1B1A SEL A B X2 X3 X C X
M2_1B1B SEL A B X2 X3 XCX
M2_1B2 SEL A B X2 X3 XCX
XC6200 Field Programmable Gate Arrays
4- 260 June 1, 1996 (Version 1.0)
or F depending on the least-significant two bits of the NOut
multiplexer select lines. Hence NC will be identical to NOut
if NOut is one of F, NIn, E or W. If NOut is one of N4In, N16,
PS4 or MN then NC will be one of F, NIn, E or W depending
on which signal is routed to NOut. The ‘C’ signal will be one
of the upper four inputs to the 8:1 multiplexers shown in
Figure 9 through Figure 12, the actual value being selected
by the two least-significant multiplexer select lines. Similar
‘C’ signals are generated in the Sswitch, Eswitch, and
WSwitch.
The S4 input to the NOut multiple xer in the Nswitch is actu-
ally the S4
input
to the adjacent Sswitch in the 4x4 block
immediately to the North of this block. This should not be
confused with the S4Out signal from that block’s Sswitch.
This is also true of some of the other inputs to the multiplex-
ers in other boundary switches. To avoid confusion, these
inputs are prefixed with the letter ‘P’ (for Previous). e.g.
PS4. This feature allows F astlane wires to perform U-turns.
Figure 8: Routing Switches at 4x4 Block Boundary
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
CellCell Cell Cell
SswitchSswitch Sswitch Sswitch
NswitchNswitch Nswitch Nswitch
Eswitch
Eswitch
Eswitch
Eswitch
Wswitch
Wswitch
Wswitch
Wswitch
MA nets
M nets
Figure 9: Contents of Nswitch
Figure 10: Contents of Sswitch
Figure 11: Contents of Eswitch
Figure 12: Contents of Wswitch
SCIn
NCL
N16
NCOut
ClkIn
MNA
PS16
N4In N4Out
MN
MS
SCL
GClr
NCL
G1
G2 ClkIn
NOut
GClk
ClkOut
Nswitch
F
NIn
E
W
N4In
PS4
MN
N16
NOut
NCOut
MN
NCL
S16
MSA
SCL
MS S4Out
S4In
PN16
Sswitch
F
E
W
SIn
S16
S4In
MS
PN4
SOut
SCOut
SCOut
NCIn
MW
MEA
PW16
WCL
ECOut
ME
E16
E4In E4Out
ECL
WCIn
Eswitch
F
N
EIn
S
PW4
E16
E4In
ME
EOut
ECOut
WCOut
ME
W16
W4In
MWA
ECIn
W4Out
PE16
MW
Wswitch
F
WIn
N
S
PE4
MW
W4In
W16
WOut
WCOut
ECL
WCL
June 1, 1996 (Version 1.0) 4- 261
Clock Distribution
As described previously, register clock inputs may be
driven from any source b ut it is recommended that the GClk
signal is used. GClk also has the advantage that it can be
stopped by writing to the Device Configuration Register.
The Global wires enter the part through dedicated input
pins and are distributed in a special low-skew ‘H’ pattern
(Figure 13). Each vertically aligned (South to Nor th) group
of four cells within a 4x4 block is clocked by its own clock
source. This is driven from a multiplexer in the Nswitch
immediately to the South of the group of cells. The connec-
tions for this multiplexer are shown in Figure 9. ClkOut
drives the Clk inputs to each of the four cells in the group.
As can be seen from Figure 9, the register clock for each
group of four cells can be driven by ClkIn, NOut, GClk,
GClr , G1, G2 or NCL. ClkIn is the ClkOut from the 4x4 b lock
to the South, allowing vertical daisy-chaining of clock sig-
nals. NOut is the N output from the cell associated with the
Nswitch. This can be used to provide local user-generated
or gated clock signals if required. GClk is the Global Clock
signal direct from the device GClk input. Clear ly this signal
only has to pass through one 4:1 multiple x er whereas GClr ,
G1 and G2 have to pass through two. This is one reason
why there is less delay on GClk.
It is also possible to route North chip-length Fastlanes onto
the Clock lines. This allows up to 64 (for a XC6216 device)
locally used clocks to be provided that can still run the
entire length of the chip with minimal skew. These local
clock signals ma y be generated internally (e.g. b y dividing a
faster clock) or sourced directly from the device program-
mable I/O pins.
Where a fast cloc k is required b y only a small fraction of the
logic on the device it may be preferable to employ user
interconnect resources rather than a Global or Chip-Length
Fastlane, since limiting fast clock distribution to the area of
the device where it is required will reduce power consump-
tion.
Clear Distribution
Register Clear inputs are routed in a similar manner to
Clock inputs. In this case ver tical groups of 16 cells, within
a 16x16 tile, share a common Clear. Clear lines run in a
Southerly direction and are sourced from the Sswitch unit
of 4x4 bloc ks which also lie on a 16x16 boundary. All of the
boundary switches at 16x16 boundaries contain additional
switching multiplexers. These are illustrated in Figure 14.
ClrOut drives the Clr inputs to each of the sixteen cells in
the group . The S and SCL connections allow the output of a
cell to provide a user-generated local Clear signal.
Input/Output Blocks (IOBs)
User-configurable Input/Output Blocks (IOBs) provide the
interface between external package pins and the internal
logic.
One IOB is provided f or e v ery cell position around the array
border. IOBs are connected to fixed pad locations. There
are more IOBs than available pads, hence some IOBs are
‘padless’. However it is still possible to route signals from
padless IOBs to device pins.
Figure 15 is a simplified diagram of an IOB and its associ-
ated IO pad. The IOB is located at the arr ay border and the
pad is located close to its device pin. The pad may be
located some distance from its associated IOB. The map-
Figure 13: Low Skew ‘H’ Distribution Of Global Signals (XC6216)
Global Input
16x16 16x16 16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
16x16
Figure 14: Additional Switches at 16x16 Boundaries
NCL
SCL
N16In
N4In
PS4
SCIn
MN
NCOut
N16Out
WCL
ECL
E16In
PW4
E4In
ECOut
ME
WCIn
E16Out
WCL
ECL
W16In
W4In
PE4
ECIn
MW
WCOut
W16Out
NCL
SCL
S16In
PN4
S4In
SCOut
MS
NCIn
S16Out
North Boundary East Boundary West Boundary
South Boundary GClr
ClrIn
SCL
G2
GClk
SOut
G1
0
ClrOut
XC6200 Field Programmable Gate Arrays
4- 262 June 1, 1996 (Version 1.0)
ping of IOBs to device pins is given in the pinout tables
starting on page 282.
The XC6200 IOB architecture incorporates a novel and
very powerful feature: every IOB has the capability of rout-
ing either an arra y signal or a control logic signal to/from the
device pin. Every signal, including all the control signals
(e.g.
CS, RdWr, Address Bus, Data Bus, etc.), passes
through an IOB. This means that all the control signals can
be routed into the logic array for use in user designs. Simi-
larly, user logic can control the XC6200 internal control cir-
cuitry. For e xample a user signal could be used to drive the
internal CS signal rather than the CS pin.
As an example of the power of this feature, an XC6200
design could include an address decoder which decoded
microprocessor read/write cycles and produced appropri-
ately retimed signals for all the parts on a board
including
itself
, thereby removing the need for address decoding
PAL’s or discrete logic.
Each IOB has an array data input and a control data input,
labelled ArrayDToPad and ControlDToPad in Figure 15.
Associated with these inputs are two enable signals - Arr ay-
Enable and ControlEnable. These signals control whether
the pad associated with this IOB is in the input or output
mode. Each IOB also supplies ArrayData and ControlData
when acting as an input.
The ‘Control’ signals are routed to the internal XC6200 con-
trol circuitry. If control signals are not required all the time
then these IOBs can be used to route other user signals
into the array. For example if only eight data bus bits were
continuously required, the remaining twenty-four IOBs
associated with the data bus could be used to route user
signals to/from the array. ControlEnable comes either from
the internal XC6200 control circuitry if there is a bidirec-
tional control signal or output signal on that IOB, or it is tied
inactive.
There are less real control signals than IOBs, hence the
three control signals on some IOBs are not connected to
the device control logic. These spare control signals are
used to route data to and from the padless IOBs mentioned
above. The control signals on the padless IOB are not
used. This is illustrated in Figure 16.
Figure 15: Input/Output Architecture
Slew
PIN
VDD
V
SS
ArrayEnable
ControlEnable
ArrayDToPad
ControlDToPad
DELAY
IOB
PDn
PUp
IO PAD
Signals From Array
Fastlane Data
Control Data
DFromPad
DToPad
Enable
L16 Output From Array
DelData
0
1
Neighbor Data
Array Data
Data
Figure 16: ‘Padless’ IOB Configuration
Control Data
ControlDToPad
ControlEnable
DFromPad
DToPad
Enable
IO PAD
Enable
DToPad
DFromPad
ArrayData
ArrayDToPad
ArrayEnable
ArrayData
ArrayDToPad
ArrayEnable ‘PADLESS’ IOB
NORMAL IOB
DFromPadB
DToPadB
EnToPadB
June 1, 1996 (Version 1.0) 4- 263
The ‘Control’ signals are also referred to as ‘B’ signals later
in this data sheet. ControlDToPad = DToPadB,
ControlEnable = EnToPadB and Control
Data = DFromPadB. Also the L16 output from the array,
which can be routed onto Control Data, is referred to as
DForPadB.
Three configuration RAM bits within each IOB control the
programmable aspects of its IO pad. These RAM bits have
no effect for padless IOBs. ‘PUp’ and ‘PDn’ enable the pull-
up and pull-down resistors. The resistors ma y be used to tie
floating logic inputs to a known value. ‘Slew’ slows the out-
put transition time to reduce supply noise and ground-
bounce. The default condition is pull-up off, pull-down off
and slew on.
The Array Enable, Array Data and Control Data multiplex-
ers are also controlled by configuration RAM bits. A fixed
delay may be optionally applied to Array Data inputs. This
allows the input data hold time specification to be remov ed.
The ArrayEnable and ArrayDToPad signals can be config-
ured to constant 0 or 1 values within the logic array. The
constant values are particularly useful for the enable signal
when the pin is to function as an input or output rather than
a bidirectional pin. Constant v alues on the data signal and a
computed value on the enable signal produce open drain
pull-up (DToPad=1) or pull-down (DToPad=0) pins.
During reset, all the output drivers are disabled and the
pull-up resistors are enabled. The pull-up and pull-down
RAM control bits have no effect. After a reset the output
drivers remain in this state. For the output drivers to be
enabled, the global OE signal m ust be asserted (low) and a
valid configuration must be present in the device ID regis-
ter . The ID register is usually the last thing to be written dur-
ing configuration and acts as a check that the prog ramming
interface is operating correctly. More details of this are
given in the ‘Programming’ section on page 268. The OE
signal provides a quick way of disabling all the output driv-
ers and may be activated at any time. Only when OE is
active and there is a valid ID pattern in the ID register, do
the pull-up and pull-down RAM control bits determine the
IO-pad resistor configuration.
I/O Routing
The array signals to and from the IOBs are generally just
the signals which would have passed between two cells in
the array. The ArrayDToPad signal in Figure 15 is actually
the neighbor output from the border cell associated with the
IOB. The Array Enable signal is the length-4 Fastlane out-
put from the same cell.
Figure 17: Array Data Sources In West IOBs
PW4In
WCIn
MWIn
PW16In ECLOut
WrEn
DataBit
DelData
‘0’ WCLIn
PW4In
WCIn
MWIn E16Out
RdEn
ControlDToPad
DelData
ECLOut
WCLIn
PW16In
WCIn
MWIn E4Out
ControlDToPad
Control Enable
DelData
ECLOut
PW4In EOut
DFromPad
XC6200 Field Programmable Gate Arrays
4- 264 June 1, 1996 (Version 1.0)
The Arra y Data m ultiplexer in Figure 15 is actually a collec-
tion of multiplexers that source the neighbor, length-4,
length-16 and chip-length wires into the array. South IOBs
(IOBs at the South edge of the array) also source the local
clock signals into the array. North IOBs source the local
clear signals. This is illustr ated for a West IOB in Figure 17.
These multiplexers also allow a number of other internal
control signals to be routed into the array: WrEn and RdEn
are signals which are active during state register accesses.
‘DataBit’ is the state register output value f or this row during
a state access. Details of the timing of these signals are
given in the “Parallel Programming Interface” on page 268.
Note that in order to provide a minimal delay signal path
into the core array, the neighbor data output from the IOB
cannot select the delayed version of DFromPad. Only the
un-delayed DFromPad and the Previous Length-4 Input
can be routed onto the neighbor data output. Therefore the
neighbor data output is unaffected by the value of the con-
figuration memory which controls the DelData multiplexer
in Figure 15.
The length-4 and length-16 routing multiple x ers at the arra y
border also expect some inputs which are not a v ailable . F or
example at the West edge , MEIn, ECIn, PE4In and PE16In
are non-existent. These inputs are tied to ground thereby
providing an abundant source of constant zeros and ones
at the array border. These can be used to provide constant
values to drive the Array Enable inputs to IOBs.
Figure 18: XC6216 Logic Symbol
OE
Reset
G1
G2
GClk
GClr
I/O
CS RdWr A(15:0) D(31:0)
FastMAP Interface
June 1, 1996 (Version 1.0) 4- 265
Designing with XC6200
The designing of XC6200 FPGAs into systems may be par-
titioned into three distinct activities: board design, logic
design, and software design.
Board Design with XC6200
An XC6200 part may be used on a board design as a
microprocessor peripheral par t, as an ASIC-type device or
as both. In the first instance the XC6200 part will hav e con-
ventional SRAM data, address and control signals . In other
cases, it ma y only require the user defined I/O signals of an
ASIC. Packaging information for the part is shown in
Table 6. The number of user I/O signals will depend on the
exact package used.
Several XC6200 devices may be tiled together on a board
to form a larger array. The regular array structure of
XC6200 devices makes this particularly easy.
The configuration RAM bits in the IOBs allow for a number
of different programmable options to make interfacing to
other ICs easier.
Logic Design with XC6200
This can be approached as an ASIC type design using the
function and routing architecture defined in the previous
sections. An example design flo w is illustrated in Figure 19.
The design may be carried out in a v ariety of different wa ys .
Hardware description languages such as VHDL may be
used with the synthesized design targeted to the XC6200
architecture. Alternatively, schematic capture, using the
extensive Xilinx Unified Librar y, with commonly used front
end design tools (e.g. ViewLogic PROcapture/ViewDraw)
may be used. These tools produce an EDIF netlist which is
subsequently passed to the underlying XC6200 place and
route software. This automatically maps the user’s design
to the XC6200 architecture in an efficient wa y and pro vides
individual node delays which can be passed back to the
high level simulation tools such as Viewlogic PROsim/
ViewSim f or accurate simulation. Simulation ma y be carried
out prior to placement to check the logical correctness of
the design using nominal delays. The place and route soft-
ware also has optimization capability to carry out tasks
such as redundant gate remov al. A binary configuration file
that can be written to the XC6200 device via the program-
ming interface is also produced automatically. The underly-
ing CAD software is highly integrated with the high level
CAD tools, providing user-friendly pull-down menus and
dialog boxes to carry out all tasks.
These methods allow designers with little or no knowledge
of the XC6200 architecture to quickly produce large and
complex designs. Some designers may wish to carry out
detailed hand placement and routing to produce ultra-opti-
mized v ery high-speed/small area sections in their designs.
Others may wish to generate large regular structures such
as systolic arrays or perform floor-planning for extra effi-
ciency. For these cases, a sophisticated physical editor is
available that allows designers to graphically modify the
Figure 19: XC6200 Logic Design Flow
EDIF Netlist
Front End Design Entry Automatic Mapping,
Place and Route Logic Simulation In-System V erification
Manual Place and Route
(optional)
Node Delays
Failed
Simulation
Binary
Config
File
D
CLK
CLR
XOR2 M2_1
Load
Data
En
FDC Out
ENTITY counter IS
PORT (data : IN std_ulogic;
out : OUT std_ulogic);......
en : IN std_ulogic;
........
ARCHITECTURE rtl OF counter IS......
D
CLK
CLR
XOR2 M2_1
Load
Data
En
FDC Out
Cell1 Cell2
Clk
Load
Data
En
Out
00010
10011
00011
10011
00100
XOR2 M2_1
FDC
using Physical Editor
Failed
Test
XC6200 Field Programmable Gate Arrays
4- 266 June 1, 1996 (Version 1.0)
automatic placement of gates/registers into cells and mod-
ify the routing as much as required. Alter natively this soft-
ware may simply be used to see how the automatic
placement and routing software has optimized a design. If a
modification is subsequently made, then only the modified
par t of the design needs to be re-laid out. This incremental
design process provides a very rapid change cycle during
debugging.
All the design tasks may be carried out on PC or Unix work-
station platforms.
As an example, the simple accumulator circuit of Figure 20
is mapped onto the XC6200 architecture. Figure 21 shows
the resulting layout as displa yed b y the Physical Editor run-
ning under Microsoft Windows in this case. The Physical
Editor tools are also available for Unix workstations. The
boundaries of basic cells within the array are denoted by
the squares, with larger rectangles representing the switch
units on 4 cell boundaries. The wiring resources used by
the design mapped onto the array are indicated by solid
black lines. When a cell function unit is used by the design
it is annotated with the instance names of the mapped
primitives. The primary inputs and outputs are not shown in
this example.
Figure 20: Accumulator Schematic
FDC1
XOR2
XOR1
MUX1
COUT
SUM
CLK CLR
CIN
IN
S0
O
D1
D0
M2_1
XOR2 XOR2
FDC
QD
CLR
C
Figure 21: Accumulator Physical Editor View
June 1, 1996 (Version 1.0) 4- 267
The inputs and outputs to the function unit are connected to
the edges of the cell box. The CAD plot shows all the rout-
ing resources available. To the left of each cell the six wires
running in a Southerly direction are: SCL, S16, Clr, S4,
Magic and S. The signal direction is indicated with arrow
heads. S, S4 and Clr are shown entering the cells on the
left edge of the cell boxes. The two outputs on the left edge
of the cell box are Magic and SOut. The inputs and outputs
on the remaining three cell box edges follow a similar pat-
tern. The Clk input on the right hand cell box edge is
denoted with a clock ‘<’ symbol.
The Physical Editor allows cells to be selected and moved.
The inter-cell routing rubber-bands and adapts automati-
cally to the new placement. The routing ma y also be man u-
ally modified if desired.
Software Design with XC6200
This is the design of a program f or the host processor which
interacts with a design running on the XC6200 FPGA. Here
various registers within the XC6200 design appear as loca-
tions within the processor’s memory map. In addition, the
configuration memory of the device appears within the
memory map and por tions of the device can be reconfig-
ured as required. Predefined device drivers and an efficient
run-time library are available to make optimal use of the
high speed reconfiguration capabilities with minimal devel-
opment time.
Register Access
The XC6200 architecture supports direct accesses from
the processor to nodes within the user’s circuit: the output
of any cell’ s function unit can be read and the flip-flop within
any cell can be written. During state reads a number of cell
outputs are routed onto the CPU data bus . The signal which
is actually read is the inverse of F in Figure 6 (= Q or D).
These accesses are carried out through the control store
interface and involve no additional wiring within the user’s
design. The CPU interface signals involved in addressing
the cell state can be routed into the configurable array so
that user circuits can detect that an access has been made
and take appropriate action: for example, calculate a new
value for an output register or process a value placed in an
input register.
In many applications this access to internal nodes will be
the main path through which data is transferred to the pro-
cessor and in some coprocessor type applications it may
be the only external I/O method: user programmable I/O
pads may not be required at all.
To allow high bandwidth transfers between the processor
and internal nodes it is necessar y to be able to transfer a
complete processor data word of up to 32 bits in one mem-
ory cycle. For this reason, access bits are mapped into a
separate region of the device address space from configu-
ration bits so that all the bits in a word contain access bits.
Figure 22 is a block diagram of the XC6216 part, showing
the row and column address decoders. Figure 23 shows
the mapping of this area of the address space: there are 64
I/O signals from each column of cells and a 6-bit column
address selects a particular column of cells to access. This
row and column addressing scheme puts a constraint on
the placement of registers within the user’s design that are
to be accessed word-wide: they must be on the same col-
umn of cells within the array.
Figure 22: XC6216 Block Diagram
Figure 23: Memory Mapped I/O
5757
64
64
64x64
Cell Array
64 I/O North
64 I/O South
Column Decode
Control Global
64
I/O
W
E
S
T
Row
D
e
c
o
d
e
64
I/O
E
A
S
T
I/O
SELECT
D(8,16 or 31:0)
Row
Column Address CA(5:0)
(0,0) (63,0)
(63,63)
(0,63)
(63:0)
XC6200 Field Programmable Gate Arrays
4- 268 June 1, 1996 (Version 1.0)
Map Register
The XC6200 architecture also provides a mechanism for
mapping the 64 possible cell outputs onto the 8,16 or 32-bit
external data bus , selecting only those cells that implement
bits of the register to be accessed. Without this unit the pro-
cessor would have to implement a complex sequence of
shift and mask operations to discard those bits correspond-
ing to cells not within the register , or the user w ould hav e to
constrain the layout so that the register bits were in adja-
cent cells. The mechanism pro vided tak es the form of a 64-
bit map register, one bit for each row I/O signal from the
array. This map register can be read and written through
the control store interface and is set up prior to state
accesses. A logic 0 in the map register indicates that the
cell in the corresponding row is part of the register to be
accessed. The unit maps rows from the cell array onto
external data lines starting with the least significant bit: thus
the first row with a 0 in the map register will connect to
external data bus bit 0, the second row with a 0 in the map
register to data bus bit 1 and so on.
This technique puts a further constraint on the user’s lay-
out: the cells implementing the bits of the register must be
ordered so that less significant bits occur below more sig-
nificant bits. However, there are no constraints about the
relative separ ations of the cells. In practice these tw o place-
ment constraints: cells occurring in the same column and in
order vertically are easy to meet in datapath type designs.
Normally, the map register will be set once to indicate the
placement of the user I/O register that will then be
accessed many times. Therefore the two write operations
required with a 32-bit bus to set up the map register repre-
sent a small overhead. In data path type designs where
several registers are required, for example two input oper-
and registers and a result register, it is easy to ensure that
the corresponding bits of the registers occur on the same
row b ut different columns of the arr ay so that the same map
register value can be used with different column addresses
to access the various registers.
If more ‘0’s exist in the map register than there are valid
data bus bits then a form of wildcarding occurs during
writes. The data bus bits are allocated to the rows of the
array with a ‘0’ in their map register bit. Once all of the data
bus bits have been allocated, Bit 0 of the data bus is allo-
cated to the next ro w whose map register bit is a ‘0’, Bit 1 of
the data bus to the next ro w and so on. This feature means
that an entire column of state registers can be written with a
single 8-bit write. For example, if the map register contains
all ‘0’s and the CPU writes FFh to a particular column. All
the state registers in that column will be written with a ‘1’.
The default state of the map register is all ‘0’s.
During reads, if there are more ‘0’ bits in the map register
than data bus bits, the first rows with ‘0’ bits are mapped
onto the bus.
If there are less ‘0’s in the map register than data bus bits,
the upper data bus bits , which are not mapped, will be read
as ‘1’s during CPU reads and ignored during CPU writes.
An example of map register operation is shown in
Figure 24. The position of the user-defined register within
the cell arra y is defined by the ‘0’ s in the 64-bit map register.
Similar registers could be defined for every column in the
array if desired.
There is a delay after a write to the map register before the
change takes effect. No state accesses should be carried
out during this time.
Mask Register
A mask unit controlled by a 32-bit register is placed
between the external data bus and the internal data con-
nections. When the external data bus is 8 or 16 bits wide
only the bottom 8 or 16 bits of this register are significant. A
logic ‘1’ in a bit of this register indicates that the corre-
sponding bit of the internal data bus is
not
relev ant. Bit loca-
tions corresponding to ‘1’s in the Mask Register will retain
their values when written. On a write operation the corre-
sponding bit line will not be enabled and the state informa-
tion for that bit will not be changed. When the device is
reset the Mask Register will contain all logic 0’s corre-
sponding to all data bus bits valid.
During CPU reads, valid register bits which are disab led will
be read as ‘0’. In valid bits (bits which do not ph ysically exist
for the register being read) may be read as ‘0’ or ‘1’.
The mask register does not affect state register accesses.
In this case the map register can be used to prev ent certain
bits being modified.
Programming
The binary data for configuring an XC6200 device, gener-
ated by CAD softw are from the te xtual description of a user
design, must be downloaded into the part itself. This may
be performed in several ways. Generally, the fastest and
most efficient way is by writing directly to the control store,
mapped into the address space of a host processor. If a
microprocessor or other parallel data source is not avail-
able, then the serial programming interface may be used.
Parallel Programming Interface
The XC6200 FPGA has a conventional programming inter-
face for static RAM, based on Chip Select (CS) and Read/
Write (RdWr) control signals. The CS signal can be used to
address a single par t within an array of devices and allows
data to be read or written. Timing for these signals is illus-
trated in Figures 28 and 29. These figures show that the
programming interface is synchronous. The GClk input is
used to sample all the interface signals. GClk is also used
when accessing user registers as illustrated in Figure 24.
This is an important point, as only registers clock ed directly
by GClk can be reliably read or written using this method.
June 1, 1996 (Version 1.0) 4- 269
Figure 29 shows two separ ate read cycles - a normal cycle
immediately followed by an extended cycle. In the normal
read cycle CS is sampled low on the first rising GClk edge
(t1) and high on the next (t2). The data bus is then driven
until the next rising GClk edge (t3). In cases where this is
not long enough, the read cycle can be extended by keep-
ing CS asserted be yond t2. This is equiv alent to adding wait
states. In this case the data bus is driven until CS is deas-
serted. CS should not be allowed to go high and low again.
This would cause another cycle to begin. CS is sampled on
ever y rising GClk edge. Other CPU interface signals such
as RdWr and the Address Bus are only sampled on the first
GClk edge of the cycle (t1 for the first cycle and t3 for the
second in the figure examples).
Extended write cycles are also possible, ho we v er these are
functionally no different to normal write cycles, the data and
address busses still being sampled on the first rising GClk
edge of the cycle (t3 in Figure 28).
CS must always be sampled as a ‘1’ before the next cycle
can begin. In Figure 29 the extended read cycle starts
immediately after the normal read cycle at time t3. A write
cycle could not star t until the
next
rising GClk edge as the
data from the read cycle is still on the data bus.
The SRAM programming interface is supplemented by
additional hardware resources designed to minimize the
number of processor cycles required for reconfiguration.
Figure 24: Internal Register Access
Data
Bus
Map Register
8-Bit Data Bus Example
Bit 0
Cell Array
User-defined register within array
Cells
Address
Decode
Address
Bus
CPU
Interface
RdWr
CS
Write Enable
XC6200 Boundary
Bit 3
Bit 5
Bit 6
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Bit 1
Bit 2
Bit 4
Bit 7
XC6200 Field Programmable Gate Arrays
4- 270 June 1, 1996 (Version 1.0)
These resources are initially inactive after a reset so the
device looks like an SRAM.
The control store layout is designed to minimize the over-
head of computations required for dynamic access while
maintaining adequate density to minimize the e xternal stor-
age required for device configurations. When an external
processor is used to configure the device it may be conve-
nient to use a compressed format of the configuration inf or-
mation.
A feature of the XC6200 architecture is that a rectangular
area of cells specified as a hierarchical bloc k within a user’ s
design corresponds directly with a rectangular area within
the configuration memory of the XC6200 device. This
means that a block within the user’s design can be dynam-
ically replaced with another block by the host processor,
reconfiguring only the corresponding area of the control
store. The binary data for both bloc ks can be pre-calculated
from the cellular design and the actual replacement can be
carried out very rapidly using a block transfer operation.
The format of the address bus to the XC6216 device is
shown in Table 3. Larger XC6200 devices have proportion-
ally more bits allocated to row and column addresses.
All the configuration memory can be accessed as 8-bit
bytes. When a 16-bit transfer occurs Address<0> is irrele-
vant. When a 32-bit transfer occurs Address<1:0> is irrele-
vant. Data Bus bits <7:0> are written to the address with
Address<1:0>=00, bits <15:8> are written to the address
with Address<1:0> = 01, etc. The Address Mode bits are
used to determine which area of the control store is to be
accessed according to Table 4.
Wildcard Registers
The wildcard register allows many cell configuration mem-
ories within the same column of cells to be written simulta-
neously with the same data. This is used during device
testing to allow regular patterns to be loaded efficiently into
the control memory but is more generally useful, especially
with regular bit sliced designs, since it allows many cells to
be changed simultaneously. For example, a 16-bit 2:1 mul-
tiplexer could be built using cell routing multiplexers and
switched between sources using a single control store
access.
Similarly, the column address decoder has a wildcard reg-
ister which allows several cells on the same row to be writ-
ten with the same configuration. The column address
decoder drives the word lines to enable par ticular columns
of RAM cells. In this case the number of columns which can
be written simultaneously is limited to 32: that is at most five
don’t care bits can be set.
The row and column wildcard registers can be used simul-
taneously to rapidly configure regular structures onto the
device.
The address decoding for the XC6216 FPGA is summa-
rized in Table 5.
Table 3: Address Bus Format (XC6216)
Mode(1:0) Column(5:0) Column Offset<1:0> Row(5:0)
15:14 13:8 7:6 5:0
Table 4: Address Mode Selection
Mode1 Mode0 Area Selected
0 0 Cell Configuration and State
0 1 East/West Switch or IOB
1 0 North/South Switch or IOB
1 1 Device Control Registers
June 1, 1996 (Version 1.0) 4- 271
Serial Programming Interface
All the memory mapped locations in an XC6200 device
may be written in parallel or serial mode. All the operations
which can be carried out with the parallel interface ma y also
be done serially. The serial interface gives random access
to all the XC6200 memory locations. The ser ial interface is
designed to operate with any Xilinx serial PROM. A single
serial PROM may be used to configure several FPGAs. In
this case one of the FPGAs acts as a ‘Master’ and the oth-
ers as ‘Slaves’. The Master controls the serial PROM and
the Slaves. This is illustrated in Figure 25.
The serial PROM interf ace consists of 6 dedicated I/O pins:
Serial
Input that controls transitions between states
in serial mode state machine.
0 => serial mode, 1 => parallel mode
Wait
Input that controls transitions between states
in serial mode state machine.
0 => continue loading, 1 => pause until
Wait
deasserted
SEReset
Output from Master FPGA that resets serial
PROM address counter.
SECE
Output from Master FPGA that enables serial
PROM output.
SEClk
Output from Master FPGA that clocks serial
PROM and slave FPGAs.
SEData
is clocked
into the FPGAs on the rising edge of
SEClk
.
SEData
Serial data input to FPGA. This is sampled in
the FPGA by
SEClk
and retimed by the
FPGA's own GClk.
In a multi-FPGA configuration a user I/O also will ha ve to be
available to provide the Wait input to the next device in the
chain.
On Reset each FPGA examines its Serial
and W ait inputs.
Any FPGA that sees both these signals low at this time
assumes it is the master and drives SEReset, SECE and
SEClk. All User I/Os are held in a high-impedance state
(with pull-up) until a valid configuration is loaded. In
Figure 25, the User I/Os will be pulled high on Reset, hence
the W ait input to the Slav es will be high and the y will config-
ure as Slaves. A valid configuration is assumed when the
device ID register is loaded with the correct ID. Programma-
ble I/Os can only be enabled when this is present.
Serial data is loaded in address/data pairs. Once an
address/data pair has been shifted into the FPGA, the data
word is parallel written to the corresponding address inside
the FPGA just as though a parallel CPU write had occurred.
This means it is possible to do all the things which can be
accomplished with the parallel interface, e.g. use of the
mask register, writes to cell state registers, etc.
Table 5: XC6216 Memory Map
Address Bus Decode
A[15:14]
(Mode[1:0])
00 Cells
01 East/West Switch or IOB
10 North/South Switch or IOB
11 Control Registers
A[13:8]
(Column[5:0])
Cell Mode - Cell column
North/South Mode - Switch column
East/West Mode -
Column[5:2] = 4x4 block number
Column[1:0] decoded as:
00 West Switch
01 West IOB (Column[5:2]=0000)
10 East IOB (Column[5:2]=1111)
11 East Switch
A[7:6]
(Column
Offset[1:0])
Cell Mode
00 Neighbor Routing
01 Function Input Routing
10 Function
11 State Access (Cell Registers)
North/South Switch Mode
00 N/S Switch or N/S IOB Reg 0
01 N/S Switch or N/S IOB Reg 1
10 N/S Switch or N/S IOB Reg 2
11 N/S Secondary Clock Mux
(Column[1:0] = 00 or 11)
East/West Switch Mode
00 E/W Switch or E/W IOB Reg 0
01 E/W IOB Reg 1
A[5:0]
(Row[5:0])
Cell Mode - Cell row
East/West Mode - Switch row
North/South Mode -
Row[5:2] = 4x4 block number
Row[1:0] decoded as:
00 South Switch
01 South IOB (Row[5:2]=0000)
10 North IOB (Row[5:2]=1111)
11 North Switch
XC6200 Field Programmable Gate Arrays
4- 272 June 1, 1996 (Version 1.0)
The write operation is pipelined so there need be no inter-
ruption in the serial data stream. The first address/data pair
must be preceded by a Synchronization Byte = 1111_1110.
There are no start/stop bits, checksums or error chec k/cor-
rection bits.
The address and data are shifted in MSB first. The address
is alwa ys 16-bits. The data word is initially 8-bits b ut ma y be
increased to 16 or 32 bits by loading the device configura-
tion register with the appropriate code. The bits are shifted
in on the rising edge of SEClk. The SEClk rate may also be
increased by writing the appropriate code to the device
configuration register. Initially SEClk is 1/16 GClk fre-
quency. It can also be set to 1/8, 1/4 or 1/2 GClk.
An example is shown in Figure 25. Data1 is loaded into
Addr1 after the address lsb has been shifted in. In this
example the first write was to the device configuration reg-
ister and the data bus width w as changed from 8 to 32 bits .
Data word 2 starts immediately after Addr1 has been
shifted in. Due to the new data bus width, 32 data bits will
be shifted in. If the width had not been changed data word
2 would also have been 8 bits. Data will continue to be
loaded until Serial goes high or Wait goes low.
Reset And Initialization
When the XC6200 FPGA is powered up or after a reset, all
configuration memory is cleared and the cell state registers
are cleared. The Reset pin is not required to be active dur-
ing or after power-up to initializ e the FPGA. To avoid poten-
tial high current random configurations, the power-up reset
is carried out automatically. The automatic power-up initial-
ization takes 2.5 µs. All the XC6200 I/O pads are disabled
during this time and it is impossible to access the device.
The XC6200 may be re-initialized at any time by asserting
the Reset input for a minimum of 20 ns. This acts as a sig-
nal to the chip to initialize itself. This initialization occurs
after Reset has been deasser ted. Therefore there is a 1.0
µs (typ.) reset recovery time when no device accesses are
possible.
Figure 25: Master-Slave Serial Configuration
Serial
Wait
SEReset
SECE
SEClk
SEData
User I/O
MASTER FPGA
SERIAL
PROM
Serial
Wait
SEClk
SEData
User I/O
SLAVE FPGA 1
Serial
Wait
SEClk
SEData
SLAVE FPGA 2
etc...
Gnd
June 1, 1996 (Version 1.0) 4- 273
Pin Descriptions
The pins are labelled as follows:
VDD
Connections to the nominal +5V supply. All must be con-
nected.
GND
Connections to ground. All must be connected.
CS
Chip Select enables the progr amming circuitry and initiates
address decoding. When CS
is low, data can be read from
or written to the control memor y. This signal is intended to
be used in conjunction with address decoding circuitry to
select one part within a larger array for programming.
D<d:0>
(d+1)-bit bidirectional data bus. Used for device configura-
tion and direct cell register access.
A<a:0>
Address bus for CPU access of internal registers and con-
figuration memory. ‘a’ varies between family members.
RdWr
When CS
is low this signal determines whether data is read
from or written to the control memor y. If RdWr is high then
a read cycle takes place. If RdWr is low, then a wr ite cycle
takes place.
GClk, GClr, G1, G2
Global signals. GClk should be used for global user clocks,
GClr for global user clears and G1 and G2 for other global,
low-skew signals. The GClk pin is
always
configured as an
input and cannot be used as a fully fle xible User I/O lik e the
majority of other control signals.
Reset
When Reset is taken low the programming registers (mask
unit and address wildcard unit) are re-initialized, resulting in
the XC6200 device appearing as a conventional SRAM.
The control store of the cell array is initialized into a low
power consumption configur ation. All programmable output
pad enable signals are forced inactive. All the IO-pad pull-
up resistors are also enabled. This signal should be taken
low immediately after power up to initialize the device. This
pin is
always
configured as an input and cannot be used as
a fully flexible User I/O lik e the majority of other control sig-
nals.
OE
When this signal is low the outputs of all progr ammab le I/O
pads are forced into a high impedance state (independent
of the contents of the control store). All the IO-pad pull-up
resistors are also enabled. This pin is
always
configured as
an input and cannot be used as a fully fle xible User I/O lik e
the majority of other control signals.
Serial
Input which controls transitions between states in serial
mode state machine.
Wait
Input which controls transitions between states in serial
mode state machine.
0 => continue loading, 1 => pause until Wait deasserted
SEReset
Output from Master FPGA which resets serial PROM
address counter.
SECE
Output from Master FPGA which enables serial PROM out-
put.
SEClk
Output from Master FPGA which clocks serial PROM and
slave FPGAs.
SEData
Serial data input to FPGA. This is sampled in the FPGA by
SEClk and retimed by the FPGA's own GClk.
ConfigOK
Signal is active (high) when a valid pattern is present in the
ID register and inactive when the pattern is invalid.
Nx
North I/Os. Connections to I/O Blocks on the north of the
array.
Sx
South I/Os. Connections to I/O Blocks on the south of the
array.
Ex
East I/Os. Connections to I/O Blocks on the east of the
array.
Wx
West I/Os. Connections to I/O Blocks on the west of the
array
XC6200 Field Programmable Gate Arrays
4- 274 June 1, 1996 (Version 1.0)
Electrical Parameters
The XC6200 series is fabricated in 0.65 micron triple metal
n-well CMOS. Foundry sources for this part hav e been cho-
sen to meet or exceed relevant military standards and
industry practice.
As with all CMOS devices, care must be exercised when
handling this part as it can be damaged by static discharge ,
although standard circuit design procedures have been
adopted to minimize this risk.
The power consumption of a XC6200 device can vary from
a few tens to several hundreds of milliamps depending on
its configuration and the data applied to it. The most signif-
icant sources of power consumption are I/O blocks and
dynamic dissipation within the array, both of which are
largely under user control. Dynamic power dissipation is of
most concern where the XC6200 device is used to imple-
ment highly concurrent computations. Power dissipation
must be considered carefully, not only because excessive
dissipation could result in device failure but also because
operating speed is reduced at high temperature.
A 0.22µF decoupling capacitor across
V
CC
and
GND
per
part is recommended. Surface mounted, radial, plastic or
ceramic capacitors are suitable.
Where possible , user designs that could result in many out-
put pads making a simultaneous transition in the same
direction should be av oided. This is especially important on
heavily loaded connections to non-XC6200 parts. To mini-
mize power dissipation, redundant connections in user
designs (which may arise in hierarchical design styles to
promote sub-block re-use) should be deleted by CAD pro-
grams prior to programming XC6200 devices. As a general
guideline, users should attempt to minimize the number of
cell resources used. Where buffers must drive heavy exter-
nal loads it may be helpful to choose I/O blocks near
GND
pads.
XC6200 parts automatically reset themselves after power
up , since the random values in the control store at this time
could correspond to a relatively high po wer dissipation con-
figuration.
The XC6200 part distributes power using a redundant
scheme which ensures minimal voltage drop betw een pads
and internal circuitry. P ower f or pads is distributed on a sep-
arate power and ground ring.
The maximum pow er consumption of the XC6200 is limited
by two factors: the metal conductors supplying the part and
heat dissipation. The metal conductors can handle up to
100mA each. Heat dissipation is generally a much more
serious consideration: a full discussion of thermal charac-
teristics for the diff erent package options is giv en in section
4 of this data book.
June 1, 1996 (Version 1.0) 4- 275
XC6200 Switching Characteristics
Notice: The information contained in this data sheet per tains to products in the initial production phases of development.
These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest
sheet before finalizing a design.
XC6200 Operating Conditions
XC6200 DC Characteristics Over Operating Conditions
Notes: 1. Sample tested.
2. Measured with no output loads, no active input pull-up resistors and all package pins at VCC or GND.
XC6200 Absolute Maximum Ratings
Warning
:
Stresses beyond those listed under XC6200 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under XC6200 Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Symbol Parameter Min Max Units
VCC Supply voltage relative to GND Commercial TJ = 0o C to 85o C junction 4.75 5.25 V
Supply voltage relative to GND Industrial TJ = -40o C to 100o C junction 4.50 5.50 V
VILT Low-level input voltage – TTL configuration 0 0.80 V
VIHT High-level input voltage – TTL configuration 2.0 VCC V
VILC Low-level input voltage – CMOS configuration 0 20% V
VIHC High-level input voltage – CMOS configuration 70% 100% V
TIN Input signal transition time 250 ns
Symbol Parameter Test Conditions Min Max Units
VOH High-level output voltage IOH = -8.0 mA
VDD = Min 3.86 V
VOL Low-level output voltage IOL = 8mA
VDD = Min 0.4 V
IIL Input leakage current VDD = Max
VIN = GND or VCC 10 10 µA
IOZ Output high-Z leakage current VDD = Max
VO = GND or VCC TBA µA
CIN Input capacitance for Input and I/O pins VIN = GND
f = 1.0 MHz 15 pF
ICC2Quiescent Supply Current VIN = VCC or GND
VDD = 5 V
f = 1.0 MHz @ 25°CTBA mA
Symbol Parameter Value Units
VCC Supply voltage with respect to GND -0.5 to 7.0 V
VIN DC Input voltage with respect to GND -0.5 to VCC+0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC+0.5 V
TSTG Storage temperature -65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
XC6200 Field Programmable Gate Arrays
4- 276 June 1, 1996 (Version 1.0)
XC6200 Power-on/Reset Timing Parameters
XC6200 Serial Configuration Timing
XC6200 Global Buffer Switching Characteristic Guidelines
Note: Typical loading values are used.
XC6200 Cell Switching Characteristic Guidelines
Notes: 1.Data input measured at input to X1 routing multiplexer. Clock input measured at register.
2.Data input measured at input to X2/X3 routing multiplexers. Clock input measured at register.
3.Measured at the actual register in the cell.
4.Typical loading values are used.
Symbol Parameter Min Typ Max Units
TWMR Master Reset input Low pulse width 20 ns
TMRR Recovery time after Master Reset deasserted 1 µs
TPRR Recovery time after power up 2.5 µs
Advance
Description Symbol Min Max Units
SEClk SEData setup 1 TDC TBA - ns
SEData hold 2 TCD TBA - ns
Setup before GClk 3 TCG TBA - ns
Hold after GClk 4 TGC TBA - ns
Advance
Speed Grade: -2
Symbol Parameter Min Max Units
TPGClk From pad through GClk buffer to any register clock 12 ns
TPG From pad through G1,G2,GClr buffers to any register clock 12 ns
TPClr From pad through global buffers to any register clear 11 ns
TPCkS Skew between any pair of register clocks using the same global 0.9 ns
TPClS Skew between any pair of register clears using the same global 0.9 ns
Advance
Speed Grade: -2
Symbol Parameter Min Max Units
TILO1 X1 change to Function Output(1) 2ns
T
ILO23 X2/X3 change to Function Output(2) 3ns
T
ICK1 Internal Register Set-Up Time @ X1(1) 3.5 ns
TICK23 Internal Register Set-Up Time @ X2/X3(2) 4ns
T
IHCK1 Internal Register Hold Time @ X1(1) -1.5 ns
TIHCK23 Internal Register Hold Time @ X2/3(2) -2 ns
TCH Clock High Time(3) 4.5 ns
TCL Clock Low Time(3) 4.5 ns
fTOG Export Control Max. flip-flop toggle rate 111 MHz
TCLW Clear Pulse Width(3) 1ns
T
CKO Clock to Function Output 2 ns
TCKLO Clock to Function Output via X2/X3 feedback mux’s 3 ns
Advance
June 1, 1996 (Version 1.0) 4- 277
XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly and guaranteed over all the operating conditions. The same parameters can also
be derived indirectly from the IOB and Global Buffer specifications. The delay calculator software uses this indirect method.
When there is a discrepancy between these two methods, the directly tested values listed below should be used and the
derived values should be ignored.
Notes: All appropriate AC specifications tested using Figure 27 as test load circuit.
These parameters are tested directly and guaranteed over the operating conditions.
As the parameters vary between I/Os, values are given for best and worst I/Os. The parameters for other I/Os will be
somewhere between these two extremes. The delay calculator software will calculate the correct value for each I/O used.
All parameters assume the cell register is the closest one to the IOB.
XC6200 IOB Switching Characteristic Guidelines
Notes: As the parameters vary between I/Os, values are given for best and worst I/Os. The parameters for other I/Os will be
somewhere between these two extremes. The delay calculator software will calculate the correct value for each I/O used.
Typical loading values are used.
Speed Grade: -2
Symbol Parameter Best I/O Worst I/O UnitsMin Max Min Max
TICKOF Global Clock (GClk) to Output (fast) 19 ns
TICKO Global Clock (GClk) to Output (slew limited) 22.6 ns
TPSUF Input Set-up Time (fast) -4 ns
TPSU Input Set-up Time with delay 5 ns
TPHF Input Hold Time (fast) 6.5 ns
TPH Input Hold Time with delay -2.5 ns
Advance
Speed Grade: -2
Symbol Parameter Best I/O Worst I/O Units
Min Max Min Max
TPID
INPUT
Pad to Neighbor data 4 ns
TPID4 Pad to L4 Fastlane 5ns
T
PDID4 Pad to L4 Fastlane with delay 13 ns
TOPF
OUTPUT
Neighbor data to Output (fast) 4 ns
TOPS Neighbor data to Output (slew rate limited) 8 ns
TTSHZ 3-state to Pad begin hi-Z (slew rate independent) 5 ns
TTSONF 3-state to Pad active and valid (fast) 5.2 ns
TTSONS 3-state to Pad active and valid (slew rate limited) 9 ns
Advance
XC6200 Field Programmable Gate Arrays
4- 278 June 1, 1996 (Version 1.0)
XC6200 Internal Routing Delays
Notes: Delays vary depending on direction. Worst case figures are given here. The delay calculator software will calculate the correct
delay for each direction.
Typical loading values are used.
XC6200 CPU Interface Timing
Notes: 1. CS must be correctly sampled as a ‘0’ at the start of the cycle (t1) and sampled as a ‘1’ at the end of the cycle (t2). Other
signals only require to be correctly sampled at t1.
2. The minimum time f or a read or write cycle is two CPU clock periods, although the cycles sho wn do not start and finish at the
start of a clock period.
3. Data is remov ed from the bus TCKDZ after t3 unless CS is still asserted at this time. In this case, data is remo v ed from the bus
asynchronously TCSDZ after CS goes high.
Speed Grade: -2
Symbol Parameter Min Max Units
TFN Function Output to Neighbor 1 ns
TNN Route Neighbor In to Neighbor Out 1.5 ns
TMagic Route X2/X3 to Magic Out 2.5 ns
TL4 Length-4 Fastlane delay 2 ns
TL16 Length-16 Fastlane delay 2.5 ns
TL64 Chip-Length Fastlane delay 5 ns
Advance
Speed Grade: -2
Symbol Parameter Min Max Units
1T
suCS CS set up before Clock16ns
2T
hCS CS hold after Clock10ns
3T
suRdWr RdWr set up before Clock 6 ns
4T
hRdWr RdWr hold after Clock 0 ns
5T
suA Address Bus set up before Clock 6 ns
6T
hA Address Bus hold after Clock 0 ns
7T
suD Data Bus set up before Clock 6 ns
8T
hD Data Bus hold after Clock 0 ns
9T
WC Write cycle time240 ns
10 TRC Read cycle time240 ns
11 TCKD Clock to Valid Data 8 ns
12 TCKDZ Clock to Data high impedance39ns
13 TCSDZ CS to Data high impedance39ns
Advance
June 1, 1996 (Version 1.0) 4- 279
Figure 26: Serial Configuration Timing
Figure 27: AC Load Circuit
D7 D6 D5 D4 D3 D2
D1 D0 A15 A14 A13 A11 A10 A9 A8A12 A7 A6 A5 A4
A3 A2 A1
SEClk
SEData
Synchronization Byte
A0 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22
1st Data Word
1st Address Word
2nd Data Word
Write Data Word 1
tDC
1tCD
2
GClk tCG
3tGC
4
VTEST
R1
R2CL
Test PointDevice Output
Device Input
Rise and Fall
Times < 3ns
XC6200 Field Programmable Gate Arrays
4- 280 June 1, 1996 (Version 1.0)
Figure 28: Configuration Memory Write Cycles
GClk
CS
RdWr
A<a:0>
D<d:0>
tsuCS
1
thCS
2
tsuRdWr
3
thRdWr
4
tsuA
5
thA
6
tsuD
7
thD
8
t1t2t3
Write Cycle Extended Write Cycle
tWC
9
June 1, 1996 (Version 1.0) 4- 281
Figure 29: Configuration Memory Read Cycles
GClk
CS
RdWr
A<a:0>
D<d:0>
tsuCS
1
thCS
2
tsuRdWr
3
thRdWr
4
tsuA
5
thA
6
t1t2t3
Read Cycle Extended Read Cycle
tRC
tCKD
11 tCKDZ
12 tCSDZ
13
10
XC6200 Field Programmable Gate Arrays
4- 282 June 1, 1996 (Version 1.0)
XC6200 Pinout Tables
XC6216 Pinouts - West Side
Notes: 1. Pin not connected.
2. Pins with a dual function have the ‘Control’ signal shown first. See section “Input/Output Blocks (IOBs)” on page 261 for
details.
Pin Description PQ240 PG299 Pin Description PQ240 PG299
D0/W1(2) 60 C18 VCC 30 A11
GND 59 A19 GND 29 A10
W14 58 A20 D19/W39 28 C10
NC 57(1) C17(1) W40 - D10
D1/W356 D16 D9/W19 27 A9
W16 55 E15 D20/W41 26 E10
D2/W554 B18 W42 -B9
W
18 53 B17 D21/W43 25 C9
D3/W752 C16 D10/W21 24 A8
NC - - W44 -B8
NC - - W46 -D9
NC - D15(1) D22/W45 23 A7
NC - A18(1) GND 22 -
W20 51 E14 W48 21 E9
D4/W950 C15 W50 20 C8
W22 49 B16 VCC 19 A6
W24 48 D14 D24/W49 18 B7
W26 47 A17 D11/W23 17 C7
D5/W11 46 C14 D23/W47 16 D8
NC - E13(1) D25/W51 15 B6
NC - B15(1) GND 14 A5
GND 45 A15 W52 -B5
W
28 44 D13 W54 -E8
W
30 43 B14 W56 13 C6
W32 42 C13 D12/W25 12 D7
D6/W13 41 A14 W58 11 A4
VCC 40 A16 D26/W53 10 C5
D16/W33 39 B13 D27/W55 9B4
W
34 38 E12 D13/W27 8E7
GND 37 - W60 -D6
NC - D12(1) W62 -A3
NC - C12(1) NC - -
NC - A13(1) NC - -
NC - B12(1) D28/W57 7C4
D7/W15 36 A12 D14/W29 6D5
D17/W35 35 D11 D29/W59 5E6
W
36 34 E11 D15/W31 4B3
D18/W37 33 C11 D30/W61 3B2
D8/W17 32 B11 D31/W63 2D4
W
38 31 B10 GND 1 B1
June 1, 1996 (Version 1.0) 4- 283
XC6216 Pinouts - South Side
Note: 1. Pin not connected.
Pin Description PQ240 PG299 Pin Description PQ240 PG299
VCC 61 B20 GND 91 K20
RdWr/S162 D17 G1/S17 92 L19
CS/S363 B19 G2/S19 93 L18
W12/S064 C19 S42 94 L16
OE/S565 F16 S41 95 L17
W10/S266 E17 S44 - M20
Reset/S767 D18 S43 - M19
W8/S468 C20 S46 - N20
NC - - S48 - M18
NC - - E0/S50 96 M17
W6/S669 F17 E2/S52 97 M16
W4/S870 G16 GND 98 -
W2/S10 71 D19 E4/S54 99 N19
W0/S12 72 E18 S45 100 P20
S14 73 D20 VCC 101 T20
S16 74 G17 S21 102 N18
S18 - F18 SEData/S23 103 P19
S20 - H16 E6/S56 104 N17
S22 - E19 S47 105 R19
S24 - F19 GND 106 R20
GND 75 E20 NC - N161
S26 76 H17 NC - P181
S33 77 G18 E8/S58 107 U20
Serial/S978 G19 S49 108 P17
Wait/S11 79 H18 S51 109 T19
VCC 80 F20 S53 110 R18
S28 81 J16 S55 - P16
S35 82 G20 S57 - V20
GND 83 - E10/S60 111 R17
S30 - J17 E12/S62 112 T18
S32 - H19 NC - -
S34 - H20 NC - -
S36 - J18 SECE/S25 113 U19
GClk/S13 84 J19 SEReset/S27 114 V19
S38 85 K16 S59 115 R16
GClr/S15 86 J20 S61 116 T17
S37 87 K17 SEClk/S29 117 U18
S40 88 K18 ConfigOK/S31 118 X20
S39 89 K19 GND 119 W20
VCC 90 L20 S63 120 V18
XC6200 Field Programmable Gate Arrays
4- 284 June 1, 1996 (Version 1.0)
XC6216 Pinouts - East Side
Note: 1. Pin not connected.
Pin Description PQ240 PG299 Pin Description PQ240 PG299
VCC 121 X19 GND 151 X11
E14 122 U17 A8/E17 152 W10
A0/E1123 W19 E40 153 V10
E16 124 W18 A9/E19 154 T10
A1/E3125 T15 E41 155 U10
E18 126 U16 E42 156 X9
A2/E5127 V17 E43 157 W9
E20 128 X18 NC - X81
NC - U151E44 -V9
NC - T141E46 -U9
NC - - E48 -T9
NC - - GND 158 -
A3/E7129 W17 A10/E21 159 W8
E22 130 V16 E50 160 X7
E24 131 X17 VCC 161 X5
E26 132 U14 E45 162 V8
A4/E9133 V15 E52 163 W7
E28 134 T13 A11/E23 164 U8
NC - W161E47 165 W6
NC - W151GND 166 X6
GND 135 X16 E54 -T8
E
30 136 U13 E56 -V7
E
32 137 V14 E58 167 X4
A5/E11 138 W14 E49 168 U7
E33 139 V13 A12/E25 169 W5
VCC 140 X15 E51 170 V6
E34 141 T12 E53 171 T7
E35 142 X14 E55 172 X3
GND 143 - NC - -
NC - U12 NC - -
NC - W13 A13/E27 173 U6
NC - X13 E57 174 V5
NC - V12 E60 -W4
A6/E13 144 W12 E62 -W3
E
36 145 T11 A14/E29 175 T6
E37 146 X12 E59 176 U5
E38 147 U11 A15/E31 177 V4
A7/E15 148 V11 E61 178 X1
E39 149 W11 E63 179 V3
VCC 150 X10 VCC 180 W1
June 1, 1996 (Version 1.0) 4- 285
XC6216 Pinouts - North Side
Note: 1. Pin not connected.
Pin Description PQ240 PG299 Pin Description PQ240 PG299
VCC 240 A2 GND 211 L1
NC - - N15 210 L2
N1239 C3 N17 209 L3
N3238 D3 N19 208 L4
N0237 E4 N42 207 M1
N2236 F5 N41 206 L5
N4235 C2 N44 205 M2
N6234 D2 GND 204 -
N8-E3 N
43 203 M3
N10 -F4 N
21 202 N1
NC - - N46 -N2
NC - - N48 -M4
N
5233 C1 N50 -P1
N
7232 G5 N52 -M5
N
12 231 F3 VCC 201 R1
N14 230 E2 N23 200 N3
N16 229 G4 N54 199 P2
N18 228 D1 N45 198 P3
N20 -G3 N
56 197 N4
N22 - H5 GND 196 T1
GND 227 F1 NC - R21
N24 226 F2 N47 195 T2
N26 225 H4 N58 194 N5
N33 224 G2 N49 193 R3
N28 223 H3 N51 192 P4
VCC 222 E1 N53 191 U1
N30 -G1 N
55 190 T3
N32 -H2 N
57 189 U2
N34 -J5 N
60 -P5
N
36 -J4 N
62 -R4
N
35 221 J3 NC - -
N9220 H1 NC - -
GND 219 - N59 188 V1
N11 218 J2 N25 187 U3
N38 217 J1 N27 186 T4
N37 216 K4 N61 185 R5
N40 215 K5 N63 184 V2
N39 214 K3 N29 183 W2
N13 213 K2 GND 182 X2
VCC 212 K1 N31 181 U4
XC6200 Field Programmable Gate Arrays
4- 286 June 1, 1996 (Version 1.0)
Product Availability
Devices are available in small and large packages. The
small packages are useful where board area is at a pre-
mium and the design can make use of the wireless I/O par-
allel CPU interface to determine the state of internal nodes.
The large package options give a very high user program-
mable I/O count where this is a prime requirement. The
available packaging options for the XC6216 are summa-
rized in Table 6. (These options are advance information
and subject to change. Please confir m availability with Xil-
inx.
Signal pins are all the non-supply pins that drive into the
array or control circuitry. Some of these pins are shared
between control signals and user I/O. The un-shared user
I/Os do not share a pin with a control signal. The n umber of
user I/Os av ailab le will be some where between the n umber
of signal pins and the number of un-shared I/Os, depending
on how many of the FPGA control signals are actually
required. For example, if only an 8-bit data bus and no
serial interface were required, the number of user I/Os
would go up by 24+6=30 in a PGA299 package.
Table 6: XC6216 Package Options
Package Pins Signal Pins Max Data
Bus Pins Unshared
User I/O
PLCC 84 68 16 22
PQFP 240 199 32 137
PGA 299 242 32 180
4-287
XC3000 Series Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
XC3000 Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-290
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-291
Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-291
I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-292
Configurable Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-294
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-295
General Purpose Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-296
Direct Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-296
Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-300
Internal Busses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-302
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-303
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-304
Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-304
Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-306
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Daisy Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-307
Special Configuration Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-308
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-310
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-310
Master Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-312
Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-314
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-316
Program Readback Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-318
General XC3000 Series Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319
Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-320
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-321
Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-321
Dynamic Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-322
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-322
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
Permanently Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
User I/O Pins That Can Have Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-323
Unrestricted User I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-324
Pin Functions During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-325
XC3000 Series Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-326
XC3000 Series 44-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-327
XC3000 Series 64-Pin Plastic VQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-328
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . 4-329
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-330
XC3000 Series 100-Pin QFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-331
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-332
XC3000 Series 144-Pin Plastic TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-333
XC3000 Series 160-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-334
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-335
XC3000 Series 176-Pin TQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-336
XC3000 Series 208-Pin PQFP Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-337
XC3000 Series Table of Contents
XC3000 Series Table of Contents
4-288
XC3195A PQ208 and PG223 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-338
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-339
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-340
XC3000A Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
XC3000A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
XC3000A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
XC3000A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-342
XC3000A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-343
XC3000A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-343
XC3000A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-344
XC3000A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-346
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-348
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-348
XC3000L Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-349
XC3000L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-350
XC3000L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-351
XC3000L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-351
XC3000L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-352
XC3000L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-354
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-356
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-356
XC3100A Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-357
XC3100A Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358
XC3100A Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-359
XC3100A Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-359
XC3100A CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-360
XC3100A IOB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-362
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-364
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-364
XC3100L Field Programmable Gate Arrays
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-365
XC3100L Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-366
XC3100L Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
XC3100L Global Buffer Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
XC3100L CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-368
XC3100L IOB Switching Characteristics Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-370
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-372
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-372
June 1, 1996 (Version 2.0) 4-289
Features
• Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
package
- Avoids the NRE, time delay, and risk of conventional
masked gate arrays
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 9 to 1.5 ns
- System clock speeds over 80 MHz
- Low quiescent and active power consumption
• Flexible FPGA architecture
- Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive packaging options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
array packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
• Complete XACT
step
Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Description
XC3000-Series Field Programmable Gate Arrays (FPGAs)
provide a group of high-performance, high-density, digital
integrated circuits. Their regular, extendable, flexible, user-
programmab le arra y architecture is composed of a configu-
ration program store plus three types of configurable ele-
ments: a perimeter of I/O Blocks (IOBs), a core array of
Configurable Logic Bocks (CLBs) and resources for inter-
connection. The general structure of an FPGA is shown in
Figure 2. The XACT
step
development system provides
schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation
are availab le as design v erification alternatives. The design
editor is used for interactive design optimization, and to
compile the data pattern that represents the configuration
program.
The FPGA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial Configu-
ration PROMs provide a very simple serial configuration
program storage in a one-time programmable package.
The XC3000 Field Programmable Gate Array families pro-
vide a variety of logic capacities, package styles, tempera-
ture ranges and speed grades.
XC3000 Series
Field Programmable Gate Arrays
June 1, 1996 (Version 2.0) Product Description
Device Max Logic
Gates Typical Gate
Range CLBs Array User I/Os
Max Flip-Flops Horizontal
Longlines Configuration
Data Bits
XC3020A, 3020L, 3120A 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779
XC3030A, 3030L, 3130A 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176
XC3042A, 3042L, 3142A, 3142L 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784
XC3064A, 3064L, 3164A 4,500 3,500 - 4,500 224 16 x 14 120 688 32 46,064
XC3090A, 3090L, 3190A, 3190L 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160
XC3195A 7,500 6,500 - 7,500 484 22 x 22 176 1,320 44 94,984
XC3000 Series Field Programmable Gate Arrays
4-290 June 1, 1996 (Version 2.0)
XC3000 Series Overview
Introduced in 1987/88, the XC3000 series is the industr y’s
most successful family of FPGAs, with over 10 million
devices shipped. In 1992/93, Xilinx introduced three addi-
tional families , offering more speed, functionality, and a new
supply-voltage option.
There are now four distinct family groupings within the
XC3000 Series of FPGA devices, with emphasis on those
listed below:
• XC3000A Family
• XC3000L Family
• XC3100A Family
• XC3100L Family
All six families share a common architecture, development
software, design and programming methodology, and also
common package pin-outs. An extensive Product Descrip-
tion covers these common aspects.
The much shorter individual Product Specifications then
provide detailed parametric information for the XC3000A,
XC3000L, XC3100A, and XC3100L product families. (The
XC3000 and XC3100 families are not recommended for
new designs , and their individual product specifications are
not included in this book.)
Here is a simple overview of those XC3000 products cur-
rently emphasized:
•XC3000A Family — The XC3000A is an enhanced
version of the basic XC3000 family, featuring additional
interconnect resources and other user-friendly
enhancements. The ease-of-use of the XC3000A f amily
makes it the obvious choice for all new designs that do
not require the speed of the XC3100A or the 3-V
operation of the XC3000L.
•XC3000L Family — The XC3000L is identical in
architecture and features to the XC3000A family, but
operates at a nominal supply voltage of 3.3 V. The
XC3000L is the right solution for battery-operated and
low-power applications.
•XC3100A Family — The XC3100A is a performance-
optimized relative of the XC3000A family. While both
families are bitstream and footprint compatible, the
XC3100A family extends toggle rates to 370 MHz and
in-system performance to over 80 MHz. The XC3100A
family also offers one additional array size, the
XC3195A. The XC3100A is best suited for designs that
require the highest clock speed or the shortest net
delays.
•XC3100L Family — The XC3100L is identical in
architectures and features to the XC3100A family, but
operates at a nominal supply voltage of 3.3V.
Figure 1 illustrates the relationships between the families.
Compared to the original XC3000 family, XC3000A offers
additional functionality and, coming soon, increased speed.
The XC3000L family offers the same additional functional-
ity, but reduced speed due to its lower supply voltage of
3.3 V. The XC3100A family offers substantially higher
speed and higher density with the XC3195A.
XC3100 XC3100A
(XC3195A)
Gate Capacity
X7068
Functionality
XC3000L XC3000A
XC3100L
Speed
Figure 1: XC3000 FPGA Families
June 1, 1996 (Version 2.0) 4-291
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Con-
figurable Logic Bloc ks (CLBs) perf orms user-specified logic
functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks, analo-
gous to printed circuit board traces connecting MSI/SSI
packages.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by pro-
gram-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configur ation program is
loaded into the device at po wer-up and ma y be reloaded on
command. The FPGA includes logic and control signals to
implement automatic or passive configuration. Program
data may be either bit serial or b yte parallel. The XACT
step
development system generates the configuration program
bitstream used to configure the device. The memory load-
ing process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory
in the Field Programmable Gate Array has been designed
specifically for high reliability and noise immunity. Integrity
of the device configur ation memory based on this design is
assured even under adverse conditions. As shown in
Figure 3, the basic memory cell consists of two CMOS
inv erters plus a pass transistor used for writing and reading
cell data. The cell is only written during configuration and
only read during readback. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
P9 P8 P7 P6 P5 P4 P3 P2 GNDPWR
DN
P11
P12
P13
U61
TCL
KIN
ADACABAA
3-State Buffers With Access
to Horizontal Long Lines Configurable Logic
Blocks
Interconnect Area
BBBA
Frame Pointer
Configuration Memory
I/O Blocks
X3241
Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
XC3000 Series Field Programmable Gate Arrays
4-292 June 1, 1996 (Version 2.0)
The memory cell outputs Q and Q use ground and VCC le v-
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors hav e been observ ed ev en in the pres-
ence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the XACT
step
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide pro-
gramming compatibility for mixes of various FPGA device
devices in a synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB sho wn in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
Q
Data
Read or
Write
Configuration
Control
Q
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
FLIP
FLOP
QD
R
SLEW
RATE PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
DQ
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IKOK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each cloc k line (not each flip-flop or latch) is prog r ammable. A
clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
June 1, 1996 (Version 2.0) 4-293
The input-buffer portion of each IOB provides threshold
detection to translate external signals applied to the pack-
age pin to internal logic levels. The global input-buffer
threshold of the IOBs can be programmed to be compatib le
with either TTL or CMOS levels. The buffered input signal
drives the data input of a storage element, which may be
configured as either a flip-flop or a latch. The cloc king polar-
ity (rising/falling edge-triggered flip-flop , High/Low transpar-
ent latch) is programmable for each of the two clock lines
on each of the four die edges. Note that a clock line driving
a
rising
edge-triggered flip-flop makes any latch driven by
the same line on the same edge Low-lev el transparent and
vice versa (
falling
edge,
High
transparent). All Xilinx primi-
tives in the supported schematic-entry packages, however,
are positive edge-triggered flip-flops or High transparent
latches. When one clock line must driv e flip-flops as well as
latches, it is necessary to compensate for the difference in
clocking polarities with an additional inverter either in the
flip-flop clock input or the latch-enable input. I/O storage
elements are reset during configuration or by the active-
Low chip RESET input. Both direct input (from IOB pin I)
and registered input (from IOB pin Q) signals are available
for interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user IOB includes a
programmable high-impedance pull-up resistor, which may
be selected by the program to provide a constant High for
otherwise undriven package pins. Although the Field Pro-
grammable Gate Array provides circuitry to provide input
protection for electrostatic discharge, normal CMOS han-
dling precautions should be observed.
Flip-flop loop delays for the IOB and logic-block flip-flops
are short, providing good performance under asynchro-
nous clock and data conditions . Short loop delays minimiz e
the probability of a metastable condition that can result
from assertion of the clock during data transitions . Because
of the shor t-loop-delay characteristic in the Field Program-
mable Gate Array, the IOB flip-flops can be used to syn-
chronize external signals applied to the device. Once
synchronized in the IOB , the signals can be used internally
without further consideration of their clock relative timing,
except as it applies to the internal logic and routing-path
delays.
IOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- com-
patible signal le v els (8 mA in the XC3100A f amily). The net-
work driving IOB pin O becomes the registered or direct
data source for the output buffer. The 3-state control signal
(IOB) pin T can control output activity. An open-drain output
may be obtained by using the same signal for driving the
output and 3-state signal nets so that the buffer output is
enabled only for a Low.
Configuration program bits for each IOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control
the following options.
• Logic inversion of the output is controlled by one
configuration program bit per IOB.
• Logic 3-state control of each IOB output buffer is
determined by the states of configuration program bits
that turn the buffer on, or off, or select the output buffer
3-state control interconnection (IOB pin T). When this
IOB output control signal is High, a logic one, the b uffer
is disabled and the package pin is high impedance.
When this IOB output control signal is Low, a logic zero ,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense
(output enable) is controlled by an additional
configuration program bit.
• Direct or registered output is selectable for each IOB.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs
and minimize system noise.
• An internal high-impedance pull-up resistor (active by
default) prevents unconnected inputs from floating.
Summary of I/O Options
• Inputs
- Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip inputs)
- Pull-up resistor/open circuit
• Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)
XC3000 Series Field Programmable Gate Arrays
4-294 June 1, 1996 (Version 2.0)
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The XA CT
step
dev elopment system is
used to compile the configuration data which is to be
loaded into the internal configuration memory to define the
operation and interconnection of each bloc k. User definition
of CLBs and their interconnecting networks may be done
by automatic translation from a schematic-capture logic
diagram or optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the asyn-
chronous RD which, when enabled and High, is dominant
ov er clock ed inputs. All flip-flops are reset b y the active-Lo w
chip input, RESET, or during the configuration process. The
flip-flops share the enable clock (EC) which, when Low,
recirculates the flip-flops’ present states and inhibits
response to the data-in or combinatorial function inputs on
a CLB. The user ma y enable these control inputs and select
their sources. The user may also select the clock net input
(K), as well as its active sense within each CLB. This pro-
grammable inversion eliminates the need to route both
phases of a clock signal throughout the device. Flexible
routing allows use of common or individual CLB clocking.
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
F
G
QX
QY
DIN
F
G
G
QY
QX
F
QD
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN 0
1
0
1
MUX
MUX
Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
- five logic variable inputs A, B, C, D, and E
- a direct data in DI
- an enable clock EC
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and Y
June 1, 1996 (Version 2.0) 4-295
The combinatorial-logic por tion of the CLB uses a 32 by 1
look-up table to implement Boolean functions. Variables
selected from the five logic inputs and two internal block
flip-flops are used as table address inputs. The combinato-
rial propagation delay through the network is independent
of the logic function generated and is spike free for single
input variable changes. This technique can generate two
independent logic functions of up to four var iables each as
shown in Figure 6a, or a single function of five variables as
shown in Figure 6b , or some functions of sev en variab les as
shown in Figure 6c. Figure 7 shows a modulo-8 binary
counter with parallel enable. It uses one CLB of each type.
The partial functions of six or seven variables are imple-
mented using the input variable (E) to dynamically select
between two functions of four different variables. For the
two functions of four variables each, the independent
results (F and G) may be used as data inputs to either flip-
flop or either logic block output. For the single function of
five variables and merged functions of six or seven vari-
ables , the F and G outputs are identical. Symmetry of the F
and G functions and the flip-flops allows the interchange of
CLB outputs to optimize routing efficiencies of the networks
interconnecting the CLBs and IOBs.
Programmable Interconnect
Programmable-interconnection resources in the Field Pro-
grammable Gate Array provide routing paths to connect
inputs and outputs of the IOBs and CLBs into logic net-
works. Interconnections between bloc ks are composed of a
two-layer grid of metal segments. Specially designed pass
transistors, each controlled b y a configur ation bit, form pro-
grammable interconnect points (PIPs) and switching matri-
ces used to implement the necessary connections between
selected metal segments and block pins. Figure 8 is an
example of a routed net. The XACT
step
development sys-
tem provides automatic routing of these interconnections.
Interactiv e routing (Editnet) is also av ailab le f or design opti-
mization. The inputs of the CLBs or IOBs are multiplexers
which can be programmed to select an input network from
the adjacent interconnect segments.
Since the switch
connections to block inputs are unidirectional, as are
block outputs, they are usable only f or bloc k input con-
nection and not for routing.
Figure 9 illustrates routing
access to logic block input variables, control inputs and
block outputs. Three types of metal resources are provided
to accommodate various network interconnect require-
ments.
• General Purpose Interconnect
• Direct Connection
• Longlines (multiplexed busses and wide AND gates
QY Any Function
of Up to 4
Variables
QY Any Function
of Up to 4
Variables
QY Any Function
of 5 Variables
QY Any Function
of Up to 4
Variables
QY Any Function
of Up to 4
Variables
5c
5b
5a
QX
QX
QX
QX
QX
A
B
C
D
A
B
C
D
E
E
A
B
C
D
E
D
A
B
C
D
C
A
B
M
U
X
F
G
F
G
F
G
E
X5442
FGM
Mode
Figure 6: Combinational Logic Options
6a. Combinatorial Logic Option FG generates two func-
tions of four variables each. One variable, A, must be
common to both functions. The second and third v ariab le
can be any choice of B, C, QX and QY. The fourth vari-
able can be any choice of D or E.
6b. Combinatorial Logic Option F generates any function
of five variables: A, D, E and two choices out of B, C , QX,
QY.
6c. Combinatorial Logic Option FGM allows variable E to
select between two functions of four variables: Both have
common inputs A and D and any choice out of B, C, QX
and QY for the remaining two variables. Option 3 can
then implement some functions of six or seven variables.
XC3000 Series Field Programmable Gate Arrays
4-296 June 1, 1996 (Version 2.0)
General Purpose Interconnect
General purpose interconnect, as shown in Figure 10, con-
sists of a grid of five horizontal and five ver tical metal seg-
ments located between the rows and columns of logic and
IOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow progr ammed interconnections between the metal grid
segments of adjoining rows and columns. The switches of
an unprogrammed device are all non-conducting. The con-
nections through the switch matrix may be established by
the automatic routing or by using Editnet to select the
desired pairs of matrix pins to be connected or discon-
nected. The legitimate switching matrix combinations for
each pin are indicated in Figure 11 and ma y be highlighted
by the use of the Show-Matrix command in the XACT
Design Editor.
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices, above
and to the right and may be highlighted by the use of the
Show BIDI command in the XACT Design Editor. The other
PIPs adjacent to the matrices are accessed to or from Lon-
glines. The development system automatically defines the
buff er direction based on the location of the interconnection
network source. The delay calculator of the XACT
step
development system automatically calculates and displays
the block, interconnect and buffer delays for any paths
selected. Generation of the simulation netlist with a worst-
case delay model is provided by an XACT option.
Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct inter-
connect to drive the D input of the bloc k immediately abo v e
and the A input of the block below. Direct interconnect
should be used to maximize the speed of high-perf ormance
por tions of logic. Where logic blocks are adjacent to IOBs,
direct connect is provided alternately to the IOB inputs (I)
and outputs (O) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent IOBs. Direct interconnections of IOBs with CLBs
are shown in Figure 13.
D Q
D Q
D Q
Count Enable
Parallel Enable
Clock
D2
D1
D0
Dual Function of 4 Variables
Function of 6 Variables
Function of 5 Variables
Q2
Q1
Q0
FG
Mode
F
Mode
FGM
Mode
Terminal
Count
X5383
Figure 7: C8BCP Macro.
The C8BCP macro (modulo-8 binary counter with parallel
enable and clock enable) uses one combinatorial logic
block of each option.
Figure 8: An XACT Design Editor view of routing
resources used to form a typical interconnection
network from CLB GA.
June 1, 1996 (Version 2.0) 4-297
Figure 9: XACT Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot
pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT Design Editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP that drives from a horizontal to a vertical line.
D:V->H is a PIP that drives from a vertical to a horizontal line.
D:C->T is a “T” PIP that drives from a cross of a T to the tail.
D:CW is a corner PIP that drives in the clockwise direction.
P0 indicates the PIP is non-conducting, P1 is on.
XC3000 Series Field Programmable Gate Arrays
4-298 June 1, 1996 (Version 2.0)
Figure 10: FPGA General-Purpose Interconnect.
Composed of a grid of metal segments that may be inter-
connected through switch matrices to form networks for
CLB and IOB inputs and outputs.
1 2 3 4 5
6 7 8 9 10
11 12 13 14 15
16 17 18 19 20
383 16
Figure 11: Switch Matrix Inter connection Options f or
Each Pin.
Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT Design Editor.
Figure 12: CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact,
direct access to inputs of adjacent CLBs
June 1, 1996 (Version 2.0) 4-299
Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs.
Global Buffer Direct Input Global Buffer Inerconnect
Alternate Buffer Direct Input
* Unbonded IOBs (6 Places)
XC3000 Series Field Programmable Gate Arrays
4-300 June 1, 1996 (Version 2.0)
Longlines
The Longlines bypass the s witch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in Figure 14, run vertically and horizon-
tally the height or width of the interconnect area. Each inter-
connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A,
two v ertical Longlines in each column are connectab le half-
length lines. On the XC3020A, only the outer Longlines are
connectable half-length lines.
Longlines can be driven by a logic bloc k or IOB output on a
column-by-column basis. This capability provides a com-
mon low skew control or clock line within each column of
logic bloc ks. Interconnections of these Longlines are sho wn
in Figure 15. Isolation buffers are provided at each input to
a Longline and are enabled automatically by the develop-
ment system when a connection is made.
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
June 1, 1996 (Version 2.0) 4-301
Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-
state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-
clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
VCC
DADBDCDN
VCC Z = DA • DB • DC • ... • DN
X3036
(LOW)
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
DA
A
DB
B
DC
C
DN
N
DAA•+=D
B
B•+D
CC•+ D
NN•Z…+
X1741A
WEAK
KEEPER CIRCUIT
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
XC3000 Series Field Programmable Gate Arrays
4-302 June 1, 1996 (Version 2.0)
A buffer in the upper left corner of the FPGA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a skew-
free, high f an-out, synchronized cloc k for use at an y or all of
the IOBs and CLBs. Configuration bits for the K input to
each logic block can select this global line or another rout-
ing resource as the clock source for its flip-flops. This net
may also be programmed to drive the die edge clock lines
for IOB use. An enhanced speed, CMOS threshold, direct
access to this buff er is a v ailab le at the second pad from the
top of the left die edge.
A buffer in the lower right cor ner of the array drives a hori-
zontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer’s Longlines can be
selected to drive the K inputs of the CLBs. CMOS thresh-
old, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buff ers, located adjacent to each CLB , per-
mits logic to drive the horizontal Longlines. Logic operation
of the 3-state buff er controls allows them to implement wide
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by apply-
ing a Low logic level on its 3-state control line. See
Figure 16. The user is required to avoid contention which
can result from multiple drivers with opposing logic levels.
Control of the 3-state input by the same signal that drives
the buff er input, creates an open-dr ain wired-AND function.
A logic High on both buffer inputs creates a high imped-
ance, which represents no contention. A logic Low enables
the buffer to drive the Longline Low. See Figure 17. Pull-up
resistors are available at each end of the Longline to pro-
vide a High output when all connected buff ers are non-con-
ducting. This for ms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state bus-
ses). In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the previous logic level when the line is not
driven by an active buffer or a pull-up resistor. Figure 18
shows 3-state buffers, Longlines and pull-up resistors.
3-STATE CONTROL
GG
HG
P40 P41 P42 P43 RST
P46
.l
X1245
.q
.Q
OS
C
P47
BCL
KIN
P48
GH
HH
.lk
.ck
I/O CLOCKS
BIDIRECTIONAL
INTERCONNECT
BUFFERS
GLOBAL NET 3 VERTICAL LONG
LINES PER COLUMN
HORIZONTAL LONG LINE
PULL-UP RESISTOR
HORIZONTAL LONG LINE
OSCILLATOR
AMPLIFIER OUTPUT
DIRECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
BUFFER
3-STATE INPUT
3-STATE BUFFER
ALTERNATE BUFFER
D
P
G
M
Figure 18: XACT Design Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.
June 1, 1996 (Version 2.0) 4-303
Crystal Oscillator
Figure 18 also shows the location of an internal high speed
inverting amplifier that may be used to implement an on-
chip crystal oscillator. It is associated with the auxiliary
buffer in the lower right cor ner of the die. When the oscilla-
tor is configured by MakeBits and connected as a signal
source, two special user IOBs are also configured to con-
nect the oscillator amplifier with external crystal oscillator
components as shown in Figure 19. A divide by two option
is available to assure symmetry. The oscillator circuit
becomes active early in the configuration process to allow
the oscillator to stabilize. Actual internal connection is
delayed until completion of configuration. In Figure 19 the
feedback resistor R1, between the output and input, biases
the amplifier at threshold. The inversion of the amplifier,
together with the R-C networks and an AT-cut series reso-
nant crystal, produce the 360-degree phase shift of the
Pierce oscillator. A series resistor R2 may be included to
add to the amplifier output impedance when needed for
phase-shift control, crystal resistance matching, or to limit
the amplifier input swing to control clipping at large ampli-
tudes. Excess feedback voltage may be corrected by the
ratio of C2/C1. The amplifier is designed to be used from 1
MHz to about one-half the specified CLB toggle frequency.
Use at frequencies below 1 MHz may require individual
characterization with respect to a series resistance. Crystal
oscillators above 20 MHz generally require a crystal which
operates in a third overtone mode, where the fundamental
frequency must be suppressed by an inductor across C2,
turning this parallel resonant circuit to double the funda-
mental crystal frequency, i.e., 2/3 of the desired third har-
monic frequency network. When the oscillator inverter is
not used, these IOBs and their package pins are available
for general user I/O.
Alternate
Clock Buffer XTAL1
XTAL2
(IN)
R1
R2
Y1
C1 C2
Internal External
R1
R2
C1, C2
Y1
Suggested Component Values
0.5 – 1 MΩ
0 – 1 kΩ
(may be required for low frequency, phase
shift and/or compensation level for crystal Q)
10 – 40 pF
1 – 20 MHz AT-cut parallel resonant
X7064
68 PIN
PLCC
47
43
84 PIN
PLCC
57
53
PGA
J11
L11
132 PIN
PGA
P13
M13
160 PIN
PQFP
82
76
XTAL 1 (OUT)
XTAL 2 (IN)
100 PIN
CQFP
67
61
PQFP
82
76
164 PIN
CQFP
105
99
44 PIN
PLCC
30
26
175 PIN
PGA
T14
P15
208 PIN
PQFP
110
100
176 PIN
TQFP
91
85
D Q
Figure 19: Crystal Oscillator In verter. When activ ated in the Mak eBits progr am and b y selecting an output network f or
its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to implement an
oscillator. An optional divide-by-two mode is available to assure symmetry.
XC3000 Series Field Programmable Gate Arrays
4-304 June 1, 1996 (Version 2.0)
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When VCC reaches the voltage at which portions
of the FPGA device begin to oper ate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allo w the power sup-
ply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a self-
generated internal timer. This nominal 1-MHz timer is sub-
ject to variations with process, temper ature and pow er sup-
ply. As shown in Table 1, five configuration mode choices
are available as determined by the input levels of three
mode pins; M0, M1 and M2.
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning of
configuration of devices using Peripheral or Slave modes
must be delayed long enough for their initialization to be
completed. An FPGA with mode lines selecting a Master
configuration mode e xtends its initialization state using f our
times the delay (43 to 130 ms) to assure that all daisy-
chained slave devices, which it may be driving, will be
ready even if the master is ver y fast, and the slave(s) very
slow. Figure 20 shows the state sequences. At the end of
Initialization, the device enters the Clear state where it
clears the configuration memory. The active Low, open-
drain initialization signal INIT indicates when the Initializa-
tion and Clear states are complete. The FPGA tests for the
absence of an external active Low RESET before it makes
a final sample of the mode lines and enters the Configura-
tion state. An external wired-AND of one or more INIT pins
can be used to control configuration by the assertion of the
active-Low RESET of a master mode device or to signal a
processor that the FPGAs are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
A re-program is initiated.when a configured XC3000 series
device senses a High-to-Low transition and subsequent >6
µs Low le vel on the DONE/PR OG package pin, or , if this pin
is externally held permanently Low, a High-to-Low transi-
Table 1: Configuration Mode Choices
M0 M1 M2 CCLK Mode Data
0 0 0 output Master Bit Serial
0 0 1 output Master Byte Wide Addr. = 0000 up
0 1 0 — reserved —
0 1 1 output Master Byte Wide Addr. = FFFF down
1 0 0 — reserved —
1 0 1 output Peripheral Byte Wide
1 1 0 — reserved —
1 1 1 input Slave Bit Serial
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
Initialization
Power-On
Time Delay
Clear
Configuration
Memory
Test
Mode Pins Configuration
Program Mode Start-Up Operational
Mode
Power Down
No HDC, LDC
or Pull-Up
No
X3399
INIT Output = Low
Clear Is
~ 200 Cycles for the XC3020A—130 to 400 µs
~ 250 Cycles for the XC3030A—165 to 500 µs
~ 290 Cycles for the XC3042A—195 to 580 µs
~ 330 Cycles for the XC3064A—220 to 660 µs
~ 375 Cycles for the XC3090A—250 to 750 µs
RESET
Active
PWRDWN
Inactive PWRDWN
Active
Active RESET
Operates on
User Logic
Low on DONE/PROGRAM and RESET
Active RESET
Power-On Delay is
2
14
Cycles for Non-Master Mode—11 to 33 ms
2
16
Cycles for Master Mode—43 to 130 ms
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
June 1, 1996 (Version 2.0) 4-305
tion and subsequent >6 µs Low time on the RESET pack-
age pin.
The device returns to the Clear state where the configura-
tion memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration pro-
gram is cleared and loaded during each configuration pro-
gram cycle.
Length count control allows a system of multiple Field Pro-
grammable Gate Arrays, of assorted sizes, to begin opera-
tion in a synchronized fashion. The configuration program
generated by the MakePROM program of the
XACTstep
development system begins with a preamble of
111111110010 follo w ed by a 24-bit length count represent-
ing the total number of configuration cloc ks needed to com-
plete loading of the configuration program(s). The data
framing is shown in Figure 21. All FPGAs connected in
series read and shift preamble and length count in on pos-
itive and out on negative configuration clock edges. A
device which has received the preamble and length count
then presents a High Data Out until it has intercepted the
appropriate number of data frames. When the configuration
program memory of an FPGA is full and the length count
does not yet compare , the device shifts any additional data
through, as it did for preamble and length count. When the
F{GA configuration memory is full and the length count
11111111
0010
< 24-Bit Length Count >
1111
0 <Data Frame # 001 > 111
0 <Data Frame # 002 > 111
0 <Data Frame # 003 > 111
. . .
. . .
. . .
0 <Data Frame # 196 > 111
0 <Data Frame # 197 > 111
1111
—Dummy Bits*
—Preamble Code
—Configuration Program Length
—Dummy Bits (4 Bits Minimum)
For XC3120
197 Configuration Data Frames
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
Postamble Code (4 Bits Minimum)
Header
Program Data
Repeated for Each Logic
Cell Array in a Daisy Chain
*The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits X5300
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generated by the XACT
step
Development System.
The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain
device) rounded up to m ultiple of 8] – (2 ≤ K ≤ 4) where K is a function of DONE and RESET timing selected. An additional
8 is added if roundup increment is less than K. K additional clocks are needed to complete star t-up after length count is
reached.
Device
XC3020A
XC3020L
XC3120
XC3120A
XC3030A
XC3030L
XC3130A
XC3042A
XC3042L
XC3142A
XC3142L
XC3064A
XC3064L
XC3164A
XC3090A
XC3090L
XC3190A
XC3190L XC3195A
Gates 1,000 to 1,500 1,500 to 2,000 2,000 to 3,000 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500
CLBs 64 100 144 224 320 484
Row x Col (8 x 8) (10 x 10) (12 x 12) (16 x 14) (20 x 16) (22 x 22)
IOBs 64 80 96 120 144 176
Flip-flops 256 360 480 688 928 1,320
Horizontal Longlines 16 20 24 32 40 44
TBUFs/Horizontal LL 9 11 13 15 17 23
Bits per Frame
(including1 start and 3 stop bits) 75 92 108 140 172 188
Frames 197 241 285 329 373 505
Program Data =
Bits x Frames + 4 bits
(excludes header)
14,779 22,176 30,784 46,064 64,160 94,944
PROM size (bits) =
Program Data
+ 40-bit Header
14,819 22,216 30,824 46,104 64,200 94,984
XC3000 Series Field Programmable Gate Arrays
4-306 June 1, 1996 (Version 2.0)
compares, the device will execute a synchronous start-up
sequence and become operational. See Figure 22. Two
CCLK cycles after the completion of loading configuration
data, the user I/O pins are enabled as configured. As
selected in MakeBits, the internal user-logic RESET is
released either one clock cycle before or after the I/O pins
become active. A similar timing selection is programmable
for the DONE/PROG output signal. DONE/PROG may also
be programmed to be an open drain or include a pull-up
resistor to accommodate wired ANDing. The High During
Configuration (HDC) and Low During Configuration (LDC)
are two user I/O pins which are driven active while an
FPGA is in its Initialization, Clear or Configure states. They
and DONE/PROG provide signals for control of external
logic signals such as RESET, bus enable or PROM enable
during configuration. For parallel Master configuration
modes, these signals provide PROM enable control and
allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs have
TTL thresholds and can change to CMOS thresholds at the
completion of configuration if the user has selected CMOS
thresholds. The threshold of PWRDWN and the direct clock
inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
Configuration Data
Configuration data to define the function and interconnec-
tion within a Field Programmab le Gate Arra y is loaded from
an external storage at pow er-up and after a re-program sig-
nal. Se v eral methods of automatic and controlled loading of
the required data are available. Logic levels applied to
mode selection pins at the start of configuration time deter-
mine the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configu-
ration mode. The different FPGAs have different sizes and
numbers of data frames. To maintain compatibility between
various device types, the Xilinx product families use com-
patible configuration for mats. For the XC3020A, configura-
tion requires 14779 bits for each device, arranged in 197
data frames. An additional 40 bits are used in the header.
See Figure 22. The specific data format for each device is
produced by the MakeBits command of the development
system and one or more of these files can then be com-
bined and appended to a length count preamble and be
transformed into a PROM format file by the MakePROM
command of the
XACTstep
development system. A com-
patibility exception precludes the use of an XC2000-series
device as the master for XC3000-series devices if their
DONE or RESET are programmed to occur after their out-
puts become active. The Tie Option of the MakeBits pro-
gram defines output levels of unused blocks of a design
and connects these to unused routing resources. This pre-
vents indeterminate levels that might produce parasitic
Preamble Length Count Data
12 24 4 Data Frame
Start
Bit Start
Bit
34
Last Frame Postamble
I/O Active
DONE
Internal Reset
Length Count*
The configuration data consists of a composite
40-bit preamble/length count, followed by one or
more concatenated FPGA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur 
one cycle before or after the I/O outputs 
become active.
Heavy lines indicate the default condition X5988
PROGRAM
Weak Pull-Up
*
Stop
3
STOP
DIN
Figure 22: Configuration and Start-up of One or More FPGAs.
June 1, 1996 (Version 2.0) 4-307
supply currents. If unused blocks are not sufficient to com-
plete the tie, the Flagnet command of EditLCA can be used
to indicate nets which must not be used to drive the remain-
ing unused routing, as that might affect timing of user nets.
Norestore will retain the results of tie for timing analysis
with Querynet before Restore returns the design to the
untied condition. Tie can be omitted for quick breadboard
iterations where a few additional milliamps of Icc are
acceptable.
The configuration bitstream begins with eight High pream-
ble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the FPGA is set
to zero and begins to count the total number of configura-
tion clock cycles applied to the device. As each configura-
tion data frame is supplied to the device, it is internally
assembled into a data word, which is then loaded in par allel
into one word of the internal configuration memory array.
The configuration loading process is complete when the
current length count equals the loaded length count and the
required configuration program data fr ames have been writ-
ten. Internal user flip-flops are held Reset during configura-
tion.
Two user-programmable pins are defined in the unconfig-
ured Field Programmab le Gate Arra y. High During Configu-
ration (HDC) and Low During Configuration (LDC) as well
as DONE/PROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length count compares, the user I/O pins become
active. Options in the MakeBits program allow timing
choices of one clock earlier or later f or the timing of the end
of the internal logic RESET and the assertion of the DONE
signal. The open-drain DONE/PROG output can be AND-
tied with multiple devices and used as an active-High
READY, an active-Low PROM enable or a RESET to other
portions of the system. The state diagram of Figure 20 illus-
trates the configuration process.
Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configura-
tion data from an external memory device. There are three
Master modes that use the internal timing source to supply
the configuration clock (CCLK) to time the incoming data.
Master Serial mode uses serial configuration data supplied
to Data-in (DIN) from a synchronous serial source such as
the Xilinx Serial Configuration PROM shown in Figure 23.
Master Parallel Low and High modes automatically use
parallel data supplied to the D0–D7 pins in response to the
16-bit address generated by the FPGA. Figure 25 shows
an example of the parallel Master mode connections
required. The HEX starting address is 0000 and increments
for Master Low mode and it is FFFF and decrements for
Master High mode. These two modes provide address
compatibility with microprocessors which begin execution
from opposite ends of memory.
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 27 shows the peripheral mode connec-
tions. Processor write cycles are decoded from the com-
mon assertion of the activ e low Write Strobe (WS), and tw o
active low and one active high Chip Selects (CS0, CS1,
CS2). The FPGA generates a configuration clock from the
internal timing generator and serializes the parallel input
data for internal framing or for succeeding slaves on Data
Out (DOUT). A output High on READY/BUSY pin indicates
the completion of loading for each byte when the input reg-
ister is ready for a ne w b yte. As with Master modes, P eriph-
eral mode may also be used as a lead device for a daisy-
chain of slave devices.
Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Field Programmab le Gate Arra y configuration as shown
in Figure 29. Serial data is supplied in conjunction with a
synchronizing input clock. Most Slave mode applications
are in daisy-chain configurations in which the data input is
driven from the pre vious FPGA’ s data out, while the clock is
supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
Daisy Chain
The
XACTstep
development system is used to create a
composite configuration for selected FPGAs including: a
preamble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possi-
ble daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 25. Loading con-
tinues while the lead device has received its configuration
program and the current length count has not reached the
full value. The additional data is passed through the lead
device and appears on the Data Out (DOUT) pin in serial
form. The lead device also generates the Configuration
Clock (CCLK) to synchronize the serial output data and
data in of down-stream FPGAs. Data is read in on DIN of
slave devices by the positive edge of CCLK and shifted out
the DOUT on the negative edge of CCLK. A parallel Master
mode device uses its internal timing generator to produce
an internal CCLK of 8 times its EPROM address rate, while
a Peripheral mode device produces a burst of 8 CCLKs for
each chip select and write-strobe cycle. The internal timing
generator continues to operate for general timing and syn-
chronization of inputs in all modes.
XC3000 Series Field Programmable Gate Arrays
4-308 June 1, 1996 (Version 2.0)
Special Configuration Functions
The configuration data includes control ov er se ver al special
functions in addition to the normal user logic functions and
interconnect.
• Input thresholds
• Readback disable
• DONE pull-up resistor
• DONE timing
• RESET timing
• Oscillator frequency divided by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal
XACTstep
development system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all FPGA input
thresholds are TTL compatible. Upon completion of config-
uration, the input thresholds become either TTL or CMOS
compatible as programmed. The use of the TTL threshold
option requires some additional supply current for threshold
shifting. The exception is the threshold of the PWRDWN
input and direct clocks which always have a CMOS input.
Prior to the completion of configuration the user I/O pins
each hav e a high impedance pull-up . The configuration pro-
gram can be used to enab le the IOB pull-up resistors in the
Operational mode to act either as an input load or to avoid
a floating input on an otherwise unused pin.
Readback
The contents of a Field Programmable Gate Array may be
read back if it has been programmed with a bitstream in
which the Readback option has been enabled. Readback
may be used for verification of configuration and as a
method of determining the state of internal logic nodes dur-
ing debugging. There are three options in generating the
configuration bitstream.
• “Never” inhibits the Readback capability.
• “One-time,” inhibits Readback after one Readback has
been executed to verify the configuration.
• “On-command” allows unrestricted use of Readback.
Readback is accomplished without the use of any of the
user I/O pins; only M0, M1 and CCLK are used. The initia-
tion of Readback is produced b y a Lo w to High tr ansition of
the M0/RTRIG (Read Trigger) pin. The CCLK input must
then be driven by external logic to read back the configur a-
tion data. The first three Low-to-High CCLK transitions
clock out dummy data. The subsequent Low-to-High CCLK
transitions shift the data frame information out on the M1/
RDATA (Read Data) pin. Note that the logic polarity is
always inver ted, a zero in configuration becomes a one in
Readback, and vice versa. Note also that each Readback
frame has one Start bit (read back as a one) but, unlike in
configuration, each Readback frame has only one Stop bit
(read back as a zero). The third leading dummy bit men-
tioned above can be considered the Start bit of the first
frame. All data frames must be read back to complete the
process and return the Mode Select and CCLK pins to their
normal functions.
Readback data includes the current state of each CLB flip-
flop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the
XACTstep
development system In-Circuit Ver ifier to
provide visibility into the internal operation of the logic while
the system is operating. To readback a uniform time-sam-
ple of all storage elements, it may be necessar y to inhibit
the system clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered f or two
cycles of the FPGA internal timing generator. When repro-
gram begins , the user-progr ammable I/O output b uffers are
disabled and high-impedance pull-ups are provided for the
package pins. The device returns to the Clear state and
clears the configuration memory before it indicates ‘initial-
ized’. Since this Clear operation uses chip-individual inter-
nal timing, the master might complete the Clear operation
and then start configuration bef ore the slav e has completed
the Clear operation. To avoid this problem, the slave INIT
pins must be AND-wired and used to f orce a RESET on the
master (see Figure 25). Reprogram control is often imple-
mented using an external open-collector driver which pulls
DONE/PROG Low. Once a stable request is recognized,
the DONE/PROG pin is held Low until the new configura-
tion has been completed. Even if the re-program request is
externally held Low beyond the configuration period, the
FPGA will begin operation upon completion of configura-
tion.
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the
FPGA is in the operational state. An optional internal pull-
up resistor can be enabled by the user of the XACT devel-
opment system when MakeBits is executed. The DONE/
PROG pins of multiple FPGAs in a daisy-chain ma y be con-
nected together to indicate all are DONE or to direct them
all to reprogram.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MakeBits progr am to occur either a CCLK
cycle before, or after, the outputs going active. See
Figure 22. This facilitates control of external functions such
as a PROM enable or holding a system in a wait state.
June 1, 1996 (Version 2.0) 4-309
RESET Timing
As with DONE timing, the timing of the release of the inter-
nal reset can be controlled by a selection in the MakeBits
program to occur either a CCLK cycle before, or after, the
outputs going active. See Figure 22. This reset keeps all
user programmable flip-flops and latches in a zero state
during configuration.
Crystal Oscillator Division
A selection in the MakeBits program allows the user to
incorporate a dedicated divide-by-two flip-flop between the
crystal oscillator and the alter nate clock line. This guaran-
tees a symmetrical clock signal. Although the frequency
stability of a crystal oscillator is very good, the symmetry of
its waveform can be affected by bias or feedback drive.
Bitstream Error Checking
Bitstream error chec king protects against erroneous con-
figuration.
Each Xilinx FPGA bitstream consists of a 40-bit preamble,
followed by a device-specific number of data frames. The
number of bits per frame is also device-specific; however,
each frame ends with three stop bits (111) followed by a
start bit for the next frame (0).
All devices in all XC3000 families start reading in a new
frame when they find the first 0 after the end of the pre vious
frame. XC3000 device does not check for the correct stop
bits, but XC3000A/XC3100A/XC3000L and XC3100L
devices chec k that the last three bits of an y fr ame are actu-
ally 111.
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
XC3000 device will always star t a new frame as soon as it
finds the first 0 after the end of the previous frame, even if
the data is completely wrong or out-of-sync. Given suffi-
cient zeros in the data stream, the de vice will also go Done,
but with incorrect configuration and the possibility of inter-
nal contention.
An XC3000A/XC3100A/XC3000L/XC3100L device starts
any new frame only if the three preceding bits are all ones.
If this check fails, it pulls INIT Low and stops the internal
configuration, although the Master CCLK keeps running.
The user must then start a new configuration by applying a
>6 µs Low level on RESET.
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as bro-
ken lines or solder-bridges.
Reset Spike Protection
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the internal clock. It tolerates submicrosecond
High spikes on RESET before configuration. The XC3000
master can be connected like an XC4000 master, but with
its RESET input used instead of INIT. (On XC3000, INIT is
output only).
Soft Start-up
After configuration, the outputs of all FPGAs in a daisy-
chain become active simultaneously, as a result of the
same CCLK edge. In the original XC3000/3100 devices,
each output becomes active in either fast or slew-rate lim-
ited mode, depending on the way it is configured. This can
lead to large ground-bounce signals. In XC3000A/
XC3000L/XC31000A/XC3100L devices, all outputs
become active first in slew-rate limited mode, reducing the
ground bounce. After this soft start-up, each individual out-
put slew rate is again controlled by the respective configu-
ration bit.
XC3000 Series Field Programmable Gate Arrays
4-310 June 1, 1996 (Version 2.0)
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that ov erflo ws the lead de vice) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
X5989
CE
GENERAL-
PURPOSE
USER I/O
PINS
M0 M1 PWRDWN
DOUT
M2
HDC
OTHER
I/O PINS
RESET
DIN
CCLK
DATA
CLK
+5 V
•
•
•
•
•
OE/RESET
XC3000
FPGA
DEVICE
D/P
SCP
CEO
CASCADED
SERIAL
MEMORY
LDC
INIT
XC17xx
RESET
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
DURING CONFIGURATION
THE 5 kΩ M2 PULL-DOWN
RESISTOR OVERCOMES THE 
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
(LOW RESETS THE XC17xx ADDRESS POINTER)
TO CCLK OF OPTIONAL
VCC VPP
+5 V
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
IF READBACK IS
ACTIVATED, A 
5-kΩ RESISTOR IS 
REQUIRED IN
SERIES WITH M1
**
CE
DATA
CLK
OE/RESET
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
INIT
Figure 23: Master Serial Mode Circuit Diagram
June 1, 1996 (Version 2.0) 4-311
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-
monotonically rising VCC may require >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P after
VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.
Figure 24: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1TDSCK
2TCKDS
n n + 1 n + 2
n – 3 n – 2 n – 1 n
X3223
Description Symbol Min Max Units
CCLK Data In setup 1 TDSCK 60 ns
Data In hold 2 CKDS 0ns
XC3000 Series Field Programmable Gate Arrays
4-312 June 1, 1996 (Version 2.0)
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead de vice) on the DOUT pin. There is an internal
delay of 1.5 CCLK periods, after the rising CCLK edge that
accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
X5990
RCLK
General-
Purpose
User I/O
Pins
M0 M1PWRDWN
M2
HDC
Other
I/O Pins
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
.....
CE
OE
FPGA
CCLK
DOUT
System Reset
A11
A12
A13
A14
A15
EPROM
RESET
...
Other
I/O Pins
DOUT
M2
HDC
LDC
FPGA
Slave #1
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
FPGA
Slave #n
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
General-
Purpose
User I/O
Pins
RESET
Master
...
+5 V
8
INIT
...
M2
HDC
LDC
INIT
General-
Purpose
User I/O
Pins
+5 V
D/P
Other
I/O Pins
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
Open
Collector
INIT N.C.
Reprogram
5 kΩ5 kΩ5 kΩ
5 kΩ Each
If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series With M1
****
Figure 25: Master Parallel Mode Circuit Diagram
June 1, 1996 (Version 2.0) 4-313
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-
monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P after
VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2TDRC
Address for Byte n + 1
D7D6
A0-A15
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1TRAC
7 CCLKs CCLK
3TRCD
Byte n - 1 X5380
Description Symbol Min Max Units
RCLK
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
TRAC
TDRC
TRCD
TRCH
TRCL
0
60
0
600
4.0
200 ns
ns
ns
ns
µs
XC3000 Series Field Programmable Gate Arrays
4-314 June 1, 1996 (Version 2.0)
Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again
when the byte-wide input b uffer has transferred its inf orma-
tion into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
Note that after the last byte has been entered, only se ven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
X5991
ADDRESS
BUS DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC CS0
...
RDY/BUSY
WS
RESET
...
OTHER
I/O PINS
D0–7 CCLK
DOUT
M2
HDC
LDC
FPGA GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0 M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 kΩ
* IF READBACK IS
ACTIVATED, A 
5-kΩ RESISTOR IS 
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 27: Peripheral Mode Circuit Diagram
June 1, 1996 (Version 2.0) 4-315
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-
monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P after
VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. TBUSY indicates that the double-b uffered parallel-to-serial con v erter is not yet ready to receive ne w data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
Note:
This timing diagram sho ws very relaxed requirements: Data need not be held be yond the rising edge of WS. BUSY will
go active within 60 ns after the end of WS . BUSY will stay active f or se v eral microseconds. WS ma y be asserted immediately
after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
6
BUSY
T
D6DOUT
RDY/BUSY
D7 D0 D1 D2
4WTRB
T
Valid
2DC
T
1
CA
T
CCLK
D0-D7
CS2
WS, CS0, CS1
3
CD
T
WRITE TO FPGA
X5992
Previous Byte New Byte
Description Symbol Min Max Units
WRITE
Effective Write time required
(Assertion of CS0, CS1, CS2, WS) 1T
CA 100 ns
DIN Setup time required
DIN Hold time required 2
3TDC
TCD
60
0ns
ns
RDY/BUSY delay after end of WS 4T
WTRB 60 ns
RDY
Earliest next WS after end of BUSY 5T
RBWT 0ns
BUSY Low time generated 6 TBUSY 2.5 9 CCLK
periods
XC3000 Series Field Programmable Gate Arrays
4-316 June 1, 1996 (Version 2.0)
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be av ailab le at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead de vice
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
RESET
X5993
FPGA
General-
Purpose
User I/O
Pins
+5 V
M0 M1 PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
...
Other
I/O Pins
INIT
+5 V
5 kΩ
If Readback is
Activated, a 
5-kΩ Resistor is 
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with 
Different
Configurations
*
Figure 29: Slave Serial Mode Circuit Diagram
June 1, 1996 (Version 2.0) 4-317
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-
monotonically rising VCC may require a >6-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P after
VCC has reached 4.0 V (2.5 V for the XC3000L).
Figure 30: Slave Serial Mode Programming Switching Characteristics
4TCCH
Bit n Bit n + 1
Bit nBit n - 1
3TCCO
5TCCL
2TCCD
1TDCC
DIN
CCLK
DOUT
(Output)
X5379
Description Symbol Min Max Units
CCLK
To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
3
1
2
4
5
TCCO
TDCC
TCCD
TCCH
TCCL
FCC
60
0
0.05
0.05
100
5.0
10
ns
ns
ns
ns
µs
MHz
XC3000 Series Field Programmable Gate Arrays
4-318 June 1, 1996 (Version 2.0)
Program Readback Switching Characteristics
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins.
3. Readback should not be initiated until configuration is complete.
4. TCCLR is 5 µs min to 15 µs max for XC3000L.
1TRTH
5
3
4
4
2
TCCL
TCCRD
TCCL
TRTCC
DONE/PROG
(OUTPUT)
X6116
RTRIG (M0)
CCLK(1)
VALID
READBACK OUTPUT
HI-Z VALID
READBACK OUTPUT
M1 Input/
RDATA Output
Description Symbol Min Max Units
RTRIG RTRIG High 1 TRTH 250 ns
CCLK
RTRIG setup
RDATA delay
High time
Low time
2
3
4
5
TRTCC
TCCRD
TCCHR
TCCLR
200
0.5
0.5
100
5
ns
ns
µs
µs
June 1, 1996 (Version 2.0) 4-319
General XC3000 Series Switching Characteristics
Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a non-
monotonically rising VCC may require a >1-µs High level on RESET, followed by a >6-µs Low level on RESET and D/P after
Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while VCC >4.0 V(2.5 V for XC3000L).
4 TMRW
2 TMR 3 TRM
5 TPGW
6 TPGI
Clear State Configuration StateUser State
Note 3
VCCPD X5387
RESET
M0/M1/M2
DONE/PROG
INIT
(Output)
PWRDWN
VCC (Valid)
Description Symbol Min Max Units
RESET (2) M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
2
3
4
TMR
TRM
TMRW
1
4.5
6
µs
µs
µs
DONE/PROG Width (Low) required for Re-config.
INIT response after D/P is pulled Low 5
6TPGW
TPGI
67µs
µs
PWRDWN (3) Power Down VCC VCCPD 2.3 V
XC3000 Series Field Programmable Gate Arrays
4-320 June 1, 1996 (Version 2.0)
Device Performance
The XC3000 families of FPGAs can achieve very high per-
formance. This is the result of
• A sub-micron manufacturing process, developed and
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
• Careful optimization of transistor geometries, circuit
design, and lay-out, based on years of experience with
the XC3000 family.
• A look-up table based, coarse-grained architecture that
can collapse multiple-layer combinatorial logic into a
single function generator. One CLB can implement up
to four layers of conventional logic in as little as 1.5 ns.
Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial
and sequential logic elements within CLBs and IOBs, plus
the delay in the interconnect routing. The A C-timing specifi-
cations state the worst-case timing parameters for the vari-
ous logic resources available in the XC3000-families
architecture. Figure 31 shows a variety of elements
involved in determining system performance.
Logic block performance is expressed as the propagation
time from the interconnect point at the input to the block to
the output of the bloc k in the interconnect area. Since com-
binatorial logic is implemented with a memory lookup table
within a CLB, the combinatorial delay through the CLB,
called TILO, is always the same, regardless of the function
being implemented. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to
the flip-flop element. The delay from the clock source to the
output of the logic block is critical in the timing signals pro-
duced by storage elements. Loading of a logic-block output
is limited only by the resulting propagation delay of the
larger interconnect network. Speed performance of the
logic block is a function of supply voltage and temperature.
See Figure 32.
Interconnect performance depends on the routing
resources used to implement the signal path. Direct inter-
connects to the neighboring CLB provide an extremely fast
path. Local interconnects go through switch matrices
(magic boxes) and suffer an RC delay, equal to the resis-
tance of the pass transistor multiplied b y the capacitance of
the driven metal line. Longlines carry the signal across the
length or breadth of the chip with only one access delay.
Generous on-chip signal buffering makes performance rel-
atively insensitive to signal fan-out; increasing fan-out from
1 to 8 changes the CLB delay by only 10%. Clocks can be
distributed with two low-skew clock distribution networks.
The tools in the
XACTstep
Development System used to
place and route a design in an XC3000 FPGA automati-
cally calculate the actual maximum worst-case delays
along each signal path. This timing information can be
back-annotated to the design’s netlist for use in timing sim-
ulation or examined with X-Delay, a static timing analyzer.
Actual system performance is applications dependent. The
maximum clock rate that can be used in a system is deter-
mined by the critical path delays within that system. These
delays are combinations of incremental logic and routing
delays, and vary from design to design. In a synchronous
system, the maximum clock r ate depends on the number of
combinatorial logic layers between re-synchronizing flip-
flops. Figure 33 shows the achievable clock rate as a func-
tion of the number of CLB layers.
CLBCLB IOBCLB
PAD
(K)
LogicLogic
CKO
T
CLOCK
Clock to Output Combinatorial Setup
TCKO TILO TICK
(K)
PAD
IOB
TPID TOKPO
OP
T
X3178
Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing.
factors. Overall performance can be evaluated with the XDelay timing calculator or by an optional simulation.
June 1, 1996 (Version 2.0) 4-321
Power
Power Distribution
Po w er for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated VCC and ground ring sur-
rounding the logic array provides power to the I/O drivers.
An independent matrix of VCC and groundlines supplies the
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all inter nal logic, pro-
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-µF capacitor
connected near the VCC and ground pins will provide ade-
quate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
1.00
0.80
0.60
0.40
0.20
SPECIFIED WORST-CASE VALUES
MAX COMMERCIAL (4.75 V)
MAX MILITARY (4.5 V)
– 55
MIN MILITARY (5.5 V)
MIN COMMERCIAL (4.75 V)
MIN COMMERCIAL (5.25 V)
TYPICAL COMMERCIAL 
(+ 5.0 V, 25°C)
TYPICAL MILITARY
TEMPERATURE (°C)
– 40 – 20 0 25 40 70 80 100 125
NORMALIZED DELAY
X6094
MIN MILITARY (4.5 V)
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
System Clock (MHz)
250
200
150
100
50
3 CLBs
(3-12)
4 CLBs
(4-16) 2 CLBs
(2-8) 1 CLB
(1-4)
XC3100A-3
XC3000A--6
CLB Levels:
Gate Levels:
300
Toggle
Rate
0
X7065
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
XC3000 Series Field Programmable Gate Arrays
4-322 June 1, 1996 (Version 2.0)
Dynamic Power Consumption
Power Consumption
The Field Programmab le Gate Array exhibits the low po wer
consumption characteristic of CMOS ICs. For any design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configura-
tion data is very low and may be maintained in a power-
down mode.
Typically, most of power dissipation is produced by external
capacitive loads on the output buffers. This load and fre-
quency dependent power is 25 µW/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the FPGA is CMOS static
memory , its cells require a v ery low standby current f or data
retention. In some systems, this low data retention current
characteristic can be used as a method of preser ving con-
figurations in the event of a primary power loss. The FPGA
has built in po werdown logic which, when activ ated, will dis-
able normal operation of the de vice and retain only the con-
figuration data. All internal operation is suspended and
output buff ers are placed in their high-impedance state with
no pull-ups. Different from the XC3000 family which can be
powered down to a current consumption of a few micro-
amps, the XC3100A dra ws 5 mA, e ven in po wer-do wn. This
makes power-down operation less meaningful. In contrast,
ICCPD for the XC3000L is only 10 µA.
To force the FPGA into the Powerdo wn state, the user must
pull the PWRDWN pin Low and continue to supply a reten-
tion voltage to the VCC pins. When normal power is
restored, VCC is elevated to its normal operating voltage
and PWRDWN is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusion of configuration. Internal-I/O and logic-b lock
storage elements will be reset, the outputs will become
enabled and the DONE/PROG pin will be released.
When VCC is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input pro-
tection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and driv e
the VCC connection. This condition can produce invalid
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buff er
may be used to isolate the input signal.
XC3042A XC3042L XC3142A
One CLB driving three local interconnects 0.25 0.17 0.25 mW per MHz
One global clock buffer and clock line 2.25 1.40 1.70 mW per MHz
One device output with a 50 pF load 1.25 1.25 1.25 mW per MHz
June 1, 1996 (Version 2.0) 4-323
Pin Descriptions
Permanently Dedicated Pins
VCC
Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are inter-
preted as High, independent of their actual level. When
PWDWN returns High, the FPGA becomes operational with
DONE Low for two cycles of the internal 1-MHz clock.
Before and during configuration, PWRDWN must be High.
If not used, PWRDWN must be tied to VCC.
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process . An internal circuit senses
the application of power and begins a minimal time-out
cycle. When the time-out and RESET are complete, the le v-
els of the M lines are sampled and configuration begins.
If RESET is asserted during a configuration, the FPGA is
re-initialized and restarts the configuration at the termina-
tion of RESET.
If RESET is asserted after configuration is complete , it pro-
vides a global asynchronous RESET of all IOB and CLB
storage elements of the FPGA.
CCLK
During configuration, Configuration Clock is an output of an
FPGA in Master mode or Peripheral mode, but an input in
Slave mode. During Readback, CCLK is a clock input for
shifting configuration data out of the FPGA.
CCLK drives dynamic circuitry inside the FPGA. The Low
time may, theref ore, not e xceed a few microseconds. When
used as an input, CCLK must be “park ed High”. An internal
pull-up resistor maintains High when the pin is not being
driven.
DONE/PROG (D/P)
DONE is an open-drain output, configurab le with or without
an internal pull-up resistor of 2 to 8 k Ω. At the completion of
configuration, the FPGA circuitry becomes active in a syn-
chronous order; DONE is programmed to go active High
one cycle either before or after the outputs go active.
Once configuration is done, a High-to-Low transition of this
pin will cause an initialization of the FPGA and start a
reconfiguration.
M0/RTRIG
As Mode 0, this input is sampled on power-on to determine
the power-on dela y (214 cycles if M0 is High, 216 cycles if M0
is Low). Before the start of configuration, this input is again
sampled together with M1, M2 to determine the configura-
tion mode to be used.
A Low-to-High input transition, after configuration is com-
plete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when gener-
ating the bitstream, this operation ma y be limited to a single
Readback, or be inhibited altogether.
M1/RDATA
As Mode 1, this input and M0, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or VCC. If Readback is e ver used, M1 must use a
5-kΩ resistor to ground or VCC, to accommodate the
RDATA output.
As an active-Low Read Data, after configuration is com-
plete, this pin is the output of the Readback data.
User I/O Pins That Can Have Special
Functions
M2
During configuration, this input has a weak pull-up resistor.
Together with M0 and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.
HDC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After config-
uration, this pin is a user-programmable I/O pin.
LDC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin. LDC
is particularly useful in Master mode as a Low enable f or an
EPROM, but it must then be programmed as a High after
configuration.
INIT
This is an active Lo w open-drain output with a w eak pull-up
and is held Low during the power stabilization and internal
clearing of the configuration memory. It can be used to indi-
cate status to a configuring microprocessor or, as a wired
XC3000 Series Field Programmable Gate Arrays
4-324 June 1, 1996 (Version 2.0)
AND of several slave mode devices, a hold-off signal for a
master mode device . After configuration this pin becomes a
user-programmable I/O pin.
BCLKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTL1
This user I/O pin can be used to operate as the output of an
amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitr y. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.
CS0, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configu-
ration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the D0-
D7 data. In Master-Parallel mode, WS and CS2 are the A0
and A1 outputs. After configuration, these pins are user-
programmable I/O pins.
RDY/BUSY
During Peripheral Parallel mode configuration this pin indi-
cates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
RCLK
During Master Parallel mode configuration, each change
on the A0-15 outputs is preceded by a rising edge on
RCLK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed I/O pin.
D0-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed I/O
pins.
A0-A15
During Master Parallel mode, these 16 pins present an
address output for a configur ation EPROM. After configura-
tion, they are user-programmable I/O pins.
DIN
During Slave or Master Serial configuration, this pin is used
as a serial-data input. In the Master or Per ipheral configu-
ration, this is the Data 0 input. After configuration is com-
plete, this pin becomes a user-programmed I/O pin.
DOUT
During configuration this pin is used to output serial-config-
uration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-pro-
grammed I/O pin.
TCLKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to the
global clock net, and the global cloc k net should be used as
the primar y clock source, this pin is usually the clock input
to the chip.
Unrestricted User I/O Pins
I/O
An I/O pin may be programmed by the user to be an Input
or an Output pin follo wing configur ation. All unrestricted I/O
pins, plus the special pins mentioned on the f ollowing page ,
have a weak pull-up resistor of 50 kΩ to 100 kΩ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.
Note:
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50 k
Ω
to 100 k
Ω
pull-up resistor.
June 1, 1996 (Version 2.0) 4-325
Pin Functions During Configuration
Configuration Mode <M2:M1:M0> *** ***
SLAVE
SERIAL
<1:1:1>
MASTER-
SERIAL
<0:0:0> PERIPH
<1:0:1>
MASTER-
HIGH
<1:1:0>
MASTER-
LOW
<1:0:0> 44
PLCC 64
VQFP 68
PLCC 84
PLCC 84
PGA 100
PQFP
100
VQFP
TQFP 132
PGA 144
TQFP 160
PQFP 175
PGA 176
TQFP 208
PQFP 223
PGA User
Function
POWR
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I) 7 17 10 12 B2 29 26 A1 1 159 B2 1 3 B2
POWER
DWN
(1)
M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I) 16 31 25 31 J2 52 49 B13 36 40 B14 45 48 C16 RDATA
M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) Mo (LOW) (I) 17 32 26 32 L1 54 51 A14 38 42 B15 47 50 B17 RTRIG (I)
M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I) 18 33 27 33 K2 56 53 C13 40 44 C15 49 56 A17 I/O
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) 19 34 28 34 K3 57 54 B14 41 45 E14 50 57 A18 I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) 20 36 30 36 L3 59 56 D14 45 49 D16 54 61 E16 I/O
INIT* INIT* INIT* INIT* INIT* 22 40 34 42 K6 65 62 G14 65 59 H15 65 77 J16 I/O
GND GND GND GND GND 23 41 35 43 J6 66 63 H12 55 19 J14 67 79 K15 GND
26 47 43 53 L11 76 73 M13 69 76 P15 85 100 V18 XTL2 OR I/O
RESET (I) RESET (I) RESET (I) RESET (I) RESET (I) 27 48 44 54 K10 78 75 P14 71 78 R15 87 102 U17 RESET (I)
DONE DONE DONE DONE DONE 28 49 45 55 J10 80 77 N13 73 80 R14 89 107 V17 PROGRAM (I)
DATA 7 (I) DATA 7 (I) DATA 7 (I) 50 46 56 K11 81 78 M12 74 81 N13 90 109 T16 I/O
30 51 47 57 J11 82 79 P13 75 82 T14 91 110 U16 XTL1 OR I/O
DATA 6 (I) DATA 7 (I) DATA 6 (I) 52 48 58 H10 83 80 N11 78 86 P12 96 115 U15 I/O
DATA 6 (I) DATA 6 (I) DATA 6 (I) 53 49 60 F10 87 84 M9 84 92 T11 102 122 U12 I/O
CS0 (I) 54 50 61 G10 88 85 N9 85 93 R10 103 123 V11 I/O
DATA (4) DATA (4) DATA (4) 55 51 62 G11 89 86 N8 88 96 R9 108 128 U10 I/O
DATA (3) DATA (3) DATA (3) 57 53 65 F11 92 89 N7 92 102 P8 112 132 T9 I/O
CS1 (I) 58 54 66 E11 93 90 P6 93 103 R8 113 133 U9 I/O
DATA (2) DATA (2) DATA (2) 59 55 67 E10 94 91 M6 96 106 R7 118 138 V8 I/O
DATA (1) DATA (1) DATA (1) 60 56 70 D10 98 95 M5 102 114 R5 124 145 U5 I/O
RDY/BUSY RCLK RCLK 61 57 71 C11 99 96 N4 103 115 P5 125 146 U4 I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) 38 62 58 72 B11 100 97 N2 106 119 R3 130 151 U3 I/O
DOUT DOUT DOUT DOUT DOUT 39 63 59 73 C10 1 98 M3 107 120 N4 131 152 V2 I/O
CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (O) 40 64 60 74 A11 2 99 P1 108 121 R2 132 153 U2 CCLK (I)
WS (I) A0 A0 1 61 75 B10 5 2 M2 111 124 P2 135 161 T3 I/O
CS2 (I) A1 A1 2 62 76 B9 6 3 N1 112 125 M3 136 162 V1 I/O
A2 A2 3 63 77 A10 8 5 L2 115 128 P1 140 165 R2 I/O
A3 A3 4 64 78 A9 9 6 L1 116 129 N1 141 166 T1 I/O
A15 A15 65 81 B6 12 9 K1 119 132 M1 146 172 N2 5
A4 A4 5 66 82 B7 13 10 J2 120 133 L2 147 173 M4 I/O
A14 A14 6 67 83 A7 14 11 H1 123 136 K2 150 178 L4 I/O
A5 A5 7 68 84 C7 15 12 H2 124 137 K1 151 179 L2 I/O
A13 A13 9 2 2 A6 17 14 G2 128 141 H2 156 184 K3 I/O
A6 A6 10 3 3 A5 18 15 G1 129 142 H1 157 185 J1 I/O
A12 A12 11 4 4 B5 19 16 F2 133 147 F2 164 192 G1 I/O
A7 A7 12 5 5 C5 20 17 E1 134 148 E1 165 193 G4 I/O
A11 A11 13 6 6 A3 23 20 D1 137 151 D1 169 199 F4 I/O
A8 A8 14 7 9 A2 24 21 D2 138 152 C1 170 200 E2 I/O
A10 A10 15 8 10 B3 25 22 B1 141 155 E3 173 203 E3 I/O
A9 A9 16 9 11 A1 26 26 C2 142 156 C2 174 204 B1 I/O
All Others
X X X X XC3x20A etc.
X X X X X X X XC3x30A etc.
X X X X X X XC3x42A etc.
X** X X XC3x64A etc.
X** X X X X X XC3x90A etc.
Notes: X** X X X XC3195A
*
(I)
**
***
****
Note:
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see page 310 through page 319.
For pinout details, see page 327 through page 338.
Represents a 50-kΩ to 100-kΩ pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not indentical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 100-kW pull-up
resistor.
XC3000 Series Field Programmable Gate Arrays
4-326 June 1, 1996 (Version 2.0)
XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 fam-
ilies in a variety of surface-mount and through-hole pack-
age types, with pin counts from 44 to 223.
Each chip is offered in several package types to accommo-
date the av ailable PC board space and manuf acturing tech-
nology. Most package types are also offered with different
chips to accommodate design changes without the need for
PC board changes.
Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
package. In some cases, the chip has more pads than
there are pins on the package , as indicated b y the informa-
tion (“unused” pads) below the line in the following table.
The IOBs of the unconnected pads can still be used as
storage elements if the specified propagation delays and
set-up times are acceptable.
In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the follow-
ing table.
3020A
3030A
3042A
3064A
3090A
3195A
Device
74
98
118
142
166
198
Pads
—
54 u
—
—
—
—
44
—
34 u
—
—
—
—
64
6 u
30 u
—
—
—
—
68
10 n.c.
14 u
34 u
50 u
82 u
114 u
84
26 n.c.
2 n.c.
18 u
—
—
—
100
—
—
14 n.c.
10 u
—
—
132
—
—
26 n.c.
2 u
—
—
144
—
—
—
18 n.c.
6 u
—
160
—
—
—
—
9 n.c
175
—
—
—
—
10 n.c.
—
176
—
—
—
—
42 n.c.
10 n.c.
208
—
—
—
—
—
25 n.c.
223
9 n.c.
32 u
n.c. = Unconnected package pin
u = Unbonded device pad X7066
Number of Package Pins
Number of Unbounded or Unconnected Pins
Number of Available I/O Pins
64
Number of Package Pins
Max I/O 68
84
100
120
132
144
156
160
164
175
191
196
208
223
240
64
80
96
120
144
176
XC3020A/XC3120A
XC3030A/XC3130A
XC3042A/XC3142A
XC3064A/XC3164A
XC3090A/XC3190A
XC3195A
54 58
58
64
74
74
70
70
70
64
80
82
96
110
96
110
120
120
138
138
144
144
144
144
176
176
X7067
44
34
176
144
June 1, 1996 (Version 2.0) 4-327
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Peripheral mode and Master Parallel mode are not supported in the PC44 package
Pin No. XC3030A Pin No. XC3030A
1 GND 23 GND
2 I/O 24 I/O
3 I/O 25 I/O
4 I/O 26 XTL2(IN)-I/O
5 I/O 27 RESET
6 I/O 28 DONE-PGM
7 PWRDWN 29 I/O
8 TCLKIN-I/O 30 XTL1(OUT)-BCLK-I/O
9 I/O 31 I/O
10 I/O 32 I/O
11 I/O 33 I/O
12 VCC 34 VCC
13 I/O 35 I/O
14 I/O 36 I/O
15 I/O 37 I/O
16 M1-RDATA 38 DIN-I/O
17 M0-RTRIG 39 DOUT-I/O
18 M2-I/O 40 CCLK
19 HDC-I/O 41 I/O
20 LDC-I/O 42 I/O
21 I/O 43 I/O
22 INIT-I/O 44 I/O
XC3000 Series Field Programmable Gate Arrays
4-328 June 1, 1996 (Version 2.0)
XC3000 Series 64-Pin Plastic VQFP Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Pin No. XC3030A Pin No. XC3030A
1 A0-WS-I/O 33 M2-I/O
2 A1-CS2-I/O 34 HDC-I/O
3 A2-I/O 35 I/O
4 A3-I/O 36 LDC-I/O
5 A4-I/O 37 I/O
6 A14-I/O 38 I/O
7 A5-I/O 39 I/O
8GND 40 INIT-I/O
9 A13-I/O 41 GND
10 A6-I/O 42 I/O
11 A12-I/O 43 I/O
12 A7-I/O 44 I/O
13 A11-I/O 45 I/O
14 A8-I/O 46 I/O
15 A10-I/O 47 XTAL2(IN)-I/O
16 A9-I/O 48 RESET
17 PWRDN 49 DONE-PG
18 TCLKIN-I/O 50 D7-I/O
19 I/O 51 XTAL1(OUT)-BCLKIN-I/O
20 I/O 52 D6-I/O
21 I/O 53 D5-I/O
22 I/O 54 CS0-I/O
23 I/O 55 D4-I/O
24 VCC 56 VCC
25 I/O 57 D3-I/O
26 I/O 58 CS1-I/O
27 I/O 59 D2-I/O
28 I/O 60 D1-I/O
29 I/O 61 RDY/BUSY-RCLK-I/O
30 I/O 62 D0-DIN-I/O
31 M1-RDATA 63 DOUT-I/O
32 M0-RTRIG 64 CCLK
June 1, 1996 (Version 2.0) 4-329
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
This table describes the pinouts of three diff erent chips in three different pac kages. The pin-description column lists 84 of the
118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,
indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin
packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a
dash (—) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages.
68 PLCC XC3020A, XC3030A,
XC3042A 84 PLCC 84 PGA
68 PLCC
XC3030A
XC3020A XC3020A, XC3030A, XC3042A 84
PLCC 84 PGA XC3020AXC3030A XC3020A
10 10 PWRDN 12 B2 44 RESET 54 K10 44
11 11 TCLKIN-I/O 13 C2 45 DONE-PG 55 J10 45
12 — I/O* 14 B1 46 D7-I/O 56 K11 46
13 12 I/O 15 C1 47 XTL1(OUT)-BCLKIN-I/O 57 J11 47
14 13 I/O 16 D2 48 D6-I/O 58 H10 48
— — I/O 17 D1 — I/O 59 H11 —
15 14 I/O 18 E3 49 D5-I/O 60 F10 49
16 15 I/O 19 E2 50 CS0-I/O 61 G10 50
— 16 I/O 20 E1 51 D4-I/O 62 G11 51
17 17 I/O 21 F2 — I/O 63 G9 —
18 18 VCC 22 F3 52 VCC 64 F9 52
19 19 I/O 23 G3 53 D3-I/O 65 F11 53
— — I/O 24 G1 54 CS1-I/O 66 E11 54
20 20 I/O 25 G2 55 D2-I/O 67 E10 55
— 21 I/O 26 F1 — I/O 68 E9 —
21 22 I/O 27 H1 — I/O* 69 D11 —
22 — I/O 28 H2 56 D1-I/O 70 D10 56
23 23 I/O 29 J1 57 RDY/BUSY-RCLK-I/O 71 C11 57
24 24 I/O 30 K1 58 D0-DIN-I/O 72 B11 58
25 25 M1-RDATA 31 J2 59 DOUT-I/O 73 C10 59
26 26 M0-RTRIG 32 L1 60 CCLK 74 A11 60
27 27 M2-I/O 33 K2 61 A0-WS-I/O 75 B10 61
28 28 HDC-I/O 34 K3 62 A1-CS2-I/O 76 B9 62
29 29 I/O 35 L2 63 A2-I/O 77 A10 63
30 30 LDC-I/O 36 L3 64 A3-I/O 78 A9 64
— 31 I/O 37 K4 — I/O* 79 B8 —
— I/O* 38 L4 — I/O* 80 A8 —
31 32 I/O 39 J5 65 A15-I/O 81 B6 65
32 33 I/O 40 K5 66 A4-I/O 82 B7 66
33 — I/O* 41 L5 67 A14-I/O 83 A7 67
34 34 INIT-I/O 42 K6 68 A5-I/O 84 C7 68
35 35 GND 43 J6 1 GND 1 C6 1
36 36 I/O 44 J7 2 A13-I/O 2 A6 2
37 37 I/O 45 L7 3 A6-I/O 3 A5 3
38 38 I/O 46 K7 4 A12-I/O 4 B5 4
39 39 I/O 47 L6 5 A7-I/O 5 C5 5
— 40 I/O 48 L8 — I/O* 6 A4 —
— 41 I/O 49 K8 — I/O* 7 B4 —
40 I/O* 50 L9 6 A11-I/O 8 A3 6
41 I/O* 51 L10 7 A8-I/O 9 A2 7
42 42 I/O 52 K9 8 A10-I/O 10 B3 8
43 43 XTL2(IN)-I/O 53 L11 9 A9-I/O 11 A1 9
XC3000 Series Field Programmable Gate Arrays
4-330 June 1, 1996 (Version 2.0)
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020A/XC3030A/XC3042A.
PLCC Pin Number XC3064A, XC3090A, XC3195A PLCC Pin Number XC3064A, XC3090A, XC3195A
12 PWRDN 54 RESET
13 TCLKIN-I/O 55 DONE-PG
14 I/O 56 D7-I/O
15 I/O 57 XTL1(OUT)-BCLKIN-I/O
16 I/O 58 D6-I/O
17 I/O 59 I/O
18 I/O 60 D5-I/O
19 I/O 61 CS0-I/O
20 I/O 62 D4-I/O
21 GND* 63 I/O
22 VCC 64 VCC
23 I/O 65 GND*
24 I/O 66 D3-I/O*
25 I/O 67 CS1-I/O*
26 I/O 68 D2-I/O*
27 I/O 69 I/O
28 I/O 70 D1-I/O
29 I/O 71 RDY/BUSY-RCLK-I/O
30 I/O 72 D0-DIN-I/O
31 M1-RDATA 73 DOUT-I/O
32 M0-RTRIG 74 CCLK
33 M2-I/O 75 A0-WS-I/O
34 HDC-I/O 76 A1-CS2-I/O
35 I/O 77 A2-I/O
36 LDC-I/O 78 A3-I/O
37 I/O 79 I/O
38 I/O 80 I/O
39 I/O 81 A15-I/O
40 I/O 82 A4-I/O
41 INIT/I/O* 83 A14-I/O
42 VCC* 84 A5-I/O
43 GND 1 GND
44 I/O 2 VCC*
45 I/O 3 A13-I/O*
46 I/O 4 A6-I/O*
47 I/O 5 A12-I/O*
48 I/O 6 A7-I/O*
49 I/O 7 I/O
50 I/O 8 A11-I/O
51 I/O 9 A8-I/O
52 I/O 10 A10-I/O
53 XTL2(IN)-I/O 11 A9-I/O
June 1, 1996 (Version 2.0) 4-331
XC3000 Series 100-Pin QFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* This tab le describes the pinouts of three diff erent chips in three different pac kages . The pin-description column lists 100 of
the 118 pads on the XC3042A that are connected to the 100 package pins . Two pads, indicated by doub le asterisks, do not
exist on the XC3030A, which has 98 pads; therefore the corresponding pins ha ve no connections . Twenty-six pads , indicated
by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no
connections. (See table on page 326.)
Pin No. XC3020A
XC3030A
XC3042A
Pin No. XC3020A
XC3030A
XC3042A
Pin No. XC3020A
XC3030A
XC3042ACQFP PQFP TQFP
VQFP CQFP PQFP TQFP
VQFP CQFP PQFP TQFP
VQFP
1 16 13 GND 35 50 47 I/O* 69 84 81 I/O*
2 17 14 A13-I/O 36 51 48 I/O* 70 85 82 I/O*
3 18 15 A6-I/O 37 52 49 M1-RD 71 86 83 I/O
4 19 16 A12-I/O 38 53 50 GND* 72 87 84 D5-I/O
5 20 17 A7-I/O 39 54 51 MO-RT 73 88 85 CS0-I/O
6 21 18 I/O* 40 55 52 VCC* 74 89 86 D4-I/O
7 22 19 I/O* 41 56 53 M2-I/O 75 90 87 I/O
8 23 20 A11-I/O 42 57 54 HDC-I/O 76 91 88 VCC
9 24 21 A8-I/O 43 58 55 I/O 77 92 89 D3-I/O
10 25 22 A10-I/O 44 59 56 LDC-I/O 78 93 90 CS1-I/O
11 26 23 A9-I/O 45 60 57 I/O* 79 94 91 D2-I/O
12 27 24 VCC* 46 61 58 I/O* 80 95 92 I/O
13 28 25 GND* 47 62 59 I/O 81 96 93 I/O*
14 29 26 PWRDN 48 63 60 I/O 82 97 94 I/O*
15 30 27 TCLKIN-I/O 49 64 61 I/O 83 98 95 D1-I/O
16 31 28 I/O** 50 65 62 INIT-I/O 84 99 96 RDY/BUSY-RCLK-I/O
17 32 29 I/O* 51 66 63 GND 85 100 97 DO-DIN-I/O
18 33 30 I/O* 52 67 64 I/O 86 1 98 DOUT-I/O
19 34 31 I/O 53 68 65 I/O 87 2 99 CCLK
20 35 32 I/O 54 69 66 I/O 88 3 100 VCC*
21 36 33 I/O 55 70 67 I/O 89 4 1 GND*
22 37 34 I/O 56 71 68 I/O 90 5 2 AO-WS-I/O
23 38 35 I/O 57 72 69 I/O 91 6 3 A1-CS2-I/O
24 39 36 I/O 58 73 70 I/O 92 7 4 I/O**
25 40 37 I/O 59 74 71 I/O* 93 8 5 A2-I/O
26 41 38 VCC 60 75 72 I/O* 94 9 6 A3-I/O
27 42 39 I/O 61 76 73 XTL2-I/O 95 10 7 I/O*
28 43 40 I/O 62 77 74 GND* 96 11 8 I/O*
29 44 41 I/O 63 78 75 RESET 97 12 9 A15-I/O
30 45 42 I/O 64 79 76 VCC* 98 13 10 A4-I/O
31 46 43 I/O 65 80 77 DONE-PG 99 14 11 A14-I/O
32 47 44 I/O 66 81 78 D7-I/O 100 15 12 A5-I/O
33 48 45 I/O 67 82 79 BCLKIN-XTL1-I/O
34 49 46 I/O 68 83 80 D6-I/O
XC3000 Series Field Programmable Gate Arrays
4-332 June 1, 1996 (Version 2.0)
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
*Indicates unconnected package pins (14) for the XC3042A.
PGA
Pin
Number XC3042A
XC3064A
PGA
Pin
Number XC3042A
XC3064A
PGA
Pin
Number XC3042A
XC3064A
PGA
Pin
Number XC3042A
XC3064A
C4 GND B13 M1-RD P14 RESET M3 DOUT-I/O
A1 PWRDN C11 GND M11 VCC P1 CCLK
C3 I/O-TCLKIN A14 M0-RT N13 DONE-PG M4 VCC
B2 I/O D12 VCC M12 D7-I/O L3 GND
B3 I/O C13 M2-I/O P13 XTL1-I/O-BCLKIN M2 A0-WS-I/O
A2 I/O* B14 HDC-I/O N12 I/O N1 A1-CS2-I/O
B4 I/O C14 I/O P12 I/O M1 I/O
C5 I/O E12 I/O N11 D6-I/O K3 I/O
A3 I/O* D13 I/O M10 I/O L2 A2-I/O
A4 I/O D14 LDC-I/O P11 I/O* L1 A3-I/O
B5 I/O E13 I/O* N10 I/O K2 I/O
C6 I/O F12 I/O P10 I/O J3 I/O
A5 I/O E14 I/O M9 D5-I/O K1 A15-I/O
B6 I/O F13 I/O N9 CS0-I/O J2 A4-I/O
A6 I/O F14 I/O P9 I/O* J1 I/O*
B7 I/O G13 I/O P8 I/O* H1 A14-I/O
C7 GND G14 INIT-I/O N8 D4-I/O H2 A5-I/O
C8 VCC G12 VCC P7 I/O H3 GND
A7 I/O H12 GND M8 VCC G3 VCC
B8 I/O H14 I/O M7 GND G2 A13-I/O
A8 I/O H13 I/O N7 D3-I/O G1 A6-I/O
A9 I/O J14 I/O P6 CS1-I/O F1 I/O*
B9 I/O J13 I/O N6 I/O* F2 A12-I/O
C9 I/O K14 I/O P5 I/O* E1 A7-I/O
A10 I/O J12 I/O M6 D2-I/O F3 I/O
B10 I/O K13 I/O N5 I/O E2 I/O
A11 I/O* L14 I/O* P4 I/O D1 A11-I/O
C10 I/O L13 I/O P3 I/O D2 A8-I/O
B11 I/O K12 I/O M5 D1-I/O E3 I/O
A12 I/O* M14 I/O N4 RDY/BUSY-RCLK-I/O C1 I/O
B12 I/O N14 I/O P2 I/O B1 A10-I/O
A13 I/O* M13 XTL2(IN)-I/O N3 I/O C2 A9-I/O
C12 I/O L12 GND N2 D0-DIN-I/O D3 VCC
June 1, 1996 (Version 2.0) 4-333
XC3000 Series 144-Pin Plastic TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* Indicates unconnected package pins (24) for the XC3042A.
Pin
Number
XC3042A
XC3064A
XC3090A
Pin
Number
XC3042A
XC3064A
XC3090A
Pin
Number
XC3042A
XC3064A
XC3090A
1 PWRDN 49 I/O 97 I/O
2 I/O-TCLKIN 50 I/O* 98 I/O
3 I/O* 51 I/O 99 I/O*
4 I/O 52 I/O 100 I/O
5 I/O 53 INIT-I/O 101 I/O*
6 I/O* 54 VCC 102 D1-I/O
7 I/O 55 GND 103 RDY/BUSY-RCLK-I/O
8 I/O 56 I/O 104 I/O
9 I/O* 57 I/O 105 I/O
10 I/O 58 I/O 106 D0-DIN-I/O
11 I/O 59 I/O 107 DOUT-I/O
12 I/O 60 I/O 108 CCLK
13 I/O 61 I/O 109 VCC
14 I/O 62 I/O 110 GND
15 I/O* 63 I/O* 111 A0-WSI/O
16 I/O 64 I/O* 112 A1-CS2-I/O
17 I/O 65 I/O 113 I/O
18 GND 66 I/O 114 I/O
19 VCC 67 I/O 115 A2-I/O
20 I/O 68 I/O 116 A3-I/O
21 I/O 69 XTL2(IN)-I/O 117 I/O
22 I/O 70 GND 118 I/O
23 I/O 71 RESET 119 A15-I/O
24 I/O 72 VCC 120 A4-I/O
25 I/O 73 DONE-PG 121 I/O*
26 I/O 74 D7-I/O 122 I/O*
27 I/O 75 XTL1(OUT)-BCLKIN-I/O 123 A14-I/O
28 I/O* 76 I/O 124 A5-I/O
29 I/O 77 I/O 125 I/O (XC3090 only)
30 I/O 78 D6-I/O 126 GND
31 I/O* 79 I/O 127 VCC
32 I/O* 80 I/O* 128 A13-I/O
33 I/O 81 I/O 129 A6-I/O
34 I/O* 82 I/O 130 I/O*
35 I/O 83 I/O* 131 I/O (XC3090 only)
36 M1-RD 84 D5-I/O 132 I/O*
37 GND 85 CS0-I/O 133 A12-I/O
38 MO-RT 86 I/O* 134 A7-I/O
39 VCC 87 I/O* 135 I/O
40 M2-I/O 88 D4-I/O 136 I/O
41 HDC-I/O 89 I/O 137 A11-I/O
42 I/O 90 VCC 138 A8-I/O
43 I/O 91 GND 139 I/O
44 I/O 92 D3-I/O 140 I/O
45 LDC-I/O 93 CS1-I/O 141 A10-I/O
46 I/O* 94 I/O* 142 A9-I/O
47 I/O 95 I/O* 143 VCC
48 I/O 96 D2-I/O 144 GND
XC3000 Series Field Programmable Gate Arrays
4-334 June 1, 1996 (Version 2.0)
XC3000 Series 160-Pin PQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed IOBs are default slew-rate limited.
*Indicates unconnected package pins (18) for the XC3064A.
PQFP Pin
Number XC3064A, XC3090A,
XC3195A
1 I/O*
2 I/O
3 I/O
4 I/O
5 I/O
6 I/O
7 I/O
8 I/O
9 I/O
10 I/O
11 I/O
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
17 I/O
18 I/O
19 GND
20 VCC
21 I/O*
22 I/O
23 I/O
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O*
39 I/O*
40 M1-RDATA
41 GND
42 M0–RTRIG
43 VCC
44 M2-I/O
45 HDC-I/O
46 I/O
47 I/O
48 I/O
49 LDC-I/O
50 I/O*
51 I/O*
52 I/O
53 I/O
54 I/O
55 I/O
56 I/O
57 I/O
58 I/O
59 INIT-I/O
60 VCC
61 GND
62 I/O
63 I/O
64 I/O
65 I/O
66 I/O
67 I/O
68 I/O
69 I/O
70 I/O
71 I/O
72 I/O
73 I/O
74 I/O
75 I/O*
76 XTL2-I/O
77 GND
78 RESET
79 VCC
80 DONE/PG
PQFP Pin
Number XC3064A, XC3090A,
XC3195A 81 D7-I/O
82 XTL1-I/O-BCLKIN
83 I/O*
84 I/O
85 I/O
86 D6-I/O
87 I/O
88 I/O
89 I/O
90 I/O
91 I/O
92 D5-I/O
93 CS0-I/O
94 I/O*
95 I/O*
96 I/O
97 I/O
98 D4-I/O
99 I/O
100 VCC
101 GND
102 D3-I/O
103 CS1-I/O
104 I/O
105 I/O
106 I/O*
107 I/O*
108 D2-I/O
109 I/O
110 I/O
111 I/O
112 I/O
113 I/O
114 D1-I/O
115 RDY/BUSY-RCLK-I/O
116 I/O
117 I/O
118 I/O*
119 D0-DIN-I/O
120 DOUT-I/O
PQFP Pin
Number XC3064A, XC3090A,
XC3195A 121 CCLK
122 VCC
123 GND
124 A0-WS-I/O
125 A1-CS2-I/O
126 I/O
127 I/O
128 A2-I/O
129 A3-I/O
130 I/O
131 I/O
132 A15-I/O
133 A4-I/O
134 I/O
135 I/O
136 A14-I/O
137 A5-I/O
138 I/O*
139 GND
140 VCC
141 A13-I/O
142 A6-I/O
143 I/O*
144 I/O*
145 I/O
146 I/O
147 A12-I/O
148 A7-I/O
149 I/O
150 I/O
151 A11-I/O
152 A8-I/O
153 I/O
154 I/O
155 A10-I/O
156 A9-I/O
157 VCC
158 GND
159 PWRDWN
160 TCLKIN-I/O
PQFP Pin
Number XC3064A, XC3090A,
XC3195A
June 1, 1996 (Version 2.0) 4-335
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
PGA Pin
Number XC3090A, XC3195A
B2 PWRDN
D4 TCLKIN-I/O
B3 I/O
C4 I/O
B4 I/O
A4 I/O
D5 I/O
C5 I/O
B5 I/O
A5 I/O
C6 I/O
D6 I/O
B6 I/O
A6 I/O
B7 I/O
C7 I/O
D7 I/O
A7 I/O
A8 I/O
B8 I/O
C8 I/O
D8 GND
D9 VCC
C9 I/O
B9 I/O
A9 I/O
A10 I/O
D10 I/O
C10 I/O
B10 I/O
A11 I/O
B11 I/O
D11 I/O
C11 I/O
A12 I/O
B12 I/O
C12 I/O
D12 I/O
A13 I/O
B13 I/O
C13 I/O
A14 I/O
D13 I/O
B14 M1-RDATA
C14 GND
B15 M0-RTRIG
D14 VCC
C15 M2-I/O
E14 HDC-I/O
B16 I/O
D15 I/O
C16 I/O
D16 LDC-I/O
F14 I/O
E15 I/O
E16 I/O
F15 I/O
F16 I/O
G14 I/O
G15 I/O
G16 I/O
H16 I/O
H15 INIT-I/O
H14 VCC
J14 GND
J15 I/O
J16 I/O
K16 I/O
K15 I/O
K14 I/O
L16 I/O
L15 I/O
M16 I/O
M15 I/O
L14 I/O
N16 I/O
P16 I/O
N15 I/O
R16 I/O
M14 I/O
P15 XTL2(IN)-I/O
N14 GND
R15 RESET
P14 VCC
PGA Pin
Number XC3090A, XC3195A
R14 DONE-PG
N13 D7-I/O
T14 XTL1(OUT)-BCLKIN-I/O
P13 I/O
R13 I/O
T13 I/O
N12 I/O
P12 D6-I/O
R12 I/O
T12 I/O
P11 I/O
N11 I/O
R11 I/O
T11 D5-I/O
R10 CS0-I/O
P10 I/O
N10 I/O
T10 I/O
T9 I/O
R9 D4-I/O
P9 I/O
N9 VCC
N8 GND
P8 D3-I/O
R8 CS1-I/O
T8 I/O
T7 I/O
N7 I/O
P7 I/O
R7 D2-I/O
T6 I/O
R6 I/O
N6 I/O
P6 I/O
T5 I/O
R5 D1-I/O
P5 RDY/BUSY-RCLK-I/O
N5 I/O
T4 I/O
R4 I/O
P4 I/O
R3 D0-DIN-I/O
PGA Pin
Number XC3090A, XC3195A
N4 DOUT-I/O
R2 CCLK
P3 VCC
N3 GND
P2 A0-WS-I/O
M3 A1-CS2-I/O
R1 I/O
N2 I/O
P1 A2-I/O
N1 A3-I/O
L3 I/O
M2 I/O
M1 A15-I/O
L2 A4-I/O
L1 I/O
K3 I/O
K2 A14-I/O
K1 A5-I/O
J1 I/O
J2 I/O
J3 GND
H3 VCC
H2 A13-I/O
H1 A6-I/O
G1 I/O
G2 I/O
G3 I/O
F1 I/O
F2 A12-I/O
E1 A7-I/O
E2 I/O
F3 I/O
D1 A11-I/O
C1 A8-I/O
D2 I/O
B1 I/O
E3 A10-I/O
C2 A9-I/O
D3 VCC
C3 GND
PGA Pin
Number XC3090A, XC3195A
XC3000 Series Field Programmable Gate Arrays
4-336 June 1, 1996 (Version 2.0)
XC3000 Series 176-Pin TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
Pin
Number XC3090A
1 PWRDWN
2 TCLKIN-I/O
3 I/O
4 I/O
5 I/O
6 I/O
7 I/O
8 I/O
9 I/O
10 I/O
11 I/O
12 I/O
13 I/O
14 I/O
15 I/O
16 I/O
17 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 GND
23 VCC
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44 –
45 M1-RDATA
46 GND
47 M0-RTRIG
48 VCC
49 M2-I/O
50 HDC-I/O
51 I/O
52 I/O
53 I/O
54 LDC-I/O
55 –
56 I/O
57 I/O
58 I/O
59 I/O
60 I/O
61 I/O
62 I/O
63 I/O
64 I/O
65 INIT-I/O
66 VCC
67 GND
68 I/O
69 I/O
70 I/O
71 I/O
72 I/O
73 I/O
74 I/O
75 I/O
76 I/O
77 I/O
78 I/O
79 I/O
80 I/O
81 I/O
82 –
83 –
84 I/O
85 XTAL2(IN)-I/O
86 GND
87 RESET
88 VCC
Pin
Number XC3090A
89 DONE-PG
90 D7-I/O
91 XTAL1(OUT)-BCLKIN-I/O
92 I/O
93 I/O
94 I/O
95 I/O
96 D6-I/O
97 I/O
98 I/O
99 I/O
100 I/O
101 I/O
102 D5-I/O
103 CS0-I/O
104 I/O
105 I/O
106 I/O
107 I/O
108 D4-I/O
109 I/O
110 VCC
111 GND
112 D3-I/O
113 CS1-I/O
114 I/O
115 I/O
116 I/O
117 I/O
118 D2-I/O
119 I/O
120 I/O
121 I/O
122 I/O
123 I/O
124 D1-I/O
125 RDY/BUSY-RCLK-I/O
126 I/O
127 I/O
128 I/O
129 I/O
130 D0-DIN-I/O
131 DOUT-I/O
132 CCLK
Pin
Number XC3090A
133 VCC
134 GND
135 A0-WS-I/O
136 A1-CS2-I/O
137 –
138 I/O
139 I/O
140 A2-I/O
141 A3-I/O
142 –
143 –
144 I/O
145 I/O
146 A15-I/O
147 A4-I/O
148 I/O
149 I/O
150 A14-I/O
151 A5-I/O
152 I/O
153 I/O
154 GND
155 VCC
156 A13-I/O
157 A6-I/O
158 I/O
159 I/O
160 –
161 –
162 I/O
163 I/O
164 A12-I/O
165 A7-I/O
166 I/O
167 I/O
168 –
169 A11-I/O
170 A8-I/O
171 I/O
172 I/O
173 A10-I/O
174 A9-I/O
175 VCC
176 GND
Pin
Number XC3090A
June 1, 1996 (Version 2.0) 4-337
XC3000 Series 208-Pin PQFP Pinouts
XC3000A, and XC3000L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
*In PQ208, XC3090A and XC3195A have different pinouts.
Pin Number XC3090A
1–
2 GND
3 PWRDWN
4 TCLKIN-I/O
5 I/O
6 I/O
7 I/O
8 I/O
9 I/O
10 I/O
11 I/O
12 I/O
13 I/O
14 I/O
15 –
16 I/O
17 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 I/O
23 I/O
24 I/O
25 GND
26 VCC
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
33 I/O
34 I/O
35 I/O
36 I/O
37 –
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44 I/O
45 I/O
46 I/O
47 I/O
48 M1-RDATA
49 GND
50 M0-RTRIG
51 –
52 –
53 –
54 –
55 VCC
56 M2-I/O
57 HDC-I/O
58 I/O
59 I/O
60 I/O
61 LDC-I/O
62 I/O
63 I/O
64 –
65 –
66 –
67 –
68 I/O
69 I/O
70 I/O
71 I/O
72 –
73 –
74 I/O
75 I/O
76 I/O
77 INIT-I/O
78 VCC
79 GND
80 I/O
81 I/O
82 I/O
83 –
84 –
85 I/O
86 I/O
87 I/O
88 I/O
89 I/O
90 –
91 –
92 –
93 I/O
94 I/O
95 I/O
96 I/O
97 I/O
98 I/O
99 I/O
100 XTL2-I/O
101 GND
102 RESET
103 –
104 –
Pin Number XC3090A 105 –
106 VCC
107 D/P
108 –
109 D7-I/O
110 XTL1-BCLKIN-I/O
111 I/O
112 I/O
113 I/O
114 I/O
115 D6-I/O
116 I/O
117 I/O
118 I/O
119 –
120 I/O
121 I/O
122 D5-I/O
123 CS0-I/O
124 I/O
125 I/O
126 I/O
127 I/O
128 D4-I/O
129 I/O
130 VCC
131 GND
132 D3-I/O
133 CS1-I/O
134 I/O
135 I/O
136 I/O
137 I/O
138 D2-I/O
139 I/O
140 I/O
141 I/O
142 –
143 I/O
144 I/O
145 D1-I/O
146 RDY/BUSY-RCLK-I/O
147 I/O
148 I/O
149 I/O
150 I/O
151 DIN-D0-I/O
152 DOUT-I/O
153 CCLK
154 VCC
155 –
156 –
Pin Number XC3090A 157 –
158 –
159 –
160 GND
161 WS-A0-I/O
162 CS2-A1-I/O
163 I/O
164 I/O
165 A2-I/O
166 A3-I/O
167 I/O
168 I/O
169 –
170 –
171 –
172 A15-I/O
173 A4-I/O
174 I/O
175 I/O
176 –
177 –
178 A14-I/O
179 A5-I/O
180 I/O
181 I/O
182 GND
183 VCC
184 A13-I/O
185 A6-I/O
186 I/O
187 I/O
188 –
189 –
190 I/O
191 I/O
192 A12-I/O
193 A7-I/O
194 –
195 –
196 –
197 I/O
198 I/O
199 A11-I/O
200 A8-I/O
201 I/O
202 I/O
203 A10-I/O
204 A9-I/O
205 VCC
206 –
207 –
208 –
Pin Number XC3090A
XC3000 Series Field Programmable Gate Arrays
4-338 June 1, 1996 (Version 2.0)
XC3195A PQ208 and PG223 Pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are
default slew-rate limited.
In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected.
In the PG223 package, the following pins are not connected: A5, A6, A13, A14, D18, E1, E18, F1, F18, N1, N18, P1, P18, V5, V6, V13, and
V14.
*In PQ208, XC3090A and XC3195A have different pinouts.
Pin Description PG223 PQ208
A9-I/O B1 206
A10-I/O E3 205
I/O E4 204
I/O C2 203
I/O C1 202
I/O D2 201
A8-I/O E2 200
A11-I/O F4 199
I/O F3 198
I/O D1 197
I/O F2 196
I/O G2 194
A7-I/O G4 193
A12-I/O G1 192
I/O H2 191
I/O H3 190
I/O H1 189
I/O H4 188
I/O J3 187
I/O J2 186
A6-I/O J1 185
A13-I/O K3 184
VCC J4 183
GND K4 182
I/O K2 181
I/O K1 180
A5-I/O L2 179
A14-I/O L4 178
I/O L3 177
I/O L1 176
I/O M1 175
I/O M2 174
A4-I/O M4 173
A15-I/O N2 172
I/O N3 171
I/O P2 169
I/O R1 168
I/O N4 167
A3-I/O T1 166
A2-I/O R2 165
I/O P3 164
I/O T2 163
I/O P4 162
I/O U1 161
A1-CS2-I/O V1 160
A0-WS-I/O T3 159
GND R3 158
VCC R4 157
CCLK U2 156
DOUT-I/O V2 155
D0-DIN-I/O U3 154
I/O V3 153
I/O R5 152
I/O T4 151
I/O V4 150
RDY/BUSY-RCLK-I/O U4 149
D1-I/O U5 148
I/O R6 147
I/O T5 146
I/O U6 145
I/O T6 144
I/O V7 141
I/O R7 140
I/O U7 139
D2-I/O V8 138
I/O U8 137
I/O T8 136
I/O R8 135
I/O V9 134
CS1-I/O U9 133
D3-I/O T9 132
GND R9 131
VCC R10 130
I/O T10 129
D4-I/O U10 128
I/O V10 127
I/O R11 126
I/O T11 125
I/O U11 124
CS0-I/O V11 123
D5-I/O U12 122
I/O R12 121
I/O V12 120
I/O T13 119
I/O U13 118
I/O T14 117
I/O R13 116
I/O U14 115
D6-I/O U15 114
I/O V15 113
I/O T15 112
I/O R14 111
I/O V16 110
XTLX1(OUT)BCLKN-I/O U16 109
D7-I/O T16 108
D/P V17 107
VCC R15 106
RESET U17 105
GND R16 104
XTL2(IN)-I/O V18 103
Pin Description PG223 PQ208 I/O U18 102
I/O P15 101
I/O T17 100
I/O T18 99
I/O P16 98
I/O R17 97
I/O N15 96
I/O R18 95
I/O P17 94
I/O N17 93
I/O N16 92
I/O M15 89
I/O M18 88
I/O M17 87
I/O L18 86
I/O L17 85
I/O L15 84
I/O L16 83
I/O K18 82
I/O K17 81
I/O K16 80
GND K15 79
VCC J15 78
INIT J16 77
I/O J17 76
I/O J18 75
I/O H16 74
I/O H15 73
I/O H17 72
I/O H18 71
I/O G17 70
I/O G18 69
I/O G15 68
I/O F16 67
I/O F17 66
I/O E17 63
I/O C18 62
I/O F15 61
I/O D17 60
LDC-I/O E16 59
I/O C17 58
I/O B18 57
I/O E15 56
HDC-I/O A18 55
M2-I/O A17 54
VCC D16 53
M0-RTIG B17 52
GND D15 51
M1/RDATA C16 50
I/O B16 49
Pin Description PG223 PQ208 I/O A16 48
I/O D14 47
I/O C15 46
I/O B15 45
I/O A15 44
I/O C14 43
I/O D13 42
I/O B14 41
I/O C13 40
I/O B13 39
I/O B12 38
I/O D12 37
I/O A12 36
I/O B11 35
I/O C11 34
I/O A11 33
I/O D11 32
I/O A10 31
I/O B10 30
I/O C10 29
I/O C9 28
VCC D10 27
GND D9 26
I/O B9 25
I/O A9 24
I/O C8 23
I/O D8 22
I/O B8 21
I/O A8 20
I/O B7 19
I/O A7 18
I/O D7 17
I/O B6 14
I/O C6 13
I/O B5 12
I/O A4 11
I/O D6 10
I/O C5 9
I/O B4 8
I/O B3 7
I/O C4 6
I/O D5 5
I/O C3 4
I/O A3 3
TCLKIN-I/O A2 2
PWRDN B2 1
GND D4 208
VCC D3 207
Pin Description PG223 PQ208
June 1, 1996 (Version 2.0) 4-339
Product Availability
Pins 44 64 68 84 100 132 144 160 164 175 176 208 223
Type Plast.
PLCC Plast.
VQFP Plast.
PLCC Plast.
PLCC Cer.
PGA Plast.P
QFP Plast.
TQFP Plast.
VQFP
Top-
Brazed
CQFP Plast.
PGA Cer.
PGA Plast.
TQFP Plast.
PQFP
Top-
Brazed
CQFP Plast.
PGA Cer.
PGA Plast.
TQFP Plast.
PQFP Cer.
PGA
Code PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3020A -7 CI CI CI CI
-6 CCCC
XC3030A -7 CI CI CI CI CI CI CI
-6CCCCCC C
XC3042A -7 CI CI CI CI CI CI CI
-6 CCC C CCC
XC3064A -7 CI CI CI CI CI
-6 C CCCC
XC3090A -7 CI CI CI CI CI CI CI
-6 C CC CCCC
XC3020L -8 C
XC3030L -8 C C C
XC3042L -8 C C C
XC3064L -8 C C
XC3090L -8 C C C
XC3120A
-5 CI CI CI CI
-4 CI CI CI CI
-3 CI CI CI CI
-2 CI CI CI CI
-1 CCCC
-09 C C C C
XC3130A
-5 CI CI CI CI CI CI CI
-4 CI CI CI CI CI CI CI
-3 CI CI CI CI CI CI CI
-2 CI CI CI CI CI CI CI
-1CCCCCC C
-09CCCCCC C
XC3142A
-5 CI CIMB CI C MB C CIMB CI
-4 CI CI CI C C CI CI
-3 CI CI CI CI CI CI CI
-2 CI CI CI CI CI CI CI
-1 CCC C CCC
-09 CCC C CCC
XC3164A
-5 CI CI CI CI CI
-4 CI CI CI CI CI
-3 CI CI CI CI CI
-2 CI CI CI CI CI
-1 C CCCC
-09 C CCCC
XC3190A
-5 CI CI MB CI CIMB CI CI
-4 CI CI CI CI CI CI
-3 CI CI CI CI CI CI
-2 CI CI CI CI CI CI
-1 C C CCCC
-09 C C CCCC
XC3195A
-5 CI CI MB CI CIMB CI CIMB
-4 CI CI CI CI CI CI
-3 CI CI CI CI CI CI
-2 CI CI CI CI CI CI
-1 C C CC CC
-09 C C CC CC
XC3000 Series Field Programmable Gate Arrays
4-340 June 1, 1996 (Version 2.0)
Ordering Information
XC3142L -3* C C C
-2* C C C
XC3190L -3* C C C
-2* C C C
Notes: * Advance Information
C = Commercial, TJ= 0° to +85°C
M=Military Temp, TC= -55° to +125°CI = Industrial, TJ = -40° to +100°C
B = MIL-STD-883C Class B
Pins 44 64 68 84 100 132 144 160 164 175 176 208 223
Type Plast.
PLCC Plast.
VQFP Plast.
PLCC Plast.
PLCC Cer.
PGA Plast.P
QFP Plast.
TQFP Plast.
VQFP
Top-
Brazed
CQFP Plast.
PGA Cer.
PGA Plast.
TQFP Plast.
PQFP
Top-
Brazed
CQFP Plast.
PGA Cer.
PGA Plast.
TQFP Plast.
PQFP Cer.
PGA
Code PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3030A-3 PC44C
Example:
Device Type
Speed Grade Temperature Range
Number of Pins
Package Type
June 1, 1996 (Version 1.0) 4-341
Features
• Enhanced, high performance FPGA family with five
device types
- Improved redesign of the basic XC3000 FPGA
family
- Logic densities from 1,000 to 6,000 gates
- Up to 144 user-definable I/Os
• Superset of the industry-leading XC3000 family
- Identical to the basic XC3000 in structure, pin out,
design methodology, and software tools
- 100% compatible with all XC3000, XC3000L, and
XC3100A bitstreams
- Improved routing and additional features
• Additional programmable interconnection points (PIPs)
- Improved access to longlines and CLB clock enable
inputs
- Most efficient XC3000-class solution to bus-oriented
designs
• Advanced 0.8 µ and 0.6 µ CMOS static memory
technology
- Low quiescent and active power consumption
• Performance specified by logic delays, faster than
corresponding XC3000 versions
• XC3000A-specific features
- 4 mA output sink and source current
- Error checking of the configuration bitstream
- Soft startup starts all outputs in slew-limited mode
upon power-up
- Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production.
Description
The XC3000A family offers the following enhancements
over the popular XC3000 family:
The XC3000A family has additional interconnect resources
to drive the I-inputs of TBUFs driving hor izontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more effi-
cient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000A devices check the bit-
stream format f or stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
star ts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all out-
puts are turned on simultaneously. After star t-up, the slew
rate of the individual outputs is, as in the XC3000 family,
determined by the individual configuration option.
The XC3000A family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000, XC3100 or
XC3100A device configures an XC3000A device exactly
the same way.
XC3000A
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0) Product Specification
Device Max Logic
Gates Typical Gate
Range CLBs Array User I/Os
Max Flip-Flops Horizontal
Longlines Configuration
Data Bits
XC3020A 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779
XC3030A 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176
XC3042A 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784
XC3064A 5,000 4,000 - 5,000 224 16 x 14 120 688 32 46,064
XC3090A 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160
XC3000A Field Programmable Gate Arrays
4-342 June 1, 1996 (Version 1.0)
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents . To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Note: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
XC3000A DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a MakeBits tie option.
2. Total continuous output sink current may not e xceed 100 mA per g round pin. Total continuous output source ma y not e xceed
100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A.
Symbol Description Min Max Units
VCC
Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25 V
Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V
VIHT High-level input voltage — TTL configuration 2.0 VCC V
VILT Low-level input voltage — TTL configuration 0 0.8 V
VIHC High-level input voltage — CMOS configuration 70% 100% VCC
VILC Low-level input voltage — CMOS configuration 0 20% VCC
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) Commercial 3.86 V
VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V
VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) Industrial 3.76 V
VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V
VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V
ICCPD Power-down supply current
(VCC(MAX) @ TMAX) 3020A
3030A
3042A
3064A
3090A
100
160
240
340
500
µA
µA
µA
µA
µA
ICCO
Quiescent FPGA supply current in addition to ICCPD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels 500
10 µA
µA
IIL Input Leakage Current –10 +10 µA
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 10
15 pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 16
20 pF
pF
IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) 0.02 0.17 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 3.4 mA
June 1, 1996 (Version 1.0) 4-343
XC3000A Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Note: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VIN Input voltage with respect to GND –0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
TJJunction temperature plastic +125 °C
Junction temperature ceramic +150 °C
Speed Grade -7 -6
Description Symbol Max Max Units
Global and Alternate Clock Distribution1
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
7.5
6.0
7.0
5.7
ns
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
TIO
TON
TON
TPUS
TPUF
4.5
9.0
11.0
16.0
10.0
4.0
8.0
10.0
14.0
8.0
ns
ns
ns
ns
ns
BIDI Bidirectional buffer delay TBIDI 1.7 1.5 ns
XC3000A Field Programmable Gate Arrays
4-344 June 1, 1996 (Version 1.0)
XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of an y CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
Speed Grade -7 -6
Description Symbol Min Max Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode 1T
ILO 5.1
5.6 4.1
4.6 ns
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
8T
CKO
TQLO
4.5
9.5
10.0
4.0
8.0
8.5
ns
ns
ns
Set-up time before clock K
Logic Variables A, B, C, D, E
FG Mode
F and FGM Mode
Data In DI
Enable Clock EC
2
4
6
TICK
TDICK
TECCK
4.5
5.0
4.0
4.5
3.5
4.0
3.0
4.0
ns
ns
ns
ns
Hold Time after clock K
Logic Variables A, B, C, D, E
Data In DI2
Enable Clock EC
3
5
7
TCKI
TCKDI
TCKEC
0
1.0
2.0
0
1.0
2.0
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TCH
TCL
FCLK
4.0
4.0
113.0
3.5
3.5
135.0
ns
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y 13
9TRPW
TRIO
6.0 6.0 5.0 5.0 ns
ns
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y TMRW
TMRQ
16.0 19.0 14.0 17.0 ns
ns
June 1, 1996 (Version 1.0) 4-345
XC3000A CLB Switching Characteristics Guidelines (continued)
1TILO
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
8TCKO
X5424
13 T
T
RPW
9T
RIO
4TDICK
6TECCK
12 TCL
2TICK 3TCKI
11 TCH
5TCKDI
7TCKEC
XC3000A Field Programmable Gate Arrays
4-346 June 1, 1996 (Version 1.0)
XC3000A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input.
Speed Grade -7 -6
Description Symbol Min Max Min Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
4.0
15.0
3.0
3.0
14.0
2.5
ns
ns
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time 1 TPICK 14.0 12.0 ns
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same (slew rate limited)
Output (O) to Pad (fast)
same (slew-rate limited)
3-state to Pad begin hi-Z (fast)
same (slew-rate limited)
3-state to Pad active and valid (fast)
same (slew -rate limited)
7
7
10
10
9
9
8
8
TOKPO
TOKPO
TOPF
TOPS
TTSHZ
TTSHZ
TTSON
TTSON
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
7.0
15.0
5.0
13.0
9.0
12.0
10.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time 5
6TOOK
TOKO
8.0
07.0
0ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TIOH
TIOL
FCLK
4.0
4.0
113.0
3.5
3.5
135.0
ns
ns
MHz
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
13
15
15
TRRI
TRPO
TRPO
24.0
33.0
43.0
23.0
29.0
37.0
ns
ns
ns
June 1, 1996 (Version 1.0) 4-347
XC3000A IOB Switching Characteristics Guidelines (continued)
3TPID
I/O Block (I)
I/O Pad Input
I/O Clock (IK/OK)
I/O Block (RI)
RESET
I/O Block (O)
I/O Pad TS
I/O Pad Output
I/O Pad Output
(Direct)
I/O Pad Output
(Registered)
X5425
5TOOK
12 TIOL
1TPICK
11 TIOH
4TIKRI
15 TRPO
13 TRRI
6TOKO
9TTSHZ
10 TOP
7TOKPO
8TTSON
FLIP
FLOP
QD
R
SLEW
RATE PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
DQ
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IKOK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
XC3000A Field Programmable Gate Arrays
4-348 June 1, 1996 (Version 1.0)
Product Availability
Note: C = Commercial, TJ = 0° to +85°C I = Industrial, TJ = -40° to +100°C
Ordering Information
PINS 44 64 68 84 100
TYPE PLAST.
PLCC PLAST.
VQFP PLAST.
PLCC PLAST.
PLCC CERAM
PGA PLAST.
PQFP PLAST.
TQFP PLAST.
VQFP
TOP-
BRAZED
CQFP
CODE PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100
XC3020A -7 C I C I C I C I
-6 CCCC
XC3030A -7 C I C I C I C I C I C I C I
-6CCCCCC C
XC3042A -7 C I C I C I C I
-6 C C C C
XC3064A -7 C I
-6 C
XC3090A -7 C I
-6 C
PINS 132 144 160 164 175 176 208 223
TYPE PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP
TOP-
BRAZED
CQFP
PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP CERAM.
PGA
CODE PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3020A -7
-6
XC3030A -7
-6
XC3042A -7 C I C I C I
-6CCC
XC3064A -7 C I C I C I C I
-6CCCC
XC3090A -7 C I C I C I C I C I C I
-6 CC CCCC
XC3020A-6PC84C
Example:
Device Type
Speed Grade Temperature Range
Number of Pins
Package Type
June 1, 1996 (Version 1.0) 4-349
Mar
Features
• Part of the Zero+ family of 3.3 V FPGAs
- JEDEC-compliant 3.3 V version of theXC3000A
FPGA family
- Logic densities from 1,000 to 6,000 gates
- Up to 144 user-definable I/Os
• Advanced, low power 0.8 µ and 0.6 µ CMOS static
memory technology
- Very low quiescent current consumption, ≤ 20µA
- Operating power consumption 56% less than
XC3000A, 66% less than previous generation 5 V
FPGAs
• Superset of the industry-leading XC3000 family
- Identical to the basic XC3000A in structure, pinout,
design methodology, and software tools
- 100% compatible with all XC3000, XC3000A,
XC3100L and XC3100A bitstreams
- Improved routing and additional features
• Additional programmable interconnection points (PIPs)
- Improved access to Longlines and CLB cloc k enab le
inputs
- Most efficient XC3000-class solution to bus-oriented
designs
• XC3000L-specific features
- Guaranteed over the 3.0 to 3.6 V Vcc range
- 4 mA output sink and source current
- Error checking of the configuration bitstream
- Soft startup starts all outputs in slew-limited mode
upon power-up
- Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production
Description
The XC3000L family of FPGAs is optimized for operation
from a nominally 3.3 V supply. Aside from the electrical and
timing parameters listed in this data sheet, the XC3000L
family is in all respects identical with the XC3000A family,
and is a superset of the XC3000 family.
The operating power consumption of Xilinx FPGAs is
almost exclusiv ely dynamic , and it changes with the square
of the supply voltage. For a given complexity and clock
speed, the XC3000L consumes, therefore, only 44% of the
power used by the equivalent XC3000A device. In accor-
dance with its use in battery-powered equipment, the
XC3000L family was designed for the lowest possible
power-down and quiescent current consumption.
In mixed supply-voltage systems, the XC3000L, fed by a
3.3 V (nominal) supply, can directly drive any device with
TTL-like input thresholds. When a 5 V device drives the
XC3000L, a current-limiting resistor (1 kΩ) or a voltage
divider is required to prevent excessive input current.
Like the XC3000A family, XC3000L offers the following
functional improvements over the popular XC3000 family:
The XC3000L family has additional interconnect resources
to drive the I-inputs of TBUFs driving hor izontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more effi-
cient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000L devices check the bit-
stream format f or stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
star ts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all out-
puts are turned on simultaneously. After star t-up, the slew
rate of the individual outputs is, as in the XC3000 family,
determined by the individual configuration option.
The XC3000L family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000 device config-
ures an XC3000L device the same way.
XC3000L
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0) Product Specification
Device Max Logic
Gates Typical Gate
Range CLBs Array User I/Os
Max Flip-Flops Horizontal
Longlines Configuration
Data Bits
XC3020L 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779
XC3030L 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176
XC3042L 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784
XC3064L 5,000 4,000 - 5,000 224 16 x 14 120 688 32 46,064
XC3090L 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160
XC3000L Field Programmable Gate Arrays
4-350 June 1, 1996 (Version 1.0)
XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents . To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000L Operating Conditions
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2. Although the present (1996) devices oper ate o v er the full supply v oltage r ange from 3.0 to 5.25 V, Xilinx reserves the right to
restrict operation to the 3.0 to 6.0 V range later, when smaller device geometries might preclude operation at 5V. Operating
conditions are guaranteed in the 3.0 – 3.6 V VCC range.
XC3000L DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a MakeBits tie option. ICCO is in addition to ICCPD.
2. Total continuous output sink current may not e xceed 100 mA per g round pin. Total continuous output source ma y not e xceed
100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L.
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial 0°C to +85°C junction 3.0 3.6 V
VIH High-level input voltage — TTL configuration 2.0 VCC+0.3 V
VIL Low-level input voltage — TTL configuration -0.3 0.8 V
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) 2.40 V
VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V
VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) VCC -0.2 V
VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.2 V
VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V
ICCPD Power-down supply current (VCC(MAX) @ TMAX)10µA
I
CCO Quiescent FPGA supply current in addition to ICCPD1
Chip thresholds programmed as CMOS levels 20 µA
IIL Input Leakage Current –10 +10 µA
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 10
15 pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 15
20 pF
pF
IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) 0.02 0.17 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 2.50 mA
June 1, 1996 (Version 1.0) 4-351
XC3000L Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000L Global Buffer Switching Characteristics Guidelines
1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VIN Input voltage with respect to GND –0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
TJJunction temperature plastic +125 °C
Junction temperature ceramic +150 °C
Speed Grade -8
Description Symbol Max Units
Global and Alternate Clock Distribution1
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
9.0
7.0
ns
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↑ to L.L. High with single pull-up resistor
TIO
TON
TPUS
5.0
12.0
24.0
ns
ns
ns
BIDI Bidirectional buffer delay TBIDI 2.0 ns
XC3000L Field Programmable Gate Arrays
4-352 June 1, 1996 (Version 1.0)
XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is based on the XC3042L, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of an y CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
Speed Grade -8
Description Symbol Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode 1T
ILO 6.7
7.5 ns
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
8T
CKO
TQLO
7.5
14.0
14.8
ns
ns
ns
Set-up time before clock K
Logic Variables A, B, C, D, E
FG Mode
F and FGM Mode
Data In DI
Enable Clock EC
2
4
6
TICK
TDICK
TECCK
5.0
5.8
5.0
6.0
ns
ns
ns
ns
Hold Time after clock K
Logic Variables A, B, C, D, E
Data In DI2
Enable Clock EC
3
5
7
TCKI
TCKDI
TCKEC
0
2.0
2.0
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TCH
TCL
FCLK
5.0
5.0
80.0
ns
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y 13
9TRPW
TRIO
7.0
7.0 ns
ns
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y TMRW
TMRQ
16.0 23.0 ns
ns
June 1, 1996 (Version 1.0) 4-353
XC3000L CLB Switching Characteristics Guidelines (continued)
1TILO
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
8TCKO
X5424
13 T
T
RPW
9T
RIO
4TDICK
6TECCK
12 TCL
2TICK 3TCKI
11 TCH
5TCKDI
7TCKEC
XC3000L Field Programmable Gate Arrays
4-354 June 1, 1996 (Version 1.0)
XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input.
Speed Grade -8
Description Symbol Min Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
5.0
24.0
6.0
ns
ns
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time 1 TPICK 22.0 ns
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same (slew rate limited)
Output (O) to Pad (fast)
same (slew-rate limited)
3-state to Pad begin hi-Z (fast)
same (slew-rate limited)
3-state to Pad active and valid (fast)
same (slew -rate limited)
7
7
10
10
9
9
8
8
TOKPO
TOKPO
TOPF
TOPS
TTSHZ
TTSHZ
TTSON
TTSON
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0
ns
ns
ns
ns
ns
ns
ns
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time 5
6TOOK
TOKO
12.0
0ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TIOH
TIOL
FCLK
5.0
5.0
80.0
ns
ns
MHz
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
13
15
15
TRRI
TRPO
TRPO
25.0
35.0
51.0
ns
ns
ns
June 1, 1996 (Version 1.0) 4-355
XC3000L IOB Switching Characteristics Guidelines (continued)
3TPID
I/O Block (I)
I/O Pad Input
I/O Clock (IK/OK)
I/O Block (RI)
RESET
I/O Block (O)
I/O Pad TS
I/O Pad Output
I/O Pad Output
(Direct)
I/O Pad Output
(Registered)
X5425
5TOOK
12 TIOL
1TPICK
11 TIOH
4TIKRI
15 TRPO
13 TRRI
6TOKO
9TTSHZ
10 TOP
7TOKPO
8TTSON
FLIP
FLOP
QD
R
SLEW
RATE PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
DQ
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IKOK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
XC3000L Field Programmable Gate Arrays
4-356 June 1, 1996 (Version 1.0)
Product Availability
Note: C = Commercial, TJ = 0° to +85°C
Ordering Information
PINS 44 64 68 84 100
TYPE PLAST.
PLCC PLAST.
VQFP PLAST.
PLCC PLAST.
PLCC CERAM
PGA PLAST.
PQFP PLAST.
TQFP PLAST.
VQFP
TOP-
BRAZED
CQFP
CODE PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100
XC3020L C
XC3030L C C C
XC3042L C C
XC3064L C
XC3090L C
PINS 132 144 160 164 175 176 208 223
TYPE PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP
TOP-
BRAZED
CQFP
PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP CERAM.
PGA
CODE PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3020L
XC3030L
XC3042L C
XC3064L C
XC3090L C C
XC3042L-8VQ100C
Example:
Device Type
Speed Grade Temperature Range
Number of Pins
Package Type
June 1, 1996 (Version 4.1) 4-357
Features
• Ultra-high-speed FPGA family with six members
- 50-95 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
• High-end additional family member in the 22 X 22 CLB
array-size XC3195A device
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other
XC3000 families
• Software and bitstream compatible with the XC3000,
XC3000A, and XC3000L families
• 100% PCI complaint (A-2, A-1, A-09 speed grade in
plastic quad flat pack (PQFP) packaging).
XC3100A combines the features of the XC3000A and
XC3100 families.
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Description
The XC3100A is a performance-optimized relative of the
XC3000A and XC3100A families . While all f amilies are foot-
print compatible, XC3100A family extends the typical sys-
tem performance beyond 85 MHz.
The XC3100A family follows the XC4000 speed-grade
nomenclature, indicating device performance with a num-
ber that is based on the internal logic-block delay, in ns.
The XC3100A family offers the following enhancements
over the popular XC3000 family.
The XC3100A family has additional interconnect resources
to drive the I-inputs of TBUFs driving hor izontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more effi-
cient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3100A devices check the bit-
stream format f or stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
star ts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all out-
puts are turned on simultaneously. After star t-up, the slew
rate of the individual outputs is, as in all XC3000 families,
determined by the individual configuration option.
The XC3100A family is a superset of the XC3000 families.
Any bitstream used to configure an XC3000, XC3000A,
XC3000L or XC3100 device, will configure the same-size
XC3100A device exactly the same way.
XC3100A
Field Programmable Gate Arrays
June 1, 1996 (Version 4.1) Product Specification
Device Max Logic
Gates Typical Gate
Range CLBs Array User I/Os
Max Flip-Flops Horizontal
Longlines Configuration
Data Bits
XC3120A 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779
XC3130A 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176
XC3142A 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784
XC3164A 4,500 3,500 - 4,500 224 16 x 14 120 688 32 46,064
XC3190A 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160
XC3195A 7,500 6,500 - 7,500 484 22 x 22 176 1,320 44 94,944
XC3100A Field Programmable Gate Arrays
4-358 June 1, 1996 (Version 4.1)
XC3100A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents . To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100A Operating Conditions
Note: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
XC3100A DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA
device configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for
the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package.
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial 0°C to +85°C junction 4.25 5.25 V
Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V
VIHT High-level input voltage — TTL configuration 2.0 VCC V
VILT Low-level input voltage — TTL configuration 0 0.8 V
VIHC High-level input voltage — CMOS configuration 70% 100% VCC
VILC Low-level input voltage — CMOS configuration 0 20% VCC
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage (@ IOH = –8.0 mA, VCC min) Commercial 3.86 V
VOL Low-level output voltage (@ IOL = 8.0 mA, VCC min) 0.40 V
VOH High-level output voltage (@ IOH = –8.0 mA, VCC min) Industrial 3.76 V
VOL Low-level output voltage (@ IOL = 8.0 mA, VCC min) 0.40 V
VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V
ICCO
Quiescent LCA supply current in addition to ICCPD1
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels 8
14 mA
mA
IIL Input Leakage Current –10 +10 µA
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 10
15 pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2 15
20 pF
pF
IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) 0.02 0.17 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.20 2.80 mA
June 1, 1996 (Version 4.1) 4-359
XC3100A Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Note: 1. Timing is based on the XC3142A, for other devices see XACT timing calculator.
The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A
devices.
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VIN Input voltage with respect to GND –0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
TJJunction temperature plastic +125 °C
Junction temperature ceramic +150 °C
Speed Grade -5 -4 -3 -2 -1 -09
Description Symbol Max Max Max Max Max Max Units
Global and Alternate Clock Distribution1
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
6.8
5.4
6.5
5.1
5.6
4.3
4.7
3.7
4.3
3.5
3.9
3.1
ns
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active) (XC3100)
(XC3100A)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
TIO
TIO
TON
TON
TPUS
TPUF
4.1
3.6
5.6
7.1
15.6
12.0
3.7
3.6
5.0
6.5
13.5
10.5
3.1
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
2.1
3.1
4.6
8.9
5.9
ns
ns
ns
ns
ns
ns
BIDI Bidirectional buffer delay TBIDI 1.4 1.2 1.0 0.9 0.85 0.75 ns
Prelim
XC3100A Field Programmable Gate Arrays
4-360 June 1, 1996 (Version 4.1)
XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. The CLB K to Q output delay (TCKO, #8) of an y CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and
0.30 ns (-09).
Speed Grade -5 -4 -3 -2 -1 -09
Description Symbol Min Max Min Max Min Max Min Max Min Max Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E,
to outputs X or Y 1T
ILO 4.1 3.3 2.7 2.2 1.75 1.5 ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is re-
turned through function generators F
or G to drive X or Y
8T
CKO
TQLO
3.1
6.3
2.5
5.2
2.1
4.3
1.7
3.5
1.4
3.1
1.25
2.7
ns
ns
Set-up time before clock K
Logic Variables A, B, C, D, E
Data In DI
Enable Clock EC
Reset Direct inactive RD
2
4
6
TICK
TDICK
TECCK
3.1
2.0
3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
1.5
1.0
2.05
1.0
ns
ns
ns
ns
Hold Time after clock K
Logic Variables A, B, C, D, E
Data In DI
Enable Clock EC
3
5
7
TCKI
TCKDI
TCKEC
0
1.0
1.0
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
0
0.7
0.55
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TCH
TCL
FCLK
2.4
2.4
188
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y 13
9TRPW
TRIO 3.8 4.4 3.2 3.7 2.7 3.1 2.3 2.7 2.3 2.4 2.05 2.15 ns
ns
Global Reset (RESET Pad)1
RESET width (Low) (XC3142A)
delay from RESET pad to outputs X or Y TMRW
TMRQ 14.0 17.0 14.0 14.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 ns
ns
Prelim
June 1, 1996 (Version 4.1) 4-361
XC3100A CLB Switching Characteristics Guidelines (continued)
1TILO
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
8TCKO
X5424
13 T
T
RPW
9T
RIO
4TDICK
6TECCK
12 TCL
2TICK 3TCKI
11 TCH
5TCKDI
7TCKEC
XC3100A Field Programmable Gate Arrays
4-362 June 1, 1996 (Version 4.1)
XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
page XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configures as a user input.
Speed Grade -5 -4 -3 -2 -1 -09
Description Symbol Min Max Min Max Min Max Min Max Min Max Min Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q)
with latch transparent (XC3100A)
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
2.8
14.0
2.8
2.5
12.0
2.5
2.2
11.0
2.2
2.0
11.0
1.9
1.7
10.0
1.7
1.55
9.2
1.55
ns
ns
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3120A, XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
1T
PICK 10.9
11.0
11.2
11.5
12.0
10.6
10.7
11.0
11.2
11.6
9.4
9.5
9.7
9.9
10.3
8.9
9.0
9.2
9.4
9.8
8.0
8.1
8.3
8.5
8.9
7.2
7.3
7.5
7.7
8.1
ns
ns
ns
ns
ns
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same
(slew rate limited)
Output (O) to Pad (fast)
same
(slew-rate limited)
(XC3100A)
3-state to Pad
begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad
active and valid (fast) (XC3100A)
same
(slew -rate limited)
7
7
10
10
9
9
8
8
TOKPO
TOKPO
TOPF
TOPS
TTSHZ
TTSHZ
TTSON
TTSON
5.5
14.0
4.1
12.1
6.9
6.9
10.0
18.0
5.0
12.0
3.7
11.0
6.2
6.2
10.0
17.0
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
3.7
9.7
3.0
8.7
5.0
5.0
8.5
14.2
3.4
8.4
3.0
8.0
4.5
4.5
6.5
11.5
3.3
6.9
2.9
6.5
4.05
4.05
5.0
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
(XC3100A)
Output (O) to clock (OK) hold time 5
6TOOK
TOKO 5.0
04.5
03.6
03.2
02.9 ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TIOH
TIOL
FCLK
2.4
2.4
188
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
Global Reset Delays
RESET Pad to Registered In (Q)
(XC3142A)
(XC3190A)
RESET Pad to output pad (fast)
(slew-rate limited)
13
15
15
TRRI
TRPO
TRPO
18.0
29.5
24.0
32.0
15.0
25.5
20.0
27.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
14.4
21.0
17.0
21.0
ns
ns
ns
ns
Preliminary
June 1, 1996 (Version 4.1) 4-363
XC3100A IOB Switching Characteristics Guidelines (continued)
3TPID
I/O Block (I)
I/O Pad Input
I/O Clock (IK/OK)
I/O Block (RI)
RESET
I/O Block (O)
I/O Pad TS
I/O Pad Output
I/O Pad Output
(Direct)
I/O Pad Output
(Registered)
X5425
5TOOK
12 TIOL
1TPICK
11 TIOH
4TIKRI
15 TRPO
13 TRRI
6TOKO
9TTSHZ
10 TOP
7TOKPO
8TTSON
FLIP
FLOP
QD
R
SLEW
RATE PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
DQ
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IKOK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
XC3100A Field Programmable Gate Arrays
4-364 June 1, 1996 (Version 4.1)
Product Availability
Note: C = Commercial, TJ = 0° to +85°C I = Industrial, TJ = -40° to +100°C M = Military, TC = -55° to +125° C B = MIL-STD-883C Class B
Ordering Information
PINS 44 64 68 84 100 132 144 160 164 175 176 208 223
TYPE Plast.
PLCC Plast.
VQFP Plast.
PLCC Plast.
PLCC Ceram
PGA Plast.
PQFP Plast.
TQFP Plast.
VQFP
Top-
Brazed
CQFP
Plast.
PGA Ceram
PGA Plast.
TQFP Plast.
PQFP
Top-
Brazed
CQFP
Plast.
PGA Ceram
PGA Plast.
TQFP Plast.
PQFP Ceram
PGA
CODE PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3120/A
-5 C I C I C I C I
-4 C I C I C I C I
-3 C I C I C I C I
-2 C I C I C I C I
-1 CCCC
-09 CCCC
XC3130A
-5 C I C I C I C I C I C I C I
-4 C I C I C I C I C I C I C I
-3 C I C I C I C I C I C I C I
-2 C I C I C I C I C I C I C I
-1CCCCCC C
-09CCCCCC C
XC3142A
-5 C I C I M B C I C I MB C I C I M B C I
-4 C I C I C I C I C I C I C I
-3 C I C I C I C I C I C I C I
-2 C I C I C I C I C I C I C I
-1 CCC C CCC
-09 CCC C CCC
XC3164A
-5 C I C I C I C I C I
-4 C I C I C I C I C I
-3 C I C I C I C I C I
-2 C I C I C I C I C I
-1 C CCCC
-09 C CCCC
XC3190A
-5 C I C I M B C I C I M B C I C I
-4 C I C I C I C I C I C I
-3 C I C I C I C I C I C I
-2 C I C I C I C I C I C I
-1 C C CCCC
-09 C C CCCC
XC3195A
-5 C I C I M B C I C I M B C I C I M B
-4 C I C I C I C I C I C I
-3 C I C I C I C I C I C I
-2 C I C I C I C I C I C I
-1 C C CC CC
-09 C C CC CC
XC3130A-3PC44C
Example:
Device Type
Speed Grade Temperature Range
Number of Pins
Package Type
June 1, 1996 (Version 1.0) 4-365
Features
• Ultra-high-speed FPGA family with two members
- 50-85 MHz system clock rates
- 270 to 325 MHz guaranteed flip-flop toggle rates
- 2.2 to 2.7 ns logic delays
• 4 mA output sink current and 4 mA source current
• JEDEC compliant 3.3 V version of XC3100A FPGA
family
• The XC3100L is 100% architecture, pin-out and
bitstream compatible with the XC3000A, XC3000L and
XC3100A families
• Advanced, 0.6 µ TLM CMOS technology
• XC3100L combines the features of the XC3000L and
XC3100A families.
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Description
XC3100L is a performance-optimized relative of the
XC3000L and XC3100A families . While all f amilies are f oot-
print compatible, the XC3100L family extends the typical
system performance beyond 80 MHz.
The XC3100L family follows the XC4000 speed-grade
nomenclature, indicating device performance with a num-
ber that is based on the internal logic-block delay, in ns.
The XC3100L family offers the following enhancements
over the popular XC3000 family.
The XC3100L family has additional interconnect resources
to drive the I-inputs of TBUFs driving hor izontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more effi-
cient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3100L devices check the bit-
stream format f or stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
star ts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all out-
puts are turned on simultaneously. After star t-up, the slew
rate of the individual outputs is, as in all XC3000 families,
determined by the individual configuration option.
Any bitstream used to configure an XC3000, XC3000A,
XC3000L or XC3100A device, will configure the same-size
XC3100L device exactly the same way.
XC3100L
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0) Advance Product Specification
Device Max Logic
Gates Typical Gate
Range CLBs Array User I/Os
Max Flip-Flops Horizontal
Longlines Configuration
Data Bits
XC3142L 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784
XC3190L 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160
XC3100L Field Programmable Gate Arrays
4-366 June 1, 1996 (Version 1.0)
XC3100L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents . To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100L Operating Conditions
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right
to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V.
Operating conditions are guaranteed in the 3.0 – 3.6 V VCC range.
XC3100L DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA
configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current ma y not
exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC3190L.
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial 0°C to +85°C junction 3.0 3.6 V
VIH High-level input voltage 2.0 VCC + 0.3 V
VIL Low-level input voltage -0.3 0.8 V
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage (@ IOH = -4.0 mA, VCC min) 2.4 V
High-level output voltage (@ IOH = -100.0 µA, VCC min) VCC -0.2 V
VOL Low-level output voltage (@ IOH = 4.0 mA, VCC min) 0.40 V
Low-level output voltage (@ IOH = +100.0 µA, VCC min) 0.2 V
VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V
ICCO Quiescent FPGA supply current
Chip thresholds programmed as CMOS levels11.5 mA
IIL Input Leakage Current -10 +10 µA
CIN
Input capacitance, all packages except PGA175
(sample tested)
All pins except XTL1 and XTL2
XTL1 and XTL2 10
15 pF
pF
Input capacitance, PGA175
(sample tested)
All pins except XTL1 and XTL2
XTL1 and XTL2 15
20 pF
pF
IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) 0.02 0.17 mA
IRLL Horizontal long line pull-up (when selected) @ logic Low 0.20 2.80 mA
June 1, 1996 (Version 1.0) 4-367
XC3100L Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100L Global Buffer Switching Characteristics Guidelines
Notes: 1. Timing is based on the XC3142L, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid option for XC3100L devices.
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VIN Input voltage with respect to GND –0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
TJJunction temperature plastic +125 °C
Junction temperature ceramic +150 °C
Speed Grade -3 -2
Description Symbol Max Max Units
Global and Alternate Clock Distribution1
Either:Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
5.6
4.3
4.7
3.7
ns
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↑ to L.L. High with single pull-up resistor
TIO
TON
TPUS
3.1
4.2
11.4
3.1
4.2
11.4
ns
ns
ns
BIDI Bidirectional buffer delay TBIDI 1.0 0.9 ns
Advance
XC3100L Field Programmable Gate Arrays
4-368 June 1, 1996 (Version 1.0)
XC3100L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. The CLB K to Q delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data
In hold time requirement (TCKDI, #5) of any CLB on the same die.
2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).
Speed Grade -3 -2
Description Symbol Min Max Min Max Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y 1 TILO 2.7 2.2 ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
8T
CKO
TQLO
2.1
4.3
1.7
3.5
ns
ns
Set-up time before clock K
Logic Variables A, B, C, D, E
Data In DI
Enable Clock EC
Reset Direct Inactive RD
2
4
6
TICK
TDICK
TECCK
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
ns
ns
ns
ns
Hold Time after clock K
Logic Variables A, B, C, D, E
Data In DI
Enable Clock EC
3
5
7
TCKI
TCKDI
TCKEC
0
0.9
0.7
0
0.9
0.7
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12 TCH
TCL
FCLK
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y 13
9TRPW
TRIO
2.7 3.1 2.3 2.7 ns
ns
Global Reset (RESET Pad)
RESET width (Low) (XC3142L)
delay from RESET pad to outputs X or Y TMRW
TMRQ
12.0 12.0 12.0 12.0
ns
ns
Advance
June 1, 1996 (Version 1.0) 4-369
XC3100L CLB Switching Characteristics Guidelines (continued)
1TILO
CLB Output (X, Y)
(Combinatorial)
CLB Input (A,B,C,D,E)
CLB Clock
CLB Input
(Direct In)
CLB Input
(Enable Clock)
CLB Output
(Flip-Flop)
CLB Input
(Reset Direct)
CLB Output
(Flip-Flop)
8TCKO
X5424
13 T
T
RPW
9T
RIO
4TDICK
6TECCK
12 TCL
2TICK 3TCKI
11 TCH
5TCKDI
7TCKEC
XC3100L Field Programmable Gate Arrays
4-370 June 1, 1996 (Version 1.0)
XC3100L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many inter nal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
Speed Grade -3 -2
Description Symbol Min Max Min Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch (XC3100L)
transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
2.2
11.0
2.2
2.0
11.0
1.9
ns
ns
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time XC3142L
XC3190L
1T
PICK 9.5
9.9 9.0
9.4 ns
ns
Propagation Delays (Output)
Clock (OK) to Pad (fast)
same (slew rate limited)
Output (O) to Pad (fast)
same (slew-rate limited)(XC3100L)
3-state to Pad begin hi-Z (fast)
same (slew-rate limited)
3-state to Pad active and valid(fast)(XC3100L)
same (slew -rate limited)
7
7
10
10
9
9
8
8
TOKPOTOK
PO
TOPF
TOPF
TTSHZ
TTSHZ
TTSON
TTSON
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
ns
ns
ns
ns
ns
ns
ns
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time (XC3100L)
Output (O) to clock (OK) hold time 5
6TOOK
TOKO
4.0
03.6
0ns
ns
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
11
12 TIOH
TIOL
FTOG
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
Global Reset Delays
RESET Pad to Registered In (Q)
(XC3142L)
(XC3190L)
RESET Pad to output pad (fast)
(slew-rate limited)
13
15
15
TRRI
TRPO
TRPO
16.0
21.0
17.0
23.0
16.0
21.0
17.0
23.0
ns
ns
ns
ns
Advance
June 1, 1996 (Version 1.0) 4-371
XC3100L IOB Switching Characteristics Guidelines (continued)
3TPID
I/O Block (I)
I/O Pad Input
I/O Clock (IK/OK)
I/O Block (RI)
RESET
I/O Block (O)
I/O Pad TS
I/O Pad Output
I/O Pad Output
(Direct)
I/O Pad Output
(Registered)
X5425
5TOOK
12 TIOL
1TPICK
11 TIOH
4TIKRI
15 TRPO
13 TRRI
6TOKO
9TTSHZ
10 TOP
7TOKPO
8TTSON
FLIP
FLOP
QD
R
SLEW
RATE PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
DQ
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IKOK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
XC3100L Field Programmable Gate Arrays
4-372 June 1, 1996 (Version 1.0)
Product Availability
Note: C = Commercial, TJ = 0° to +85°C
Ordering Information
PINS 44 64 68 84 100
TYPE PLAST.
PLCC PLAST.
VQFP PLAST.
PLCC PLAST.
PLCC CERAM
PGA PLAST.
PQFP PLAST.
TQFP PLAST.
VQFP
TOP-
BRAZED
CQFP
CODE PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100
XC3142L -3 C C
-2 C C
XC3190L -3 C
-2 C
Adv.
PINS 132 144 160 164 175 176 208 223
TYPE PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP
TOP-
BRAZED
CQFP
PLAST.
PGA CERAM.
PGA PLAST.
TQFP PLAST.
PQFP CERAM.
PGA
CODE PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
XC3142L -3 C
-2 C
XC3190L -3 C C
-2 C C
Adv.
XC3142L-3PC84C
Example:
Device Type
Speed Grade Temperature Range
Number of Pins
Package Type
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
OTP FPGA Products
XC8100 FPGA Family
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Performance Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Estimating XC8100 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Programmable Cell (CLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Cascade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Global Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Input/Output Cell (IOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Pull-up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
IEEE 1149.1 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
3.3 V Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Metastability Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
XACTstep Series 8000 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
XC8100 Synthesis Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
XC8100 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
XC8100 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
XC8101 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
XC8103 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
XC8106 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
XC8109 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Package Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
OTP FPGA Products Table of Contents
June 1, 1996 (Version 1.0) 5-1
Features
• Synthesis-targeted sea-of-gates architecture
- Efficient results with top-down design
- Design without architecture knowledge
- Predictable pre-layout timing estimation
- Accurate back-annotation
- Very high routability
- ASIC design flow
• Fine-grain architecture
- High, predictable utilization: >95%
- TrueMap logic mapping
• Innovative programmable cell
- Combinatorial, synchronous, or three-state
- High logic utilization for all designs
• Family of devices: 1K-45K usable gates
- Same pinout as XC4000 and XC5200
- MicroVia™ antifuse technology
• Low power CMOS
• System features
- JTAG boundary scan
- Fast, wide internal decode
- On-chip three-state for internal bussing
- I/O drive = 24 mA; PCI drive compliant
- Slew-rate options to control ground bounce
- Modular clock/buffer resources
- 5 V, 3.3 V operation
• One-time programmable, single-chip solution
- Design security
- Xilinx and third party programmers
- Self-test logic for 100% testability
- Automatic post-programming test
•XACT
step
™ Series 8000 development system
- Xilinx unified design entry libraries
- Floorplanning, incremental design
- High-speed PowerMaze™ router
- PC: Windows 3.1/95/NT
- WS: Sparcstation, HP PA, RS6000
• Supported by XACT
step
Foundation Series
Description
The XC8100 family of field programmable gate arrays
(FPGAs) provides the same overall benefits as other Xilinx
FPGAs: fast time-to-market, reduced design risk, low
power, standard product av ailability, and the use of e xisting
design methodologies. It combines the density of mask
gate arrays with the flexibility of programmable logic.
The XC8100 family is targeted to be e xtremely efficient and
cost effective when using top-down, technology-indepen-
dent design methods. The XC8100 employs a new sea-of-
gates FPGA architecture. The basic cell is small and was
specifically architected for technology-independent design.
A new process, the Xilinx MicroVia technology, minimizes
the area taken up by the many interconnect elements used
in a fine-grain structure. Programmable interconnect ele-
ments are stacked ver tically between metal layers and are
above the logic cells, using significantly less area than
other programmable logic technologies. (Note that archi-
tectural diagrams in this data sheet do not necessarily
show this internal structure). The result is that XC8100
devices have ver y rich interconnect resources while main-
taining cost effectiveness. The XC8100 sea-of-gates archi-
tecture delivers high gate utilization, high routability, low
cost, and fast design cycles. For high speed, the MicroVia
antifuse has a typical on-resistance less than 50 Ω.
Like all true FPGAs, as shown in Figure 1, the XC8100
family consists of an array of logic cells and programmable
routing resources surrounded by a ring of I/O connections.
Unlike most FPGAs, which attempt to offer the “best” fixed
cell, the XC8100 logic cells are themselves prog rammable.
They can implement synchronous, combinatorial, or three-
state functions. This means the XC8100 software has the
flexibility to choose the best cell structure, depending on
the logic to be implemented. A design does not have to be
evaluated to see if it “fits”, but instead can be implemented
top-down.
Note: * Future product plans
XC8100 FPGA Family
June 1, 1996 (Version 1.0) Preliminary Product Specification
Table 1: Product Line
Product XC8100 XC8101 XC8103 XC8106 XC8109 XC8112* XC8116* XC8120*
Max Logic Gates 1K 2K 7K 13K 20K 27K 36K 45K
Typical Gate Range .6 - 1K 1K - 2K 3K - 7K 6K - 13K 9K - 20K 12K - 27K 16K - 36K 20K - 45K
Cells 192 384 1024 1728 2688 3744 4800 6144
Flip-Flops (Max) 96 192 512 864 1344 1872 2400 3072
I/O 32 72 128 168 192 248 280 320
XC8100 FPGA Family
5-2 June 1, 1996 (Version 1.0)
Compared to Xilinx XC2000, XC3000, or XC4000 FPGAs,
this architecture has many more cells, each with fewer
gates. It also has fewer preconfigured resources — for
example, no flip-flops in the logic cells or in the I/O cells.
Routing resources are abundant and there is a very large
ratio of interconnects to logic cell inputs and outputs. The
architecture’s objective is to achieve the highest gate utili-
zation and routability across a diverse set of applications.
Unlike Xilinx SRAM FPGAs , which are infinitely reprogr am-
mable, the XC8100 family is one-time programmable
(OTP). XC8100 devices use MicroVia process technology,
a combination of CMOS, a metal-to-metal antifuse and
three layers of metal. Programming is done by Xilinx or
third-par ty programmers, similar to OTP PLDs. There is no
need for configuration storage in the target application and
design security is very high.
The XC8100 design flow is exactly like that of an ASIC or
gate array. Designs are entered and simulated with third-
party CAE tools and then placed and routed by Xilinx
XACT
step
Series 8000 tools. A key f eature of the synthesis
design flow is that technology mapping occurs in the syn-
thesizer. All instance names, net names, and hierarchy in
the EDIF netlist from the synthesizer are maintained b y the
Series 8000 software. Every logic gate in the design corre-
sponds to a logic gate/CLC in the FPGA. Every net in the
design corresponds to a net in the FPGA. Therefore, this
information and the associated timings are available for
backannotation, simulation and debugging. Figure 2 shows
this mapping process – called TrueMap.
The XC8100 architecture maximizes the chance that a
design will be completed automatically. Because of the
architecture and new software written for it, device utiliza-
Viewer - count32.xb
Active Design
File View Highlight Preferences
X1Y4 add_11/U2/I2 (xnor 2)
Horizontal
Routing
IOC
Global
Clock
Net
GCK
Pin
Cursor
Location
O I0I1I2I3 Cell
X5980
Row Buffer
Figure 1: XC8100 Architecture in Viewer Window
June 1, 1996 (Version 1.0) 5-3
tion does not degrade when technology independent
design entry is used. Designs can be entered in HDLs with
little concern for the IC architecture. With the very high
probability of routing, different logic implementations can
be accurately evaluated before place and route.
The Series 8000 software allows user control, primarily for
maximizing the speed of the design. High level floorplan-
ning works with constraints based on hierarchical block
names. The fast PowerMaze router makes incremental
design easier. The router can route a fully-utilized XC8106
in less than one minute – in most cases in only seconds.
Applications
The XC8100 family is targeted at three primary applica-
tions:
1. High-lev el design language (HDL) using logic synthesis .
The architecture was developed to give very high gate
utilization and low cost when designs are entered with a
technology-independent methodology. Most synthesis
algorithms were originally designed for gate arrays, and
they are sub-optimal for the different architectures used
in FPGAs and complex PLDs. The XC8100 architecture
was specifically designed to fit the logic implementa-
tions that are produced by synthesis algorithms. During
development, architectural simulations were run using
actual synthesis products. The XC8100 programmable
cell and design library were chosen to give cost-eff ective
results when using logic synthesis. The XC8100 soft-
ware is very ASIC-like and gives accurate estimations
when synthesizing and evaluating architectural trade-
offs before place and route.
2. General logic applications, especially telecommunica-
tions and industrial control. The XC8100 offers high and
predictable utilization over a wide range of logic func-
tions. It can handle designs that are heavily synchro-
nous or heavily combinatorial. Since the architecture
delivers “usab le gates” irrespective of the target applica-
tion, designs can be quickly entered and results will be
predictable. There is no need to analyze the target
design for flip-flops, latches, three-states, etc., to deter-
mine how well the design “fits.”
XC8100 devices, especially the XC8100 and XC8101,
can also implement logic traditionally done in CPLDs,
with less than one-tenth the power.
3. Applications requiring a single-chip FPGA. These
include high security and fast initial pow er-up operation.
Security
The XC8100 offers a high level of security for designs that
are subject to reverse-engineering. The security strategy
includes the software, the IC architecture , and the process .
The XC8100 software automatically stores design informa-
tion (.xb file) in a compressed and encrypted file format. In
addition, there is an optional password capability that only
allows the design file to be used for programming, not for
viewing or writing or manipulating. In other w ords, the pass-
word-protected design file can be given out for device pro-
gramming while still maintaining security.
XC8100 devices receive programming information through
the JTAG (boundary scan) port and data registers. While
this information can be read back for factory testing pur-
poses, these JTAG instructions are not documented. The
user can program a bit which defeats the JTAG test/pro-
gramming readback instructions, thereby eliminating this
form of reverse engineering.
The third part of the security strategy involves the process.
The physical implementation of a design occurs by pro-
gramming the desired connection pattern. The connection
is formed by creating a metal filament through a layer of
amorphous silicon. Only a small percentage of the anti-
fuses are programmed. In a typical design in the XC8106,
about 2% of the approximately 700,000 antifuses will be
programmed. The functionality of the design can only be
copied by kno wing exactly which of the antifuses were pro-
grammed.
The antifuses are located between the second and third
layer of metal. This means that programmed and unpro-
grammed antifuses are covered by a layer of metal and a
protective passivation layer. It is impossible to distinguish
programmed antifuses from unprogrammed antifuses by
inspection of the top of the chip. Attempts to remove the
protection and metal layers will certainly result in damage
or removal of the conductive filament between the metal
layers.
Moreover, antifuses, whether programmed or unpro-
grammed, are difficult to distinguish from regular, perma-
nent connections between the second and third layers of
metal (vias). Note that this is different from a gate array,
where vias only exist where connections are intended. In
the XC8100, vias, programmed antifuses, and unpro-
grammed antifuses all exist simultaneously.
Another method of rev erse engineering is hot spot analysis,
which relies on distinguishing programmed from unpro-
grammed fuses by investigation of heat dissipation. Since
D Q Q
I4
n3
Clock
D
C
B
A
Logic
Design
n1
I1
I2
I3
X5776
I4I3I2I1
A
B
C
D
Clock
n3n2
n1
Q
Portion of
Physical
XC8100
Chip
Figure 2: TrueMap™ Logic Mappings
XC8100 FPGA Family
5-4 June 1, 1996 (Version 1.0)
the on-resistance of the programmed antifuses is very low,
the heat dissipation is very low also. This makes this tech-
nique useless for determination of the state of the antifuse.
Performance Overview
The XC8100 family has been benchmarked with many
actual customer designs running synchronous clock rates
of 20-40 MHz (-1 speed grade). The performance of any
design depends on the type of circuit implemented, includ-
ing the delay through the combinatorial and sequential logic
elements plus the delay in the interconnect routing.
Figure 3 shows some performance numbers for represen-
tative circuits , using w orst case timing par ameters . A rough
estimate of timing can be made by assuming 6 ns per logic
level. This includes 3 ns for the CLC delay and 3 ns for the
routing delays. More accurate estimations can be made
using the information in the next section.
*Advance Information
The XC8100 architecture and software are architected to
deliver the maximum device perfor mance when using syn-
thesis CAE tools. This is possible due to:
- CLC designed to fit synthesis algorithms
- predictable prelayout timing for accurate synthesis
- block-level hierarchical floorplanning
- buffer resources for high fanout nets or critical
signals
- flexible CLC - many flip-flops possible - allows
pipelining
- cascade
- High drive outputs specified for 50 pF
Estimating XC8100 Timing
Like an ASIC or FPGA, XC8100 circuit timings depend on
the actual layout (placement and routing) of the design.
XC8100 software calculates the timing using a very accu-
rate SPICE-like timing model. However, prior to layout
actual circuit performance can be estimated. This is done
automatically by synthesis tools using the XC8100 library
and can be done manually using information in this data
sheet.
Accurate timing estimates prior to place and route are nec-
essary when exploring a design space with synthesis tools.
This allows the synthesizer to make the proper speed/area
trade-offs without leaving the synthesis environment (i.e.
without going through a full place and route cycle). The tim-
ing estimates for the XC8100 architecture are accurate to
within 10% of the post place and route numbers. This high
correlation between pre- and post- timing numbers is a
result of the follo wing architecture and design flow f eatures:
• No logic mapping - the placed and routed design
matches the synthesized design netlist e xactly. There is
no technology mapping phase where logic gates from
the design netlist are mapped into different physical
gates on the chip.
• All cell delays are built into the synthesis library. This, in
conjunction with point 1, means that all cell delays used
in the synthesis tool are preserved in the final chip.
• The wire load model is well characterized. The
abundant routing in the architecture increases the
likelihood of direct routes between CLCs rather than
circuitous paths. This reduces the standard deviation of
the estimated versus actual net delays.
The timing for the XC8100 is modeled with two elements:
the cell delay and a fanout-dependent net delay (wireload
model). Cell delay timings for most of the primitive library
elements are shown in the AC Timing section of the data
sheet. For e xample, the data sheet shows four numbers for
the AND4 primitive. Worst-case numbers are worst-case
voltage, worst-case temperature, worst-case process, and
XC8100 Performance
Function -1 -3*
16-bit decoder from input pads
(delay from strobe)
(delay for full decode) 7.6
11.7 5.1
7.9 ns
ns
16-to-1 multiplexer 18.8 14.2 ns
16-bit loadable shift register 148 172 MHz
16-bit Johnson counter 109 161 MHz
16-bit prescaled counter 91 125 MHz
16-bit loadable counter 51 77 MHz
16-bit accumulator 28 41 MHz
Complexity
100
75
50
25
MHz
16-bit
Johnson
Counter 16-bit
Prescaled
Counter
16-bit
Loadable
Counter 16-bit
Accumulator
X5935
(-3)
(-1)
16-bit
Loadable
Shift
Register
125
150
175
200
Figure 3: Representative Circuit Performance
SOP3
XOR2
FD
net n63
X5810
AND8
I0
Figure 4: Example Path Delay Calculation
June 1, 1996 (Version 1.0) 5-5
worst-case falling or rising edge. Note that the XC8100
library has input-to-output numbers, both rising and falling
edges, for all pins. Synthesis software will automatically
take adv antage of the f astest pin if required, and schematic
users can do this manually.
Pre-layout net delays are modeled as a function of fanout
and can be estimated by using Table 2. Note that various
buffers, as explained later, can be used to limit the delay of
wide fanout nets.
For example, in Figure 4, net n63 has a fanout of 3, so the
estimated delay (-1 speed grade) from the I0 input of the
AND8 to the D input of FD is: 3.0 + 3 = 6.0 ns.
Architecture
Xilinx field-programmable gate arrays are comprised of
three major configurable elements: configurable cells,
input/output blocks and interconnections. The cells provide
the functional elements for constructing the design’s logic.
The I/O cells provide the interface between the package
pins and internal signal lines. The programmable intercon-
nect resources provide routing paths to connect the inputs
and outputs of the cells and I/O bloc ks onto the appropriate
nets. In the XC8100, user configuration is established by
one-time programming of MicroVia antifuses that deter-
mine the cell logic functions, I/O functions, and the inter-
connections.
Programmable Cell (CLC)
The XC8100 implements combinatorial and sequential
logic by configuring and interconnecting identical Config-
urable Logic Cells (CLC). Each CLC is equivalent to 3.25
“LSI-Logic gates.” This figure w as derived by synthesizing a
range of designs first to the XC8100, and then to an LSI
Logic library.
In order to allow the widest range of logic - combinatorial,
synchronous, and three-state - to map efficiently to the
XC8100 architecture, CLCs are internally programmable.
While this is also true of Xilinx SRAM FPGAs, other anti-
fuse FPGA architectures hav e fixed cell structures with only
programmable interconnect. A programmable cell ensures
that logic will more frequently fit efficiently into a cell. The
cell is programmable as to: input inversions, combinatorial
function choice, synchronous logic internal feedback path,
three-state, and cascade enable. The XC8100 software
automatically configures the cell based on the user’s
design netlist. The v ariety of building bloc ks means a higher
device utilization for a range of logic functions.
Figure 5 shows the different possible implementations of a
single CLC. Each CLC has four logic inputs plus a cascade
input, and one logic output plus a cascade output (cascade
not shown). The logic output has three-state control, and
each CLC is also connected to a global reset network.
Each of the four inputs can be configured as inverted or
non-inverted, so input signal inversions (“bubbling”) are
free and output bubbles don’t matter. Cells do not have to
be “w asted” as inv erters , which would lower the gate utiliza-
tion. Any input can be hardwired to logic zero or one.
Table 2: Pre-Layout Net Delays vs. Fanout
Fanout Net Delay (ns) (-1)
1 1.2
22
33
44
nn
O
I3
I2
I1
I0
SOP
O = I3 • I2 + I1 • I0
Q
D
G
D Latch
O
I3
I2
I1
I0
AND
O = I3 • I2 • I1 • I0
O
I
E
Three-State Logic
Combinatorial Logic
Programmable
Inversion
X5811
Note: Cascade not shown
Figure 5: Programmable Cell
XC8100 FPGA Family
5-6 June 1, 1996 (Version 1.0)
For combinatorial logic, the cell has two programmable
functions, AND or Sum-of-Products (SOP). Pairs of CLC
inputs are internally ANDed, and the two signals are then
combined in a circuit programmable as either an OR or an
AND gate. The SOP can also be considered a 2-input mul-
tiplexer, or a 2-input XOR and XNOR.
For synchronous logic, configuring the cell-internal feed-
back path makes any CLC a latch with D and G inputs (LD
primitive). When G is high, the latch is in the pass-through
state. Both inputs can be configured to be either activ e High
or active Low. A two-cell latch (LDC primitive) adds an
asynchronous CLR input. All latches are also controlled by
the global Reset signal.
The XC8100 software automatically combines two adjacent
latches through the Cascade connection to create a D-flip-
flop. One CLC is the master latch and the second is the
slave latch. The flip-flop has a global Reset which does not
involve user routing and also has an overriding asynchro-
nous Clear input (FDC primitive). It can also have an asyn-
chronous Preset input that overrides the D input (FDP
primitive). Note that neither the feedback connections of
both latches nor the master-slave connection use general
routing elements, or have programming elements in their
paths. This gives the flip-flops excellent speed and meta-
stability behavior. The XC8100 “semi-dedicated” flip-flops
combine performance with flexibility in utilization.
For three-state logic, one of the CLC inputs controls a tri-
state buffer in the output path (BUFE primitive). The Data
and Enable control inputs can be configured active High or
active Low. Combining the latch and three-state functions
gives a register file capability (LDE4 primitiv e) which can be
used to build FIFOs, see Figure 6.
Global Reset
A global reset signal is automatically distributed to each
CLC latch, and therefore each flip-flop. It is controlled inter-
nally by the GRST library primitive. It is activated automati-
cally on power-up. When active, the net presets all
asynchronous preset flip-flops (FDP primitive) and resets
all other flip-flops. In the case of the latches, the clear only
takes place when the latches are in the latching state. In
other words, reset does not affect the output in pass-
through mode. Global reset is typically complete within 100
ns. See AC timings.
Master Reset
A master reset of the chip is accomplished by pulling the
MR pin low. This star ts the power-on reset sequence, pre-
setting all asynchronous preset flip-flops (FDP) and reset-
ting all other flip-flops and latches. The master reset locks
out the device for several ms. See the AC timings. The pri-
mary use of the master reset is as part of a system, board
or module reset.
Cascade
Each CLC has a fifth input and second output for cascade.
The cascade inputs and outputs use dedicated routing to
the nearest cells, extending along an entire row. See
Figure 8. Combining two adjacent CLCs through their cas-
cade connection expands the functionality. For synchro-
nous logic, cascade is used to automatically b uild flip-flops,
as explained earlier. For combinatorial functions, the soft-
ware cascades CLCs to b uild the wider ANDs and SOPS in
the primitive library. Cascade can also be used (with
ANDCC and SOPCC primitives) to build functions like wide
decode and fast shift registers. The cascade connection
has several advantages over conventional routing:
• It is faster because it doesn’t need a programmable
element and it avoids the delay of the cell output driver.
• It has known timing.
• It does not consume any general routing resources.
Address Decoders
The cascade can be used to build wide decode functions.
See Figure 7. For example, five CLCs, each configured as
a four-input AND gate, can feed a CLC configured as a
four-input AND with cascade (ANDCX). The delay for this
20 input decoder is less than 12 ns. Using two-CLC AND8
primitives produces a for ty-input decoder that has a delay
less than 15 ns. If the address is av ailab le , the strobe delay
is about 8 ns (-1).
Programmable Interconnect
Most programmable logic devices have to balance routing/
interconnect resources with die size and cost. Howe v er , the
XC8100 architecture offers a small die size with an abun-
dant amount of routing, both metal-segment wires and
interconnections. The routing software has many alterna-
tives to make sure a design is fully routed.
Figure 8 is an example diagram of the interconnect, show-
ing only the wires actually used for nets in a design. In the
horizontal direction, there are 47 wires that each cell can
connect to (not all shown in Figure 8). There are 5 separate
types, three of which can also be connected horizontally:
G
D3
D2
D1
D0
E
Q3
Q2
Q1
Q0
LDE4 X5632
Figure 6: Quad Latch Bank with Three-State Output
Uses Four CLCs
June 1, 1996 (Version 1.0) 5-7
• single-bloc k (a bloc k is 4 cells wide) length wires e xtend
for one block only. They are used primarily to connect
the cells within the block.
• double-block length wires connect left and right to
adjacent blocks.
• quad-block length wires connect left and right for a
length of four blocks. They can connect any cells that
are spanned within the four-block length.
• horizontal long lines run the entire width of the device.
They can connect any cells in a row. These wires are
optionally used by the row buffers.
• constant 0 used for logic 0 and 1 inputs.
There are two wire types in the vertical direction:
• double-block length wires, analogous to the horizontal
ones.
• quad-block length wires.
In addition to the wires that run along all the rows and col-
umns of the device, there are twelve vertical long lines
(VLLs) on each side of the device. They interconnect with
any horizontal wire and mak e routing with preassigned I/Os
easier.
Global Nets
Global nets are those needing optimized timing or low sk ew
for the distribution of clock, time-critical and/or high fan-out
control signals. The XC8100 has dedicated hardware
resources for this purpose. The XC8100 system is very
flexible since the various buffers can be used indepen-
dently or together , for clocks or data. See Table 3, Figure 9,
and Figure 10. Four pac kage pins, GCK1-4, f eed four dedi-
cated high drive buffers (BUFEDGE) that drive four vertical
long lines (not part of the general lines described in the
Programmable Interconnect section) on two sides of the
device. If the GCK pins are not used, they are available for
user I/O . Each pair of rows of CLCs also has f our dedicated
buffers (BUFROW). To limit fanout, the XC8100 software
can also use CLCs as buffers (BUF1X primitive). These
buff ers can be automatically selected b y the synthesis soft-
ware.
ANDXC
X5812
AND4B1
AND4
AND4
ANDCXB1
IBUF
IBUF
Strobe
Address
Bit
Address
Bits
ANDXC
AND4B1
AND4
AND4B2
AND4
6 CLCs
ANDCX
AND8
AND8
AND8
AND8
AND8
11 CLCs
ANDCX
8
8
8
8
8
Net uses
cascade
Figure 7: Wide Decode Using Cascade
X5813
Vertical Routing
Horizontal
Routing
Cascade
Clock Net
CLC
III OI IIII IIII III OO
IIII IIIIO IIIIO IIIIO
CLC CLC CLC
CLC CLC CLC CLC
Cascade
Figure 8: Example Routing Detail
XC8100 FPGA Family
5-8 June 1, 1996 (Version 1.0)
Table 3: XC8100 Buffers
Name Description
BUFGP
BUFGS
BUF1X
BUFROW
This global buffer is formed by a BUFEDGE driving some number of BUFROWs. The source for this buffer is
one of four specific external pins, GCK1 - 4. The output of the buffer can drive all CLCs in a chip. The maximum
number of BUFGP buffers is four.
This can be thought of as an internal BUFGP. It is accessible internally and can drive any number of
BUFROWs.
This buffer is formed by using a single CLC. It has the same drive and fanout characteristics as the CLC. It can
be automatically selected by synthesis tools to limit fanout in critical paths.
This is a dedicated high drive buffer whose output drives all CLCs in the driven row. The input to this buffer is
from a CLC or from external pads through IBUF cells. Using this buffer automatically constrains the placement
of the driven CLCs to the row. Each BUFROW drives two rows of CLC/FFs:
XC8100 48 CLCs (24 FFs)
XC8101 48 CLCs (24 FFs)
XC8103 64 CLCs (32 FFs)
XC8106 96 CLCs (48 FFs)
XC8109 112 CLCs (56 FFs)
CLC
BUFROWs
CLC
X5623
BUFROWs
BUFROWs BUFROWs
BUFEDGE BUFEDGE
BUFEDGE BUFEDGE GCK
Pin
GCK
Pin
GCK
Pin GCK
Pin
Figure 9: XC8100 Buffer Configurations
June 1, 1996 (Version 1.0) 5-9
Input/Output Cell (IOC)
The IOCs form the interface between the internal logic and
the I/O pads of the device. Each IOC consist of a program-
mable output section that drives the pad, and a program-
mable input section that receives data from the pad. See
Figure 11. Aside from being connected to the same pad,
the input and output sections hav e nothing else in common.
Input
The input section receives data from the pad or the JTAG
circuitry and passes it to the interconnect str ucture. Inputs
can be globally programmed f or TTL or CMOS input thresh-
olds. TTL is the default. There are two input buffer timing
specifications. The faster one is selected b y using the IBUF
library element, while a delayed timing is available with the
DBUF library element. The DBUF is used f or the data signal
to guarantee zero hold time if data and clock signals are
going from external pins to an internal flip-flop.
BUFGP Global Buffer
BUFROW Row Buffer
IBUF
GCK
There are four BUFGP buffers in each XC8100 device. They are only driven by the four external 
GCK pins. BUFGP is the low-skew global clock driver, and should be used for any high-fanout net, 
as it can connect to all input pins on all CLCs. To use the BUFGP, either add the BUFGP symbol to 
your schematic, instantiate the BUFGP primitive in your HDL code, or see the XACT
step
Series 8000 
User Guide for information on directing synthesis tools to automatically include the BUFGP.
There are four BUFROW buffers for every two rows of CLCs, two on each end. The BUFROW can only drive the inputs of
CLCs in the two rows adjacent to the BUFROW. Any CLC in any row can drive the input to the BUFROW. Using the BUFROWs 
as individual clock drivers allows more than four different clocks in a design. The above figure shows two BUFROW examples; 
one BUFROW driven by an IBUF input buffer, the other BUFROW driven by an internal CLC.
BUFGS Secondary Global Buffer
BUFGS is a library primitive that utilizes BUFROWs to form a global low-skew driver. The BUFGS can drive any number of 
CLCs, since it uses a BUFROW to drive the CLCs in each row. If there are no driven CLCs in a row, then no BUFROW is used 
in that row. Like the BUFROW, the BUFGS can be driven by a CLC (shown above) or by an IBUF input buffer.
X5936
O
O
Figure 10: XC8100 Buffer Usage
XC8100 FPGA Family
5-10 June 1, 1996 (Version 1.0)
Pull-up Resistor
Each I/O pad can be programmed with or without a pull-up
resistor. This selection is independent of the IOC usage.
The default is for the software to automatically program the
pull-up resistor to prevent a floating input. The pullup is
about 50K ohms.
Output
The output section takes data and three-state control infor-
mation from the interconnect structure. It can also tak e data
from the JTAG scan circuitry. Output data can be inverted
or non-inverted.
The output driver has f our options: 1) it can be permanently
disabled, making the pad an input-only pad (IBUF, DBUF
primitives); 2) the driv er can be permanently active, making
the pad output only (OBUF, RBUF primitives); 3) it can be
three-state controlled from either the internal logic or the
JTAG circuitry (OBUFE, RBUFE primitives): or 4) a combi-
nation (IOBUF). The three-state control signal can be
inverted, allowing the signal to be thought of as either
active Low Output Enable, or active Low three-state. The
outputs are CMOS compatible, which results in an
unloaded rail-to-rail signal swing. Each output can be indi-
vidually configured for either of tw o slew-rate options , which
affect only the pull-down operation. See Figure 12.
When programmed for resistive mode (RBUF, RBUFE
primitives), the pull-down tr ansistor is driven hard, resulting
in a practically constant on-resistance of < 20 Ω. This
results in the fastest High-to-Low transition, and the capa-
bility to sink up to 24 mA. Resistive mode is required for
driving terminated transmission lines with 4 to 24 mA of dc
sink current and for highly capacitive loads (>200 pF).
When many resistive mode outputs switch simultaneously
High to Low, this configuration option may result in exces-
sive ground bounce. The user must limit the number of
simultaneous transitions per package ground pin - see the
DC specification section.
The slew rate limited configuration is capacitive mode
(OBUF, OBUFE). This mode uses a novel, patent-pending
method of slew rate control that reduces ground bounce
without any significant delay penalty. The High-to-Low tran-
sition starts as described above, but the drive to the pull-
down transistor is reduced as soon as the output voltage
reaches a value around 1V. This results in a higher resis-
tance in the pull-down transistor, a slowing down of the fall-
ing edge, and significantly reduced ground bounce. In this
mode the output driver sinks 4 mA at V OL. This mode is rec-
ommended for outputs requiring less than 4 mA DC or for
capacitive loads of less than 200 pF. See Figure 13 for typ-
ical output V/I characteristics.
I - Capture
I - Update
JTAG
Input Data I
X5775
V
CC
Slew
Rate
INTEST/
EXTEST
3-State TS TS/OE
O - Update
Output Data O
O - Capture
JTAG
TS - Update
TS - Capture
JTAG
Pull
Up
CMOS/TTL
Input
Buffer
ESD
ESD
PAD
OUTPUT
INPUT
Programmable
Inversion
Programmable
Inversion
CMOS
Output
Buffer
Resistive/capacitive modes
selectable on a pin basis
Globally selectable
Figure 11: Input/Output Cell Diagram
June 1, 1996 (Version 1.0) 5-11
IEEE 1149.1 Boundary Scan
The XC8100 has similar IEEE 1149.1/JTAG (Joint Test
Action Group) capabilities as the XC4000. Three differ-
ences are that:
• The XC8100 JTAG pins TDI, TDO, TMS and TCK are
dedicated.
• The XC8100 supports the JTAG instruction IDCODE.
• The XC8100 instruction word length is 10 bits.
JTAG is an industry-standard serial access interface
designed to provide an efficient and convenient means of
testing and monitoring integrated circuit components on a
circuit board. It was designed to provide an alternative to
the traditional bed-of-nails circuit board testers which have
difficulty accommodating high pin count, fine pitch compo-
nent packages, and which are unable to support surface
mount boards with components on both sides. In the
XC8100, the JTAG interface both serves its traditional
board testing role and is also the primar y test and antifuse
programming interface. Virtually all factory test and pro-
gramming operations are accessed via the JTAG interface.
The 1149.1 interface consists of four pins, TDI, TDO, TCK,
and TMS. The basic concept is that the TDI and TDO pins
form the beginning and end of serial shift registers within
the device. See Figure 14. TCK and TMS provide a means
to select a specific shift register and when and what to shift.
In order to provide control of the JTAG data registers, the
JTAG specification includes a definition of what is called the
test access por t (TAP) controller. Since there are only two
pins to control it, the TAP controller is designed as a state
machine with one input, TMS. The XC8100 TAP controller is
clocked by the TMS pin and uses the standard IEEE JTAG
state diagram.The XC8100 provides the full set of IEEE
1149.1 boundary scan instructions, including the optional
IDCODE. See the following Table:
INTEST/EXTEST
This instruction combines the mandatory JTAG EXTEST
with the optional INTEST instruction. When selected, this
instruction uses the JTAG boundary scan register values to:
• Drive the signal at the output of the input buffer
(INTEST)
• Drive the data input of the output buffer (EXTEST)
• Drive the enable input of the output buffer (EXTEST)
To do this, the signals which normally drive these nodes are
disabled via multiplexers.
SAMPLE
This instruction samples the logic values at each pin. For a
bidirectional I/O pin, three values are sampled:
• The signal at the output of the input buffer
• The signal at the data input of the output buffer
• The signal at the enable input of the output buffer
IDCODE
This instruction provides access to a 32-bit data register
that alwa ys captures a 32-bit w ord b uilt into the device. The
register can be read by the programming software. See
Figure 15.
Resistive Mode
“Sharp Pull Down”
4 mA < IOUT (DC) < 24 mA
VCC
TR>TC
0.5 V
Gnd
VOLmax
TRt
Capacitive Mode
“SoftEdge”
IOUT (DC) < 4 mA
VCC
0.5 V
Gnd
VOLmax
TC
t
X5814
RBUF, RBUFE, IRBUF, DRBUF OBUF, OBUFE, IOBUF, DOBUF
Figure 12: Output Slew Rate Options
4.5 V, 90°C, 1 Output
0.1 VOL
X5777
10
20
30
40
50
60
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Volts
IOL
mA
Resistive
Mode
Capacitive
Mode
4.5 V, 90°C, 1 Output
3.0 VOH
10
20
30
40
3.5 4.0
Volts
IOH
mA
Figure 13: Typical Output V/I Characteristics
Instruction Code Instruction Description
0000000000 INTEST/
EXTEST Forces state of I/O cells
0000000001 SAMPLE Samples state of I/O cells
1111111101 USERCODE User-programmable register
1111111110 IDCODE Samples existing device code
1111111111 BYPASS Selects bypass register
XC8100 FPGA Family
5-12 June 1, 1996 (Version 1.0)
In hex, the IDCODEs are:
XC8100 — X7E90093
XC8101 1X X7E94093
XC8101 2X X7E95093
XC8103 1X X7E9C093
XC8103 2X X7E9D093
XC8106 1X X7EA8093
XC8106 2X X7EA9093
XC8109 2X X7B58093
USERCODE
This instruction provides access to a 32-bit data register
which can be programmed b y the user , for e xample with the
design version.
BYPASS
This instruction places a single flip-flop between TDI and
TDO. Its capture value is 0.
The Boundary Scan Register bits are shown in the pinout
tables (The pinout tab les section begins on page 25). There
are three bits for each I/O pin. The bits are TS, O, and I, as
shown in Figure 11, with TS closest to the TDO end. There
is a fourth bit for the four GCK/I/O pins.
Power Consumption
The XC8100 has the power consumption characteristics of
Xilinx CMOS FPGAs. There are two components to the
power. DC quiescent power is low and almost all of the
power dissipation is a function of the design speed, the
number of nodes toggling, and the capacitive loading on
the outputs.
Quiescent current can be minimized by attention to its six
sources:
1. Using the TTL input voltage mode draws current of
about 8 mA to 30 mA, worst case, depending on the
device, the package, and the voltage state of the input
pins. There are two components to this current. First, the
reference circuit draws 8 mA worst case, 4 mA typical,
independent of device. Second, each I/O pin will draw
about 100 µA worst-case if the input to the pin is held at
DC low. Therefore this component depends on the cir-
cuit and the package (number of I/Os available). Both
components are eliminated by selecting CMOS input
lev els (2.2 V trip point). At 3.3 V operation, the input le vel
must be CMOS, so this source of current is not applica-
ble.
2. Pulling down an I/O pin with the weak pull-up transistor
enabled draws about 50 µA per pin at 3.3 V, 100 µA per
pin at 5 V. The weak I/O pull-ups are automatically
enabled b y the design softw are (although the y are auto-
matically turned off when an I/O is driv en b y the FPGA).
They can be disab led within the Series 8000 software by
the command: set_attribute -port
my_input_pin
pullup
false.
3. Leaving a non-pulled up I/O pin floating can produce a
worst-case current of about 0.5 mA per pin at 3.3 V, 1mA
per pin at 5 V. This occurs when the input voltage is at
the I/O trip point. To eliminate this source of quiescent
current, do not allow non-pulled up pins to float.
Remember the default is that all I/Os have pull-ups. The
JTAG TCK pin, which by the IEEE specification may not
have a pullup or pulldown, m ust be connected to VCC or
GND to eliminate it as a source of quiescent current.
4. MicroVia leakage current depends on the design and is
not under user control. It is typically very small and can
be calculated after the design is placed and routed.
Series 8000 software has a command (report -
Instruction Register (10 bits)
X5626
TAP Controller
Bypass Register (1 bit)
User Code Register (32 bits)
ID Code Register (32 bits)
Boundary Scan Register
TCK
TMS
Test/Programming Registers
TDI TDO
MUX
Figure 14: XC8100 IEEE 1149.1 Architecture
MSB
Family
Code
X X X X
Version
0 1 1 1 1 1 1 0 1 0 1 0 1 0
Part
Number
0 0
Manufacturer
ID
0 0 0 0 1 0 0 1 0 0 1
31
LSB
28 27 14 13 12 11 10
1
X7EA 0 93
8,106X 0 Xilinx = 147
X5633
Figure 15: XC89106 IDCODE Register
June 1, 1996 (Version 1.0) 5-13
stress_factor) that shows the number of antifuses to be
programmed in the design and the number of “critical”
antifuses. Critical antifuses are those which have the
potential of being between two active and different nets.
Only these antifuses can contribute to quiescent cur-
rent. The worst-case theoretical MicroVia leakage cur-
rent, assuming all critical antifuses have opposite logic
potential on their terminals, is calculated by multiplying
each critical antifuse by 100 pA at 3.3 V, 10 nA at 5 V. On
small designs (XC8100, XC8101) this number is typi-
cally less than a few hundred µA, worst case tempera-
ture and 5.25 V. At room temperature, 5.0 V, the
MicroVia leakage would be about an order of magnitude
less.
5. CMOS leakage current is proportional to the device and
is not under user control. It is typically a few µA. Current
(May 96) test limits are a few mA for the XC8106 at 5 V
with other devices proportionally less or more.
6. A small current is used by an internal voltage detector
on the VPP pin. With VPP tied to VCC, this current is
about 100 µA at 5 V, 30 µA at 3.3 V. A larger current
exists if VPP is tied to ground. A minor enhancement is
scheduled for 2H 1996 to eliminate this source of cur-
rent.
Attention to these factors can result in a typical quiescent
current of a few µAs for small designs at 3.3 V.
Almost all power is dynamic , and is determined by the num-
ber of nodes, their capacitance, and the frequency the y are
discharging and charging. This number is very design
dependent, especially on the number and frequency of
inputs that are toggling, not just the circuit implementation
in the FPGA.
Figure 16 is a test design that illustrates the power con-
sumption of an XC8106 at 5 V and 3.3 V. The design uses
1550 CLCs (90% of the XC8106), with 10% sequential
logic and 90% combinational. All outputs are unloaded. The
design consists of a 16-bit counter, a 16-bit 4-to-1 MUX,
and a 16-bit multiplier . The select lines , by controlling one of
the multiplier inputs, determine the number of nodes that
switch.
3.3 V Operation
XC8100 devices can be oper ated at 5 V or 3.3 V. At 3.3, the
timing parameters are derated (see “De vice Specifications”
on page 33). I/O pins cannot be directly driven above VCC,
although there are standard resistor solutions. The CMOS/
TTL input voltage choice should be set in the software to
CMOS.
Programming
Programming XC8100 FPGAs is supported by several
methods: 1) the Xilinx HW-130 Programmer; 2) selected
third-party programmers; 3) distributors; and 4) Xilinx for
volume designs. Series 8000 software has a Demo Mode
where no key is needed. The software can be copied for
programming XC8100 devices in parallel using multiple
PCs or workstations. Another option is to run multiple Win-
dows 95 sessions to multiple serial ports.
On the device , only 5 pins are required for the prog ramming
interface. The JTAG pins TDI, TDO, TCK, and TMS are
used for addressing the elements to be programmed, for
shifting the programming data in, for verification, and for
testing. The Vpp pin provides a high voltage during pro-
gramming and is used to measure the resistance of the pro-
grammed antifuse.
0
0
50
100
150
200
250
300
350
10 20 30 40
Frequency (MHz)
Current (mA)
Sel-00
Sel-01 Sel-10
Sel-11
X5839
0
0
20
40
60
80
100
120
140
51015 30
Frequency (MHz)
Current (mA)
Sel-00
Sel-01 Sel-10
Sel-11
20 25
XC8106 5.0 V Current Consumption
XC8106 3.3 V Current Consumption
32
Output
Clk
Clk
(15:0)
*
(15:0)
(0:15)
Sel
0002
FFFF
32
16
11
10
01
00
+1
16
32
Figure 16: XC8106 Example Design
XC8100 FPGA Family
5-14 June 1, 1996 (Version 1.0)
The programming algorithm includes measuring the resis-
tance of the programmed MicroVia antifuse to guarantee
the speed and functionality of the part. Since this is the one
aspect that cannot be verified during factory test, it com-
pletes the 100% functional testing of the device.
There are several unique capabilities in the XC8100 pro-
gramming architecture. They are aimed at addressing the
issues of accurate programming and 100% post-program-
ming yield. Series 8000 programming software takes
advantage of a unique XC8100 f eature that each and e v ery
antifuse can be randomly addressed. The capabilities
include:
• Series 8000 software can run a complete functional
factory test on an unprogrammed part in a programmer
using the JTAG port. Figure 17 is a screen shot of the
Series 8000 software running the test suite on an
unprogrammed device
• As noted above, during programming the actual
resistance of each programmed fuse is measured;
• To guarantee post-programming yield, after
programming all nets are checked to see that only
intended nets have been programmed, i.e. no
unintended antifuses have been programmed. This is
done without user test vectors;
• While these capabilities ensure that XC8100 devices
are 100% testable without v ectors, it is possib le to apply
post-programming test vectors using the programmer
hardware. The XC8100 software can take simulation
vectors and apply them to the device and read back the
results through the JTAG port.
Series 8000 Design System
File Edit Place/Route Analysis Program Help
Design (unnamed) Part: XC8106PC84
Initializing design data-base for 36 rows by 48 columns...
cmd> factory_test_suite
Requesting programmer on serial port /dev/ttya, 19200 baud...
Found HW-130
Running factory tests...
Power-up Current Test:
ID Code Power-Up Test:
ID Code Test:
Metal Data Register Test:
Metal Test:
VP Line Short Test:
CCU Loop Test:
CCU Chain Test:
CCU Capture Test:
Constant Zero Test:
TTL Bit Test:
Boundary Scan Test:
Row Buffer Test:
Edge Buffer Test:
Intest-In Test:
Output Test:
Input Test:
PROM Test:
CLC Test sop4 61 00 0:
CLC Test sop4 61 03 1:
CLC Test sop4 61 0a 0:
CLC Test sop4 61 0c 1:
CLC Test sop4 61 05 0:
CLC Test sop4 61 0f 1:
CLC Test and4 21 00 0:
CLC Test and4 21 01 0:
CLC Test and4 21 03 0:
CLC Test and4 21 07 0:
CLC Test and4 21 0f 1:
CLC Test and4b1a 31 01 0:
CLC Test and4b1a 31 0e 1:
CLC Test and4b1b 29 02 0:
CLC Test and4b1b 29 0d 1:
CLC Test and4b1c 25 04 0:
CLC Test and4b1c 25 0b 1:
CLC Test and4b1d 23 08 0:
CLC Test and4b1d 23 07 1:
Summary of test results:
X5937
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
Passed
cmd>
Placement Routing Timing
Figure 17: Series 8000 Software Testing a Device in an HW-130
June 1, 1996 (Version 1.0) 5-15
Testing
The functionality of gate arrays and older one-time pro-
grammable (OTP) PLDs has to be v erified with test vectors
after personalization. Even then, fault coverage is often
below the standards of off-the-shelf devices. XC8100
FPGAs address this problem through the following:
• An architecture designed for testability.
• The use of extensive on-chip test circuitry.
• A novel method of post-programming net verification.
The test circuitry is used in conjunction with a set of special
test instructions which are written to the dedicated JTAG
port. This circuitry allows each device function — except
the actual antifuses to be programmed — to be separately
isolated and 100% tested before shipping. The pro-
grammed antifuses are later verified by the programmer.
The result is the XC8100 family achieves the 100% tested
level of Xilinx SRAM-based reprogrammable devices.
In concept, XC8100 FPGAs are tested in four stages. The
first three are done at the factory before programming, the
last by the programming hardware. First, both the function-
ality and speed performance of all CMOS logic on the
device are v erified. This includes programming circuitry, the
CLC logic, the IOC logic, and the long line and clock buff-
ers. The inputs and outputs of all the internal logic are
accessible for 100% testing. Second, all metal interconnect
lines are tested. Special patented circuitr y allows all metal
lines to be accessible. Third, all antifuses are stressed and
tested to be in the correct state (off) before programming.
Fourth, during programming the programmer checks that
all interconnect elements meet their resistance specifica-
tion after programming. The current through each pro-
grammed antifuse is measured so that the resistance
meets the speed specification. Moreov er , all nets are tested
to ensure no antifuses have been inadvertently pro-
grammed.
Metastability Calculation
Whenever a clocked flip-flop synchronizes an asynchro-
nous input, there is a small probability that the flip-flop will
exhibit an unpredictab le cloc k-to-Q dela y. This occurs when
the input transition not only violates the setup and hold time
specifications, b ut actually occurs within the tiny timing win-
dow where the flip-flop accepts the new input. This results
in the flip-flop’ s output being betw een a logic zero and logic
one – a “metastable” state. The time required to transition
from the metastable state to a valid logic one or zero is the
delay. The Mean Time Between Failure (MTBF) for meta-
stability is defined statistically. Figure 19 sho ws the data for
the XC8100 using a 1 MHz data rate and a 10 MHz clock.
The XC8100 offers two options in designing for metastabil-
ity. The standard XC8100 flip-flops (FD, FDC, FDP) provide
MTBFs that are in the range of programmab le logic de vices
today. An additional option is the four-CLC, double-syn-
chronized versions of the flip-flop elements, (FD_SYNC),
which automatically use two flip-flops connected through
cascade. This option has one additional clock cycle of
latency. This may make sense for certain signals given the
large number of CLCs/FFs on XC8100 FPGAs. Figure 19
shows that for these flip-flops, a delay of 3 ns has a MTBF
over 100 years.
ICC Max 
Test
Continuity-
I/O Opens and Shorts
Device ID
Check
Metal Test
X5815
I/O
Leakage Test
CLC Test
Verify All CLC Functions
Fuse Stress and Test
Verify All Antifuses Are Open
Serpentine Test For
All Interconnect Lines
I/O Functionality Test
Boundary Scan, R/C Output Modes,
DC Specifications:
VOH, VOL, VIH, VIL
Clock Buffer Test
Row Buffers, Edge Buffers
Speed Test
Figure 18: XC8100 F actory Test Flow Chart Used f or
the Factory Test of all XC8100 FPGAs
XC8100 FPGA Family
5-16 June 1, 1996 (Version 1.0)
XACT
step
Series 8000 Development
System
The XC8100 development system, part of the Xilinx XACT-
step system, employs many new features to take advan-
tage of the new architecture:
• command shell and unified database structure
• new placement and routing software
• ASIC-like design flow
• 1-to-1 mapping between input netlist and CLCs in the
device: TrueMap Logic
• maintains hierarchical information throughout the
design flow
• maintains original net and instance names throughout
the flow
• EDIF and SDF for CAE tool interfacing
Similar to other Xilinx FPGAs, the XC8100 FPGA design
flow is based on a four-step process:
1. Design entry and functional verification using standard
CAE tools.
2. Design implementation using XC8100 tools.
3. Design verification using standard CAE tools.
4. For the XC8100, programming is the fourth step.
Design Entry
The design is first described using a variety of methods:
Verilog, VHDL, schematic, equations, or state machine.
The designer uses standard CAE tools in this phase — Xil-
inx supplies a design kit (synthesis models, schematic
library) for the third-party CAE vendor’s tool. Some CAE
vendors supply the design kit themselves. The flexibility of
the XC8100 architecture means that the user can design
with little concern for the architecture or implementation
details. In most cases, the software automatically chooses
all the capabilities described in the Architecture section.
Design Implementation
The second step in the process takes an EDIF netlist output
from the design entry stage and:
• reads the design netlist, including hierarchy.
• places the netlist primitives on specific CLCs without
changing any of the logic. This insures a 1-1
correspondence between design and implementation.
• routes all nets. The router uses rip-up-and-retry
algorithms to shift congestion.
• calculates actual timing delays for all nets. This
information is used f or timing analysis and by third party
timing/simulation tools.
• shows a view of the design at the physical level.
Figure 21 is an output of the Vie wer, showing the dense
routing used to implement a 6502 VHDL model in an
XC8106.
• generates fusemap and files for the programmer
hardware.
Design Verification
The third step lets the designer use third-party CAE tools
for analysis or simulation of the timings exported by
Series 8000 software.
Programming
All programming software is included in XACT
step
Series
8000. The software connects to the programmer hardware
through a serial port.
Platforms
The XC8100 software runs under Windows 3.1, Windows
95, Windows NT, SunOS 4.1.1 or later, Solaris 2.4 or later,
HPUX 9.05 or later, and AIX 3.2 or later. Platforms include
PC, Sparcstation, HP PA, and RS6000.
Workstation General Requirements
- minimum 32 MB of memory
- hard disk with at least 40 MB available for XC8100
programs, symbol libraries and data files
- minimum swap space of 100 MB
- color console monitor (any text terminal is sufficient
when using only the XC8100 command shell)
- two or three-button mouse (no mouse is required
when using only XC8100 command shell)
- postscript printer such as the Apple Laser Writer II
Sun Sparcstation
- SunOS 4.1.1 or later, Solaris 2.4 or later
- access to CD ROM drive
- Motif Window Manager or OpenLook Window
2468
101
102
103
104
105
106
107
108
109
1010
1011
1 Hour
1 Day
1 Month
1 Year
1000 Years
fDATA = 1 MHz
fCLOCK = 10 MHz
(ns)
(seconds)
MTBF
X5779
1012
1013
1014
10
FD, FDC, FDP
Double-synchronized
FD_SYNC
Figure 19: Metastable MTBF
June 1, 1996 (Version 1.0) 5-17
HP PA series
- access to CD ROM drive
- HPUX 9.0 or later
- HP VUE 3.0 or later
RS 6000 series
- access to CD ROM drive
- AIX 3.2 or later
IBM Compatible PC’s
- Run on 386 or 486, Pentium recommended
- 8 MB RAM (small designs), 16 MB recommended
- hard disk space varies with the selected installation:
8 MB min, 13 MB typ, and 57 MB full
- color monitor capable of running in VGA mode or
better
- two or three button Windows-compatible mouse
- Windows driver program for graphics adapter and
display
- access to CD ROM drive
HW-130 Programmer
- PC or workstation serial port
XC8100 FPGA Family
5-18 June 1, 1996 (Version 1.0)
Simulator Placement
& Routing
Timing
Analysis
Programming
Synthesis
Speed/Area
Constraints
Verilog/
VHDL
Series 8000 EDIF
Timing
Device
Programmer
Programmed
FPGA
X5816
Netlist
Figure 20: XC8100 Synthesis Design Flow
DS-8000-STD-PC1-C
Design
System Media
C = CD
Platform
PC1 = PC Windows
SN2 = Sun 4
HP7 = HP700
RS6 = RS6000
Series 8000
XC8100
STD = Schematic bundle
EXT = Synthesis + schematic
HW-130-PC1-01
Programmer
Hardware Power Supply
01 = US/Asia
02 = EC
03 = UK
04 = Japan
130 = Programmer
HW-138-PC84
 Programmer
138 = Package
Adapters
VQ44 = VQFP44
PC44 = PLCC44
PC84 = PLCC84
PQ100 = PQFP100
PQ160 = PQFP160
BG225 = BGA225
X5938
Series 8000 Software Ordering Information
Figure 21: XC8100 Architecture in Software Viewer
June 1, 1996 (Version 1.0) 5-19
XC8100 Synthesis Library
The XC8100 synthesis library is the set of pr imitives used
by synthesis CAE tools to generate the gate-level EDIF net
list for the XC8100 software tools. It does not include mac-
ros used for schematic design entry. The library uses the
standardized conventions of the Xilinx unified library.
O
AND2
I1
I0
O
AND2B1
I1
I0
O
AND2B2
I1
I0
O
AND3
I1
I0
I2
O
AND3B1
I1
I0
I2
O
AND3B2
I1
I0
I2
O
AND3B3
I1
I0
I2
O
AND4
I1
I0
I2
I3
O
AND4B1
I1
I0
I2
I3
O
AND4B2
I1
I0
I2
I3
O
AND4B3
I1
I0
I2
I3
O
AND4B4
I1
I0
I2
I3
O
AND5
I3
I1
I0
I2
I4
O
AND5B1
I3
I1
I0
I2
I4
O
AND5B2
I3
I1
I0
I2
I4
O
AND5B3
I3
I1
I0
I2
I4
O
AND5B4
I3
I1
I0
I2
I4
O
AND5B5
I3
I1
I0
I2
I4
O
AND6
I3
I1
I0
I2
I4
I5
O
AND6B1
I3
I1
I0
I2
I4
I5
O
AND6B2
I3
I1
I0
I2
I4
I5
O
AND6B3
I3
I1
I0
I2
I4
I5
O
AND6B4
I3
I1
I0
I2
I4
I5
O
AND6B5
I3
I1
I0
I2
I4
I5
O
AND6B6
I3
I1
I0
I2
I4
I5
O
AND7
I3
I1
I0
I2
I4
I6
I5
O
AND7B1
I3
I1
I0
I2
I4
I6
I5
O
AND7B2
I3
I1
I0
I2
I4
I6
I5
O
AND7B3
I3
I1
I0
I2
I4
I6
I5
O
AND7B4
I3
I1
I0
I2
I4
I6
I5
O
AND7B5
I3
I1
I0
I2
I4
I6
I5
O
AND7B6
I3
I1
I0
I2
I4
I6
I5
O
AND7B7
I3
I1
I0
I2
I4
I6
I5
O
AND8
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B1
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B2
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B3
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B4
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B5
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B6
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B7
I3
I1
I0
I2
I4
I7
I5
I6
O
AND8B8
I3
I1
I0
I2
I4
I7
I5
I6
AND Gates (2 CLCs)
AND Gates (1 CLC)
XC8100 FPGA Family
5-20 June 1, 1996 (Version 1.0)
O
ANDCC
I1
I0
I2
CIN
I3 COUT
O
ANDCCB1
I1
I0
I2
CIN
I3 COUT
O
ANDCCB2
I1
I0
I2
CIN
I3 COUT
O
ANDCCB3
I1
I0
I2
CIN
I3 COUT
O
ANDCCB4
I1
I0
I2
CIN
I3 COUT
O
ANDXC
I1
I0
I2
I3 COUT
O
ANDXCB1
I1
I0
I2
I3 COUT
O
ANDXCB2
I1
I0
I2
I3 COUT
O
ANDXCB3
I1
I0
I2
I3 COUT
O
ANDXCB4
I1
I0
I2
I3 COUT
IO
BUFGS
IO
BUFGP
IO
BUFROW
IO
BUF1X
IO
BUFE
E
IO
BUFEB1A
E
IO
BUFEB1B
EB
IO
BUFEB2
EB
D
FD
Q
C
D
FD_1
Q
C
D
FD_2
Q
C
D
FD_3
Q
C
DC
FD_CC
QC
C
FD_CX FD_XC
DC
Q
C
D
QC
C
Q Q
D
FDC
Q
C
D
FDC_1
Q
C
D
FDC_2
Q
C
D
FDC_3
Q
C
D
FDC_4
Q
C
D
FDC_5
Q
C
D
FDC_6
Q
C
D
FDC_7
Q
C
CLR CLR CLR CLR
CLR CLR CLR CLR
DC
FDC_CC
Q
C
CLR
QC DC
FDC_CX
C
CLR
QD
FDC_XC
Q
C
CLR
QC
D
FDP
Q
C
D
FDP_1
Q
C
D
FDP_2
Q
C
D
FDP_3
Q
C
D
FDP_4
Q
C
D
FDP_5
Q
C
D
FDP_6
Q
C
D
FDP_7
Q
C
PRE PRE PRE PRE
PRE PRE PRE PRE
GROUND
I
GRST
GSR
RTN
IB
GRSTB1
GSR
RTN
IO
IBUF
IO
DBUF
ANDCC – AND with Cascade In and Out
1 CLC
ANDCX – AND with Cascade In
ANDXC – AND with Cascade Out
1 CLC
BUF – Clock/Net Buffers
0 CLCs 1 CLC
BUFE – Three-State Buffers
1 CLC
FD – D Flip-Flops
2 CLCs
FDC – D Flip-Flop with Asynchronous Clear
2 CLCs
FDP – D Flip-Flop with Asynchronous Preset
2 CLCs
GND – Ground Signal Tag
0 CLCs
GRST
0 CLCs
IBUF, DBUF – Input Pad Buffers
0 CLCs 0 CLCs
O
ANDCX
I1
I0
I2
CIN
I3 O
ANDCXB1
I1
I0
I2
CIN
I3 O
ANDCXB2
I1
I0
I2
CIN
I3 O
ANDCXB3
I1
I0
I2
CIN
I3 O
ANDCXB4
I1
I0
I2
CIN
I3
June 1, 1996 (Version 1.0) 5-21
IO
INV1X
IO IO IO IOO
IOBUF
I
E
O
IOBUFB1A
I
E
O
IOBUFB1B
I
EB
O
IOBUFB2
I
EB
DOBUF DOBUFB1A DOBUFB1B DOBUFB2
IRBUF IRBUFB1A IRBUFB1B IRBUFB2
DRBUF DRBUFB1A DRBUFB1B DRBUFB2
D
LD
Q
G
D
LD_1
Q
G
D
LD_2
Q
G
D
LD_3
Q
G
D
LDC
Q
G
CLR
D
LDC_1
Q
G
CLR
D
LDC_2
Q
G
CLR
D
LDC_3
Q
G
CLR
D
LDC_4
Q
G
CLR
D
LDC_5
Q
G
CLR
D
LDC_6
Q
G
CLR
D
LDC_7
Q
G
CLR
G
D3
D2
D1
D0
EB
Q3
Q2
Q1
Q0
LDE4B2
G
D3
D2
D1
D0
EB
Q3
Q2
Q1
Q0
LDE4B1B
G
D3
D2
D1
D0
E
Q3
Q2
Q1
Q0
LDE4B1A
G
D3
D2
D1
D0
E
Q3
Q2
Q1
Q0
LDE4
D0
M2_1
D1
S0
OD0
M2_1B1A
D1
S0
OD0
M2_1B1B
D1
S0
OD0
M2_1B2
D1
S0
O
O
NAND5
I3
I1
I0
I2
I4
O
NAND5B1
I3
I1
I0
I2
I4
O
NAND5B2
I3
I1
I0
I2
I4
O
NAND5B3
I3
I1
I0
I2
I4
O
NAND5B4
I3
I1
I0
I2
I4
O
NAND5B5
I3
I1
I0
I2
I4
O
NAND6
I3
I1
I0
I2
I4
I5
O
NAND7
I3
I1
I0
I2
I4
I6
I5
O
NAND8
I3
I1
I0
I2
I4
I7
I5
I6
O
NAND2
I1
I0
O
NAND2B1
I1
I0
O
NAND2B2
I1
I0
O
NAND3
I1
I0
I2
O
NAND3B1
I1
I0
I2
O
NAND3B2
I1
I0
I2
O
NAND3B3
I1
I0
I2
O
NAND4
I1
I0
I2
I3
O
NAND4B1
I1
I0
I2
I3
O
NAND4B2
I1
I0
I2
I3
O
NAND4B3
I1
I0
I2
I3
O
NAND4B4
I1
I0
I2
I3
INV – Inverting Buffers
1 CLC
IOBUF, DBUF, IRBUF, DRBUF – Bidirectional
Three-State Pad Buffers
0 CLCs
LD – Transparent Data Latches
1 CLC
LDC – Transparent Data Latch with
Asynchronous Clear
2 CLCs
LDE4 – Quad Latch Bank with Three-State Output
4 CLCs
M2_1 – 2 to 1 Multiplexers
1 CLC
NAND Gates (1 CLC)
1 CLC
NAND Gates (2 CLCs)
2 CLCs
XC8100 FPGA Family
5-22 June 1, 1996 (Version 1.0)
NOR2
I1
I0 O
NOR2
I1
I0 O
NOR2
I1
I0 O
NOR3
I1
I0
O
I2
NOR3B1
I1
I0
O
I2
NOR3B2
I1
I0
O
I2
NOR3B3
I1
I0
O
I2
NOR4
I2
I0
O
I3
I1
NOR4B1
I2
I0
O
I3
I1
NOR4B2
I2
I0
O
I3
I1
NOR4B3
I2
I0
O
I3
I1
NOR4B4
I2
I0
O
I3
I1
NOR5
I2
I0
O
I4
I1
I3
NOR5B1
I2
I0
O
I4
I1
I3
NOR5B2
I2
I0
O
I4
I1
I3
NOR5B3
I2
I0
O
I4
I1
I3
NOR5B4
I2
I0
O
I4
I1
I3
NOR5B5
I2
I0
O
I4
I1
I3
NOR6
I2
I0
O
I5
I1
I3
I4
NOR7
I2
I0
O
I6
I1
I3
I4
I5
NOR8
I2
I0
O
I7
I1
I3
I4
I5
I6
IO
OBUF
IO
OBUFB1
IO
RBUF
IO
RBUFB1
IO
OBUFE
E
IO
OBUFEB1A
E
IO
OBUFEB1B
EB
IO
OBUFEB2
EB
RBUFE RBUFEB1A RBUFEB1B RBUFEB2
OR2
I1
I0 O
OR2B1
I1
I0 O
OR2B2
I1
I0 O
OR3
I1
I0
O
I2
OR3B1
I1
I0
O
I2
OR3B2
I1
I0
O
I2
OR3B3
I1
I0
O
I2
OR4
I2
I0
O
I3
I1
OR4B1
I2
I0
O
I3
I1
OR4B2
I2
I0
O
I3
I1
OR4B3
I2
I0
O
I3
I1
OR4B4
I2
I0
O
I3
I1
OR5
I2
I0
O
I4
I1
I3
OR5B1
I2
I0
O
I4
I1
I3
OR5B2
I2
I0
O
I4
I1
I3
OR5B3
I2
I0
O
I4
I1
I3
OR5B4
I2
I0
O
I4
I1
I3
OR5B5
I2
I0
O
I4
I1
I3
OR6
I2
I0
O
I5
I1
I3
I4
OR7
I2
I0
O
I6
I1
I3
I4
I5
OR8
I2
I0
O
I7
I1
I3
I4
I5
I6
NOR Gates (1 CLC)
1 CLC
NOR Gates (2 CLCs)
2 CLCs
OBUF, RBUF – Output Pad Buffers (C, R modes)
0 CLCs
OBUFE, RBUFE – Output Pad Three-State
Buffers
0 CLCs
OR Gates (1 CLC)
1 CLC
OR Gates (2 CLCs)
2 CLCs
June 1, 1996 (Version 1.0) 5-23
SOPCXB3A
I1
I0
I3
I2
SOPCXB3B
I1
I0
I3
I2
SOPCXB2A
I1
I0
I3
I2
SOPCXB2B
I1
I0
I3
I2
SOPCX
I1
I0
I3
I2
SOPCXB1A
I1
I0
I3
I2
CIN CIN CIN
CINCINCIN
O
O
O
O
O
O
SOPCXB1B
I1
I0
I3
I2
CIN
O
SOPCXB2C
I1
I0
I3
I2
CIN
O
SOPCXB4
I1
I0
I3
I2
CIN
O
SOP3
I1
I0
I2
O
SOP4
I1
I0
I3
I2
SOP3B1A
I1
I0
I2
SOP3B1B
I1
I0
I2
SOP3B2A
I1
I0
I2
SOP3B2B
I1
I0
I2
SOP3B3
I1
I0
I2
SOP4B1
I1
I0
I3
I2
SOP4B2A
I1
I0
I3
I2
SOP4B2B
I1
I0
I3
I2
SOP4B3
I1
I0
I3
I2
SOP4B4
I1
I0
I3
I2
O
O
O
O
O
O
O
O
O
O
O
O
SOP6B6
I1
I0
I5
I4
I3
I2
O
SOP6B5
I1
I0
I5
I4
I3
I2
O
SOP6B4B
I1
I0
I5
I4
I3
I2
O
SOP6B4A
I1
I0
I5
I4
I3
I2
O
SOP6B3B
I1
I0
I5
I4
I3
I2
O
SOP6B3A
I1
I0
I5
I4
I3
I2
O
SOP6B2B
I1
I0
I5
I4
I3
I2
O
SOP6B2A
I1
I0
I5
I4
I3
I2
O
SOP6B1
I1
I0
I5
I4
I3
I2
O
SOP6
I1
I0
I5
I4
I3
I2
SOPCCB3A
I1
I0
I3
I2
SOPCCB3B
I1
I0
I3
I2
SOPCCB2A
I1
I0
I3
I2
SOPCCB2B
I1
I0
I3
I2
SOPCC
I1
I0
I3
I2
SOPCCB1A
I1
I0
I3
I2
COUT
CIN CIN CIN
CINCINCIN
O
COUT
O
COUT
O
COUT
O
COUT
O
COUT
O
SOPCCB1B
I1
I0
I3
I2
COUT
CIN
O
SOPCCB2C
I1
I0
I3
I2
CIN COUT
O
SOPCCB4
I1
I0
I3
I2
CIN COUT
O
VCC
+5
VCC
XNOR2
I1
I0 O
XOR2
I1
I0 O
SOP – Sum of Products (1 CLC)
1 CLC
SOP – Sum of Products (2 CLCs)
2 CLCs
SOPCC – Sum of Products with Cascade In and
Out
1 CLC
SOPCX – Sum of Products with Cascade In
1 CLC
SOPXC – Sum of Products with Cascade Out
1 CLC
VCC – VCC Signal Tag
0 CLCs
XOR2, XNOR2 – Two-Input Exclusion OR/NOR
1 CLC
SOPXCB3
I1
I0
I3
I2
SOPXCB4
I1
I0
I3
I2
SOPXCB2A
I1
I0
I3
I2
SOPXCB2B
I1
I0
I3
I2
SOPXC
I1
I0
I3
I2
SOPXCB1
I1
I0
I3
I2
COUT
O
COUT
O
COUT
O
COUT
O
COUT
O
COUT
O
XC8100 FPGA Family
5-24 June 1, 1996 (Version 1.0)
Pin Descriptions
VCC
Two or more, depending on the package type. All must be
connected to the +5 V/3.3 V supply voltage.
VPP
Vpp is the programming voltage. This pin can be left float-
ing, but will dra w slightly less ICCO if connected to VCC dur-
ing operation.
GND
Four or more, depending on the package type. All must be
connected to ground.
GCK1 - GCK4 - I/O
Four global clock inputs each connect to a dedicated inter-
nal global buffer (bufedge) with short delay and minimal
skew. If not used for this purpose, these pins are user I/O.
TDO
Test Data Output pin for JTAG operation and testing. This is
a dedicated pin and is not available for user I/O. It has no
pull-up or pull-down.
TDI, TCK, TMS
Test Data In, Test Clock, and Test Mode Select inputs for
JTAG boundary scan, programming, and testing. These are
dedicated pins and are not available for user I/O. TMS and
TDI have pull-ups, TCK does not.
MASTER RESET
This active-low pin has the same functionality as removing
VCC and then reapplying power. It resets all synchronous
logic. Master Reset three-states all I/O pins while held low,
and can be useful for board testing. The pin has an internal
pull-up resistor, so no external resistor is needed if the pin
is unused. All synchronous logic is reset time TMRQ after
MR is raised high. It is recommended that MR on the
XC8100 (625 gate) device have a 1kΩ resistor in series to
limit current from signals that violate the VIN specification of
-0.5V.
I/O
These pins are configured by the user to be either input or
output. Programmable options include input voltage levels
(CMOS or TTL on a per-chip basis) and output slew rate
(resistive or capacitiv e mode on a per-pin basis). If an I/O is
not used, an internal pull-up resistor is automatically
enabled, so no external resistor is required.
XC8100 Pin Assignments
The XC8100 pinout is based on the XC4000 pinouts. This
means that, for an y package , pow er and control pins are on
the same pins as in the XC4000. However, not all the con-
trol pins have the same function. Typically the XC4000 M0/
M1/M2 pins are fixed. If JTAG is not used on the XC8100,
this is compatible . DONE can be an input or an output. If it’ s
an input, the XC8100 trace would have to be cut. The VPP
pin is compatible with either CCLK as an input or outputs,
although VPP has a larger input capacitance. Following is
the mapping:
Type XC8100 XC4000
VCC Same as XC4000 –
GND Same as XC4000 –
Control TMS M0
TCK M1
TDI M2
TDO TDO
VPP CCLK
MR DONE
June 1, 1996 (Version 1.0) 5-25
Number of Available I/O Pins
Note: Parentheses indicates future products
XC8100 Pinouts
Device Packages
Max I/O PC44 VQ44 PC84 PQ100 PQ160 BG225
XC8100 32 32 32 – – – –
XC8101 72 (32) (32) 61 72 – –
XC8103 128 32 32 61 64 (128) –
XC8106 168 – – 61 76 (129) (168)
XC8109 192 – – 61 – 129 192
Pin
Description PC44 VQ44 Bound
Scan Pin
Description PC44 VQ44 Bound
Scan Pin
Description PC44 VQ44 Bound
Scan
VCC 2 40 - TDI 16 10 – MR 31 25 –
I/O 3 41 69 GCK2-I/O 17 11 0 I/O 32 26 38
I/O 4 42 72 I/O 18 12 4 GCK3-I/O 33 27 41
I/O 5 43 75 I/O 19 13 7 GND 34 28 –
I/O 6 44 78 I/O 20 14 10 I/O 35 29 44
I/O 7 1 81 I/O 21 15 13 I/O 36 30 47
I/O 8 2 84 I/O 22 16 16 VPP 37 31 –
GCK1-I/O 9 3 87 VCC 23 17 – TDO 38 32 –
I/O 10 4 91 GND 24 18 – I/O 39 33 51
GND 11 5 – I/O 25 19 19 GCK4-I/O 40 34 54
I/O 12 6 94 I/O 26 20 22 I/O 41 35 57
I/O 13 7 97 I/O 27 21 25 I/O 42 36 60
TCK 14 8 – I/O 28 22 28 I/O 43 37 63
TMS 15 9 – I/O 29 23 31 I/O 44 38 66
I/O 30 24 34 GND 1 39 –
XC8100 FPGA FamilyXC8100 FPGA Family
5-26 June 1, 1996 (Version 1.0)
XC8101 Pinouts
Pin
Description PC84 PQ100 Bound
Scan Pin
Description PC84 PQ100 Bound
Scan Pin
Description PC84 PQ100 Bound
Scan
VCC 2 92 - GND 31 26 - I/O 58 58 80
I/O 3 93 159 TMS 32 27 - I/O - 59 83
I/O 4 94 162 VCC 33 28 - I/O 59 60 86
I/O - 95 165 TDI 34 29 - I/O 60 61 89
I/O - 96 168 GCK2-I/O 35 30 0 NC - 62 -
I/O 5 97 171 I/O 36 31 4 NC - 63 -
I/O 6 98 174 I/O - - 7 I/O 61 64 92
I/O 7 99 177 I/O - - 10 I/O 62 65 95
I/O 8 100 180 I/O - 32 13 VCC 63 66 -
I/O - - 193 I/O 37 33 16 GND 64 67 -
I/O - - 196 I/O 38 34 19 I/O 65 68 98
I/O 9 1 189 I/O 39 35 22 I/O 66 69 101
I/O 10 2 192 I/O - 36 25 NC - 70 -
VCC 11 3 - I/O - 37 28 I/O 67 71 104
GND 12 4 - I/O 40 38 31 I/O 68 72 107
GCK1-I/O 13 5 195 I/O 41 39 34 I/O 69 73 110
I/O 14 6 199 VCC 42 40 - I/O 70 74 113
I/O 15 7 202 GND 43 41 - I/O 71 75 116
I/O 16 8 205 I/O 44 42 37 I/O 72 76 119
I/O 17 9 208 I/O 45 43 40 VPP 73 77 -
I/O 18 10 211 I/O - 44 43 VCC 74 78 -
NC - 11 - I/O - 45 46 TDO 75 79 -
I/O 19 12 214 I/O 46 46 49 GND 76 80 -
I/O 20 13 217 I/O 47 47 52 I/O 77 81 123
GND 21 14 - I/O 48 48 55 GCK4-I/O 78 82 126
VCC 22 15 - I/O 49 49 58 I/O - - 129
I/O 23 16 220 I/O - - 61 I/O - - 132
I/O 24 17 223 I/O - - 64 I/O 79 83 135
NC - 18 - I/O 50 50 67 I/O 80 84 138
I/O 25 19 226 I/O 51 51 70 I/O 81 85 141
I/O 26 20 229 GND 52 52 - I/O 82 86 144
I/O 27 21 232 MR 53 53 - I/O - 87 147
I/O - 22 235 VCC 54 54 - I/O - 88 150
I/O 28 23 238 NC 55 55 - I/O 83 89 153
I/O 29 24 241 I/O 56 56 74 I/O 84 90 156
TCK 30 25 - GCK3-I/O 57 57 77 GND 1 91 -
June 1, 1996 (Version 1.0) 5-27
XC8103 Pinouts
Pin Bound Pin Bound Pin Bound
Description PC84 PQ100 Scan Description PC84 PQ100 Scan Description PC84 PQ100 Scan
VCC 2 92 - I/O 28 23 190 - - -
I/O 3 93 123 I/O 29 24 193 GND - -
I/O 4 94 126 TCK 30 25 - - - -
NC - 95 - GND 31 26 - - - -
NC - 96 - TMS 32 27 - I/O 59 60 62
I/O 5 97 129 VCC 33 28 - I/O 60 61 65
I/O 6 98 132 TDI 34 29 - NC - 62 -
- - - - GCK2-I/O 35 30 0 NC - 63 -
- - - - I/O 36 31 4 I/O 61 64 68
GND - - - I/O - - - I/O 62 65 71
- - - - I/O - - - VCC 63 66 -
- - - - I/O - 32 7 GND 64 67 -
I/O 7 99 135 I/O 37 33 10 I/O 65 68 74
I/O 8 100 138 - - - - I/O 66 69 77
I/O --- - --- NC -70-
I/O - - - GND - - - I/O - - -
I/O 9 1 141 - - - - I/O 67 71 80
I/O 10 2 144 - - - - I/O 68 72 83
VCC 11 3 - I/O 38 34 13 - - - -
GND 12 4 - I/O 39 35 16 - - - -
GCK1-I/O 13 5 147 NC - 36 - GND - - -
I/O 14 6 151 NC - 37 - - - - -
I/O - - - I/O 40 38 19 - - - -
I/O - - - I/O 41 39 22 I/O 69 73 86
I/O 15 7 154 VCC 42 40 - I/O 70 74 89
I/O 16 8 157 GND 43 41 - I/O - - -
- - - - I/O 44 42 25 I/O - - -
- - - - I/O 45 43 28 I/O 71 75 92
GND - - - NC - 44 - I/O 72 76 95
- - - - NC - 45 - VPP 73 77 -
- - - - I/O 46 46 31 VCC 74 78 -
I/O 17 9 160 I/O 47 47 34 TDO 75 79 -
I/O 18 10 163 - - - - GND 76 80 -
NC - 11 - - - - - I/O 77 81 99
I/O - - - GND - - - GCK4-I/O 78 82 102
I/O 19 12 166 - - - - I/O - - -
I/O 20 13 169 - - - - I/O - - -
GND 21 14 - I/O 48 48 37 I/O 79 83 105
VCC 22 15 - I/O 49 49 40 I/O 80 84 108
I/O 23 16 172 I/O - - - - - - -
I/O 24 17 175 I/O - - - - - - -
NC - 18 - I/O 50 50 43 GND - - -
I/O - - - I/O 51 51 46 - - - -
I/O 25 19 178 GND 52 52 - - - - -
I/O 26 20 181 MR 53 53 - I/O 81 85 111
- - - - VCC 54 54 - I/O 82 86 114
- - - - NC 55 55 - - - - -
GND - - - I/O 56 56 50 NC - 87 -
- - - - GCK3-I/O 57 57 53 NC - 88 -
- - - - I/O - - - I/O 83 89 117
I/O 27 21 184 I/O - - - I/O 84 90 120
I/O - 22 187 I/O 58 58 56 GND 1 91 -
I/O - - - I/O - 59 59
I/O --- - ---
XC8100 FPGA FamilyXC8100 FPGA Family
5-28 June 1, 1996 (Version 1.0)
XC8106 Pinouts
Pin Bound Pin Bound Pin Bound
Description PC84 PQ100 Scan PQ160 Description PC84 PQ100 Scan PQ160 Description PC84 PQ100 Scan PQ160
VCC 2 92 - 142 I/O 28 23 250 36 I/O - - - 90
I/O 3 93 165 143 I/O 29 24 253 37 GND - - - 91
I/O 4 94 168 144 TCK 30 25 - 38 I/O - - - 92
I/O - 95 171 145 GND 31 26 - 39 I/O - - - 93
I/O - 96 174 146 TMS 32 27 - 40 I/O 59 60 86 94
I/O 5 97 177 147 VCC 33 28 - 41 I/O 60 61 89 95
I/O 6 98 180 148 TDI 34 29 - 42 I/O - - - 96
I/O - - - 149 GCK2-I/O 35 30 0 43 NC - 62 - -
I/O - - - 150 I/O 36 31 4 44 I/O - 63 92 97
GND - - - 151 I/O - - 7 45 I/O 61 64 95 98
I/O - - - 152 I/O - - 10 46 I/O 62 65 98 99
I/O - - - 153 I/O - 32 13 47 VCC 63 66 - 100
I/O 7 99 183 154 I/O 37 33 16 48 GND 64 67 - 101
I/O 8 100 186 155 I/O - - - 49 I/O 65 68 101 102
I/O - - 189 156 I/O - - - 50 I/O 66 69 104 103
I/O - - 192 157 GND - - - 51 I/O - 70 107 104
I/O 9 1 195 158 I/O - - - 52 I/O - - - 105
I/O 10 2 198 159 I/O - - - 53 I/O 67 71 110 106
VCC 11 3 - 160 I/O 38 34 19 54 I/O 68 72 113 107
GND 12 4 - 1 I/O 39 35 22 55 I/O - - - 108
GCK1-I/O 13 5 201 2 I/O - 36 25 56 I/O - - - 109
I/O 14 6 205 3 I/O - 37 28 57 GND - - - 110
I/O - - - 4 I/O 40 38 31 58 I/O - - - 111
I/O - - - 5 I/O 41 39 34 59 I/O - - - 112
I/O 15 7 208 6 VCC 42 40 - 60 I/O 69 73 116 113
I/O 16 8 211 7 GND 43 41 - 61 I/O 70 74 119 114
I/O - - - 8 I/O 44 42 37 62 I/O - - - 115
I/O - - - 9 I/O 45 43 40 63 I/O - - - 116
GND - - - 10 I/O - 44 43 64 I/O 71 75 122 117
I/O - - - 11 I/O - 45 46 65 I/O 72 76 125 118
I/O - - - 12 I/O 46 46 49 66 VPP 73 77 - 119
I/O 17 9 214 13 I/O 47 47 52 67 VCC 74 78 - 120
I/O 18 10 217 14 I/O - - - 68 TDO 75 79 - 121
I/O - - - 15 I/O - - - 69 GND 76 80 - 122
I/O - 11 220 16 GND - - - 70 I/O 77 81 129 123
I/O 19 12 223 17 I/O - - - 71 GCK4-I/O 78 82 132 124
I/O 20 13 226 18 I/O - - - 72 I/O - - 135 125
GND 21 14 - 19 I/O 48 48 55 73 I/O - - 138 126
VCC 22 15 - 20 I/O 49 49 58 74 I/O 79 83 141 127
I/O 23 16 229 21 I/O - - 61 75 I/O 80 84 144 128
I/O 24 17 232 22 I/O - - 64 76 I/O - - - 129
I/O - 18 235 23 I/O 50 50 67 77 I/O - - - 130
I/O - - - 24 I/O 51 51 70 78 GND - - - 131
I/O 25 19 238 25 GND 52 52 - 79 I/O - - - 132
I/O 26 20 241 26 MR 53 53 - 80 I/O - - - 133
I/O - - - 27 VCC 54 54 - 81 I/O 81 85 147 134
I/O - - - 28 NC 55 55 - 82 I/O 82 86 150 135
GND - - - 29 I/O 56 56 74 83 I/O - - - 136
I/O - - - 30 GCK3-I/O 57 57 77 84 I/O - 87 153 137
I/O - - - 31 I/O - - - 85 I/O - 88 156 138
I/O 27 21 244 32 I/O - - - 86 I/O 83 89 159 139
I/O - 22 247 33 I/O 58 58 80 87 I/O 84 90 162 140
I/O - - - 34 I/O - 59 83 88 GND 1 91 - 141
I/O - - - 35 I/O - - - 89
June 1, 1996 (Version 1.0) 5-29
XC8109 Pinouts
Note: ** These BGA225 balls are connected to ground: F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8
Pin
Description PC
84 PQ
160 PG
223 BG
225 Bound
Scan
VCC 2 142 J4 D8 -
I/O 3 143 J3 E8 399
I/O 4 144 J2 B7 402
I/O - 145 J1 A7 405
I/O - 146 H1 C7 408
I/O - - H2 D7 411
I/O - - H3 E7 414
I/O 5 147 G1 A6 417
I/O 6 148 G2 B6 420
I/O - - - - 423
I/O - - - - 426
I/O - - - - 429
I/O - - H4 C6 432
I/O - - G4 F7 435
I/O - 149 F1 A5 438
I/O - 150 E1 B5 441
GND - 151 G3 ** -
I/O - - - - 444
I/O - - F2 D6 447
I/O - - D1 C5 450
I/O - 152 C1 A4 453
I/O - 153 E2 E6 456
I/O 7 154 F3 B4 459
I/O 8 155 D2 D5 462
I/O - - F4 A3 465
I/O - - E4 C4 468
I/O - 156 B1 B3 471
I/O - 157 E3 F6 474
I/O 9 158 C2 A2 477
I/O 10 159 B2 C3 480
VCC 11 160 D3 B2 -
GND 12 1 D4 A1 -
GCK1-I/O 13 2 C3 D4 483
I/O 14 3 C4 B1 487
I/O - 4 B3 C2 490
I/O - 5 C5 E5 493
I/O 15 6 A2 D3 496
I/O 16 7 B4 C1 499
I/O - 8 C6 D2 502
I/O - 9 A3 G6 505
I/O - - B5 E4 508
I/O - - B6 D1 511
I/O - - D5 E3 514
I/O - - D6 E2 517
GND - 10 C7 ** -
I/O - 11 A4 F5 520
I/O - 12 A5 E1 523
I/O 17 13 B7 F4 526
I/O 18 14 A6 F3 529
I/O - - D7 F2 532
I/O - - D8 F1 535
I/O - - C8 G4 538
I/O - - A7 G3 541
I/O - 15 B8 G2 544
I/O - 16 A8 G1 547
I/O 19 17 B9 G5 550
I/O 20 18 C9 H3 553
GND 21 19 D9 H2 -
VCC 22 20 D10 H1 -
I/O 23 21 C10 H4 556
I/O 24 22 B10 H5 559
I/O - 23 A9 J2 562
I/O - 24 A10 J1 565
I/O - - A11 J3 568
I/O - - C11 J4 571
I/O - - D11 J5 574
I/O - - D12 K1 577
I/O 25 25 B11 K2 580
I/O 26 26 A12 K3 583
I/O - 27 B12 J6 586
I/O - 28 A13 L1 589
GND - 29 C12 ** -
I/O - - D13 L2 592
I/O - - D14 K4 595
I/O - - B13 L3 598
I/O - - A14 M1 601
I/O - 30 A15 K5 604
I/O - 31 C13 M2 607
I/O 27 32 B14 L4 610
I/O - 33 A16 N1 613
I/O - 34 B15 M3 616
I/O - 35 C14 N2 619
I/O 28 36 A17 K6 622
I/O 29 37 B16 P1 625
TCK 30 38 C15 N3 -
GND 31 39 D15 ** -
TMS 32 40 A18 P2 -
VCC 33 41 D16 R1 -
TDI 34 42 C16 M4 -
GCK2-I/O 35 43 B17 R2 0
I/O 36 44 E16 P3 4
I/O - 45 C17 L5 7
I/O - 46 D17 N4 10
I/O - 47 B18 R3 13
I/O 37 48 E17 P4 16
I/O - 49 F16 K7 19
I/O - 50 C18 M5 22
I/O - - D18 R4 25
I/O - - F17 N5 28
I/O - - E15 P5 31
I/O - - F15 L6 34
I/O - - - - 37
GND - 51 G16 ** -
I/O - 52 E18 R5 40
I/O - 53 F18 M6 43
I/O 38 54 G17 N6 46
I/O 39 55 G18 P6 49
I/O - - - - 52
I/O - - - - 55
I/O - - - - 58
I/O - - H16 R6 61
I/O - - H17 M7 64
I/O - - G15 N7 67
I/O - - H15 P7 70
I/O - 56 H18 R7 73
I/O - 57 J18 L7 76
I/O 40 58 J17 N8 79
I/O 41 59 J16 P8 82
VCC 42 60 J15 R8 -
GND 43 61 K15 M8 -
Pin
Description PC
84 PQ
160 PG
223 BG
225 Bound
Scan
I/O 44 62 K16 L8 85
I/O 45 63 K17 P9 88
I/O - 64 K18 R9 91
I/O - 65 L18 N9 94
I/O - - L17 M9 97
I/O - - L16 L9 100
I/O - - L15 R10 103
I/O - - M15 P10 106
I/O - - - - 109
I/O - - - - 112
I/O - - - - 115
I/O 46 66 M18 N10 118
I/O 47 67 M17 K9 121
I/O - 68 N18 R11 124
I/O - 69 P18 P11 127
GND - 70 M16 ** -
I/O - - - - 130
I/O - - N15 M10 133
I/O - - P15 N11 136
I/O - - N17 R12 139
I/O - - R18 L10 142
I/O - 71 T18 P12 145
I/O - 72 P17 M11 148
I/O 48 73 N16 R13 151
I/O 49 74 T17 N12 154
I/O - 75 R17 P13 157
I/O - 76 P16 K10 160
I/O 50 77 U18 R14 163
I/O 51 78 T16 N13 166
GND 52 79 R16 ** -
MR 53 80 U17 P14 -
VCC 54 81 R15 R15 -
NC 53 82 V18 M12 -
I/O 56 83 T15 P15 170
GCK3-I/O 57 84 U16 N14 173
I/O - 85 T14 L11 176
I/O - 86 U15 M13 179
I/O - - R14 N15 182
I/O - - R13 M14 185
I/O 58 87 V17 J10 188
I/O - 88 V16 L12 191
I/O - 89 T13 M15 194
I/O - 90 U14 L13 197
I/O - - V15 L14 200
I/O - - V14 K11 203
GND - 91 T12 ** -
I/O - - R12 L15 206
I/O - - R11 K12 209
I/O - 92 U13 K13 212
I/O - 93 V13 K14 215
I/O 59 94 U12 K15 218
I/O 60 95 V12 J12 221
I/O - - T11 J13 224
I/O - - U11 J14 227
I/O - 96 V11 J15 230
I/O - 97 V10 J11 233
I/O 61 98 U10 H13 236
I/O 62 99 T10 H14 239
VCC 63 100 R10 H15 -
GND 64 101 R9 ** -
Pin
Description PC
84 PQ
160 PG
223 BG
225 Bound
Scan
I/O 65 102 T9 H12 242
I/O 66 103 U9 H11 245
I/O - 104 V9 G14 248
I/O - 105 V8 G15 251
I/O - - U8 G13 254
I/O - - T8 G12 257
I/O 67 106 V7 G11 260
I/O 68 107 U7 F15 263
I/O - 108 V6 F14 266
I/O - 109 U6 F13 269
I/O - - R8 G10 272
I/O - - R7 E15 275
GND - 110 T7 ** -
I/O - - R6 E14 278
I/O - - R5 F12 281
I/O - - V5 E13 284
I/O - - V4 D15 287
I/O - 111 U5 F11 290
I/O - 112 T6 D14 293
I/O 69 113 V3 E12 296
I/O 70 114 V2 C15 299
I/O - 115 U4 D13 302
I/O - 116 T5 C14 305
I/O 71 117 U3 F10 308
I/O 72 118 T4 B15 311
VPP 73 119 V1 C13 -
VCC 74 120 R4 B14 -
TDO 75 121 U2 A15 -
GND 76 122 R3 D12 -
I/O 77 123 T3 A14 315
GCK4-I/O 78 124 U1 B13 318
I/O - 125 P3 E11 321
I/O - 126 R2 C12 324
I/O 79 127 T2 A13 327
I/O 80 128 N3 B12 330
I/O - - P4 F9 333
I/O - - N4 D11 336
I/O - 129 P2 A12 339
I/O - 130 T1 C11 342
I/O - - R1 B11 345
I/O - - N2 E10 348
I/O 351
GND - 131 M3 ** -
I/O - 132 P1 A11 354
I/O - 133 N1 D10 357
I/O - - M4 C10 360
I/O - - L4 B10 363
I/O - - - - 366
I/O - - - - 369
I/O - - - - 372
I/O 81 134 M2 A10 375
I/O 82 135 M1 D9 378
I/O - - L3 C9 381
I/O - 136 L2 B9 384
I/O - 137 L1 A9 387
I/O - 138 K1 E9 390
I/O 83 139 K2 C8 393
I/O 84 140 K3 B8 396
GND 1 141 K4 A8 -
Pin
Description PC
84 PQ
160 PG
223 BG
225 Bound
Scan
XC8100 FPGA FamilyXC8100 FPGA Family
5-30 June 1, 1996 (Version 1.0)
Package Pinout Diagrams
Figure 22: PC44 PLCC with 44 Leads, 50 mil Lead Pitch
Figure 23: VQ44 VQFP with 44 Leads, 0.8 mm Lead Pitch
(39)
(7)
(29)
Top View
X5831
GND (11)
(17)
TDI (16)
TMS (15)
TCK (14)
(18)
VCC (23)
GND (24)
(28)
(31) MR
(34) GND
(37) VPP
(38) TDO
(40)
(1) GND
(2) VCC
(6)
Top View
GND (5)
TCK (8)
TMS (9)
TDI (10)
(1)
(11)
VCC (40)
GND (39)
(34)
(44)
(17) VCC
(12)
(22)
(18) GND
(23)
(28) GND
(25) MR
(33)
(32) TDO
(31) VPP
X5939
June 1, 1996 (Version 1.0) 5-31
Figure 24: PC84 PLCC with 84 Leads, 50 mil Lead Pitch
(63) VCC
TMS (32)
GND (31)
VCC (42)
GND (43)
(74) VCC
(1) GND
Top View
VCC (22)
(54) VCC
GND (12)
GND (21)
(2) VCC
(64) GND
TCK (30)
VCC (33)
TDI (34)
MR (53)
GND (52)
(57) GCK3-I/O
(73) VPP
(75) TD0
(76) GND
(11) VCC
GCK1-I/O (13)
GCK2-I/O (35)
(78) GCK4-I/O
X5628
(55) NC
Figure 25: PQ100 PQFP with 100 Leads, .65 mm Lead Pitch
(80) GND
(78) VCC
VCC (92)
GND (91)
GCK2-I/O (30) (51)
(54) VCC
(52) GND
Top View
(50)
(31)
* Depends on device
(41) GND
(40) VCC
GND (4)
GCK1-I/O (5)
(1)
VCC (3)
(100)
(81)
GCK4-I/O (82)
GND (14)
VCC (15)
GND (26)
VCC (28)
(66) VCC
(67) GND
* (11)
* (18) (62) *
(63) *
(70) *
TCK (25)
TMS (27) (53) MR
(55) NC
(57) GCK3-I/O
(77) VPP
(79) TD0
TDI (29)
X5780
XC8100 FPGA FamilyXC8100 FPGA Family
5-32 June 1, 1996 (Version 1.0)
Figure 26: PQ160 PQFP with 160 Leads, .65mm Lead Pitch
(120) VCC
(81) VCC
(61) GND
(79) GND
(52) *
Top View
(51) GND
(41) VCC
* Depends on device
TD0 (121)
VCC (160)
GND (1)
GCK1-I/O (2)
* (11)
* (9)
TMS (40)
TCK (38)
(101) GND
(89) *
(42) TDI
(43) GCK2-I/O
(80) MR
GND (10)
GND (39) (82) NC
(84) GCK3-I/O
(92) *
(90) *
(91) GND
(93) *
(119) VPP
GND (141)
VCC (142)
* (8)
* (12)
GND (19)
* (30)
* (28)
GND (29)
* (27)
* (31)
(53) *
(50) *
(49) *
(71) *
(70) GND
(72) *
(69) *
(68) *
(108) *
(111) *
(109) *
(110) GND
(112) *
GND (122)
GCK4-I/O (124)
* (129)
* (130)
GND (131)
* (132)
* (133)
* (136)
* (149)
* (150)
GND (151)
* (152)
* (153)
VCC (20)
(60) VCC
(100) VCC
X5781
Figure 27: BG225 Plastic Ball Grid Array with 225 PbSn Balls, 15 x 15 Array, 1.50 mm Lead Pitch
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
15 14 13 12 11 10 9 8
X5807
7654321
VCC
VCC
VCC
VCC VCC VCC
VCC
VCC
GND
GND
GNDNC
GND
GND
GND
GND GND GND
GND GND GNDGND GND
GND GND GND
GND
TMS
TCK
MR
VPP
TD0
* Depends on device
*
*
***
*
****
*****
*
*
***
***
**
***
***
*
TDI
Top View (through package)
June 1, 1996 (Version 1.0) 5-33
Device Specifications
Absolute Maximum Ratings
Note: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
5 V Operating Conditions
DC Characteristics Over 5 V Operating Conditions
Notes: 1. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies by package.
2. With no output current loads, no active inputs, all package pins at VCC or GND. Typical quiescent supply current at room
temperature is less than 50% of the maximum.
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to + 7.0 V
VIN Input voltage with respect to GND -0.5 to VCC + 0.5 V
VTS Voltage applied to three-state output -0.5 to VCC + 0.5 V
TSTG Storage temperature (ambient) -65 to + 150 °C
TSOL Maximum soldering temperature (10 sec @ 1/16 inch) + 260 °C
TJJunction temperature - Ceramic + 150 °C
Junction temperature - Plastic + 125 °C
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial 0°C to 70°C 4.75 5.25 V
VIHT High-level input voltage for TTL threshold 2.0 VCC V
VIHC High-level input voltage for CMOS threshold 70% 100% VCC
VILT Low-level input voltage for TTL threshold 0 0.8 V
VILC Low-level input voltage for CMOS threshold 0 20% VCC
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage, IOH = -4 mA, VCC min 3.86 V
VOLR Low-level output voltage, IOL = 24 mA, VCC min
resistive mode (Note 1) 0.50 V
VOLC Low-level output voltage, IOL = 4 mA, VCC min
capacitive mode (Note 1) 0.40 V
ICCO
Quiescent supply current, CMOS mode, (Note 2) XC8100
– actual ICCO depends on the design XC8101
– TTL mode adds 8-30 mA XC8103
– see Power Consumption section XC8106
XC8109
0.8
1.5
3.0
6.0
10.0
mA
mA
mA
mA
mA
IIInput leakage current - 10 + 10 µA
IRIN Pad pull-up current, VIN = 0 V (sample tested) 0.02 0.20 mA
CIN Input capacitance (sample tested) 15 pF
XC8100 FPGA FamilyXC8100 FPGA Family
5-34 June 1, 1996 (Version 1.0)
DC Characteristics Over 3.3 V Operating Conditions
Notes: 1. Set CMOS/TTL input threshold to CMOS mode for use at 3.3 V.
2. With no output current loads, no active inputs, all package pins at VCC or GND. Typical quiescent supply current at room
temperature is less than 25% of the maximum.
Symbol Description Min Max Units
VCC Supply voltage relative to GND Commercial 0°C to 70°C 3.0 3.6 V
VIH High-level input voltage (Note 1) 2.0 VCC + 0.3 V
VIL Low-level input voltage (Note 1) - 0.3 0.8 V
VOH High-level output voltage, IOH = -4.0 mA, VCC min
IOH = -100 µA, VCC min 2.4
VCC -0.2 V
V
VOLR Low-level output voltage, IOL = 12.0 mA, VCC min
resistance mode 0.4 V
VOLC Low-level output voltage, IOL = 4.0 mA, VCC min
capacitive mode 0.4 V
ICCO
Quiescent supply current, CMOS mode, (Note 2) XC8100
– actual ICCO depends on the design XC8101
– see Power Consumption section XC8103
XC8106
XC8109
250
500
800
1500
3000
µA
µA
µA
µA
µA
June 1, 1996 (Version 1.0) 5-35
CLC Combinatorial Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
factory tested except f or the progr ammed resistance of the fuses that will be used in the end application. Since many internal
timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines
reflect worst-case values over the recommended operating conditions. See the XC8100 software for complete timing
information
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
AND4 Input I0 to output O
Input I1 to output O
Input I2 to output O
Input I3 to output O
i0r
i1r
i2r
i3r
3.0
2.9
3.2
2.9
5.3
5.2
5.8
5.2
ns
ns
ns
ns
AND8 Input I0 to output O
Input I4 to output O
Input I7 to output O
Note: Inputs I0 to I3 are faster than the
cascaded inputs I4 to I7
i0r
i4r
i7r
3.0
5.4
5.3
5.4
9.9
9.7
ns
ns
ns
ANDCC Input I0 to output O
Input I3 to output O
Input I0 to output COUT
Input I3 to output COUT
Input CIN to output COUT
i0r
i3r
i0rc
i3rc
circ
3.0
3.3
2.3
2.6
2.4
5.4
6.1
4.2
4.9
4.6
ns
ns
ns
ns
ns
BUFE Input I to output O flow-through
Three-state E to output O begin hi-Z
Three-state E to output O active
ir
ehz
ezh
2.8
4.6
4.6
4.8
7.3
7.3
ns
ns
ns
M2_1 Input D0 to output O
Input D1 to output O
Select input S to output O
d0r
d1r
s0r
3.0
2.8
3.1
5.1
5.0
5.6
ns
ns
ns
SOP4 Input I0 to output O
Input I1 to output O
Input I2 to output O
Input I3 to output O
i0r
i1r
i2r
i3r
3.1
3.0
3.1
2.8
5.5
5.3
5.5
4.9
ns
ns
ns
ns
SOP6 Input I0 to output O
Input I2 to output O
Input I5 to output O
Note: Inputs I0 and I1 are faster and
are approximately the same delay
i0r
i2r
i5r
3.1
4.8
4.6
5.5
8.4
7.9
ns
ns
ns
O
I1
I0
I2
I3
O
I3
I1
I0
I2
I4
I7
I5
I6
O
I1
I0
I2
CIN
I3 COUT
IO
E
D0
D1
S0
O
I1
I0
I3
I2 O
O
I1
I0
I5
I4
I3
I2
XC8100 FPGA FamilyXC8100 FPGA Family
5-36 June 1, 1996 (Version 1.0)
CLC Combinatorial Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested
except for the programmed resistance of the fuses that will be used in the end application. Since many inter nal timing parameters cannot be
measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the
recommended operating conditions. See the XC8100 software for complete timing information.
Notes: 1. Symbol names are those used in timing parameters in the XC8100 software, e.g., and4_i0r.
2. CLC combinatorial worst-case timings use rising edges. Falling edge signals are typically 0.6 ns faster.
3. Using inverted inputs (“bubbled”) has minimal change on rising edge combinatorial timings. Inverting falling edge signals
typically adds 0.4 - 0.5 ns.
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
SOPCC Input I0 to output O
Input I3 to output O
Input I0 to output COUT
Input I3 to output COUT
Input CIN to output COUT
i0r
i3r
i0r
i3r
circ
3.1
3.2
2.3
2.4
2.2
5.5
5.8
4.3
4.7
4.2
ns
ns
ns
ns
ns
XOR2 Input I0 to output O
Input I1 to output O i0r
i1r 3.3
3.0 5.6
5.1 ns
ns
I1
I0
I3
I2
CIN COUT
O
I1
I0 O
June 1, 1996 (Version 1.0) 5-37
CLC Sequential Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested
except for the programmed resistance of the fuses that will be used in the end application. Since many inter nal timing parameters cannot be
measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the
recommended operating conditions. See the XC8100 software for complete timing information.
Note: Sequential worst-case timings delays use rising edges. Falling edge signals are typically 0.5 ns faster for single-CLC functions
(e.g. LD) and 1.0 ns faster for double-CLC functions (e.g. FD).Toggle frequency based on worst-case data from XC8100 software.
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
FD Clock C to output Q delay
Data set-up time before clock C
Data hold time after clock C
ckqr
su
hold 2.3
0.0
3.5 3.3
0.0
6.1 ns
ns
ns
FDC Clock C to output Q delay
Data set-up time before clock C
Data hold time after clock C
Asynchronous CLR to output Q
CLR width
Note: timings are similar for FDP
(D FF with Reset)
ckqr
su
hold
clqf
clpmin
2.3
0.0
1.7
3.5
3.0
3.3
0.0
3.3
6.1
5.9
ns
ns
ns
ns
ns
LD Data D to output Q delay
Latch G to output Q delay
Data set-up time to G
Data hold time from G
G width
Note: when G is high, data flows
through. G latches on the falling edge
dqr
gqr
su
hold
gpmin
2.2
0.0
2.5
2.8
3.0 4.5
0.0
5.3
5.1
5.4 ns
ns
ns
ns
ns
LDC Data D to output Q delay
Latch G to output Q delay
Data set-up time to G
Data hold time from G
Asynchronous CLR to output Q
CLR width
dqr
gqr
su
hold
clqr
clpmin
2.2
0.0
2.2
3.2
3.4
5.1
4.5
0.0
3.9
5.8
6.4
9.1
ns
ns
ns
ns
ns
ns
Clock High time
Low time
Toggle Frequency
TCH
TCL
FTOG
2.6
2.6 144
5.2
5.2 ns
ns
MHz
DQ
C
DQ
C
CLR
DQ
G
DQ
G
CLR
CLK
D, G
Q
CLR, PRE
CH
T
X5631
CL
T
CKQR
T
CLQR
T
CLPMIN
T
SU
THOLD
T
XC8100 FPGA FamilyXC8100 FPGA Family
5-38 June 1, 1996 (Version 1.0)
Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested
except for the programmed resistance of the fuses that will be used in the end application. Since many inter nal timing parameters cannot be
measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the
recommended operating conditions. See the XC8100 software for complete timing information.
Note: 1. Symbols are Xilinx standard names and timing parameters used in XC8100 software, e.g., ibuf_ir.
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
BUF1X Input I to output O delay TIO
ir 2.8 4.8 ns
BUFGP Input I to output O delay
Note: Timing is for buffer only, and
does not include device-dependent
wire delays
TIO
ir 4.6 7.6 ns
BUFROW Input I to output O delay
Notes:
1. Same delay for BUFGS
2. Timing is for buffer only, and does
not include device-dependent
wire delays
TIO
ir 2.0 3.3 ns
INV1X Input I to output O delay TIO
ir 3.0 5.1 ns
IO
IO
IO
IO
June 1, 1996 (Version 1.0) 5-39
I/O Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% factory tested
except for the programmed resistance of the fuses that will be used in the end application. Since many inter nal timing parameters cannot be
measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the
recommended operating conditions. See the XC8100 software for complete timing information.
Notes: 1. Symbols are Xilinx standard names (e.g. TPID) and timing parameters used in XC8100 software, e.g., ibuf_ir.
2. Timing is measured at pin threshold, with 50 pF load.
3.
4. Output delays (e xcept input E to pad O begin hi Z) change with capacitiv e load according to the f ollowing tab le. Delays abo ve
are calculated for 50 pF. As an example, obuf_ir at 20 pF is: 3.4 -(30 x 0.21) = 2.77 ns. XC8100 software can make these
calculations automatically.
5. Unused (bonded or unbonded) pads are automatically pulled-up internally with a ~50K Ω resistor.
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
IBUF Input propagation delay
Note: same timing for IOBUF B-to-O
TPID
ir 1.8 3.0 ns
DBUF Input propagation delay
(with delay)
Note: same timing for DOBUF B-to-O
TPID
ir 14.5 26.3 ns
OBUF Output delay to pin
(capacitive mode) TOP
ir
if 3.4
5.4 6.7
7.2 ns
ns
OBUFE Output delay to pin (capacitive mode)
Three-state input E to pad O begin hi-Z
Three-state input E to pad O active
Note: same timing for IOBUF E-to-O
ir
if
ehz
ezl
3.4
5.4
3.9
5.7
6.8
7.3
7.0
9.2
ns
ns
ns
ns
RBUF Output delay to pin (resistive mode)
Note: same timing for RBUFE
TOPR
ir
if 3.5
4.5 6.1
6.0 ns
ns
5 V 3.3 V
Rise Fall Rise Fall Units
Resistive Mode
Capacitive Mode 0.017
0.021 0.030
0.046 0.033
0.054 0.026
0.049 ns/pF
ns/pF
IO
IO
IO
IO
E
IO
R
1
R
1
R
2
V
CC
50 pF R2
Output
X5943
5 V
177
370 294 Ω
RBUF loading:
3.3 V
217 Ω
XC8100 FPGA FamilyXC8100 FPGA Family
5-40 June 1, 1996 (Version 1.0)
Input and Output Parameters (Pin-to-Pin)
The following values reflect worst-case values over the recommended operating conditions. The exact timing depends on placement and
routing so results may vary from design to design. See the XC8100 software for complete timing information.
Note: The external pin-to-pin setup and hold times for
synchronous elements depend on the intrinsic
setup and hold requirements of the appropriate
CLC and the relative delays of the data and clock
input nets. Specifically:
Tsetup = Delaydata + TsetupCLC - Delayclock
Thold = Delayclock + TholdCLC - Delaydata
Speed Grade -1 -2
Units
Supply V oltage 5 V 3.3 V 5 V 3.3 V
Description Sym Min Max Min Max Min Max Min Max
Global clock pin to output pin (resistive), 24 FF per
row, all rows TICKO
(Max)
XC8100
XC8101
XC8103
XC8106
XC8109
18.8
19.0
20.0
21.5
21.9
28.0
29.0
30.1
31.6
32.0
ns
ns
ns
ns
ns
I/O pin to row output pin (resistive)
24 FF, 1 row TICKO
(Max)
XC8100
XC8101
XC8103
XC8106
XC8109
15.5
15.6
16.0
16.7
17.4
24.0
24.1
24.2
25.1
25.8
ns
ns
ns
ns
ns
Input set-up time, no delay, 1 FF TPSUF
(Min)
XC8100
XC8101
XC8103
XC8106
XC8109
0.1
0.3
0.3
0.1
0
0
0
0
0
0
ns
ns
ns
ns
ns
Input hold time, no delay, 24 FF per row, all rows TPHF
(Min)
XC8100
XC8101
XC8103
XC8106
XC8109
7.8
7.9
8.0
8.3
9.3
11.5
11.6
11.6
12.1
13.1
ns
ns
ns
ns
ns
Input set-up time, with DBUF delay, 1 FF TPSU
(Min)
XC8100
XC8101
XC8103
XC8106
XC8109
12.9
13.1
13.0
12.9
13.0
22.9
23.2
23.1
23.1
23.0
ns
ns
ns
ns
ns
Input hold time, with DBUF delay, 24 FF per row,
all rows TPH
(Min)
XC8100
XC8101
XC8103
XC8106
XC8109
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
FD
X5783
Global Clock-to-Output
BUFGP
RBUF
FD
X5636
Clock-to-Output
IBUF BUFROW
RBUF
FD
Input
Set-Up
&
Hold
TimeX5784
BUFGP
IBUF
FD
Input
Set-Up
&
Hold
TimeX5784
BUFGP
IBUF
FD
Input
Set-Up
&
Hold
TimeX5630
BUFGP
DBUF
FD
Input
Set-Up
&
Hold
TimeX5630
BUFGP
DBUF
FD
CLC
Data
Clock
X5840
Delay Clock
Delay Data
June 1, 1996 (Version 1.0) 5-41
The data and clock delays consist of the delays associated
with any b locks in the path (e.g. input buff ers) and the net or
wire delays. Once the design has been placed, routed and
timed, the Series 8000 timing tool can be used to calculate
the maximum possible delay for all paths. The actual delay
will be less than these values particularly under non-worst
case conditions. In most cases the delays on the clock and
data paths will track. However not all nets depend identi-
cally on the same physical properties (resistance, capaci-
tance, threshold voltage etc.) and hence not all delays will
track perfectly.
Extensive simulation and characterization has shown that
tracking between nets within one device will be better than
70%. To guarantee actual worst case setup and hold times,
the worst possible tracking should be assumed.
Therefore the formulae become:
Tsetup = Delaydata + TsetupCLC - 0.7* (Delayclock)
Thold = Delayclock + TholdCLC - 0.7* (Delaydata)
The user should use the 70% tracking factor when analyz-
ing and interpreting timing information.
Achieving a 0 ns hold time at the pin level is a common
requirement for FPGA designs. This entails having a data
path which is slower than the clock path, which may be dif-
ficult if the clock has high fanout. To facilitate 0 ns hold
times, an input buffer with additional delay (DBUF) is pro-
vided. This element has been designed to guar antee a 0 ns
hold time even for a very heavily loaded clock signal.
When using DBUF to achie ve 0 ns , the clock signal must be
driven by a B UFGP element and should drive no more than
24 FFs per row. All rows may be driven provided each row
contains a maximum of 24 FFs. If these conditions are met
then the 0 ns hold time is guaranteed and this guideline
supersedes the timing requirements indicated by the
Series 8000 tool.
If the extra setup delay needed for DBUF cannot be toler-
ated, then IBUF should be used. In this case, the user may
need to guarantee a positiv e hold time f or data with respect
to the clock for correct operation. The Series 8000 timing
requirements combined with the tracking factor should be
followed.
Description Symbol Device Min Max Units
Reset Switching Characteristics Guidelines
Delay from Master Reset pin high to device active
Low width on external MR pin
Delay from internal GRST to FF reset -5 V
Delay from internal GRST to FF reset -3.3 V
GRST input I width (High or Low) -5 V
GRST input I width (High or Low) -3.3 V
TMRQ
TMRW
TGRIQ
TGRIQ
TGRW
TGRW
5
45
60
3
90
120
ms
µs
ns
ns
ns
ns
Power-On Reset and Initalization Time
VCC above 2.5 V to device active. VCC must rise
monotonically. TPOR 3ms
XC8100 FPGA FamilyXC8100 FPGA Family
5-42 June 1, 1996 (Version 1.0)
Ordering Information
Product Availability (5/96)
Notes: Parentheses indicate future product plans
XC8106-1 PC84C
Device Type
Example:
Temperature
Range
Number of
Pins
Package
Type
Speed Grade
-1 Standard
-2 
-3
X5944
Note: Each Speed Grade can operate at 5 V or 3.3 V
Pins 44 44 84 100 160 225
Type Plastic VQFP Plastic PLCC Plastic PLCC Plastic PQFP Plastic PQFP Plastic BGFP
Code VQ44 PC44 PC84 PQ100 PQ160 BG225
XC8100-1 C C
XC8101-1 (C) (C) C C
XC8103-1 (C) C C C (C)
XC8106-1 C C (C) (C)
XC8109-1 C C C
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
SPROM Products
XC1700D Family of Serial Configuration PROMs
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Controlling Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
FPGA Master Serial Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Programming the XC1700 Family Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
XC1718D, XC1736D, XC1765D, XC17128D and XC17256D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
XC1718L, XC1765L, XC17128L and XC17256L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
DC Characteristics Over Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
AC Characteristics Over Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
SPROM Products Table of Contents
June 1, 1996 (Version 1.0) 6-1
Features
• Extended family of one-time programmable (OTP)
bit-serial read-only memories used for storing the
configuration bitstreams of Xilinx FPGAs
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmab le reset polarity (active High or activ e Low)
for compatibility with different FPGA solutions
• XC17128D or XC17256D supports XC4000 fast
configuration mode (12.5 MHz)
• Low-power CMOS EPROM process
• Available in 5 V and 3.3 V versions
• Available in plastic and ceramic packages, and
commercial, industrial and military temperature ranges
• Space efficient 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or
20-pin surface-mount packages.
• Programming support by leading programmer
manufacturers.
Description
The XC1700 family of serial configuration PROMs (SCPs)
provides an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that driv es the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disab les the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, the XACT development system
compiles the FPGA design file into a standard Hex for mat,
which is then transferred to the programmer.
XC1700D Family of
Serial Configuration PROMs
June 1, 1996 (Version 1.0) Product Specification
Figure 1: Simplified Block Diagram (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
RESET/
OE or
OE/
RESET
DATA
CEO
OE
Output
CLK
VCC VPP GND
X3185
TC
XC1700D Family of Serial Configuration PROMs
6-2 June 1, 1996 (Version 1.0)
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the D ATA pin is I/O. Note that OE can
be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the inter nal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all
devices. When RESET is active, the address counter is
held at zero, and the DATA output is 3-stated. The polarity
of this input is programmable. The default is active High
RESET, but the preferred option is active Low RESET,
because it can be driven by the FPGA’s INIT pin.
The polarity of this pin is controlled in the programmer inter-
face by writing data into four high-end byte locations. This
input pin is easily inv erted using the Xilinx PROM program-
mer software (XPP). Third-party programmers have differ-
ent methods to invert this pin.
For RESET/OE, fill the four polarity bytes with Ones or do
nothing.
For RESET/OE, fill these four bytes with Zeros.
CE
When High, this pin disables the internal address counter,
3-states the D ATA output, and forces the de vice into low-ICC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next SCP in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value . In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive , CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin
must
be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging.
Do not leav e
VPP floating!
VCC
Positive supply pin.
GND
Ground pin.
Serial PROM Pinouts
Capacity
plus 32 bits for reset polarity control
Number of Configuration Bits, Including Header
for all Xilinx FPGAs and Compatible SCP Type
Pin Name 8-Pin 20-Pin
DATA 1 2
CLK 2 4
RESET/OE (OE/RESET)36
CE 48
GND 5 10
CEO 614
V
PP 717
V
CC 820
Device Configuration Bits
XC1718D or L 18,144
XC1736D 36,288
XC1765D or L 65,536
XC17128D or L
XC17256D or L 131,072
262,144
Device Configuration Bits SCP
XC3020/A/L+3120A 14,819 XC1718D
XC3030/A/L+3130A 22,216 XC1736D
XC3042/A/L+3142A 30,824 XC1736D
XC3064/A/L+3164A 46,104 XC1765D
XC3090/A/L+3190A 64,200 XC1765D
XC3195A 94,984 XC17128D
XC4003E 53,976 XC1765D
XC4005E/L 95,000 XC17128D/L
XC4006E 119,832 XC17128D
XC4008E 147,544 XC17256D
XC4010E/L 178,136 XC17256D/L
XC4013E/L 247,960 XC17256D/L
XC4020E 329,304 XC17256D +
XC17128D
XC4025E 422,168 XC17256D +
XC17256D
XC5202 42,416 XC1765D
XC5204 70,704 XC17128D
XC5206 106,288 XC17128D
XC5210 165,488 XC17256D
XC5215 237,744 XC17256D
June 1, 1996 (Version 1.0) 6-3
Controlling Serial PROMs
Most connections between the FPGA de vice and the Serial
PROM are simple and self-explanatory.
• The D ATA output(s) of the of the Serial PR OM(s) driv es
the DIN input of the lead FPGA device.
• The master FPGA CCLK output drives the CLK input(s)
of the Serial PROM(s).
• The CEO output of a Serial PROM drives the CE input
of the next Serial PROM in a daisy chain (if any).
• The RESET/OE input of all Serial PROMs is best driven
by the INIT output of the XC3000 or XC4000 lead
FPGA device. This connection assures that the Serial
PROM address counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a VCC glitch. Other methods – such as
driving RESET/OE from LDC or system reset – assume
that the Serial PROM internal power-on-reset is always
in step with the FPGA’s internal power-on-reset, which
may not be a safe assumption.
• The CE input of the lead (or only) Serial PROM is driven
by the DONE/PRGM or DONE output of the lead FPGA
device, provided that DONE/PRGM is not permanently
grounded. Otherwise, LDC can be used to drive CE, b ut
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Logic Cell Arra y and their
associated interconnections are established by a configu-
ration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an
external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial Mode whenev er all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the Serial Configuration PROM sequentially on a single
data line. Synchronization is provided by the rising edge of
the temporary signal CCLK, which is generated during con-
figuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the Ser ial Con-
figuration PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configur ation, it must still be held at a
defined level during normal operation. The XC3000 and
XC4000 families take care of this automatically with an on-
chip default pull-up resistor. With XC2000-family devices,
the user must either configure DIN as an active output, or
provide a defined level, e.g., by using an external pull-up
resistor, if DIN is configured as an input.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low. Upon power-up, the internal address counters
are reset and configuration begins with the first program
stored in memory. Since the OE pin is held Low, the
address counters are left unchanged after configuration is
complete. Therefore, to reprogram the FPGA with another
program, the D/P line is pulled Low and configuration
begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restar ts a new configuration, as intended, but the
Serial PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configura-
tion, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (24) and D/P goes High. However,
the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded SCPs provide additional memory. After the last bit
from the first SCP is read, the next clock signal to the SCP
asserts its CEO output Low and disables its DATA line. The
second SCP recognizes the Low level on its CE input and
enables its DATA output. See Figure 2.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the FPGA RESET pin goes
Low, assuming the SCP reset polarity option has been
inverted.
To reprogram the FPGA with another progr am, the D/P line
goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
XC1700D Family of Serial Configuration PROMs
6-4 June 1, 1996 (Version 1.0)
Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs . Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
* If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series With M1
During Configuration
the 5 kΩ M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be User I/O. General-
Purpose
User I/O
Pins
Other
I/O Pins
M2
HDC
LDC
INIT
RESET
DIN
CCLK
INIT
D/P SCP
DATA
CEO
CLK
CE
OPTIONAL
Slave FPGAs
with Identical
Configurations
+5 V
*
M0 M1 PWRDWN
XC3000
FPGA
Device
(Low Resets the Address Pointer)
•
•
•
•
•
+5 V
V
CC
V
PP
RESET
X5090
Cascaded
Serial
Memory
DATA
CLK
CE
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
DOUT
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
OE/RESET OE/RESET
June 1, 1996 (Version 1.0) 6-5
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asser ted High. The output remains in a high imped-
ance state regardless of the state of the OE input.
(A technique for further reducing the standby current of a
Serial Configuration PROM is described in the XCELL jour-
nal, Issue 11, page 13.)
Programming the XC1700 Family
Serial PROMs
The devices can be prog rammed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and
voltages are used. Different product types use different
algorithms and voltages, and the wrong choice can perma-
nently damage the device.
Notes: 1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC+1 = address 0.
IMPORTANT: Always be sure to use the proper programming algorithm. “D” series PROMs will not program properly using
“A” -series algorithms. Always tie the VPP pin to VCC in your application. Never leave VPP floating.
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs Internal Address Outputs
RESET CE DATA CEO Icc
Inactive Low if address < TC: increment
if address > TC: don’t change active
3-state High
Low active
reduced
Active Low Held reset 3-state High active
Inactive High Not changing 3-state High standby
Active High Held reset 3-state High standby
Table 2: Data I/O Programmer Locations for Programming RESET Polarity
Device Hex Address
XC1718D or L 8DC through 8DF
XC1736D 11B8 through 11BB
XC1765D or L 2000 through 2003
XC17128D or L 4000 through 4003
XC17256D or L 8000 through 8003
XC1700D Family of Serial Configuration PROMs
6-6 June 1, 1996 (Version 1.0)
XC1718D, XC1736D, XC1765D, XC17128D and XC17256D
Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Operating Conditions
DC Characteristics Over Operating Condition
Note: During normal read operation VPP
must
be connected to VCC
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VPP Supply voltage relative to GND -0.5 to +12.5 V
VIN Input voltage relative to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +125 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
Symbol Description Min Max Units
VCC Commercial Supply voltage relative to GND 0°C to +70°C junction 4.75 5.25 V
Industrial Supply voltage relative to GND -40°C to +85°C junction 4.50 5.50 V
Military Supply voltage relative to GND -55°C to +125°C case 4.50 5.50 V
Symbol Description Min Max Units
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = -4 mA) Commercial 3.86 V
VOL Low-level output voltage (IOL = +4 mA) 0.32 V
VOH High-level output voltage (IOH = -4 mA) Industrial 3.76 V
VOL Low-level output voltage (IOL = +4 mA) 0.37 V
VOH High-level output voltage (IOH = -4 mA) Military 3.7 V
VOL Low-level output voltage (IOL = +4 mA) 0.4 V
ICCA Supply current, active mode 10.0 mA
ICCS Supply current, standby mode, XC17128D, XC17256D 50.0 µA
Supply current, standby mode, XC1718D, XC1736D, XC1765D 1.5 mA
ILInput or output leakage current -10.0 10.0 µA
June 1, 1996 (Version 1.0) 6-7
XC1718L, XC1765L, XC17128L and XC17256L
Absolute Maximum Ratings
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Operating Conditions
DC Characteristics Over Operating Condition
Note: During normal read operation VPP
must
be connected to VCC
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +6.0 V
VPP Supply voltage relative to GND -0.5 to +12.5 V
VIN Input voltage with respect to GND -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C
Symbol Description Min Max Units
VCC Commercial Supply voltage relative to GND 0°C to +70°C junction 3.0 3.6 V
Symbol Description Min Max Units
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = -4 mA) 2.4 V
VOL Low-level output voltage (IOL = +4 mA) 0.4 V
ICCA Supply current, active mode 5.0 mA
ICCS Supply current, standby mode, XC1718L, XC1765L
Supply current, standby mode, XC17128L, XC17265L 1.5
50.0 mA
µA
ILInput or output leakage current -10.0 10.0 µA
XC1700D Family of Serial Configuration PROMs
6-8 June 1, 1996 (Version 1.0)
AC Characteristics Over Operating Condition
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ac load and maximum dc load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
RESET/OE
CE
CLK
DATA
1
TCE
2
TOE
TLC
7
9 TSCE TSCE THCE
THOE
11
TCAC TOH TDF
5
TOH
4
43
910
THC
8
X2634
TCYC
6
Symbol Description
XC1718D
XC1736D
XC1765D
XC1718L
XC1765L XC17128D
XC17256D XC17128L
XC17256L Units
Min Max Min Max Min Max Min Max
1T
OE OE to Data Delay 45 45 25 30 ns
2T
CE CE to Data Delay 60 60 45 60 ns
3T
CAC CLK to Data Delay 150 200 50 60 ns
4T
OH Data Hold From CE, OE, or CLK0000ns
5T
DF CE or OE to Data Float Delay250 50 50 50 ns
6T
CYC Clock Periods 200 400 80 100 ns
7T
LC CLK Low Time3100 100 20 25 ns
8 THC CLK High Time3100 100 20 25 ns
9 TSCE CE Setup Time to CLK (to guarantee
proper counting) 25 40 20 25 ns
10 THCE CE Hold Time to CLK (to guarantee
proper counting) 000 0 ns
11 THOE OE Hold Time (guarantees counters are
reset) 100 100 20 25 ns
June 1, 1996 (Version 1.0) 6-9
AC Characteristics Over Operating Condition (continued)
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ac load and maximum dc load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
Symbol Description
XC1718D
XC1736D
XC1765D
XC1718L
XC1765L XC17128D
XC17256D XC17128L
XC17256L Units
Min Max Min Max Min Max Min Max
12 TCDF CLK to Data Float Delay250 50 50 50 ns
13 TOCK CLK to CEO Delay 65 65 30 30 ns
14 TOCE CE to CEO Delay 45 45 35 35 ns
15 TOOE RESET/OE to CEO Delay 40 40 30 30 ns
RESET/OE
CLK
DATA
CE
15 TOOE
CEO
First Bit Last Bit
TOCE
13 TOCK
12 TCDF
X3183
14
TOCE
14
XC1700D Family of Serial Configuration PROMs
6-10 June 1, 1996 (Version 1.0)
Ordering Information
Valid Ordering Combinations
Marking Information
Due to the small size of the serial PROM package, the complete ordering par t number cannot be marked on the package.
The XC prefix is deleted and the package code is simplified. Device marking is as follows.
XC17128DPD8C XC1718DPD8C XC17256DPD8C XC1736DPD8C XC1765DPD8C
XC17128DVO8C XC1718DSO8C XC17256DVO8C XC1736DSO8C XC1765DSO8C
XC17128DPC20C XC1718DVO8C XC17256DPC20C XC1736DVO8C XC1765DVO8C
XC17128DPD8I XC1718DPC20C XC17256DPD8I XC1736DPC20C XC1765DPC20C
XC17128DVO8I XC1718DPD8I XC17256DVO8I XC1736DPD8I XC1765DPD8I
XC17128DPC20I XC1718DSO8I XC17256DPC20I XC1736DSO8I XC1765DSO8I
XC17128DDD8M XC1718DVO8I XC17256DDD8M XC1736DVO8I XC1765DVO8I
XC1718DPC20I XC17256DDD8B XC1736DPC20I XC1765DPC20I
XC1736DDD8M XC1765DDD8M
XC1765DDD8B
XC17128LPD8C XC1718LPD8C XC17256LPD8C XC1765LPD8C
XC17128LVO8C XC1718LSO8C XC17256LVO8C XC1765LSO8C
XC17128LPC20C XC1718LVO8C XC17256LPC20C XC1765LVO8C
XC17128LPD8I XC1718LPC20C XC17256LPD8I XC1765LPC20C
XC17128LVO8I XC1718LPD8I XC17256LVO8I XC1765LPD8I
XC17128LPC20I XC1718LSO8I XC17256LPC20I XC1765LSO8I
XC1718LVO8I XC1765LVO8I
XC1718LPC20I XC1765LPC20I
XC1736D - PC20 C
Operating Range/Processing
C = Commercial (0° to +70°C)
I = Industrial (–40° to +85°C)
M = Military (–55° to +125°C)
B = Military (–55° to +125°C)
MIL-STD-883 Level B compliant
Package T ype
PD8 = 8-Pin Plastic DIP
DD8 = 8-Pin CerDIP
SO8 = 8-Pin Plastic Small-Outline Package
VO8 = 8-Pin Plastic Small-Outline Thin Package
PC20 = 20-Pin Plastic Leaded Chip Carrier
Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L
1736D P C
Operating Range/Processing
C = Commercial (0° to +70°C)
I = Industrial (–40° to +85°C)
M = Military (–55° to +125°C)
B = Military (–55° to +125°C)
MIL-STD-883 Level B compliant
Package T ype
P = 8-Pin Plastic DIP
D = 8-Pin CerDIP
S = 8-Pin Plastic Small-Outline Package
V = 8-Pin Plastic Small-Outline Thin Package
J = 20-Pin Plastic Leaded Chip Carrier
Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
3V Products
3.3 V and Mixed Voltage Compatible Products
FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L, XC8100 . . . . . . . . . . . . . 7-1
3 V PCI-Compliant FPGA: XC3100L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL. . . . . . . . . . . . . . . . . . . . . 7-1
High-Density FPGAs Without On-chip RAM: XC5200L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
5 V Compatible Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
One-Time-Programmable FPGAs: XC8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX . . . . . . . . . . . . . . . . 7-1
CPLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Supply Voltage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Interfacing Between 5 V and 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
3.3 V Devices Driving Inputs on 5 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
5 V Devices Driving Inputs on 3.3 V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
XC4000E/EX is Fully Compatible With 3.3 V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
3V Products Table of Contents
June 1, 1996 (Version 1.0) 7-1
In anticipation of the market shift from 5 V to 3.3 V products,
Xilinx introduced the Zero+ product line, the industry’s first
3.3 V FPGAs, in 1993. The number of 3.3 V product offer-
ings has since tripled and includes high-performance
devices with system clock speeds of 85 MHz, high-density
devices, and mixed-voltage devices.
Complete data sheets for the products mentioned below
can be found in Chapters 3, 4, and 5 of this Data Book.
3.3 V versions of the Serial PROM devices also are avail-
able (see Chapter 6).
FPGAs
The Zero+ Family of Ultra Low Power
Devices: XC3000L, XC4000L, XC8100
The Zero+ Product Line includes three major families: the
XC3000L, XC4000L and XC8100 FPGAs. These devices
have quiescent supply currents below 1mA, with some
below 50 µA. This is important in systems where prolonged
battery life is critical.
3 V PCI-Compliant FPGA: XC3100L
The XC3100L is the highest performance 3.3 V FPGA, and
is the only 3.3 V FPGA f amily that meets the stringent spec-
ifications of 3.3 V PCI applications.
High-Density FPGAs With On-Chip RAM:
XC4000L and XC4000XL
Ranging from 5,000 to over 60,000 gates, the XC4000L
and XC4000XL FPGA families represent the broadest 3.3 V
product line in the industry.
High-Density FPGAs Without On-chip RAM:
XC5200L
The XC5200L family features 5 V compatible inputs and
densities from 2,000 to 23,000 gates.
5 V Compatible Inputs on 3.3 V Devices
Conventional 3.3 V device inputs cannot or should not be
driven substantially higher than 3.6 V. The new XC5200L
inputs can, howe v er , be driven up to 5.5 V, provided that the
5 V supply v oltage is connected to one dedicated bias sup-
ply pin, called VTT, on the 3.3 V device.
All Xilinx device inputs maintain their excellent protection
against Electro-Static Discharge (ESD), typically 10,000 V,
even in mixed-voltage applications.
One-Time-Programmable FPGAs: XC8100
The XC8100 family consumes very low quiescent current
when operating at 3.0 to 3.6 V. Thus, the feature-rich
XC8100 is an excellent candidate for use in por table and
hand-held applications.
5 V SRAM FPGAs for Mixed-Voltage
Systems: XC4000E and XC4000EX
While the market slowly shifts from 5V systems to 3.3V sys-
tems, a need exists for devices to function in dual environ-
ments. The 5 V XC4000E and XC4000EX FPGA families
feature a unique output structure which makes them suit-
able for mixed-voltage system applications. When config-
ured in TTL mode, the XC4000E and XC4000EX can be
directly mixed with 3.3 V devices without the aid of external
components such as current limiting resistors. This is
described in more detail under, “Interfacing Between 5 V
and 3.3 V Devices” on page 7-2.
CPLDs
5 V CPLDs for Mixed-Voltage Systems:
XC7300 and XC9500
Xilinx CPLDs are an excellent fit for 5 V only and mixed-
voltage systems. The Input/Output (I/O) ring can be pow-
ered by either a 5 V VCCIO or a 3.3 V VCCIO. Independent of
the VCCIO voltage le v el, the inputs can accept 5 V and 3.3 V
inputs. The rail-to-rail output level is defined by VCCIO.
These single-chip solutions function extremely well in
mixed-voltage systems without any performance penalty.
3.3 V and Mixed Voltage
Compatible Products
June 1, 1996 (Version 1.0)
3.3 V and Mixed Voltage Compatible Products
7-2 June 1, 1996 (Version 1.0)
Supply Voltage Options
Notes: 1. Provided VTT pin is connected to 5 V supply.
2. Initial XC4000XL devices do not ha v e 5 V tolerant inputs. Future XC4000XL de vices will ha v e 5 V tolerant inputs. Contact the
factory.
Interfacing Between 5 V and 3.3 V Devices
This section discusses the compatibility issues between
devices with diff erent supply voltages , and explains ho w 5 V
XC4000E/EX devices are directly compatible with 3.3 V
devices.
In the past, almost all digital logic devices used a 5 V supply
voltage. To reduce chip size and meet the demand for
higher integration and lower power consumption, the semi-
conductor industry has started the transition to 3.3 V logic.
In the future, 3.3 V will become the dominant supply volt-
age. Today, many designs must accommodate both types
of ICs on the same board. Since both types of supply share
a common ground, there are no problems interfacing logic
Low levels in either direction, but there are compatibility
issues for the logic High levels.
3.3 V Devices Driving Inputs on 5 V Devices
The lowest output High v oltage (VOH) of the 3.3 V device must
exceed the VIH requirements of the 5 V device. This is not a
problem if the 5 V de vice uses TTL-compatib le input thresholds,
available on all Xilinx devices. If, however, the 5 V device has
CMOS input thresholds, an external pull-up resistor to 5 V on
each such input will assure a sufficiently high input voltage . The
resistor should be somewhere between 10 kΩ and 1 kΩ in
value. The upper limit causes the rising input transition to be
slow; the lower limit is set by the output current sinking capabil-
ity of the 3.3 V device output. In the High state, the voltage will
be clamped by the ESD protection diode of the 3.3 V de vice, as
described later in this application note. With less than 1.5 V
across this resistor, the current will be fairly small, but care
should be taken that the sum of these pull-up currents does not
exceed the 3.3 V supply current, thereby reverse-biasing the
power supply and raising the 3.3 V supply voltage to an unde-
fined lev el (b ut ob viously lo wer than the 5 V VCC min us a diode
drop of ~0.7 V).
5 V Devices Driving Inputs on 3.3 V Devices
The highest 5 V device output voltage must not force exces-
sive current into the input of the 3.3 V de vice. If the 5 V de vice
has a truly complementary CMOS output (like all Xilinx
FPGAs and CPLDS except the XC4000 family devices
have), then the input current must be limited by a series
resistor of no less than 150 Ω. This guarantees an input cur-
rent below 10 mA, flowing through the ESD input protection
diode backwards into the 3.3 V supply. That amount of input
current is generally considered safe, causing neither metal
migration nor latch-up problems. Care must be taken to
avoid forcing the nominally 3.3 V supply voltage above its
3.6 V maximum whenever a large number of active High
Availability
Single
3.3 V
Supply
Single
5 V
Supply Dual
Supply
Mixed-Voltage Applications
Key Features
Core VCC = 5 V
I/O VCC = 3.3 V
Inputs are 5 V
Compatible
VCC = 5 V
Inputs are
3.3 V
Compatible
VCC = 3.3 V
Inputs are
5 V
Compatible1
Reconfigurable
FPGAs Yes
XC3000A Now Yes Low quiescent current
XC3000L Now Yes µA powerdown current and
µA quiescent current
XC3100A Now Yes Yes Highest performance 5 V FPGA
XC3100L Now Yes Highest performance 3.3 V FPGA
XC4000E Now Yes Yes Mixed voltage system capable
XC4000L Now Yes High Density 3.3 V FPGAs
XC4000EX 2H96 Yes Yes Mixed voltage system capable
XC4000XL 2H96 Yes Note 2 Note 2 Highest Density 3.3 V FPGA
XC5200 Now Yes Yes Best value and broadest density
FPGAs
XC5200L 4H96 Yes Yes Yes Best 3.3 V FPGA value
OTP FPGAs
XC8100 Now Yes Yes Yes 1. Hundreds of µA quiescent current.
2. Design security
CPLDs
XC7300 Now Yes Yes Yes Yes Mixed voltage system capable
XC9500 2H96 Yes Yes Yes Yes Mixed voltage system capable
June 1, 1996 (Version 1.0) 7-3
inputs drive the 3.3 V device, potentially causing the 3.3 V
supply current to go negative.
If the 5 V device has “totem-pole” n-channel-only outputs,
VOH is reduced by one threshold and the series resistor
can be eliminated, provided the nominally 5 V supply does
not exceed 5.25 V. This is described in detail in the f ollowing
section.
XC4000E/EX is Fully Compatible With 3.3 V
Logic
As a default option, all XC4000E/EX have a TTL-like input
threshold (compatible with 3.3 V output levels) and an n-
channel-only “totem-pole” or TTL-like output structure with
an n-channel transistor pulling the output to a VOH level
that is one threshold below VCC.
At a nominal 5.0 V VCC, the unloaded output High voltage
VOH is <3.7 V. When applied to the input of a device with a
nominal 3.3 V VCC, there is no additional input current, and
the input level does not violate the conventional specifica-
tion that prohibits input voltages more than 0.5 V above
VCC. See Figure 1.
If both 5 V and 3.3 V supply voltages track reasonably
between their max and min values, there will never be any
additional input current in excess of 1 µA at any commercial
or industrial operating temperature.
A worst-case analysis of the interface might assume the
(unrealistic) condition where the 5 V supply is at its max
value (5.25 V for commercial applications), while the
3.3 V supply is at its min value of 3.0 V. Under these
conditions, the interface violates the conventional spec-
ification, and drives current into the input of the 3.3 V
device, as shown in figure 2. The following paragraphs
explain that this interface is nevertheless reliable.
For protection against electro-static discharge (ESD), all
CMOS inputs and I/O pins usually have a diode between
the pin and the nearest VCC connection. This diode pre-
vents the input from going substantially more positive than
VCC, which might destroy the input transistor by rupturing
its gate oxide. At room temperature, this ESD protection
diode conducts negligible current at < 0.6 V forward bias,
and conducts ~1 mA at ~0.7 V forward bias, typical for any
silicon junction diode. These voltages have a predictable
negative temper ature coefficient of –2 mV per deg ree C. At
85 degrees C, these voltages are, therefore 120 mV lower.
Figure 1 superimposes the output characteristic of the
XC4000E/EX and the input current characteristic of a typi-
cal 3.3 V device input. Both supply voltages are at their
nominal value, but the die temperatures are at their worst-
case value of 85 degrees C, and worst-case processing is
assumed.
Figure 2 shows the same curves, but with 5.25 V and 3.0 V
VCC respectively. The intersection of the tw o curves defines
the worst-case operating point of 3.8 V and 6 mA. That
means that the XC4000E output drives 6 mA into the for-
ward-biased ESD protection diode, r aising the input voltage
0.8 V above 3.0 V, the assumed lowest value of the nomi-
nally 3.3 V supply voltage.
1
3.0 3.3 3.5 4.0 4.5 5.0 5.5
2
3
4
5
6
7
8
9
10
I
mA
VCC
IOUT
IIN
Nominal 
Supply Voltages
85°C
X5969
Figure 1: XC4000E Output in “TTL-Mode” driving
3.3 V Device Input with Both Supplies at Nominal
Voltage (5.0 V and 3.3 V)
1
2
3
4
5
6
7
8
9
10
I
mA
3.0 3.5 4.0 4.5 5.0 5.5VCC
IOUT
IIN
X5970
Figure 2: XC4000E Output in “TTL-Mode” driving
3.3 V Device Input with Both Supplies at Extreme
Values (5.25 V and 3.0 V)
3.3 V and Mixed Voltage Compatible Products
7-4 June 1, 1996 (Version 1.0)
Although this input condition is not covered by the conven-
tional specification, it does not cause any harm and does
not affect reliability. ESD protection diodes are designed to
conduct hundreds of mA, and the absolute value of the
input voltage with respect to g round will nev er e xceed 3.9 V.
If the input pin is par t of an I/O structure, there is theoreti-
cally possibility of causing latch-up, but all reputable IC
manufacturers design their circuits such that latch-up does
not occur below 100 mA of input current per pin.
The system designer must estimate the sum of all maxi-
mum input currents, and calculate the impact of this current
flowing bac kw ards to w ards the 3.3 V supply. But even if the
total 3.3 V supply current goes to zero, VCC for the 3.3 V
device is still limited to < 3.6 V (the highest output voltage of
the 5 V device minus the forward voltage drop of the ESD
diode).
Conclusion
5 V XC4000E/EX devices can be freely mixed with 3.3 V
devices, without any current or voltage limiting interface
resistors, if the following conditions are met:
• The 5 V XC4000E/EX devices are in their default “TTL
mode” with respect to input thresholds and output
levels.
• The upper limit on the 5 V VCC is 5.25 V and the lower
limit on the 3.3 V supply is 3.0 V, as per standard
commercial specifications.
• For industrial operating conditions with higher Vcc max,
the user must make sure that the absolute difference
between the two supply v oltages does not exceed 2.20 V.
Specifically, if the nominally 5 V VCC is at its max v alue of
5.50 V, the nominally 3.3 V VCC must not be lower than
3.30 V.
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
HardWire Products
Xilinx HardWire™ Array Overview
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Advantages of Using Xilinx HardWire Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
HardWire versus Full ASIC Gate Array Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Reverifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Fault Coverage and Test Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Packaging and Silicon Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Support for the Entire Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
The HardWire Product Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
HardWire Products Table of
Contents
June 1, 1996 (Version 1.0) 8-1
Features
• Mask-programmed versions of Xilinx programmable
devices
- Specifically designed for easy conversions
- Significant cost reduction for high-volume
applications
- Same specifications and architecture as the
programmable devices
- On-chip scan path test registers
- High-performance CMOS process
• Easy conversion with guaranteed results
- “Design Once Methodology” requires no customer
engineering resources for conversion
- Fully pin-for-pin compatible with the programmable
device
- Support for most popular package types
- PLD database file used to generate production-
ready prototypes
- Automatic test vector generation with >95% fault
coverage
- Prototypes built on production line
The following is an overview of the Xilinx HardWire device
product line. Product specifications for the HardWire
devices and additional infor mation are available in a sepa-
rate publication - The HardWire Data Book.
HardWire Arrays are mask-programmed versions of the
popular XC2000, XC3000, XC4000, XC5000, and XC8000
series FPGAs, as well as the XC9500 CPLDs. The Hard-
Wire devices provide a transparent migration path from a
programmable logic device to a cost-reduced device with-
out the engineering burden associated with conventional
gate-array re-design.
In standard programmable logic, the functions and inter-
connections are determined by configuration data stored in
memory cells. In the HardWire components, the memory
cells and the logic they control are replaced by metal con-
nections. All other circuitry in the HardWire de vices is iden-
tical to the corresponding programmable logic’s internal
circuitry. Thus, a HardWire device is a semicustom device
manuf actured to pro vide a specific functionality, yet is com-
pletely compatible with the programmable device it
replaces.
Advantages of Using Xilinx
HardWire Arrays
Xilinx offers an easy, seamless process for achieving the
shortest Time-to-Volume solution possible. Simply stated,
our unique Design Once methodology allows engineers to
dev elop their design in a prog rammab le de vice, then s witch
to a lower cost mask-programmed product without utilizing
additional internal resources.
Production is often star ted using the same programmable
logic in which the application was designed. This flexibility
allows the product to be introduced to the market quickly.
Later in the production process, the PLD can be replaced
with a HardWire Array without expending additional engi-
neering time and effort to redesign either the FPGA’s circuit
or the printed circuit board. Other conversion methodolo-
gies introduce risk at each project milestone of the conver-
sion process. Only the Xilinx Design Once Methodology
can offer this no risk, 100% pin-for-pin compatible path to
dramatic cost reductions.
Whenever a system incorporating Xilinx PLDs ramps to
high production volumes, the HardWire mask-programmed
solution should be the first consideration f or cost reduction.
Because the HardWire implementation dramatically
reduces the die size by removing programmable elements,
the resulting device is much smaller than the equivalent
PLD. This smaller die provides a no-risk path to achieve
dramatic cost reductions.
HardWire versus Full ASIC Gate Array
Implementation
Converting a device from programmable logic to a Hard-
Wire Array has many advantages over generic gate array
redesign. The most important is that the Xilinx HardWire
methodology requires no additional customer engineering
to conv ert the programmab le logic design into a fully tested,
completely verified mask-programmed design.
This ease of conversion is available only through Xilinx
because the PLD database file is the actual physical data
base previously created and verified in the process of
developing the PLD design. Xilinx has the only methodol-
ogy that preserves all attributes of the original physical data
base file. If the design is mapped to a third party library for
conversion at the schematic level to another technology,
the design must be verified and prototyped. Third party
implementation will change the placement and routing,
thereby changing the design’s performance characteristics.
Xilinx HardWire™ Array Overview
June 1, 1996 (Version 1.0)
Xilinx HardWire™ Array Overview
8-2 June 1, 1996 (Version 1.0)
Thus, the revised device needs to be re-verified and re-
tested in the system to be certain both the functionality and
the performance still meet the application’s requirements.
A comparison of the activities required to convert a Hard-
Wire Array versus a standard array is shown in Figure 1.
Reverifying the Design
In conventional gate array conversion (redesign), the
design must be re-verified after the schematic is translated
or recaptured. The process of reverifying a design is r igor-
ous and time-consuming. Functional simulation vectors
need to be created, and the device must be exhaustively
simulated before and after place and route. A suitable test
methodology must be considered and implemented.
In contrast, no additional effort is required when con verting
to Xilinx HardWire Arrays. The HardWire design is self-ver-
ifying because the actual PLD database file is used for the
conversion.
Fault Coverage and Test Vectors
All designs need to be testable. In a traditional mask-pro-
grammed gate array, the designer is required to build in
testability and generate test vectors that verify chip perfor-
mance by exercising as much of the device’s circuitry as
possible. Most designers strive for greater than 95% fault
coverage. However, they often settle for significantly less
because the iterative process is extremely time consuming
and increases exponentially as fault coverage is increased.
Any third-party conversion from a Xilinx FPGA or CPLD to a
gate arra y or other similar technology will require test vector
generation. Typically, the or iginal designers create the test
vectors, since they are most familiar with the design imple-
mentation. This method ties up valuable design resources
and reverses the value of the original decision to use pro-
grammable logic for their ease of design and time-to-mar-
ket advantages. Another alternative is to contract with the
conversion or gate array vendor to create the test vectors.
This method can be both time-consuming and expensive,
since vendors usually charge by the v ector. In some cases ,
conversion or gate array vendors will accept a design with-
out test vectors, but the customer accepts all the liability of
determining whether the resulting device is production wor-
thy. In today’s competitive market, many projects can not
afford the risk of possib le respins if the design doesn’t work.
Converting from a Xilinx programmable to a HardWire
device requires no test v ector generation. Xilinx guarantees
greater than 95% fault coverage through a proprietary
Automatic Test Vector Generation methodology. All Hard-
Wire Arra ys are 100% fully guaranteed to work in the user’ s
application exactly like the programmable logic.
• Convert netlist to G/A format
• Logic changes for design compatibility
• Logic changes for pin compatibility
• Logic changes for configuration emulation
• Logic changes for Boundary Scan
• Design Check
• Functional Simulation
• Place and Route
• Back-Annotation
• Timing simulation and new models
• Test Vector generation
• Create 2-4 custom masks
Generic Gate Array
Working Xilinx FPGA Design
• Design Check
• Design Conversion
• Custom Mask
Xilinx HardWire Array
X5945
Figure 1: Steps Involved in Converting a PLD Design to a Gate Array as Compared to a Hard Wire Array
June 1, 1996 (Version 1.0) 8-3
Packaging and Silicon
Considerations
All of the physical attrib utes of the HardWire Arrays are vir-
tually identical to the programmable logic devices. Xilinx
uses the same qualified fabrication facilities for both the
PLD and HardWire devices. The same IC process, as well
as packaging, assembly, and test facilities, are used. This
allows users to circumvent costly and time-consuming
requalification efforts.
Conv erting from a Xilinx programmable logic de vice to an y-
thing but a Xilinx HardWire Array means a change to sili-
con, packaging, assemb ly and test. Each of these changes
adds an element of risk into the qualification process.
Support for the Entire Product Life Cycle
Figure 2 shows the typical life cycle of a high-volume prod-
uct, and illustrates the optimal way for using the program-
mable and HardWire devices.
During the development, prototype, and initial production
stages, the programmable device is the best choice. Later
in the life-cycle, when the design is stable and in high vol-
ume production, the HardWire Array can be used in place
of the original programmable device.
Since the circuit board was designed initially f or a progr am-
mable device, production can be switched back from the
HardWire Array to the programmable device if the situation
warrants . For example, if demand f or the product increases
dramatically, production can be increased in days or weeks
by using programmable devices. In addition, a change can
be quickly made to the product, since there is no manufac-
turing lead-time for an off-the-shelf programmable device.
Production can be switched to programmable devices as
the product nears the end of the life cycle, a voiding end-of-
life buys and the risk of obsolescence.
Furthermore, designs implemented with multiple static
RAM-based FPGAs can be cost reduced incrementally,
converting one or more of the programmable devices while
leaving the others for future conversion. As each PLD is
converted to a Xilinx HardWire Array, the user enjoys a
lower cost f or that unit, while maintaining the ease-of-use of
off-the-shelf programmable logic in the other sockets.
When all of the devices are con verted, the storage element
can then be removed, giving even further cost reductions.
This flexibility is unique to Xilinx, and allows OEMs to
achieve cost reductions quickly with minimal effort.
The HardWire Product Series
As listed in Table 1, the HardWire product chart, there is a
range of products available for Xilinx FPGAs and XC9500
CPLDs. For designs developed using the Xilinx XC4000
family, there are two HardWire options. The XC4400 family
is based on Xilinx advanced technology. It is most benefi-
cial for higher volume applications, as well as XC4000E
designs utilizing Xilinx’s Select-RAM™ features, and low
power 3.3 volt designs. For an application with low annual
volumes (as low as 1500 units) and where a low NRE is
required, the XC4300 family pro vides the best fit. Xilinx also
supports the low-power 3.3 volt XC2000L and XC3000L.
X5946
Production
Ramp-Up
End-of-Life
HardWire
Array
V
O
L
U
M
E
Unplanned Upside
Programmable Logic Volume
HardWire Array Volume
Figure 2: Typical High Volume Product Life Cycle
Xilinx HardWire™ Array Overview
8-4 June 1, 1996 (Version 1.0)
Notes: 1. Industrial temperature grades are available for all products.
2. The XC4300 supports the XC4000 design features. The XC4400 supports both the XC4000 and XC4000E design features.
Table 1: HardWire Product Chart1
PLD Family H/W Equivalent Minimum Order
Quantity (KU) Minimum
Shipment (KU) Production
Availability
XC2000 XC2300 7 2
Now
XC3000/A XC3330 10 2
XC3100A XC3342 6 1
XC3390 4 0.5
XC3195 XC4495T 10 2
XC4000/E2
XC4303 6 2
XC4305 4 1
XC4310 1.5 0.4
XC4313 1.5 0.4
XC4403/H 10 2
XC4405/H 10 2
XC4406 5 1
XC4408 5 1
XC4410 5 1
XC4413 3.5 0.5
XC4425 2.5 0.5
XC4000EX
XH4028EX 2.5 0.5 Q4/96
XH4036EX 2.5 0.5 Q4/96
XH4044EX 2.5 0.5 Q1/97
XH4052EX 2.5 0.5 Q1/97
XH4062EX 2.5 0.5 Q1/97
XC5200
XC5402 10 2
Now
XC5404 10 2
XC5406 5 1
XC5410 5 1
XC5415 3.5 0.5
XC8100 XH8103 10 2
XH8106 10 2
XH8109 6 1
XC9500
XC95144 10 10
Q2/97
XC95180 10 10
XC95216 10 10
XC95288 10 10
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Military Products
High-Reliability and Military Products
Unmatched Hi-Rel Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Committed to the Hi-Rel Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Xilinx Hi-Rel Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Military Products Table of Contents
June 1, 1996 (Version 1.0) 9-1
Xilinx is the world’s leading supplier of High-Reliability Pro-
grammable Logic Devices (Hi-REL PLDs) to the aero-
space, military, defense electronics, and related markets.
These devices are being used in a wide variety of pro-
grams, including applications such as electronic warfare,
missile guidance and targeting, RADAR/SONAR, commu-
nications, signal processing, aerospace and avionics.
Unmatched Hi-Rel Product Offering
Xilinx offers a wide variety of de vices, deliv ering the fastest
and biggest Hi-Rel devices available. Products with up to
25,000 gates are av ailable toda y, with ev en higher densities
to come. Xilinx offers multiple product families to allow you
to select the right device to meet y our design requirements.
This broad range of de vices is av ailable in a wide v ariety of
speed and package options. Both military temperature
range and full MIL-STD-883B/SMD versions are available
as standard, off-the-shelf products, in through-hole and
surface mount packages.
Committed to the Hi-Rel Market
Xilinx understands that you need to be able to count on
your Hi-Rel supplier. Xilinx is committed to our customers,
and we are e xpanding our Hi-Rel support and product port-
folio. The unique capabilities of the Xilinx FPGA solution
provide increased design flexibility, field-upgradability and
system feature integration, while eliminating the NREs,
lead-time and inventory problems of custom logic and gate
arra ys . Now more than e v er, Xilinx is your Hi-Rel logic solu-
tion.
Xilinx Hi-Rel Products
Table 1 summarizes Xilinx high density and high perfor-
mance product offerings. The following pages contain a
complete listing of current Xilinx SMD (Standard Microcir-
cuit Drawings) devices and “B” gr ade equiv alents. Architec-
tural descriptions for these FPGA products can be found in
Chapter 4. For additional information, including Data
Sheets on Hi-Rel devices, contact the nearest Xilinx Sales
Office or Sales Representative.
High-Reliability and Military
Products
June 1, 1996 (Version 1.0)
Table 1: High Density and High Performance Products
Family Devices Features
XC4000/E XC4003A
XC4005/E
XC4010/E
XC4013/E
XC4025E
Highest Density/Most Features Family
• 3,000-25,000+ gates
• Up to 256 user-definable I/Os
• Extensive system features include on-chip user RAM, built-in 1149.1
test support and fast carry logic
XC3100A XC3142A
XC3190A
XC3195A
Highest Performance Family
• 2,500-7,500 gates
• Up to 144 user-definable I/Os
High-Reliability and Military Products
9-2 June 1, 1996 (Version 1.0)
Table 2: Xilinx SMD (Standard Microcircuit Drawing)
XC1700 Products
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-9471701MPA XC1765DDD8B DD8 TOP
5962-9561701MPA XC17256DDD8B DD8 TOP
XC2000 Products
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-8863801XC XC2018-33PG84B -33 PG84 TOP
5962-8863802XC XC2018-50PG84B -50 PG84 TOP
5962-8863803XC XC2018-70PG84B -70 PG84 TOP
5962-8863804XC XC2018-100PG84B -100 PG84 TOP
XC3000 Products
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-8994801MXC XC3020-50PG84B -50 PG84 TOP
5962-8994802MXC XC3020-70PG84B -70 PG84 TOP
5962-8994803MXC XC3020-100PG84B -100 PG84 TOP
5962-8994801MNC XC3020-50CB100B -50 CB100 BASE
5962-8994802MNC XC3020-70CB100B -70 CB100 BASE
5962-8994803MNC XC3020-100CB100B -100 CB100 BASE
5962-8994801MMC -50 CB100 LID
5962-8994802MMC -70 CB100 LID
5962-8994803MMC -100 CB100 LID
5962-8994801MYA* XC3020-50CQ100B -50 CQ100 BASE
5962-8994802MYA* XC3020-70CQ100B -70 CQ100 BASE
5962-8994803MYA* XC3020-100CQ100B -100 CQ100 BASE
5962-8994801MTA* -50 CQ100 LID
5962-8994802MTA* -70 CQ100 LID
5962-8994803MTA* -100 CQ100 LID
* Do Not Use for New Designs (package to be obsoleted). Use “CB” Package Instead.
June 1, 1996 (Version 1.0) 9-3
XC3000 Products (continued)
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-8971301MXC XC3042-50PG84B -50 PG84 TOP
5962-8971302MXC XC3042-70PG84B -70 PG84 TOP
5962-8971303MXC XC3042-100PG84B -100 PG84 TOP
5962-8971301MZC XC3042-50PG132B -50 PG132 TOP
5962-8971302MZC XC3042-70PG132B -70 PG132 TOP
5962-8971303MZC XC3042-100PG132B -100 PG132 TOP
5962-8971301M9C XC3042-50CB100B -50 CB100 BASE
5962-8971302M9C XC3042-70CB100B -70 CB100 BASE
5962-8971303M9C XC3042-100CB100B -100 CB100 BASE
5962-8971301MMC -50 CB100 LID
5962-8971302MMC -70 CB100 LID
5962-8971303MMC -100 CB100 LID
5962-8971301MYA* XC3042-50CQ100B -50 CQ100 BASE
5962-8971302MYA* XC3042-70CQ100B -70 CQ100 BASE
5962-8971303MYA* XC3042-100CQ100B -100 CQ100 BASE
5962-8971301MNA* -50 CQ100 LID
5962-8971302MNA* -70 CQ100 LID
5962-8971303MNA* -100 CQ100 LID
* Do Not Use for New Designs (package to be obsoleted). Use “CB” Package Instead.
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-8982301MXC XC3090-50PG175B -50 PG175 TOP
5962-8982302MXC XC3090-70PG175B -70 PG175 TOP
5962-8982303MXC XC3090-100PG175B -100 PG175 TOP
5962-8982301MZC XC3090-50PG164B -50 CB164 BASE
5962-8982302MZC XC3090-70PG164B -70 CB164 BASE
5962-8982303MZC XC3090-100PG164B -100 CB164 BASE
5962-8982301MTC -50 CB164 LID
5962-8982302MTC -70 CB164 LID
5962-8982303MTC -100 CB164 LID
5962-8982301MYA* XC3090-50CQ164B -50 CQ164 BASE
5962-8982302MYA* XC3090-70CQ164B -70 CQ164 BASE
5962-8982303MYA* XC3090-100CQ164B -100 CQ164 BASE
5962-8982301MUA* -50 CQ164 LID
5962-8982302MUA* -70 CQ164 LID
5962-8982303MUA* -100 CQ164 LID
* Package OBSOLETE. Use “CB” Package Instead.
High-Reliability and Military Products
9-4 June 1, 1996 (Version 1.0)
XC3100A Products
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-9561001MXC XC3142A-5PG84B -5 PG84 TOP
5962-9561002MXC XC3142A-4PG84B -4 PG84 TOP
5962-9561001MUC XC3142A-5PG132B -5 PG132 TOP
5962-9561002MUC XC3142A-4PG132B -4 PG132 TOP
5962-9561001MYC XC3142A-5CB100B -5 CB100 BASE
5962-9561002MYC XC3142A-4CB100B -4 CB100 BASE
5962-9561001MZC -5 CB100 LID
5962-9561002MZC -4 CB100 LID
5962-9561101MXC XC3190A-5PG175B -5 PG175 TOP
5962-9561102MXC XC3190A-4PG175B -4 PG175 TOP
5962-9561101MYC XC3190A-5CB164B -5 CB164 BASE
5962-9561102MYC XC3190A-4CB164B -4 CB164 BASE
5962-9561101MZC -5 CB164 LID
5962-9561102MZC -4 CB164 LID
5962-9561201MXC XC3195A-5PG175B -5 PG175 TOP
5962-9561202MXC XC3195A-4PG175B -4 PG175 TOP
5962-9561201MYC XC3195A-5CB164B -5 CB164 BASE
5962-9561202MYC XC3195A-4CB164B -4 CB164 BASE
5962-9561201MZC -5 CB164 LID
5962-9561202MZC -4 CB164 LID
XC4000 Products
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-9471201MXC XC4003A-10PG120B -10 PG120 TOP
5962-9471202MXC XC4003A-6PG120B -6 PG120 TOP
5962-9471201MYC XC4003A-10CB100B -10 CB100 BASE
5962-9471202MYC XC4003A-6CB100B -6 CB100 BASE
5962-9471201MZC -10 CB100 LID
5962-9471202MZC -6 CB100 LID
5962-9225201MXC XC4005-10PG156B -10 PG156 TOP
5962-9225202MXC XC4005-6PG156B -6 PG156 TOP
5962-9225203MXC XC4005-5PG156B -5 PG156 TOP
5962-9225201MYC -10 CB164 LID
5962-9225202MYC -6 CB164 LID
5962-9225203MYC -5 CB164 LID
5962-9225201MZC XC4005-10CB164B -10 CB164 BASE
5962-9225202MZC XC4005-6CB164B -6 CB164 BASE
5962-9225203MZC XC4005-5CB164B -5 CB164 BASE
June 1, 1996 (Version 1.0) 9-5
XC4000 Products (continued)
SMD Number Equivalent “B” Grade P/N Speed Package Mark Loc
5962-9230501MXC XC4010-10PG191B -10 PG191 TOP
5962-9230502MXC XC4010-6PG191B -6 PG191 TOP
5962-9230503MXC XC4010-5PG191B -5 PG191 TOP
5962-9230501MYC XC4010-10CB196B -10 CB196 BASE
5962-9230502MYC XC4010-6CB196B -6 CB196 BASE
5962-9230503MYC XC4010-5CB196B -5 CB196 BASE
5962-9230501MZC -10 CB196 LID
5962-9230502MZC -6 CB196 LID
5962-9230503MZC -5 CB196 LID
5962-9473001MXC XC4013-10PG223B -10 PG223 TOP
5962-9473002MXC XC4013-6PG223B -6 PG223 TOP
5962-9473001MYC XC4013-10CB228B -10 CB228 BASE
5962-9473002MYC XC4013-6CB228B -6 CB228 BASE
5962-9473001MZC -10 CB228 LID
5962-9473002MZC -6 CB228 LID
High-Reliability and Military Products
9-6 June 1, 1996 (Version 1.0)
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Programming Support
HW-130 Programmer
Programs All Xilinx Nonvolatile Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programmer Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Interface Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programmer Functional Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Programming Socket Adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Electrical Requirements and Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
New Programming Algorithm Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Adapter Selector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Programming Support Table of
Contents
June 1, 1996 (Version 1.0) 10-1
Programs All Xilinx Nonvolatile Devices
• XC1700 Serial PROMs
• XC7000 CPLDs
• XC8100 FPGAs
• XC9500 CPLDs
• Supports all Xilinx package types
Programmer Accessories
• Universal international power supply
• Power cord options for US/Asia, UK, EU and KK
standards.
• Serial download cable and adapters
• Users manual
Interface Software and System
Requirements
The programmer softw are operates on a variety of diff erent
platforms. Table 1 indicates the minimum system require-
ments for each of the supported platforms. In all cases, a
3.5” disk drive or a CD-ROM drive and an RS-232 serial
port are required. A mouse is recommended.
Programmer Functional Specifications
• Device programming and verification
• CPLD security control
• PROM reset polarity control
• Checksum calculation and comparison
• Blank check and signature ID tests
• Master device program upload
• File transfer and comparison
• Self check and auto calibration
Programming Socket Adapters
• Supports all package styles: PLCC, PQFP, BGA, SOIC,
VOIC, PGA and DIP
• CPLD adapters for the HW-120 may be used on the
HW-130
Electrical Requirements and Physical
Specifications
• Operating voltage: 100-250 VAC, 50-60 Mhz
• Power consumption: 1.0 Amps
• Dimensions: 6” x 7.75” x 2”
• Weight: 1 lb.
• Safety standards: approved by UL, CSA, TUV
New Programming Algorithm Support
• Available via the Xilinx BBS and e-mail.
• Send e-mail to xdocs@Xilinx. com with “search hw130”
in the subject field.
• For the bulletin board, refer to page 6-2 in the data
book. Type “F” and select directory #3. Select either
Programming Support or type “Zhw130” to view all HW-
130 related files.
HW-130 Programmer
June 1, 1996 (Version 1.0)
Table 1: Interface Software and System Requirements
Requirements DOS Windows 3.1 Windows 95 Windows NT Sun OS Solaris HP9000/700 IBM RS6000
Memory Needed 540KB 4MB 8MB 16MB — — — —
Hard Disk Space 2MB 2MB 2MB 2MB 1MB 1MB 1MB 1MB
System Software 3.3 or
greater 3.1 or greater 4.00 3.1 or greater SunOS 4.1.3 or
greater, X11R5
with Motif 1.2 or
greater
SunOS 5.4 or
greater,
X11R5 with
Motif 1.2 or
greater
HP-UX A09.05
or greater,
X11R5 with
Motif 1.2 or
greater
AIX 3.2 or
greater,
X11R5 with
Motif 1.2 or
greater
HW-130 Programmer
10-2 June 1, 1996 (Version 1.0)
Adapter Selector Table
Product Family Package Types Adapter P/N
XC7200A PLCC/CLCC 44 HW-132-PC44
XC7200A PLCC/CLCC 68 HW-132-PC68
XC7200A PLCC/CLCC 84 HW-132-PC84
XC7200A PGA 84 HW-132-PG84
XC7300 PLCC/CLCC 44 HW-133-PC44
XC7300 PQFP 44 HW-133-PQ44
XC7300 VQFP 44 HW-133-VQ44
XC7300 PLCC/CLCC 68 HW-133-PC68
XC7300 PLCC/CLCC 84 HW-133-PC84
XC7300 PQFP 100 HW-133-PQ100
XC7300 PGA 144 HW-133-PG144
XC7300 PQFP 160 HW-133-PQ160
XC7300 BGA 225 HW-133-BG225
XC1700 DIP 8 HW-137-DIP8
XC1700 PLCC20/SO8/VO8 HW-137-PC20/SO8
XC8100 PLCC/CLCC 44 HW-138-PC44
XC8100 VQFP 44 HW-138-VQ44
XC8100 PLCC 84 HW-138-PC84
XC8100 PQFP 100 HW-138-PQ100
XC8100 PQFP 160 HW-138-PQ160
XC8100 BGA 225 HW-138-BG225
Calibration Adapter HW-130-CAL
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Packages and Thermal
Characteristics
Packages and Thermal Characteristics
Number of Available I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Package Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Package Thermal Characterization Methods & Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Some Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Component Mass (Weight) by Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Xilinx Thermally Enhanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Moisture Sensitivity of PSMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Reflow Soldering Process Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
Plastic DIP Packages — PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
SOIC Packages — SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
TSOP Packages — VO8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
PLCC Packages — PC20, PC28, PC44, PC68, PC84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
PQFP Packages — PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160,
HQ208, HQ240, HQ304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
TQFP Packages — TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . 11-38
VQFP Packages — VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
BGA Packages — BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
Ceramic DIP Packages — DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
Ceramic PGA Packages — PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175,
PG191, PG223, PG299, PG411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
Ceramic Brazed QFP Packages — CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . 11-61
CLCC Packages — CC20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67
Plastic PGA Packages — PP132, PP175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68
Windowed CLCC Packages — WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-70
Metal Quad Packages — MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-71
Packages and Thermal
Characteristics Table of Contents
June 1, 1996 (Version 1.0) 11-1
Packages and Thermal
Characteristics
June 1, 1996 (Version 1.0)
Number of Available I/O Pins
Max
I/O 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 225 228 240 299 304 352 411 432 499
XC7236A 36 36
XC7272A 72 56 72
XC7318 38 38
XC7336 38 38
XC7336Q 38 38
XC7354 58 38 58
XC7372 84 57 72 84
XC73108 120 72 84 120 120 120
XC73144 156 136 156
XC9536 34 34
XC9572 72 69 72
XC95108 108 69 81 108
XC95144 133 81 133
XC95180 168 133 168
XC95216 168 133 168
XC95288 192 168 192
XC95432 240 240
XC95576 240 240
XC3020/A/L &
XC3120A 64 58 64 64
XC3030/A/L &
XC3130A 80 34 54 58 74 80
XC3042/A/L &
XC3142A/L 96 74 82 96 96
XC3064/A/L &
XC3164A 120 70 110 110 120
XC3090/A/L &
XC3190A/L 144 70 120 138 144 144 144 144
XC3195A 176 70 138 144 176 176
XC4003E 80 61 77 80
XC4005E 112 61 77 112 112 112 112 112
XC4005L 112 61 112
XC4006E 128 61 113 125 128 128
XC4008E 144 61 129 144 144
XC4010E 160 61 129 160 160 160 160
XC4010L 160 61 153 160
XC4013E 192 129 160 192 192 192 192
XC4013L 192 160 192 192
XC4020E 224 160 192 193
XC4025E 256 192 192 193 256 256
XC4028EX 256 160 193 256 256 256
XC4028XL 256 160 193 256 256 256
XC4036EX 288 256 288 288
XC4036XL 288 256 288 288
Packages and Thermal Characteristics
11-2 June 1, 1996 (Version 1.0)
XC4044EX 320 320 320
XC4044XL 320 320 320
XC4052XL 352 352 352
XC4062XL 384 384
XC5202 84 65 81 84 84
XC5204 124 65 81 117 124 124
XC5206 148 65 81 117 133 148 148 148
XC5210 196 65 117 133 149 164 196 196 196
XC5215 244 133 164 196 197 244 244 244
XC6209 180 180 180
XC6216 242 199 242
XC6236 384
XC6264 512
XC8100 32 32
XC8101 80 32 61 72
XC8103 128 32 61 64
XC8106 168 61 76 129 192
XC8109 208 61 129 192
Number of Available I/O Pins (Continued)
Max
I/O 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 225 228 240 299 304 352 411 432 499
June 1, 1996 (Version 1.0) 11-3
Package Options
Surface Mount Through-
hole
PLCC PQFP HQFP TQFP VQFP CQFP BGA PGA
Standard JEDEC EIAJ EIAJ EIAJ EIAJ JEDEC JEDEC JEDEC
Lead Pitch 50 mil 0.65/0.5 mm 0.65/0.5 mm 0.5 mm 0.5 mm 25 mil 1.5 mm 100 mil
Body Plastic Plastic Plastic/Metal Plastic Plastic Ceramic FR4 Ceramic/
Plastic
Temperature
Options C, I C, I C, I C, I C, I M, B C C, I, M, B
Ordering Code PC PQ HQ TQ/HT VQ CB BG PG, PP
XC7236A 44
XC7272A 68, 84 84
XC7318 44 44
XC7336 44 44
XC7336Q 44 44 44
XC7354 44, 68
XC7372 68, 84 100
XC73108 84 100,160 225 144
XC73144 160 225 184
XC9536 44 44
XC9572 84 100 100
XC95108 84 100, 160 100 100
XC95144 100, 160
XC95180 160 208
XC95216 160 208
XC95288 208, 304
XC95432 304
XC95576 304
XC3020/A/L &
XC3120A 68, 84 100 100 84
XC3030/A/L &
XC3130A 44, 68, 84 100 100 100 64 84
XC3042/A/L &
XC3142A/L 68, 84 100 100, 144 100, 144 100 84, 132
XC3064/A/L &
XC3164A 84 160 144 144 132
XC3090/A/L &
XC3190A/L 84 160, 208 144, 176 164 175
XC3195A 84 160, 208 175, 223
XC4003E 84 100 100 120
XC4005E 84 100, 160, 208 144 164 156
XC4005L 84 208
XC4006E 84 160, 208 144 156
XC4008E 84 160, 208 191
XC4010E 84 160, 208 196 255 191
XC4010L 84 208 176
XC4013E 160, 208, 240 208, 240 228 225 223
XC4013L 208, 240 225
XC4020E 208, 240 223
Packages and Thermal Characteristics
11-4 June 1, 1996 (Version 1.0)
Inches vs. Millimeters
The JEDEC standards for PLCC, CQFP, and PGA pack-
ages define package dimensions in inches. The lead spac-
ing is specified as 25, 50, or 100 mils (0.025", 0.050" or
0.100").
The EIAJ standards for PQFP, HQFP, TQFP, and VQFP
packages define pac kage dimensions in millimeters. These
packages have a lead spacing of 0.5 mm, except for the
100- and 160-pin PQFP packages , which hav e a lead spac-
ing of 0.65 mm.
Because of the potential for measurement discrepancies,
this Data Book provides measurements in the controlling
standard only, either inches or millimeters.
XC4025E 240, 304 228 223, 299
XC4028EX 208, 240, 304 352 299
XC4028XL 208, 240, 304 352 299
XC4036EX 304 432 411
XC4036XL 304 432 411
XC4044EX 432 411
XC4044XL 432 411
XC4052XL 432 411
XC4062XL 499
XC5202 84 100 144 100 156
XC5204 84 100, 160 144 100 156
XC5206 84 100, 160, 208 144, 176 100 191
XC5210 84 160, 208, 240 144, 176 225 223
XC5215 160 208, 240, 304 225, 352 299
XC6209 84 240 299
XC6216 84 240 299
XC6236
XC6264
XC8100 44 44
XC8101 84 100 44
XC8103 84 100 44
XC8106 84 100, 160 225
XC8109 84 160 225
Package Options (Continued)
Surface Mount Through-
hole
PLCC PQFP HQFP TQFP VQFP CQFP BGA PGA
Standard JEDEC EIAJ EIAJ EIAJ EIAJ JEDEC JEDEC JEDEC
Lead Pitch 50 mil 0.65/0.5 mm 0.65/0.5 mm 0.5 mm 0.5 mm 25 mil 1.5 mm 100 mil
Body Plastic Plastic Plastic/Metal Plastic Plastic Ceramic FR4 Ceramic/
Plastic
Temperature
Options C, I C, I C, I C, I C, I M, B C C, I, M, B
Ordering Code PC PQ HQ TQ/HT VQ CB BG PG, PP
June 1, 1996 (Version 1.0) 11-5
EIA Standard Board Layout of Soldered Pads for QFP Devices
Notes: 1. Dimensions in millimeters
2. For 3.2 mm footprint per MS022, JEDEC Publication 95.
Cavity Up or Cavity Down
Most Xilinx devices attach the die against the inside bottom
of the package (the side that does not carry the Xilinx logo).
This is called cavity-up, and has been the standard IC
assembly method for over 25 years. This method does not
provide the best thermal characteristics. Pin Grid Arrays
(greater than 130 pins) and Ceramic Quad Flat Packs are
assembled “Cavity Down”, with the die attached to the
inside top of the package, for optimal heat transfer to the
ambient air.
For most pac kages this information does not affect ho w the
package is used because the user has no choice in ho w the
package is mounted on a board. For Ceramic Quad Flat
Pack (CQFP) packages however, the leads can be formed
to either side. Therefore, for best heat transfer to the sur-
rounding air, CQFP packages should be mounted with the
logo up, facing away from the PC board.
Clockwise or Counterclockwise
The orientation of the die in the package and the orientation
of the package on the PC board aff ect the PC board layout.
PLCC and PQFP packages specify pins in a counterclock-
wise direction, when viewed from the top of the package
(the surface with the Xilinx logo). PLCCs have pin 1 in the
center of the beveled edge while all other packages have
pin 1 in one corner, with one exception: The 100- and 165-
pin CQFPs (CB100 and CB164) for the XC3000 devices
have pin 1 in the center of one edge.
CQFP packages specify pins in a cloc kwise direction, when
viewed from the top of the pac kage . The user can mak e the
pins run counterclockwise by forming the leads such that
the logo mounts against the PC board. However, heat flow
to the surrounding air is impaired if the logo is mounted
down.
Table 1: Dimensions for Xilinx Quad Flat Packs1
Dim. PQ44 VQ64 PQ100 PQ160 HQ/MQ/PQ208 VQ/TQ100 TQ144 TQ176 HQ/MQ/PQ240 HQ304
MID 10.40 9.80 20.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20
MIE 10.40 9.80 14.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20
e 0.80 0.50 0.65 0.65 0.50 0.50 0.50 0.50 0.50 0.50
b20.4 - 0.6 0.3 - 0.4 0.3 - 0.5 0.3 - 0.5 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4
I21.80 1.60 1.8021.80 1.60 1.60 1.60 1.60 1.60 1.60
b2
MID
MIE
e
l2
e
e
e
Packages and Thermal Characteristics
11-6 June 1, 1996 (Version 1.0)
Thermal Management
Modern high speed logic devices consume an appreciable
amount of electrical energy. This energy invariably turns
into heat. Higher device integration drives technologies to
produce smaller device geometry and interconnections.
With smaller chip sizes and higher circuit densities, heat
generation on a fast switching CMOS circuit can be very
significant. The heat removal needs for these modern
devices must be addressed.
Managing heat generation in a modern CMOS logic device
is an industry-wide pursuit. However, unlike the power
needs of a typical Application Specific Integrated Circuit
(ASIC) gate array, the power requirements for FPGAs are
not determined as the device leaves the factory. Designs
vary in power needs.
There is no way of anticipating the power needs of an
FPGA device short of depending on compiled data from
previous designs. For each device type, primary packages
are chosen to handle ‘typical’ designs and gate utilization
requirements. For the most part the choice of a package as
the primary heat removal casing works well.
Occasionally designers exercise an FPGA device, particu-
larly the high gate count variety, beyond “typical” designs.
The use of the primary package without enhancement may
not adequately address the device’s heat removal needs.
Heat removal management through external means or an
alternative enhanced package should be considered.
Removing heat ensures the functional and maximum
design temperature limits are maintained. The device may
go outside the temperature limits if heat build up becomes
excessive. As a consequence, the device may fail to meet
electrical performance specifications. It is also necessary
to satisfy reliability objectives by operating at a lower tem-
perature. Failure mechanisms and the failure rate of
devices depend on device operating temperature. Control
of the package and the device temperature ensures prod-
uct reliability.
Package Thermal Characterization
Methods & Conditions
Method and Calibration
Xilinx uses the indirect electrical method for package ther-
mal resistance characterization. The forward-voltage drop
of an isolated diode residing on a special test die is cali-
brated at constant forcing current of 0.520mA with respect
to temperature over a correlation temperature range of
22°C to 125°C (degree Celsius). The calibrated device is
then mounted in an appropriate environment (still air,
forced convection, circulating FC-40, etc.) Depending on
the package, between 0.5 to 4 watts of power (Pd) is
applied. Power (Pd) is applied to the device through dif-
fused resistors on the same thermal die. The resulting r ise
in junction temperature is monitored with the forward-volt-
age drop of the precalibrated diode. Typically, three identi-
cal samples are tested at each data point. The
reproducibility error in the set-up is within 6%.
Definition of Terms
TJ Junction Temperature — the maximum temperature
on the die, expressed in °C (degree Celsius)
TAAmbient Temperature — expressed in °C.
TCThe temperature of the package body taken at a
defined location on the body. This is taken at the pri-
mary heat flow path on the package and represents
the hottest part on the package — expressed in °C.
TlThe isothermal fluid temperature when junction to
case temperature is taken — expressed in °C.
PdThe total device power dissipation — expressed in
watts.
Junction-to-Reference General Setup
Junction-to-Case Measurement — ΘJC
ΘJC is measured in a 3M Flourinert (FC-40) isothermal cir-
culating fluid stabilized at 25°C. The Device Under Test
(DUT) is completely immersed in the fluid and initial stable
conditions are recorded. Pd is then applied. Case temper-
ature (TC)
is measured at the primary heat-flow path of the
par ticular package. Junction temperature (TJ) is calculated
from the diode forward-voltage drop from the initial stable
condition before power was applied.
ΘJC = (TJ - TC)/Pd
The junction-to-isothermal-fluid measurement (ΘJI) is also
calculated from the same data.
ΘJL = (TJ - TI)/Pd
Figure 1: Thermal Measurement Set-Up (Schematic
for Junction to Reference)
June 1, 1996 (Version 1.0) 11-7
The latter data is considered as the ideal ΘJA data for the
package that can be obtained with the most efficient heat
removal scheme. Other schemes such as airflow, heat-
sinks, use of copper clad board, or some combination of all
these will tend towards this ideal figure. Since this is not a
widely used parameter in the industry, and it is not very
realistic for normal application of Xilinx packages, the ΘJI
data is not published. The thermal lab keeps such data for
package comparisons.
Junction-to-Ambient Measurement — ΘJA
ΘJA is measured on FR4 based PC boards measuring 4.5”
x 6.0” x .0625” (114.3mm x 152.4mm x 1.6mm) with edge
connectors. There are two main board types.
Type I, 2L/0P board, is single layer with 2 signal planes
(one on each surface) and no internal Power/GND planes.
The trace density on this board is less than 10% per side.
Type II, the 4L/2P board, has 2 internal copper planes (one
power, one ground) and 2 signal trace layers on both sur-
faces.
Data may be tak en with the package mounted in a soc ket or
with the package mounted directly on the board. Socket
measurements typically use the 2L/0P boards. SMT
devices may use either board. Published data always
reflects the board and mount conditions used.
Data is taken at the prevailing temperature and pressure
conditions (22°C to 25°C ambient). The board with the DUT
is mounted in a cylindrical enclosure. The pow er application
and signal monitoring are the same as ΘJC measurements.
The enclosure (ambient) thermocouple is substituted for
the fluid thermocouple and two extra thermocouples
brought in to monitor room and board temperatures. The
junction to ambient thermal resistance is calculated as fol-
lows:
ΘJA = (TJ - TA)/Pd
The setup described herein lends itself to the application of
various airflow velocities from 0 - 800 Linear Feet per
Minute (LFM), i.e., 0 - 4.06 m/s. Since the board selection
(copper trace density, absence or presence of ground
planes, etc.) affects the results of the thermal resistance,
the data from these tests shall always be qualified with the
board mounting information.
Data Acquisition and Package Thermal
Database
Xilinx gathers data for a package type in die sizes, power
levels and cooling modes (air flow and sometimes heatsink
effects) with a Data Acquisition and Control system (DAS).
The DAS controls the power supplies and other ancillary
equipment for hands-free data taking. Different setups
within the DAS software are used to run calibration, ΘJA,
ΘJC, f an tests , as well as the po wer effect characteristics of
a package.
A package is characterized with respect to the major var i-
ables that influence the thermal resistance. The results are
stored in a database. Thermal resistance data is interpo-
lated as typical values for the individual Xilinx devices that
are assembled in the characterized package. Table 1
shows the typical values for different packages. Specific
device data may not be the same as the typical data. How-
ever, the data will fall within the given minimum and maxi-
mum ranges. The more widely used packages will have a
wider range. Customers may contact the Xilinx application
group for specific device data.
Packages and Thermal Characteristics
11-8 June 1, 1996 (Version 1.0)
Table 2: Summary of Thermal Resistance for Packages
PKG-CODE ΘJA at 07
(Max) ΘJA at 07
(Typ) ΘJA at 07
(Min) ΘJA at 2506
(Typ) ΘJA at 5006
(Typ) ΘJA at 7506
(Typ) ΘJC
(Typ) Comments
°C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt
BG225 37 30 24 19 17 16 3.3 Various
CB100 44 41 38 25 19 17 5.1 Socketed
CB164 29 26 25 17 12 11 3.6 Socketed
CB196 25 24 24 15 11 10 1.8 Socketed
CB228 19 18 17 11 8 7 1.3 Socketed
CQ100 46 45 44 37 30 25 7.1 Socketed
DD8 114 109 97 90 73 60 8.2 Socketed
HQ208 15 14 14 10 8 7 1.7 4L/2P-SMT
HQ240 13 12 12 9 7 6 1.5 4L/2P-SMT
HQ304 11 11 10 7 5 5 0.9 4L/2P-SMT
MQ208 18 18 17 14 13 12 1.2 2L/0P-SMT
MQ240 17 17 16 12 11 10 1.2 2L/0P-SMT
PC20 86 84 76 63 56 53 25.8 2L/0P-SMT
PC44 51 46 42 35 31 29 13.7 2L/0P-SMT
PC68 46 42 38 31 28 26 9.3 2L/0P-SMT
PC84 41 33 28 25 21 17 5.3 2L/0P-SMT
PD48 43 43 43 33 29 27 11.6 Socketed
PD8 82 79 73 60 54 50 22.2 Socketed
PG120 32 27 25 19 15 13 3.6 Socketed
PG132 32 28 24 20 17 15 2.8 Socketed
PG144 26 25 23 17 14 13 3.7 Socketed
PG156 25 23 21 15 11 10 2.6 Socketed
PG175 25 23 20 14 11 10 2.6 Socketed
PG191 24 21 18 15 12 11 1.5 Socketed
PG223 24 20 18 15 12 11 1.5 Socketed
PG299 18 17 16 10 9 8 1.9 Socketed
PG411 16 15 14 9 8 7 1.2 Estimated
PG68 39 37 34 26 20 17 7.8 Socketed
PG84 37 34 31 24 18 16 5.8 Socketed
PP132 35 34 33 23 18 17 6.0 Socketed
PP175 29 29 28 19 15 13 2.5 Socketed
PQ100 35 33 32 29 28 27 5.5 4L/2P-SMT
PQ160 37 32 22 24 21 20 4.6 2L/0P-SMT
PQ208 35 32 26 23 21 19 4.3 2L/0P-SMT
PQ240 28 23 19 17 15 14 2.8 2L/0P-SMT
PQ44 52 51 51 40 36 35 12.4 4L/2P-SMT
SO8 147 147 147 112 105 98 48.3 IEEE-(Ref)
TQ100 37 31 31 26 24 23 7.5 4L/2P-SMT
TQ144 35 32 30 25 21 20 5.3 4L/2P-SMT
TQ176 29 28 27 21 18 17 5.3 4L/2P-SMT
VO8 162 162 162 123 116 108 48.3 Estimated
VQ100 47 38 32 32 30 29 9.0 4L/2P-SMT
VQ44 44 44 44 36 34 33 8.2 4L/2P-SMT
VQ64 44 41 39 34 32 31 8.2 4L/2P-SMT
June 1, 1996 (Version 1.0) 11-9
Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time of
compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie
within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data in a
package may be obtained from the factory.
2. Package configurations and drawings are in the package section of the data book.
3. 2L/0P - SMT: the data is from a surface mount type I board -- no internal planes on the board.
4. 4L/2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket.
5. Thermal data is in degree Celsius/watt.
6. Airflow is reported in Linear Feet per minute (LFM).
7. Columns 1, 2 and 3 are for ΘJA in still air.
Application of Thermal Resistance Data
Thermal resistance data gauges the IC package thermal
performance. ΘJC measures the internal package resis-
tance to heat conduction from the die surface, through the
die mount material to the package exterior. ΘJC strongly
depends on the package’s heat conductivity, architecture
and geometrical considerations.
ΘJA measures the total package thermal resistance includ-
ing ΘJC. ΘJA depends on the package material proper ties
and such external conditions as convective efficiency and
board mount conditions. For example, a package mounted
on a socket may have a ΘJA value 20% higher than the
same package mounted on a 4 layer board with power and
ground planes.
By specifying a few constraints, devices are ensured to
operate within the intended temperature range. This also
ensures device reliability and functionality. The system
ambient temperature needs to be specified. A maximum TJ
also needs to be established for the system. The following
inequality will hold.
TJ(max) > ΘJA* Pd +TA
The following two examples illustrates the use of this ine-
quality.
Example 1:
The manufacturer’s goal is TJ (max) < 100°C
A module is designed for a TA = 45°C max.
A XC3042 in a PLCC 84 has a ΘJA = 32°C/watt.
Given a XC3042 with a logic design with a rated power
Pd of 0.75watt.
With this information, the maximum die temperature
can be calculated as:
TJ = 45 + (32 x .75) ==> 69°C.
The system manufacturer’s goal of TJ < 100°C is met.
WB144 28 28 28 — — — 6.0 2L/0P-SMT
WB225 28 28 28 — — — 6.0 2L/0P-SMT
WC44 47 46 45 38 31 25 9.1 Socketed
WC68 46 43 40 31 26 23 7.0 Socketed
WC84 43 41 38 29 24 21 3.9 Socketed
Table 2: Summary of Thermal Resistance for Packages (Continued)
PKG-CODE ΘJA at 07
(Max) ΘJA at 07
(Typ) ΘJA at 07
(Min) ΘJA at 2506
(Typ) ΘJA at 5006
(Typ) ΘJA at 7506
(Typ) ΘJC
(Typ) Comments
°C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt
Packages and Thermal Characteristics
11-10 June 1, 1996 (Version 1.0)
Example 2:
A module has a TA = 55°C max.
The Xilinx XC4013E is in a PQ240 package (HQ240 is
also considered).
A XC4013E, in an example logic design, has a rated
power of 2.50 watts. The module manufacturers goal is
TJ(max.) < 100°C.
Table 3 shows the package and thermal enhancement
combinations required to meet the goal of TJ < 100°C.
Possible Solutions to meet the module requirements of 100°C:
For all solutions, the junction temperature is calculated as:
TJ = Power x ΘJA + TA
All solutions meet the module requirement of less than
100°C, with the exception of the PQ240 package in still air.
In general, depending on ambient and board temperatures
conditions, and most importantly the total power dissipa-
tion, thermal enhancements -- such as forced air cooling,
heat sinking, etc. may be necessary to meet the TJ(max)
conditions set.
Table 3: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages
Dev Name Package ΘJA
still air ΘJA
(250 LFM) ΘJA
(500 LFM) ΘJA
(750 LFM) ΘJC Comments
XC4013E PQ240 23.7 17.5 15.4 14.3 2.7 Cu, SMT 2L/0P
XC4013E HQ240 12.5 8.6 6.9 6.2 1.5 4 Layer Board data
1a. Using the standard PQ240; TJ = 55 + (23.7 x 2.50) ==> 114.25 °C.
1b. Using standard PQ240 with 250LFM forced air TJ = 55 + (17.5 x 2.50) ==> 98.75 °C
2a. Using standard HQ240 TJ = 55 + (12.5 x 2.50) ==> 86.25 °C
2b. Using HQ240 with 250 LFM forced air TJ = 55 + (8.6 x 2.50) ==> 76.5 °C
June 1, 1996 (Version 1.0) 11-11
PQ/HQ Thermal Data Comparison
5
10
15
20
25
30
35
Θ
JA
(°C/watt)
200 300 400 500 600 700
Die size (mils)
HQ208
HQ240
HQ304
PQ208
PQ240
HQ/PQ Thermal Data
Size effect on Θ
JA
0
5
10
15
20
25
30
ΘJA (°C/watt)
0 200 400 600 800
Airflow - LFM
XC4010E-HQ208 XC4013E-HQ240 XC4025E-HQ304
XC4010E-PQ208 XC4013E-PQ240
HQ/PQ Thermal Data
Effect of Forced Air on ΘJA
Packages and Thermal Characteristics
11-12 June 1, 1996 (Version 1.0)
10
15
20
25
30
35
40
Θ
JA
(°C/watt)
0 200 400 600 800
Air Flow - LFM
XC4010E-BG225 (2L) XC4013E-BG225(4L) XC73144-BG225(4L)
XC73108-BG225(2L) XC5210-BG225(2L)
BGA Thermal Resistance
Effect of Air Flow on Θ
JA
0
5
10
15
20
Θ
JA
(°C/watt)
A B C D EF
PG299 - Various Enhancements
PG299 Thermal Resistance
Effects of Active & Passive Heat sinks
Pkg+Active Fan (V=12)DStandard PkgA Std Pkg +250LFMEPkg+Finned HS (Passive)B Pkg+Finned HS+ 250LFMFPkg+Active Fan (V=0)C
June 1, 1996 (Version 1.0) 11-13
0
5
10
15
20
25
Θ
JA
(°C/watt)
0 100 200 300 400 500 600 700
Air Flow - LFM
PG191-XC4010E PG223-XC4013E
PG299-XC4025E PG299-FHS(XC4025E)
PGA 299 Thermal Resistance
Effect of Air Flow on Θ
JA
Packages and Thermal Characteristics
11-14 June 1, 1996 (Version 1.0)
Some Power Management Options
FPGA devices are usually not the dominating power con-
sumers in a system, and do not hav e a big impact on pow er
supply designs. There are obvious exceptions. When the
actual or estimated power dissipation appears to be more
than the specification of the chosen package , some options
can be considered. Details on the engineering designs and
analysis of some of these suggested considerations may
be obtained from the references listed at the end of the sec-
tion. The options include:
• A Xilinx low power (L) version of the circuit in the same
package. With the product and speed grade of choice,
up to a 40% power reduction can be anticipated. For
more information, contact the Xilinx Hotline group.
• Explore thermally enhanced package options available
for the same device. As illustrated above, the HQ240
package has a thermal impedance of about 50% of the
equivalent PQ240. Besides, the 240 lead, the 208 lead
and the 304 lead Quad packages have equivalent
heatsink enhanced versions. Typically 25% to 40%
improvement in thermal performance can be expected
from these heatsink enhanced packages. Most of the
high gate count devices above the XC4013 level come
either exclusively in heat enhanced packages or have
these packages as options. If the use of a standard PQ
appears to be a handicap in this respect, a move to the
equivalent HQ package if available may resolve the
issue. The heat enhanced packages are pin to pin
compatible and they use the same board layout.
• The use of forced air is an effective way to improve
thermal performance. As seen on the graphs and the
calculations above, forced air (200 -- 300 LFM) can
reduce junction to ambient thermal resistance by 30%.
• If space will allow, the use of finned external heatsinks
can be effective. If implemented with forced air as well,
the benefit can be a 40% to 50% reduction. The HQ304,
all cavity down PGAs, and the BG352 with exposed
heatsink lend themselves to the application of external
heatsinks for further heat removal efficiency.
• Outside the package itself, the board on which the
package sits can have a significant impact. Board
designs may be implemented to take advantage of this.
Heat flows to the outside of a board mounted package
and is sunk into the board to radiate. The effect of the
board will be dependent on the size and how it
conducts heat. Board size, the le v el of copper traces on
it, the number of buried copper planes all lower the
junction-to-ambient thermal resistance for a package.
Some of the heatsink packages with the exposed
heatsink on the board side can be glued to the board
with thermal compound to enhance heat removal.
References
Forced Air Cooling Application Engineering
COMAIR ROTRON
2675 Custom House Court
San Ysidro, CA 92173
1-619-661-6688
Heatsink Application Engineering
The following facilities provide heatsink solutions for indus-
try standard packages.
AA VID Thermal Technologies
1 Kool Path
Box 400
Laconia, NH 03247-0400
1-603-528-3400
Thermalloy, Inc.
2021 W . Valley View Lane
Box 810839
Dallas, TX 75381-0839
1-214-243-4321
Wakefield Engineering, Inc.
60 Audubon Road
Wakefield MA 01880-1255
1-617-245-5900
Xilinx does not endorse these vendors nor their products.
They are listed here for reference only. Any materials or
services received from the vendors should be e v aluated for
compatibility with Xilinx components.
June 1, 1996 (Version 1.0) 11-15
Component Mass (Weight) by Package Type
Package Description JEDEC Outline # Xilinx # Mass (g)
BG225 MOLDED BGA 27mm- ANAM MO-151-CAL OBG0001 2.2
BG352 SUPERBGA - 35X35MM AMKOR MO-151-BAR OBG0008 7.1
BG432 SUPERBGA - 40X40MM AMKOR MO-151-BAU OBG0009 9.1
CB100 NCTB TOP BRAZE 3K VER MO-113 OCQ0008 10.8
CB100 NCTB TOP BRAZE 4K VER MO-113 OCQ0006 10.8
CB164 NCTB TOP BRAZE 3K VER MO-113-AA OCQ0003 11.5
CB164 NCTB TOP BRAZE 4K VER MO-113-AA OCQ0007 11.5
CB196 NCTB TOP BRAZE 4K VER MO-113-AB OCQ0005 15.3
CB228 NCTB TOP BRAZE 4K VER MO-113 OCQ0012 17.6
CC20 CERAMIC LEADED CHIP CARRIER N/A OCQ0011 8.4
DD8 .300 CERDIP PACKAGE MO-036-AA OPD0005 1.1
HQ208 METRIC 28 X 28 - H/S DIE UP MO-143-FA1 OPQ0020 10.8
HQ240 METRIC QFP 32 32 - H/S DIE UP MO-143-GA OPQ0019 15.0
HQ304 METRIC QFP 40 40-H/S DIE DOWN MO-143-JA OPQ0014 26.2
MQ208 METAL QUAD EIAJ N/A OPQ0006 6.1
MQ240 METAL QUAD N/A OPQ0011 8.0
PC20 PLCC JEDEC MO-047 MO-047-AA OPC0006 0.8
PC28 PLCC JEDEC MO-047 MO-047-AB OPC0001 1.1
PC44 PLCC JEDEC MO-047 MO-047-AC OPC0005 1.2
PC68 PLCC JEDEC MO-047 MO-047-AE OPC0001 4.8
PC84 PLCC JEDEC MO-047 MO-047-AF OPC0001 6.8
PD48 DIP .600 N/A OPD0001 7.9
PD8 DIP .300 STANDARD MO-001-AA OPD0002 0.5
PG120 CERAMIC PGA 13 X 13 MATRIX MO-067-AE OPG0012 11.5
PG132 CERAMIC PGA 14 X 14 MATRIX MO-067-AF OPG0004 11.8
PG144 CERAMIC PGA 15 X15 CAVITY UP MO-067-AG OPG0017 16.9
PG156 CERAMIC PGA 16 X 16 MATRIX MO-067-AH OPG0007 17.1
PG175 CERAMIC PGA 16X16 STD VER. MO-067-AH OPG0009 17.7
PG184 CERAMIC PGA 15 X15 CAVITY UP MO-067-AG OPG0019 17.5
PG191 CERAMIC PGA 18 X 18 STD - ALL MO-067-AK OPG0008 21.8
PG223 CERAMIC PGA 18 X 18 TYPE MO-067-AK OPG0016 26.0
PG299 CERAMIC PGA 20 X 20 HEATSINK MO-067-AK OPG0022 37.5
PG299 CERAMIC PGA 20 X 20 TYPE MO-067-AM OPG0015 29.8
PG411 CERAMIC PGA 39 X 39 STAGGER MO-128-AM OPG0019 36.7
PG68 CERAMIC PGA CAV UP 11X11 MO-067-AC OPG0002 7.0
PG84 CERAMIC PGA CAV UP 11X11 MO-067-AC OPG0003 7.2
PP132 PLASTIC PGA 14 X 14 MATRIX MO-83-AF OPG0001 8.1
PP175 PLASTIC PGA 16X16 BURRIED MO-83-AH OPG0006 11.1
PQ100 EIAJ 14X20 QFP - 1.60 MO-108-CC1 OPQ0013 1.6
PQ160 EIAJ 28X28 .65MM 1.60 MO-108-DD1 OPQ0002 5.8
PQ208 EIAJ 28X28 .5MM 1.30 MO-143-FAI OPQ0003 5.3
PQ240 EIAJ 32 X 32 .5MM MO-143-GA OPQ0010 7.1
PQ44 EIAJ 10 X 10 X 2.0 MO-108-AA2 OPQ0015 0.5
SO8 VERSION 1 - .150/55MIL MO-150 OPD0006 0.1
TQ100 THIN QFP 1.4mm thick MS-026-BDE OPQ0004 0.7
Packages and Thermal Characteristics
11-16 June 1, 1996 (Version 1.0)
Notes: 1. Data represents average values for typical packages with typical devices. The accuracy is between 7% to 10%.
2. More precise numbers (below 5% accuracy) for specific devices may be obtained from Xilinx through a factory
representative or by calling the Xilinx Hotline.
TQ144 THIN QFP 1.4mm thick MS-026-BFB OPQ0007 1.4
TQ176 THIN QFP 1.4mm thick MS-026-BGA OPQ0008 0.9
VO8 THIN SOIC-II N/A OPD0007 0.1
VQ100 THIN QFP 1.0 thick MS-026-AED OPQ0012 0.6
VQ44 EIAJ 10 X 10 X 1.0 MS-026-ACB OPQ0017 0.4
VQ64 THIN QFP 1.0 thick MS-026-ACD OPQ0009 0.5
WC44 JEDEC WINDOWED CQUAD MO-087 OCQ0004 2.9
WC68 WINDOWED CERQUAD MO-087 OCQ0009 7.3
WC84 WINDOWED CERQUAD MO-087 OCQ0010 11.0
Component Mass (Weight) by Package Type (Continued)
Package Description JEDEC Outline # Xilinx # Mass (g)
June 1, 1996 (Version 1.0) 11-17
Xilinx Thermally Enhanced Packaging
The Package Offering
Overview
Xilinx offers thermally enhanced quad flat pack packages
on certain de vices . This section discusses the perf ormance
and usage of these packages (designated HQ). In sum-
mary:
• The HQ-series and the regular PQ packages conform
to the same JEDEC drawings.
• The HQ and PQ packages use the same PCB land
patterns.
• The HQ packages have more mass
• Thermal performance is better for the HQ packages
Where and When Offered
- HQ packages are off ered as the thermally enhanced
equivalents of PQ packages. They are used for high
gate count or high l/O count devices in packages,
where heat dissipation without the enhancement
may be a handicap for device performance. Such
devices include XC4013E, XC4020E, XC4025E, and
XC5215.
- They are also being used in place of MQUAD (MQ)
packages of the same lead count for new devices.
- The HQ series at the 240 pin count level or below
are offered with the heatsink at the bottom of the
package. This was done to ensure pin to pin
compatibility with the existing PQ and MQ pac kages .
- At the 304 pin count level, the HQ is offered with the
heatsink up . This arrangement offers a better potential
for further thermal enhancement b y the designer.
Mass Comparison
Because of the copper heatsink, the HQ series of packages
are about twice as heavy as the equivalent PQ. Here is a
quick comparison.
Thermal Data for the HQ
The data for individual de vices may be obtained from Xilinx.
Note: ΘJC is typically between 1 and 2 °C/Watt for HQ
and MQ P ackages. For PQ’s, it is between 2 and 7
°C/Watt.
Other Information
- Leadframe: Copper EFTEC-64 or C7025
- Heat Slug: Copper - Nickel plated → Heatsink metal
is Grounded
- Lead Finish 85/15 Sn/Pb 300 microinches minimum
- D/A material - Same as PQ; Epoxy 84-1LMISR4
- Mold Cpd. Same as PQ - EME7304LC
- Packed in the same JEDEC trays
Xilinx Code Body (mm) THK (mm) Mass (gm) Heatsink
Location JEDEC No. Xilinx No.
HQ304 40x40 3.80 26.2 TOP MO-143-JA OPQ0014
HQ240 32x32 3.40 15.0 DOWN MO-143-GA OPQ0019
HQ208 28x28 3.37 10.0 DOWN MO-143-FA OPQ0020
ADie Up/Heatsink Down
A – Heatsink down orientation
B – Heatsink up orientation
BDie Down/Heatsink Up
X5962
PQ (gm) MQ (gm) HQ (gm)
208 Pin 5.3 6.1 10.0
240 Pin 7.1 8.0 15.0
304 Pin N/A N/A 26.2
Still Air Data Comparison
HQ
ΘJA (°C/Watt) MQ
ΘJA (°C/watt) PQ
ΘJA (°C/watt)
208 Pin 10-14 17-19 25-32
240 Pin 11-14 15-17 18-28
304 Pin 10-12 N/A N/A
Data Comparison at Airflow - 250 LFM
HQ
ΘJA (°C/watt) MQ
ΘJA (°C/watt) PQ
ΘJA (°C/watt)
208 Pin 9-10 14-15 19-25
240 Pin 8-9 11-13 14-20
304 Pin 6.5-8 N/A N/A
Packages and Thermal Characteristics
11-18 June 1, 1996 (Version 1.0)
Moisture Sensitivity of PSMCs
Moisture Induced Cracking During Solder
Reflow
The surface mount reflow processing step subjects the
Plastic Surface Mount Components (PSMC) to high ther-
mal exposure and chemicals from solder fluxes and clean-
ing fluids during user’s board mount assembly. The plastic
mold compounds used for device encapsulation are, uni-
versally, hygroscopic and absorb moisture at a level deter-
mined by storage environment and other factors.
Entrapped moisture can vaporize during rapid heating in
the solder reflow process generating internal hydrostatic
pressure. Additional stress is added due to thermal mis-
match, and the Thermal Coefficient of Expansion (TCE) of
plastic, metal lead frame, and silicon die. The resultant
pressure may be sufficient to cause delamination within the
package , or worse , an internal or external crack in the plas-
tic package. Cracks in the plastic package can allow high
moisture penetration, inducing transport of ionic contami-
nants to the die surface and increasing the potential for
early device failure.
How the eff ects of moisture in plastic packages and the crit-
ical moisture content result in package damage or failure is
a complex function of several variables. Among them are
package construction details -- materials, design, geome-
try, die size, encapsulant thickness, encapsulant proper-
ties, TCE, and the amount of moisture absorbed. The
PSMC moisture sensitivity has, in addition to package
cracking, been identified as a contributor to delamination-
related package f ailure artifacts. These pac kage f ailure arti-
facts include bond lifting and breaking, wire neckdown,
bond cratering, die passivation, and metal breakage.
Because of the importance of the PSMC moisture sensitiv-
ity, both device suppliers and device users have ownership
and responsibility. The background for present conditions,
moisture sensitivity standardized test and handling proce-
dures have been published by two national organizations.
Users and suppliers are urged to obtain copies of both doc-
uments (listed below) and use them rigorously. Xilinx
adheres to both.
• JEDEC STANDARD JESD22-A112. Test Method A112
“Moisture-Induced Stress Sensitivity for Plastic Surface
Mounted Devices”.
Available through Global Engineering Documents
Phone: USA and Canada 800-854-7179, International
1-303-792-2181
• IPC Standard IPC-SM-786A “Procedures for
Characterizing and Handling of Moisture/Reflow
Sensitive ICs”.
Available through IPC
Phone: 1-708-677-2850
None of the previously stated or following recommenda-
tions apply to parts in a socketed application. For board
mounted parts careful handling by the supplier and the user
is vital. Each of the above publications has addressed the
sensitivity issue and has established 6 levels of sensitivity
(based on the variables identified). A replication of those
listings, including the preconditioning and test require-
ments, and the f actory floor life conditions f or each lev el are
outlined in Table 4. Xilinx devices are characterized to their
proper level as listed. This information is conveyed to the
user via special labeling on the Moisture Barrier Bag
(MBB).
In Table 4, the level number is entered on the MBB prior to
shipment. This establishes the user’s factory floor life con-
ditions as listed in the time column. The soak requirement
is the test limit used by Xilinx to determine the lev el number .
This time includes manuf acturer’ s exposure time or the time
it will take for Xilinx to bag the product after baking.
June 1, 1996 (Version 1.0) 11-19
Notes: X = Default value of semiconductor manufacturer’s time between bake and bag. If the semiconductor manufacturer’s
actual time between bake and bag is different from the default value, use the actual time.
Y = Floor life of package after it is removed from dry pack bag.
Z = Total soak time for evaluation.
Factory Floor Life
Factory floor life conditions for Xilinx devices are clearly
stated on MBB containing moisture sensitive PSMCs.
These conditions have been ascertained by following Test
Methods outlined in JEDEC JESD22-A112 and are repli-
cated in Table 4. If factory floor conditions are outside the
stated environmental conditions (85°C/85% RH for level 1,
and 30°C/60% RH for Le v els 2-6) or if time limits hav e been
exceeded, then recovery can be achieved by baking the
devices before the reflow step. Identified in the ne xt section
are two acceptable bake schedules. Either can be used for
recovery to the required factory floor level.
Dry Bake Recommendation and Dry Bag
Policy
Xilinx recommends, as do the mentioned publications and
other industry studies, that all moisture sensitive PSMCs
be baked prior to use in surface mount applications, or
comply strictly with requirements as specified on the MBB.
Tape and Reeled par ts are universally dry packed. Level 1
parts are shipped without the need for, or use of, an MBB.
Two bake schedules have been identified as acceptable
and equivalent. The first is 24 hours in air at 125°C ., in ship-
ping media capable of handling that temperature. The sec-
ond bake schedule is for 192 hours in a controlled
atmosphere of 40°C, equal to or less than 5% RH.
Dry Devices are sealed in special military specification
Moisture Barrier Bags (MBB). Enough desiccant pouches
are enclosed in the MBB to maintain contents at less than
20% RH for up to 12 months from the date of seal. A revers-
ible Humidity Indicator Card (HIC) is enclosed to monitor
the internal humidity level. The loaded bag is then sealed
shut under a partial vacuum with an impulse heat sealer.
Artwork on the bags provides storage, handling and use
information. There are areas to mark the seal date, quan-
tity, and moisture sensitivity level and other information.
The following paragraphs contain additional information on
handling PSMCs.
Handling Parts in Sealed Bags
Inspection
Note the seal date and all other printed or hand entered
notations. Revie w the content inf ormation against what was
ordered. Thoroughly inspect for holes, tears, or punctures
that may expose contents. Xilinx strongly recommends that
the MBB remain closed until it reaches the actual work sta-
tion where the par ts will be removed from the factory ship-
ping form.
Storage
The sealed MBB should be stored, unopened, in an envi-
ronment of not more than 90% RH and 40°C. The enclosed
HIC is the only verification to show if the parts have been
exposed to moisture . Nothing in part appearance can v erify
moisture levels.
Table 4: Package Moisture Sensitivity Levels per JEDEC A112
Level Factory Floor Life Soak Requirements (Preconditioning)
Conditions Time Time Conditions
1≤30°C / 90%
RH Unlimited 168 hours 85°C / 85% RH
2≤30°C / 60%
RH 1 year 168 hours 85°C / 60% RH
Time (hours)
X + Y = Z
3≤30°C / 60%
RH 168 hours 24 168 192 ≤30°C / 60% RH
4≤30°C / 60%
RH 72 hours 12 72 84 ≤30°C / 60% RH
5≤30°C / 60%
RH 24 hours 6 24 30 ≤30°C / 60% RH
6≤30°C / 60%
RH 6 hours 0 6 6 ≤30°C / 60% RH
Packages and Thermal Characteristics
11-20 June 1, 1996 (Version 1.0)
Expiration Date
The seal date is indicated on the MBB. The expiration date
is 12 months from the seal date. If the expiration date has
been exceeded or HIC shows exposure beyond 20% upon
opening the bag bake the devices per the earlier stated
bake schedules. The three following options apply after
baking:
Use the devices within time limits stated on the MBB.
Reseal the parts completely under a partial vacuum
with an impulse sealer (hot bar sealer) in an approved
MBB within 12 hours, using fresh desiccant and HIC,
and label accordingly. Partial closures using staples,
plastic tape, or cloth tape are unacceptable.
Store the out-of-bag devices in a controlled atmosphere
at less than 20% RH. A desiccator cabinet with con-
trolled dry air or dry nitrogen is ideal.
Other Conditions
Open the MBB when parts are to be used. Open the bag by
cutting across the top as close to the seal as possible. This
provides room for possible resealing and adhering to the
reseal conditions outlined above. After opening, strictly
adhere to factory floor life conditions to ensure that devices
are maintained below critical moisture levels.
Bags opened for less than one hour (strongly dependent on
environment) ma y be resealed with the original desiccant. If
the bag is not resealed immediately, new desiccant or the
old one that has been dried out may be used to reseal, if
the factory floor life has not been exceeded. Note that
factory floor life is cumulative. Any period of time when
MBB is opened must be added to all other opened periods.
Both the desiccant pouches and the HIC are reversible.
Restoration to dry condition is accomplished by baking at
125°C for 10-16 hours, depending on oven loading condi-
tions.
June 1, 1996 (Version 1.0) 11-21
Tape and Reel
Xilinx offers a tape & reel pac king for PLCC , BGA, QFP, and
SO packages. The packing material is made of black con-
ductive Polystyrene and protects the packages from
mechanical and electrical damage. The reel material pro-
vides a suitable medium for pick and place equipment.
The tape & reel packaging consists of a pocketed carrier
tape, sealed with a protectiv e cov er . The device sits on ped-
estals (for PLCC, QFP packages) to protect the leads from
mechanical damage. All devices loaded into the tape carri-
ers are baked, lead scanned before the cover tape is
attached and sealed to the carrier. In-line mar k inspection
for mark quality and package orientation is used to ensure
shipping quality.
Benefits
• Increased quantity of devices per reel versus tubes
improves cycle time and reduces the amount of time to
index spent tubes.
• Tape & reel packaging enables automated pick and
place board assembly.
• Reels are uniform in size enabling equipment flexibility.
• Transparent cover tape allows device verification and
orientation.
• Anti-static reel materials provides ESD protection.
• Carrier design include a pedestal to protect package
leads during shipment.
• Bar code labels on each reel facilitate automated
inventory control and component traceability.
• All tape & reel shipments include desiccant pouches
and humidity indicators to insure products are safe from
moisture.
• Compliant to Electronic Industries Association (EIA)
481.
Material and Construction
Carrier T ape
• The pocketed carrier Tape is made of conductive
polystyrene material, or equivalent, with a surface
resistivity level of less than 106 ohms per square inch.
• Devices are loaded ‘live bug’ or leads down, into a
device pocket.
• Each carrier pocket has a hole in the center for
automated sensing of whether a unit is in the pocket or
not.
• Sprocket holes along the edge of the carrier tape
enable direct feeding into an automated board
assembly equipment.
Cover T ape
• An anti-static, transparent, polyester cover tape, with
heat activated adhesive coating, sealed to the carrier
edges to hold the devices in the carrier pockets.
• Surface resistivity on both sides is less than 1011 ohms
per square inch.
Reel
• The reel is made of anti-static P olystyrene material. The
loaded carrier tape is wound onto this conductive
plastic reel.
• A protective strip made of conductive Polystyrene
material is placed on the outer part of the reel to protect
the devices from external pressure in shipment.
• Surface resistivity is less than 1011 ohms per square
inch.
• Device loading orientation is in compliance with EIA
Standard 481.
Bar Code Label
• The bar code label on each reel provides customer
identification, device part number, date code of the
product and quantity in the reel.
• Print quality are in accordance with ANSI X3.182-1990
Bar Code Print Quality Guidelines. Presentation of Data
on labels are EIA-556-A compliant.
• The label is an alphanumeric, medium density Code 39
labels.
• This machine-readable label enhances inventory
management and data input accuracy.
Shipping Box
• The shipping container for the reels are in a 13” x 13” x
3” C-flute, corrugated, # 3 white ‘pizza’ box, rated to
200 lb test.
Packages and Thermal Characteristics
11-22 June 1, 1996 (Version 1.0)
l
Notes: 1.A minimum of 230mm of empty pockets are provided at the beginning (leader) of each reel.
2.A minimum of 160mm of empty pockets are provided at the end (trailer) of each reel.
3.Tape Leader/Trailer requirements are in compliance to EIA Standards 481.
4.Peel Strength between 20 and 120 grams ensures consistency during de-reeling operations and is compliant to EIA
Standard 481.
5.Each reel is subject to peel back strength tests.
6.For packages not listed above, please contact your Xilinx sales representative for updated information.
Standard Bar Code Label Locations
Table 5: Tape & Reel Packaging
Package T ype Pin Count Carrier
Width Cover
Width Pitch Reel Size Qty per
Reel
PLCC (Plastic Leaded Chip Carrier) 20 16 mm 13.3 mm 12 mm 7 inch 250
20 16 mm 13.3 mm 12 mm 13 inch 750
44 32 mm 25.5 mm 24 mm 13 inch 500
68 44 mm 37.5 mm 32 mm 13 inch 250
84 44 mm 37.5 mm 36 mm 13 inch 250
SO (Plastic Small Outline) 8 12 mm 9.2 mm 8 mm 7 inch 750
QFP (Plastic Quad Flat Pack) 100 44 mm 37.5 mm 32 mm 13 inch 250
160 44 mm 37.5 mm 40 mm 13 inch 200
BGA (Plastic Ball Grid Array) 225 44 mm 37.5 mm 32 mm 13 inch 500
June 1, 1996 (Version 1.0) 11-23
Reflow Soldering Process Guidelines
In order to implement and control the production of surface
mount assemblies, the dynamics of the solder reflow pro-
cess, and how each element of the process is related to the
end result, must be thoroughly understood.
The primary phases of the reflow process are as follows:
1. Melting the particles in the solder paste
2. Wetting the surfaces to be joined
3. Solidifying the solder into a strong metallurgical bond
The sequence of five actions that occur during this process
is shown in Figure 2.
Each phase of a surface mount reflow profile has min/max
limits that should be viewed as a process window. The pro-
cess requires a careful selection and control of the materi-
als, geometries of the mating surfaces (package footprint
vs. PCB land pattern geometries) and the time temperature
of the profile. If all of the factors of the process are suffi-
ciently optimized, there will be good solder wetting and fillet
formation (between component leads and the land patterns
on the substrate). If factors are not matched and optimized
there can be potential problems as summarized in Figure 3.
200
150
100
50
Temperature (°C)
Time
Solvent
Evaporation
Flux Reduces
Metal Oxides
Solder Balls Melt,
Wetting and Wicking Begin
Solder Melting Completes,
Surface Tension Takes Over
Cool Down Phase
Reflow Soldering Phases
X5975
Figure 2:
Time
Temperature
Potential Reflow Soldering Issues
X5976
1. Insufficient Temperature to Evaporate Solvent
2. Component Shock and Solder Splatter
3. Insufficient Flux Activation
4. Excessive Flux Activity and Oxidation
5. Trapping of Solvent and Flux, Void Formation
6. Component and/or Board Damage
2
1
4
3
5
6
Figure 3:
Packages and Thermal Characteristics
11-24 June 1, 1996 (Version 1.0)
Figure 4 and Figure 5 show typical conditions for solder
reflow processing using Vapor Phase or IR Reflow. The
moisture sensitivity of Plastic Surface Mount Components
(PSMCs) must be verified prior to surface mount flow. See
the preceding sections for a more complete discussion on
PSMC moisture sensitivity.
Time (s)
Temperature °C
2
3
Preheat & drying dwell
120 - 180 s
between 95° - 180°C
Temp = 183°C
2 - 4°C/s
t183
Ramp down
2 - 4°C/s
T-Max (leads)
220° - 235°C
60s < t183 < 120s
applies to lead area
X5973
Figure 4: Typical conditions for IR reflow soldering
Notes:
1. Max temperature range = 220°C-235°C (leads)
Time at temp 30-60 seconds
2. Preheat drying transition rate 2-4°C/s
3. Preheat dwell 95-180°C for 120-180 seconds
4. IR reflow shall be performed on dry packages
The IR process is strongly dependent on equipment and
loading differences. Components may overheat due to lack
of thermal constraints. Unbalanced loading may lead to
significant temperature variation on the board. This
guideline is intended to assist users in avoiding damage to
the components; the actual profile should be determined by
the users using these guidelines.
Time (s)
Temperature °C
2
Preheat & drying dwell
120 s min between
95° - 180°C
3
2
Ramp down
2 - 4°C/s
t183
Dwell = 30 - 60 s
215 - 219°C
≅ 45 s max
X5974
Figure 5: Typical conditions for vapor phase reflow
soldering
Notes:
1. Solvent - FC5312 or equivalent - ensures temperature
range of leads @ 215-219°C
2. Transition rate 4-5°C/s
3. Dwell is intended for partial dryout and reduces the
difference in temperature between leads and PCB
land patterns.
4. These guidelines are for reference. They are based on
laboratory runs using dry packages. It is
recommended that actual packages with known loads
be checked with the commercial equipment prior to
mass production.
June 1, 1996 (Version 1.0) 11-25
Sockets
Table 6 lists manufacturers known to offer soc k ets f or Xilinx
Package types. This summary does not imply an endorse- ment by Xilinx. Each user has the responsibility to evaluate
and approve a particular socket manufacturer.
Table 6: Socket Manufacturers
Manufacturer
Packages
DIP
SO
VO PC
WC
PQ
HQ
TQ
VQ PG
PP CB BG
CG
AMP Inc.
470 Friendship Road
Harrisburg, PA 17105-3608
(800) 522-6752
XX X
Augat Inc.
452 John Dietsch Blvd.
P.O. Box 2510
Attleboro Falls, MA 02763-2510
(508) 699-7646
XX X
McKenzie Socket Division
910 Page Avenue
Fremont, CA 94538
(510) 651-2700
XX X
3M Textool
6801 River Place Blvd.
Austin, TX 78726-9000
(800) 328-0411
(612) 736-7167
XX X
Wells Electronics
1701 South Main Street
South Bend, IN 46613-2299
(219) 287-5941
X
Yamaichi Electronics Inc.
2235 Zanker Road
San Jose, CA 95131
(408) 456-0797
XXXX
Packages and Thermal Characteristics
11-26 June 1, 1996 (Version 1.0)
Physical Dimensions
Plastic DIP Packages — PD8, PD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SOIC Packages — SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSOP Packages — VO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLCC Packages — PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PQFP Packages — PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304 . . . . . 32
TQFP Packages — TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VQFP Packages — VQ44, VQ64, VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
BGA Packages — BG225, BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ceramic DIP Packages — DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ceramic PGA Packages — PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299,
PG411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ceramic Brazed QFP Packages — CB100, CB164, CB196, CB228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
CLCC Packages — CC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Plastic PGA Packages — PP132, PP175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Windowed CLCC Packages — WC44, WC68, WC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Metal Quad Packages — MQ208, MQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
June 1, 1996 (Version 1.0) 11-27
Plastic DIP Packages — PD8, PD48
Packages and Thermal Characteristics
11-28 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-29
SOIC Packages — SO8
Packages and Thermal Characteristics
11-30 June 1, 1996 (Version 1.0)
TSOP Packages — VO8
June 1, 1996 (Version 1.0) 11-31
PLCC Packages — PC20, PC28, PC44, PC68, PC84
Packages and Thermal Characteristics
11-32 June 1, 1996 (Version 1.0)
PQFP Packages — PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208,
HQ240, HQ304
June 1, 1996 (Version 1.0) 11-33
Packages and Thermal Characteristics
11-34 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-35
Packages and Thermal Characteristics
11-36 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-37
Packages and Thermal Characteristics
11-38 June 1, 1996 (Version 1.0)
TQFP Packages — TQ44, TQ100, TQ144, TQ176, HT100, HT140, HT176
June 1, 1996 (Version 1.0) 11-39
Packages and Thermal Characteristics
11-40 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-41
Packages and Thermal Characteristics
11-42 June 1, 1996 (Version 1.0)
VQFP Packages — VQ44, VQ64, VQ100
June 1, 1996 (Version 1.0) 11-43
Packages and Thermal Characteristics
11-44 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-45
BGA Packages — BG225, BG352, BG432
Packages and Thermal Characteristics
11-46 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-47
Packages and Thermal Characteristics
11-48 June 1, 1996 (Version 1.0)
Ceramic DIP Packages — DD8
June 1, 1996 (Version 1.0) 11-49
Ceramic PGA Packages — PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175,
PG191, PG223, PG299, PG411
Packages and Thermal Characteristics
11-50 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-51
Packages and Thermal Characteristics
11-52 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-53
Packages and Thermal Characteristics
11-54 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-55
Packages and Thermal Characteristics
11-56 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-57
Packages and Thermal Characteristics
11-58 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-59
Packages and Thermal Characteristics
11-60 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-61
Ceramic Brazed QFP Packages — CB100, CB164, CB196, CB228
Packages and Thermal Characteristics
11-62 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-63
Packages and Thermal Characteristics
11-64 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-65
Packages and Thermal Characteristics
11-66 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 11-67
CLCC Packages — CC20
Packages and Thermal Characteristics
11-68 June 1, 1996 (Version 1.0)
Plastic PGA Packages — PP132, PP175
June 1, 1996 (Version 1.0) 11-69
Packages and Thermal Characteristics
11-70 June 1, 1996 (Version 1.0)
Windowed CLCC Packages — WC44, WC68, WC84
June 1, 1996 (Version 1.0) 11-71
Metal Quad Packages — MQ208, MQ240
Packages and Thermal Characteristics
11-72 June 1, 1996 (Version 1.0)
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Testing, Quality, and Reliability
Quality Assurance and Reliability
Quality Assurance Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Device Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Description of Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Package Integrity and Assembly Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Testing Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Memory Cell Design in the FPGA Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
High Temperature Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Testing, Quality, and Reliability
Table of Contents
June 1, 1996 (Version 1.0) 12-1
Quality Assurance Program
All aspects of the Quality Assurance Program at Xilinx ha v e
been designed to eliminate the root cause of defects , rather
than to try to remove them by inspection. A quality system
was put in place which is in full compliance with the require-
ments of ISO9002. Xilinx w as f ound to be in full compliance
of the requirements of ISO9002:1994 by an independent
auditor in October, 1995. At that time Xilinx was registered
for “the manufacturing and testing of programmable logic
devices”.
The aspects of ISO compliance in place at Xilinx include
the following seventeen points:
•Management Review: a comprehensive system of
management attention and direction for all aspects of
company performance that directly affect our
customers. These include (among others) Xilinx
performance in the areas of Quality, Reliability and On-
Time Delivery. Management assures that this quality
policy is understood, implemented and maintained at all
levels in the organization.
•Quality Systems: are in place to ensure that product
conforms to customer specifications. These systems
facilitate, measure and continuously improve Xilinx
performance in those areas that affect customer
satisfaction. Xilinx remains committed to achieving
100% customer satisfaction.
•Contract Review: is conducted to ensure each
contract adequately defines and documents
requirements, that differences between customer and
Xilinx standard specifications are mutually satisf actorily
resolved, and that Xilinx has the capability to meet
contract requirements.
•Document Control: procedures are established and
maintained to control all documents and data that relate
to the performance of Xilinx business and processing
requirements. All organizations who need access to
such documentation during the performance of their
functions are assured availability of the latest,
controlled versions of that documentation.
•Purchasing: procedures are in place to ensure that all
purchased products conform to the specified
requirements. As Xilinx is a “fabless” manufacturing
company, special attention is paid to our subcontract
partners. They are required to demonstrate the type of
control and capabilities that our customers require. All
key Xilinx subcontract partners are ISO certified.
•Product Identification & Traceability: is maintained
throughout the manuf acturing process . Traceability back
to the starting materials is available through unique
product identification techniques and markings
throughout the manufacturing process.
•Process Control: is assured by identifying and
controlling those processes that directly affect the
quality of our products, whether those processes are
performed directly by Xilinx, or by our subcontract
partners.
•Inspection & Test: is performed to ensure that
incoming product is not used or processed until it has
been verified as conforming to required specifications.
This inspection is done jointly by Xilinx and by its
subcontract partners.
•Inspection, Measuring and Test Equipment: is
calibrated in conformance with the requirements of Mil
Ref 45662 and/or other international standards.
Equipment is maintained in such a manner to ensure
that measurement uncertainty is known and is
consistent with specification requirements.
•Inspection & Test Status: of product is uniquely
identified throughout the manuf acturing process both at
Xilinx and at our subcontract partners. Records are kept
to identify the authority responsible for the release of
conforming production.
•Control of Non-Conforming Product: is assured
through disposition procedures that are defined in such
a manner as to prevent the shipping of non-conforming
products. The responsibility and authority for the
disposition of such products are well defined.
•Corrective Action: processes are documented and
implemented to prevent the recurrence of
nonconforming product. These processes are the key to
implementing the Xilinx strategy of eliminating the root
causes of nonconformity, rather that to apply inspection
to try to remove nonconformity.
•Handling, Storage, Packing & Delivery: procedures
are defined and implemented to prevent damage or
deterioration of product once the manufacturing
process is complete.
•Quality Records: procedures are established and
maintained for the identification, collection, indexing,
filing, storage, maintenance and disposition of quality
records.
•Internal Quality Audits: are carried out to verify
whether quality activities comply with planned
arrangements and to determine the effectiv eness of the
quality system. These audits are regularly
Quality Assurance and Reliability
June 1, 1996 (Version 1.0)
Quality Assurance and Reliability
12-2 June 1, 1996 (Version 1.0)
supplemented by quality audits performed by our
customers, and by our independent ISO auditors.
•Training: procedures have been established and are
maintained to identify the training needs of all personnel
affecting quality during the production of Xilinx
products. Personnel performing such activities are
qualified based upon appropriate education, training
and/or experience.
•Statistical Techniques: are in place at Xilinx and at our
subcontract partners for verifying the acceptability of
process capabilities and product characteristics.
These key requirements are in place at Xilinx and at our
subcontract partners to ensure our ability to achieve cus-
tomer satisfaction through the on-time delivery of quality
products that meet customer requirements and are reli-
able.
Device Reliability
Device reliability is often expressed in a measurement
called
Failures in Time
(FITs). In this measure one FIT
equals one failure per billion (109) device operating hours.
A failure rate in FITS must include the operating tempera-
ture to be meaningful. Hence failure rates are often
expressed in FITS at 70°C (or some other temperature in
excess of the application).
Since one billion hours is well in excess of 100,000 years,
the FIT rate of modern ICs can only be measured by accel-
erating the failure rate by testing at a higher junction tem-
perature (usually 125°C or 145°C). Extensive testing of
Xilinx devices (performed on actual production devices
taken directly from finished goods) has been accomplished
continuously since 1989 and reported quar terly. Quarterly
reports on the reliability of Xilinx products are available
through your Xilinx sales representativ e. During the last two
years, over 20,000 devices have accumulated a total of
ov er 36,000,000 hours of both static and dynamic operation
at 125°C (equivalent) to yield the FIT rates shown in
Figure 1.
Description of Tests
Die Qualification
1. High Temperature Life: This test is performed to evalu-
ate the long-term reliability and life characteristics of the
die. It is defined by the Military Standard from which it is
derived as a “Die-Related Test” and is contained in the
Group C Quality Conformance Tests. Because of the
acceleration factor induced by higher temperatures,
(typically 125°C and/or 145°C) data representing a large
number of equivalent hours at a normal temperature of
25°C can be accumulated in a reasonable period of
time.
2. Biased Moisture Life: This test is performed to evalu-
ate the reliability of the die under conditions of long-term
exposure to severe, high-moisture environments that
could cause corrosion. Although it clearly stresses the
package as well, this test is typically grouped under the
die-related tests. The device is operated at maximum-
rated voltage, 5.5 Vdc, and is exposed to a temperature
of 85°C and a relative humidity of 85% throughout the
test.
Package Integrity and Assembly
Qualification
1. Unbiased Pressure Pot: This test is performed at a
temperature of 121°C and a pressure of 2 atm of satu-
rated steam to evaluate the ability of the plastic encap-
sulating material to resist water vapor. Moisture
penetrating the package could induce corrosion of the
bonding wires and nonglassivated metal areas of the die
(bonding pads only for FPGA devices). Under extreme
conditions, moisture could cause drive-in and corrosion
under the glassivation. Although it is difficult to correlate
this test to actual field conditions, it provides a well-
established method for relative comparison of plastic
packaging materials and assembly and molding tech-
niques.
Failure Rate in FITs @ 70°C
-10
0
10
20
30
40
50
6/94 9/94 10/94 3/95 6/95 9/95 12/95
Time
Failure Rate
XC1700
XC3100
X5977
XC4000
XC3000
XC2000
Figure 1: Failure Rates in FITs
June 1, 1996 (Version 1.0) 12-3
2. Thermal Shock: This test is performed to evaluate the
resistance of the package to cracking and resistance of
the bonding wires and lead frame to separation or dam-
age. It involves nearly instantaneous change in temper-
ature from -65°C to +150°C (condition “C”).
3. Temperature Cycling: This test is performed to evalu-
ate the long-term resistance of the package to damage
from alternating exposure to temperature extremes. The
range of temperatures is -65°C to +150°C (condition
“C”). The transition time is longer than that in the Ther-
mal Shock test but the test is conducted for many more
cycles.
4. Salt Atmosphere: This test was originally designed by
the US Navy to evaluate resistance of military-grade
ship-board electronics to corrosion from sea water. It is
used more generally for non-hermetic industrial and
commercial products as a test of corrosion resistance of
the package marking and finish.
5. Resistance to Solvents: This test is performed to eval-
uate the integrity of the package marking during expo-
sure to a variety of solvents. This is an especially
important test, since an increasing number of board-
level assemblies are subjected to severe conditions of
automated cleaning before system assemb ly. This test is
performed according to the methods specified by MIL-
STD-883.
6. Solderability: This test is performed to ev aluate the sol-
derability of the leads under conditions of low soldering
temperature following exposure to the aging effects of
water vapor.
7. Lead Fatigue: This test is performed to evaluate the
resistance of the completed assembly to vibrations dur-
ing storage, shipping, and operation.
Testing Facilities
Xilinx has complete capability to perform High Temperature
Life Testing, Ther mal Shock, Temperature Cycling, Biased
Moisture Life Test, Unbiased Pressure Pot, Solderability
and Hermeticity, as well as complete Failure Analysis in
house. Table 1 and Table 2 show typical qualification
requirements for new and/or changed process flows.
Table 3 is a list of current f ailure analysis capabilities. These
laboratories are dedicated exclusively to increasing cus-
tomer satisfaction through continuous improvements in our
processes and technologies.
Quality Assurance and Reliability
12-4 June 1, 1996 (Version 1.0)
Notes: 1) Test method and stress conditions available upon request.
2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is
required.
3) Any new package which has not been qualified in the qualified assembly facility.
4) Any new package where the same body size with different lead pitch has been qualified.
5) New leadframe design whereby the paddle size is larger than the existing leadframe paddle size used in the same qualified
package.
6) For new mask from same device family, only high temp life test, ESD, Latch & Capacitance are required.
7) In-process monitor data may be used to satisfy this requirement.
*) Electrical rejects can be used as test sample.
**)This is a non-destructive test, sample can be re-used.
Table 1: Plastic Package/Product Qualification Requirements
New Assy Techniques (Mat’l/Process/Method
T est
Seq T est Description
(note 1) Acc#
S.Size
(note 2)
New
Assy
Plant
New
Pkg
T ype I
(note3)
New
Pkg
T ype II
(note4)
New
Pkg
T ype
III LF
Design
(note5)
Lead
Frame Die
Attach Die
Coat Wire
Bond Mold
CLP Lead
Finish New
Device
Mask
(note6)
New
Fab
Proc
Full
Qual
B1 * Phy. Dimension 0/5 X X X X X
B2 * Resist. to Solvents 0/3 X X X X
B3 * Solderability Test (note 7) 0/5 X X X X
B4 Solder Heat Test (Optn’l) 0/15 X X X X
B5 Auto Clave (SPP)(Optn’l) 0/76 0/76 XXXXXXXXX
B6 * Ball Shear/Bond Pull (note 7) 0/5 X X X X X X X X
B7 ** X-Ray (note 7) 0/5 XXXX XXX X X
B8 * S.A.T/Dye Pen Test (note 7) 0/10 XXXXX XX X
B9 * Adhesion of L/Finish (Optn’l) 0/3 X X X X
B10 * External Visual (note 7) 0/25 XXXXX X X
B11 Internal Visual (note 7) 0/5 X X X XXXX XXX
B12 * Die Shear (note 7) 0/5 X X X X X
B13 Flammability Test (note 7) Per lot XX
C1-A High Temp Life Test 0/76 X X X X
C1-B Low Temp Life Test (note 7) 0/22 XXX
C2 C2-A:HAST (0/22) or C2-B: 85/85 0/76 X X XXXX X XX
C3 ESD (HBM) 0/3 XXX
C4 High Temp Storage (Optn’l) 0/77 X XXX
D1 * Lead Integrity 0/3 X X X X X
D2 Thermal Shock (Optn’l) 0/76 X
D3 Temp Cycle 0/76 XXXXXXXXX XX
E1 Electrical Test & Data Log 0/30 XXX
E2 Electrical Characterization 0/30 XXX
E3 T.D.D.B (note 7) – XXX
E4 Latch-up 0/9 XXX
E5 Electromigration (note 7) – XXX
E6 Photosensitivity (Optn’l) 0/11 XXX
E7 Data Retention Bake EPLD & EPR 0/22 XXX
E8 Input/Output Capacitance 0/5 XXX
E9 Power Cycling (Optn’l) 0/22 XXX
E.Good 239 238 162 248 248 157 314 86 325 0 393 464 636
Qty required per lot E.Reject 63 48 43 35 43 5 5 5 43 29 10 10 64
Total 302 286 205 283 291 162 319 91 368 29 403 474 700
June 1, 1996 (Version 1.0) 12-5
Notes: 1) Test method and stress conditions available upon request.
2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is
required.
3) Package Family - A set of package type with the same package, material, Package construction techniques, terminal pitch,
lead shape, row spacing and with identical package assembly tech.
4) Package Type - A package with a unique case outline, configuration, material, piece parts and assembly process.
5) Application to new piece parts or leadframe where cavity size is larger than the largest cavity size for the same package.
6) For new mask from same device family, only high temp life test, ESP, Latch & Capacitance are required.
7) In-process monitor data may be used to satisfy this requirement, for Qual data, data from Assy. lot traveler maybe used.
*) Electrical rejects can be used as test samples
Table 2: Hermetic Package/Product Qualification Requirements (Commercial)
New Assy Techniques (Mat’l/Process/Method
T est
Seq T est Description
(note 1) Acc#
S.Size
(note 2)
New
Assy
Plant
New
Pkg
Family
(note3)
New
Pkg
Qual
Family
(note4)
Lead
Frame Die
Attach Die
Coat Wire
Bond Type of
Seal Lead
Finish New
Cavity
Size
(note6)
New
Device
(note6)
New
Fab
Proc
Full
Qual
B1 Solder Heat Test (Optn’l) 0/15 X X X X X
B2 * Resist. to Solvents (note 7) 0/3 X X X X
B3 * Solderability Test (note 7) 0/3 X X X X X
B4 * Die Shear/Stud Pull (note 7) 0/5 X X X X X X X
B5 * Bond Pull (note 7) 0/2 XXXX XX XXX
B6 * External Visual (note 7) 0/25 XXXX X X X
B7 Internal Visual (note 7) 0/5 XXXXXXX XXX
C1-A High Temp Life Test 0/76 X X X X X X X
C1-B Low Temp Life Test (note 7) 0/22 XXX
C2 High Temp Storage (Optn’l) 0/77 X X X X
C3 ESD (HBM) 0/3 XXX
D1 * Phy. Dimension 0/15 X X X X X X X
D2 * Lead Integrity 0/3 XXXX X XX
D3 Thermal Shock + Temp Cycl +
Moisture Resistance 0/32 XXXXXXXXXXXXX
D4 Mech. Shock + Vibration + Con-
stant Acceleration 0/32 XXXXX XX XXXX
D5 * Salt Atmosphere 0/15 X X X X X X
D6 * Internal Vapor Content (note 7) 0/3 X X X X XXXX X
D7 * Adhesion of L/Finish (Optn’l) 0/2 XXXX X XX
D8 * Lid Torque 0/5 X X X X X X X
D9 Temp Cycle 0/45 X X X XXXX XXXX
E1 Electrical Test & Data Log 0/30 XXX
E2 Electrical Characterization 0/30 XXX
E3 T.D.D.B (note 7) – XXX
E4 Latch-up 0/9 XXX
E5 Electromigration (note 7) – XXX
E6 Photosensitivity (Optn’l) 0/11 XXX
E7 Data Retention Bake 0/22 XXX
E8 Input/Output Capacitance 0/5 XXX
E.Good 190 205 129 69 114 235 190 124 32 124 399 399 414
Qty required per lot E.Reject 81 81 75 50 8 5 2 33 41 48 7 50 81
Total 271 286 204 119 122 240 192 157 73 172 406 449 495
Quality Assurance and Reliability
12-6 June 1, 1996 (Version 1.0)
Data Integrity
Memory Cell Design in the FPGA Device
An important aspect of SRAM-based FPGA device reliabil-
ity is the robustness of the static memory cells used to store
the configuration program.
The basic cell is a single-ended 5-transistor memory ele-
ment (Figure 2). By eliminating a sixth transistor, which
would have been used as a pass transistor for the comple-
mentary bit line, a higher circuit density is achiev ed. During
normal operation, the outputs of these cells are fixed, since
they determine the user configuration. Write and readback
times, which have no relation to the device performance
during normal operation, will be slower without the extra
transistor. In return, the user receives more functionality
per unit area.
This explains the basic cell, but how is the FPGA user
assured of high data integrity in a noisy environment? Con-
sider three different situations: normal operation, a Write
operation and a Read operation. In the normal operation,
the data in the basic memory element is not changed.
Since the two circularly linked inverters that hold the data
are physically adjacent, supply transients result in only
small relative differences in voltages. Each inver ter is truly
a complementary pair of transistors. Therefore , whether the
output is High or Low, a low-impedance path exists to the
supply rail, resulting in extremely high noise immunity.
Power supply or ground transients of several volts have no
effect on stored data.
The transistor driving the bit line has been carefully
designed so that whenever the data to be wr itten is oppo-
site the data stored, it can easily override the output of the
feedback inverter. The reliability of the Write operation is
guaranteed within the tolerances of the manufacturing pro-
cess.
Table 3: Failure Analysis Equipment List
Item Equipment Vendor Model
Number Item Equipment Vendor Model
Number
1Scanning Electron Microscope JEOL JMS-6401F 17 Die-Shear Tester KELLER see #7
2Gold Sputter (SEM Sample
Prep) ANATECH Hummer VIII 18 Steam Aging System Robotic
Systems ST2D
3Energy Dispersive X-Ray OXFORD
INST. LINK ISIS-
L200C 19 Solder Wave/Pot Robotic
Systems RPS-202
4F.I.B. - Focused Ion Beam
Workstation F.E.I. FIB-600 20 Lead Fatigue Tester B & G 004-012-00
5Real-Time X-Ray Imaging Sys-
tem FEIN FOCUS FXS-100.10 21 Conventional Oven (C.D.A.) BID Services
6Scanning Acoustic Microscopy Sonix Micro-Scan
4HF-200 22 Drill-bit to open MQUADS
+ Decapping vise
7Ball Shear Strength Tester KELLER MBS-200 23 Color Printer Tektronic Tektronic
Phaser IISD
8XRF Lead Finish/Composition
Measurement System Twin City, Inc. XRF-5500 24 Stud Pull Tester B & G 003-010-00
9Liquid Crystal Hot Spot Detec-
tion System/Kit, with 3 temp. Technology
Associates P/N 4330 25 Work Benches
10 Emission Microscope for
Multilayer Inspection (EMMI) Hypervision Visionary
2000 26 Cabinets
11 Curve Tracer BID Services 27 Facilities (Lab Area and
Equipment Installation Costs)
12 Metallurgical High Power
Microscope Scientific
Instrument
Company
see quote
(various) 28 Tool Maker Microscope
13 Stereozoom Low Power
Microscope - video camera +
monitor
Scientific
Instrument
Company
see quote
(various) 29 Flowhood & Rinse Station
14 Micro-Etcher System TM Associates 30 Precision X-Sectioning Equip-
ment
15 Viseco Camera Interface with
High Power Microscope Computer
Modules 31 Plasma Etcher March
Instruments CS-1701
16 Hermeticity Test System
- Fine Leak
- Gross Leak
BID Services -Trio-tech 486
- Veeco MS-
170
32 E-Beam IDS-3000
June 1, 1996 (Version 1.0) 12-7
In the Read mode, the bit line, which has a significant
amount of parasitic capacitance, is precharged to a logic
one. The pass transistor is then enabled b y driving the word
line High. If the stored value is a zero, the line is then dis-
charged to ground. Reliable reading of the memory cell is
achieved by reducing the word line High level dur ing read-
ing to a level that insures that the cell will not be disturbed.
Electrostatic Discharge
Electrostatic-discharge (ESD) protection for each pad is
provided b y circuitry that uses distributed tr ansistors and/or
diodes, represented by the circles in Figure 3. In older
devices, these protection circuits are conventional diffused
structures. In newer designs, Xilinx utilizes proprietary
device structures which exhibit substantially enhanced
ESD performance (see Table 4).
Whenever the voltage on a pad approaches a dangerous
level, current flows through the protective structures to or
from a power supply rail (VCC or ground). In addition, the
capacitances in these structures integrate the pulse to pro-
vide sufficient time for the protection netw orks to clamp the
input, avoiding damage to the circuit being protected.
Geometries and doping levels are chosen to provide ESD
protection on all pads for both positive and negative volt-
ages.
Table 4: ESD Performance of Xilinx Components
DS Q
SEL
DR
DK
DS Q
SEL
DR
DK
Configuration Data Shift Regiater
Memory Cell
Memory
Cell
Circuit Memory
Cell
Memory
Cell
Memory
Cell
D Q
CK
Clock Address QN-1
Word
Line
Driver
D Q
CK
Word
Line
Driver
Bit M+1
Bit M
Word N+1
Word N
Precharge
WR/RD
Q N-1
Data Clock
Configuration
Address
Shift Regiater
Read
VCC
VCC
X3124
Figure 2: Configuration Memory Cell
Circuit
Family
Human Body
Model
883D
Method 3015
Machine
Model
EIAJ
Method 20
Charged
Device
Model CDM
XC1700D >6,000 V 800 V – 900 V >2,000 V
XC2000 2,000 V – 2,500 V 250 V – 280 V
XC3000A 3,000 V – 8,000 V 600 V – 700 V >2,000 V
XC3100 2,500 V – 3,500 V 600 V – 700 V
XC4000 4,000 V – 9,000 V 800 V – 900 V >2,000 V
XC4000E 4,000 V– 5,000 V 600 V– 900 V >2,000 V
XC5200 3,000 V– 5,000 V tbd
XC7000 2,000 V– 4,000 V 250 V– 300 V >2,000 V
Quality Assurance and Reliability
12-8 June 1, 1996 (Version 1.0)
Latchup
Latchup is a condition in which parasitic bipolar transistors
form a positive feedback loop (Figure 4), which quickly
reaches current levels that permanently damage the
device. Xilinx uses techniques based on doping levels and
circuit placement to avoid this phenomenon. The beta of
each parasitic transistor is minimized by increasing the
base width. This is achieved with large physical spacings.
The butting contacts eff ectiv ely short the n+ and p+ regions
for both wells, which makes the VBE of each parasitic very
close to zero. This also makes the parasitic tr ansistors very
hard to forward bias. Finally, each well is surrounded by a
dummy collector, which forces the VCE of each parasitic
almost to zero and creates a structure in which the base
width of each parasitic is large, thus making latchup
extremely difficult to induce.
At elev ated temperatures , 100 mA will not cause latchup. At
room temperature, the FPGA can withstand more than 300
mA without latchup; the EPLD device can withstand more
than 200 mA without latchup. However, to avoid metal-
migration problems, continuous currents in excess of 10
mA are not recommended.
High Temperature Performance
Although Xilinx guarantees parts to perform only within the
specifications of the data sheet, extensive high tempera-
ture life testing has been done at 145°C with excellent
results.
Output
Ground
Input
VCC
RIN
ROUT
Pad
Ground
VCC
= Symbol for electrostatic discharge protection circuit X3132
Figure 3: Input/Output Protection Circuity
Pad
VCC
X1825
Figure 4: SCR Model
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Technical Support
Technical Support
Technical Support Hotlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Hotline Support, Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
X-TALX: The Xilinx Network of Electronic Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
WebLINX World Wide Web Site
(www.xilinx.com). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
XDOCs E-mail Document Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
XFACTS Document Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Xilinx Technical Bulletin Board Service (408) 559-9327. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
E-mail addresses for questions related to specific applications . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Technical Support E-mail addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Technical Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
AppLINX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
XCELL Newsletter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
What You Will Learn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
The Training Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Hands-On Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Instructors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Course Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Product Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Schematic-Based Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Synthesis-Based Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Synthesis-Based Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Update and Advanced Training Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Training Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Customer-Site Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Technical Support Table of Contents
June 1, 1996 (Version 1.0) 13-1
A complete and uniquely accessible offering of worldwide
technical support services is available to Xilinx users.
Xilinx Field Application Engineers, located at sales offices
and technical support centers worldwide, provide local
engineering support, including design evaluation of new
projects, close consultation throughout the design process,
special training assignments, and new product presenta-
tions. Because their role as advisors and troubleshooters
keeps them constantly on the go , they are best used, not f or
general questions, but for more targeted queries such as
those related to architectural recommendations. The world-
wide network of Xilinx sales representatives and distribu-
tors also provide local technical support for Xilinx users.
More general queries can be directed to the telephone “hot-
lines”. Permanent teams of expert Technical Suppor t Engi-
neers located in the United States, United Kingdom,
France, Germany, and Japan can handle problems and
answer questions right on the spot, ensuring that the
design process keeps moving forward.
In addition, Xilinx has several automated services, collec-
tively referred to as X-TALX, to provide answers to user’s
queries 24 hours a day. These include a world wide web
site, E-mail server, automated FAX system, bulletin board
system, and special interest E-mail groups.
Many different publications assist users in completing
designs quickly and efficiently, including technical manuals,
data sheets, the AppLINX CD-ROM (a regularly-updated
collection of the latest application notes and design hints),
and the quarterly XCell newsletter.
For more in-depth support and instruction, a dedicated
training organization conducts technical training classes
worldwide. Courses geared for both novice and experi-
enced users are available.
The following Technical Support Ser vices are discussed in
more detail in this chapter:
• Technical Support Hotline
• X-TALX: The Xilinx Network of Electronic Services
- WebLINX W orld Wide Web Site
- XDOCs E-mail document server
- XFACTS document server
- Xilinx Technical Bulletin Board Service
• Technical Literature
• AppLINX CD-ROM
• XCELL newsletter
• Training Courses
Technical Support
June 1, 1996 (Version 1.0)
Technical Support
13-2 June 1, 1996 (Version 1.0)
Technical Support Hotlines
The technical suppor t hotlines give Xilinx users direct tele-
phone access to Xilinx Technical Support Engineers world-
wide, providing a quick resolution to any problem that
occurs during the design process. Technical questions also
may be submitted via FAX or E-mail.
Hotline Support, U.S.
Hotline Support, Japan
telephone: (81) 3-3297-9163
fax: (81) 3-3297-0067
e-mail: jhotline@xilinx.com
Hotline Support, Europe
UK, London Office
telephone: (44) 1932 820821
fax: (44) 1932 828522
Bulletin Board Service: (44) 1932 333540
e-mail: ukhelp@xilinx.com
France, Paris Office
telephone: (33) 1 3463 0100
fax: (33) 1 3463 0959
e-mail: frhelp@xilinx.com
Germany, Munich Office
telephone: (49) 89 991 54930
fax: (49) 89 904 4748
e-mail: dlhelp@xilinx.com
Customer Support
Hotline 800-255-7778
Hrs: 8:00 a.m. - 5:00 p.m. Pacific
time
Customer Support
Fax Number 408-879-4442
Avail: 24 hrs/day-7 days/week
E-mail Address hotline@xilinx.com
Electronic Technical
Bulletin Board 408-559-9327
Customer Service
(Call for software up-
dates, authorization
codes, documentation
updates, etc.)
408-559-7778,
Ask for customer service
June 1, 1996 (Version 1.0) 13-3
X-TALX: The Xilinx Network of Electronic Services
WebLINX W orld Wide Web Site
(www.xilinx.com)
Our World Wide Web site provides access to current infor-
mation, including product data sheets, application notes,
press releases, financial status, employment opportunities,
and an on-line technical support database.
Smart
Search,
our industry-wide search engine, is the definitive resource
for programmab le logic information.
Smart
Search Agents
will watch the Web for y ou and inform you, via e-mail, when
new or updated information is found. An FTP site also is
available to facilitate the quick and easy transfer of design
and data files (ftp.xilinx.com).
XDOCs E-mail Document Server
The XDOCS E-mail system provides 24-hour a day, 7 days
a week access to the same database that the Technical
Support Engineers use. This database is updated regularly
with information on bugs, workarounds, and helpful hints.
Via E-mail, users can search for a specific record, or supply
keywords to trigger a search of the database; XDOCS will
send the requested information by return E-mail. Auto-
mated updates also can be sent on a periodic basis notify-
ing users of new additions to the system. To subscribe to
XDOCS, send an E-mail to xdocs@xilinx.com with “help”
as the only word in the subject header.
XFACTS Document Server
The XFACTS automated FAX system provides the same
information as XDOCS, but uses a phone/FAX interface
instead of E-mail. Using a touch-tone telephone, users can
request documents that are sent to their FAX machine.
Located in San Jose, California, the XFACTS system can
be reached at 408-879-4400.
Xilinx Technical Bulletin Board Service
(408) 559-9327
To provide users with up-to-date information and software
suppor t, Xilinx provides a 24-hour electronic bulletin board
system (BBS). The Xilinx Technical Support BBS is avail-
able to all registered Xilinx development system users.
Users with full privileges can browse files on the bulletin
board, download those of interest, or upload files to Techni-
cal Support Engineers.
All BBS files can be accessed through the Xilinx Web and
FTP locations.
New bulletin board users must answer a questionnaire
when they first access the BBS. After answering the ques-
tionnaire, callers can browse through the file areas or
upload files. A caller with a valid XACT protection key or
valid host ID will be given full user privileges within 24
hours.
The software and hardware requirements for accessing the
BBS are as follows:
Baud Rate 28.8K or less bps
Character Format 8 data bits, no parity, 1 stop bit
Transfer Protocols ASCII, Xmodem, Ymodem, Zmodem
The Xilinx Technical Support BBS is a menu-driv en system.
To choose a menu command, simply type the highlighted
first letter of the command. Most commands are “hot keys”
and do not require you to press the return key. Here is a
quick description of the available menu commands:
Main
U)pload Upload a file to the Technical Suppor t
group.
D)ownload Download a file. This assumes you
already know the filename, otherwise
select the File Manager.
F)ile Manager Takes you to the File Manager menu.
This menu is for locating files.
S)ystem Folder Takes you to the System menu. This
menu is for changing your password,
display options, etc.
File Manager
F)lag Flag files for download.
L)ocate Files Use wildcards to search for files.
N)ew Files Lists recently added files.
Z)ippy DIR scan Searches for text in file descriptions.
#’s Chooses a file area to browse.
System
M)ode of display Toggles between text and graphics
display
P)age length Changes the number of printed lines
between “More?” prompts.
T)ransfer Protocol Changes the default transfer protocol.
V)iew Settings Shows current settings and user infor-
mation.
W)rite User Info Changes current user settings.
Technical Support
13-4 June 1, 1996 (Version 1.0)
E-mail addresses for questions related to
specific applications
Technical Support E-mail addresses
Digital Signal Processing
applications dsp@xilinx.com
PCI-bus applications pci@xilinx.com
Plug and Play ISA applications PnP@xilinx.com
PCMCIA card applications pcmcia@xilinx.com
Asynchronous Transfer Mode
applications atm@xilinx.com
Reconfigurable Computing
applications reconfig@xilinx.com
hotline@xilinx.com USA, Xilinx Headquarters
ukhelp@xilinx.com United Kingdom
frhelp@xilinx.com France
dlhelp@xilinx.com Germany
jhotline@xilinx.com Japan
June 1, 1996 (Version 1.0) 13-5
Technical Literature
Xilinx offers many different publications to assist users in
completing designs quickly and efficiently. These include
technical manuals, Data Books, data sheets, application
notes, AppLINX CD, and the XCELL newsletter. Many of
these publications are available on-line at the Xilinx
WebLINX W orld Wide W eb site.
As part of the development system products, Xilinx pro-
vides manuals and supporting documents for the develop-
ment system tools, libraries, CAE tool interfaces, and
related software tools. Many of these manuals are av ailable
on the CD that holds the software as well as hardcopy for-
mat. On-line help facilities also are an integral part of the
development system products.
AppLINX
AppLINX is a collection of current application notes and
other new technical documentation pro vided on a CD-ROM
for easy reference by the design engineer. All the material
on the CD is provided in Adobe Acrobat format for easy
viewing and printing. The AppLINX CD is updated regularly
as new material becomes available.
XCELL Newsletter
XCELL, the quar ter ly jour nal for Xilinx programmable logic
users, is dedicated to supplying up-to-date information for
system designers. A typical issue includes descriptions of
new products, updates on component and software avail-
ability and revision levels, application ideas, design hints
and techniques, and answers to frequently-asked ques-
tions.
To add your name to the XCELL subscription list, please
send your name, company affiliation, and mailing address
to Brad Fawcett, XCELL editor , via FAX at 408-879-4676 or
via e-mail sent to brad.fawcett@xilinx.com.
Technical Support
13-6 June 1, 1996 (Version 1.0)
Programmable Logic Training
Courses
All users of Xilinx products should attend one of our Train-
ing Courses. Attending a Xilinx Training Course is one of
the fastest and most efficient ways to learn how to design
with FPGA or CPLD devices from Xilinx. Hands-on exper t
instruction with the latest information and software will
allow you to implement your own designs in less time with
more effective use of the devices.
Xilinx offers a variety of classes to meet your specific
needs. Training centers around the world schedule classes
on a regular basis, and the classes can even be brought to
your own facility.
What Y ou Will Learn
Not only will you learn about our products, but we will rec-
ommend the best ways to use the software based on our
years of experience with thousands of designs. You will
learn how to efficiently enter, implement, and verify your
design. The powerful yet easy-to-use Xilinx development
system allows you to utilize the Xilinx automatic mode, or
take a power-user approach and direct the automatic tools
to the best implementation of your design.
Prerequisites
Students need only have a background in digital logic
design. Basic familiarity with the PC or workstation is help-
ful but not required. It will benefit you to learn your design
entry tool of choice before attending the Xilinx class, includ-
ing an HDL language for the synthesis-based classes.
Update or Advanced classes require previous experience
with the Xilinx products.
Benefits
• Start or Complete Your Design During the Class
• Reduce Your Learning Time
• Make Fewer Design Iterations
• Get to Market Faster
• Lower Production Costs
• Increase Quality
The T raining Classes
Xilinx offers classes for both schematic entry users and
synthesis users, and both new and experienced users. All
Xilinx classes focus on the Xilinx products, independent of
the specific design entry tool.
Hands-On Experience
Each class includes over two hours each day for hands-on
labs. There is at least one computer for every two people in
the class.
Instructors
Xilinx Training Courses have been successfully held world-
wide for over six years. The instructors are Xilinx experts
who are skilled at passing that knowledge on to f ellow engi-
neers. A dedicated Training organization at Xilinx works
closely with the Applications and Engineering groups to
keep the classes up-to-date with the latest improvements
and recommendations for Xilinx and third-party tools.
Course Materials
All course materials are supplied by Xilinx. Every student
gets an excellent ref erence tool in the f orm of course notes,
that include all the material presented during the class. The
course notes are bound for easy use and include additional
reference material beyond what is covered in the class.
Product Coverage
Xilinx classes will cover the latest released versions of our
devices and de v elopment systems. While all a vailab le prod-
ucts are covered, emphasis is placed on the more popular
and/or recommended solutions. Ne w products are added to
the class as they become available.
June 1, 1996 (Version 1.0) 13-7
Schematic-Based Course Outline
The schematic-based Xilinx Training Class lasts three da ys.
All North American training sites, and most international
locations, teach the same class.
• Introduction
- Development System Overview
- Architecture Overview
• Xilinx Design Flow
- Schematic Entry Guidelines
- Design Manager
- Flow Engine Automatic Translation
• Timing Specification
- XACT-Performance Delay Specification
- Static Timing Analyzer
• Designing for Xilinx FPGAs
- Combinatorial Logic
- Registered Logic
- Memory Design
- I/O Design
- X-BLOX Module Generation
• Designing for Xilinx CPLDs
• Text Entry Guidelines
- Xilinx-ABEL software
• Floorplanning
- Incremental Design
- XACT-Floorplanner
- Relationally-Placed Macros
• Timing Analysis
- Good Design Practices
- Simulation Guidelines
• Configuration
- Programming Modes
- Bitstream Generator
- PROM File Formatter
- Hardware Debugger Download & Readback
Synthesis-Based Classes
Designing with high-level languages (VHDL and Verilog)
and synthesis tools can be very different from using sche-
matic entry. As a result, Xilinx offers classes that focus on
VHDL and Verilog design entry for Xilinx products. Xilinx
highly recommends the synthesis-based class for anyone
using VHDL or Verilog for design entry. Synthesis-based
classes include the following additional topics, using HDL
code for design entry:
• Good coding styles
• Hierarchy within synthesis
• Synthesis design flow
• Controlling Xilinx implementation tools with synthesis
Synthesis-Based Course Outline
The follo wing is a complete outline of the three-day synthe-
sis-based class:
• Introduction
• FPGA Architecture
• Xilinx-Synopsys Design Flow
- Good Coding Styles
- Synopsys Scripts
- Design Manager
- Automatic Translation
• Timing Specification
- XACT-Performance Delay Specification
- Static Timing Analyzer
• Simulation Guidelines
• Good Design Practices
• Coding for Xilinx FPGAs
- Combinatorial Logic
- Carry Logic and X-BLOX Module Generation
- Registered Logic
- I/O Design
- Memory Design
• Hierarchy
• Floorplanning
- Incremental Design
- XACT-Floorplanner
• Configuration
- Programming Modes
- Bitstream Generator
- PROM File Formatter
- XChecker Download & Readback
Update and Advanced Training Classes
If you have already attended a Xilinx class or have experi-
ence using Xilinx products, consider attending a one-day
Update or Advanced Training session. These sessions will
be most useful if you have the latest software.
Update Classes
One-day Update classes focus on the latest released prod-
ucts from Xilinx, describing them in relation to previous v er-
sions. For example , an Update class is a v ailab le describing
the new features in XACT
step
6.0. The class will be offered
for a limited time at regional sites , or can be brought to y our
facility. Browse the Xilinx web site (www.xilinx.com) for the
latest information regarding special Update classes on new
products from Xilinx.
Technical Support
13-8 June 1, 1996 (Version 1.0)
Advanced T raining Classes
If you have already attended a Xilinx class or have experi-
ence using Xilinx products, consider attending a one-day
Advanced Training session. Advanced Training classes are
offered at no charge to current in-warranty Xilinx custom-
ers; otherwise tuition is $200. Advanced Training sessions
can vary according to the interests of the students. P opular
topics include:
• Example Logic Design Techniques
• Timing Analysis and Avoiding Timing Hazards
• Design Methodology for Tough Designs
• Details of Advanced Optimization Capabilities
• XACT Design Editor
• Floorplanning
Advanced Training classes are held regularly at Xilinx
headquarters, and sometimes at regional locations , b ut are
replaced by Update Classes when appropriate. See the
web site (www .xilinx.com) f or scheduled classes , or contact
Xilinx Training to hold an Advanced Training session at your
site.
Training Locations
Xilinx Headquarters
Classes are held regularly at Xilinx headquarters in San
Jose, California. During the class, you may elect to meet
one-on-one with Xilinx Applications engineers to discuss
specific issues not cov ered in the class . Topics ma y include
using a specific third-party tool, optimizing your particular
design, or more advanced issues beyond the coverage of
the class.
North American Distributor Locations
Xilinx distributors sponsor training classes jointly with Xil-
inx, using the same material as the headquar ters classes.
Since the distributor sponsors the class, the tuition cost is
often reduced to $495 for customers of the sponsoring dis-
tributor. Check with the distributor when registering. Loca-
tions include over fifty cities across North America.
International Locations
Xilinx classes are held throughout Europe, Asia, India,
Israel, South Africa, Australia, South America, and other
international locations. Classes vary in length and tuition,
but are based on the same material used in North America.
Contact your local Xilinx sales office or representative for
classes in your area.
Customer-Site Classes
Xilinx can bring a Training Course to your o wn facility f or the
greatest convenience to your company.
On-Site Classes Provide Additional Benefits:
No T ravel Costs
On-site Xilinx training classes eliminate travel time and
expenses:
- No airfare
- No hotel bills
- No car rental
Classes T ailored To Y our Needs
On-site classes can be tailored to meet the specific needs
of your company:
- Convenient class time and location
- Projects of a proprietary nature can be discussed
openly
- Students can use their own equipment and begin an
actual design right in class
Costs: North America
Prices star t at $4,500 for a minimum class size of six stu-
dents.
Costs: International
- Prices vary; contact your local Xilinx sales
representative.
Included in class fees:
- A Xilinx-certified instructor
- Training materials for each student
- PC for every two students (or if you prefer, the
training labs can be done on your PCs or
workstations)
Scheduling a Class
To schedule a training class at your facility and deter mine
pricing, call the Xilinx sales office nearest you, or your local
Xilinx sales representative. On-site training classes are
popular, so the more advanced notice we have, the better
our ability to schedule your class exactly when you want it.
June 1, 1996 (Version 1.0) 13-9
Registration
Tuition
Class tuition in North America is $1,000 per student for the
three-day classes , including the synthesis-based and work-
station-based classes at Xilinx headquar ters. The distribu-
tor-sponsored, schematic-based classes are offered at a
reduced rate of $495 for customers of the sponsoring dis-
tributor. On-site classes start at $4500 per class, and vary
according to the class and the number of students. For
international locations, call the local registrar for pricing.
Most classes include a full lunch, with morning and after-
noon snacks . Let the registrar know if you ha ve any special
dietary needs when registering for the class.
Money-back Guarantee
We are so confident y ou will be satisfied with the benefits of
a Xilinx training class that we offer the following guarantee:
Full refund of the class cost if you are not
completely satisfied.
Enrollment
To enroll, call the registrar f or the location where you would
like to attend a class . Or you ma y call the Training Registrar
at Xilinx headquarters at (800) 231-3386 or contact your
local sales office. You may also register on-line at www.xil-
inx.com.
Xilinx T raining Registrar
Training Registrar
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: (800) 231-3386 x1
Fax: (408) 879-4676, attn: Customer Training Registrar
E-mail: customer.training@xilinx.com
Register on-line: www.xilinx.com
Location Tuition Benefits
North America
Xilinx Headquarters $1,000 • Can meet with applications engineers
• Classes held frequently
• All class types available
Distributor Locations $495 • Lower cost for distributor’s customers
• Local
Customer Site Starts at $4,500 • Convenience; can focus on specific issues
Update Typically $100 • One day, focus on new products
Advanced Free • For experienced, in-warranty users
International
International Locations Varies • Offered in over 21 countries
• Native language
Customer Site Varies • Convenience
• Can focus on specific issues
Technical Support
13-10 June 1, 1996 (Version 1.0)
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Product T echnical Information
Product Technical Information Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
FPGA Configuration Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Configuring Mixed FPGA Daisy Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Configuration Issues: Power-up, Volatility, Security, Battery Back-up. . . . . . . . . . . . . . . . . . 14-35
Dynamic Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41
Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45
Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47
Boundary Scan in XC4000 and XC5000 Series Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49
Product T echnical Information T able
of Contents
1
Choosing a Xilinx Product Family
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
SRAM-Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200). . . . . . . . . . . . . . . . . . . 14-3
Overview of SRAM-Based FPGA Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) . . . . . . . . . . . . . . . 14-5
Antifuse-Based FPGAs (XC8100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
EPROM- and FLASH-Based CPLDs (XC7300, XC9500). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Overview of CPLD Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Selecting the Appropriate Xilinx Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Type of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Special Features Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
XC4000 Series Technical Information
Voltage/Current Characteristics of XC4000-Family Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Additional Output Delays When Driving Capacitive Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Ground Bounce in XC4000 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Test Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Interpretation of the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Guidelines for Reducing Ground-Bounce Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Ground-Bounce vs Delay Trade-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
XC4000 and XC4000E Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
XC3000 Series Technical Information
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Configurable Logic Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Function Generator Avoids Glitches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Input/Output Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
I/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Horizontal Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Internal Bus Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Vertical Longlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Clock Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Crystal-Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
CCLK Frequency Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
CCLK Low-Time Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Battery Back-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Powerdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Configuration and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Beware of a Slow-Rising XC3000 Series RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
Product T echnical Information T able
of Contents
Product Technical Information Table of Contents
2
FPGA Configuration Guidelines
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Protection Against Data or Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Start-Up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
Selecting the Best Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
When Configuration Fails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
General Debugging Hints for all Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
General Debugging Hints for the XC2000 and XC3000 Families. . . . . . . . . . . . . . . . . . . . . . . . 14-30
General Debugging Hints for the XC4000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Additional Mode-Specific Debugging Hints for All Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Daisy Chain Debugging Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
Potential Length-Count Problem in Parallel or Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . 14-32
Miscellaneous Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
Configuring Mixed FPGA Daisy Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
Sensitivity to VCC Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
Design Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Design Security when Configuration Data is Accessible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Design Security by Hiding the Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
Battery Back-up and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
Dynamic Reconfiguration
Important Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39
Reconfiguration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
Initiating Reconfiguration in Different Xilinx Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
XC2000 and XC3000 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
XC4000 Series and XC5200 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
Metastable Recovery
Metastability Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42
Metastability Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42
Set-up and Hold Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45
Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47
Boundary Scan in XC4000 and XC5000 Series Devices
Overview of XC4000/XC5000 Boundary-Scan Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49
Deviations from the IEEE Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50
Boundary-Scan Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
The Boundary-Scan Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
The Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
Using Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54
Boundary Scan Description Language Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57
June 1, 1996 (Version 1.0) 14-3
Summary
This Application Note describes the various Xilinx product families. Differences between the families are highlighted. The
focus of the discussion is how to choose the appropriate family for a particular application.
Xilinx Families
XC2000, XC3000, XC4000, XC5000, XC6000, XC7000,
XC8000, XC9000
Demonstrates
Choosing an appropriate Xilinx family based on the
intended application
Table of Contents
SRAM-Based FPGAs
Antifuse-Based FPGAs
EPROM and FLASH-Based CPLDs
Selecting the Appropriate Xilinx Family
Introduction
Xilinx offers Field-Programmable Logic circuits, mass-pro-
duced standard integrated circuits that the user can cus-
tomize for the specific application.
Xilinx products offer the following advantages:
• High integration (less space, lower power, higher
reliability, lower cost) than solutions based on existing
standard devices like MSI and PALs.
• No non-recurring engineering charges and associated
risk, typically required for mask-progr ammed gate arra y
solutions.
• Fast design time and easy design modification,
important for early time-to-market.
• Designs can be upgraded in the field for added
functionality.
Some potential users might be confused by the wide diver-
sity of Xilinx product offerings. This application note pro-
vides a broad overview from the user’s perspective.
Xilinx offers programmable logic circuits in three distinctly
different technologies.
• SRAM-based FPGAs, the original Xilinx offering, now
encompassing the XC2000, XC3000, XC4000,
XC5200, and XC6200 series and their sub-families, lik e
the XC3000A, XC3000L, XC3100, XC3100A,
XC4000A, XC4000H, XC4000E, XC4000L, XC4000EX,
and XC4000XL.
• Antifuse-based FPGAs, the new sea-of-gates XC8100
family.
• Complex PLDs or EPLDs, XC7300, and XC9500
families.
SRAM-Based FPGAs
Xilinx SRAM-based FPGAs fall into two distinct categories.
All are reconfigurable and can be programmed in-system;
only the XC6200 family can be partially reconfigured and
offers a built-in microprocessor interface. The two catego-
ries of devices are separately described below.
SRAM-Based FPGAs (XC2000, XC3000,
XC3100, XC4000, XC5200)
These families represent an ongoing evolution of the origi-
nal Xilinx FPGA architecture, characterized by structural
flexibility and an abundance of flip-flops. Logic is imple-
mented in look-up tables , and is interconnected by a hierar-
chy of metal lines controlled by pass transistors.
Attractive systems features include on-chip bidirectional
busses and individual output 3-state and slew-rate control,
common reset for all flip-flops , and multiple global low-sk ew
clock networks.
The configuration can be loaded while the de vices are con-
nected into a system, and can be changed an unlimited
number of times by reloading the “bitstream,” the series of
bits used to program the device. Configuration must be
reloaded whenever Vcc is re-applied. Reconfiguration
takes 20 to 200 ms, during which time all outputs are inac-
tive.
Static power consumption is very low, down to microwatts
for some of the families. Dynamic power consumption is
proportional to the clock frequency, and depends on the
logic activity inside the device and on the outputs.
The description “SRAM-based” refers primarily to the stan-
dard high-volume manufacturing process, and secondarily
to the fact that configur ation data is stored in latches. Differ-
ent from typical SRAMs, these latches use low-impedance
active pull-up and pull-do wn tr ansistors . An on-chip voltage
monitor 3-states the outputs and initiates reconfiguration
when Vcc drops significantly (to 3.2 V in a 5-V system).
Choosing a Xilinx Product Family
June 1, 1996 (Version 1.0) Application Note By PETER ALFKE
Choosing a Xilinx Product Family
14-4 June 1, 1996 (Version 1.0)
These FPGAs are available in different sizes and many dif-
ferent packages. Usually each device type is available in
many package types. Any package can accommodate dif-
ferent sized devices with compatible pinouts, so the user
can migrate to a larger or smaller device without changing
the PC-board layout.
Overview of SRAM-Based FPGA Families
XC2000: Oldest, simplest, smallest, and lo west-cost FPGA
family; not recommended for new designs
• Used for simple, very cost-sensitive applications.
• Accept limited logic flexibility, 3-input look-up tables, no
clock enables, no output slew-rate control, only two
device types covering the narrow complexity range of
600 to 1500 gates.
The XC5200 and XC8100 FPGA families, or the XC7300
and XC9500 EPLD families, may often be a better alterna-
tive.
XC2000L: 3.3-V version of XC2000; not recommended for
new designs
• Used for simple, battery-operated applications.
• Accept significantly slower speed at 3.3 V, compared to
XC2000 at 5 V.
XC3000: Superseded
Don’t use this vener able f amily for ne w designs, since it has
been superseded by the improved, but fully backwards
compatible, XC3000A family.
XC3000A: Newest version of the popular XC3000 family
Five device types cover a complexity range from 1,300 to
7,500 gates, with 256 to 928 flip-flops. Logic is imple-
mented in 4-input look-up tables; two tables can be com-
bined to implement any logic function of five variables with
only one combinatorial delay of 4 or 5 ns. Flip-flop toggle
rate is over 110 MHz.
Global choice of input thresholds (1.2 V or 2.5 V), output
slew-rate control, and an on-chip crystal oscillator circuit
are attractive system features.
• Use for medium-speed, medium-complexity
applications.
• Accept lack of dedicated carry circuits, resulting in less
efficient and slower arithmetic and counters than in
XC4000E families. No on-chip RAM; data storage is
thus limited to the available 256 to 928 flip flops.
XC3000L: 3.3-V version of XC3000A
• Use for battery-operated applications.
• Accept significantly slower speed at 3.3 V, compared to
XC3000A at 5 V.
XC3100: Superseded
Don’t use this family for new designs, since it has been
superseded by the improved, but fully backwards compati-
ble XC3100A family.
XC3100A: Newest version of the popular high-speed
XC3100 family
XC3100A devices are functionally and bitstream identical
with the XC3000A, and are av ailab le in the same pac kages
with the same pinouts. The only difference is the higher
speed of the XC3100A, with a look-up table delay of 1.5 to
4 ns, and the slightly higher standby current of 8 to 14 mA.
One additional high-end family member, the XC3195A, can
implement up to 9,000 gates and 1,320 flip-flops.
• Use for high performance design with system clock
rates up to 100 MHz.
• Accept lack of dedicated carry circuits, resulting in less
efficient and possibly slower arithmetic and counters
than in XC4000E. No on-chip RAM; data storage is thus
limited to the available 256 to 1,320 flip-flops.
XC3100L: 3.3-V version of XC3100A
• Use for 3.3-V applications.
• Accept significantly slower speed at 3.3 V, compared to
XC3100A at 5 V, as well as higher quiescent power and
much higher pow erdown current than XC3000L at 3.3 V.
XC4000: Superseded
Don’t use this family for new designs, since it has been
superseded by the improved, but fully backwards compati-
ble XC4000E family.
XC4000A: Superseded
Don’t use this family for new designs, since it has been
superseded by the improved, faster, less expensive, and
pinout-compatible – but not bitstream-compatible –
XC4000E family.
XC4000E: Enhanced superset of the XC4000 family
The XC4000E family is recommended for new designs.
The ten devices in this family stretch from 2,000 to 25,000
gate complexity. The emphasis is on systems features and
speed. The function generators are more versatile than in
the XC3000-Series parts, and there is a dedicated carry
network to speed up arithmetic and counters and make
them more efficient. Most importantly, the function genera-
tors can be used as user RAM with asynchronous or syn-
chronous write addressing, even as dual-port RAMs. This
capability makes register files , shift registers and especially
FIFOs faster and much more efficient than in any other
FPGA.
Logic speed is not as fast as XC3100, but dedicated carry
logic can speed up wide arithmetic and long counters even
above XC3100 speed.
• Use for general-purpose logic and data-path logic that
can take advantage of internal busses and fast
arithmetic carry logic. Use f or on-chip distributed RAMs,
e.g. 50-MHz FIFOs up to 64 deep, 32 bits wide.
• Accept lack of crystal oscillator circuitry and lack of
Powerdown feature.
June 1, 1996 (Version 1.0) 14-5
XC4000EX: Larger version of the XC4000E family, largest
devices made by Xilinx
Extension of the XC4000E family from 28k to 125k gates,
with greatly increased routing resources, faster clocking
options and more versatile output logic.
• Use for designs beyond 20,000 gate complexity.
XC4000H: High I/O version of XC4000, not recommended
for new designs
Variations of XC4003 and XC4005, with significantly
increased number of I/Os. Internal functionality identical to
XC4003 and XC4005, but number of I/Os increased from
80 to 160 for XC4003H, from 112 to 192 for XC4005H. No
input or output flip-flops in the IOBs, b ut 24 mA sink current
and sophisticated slew-rate control that can minimize
ground bounce.
• Used for I/O-intensive applications, but also consider
XC5200 as a lower-cost alternative when internal RAM
is not required.
• Accept lack of I/O flip-flops, thus larger output delay,
larger uncertainty in input set-up time.
XC5200: Low-cost FPGA
New architecture optimized for low cost, good routability,
and the ability to lock pinout while internal logic is being
modified. Dedicated carr y structure similar to XC4000, but
no RAM. Four-input function generators avoid the XC3000
input constraints. IOBs are less rigidly coupled to the inter-
nal matrix of CLBs and interconnects, which greatly
improves the flexibility of pin-locked designs. IOBs have no
flip-flops.
The XC5200 family offers the lowest cost per gate of all Xil-
inx FPGAs, whenever RAM is not required.
Performance is similar to XC3000A, but dedicated carry
logic can speed up wide arithmetic and long counters.
• Use for medium-speed general-purpose logic, and for
data-path logic that can take advantage of internal
busses and fast arithmetic carry logic. Alternative to
XC3000A at lower cost, and with additional benefits,
such as dedicated carry for arithmetic and counters,
improv ed routing, and ability to cope with loc k ed pinout.
High I/O count. Package pinout compatible with
XC4000.
• Accept lack of internal RAM and lack of crystal
oscillator circuitry.
Partially-Reconfigurable SRAM-Based
FPGA with Bus Interface (XC6200)
This new fine-gr ained architecture is very different from the
other Xilinx families. It offers partial and very fast reconfig-
urability, suppor ted by an 8/16/32 bit wide microprocessor
bus interface. This interface can directly write to and read
from any internal cell, and can ev en treat part of the internal
configuration as user RAM.
• Use for innovative reconfigurable-processor solutions,
and for general purpose solutions where fast
(re)configuration is an advantage, or for register-
intensive , datapath-oriented, highly structured designs.
• Accept product availability starting later in 1996.
Antifuse-Based FPGAs (XC8100)
The XC8100 family uses antifuses in a sea-of-gates archi-
tecture, with progr ammable interconnects physically on top
of the relatively fine-grained logic blocks. Antifuses offer a
one-chip non-volatile solution with a very high level of
design security, i.e. protection against reverse engineering.
The XC8100 family covers a very wide range of logic den-
sities from 500 gates to 15,000 gates. The architecture
uses many relatively simple blocks, and is thus closer than
other FPGAs to the structure of traditional gate arra ys . This
architecture simplifies and speeds up logic synthesis and
design compilation.
• Use XC8100 for design flexibility, for single-chip and
secure applications, and for designs that need to take
advantage of the easy-to-use synthesis-friendly
software.
• Accept one-time-programmability, and the need to
program devices in external programming equipment.
EPROM- and FLASH-Based CPLDs
(XC7300, XC9500)
These device families are extensions of the popular PAL
architecture, implementing logic as wide AND gates, ORed
together, driving either a flip-flop or an output directly. The
simple logic structure makes these devices easy to under-
stand, and results in both fast design compilation and short
pin-to-pin delays. Wide input gating and fast system clock
rates up to 150 MHz are attractive features for state
machines and complex synchronous counters.
The XC7300 CPLDs use EPROM technology.
The new XC9500 in-system programmable family, based
on FLASH technology, eliminates the need for a separate
programmer. These new devices also offer boundar y scan
(JTAG) to simplify board testing.
Overview of CPLD Families
XC7200A: Superseded
Not recommended for new designs. Use XC7300 instead.
XC7300: EPROM-Based CPLD
Six devices cover the range from 18 to 144 macrocells in
44- to 225-pin packages.
• Use for high-speed logic, short pin-to-pin delays, for
state machines and flexible address decoding, and as
PAL replacement. Dedicated carry logic offers fast and
efficient adders, subtractors, comparators, and
counters.
Choosing a Xilinx Product Family
14-6 June 1, 1996 (Version 1.0)
• Accept higher power consumption and fewer available
flip-flops compared to SRAM-based or antifuse-based
FPGAs.
• The XC7318, XC7336/Q, and XC7354 are very
effective as PAL replacements. The XC7336Q boasts
significantly reduced power consumption.
Delays are deterministic, and compile times are very short.
XC9500: FLASH-Based CPLD
Nine devices cover the range from 36 to 576 macrocells.
The new XC9500 family provides advanced in-system pro-
gramming and test capabilities for high performance, gen-
eral purpose logic integration.
• Use XC9500 for CPLD applications requiring fast pin-
to-pin speeds.
• Accept higher power consumption and fewer available
flip-flops compared to SRAM- or antifuse-based FPGA.
Selecting the Appropriate Xilinx
Family
It is not always obvious which Xilinx family is the “right”
choice for a particular application. To make a decision, start
with the known data, the target application. Then address
the following questions:
• What type of logic is used in the application?
• What special features are required?
Type of Logic
All Xilinx devices are general-purpose. Any family can
implement any type of logic. There are , ho wever, some f ea-
tures that make certain families more appropriate than oth-
ers. The following items should be interpreted as “soft”
suggestions, not as absolute, unequivocal choices.
1. For shortest pin-to-pin delays and fastest flip- flops:
Use XC9500, XC7300, or, if fan-in is sufficient, XC3100A,
XC4000E/EX.
XC9500 and XC7300 CPLDs have a PAL-like AND/OR
structure that is inherently very fast. XC3100 has extremely
fast logic b loc ks , b ut the single-level fan-in is limited to fiv e .
XC4000E/EX hav e slo wer logic b loc ks, b ut a wider f an-in of
nine. XC4000EX FPGAs offer a very fast pin-to-pin path
using a FastClk buffer and a 2-input function generator in
the IOB.
2. For fastest state machines:
For encoded state machines, use XC9500, XC7300.
For “one-hot” state machines, use XC3100, XC4000E/EX,
XC5200.
3. For fast counters/adders/subtractors/accumulators/
comparators:
Use XC4000E/EX, XC5200 or XC7300 for wide functions.
Use XC3100A for very fast, but short or simple counters.
XC4000E/EX and XC5200 have dedicated carry-logic that
is most effective over the range of 8 to 32 bits.
XC7300 has dedicated carry within a function block, and
can implement unlimited carry look-ahead in the Universal
Interconnect Matrix.
XC3100A achieves high speed for short word-length and
simple operations (such as non-loadable counters) through
its extremely fast logic blocks.
4. For I/O-intensive applications with a high ratio of I/O
to gates:
Use XC5200.
5. For shortest design compilation time:
Use XC9500, XC6200 or XC8100.
XC9500 achieves fast compilation through the simplicity of
its PAL-like architecture.
XC8100 and XC6200 achiev e f ast compilation through their
ASIC-like small granularity, which requires no logic parti-
tioning effort.
6. For lowest cost per gate, when on-chip RAM is not
required:
Use XC5200, XC8100, XC3000A (XC2000 for small
devices in high volume).
7. For pinout compatibility within and between families:
Use XC4000E/EX, XC5200, XC8100.
These three families are carefully designed to fit the same
pinout in any given available package. This allows easy
migration to different device sizes or families in the same
package. The user can add logic or streamline the design
or even use a less costly or faster family without any need
to change the existing PC-board layout.
8. For Digital Signal Processing (multiply-accumulate)
applications:
Use XC4000E/EX.
The look-up-table architecture and the dedicated carry
structure are very efficient for distributed arithmetic, a fast
and effective way to implement fixed-point multiplication in
digital filters.
Special Features Required
The sixteen items below describe specific features and
characteristics available only in the listed families. These
are, therefore, “hard” selection criteria.
June 1, 1996 (Version 1.0) 14-7
9. For on-chip RAM:
Use XC4000E, XC4000EX, or XC6200.
XC4000E/EX has many 16x1 or 32x1 RAMs with synchro-
nous or asynchronous write and dual-port capability.
XC6200 can implement an arbitrary portion of the configu-
ration-memory space as user RAM.
10. For on-chip (bidirectional) bussing:
Use XC3000A, XC3100A, XC4000E, XC4000EX, XC5200,
XC7300, XC9500, XC8100 (i.e., use any Xilinx family
except XC2000).
XC3000A, XC3100A, XC4000, and XC5200 families have
horizontal Longlines that can be driven by internal 3-state
drivers.
XC9500 and XC7300 devices implement busses indirectly
using the wired-AND capability in the switch matrix.
XC8100 uses internal 3-state dr ivers on arbitrarily defined
interconnects.
11. For on-chip crystal oscillator circuitry:
Use XC2000/L, XC3000A/L, XC3100A/L.
The on-chip circuit is just a dedicated single-stage inv erting
amplifier that can be configured between two dedicated
pins. It is not recommended for designs requiring very low
power consumption or crystal frequencies below 1 MHz.
12. For very fast or partial reconfiguration, and for a
dedicated microprocessor interface:
Use XC6200.
All other SRAM-based families must be completely recon-
figured.
13. For non-volatile single-chip solutions:
Use XC9500, XC7300, XC8100 or any HardWire device.
The SRAM-based devices require an e xternal configuration
source, which may be contained in the microprocessor’s
memory. XC3000A and XC3000L de vices can be used with
a battery-backed-up supply, thus eliminating the need for
external configuration storage.
14. For lo west possible static po wer consumption at 5V:
Use XC2000, XC3000A, XC8100 and, to a lesser extent,
XC5200, XC4000E, XC4000EX.
For Icc down to a few microamps, use XC2000/L or
XC3000A/L in powerdown. The other families consume a
few milliamps.
Configurations for CMOS input thresholds on all inputs
reduce supply current significantly.
15. For avoiding pin-locking problems with routing-
intensive designs:
Use XC9500, XC7300, XC4000EX, XC5200, XC8100.
XC9500 and XC7300 have special architectural features to
enable pin locking.
XC4000EX and XC5200 provide additional routing chan-
nels, called VersaRing, between the core logic and the I/O.
XC8100 has very generous routing resources that elimi-
nate most pin-locking problems.
16. For Boundary-Scan support:
Use XC4000E, XC4000EX, XC5200, XC8100, XC9500.
17. For rail-to-rail output voltage swing at 5 V Vcc:
Use XC2000, XC3000A, XC3100A, XC4000H, XC4000E,
XC4000EX, XC5200, XC6200, XC8100.
(In XC4000H/E/EX, rail-to-rail is a user-option.)
XC4000, XC7300, and XC9500 have a “totem-pole” output
structure with lower Voh.
XC4000E/EX can be configured with a global choice of
either totem-pole or rail-to-rail outputs.
XC4000H has this option per individual pin.
18. For 3.3-V operation:
Use XC2000L, XC3000L, XC4000L, XC4000XL, XC8100.
19. For 5-V operation Interfacing with 3.3-V devices:
Use XC9500, XC7300 or XC4000E/EX.
Any XC4000E/EX “totem-pole” output drives 3.3-V inputs
safely, and the TTL-like input threshold can be driven from
3.3-V logic.
20. For In-system programmability:
Use all Xilinx families except XC7300 and XC8100.
21. For PCl compatibility:
Use XC4000E/EX and XC9500.
Target and Initiator designs are av ailable for the XC4000E.
XC3100 and XC7300 can implement target-only interfaces .
22. For Hi-Rel, military, or mil temperature-range
applications:
Use XC2018, XC3000, XC3100A, XC4003A, XC4005,
XC4010, XC4013.
23. For battery-operated applications requiring low
stand-by current:
Use XC2000/L, XC3000A/L, XC4000E/EX, XC5200,
XC6200, XC8100.
Choosing a Xilinx Product Family
14-8 June 1, 1996 (Version 1.0)
XC2000L and XC3000L have inherently very low static
power consumption.
XC2000 and XC3000A can use powerdown to ignore all
input activity and tolerate Vcc down to 2.3 V, while maintain-
ing configuration.
XC4000E/EX and XC8100 must be configured for CMOS
input thresholds, and must shut do wn clock and logic activ-
ities externally.
24. For best protection against Illegal copying of a
design (design security):
Use XC8100, XC7300, XC9500 with security bit activated.
Use XC2000, XC2000L, XC3000A, XC3000L with power-
down battery-backed-up configuration.
Further Information
For further information on any of the Xilinx products dis-
cussed in this application note, see the Xilinx WEBLINX at
http://www.xilinx.com, or call your local sales office.
Table 1: Selecting a Xilinx Family
XC3000 XC3100 XC4000 XC XC XC XC XC
Feature A L A L E L EX XL 5200 6200 8100 7300 9500
1. Shortest pin-to-pin X X X X X
2. Fastest state machines XXXX XX
3. Fastest arithmetic counters X X X X
4. High I/O to gate ratio X
5. Fastest compilation XXXX
6. Lowest cost, no RAM X X X
7. Footprint compatible families XXXXX X
8. DSP (multiply/accumulate) XXXX
9. RAM XXXX X
10. Bidirectional busses XXXXXXXXX XXX
11. Crystal oscillator XXXX
12. Fast/partial configuration X
13. Non-volatile/single chip XXX
14. Low power @ 5 V X XXXX
15. Tolerates pin-locking X X X X X X
16. Boundary scan XXXXX X X
17. Full-swing 5 V output X X option option X X X
18. 3.3 V operation XXXX X
19. 5 V out drives 3.3 V option option X X
20. In-system programmable XXXXXXXXXX X
21. PCI-compatible X X X X X
22. Hi-rel, mil, mil-temp X X X
23. Low standby current X X XXXXXXX
24. Design security X X X X X
June 1, 1996 (Version 1.0) 14-9
Summary
This Application Note contains additional information that may be of use when designing with XC4000 Series devices. This
information supplements the product descriptions and specifications, and is provided for guidance only.
Xilinx Family
XC4000/XC4000A/XC4000H/XC4000E/XC4000L
Introduction
This application note describes the electrical characteris-
tics of the output drivers, their static output characteristics
or I/V curves, the additional delay caused by capacitive
loading, and the ground bounce created when many out-
puts switch simultaneously.
Voltage/Current Characteristics of
XC4000-Family Outputs
Figures 1 and 2 show the output source and sink currents,
both drawn as absolute values. Note that the XC4000E/EX
families offer a configuration choice between an n-channel
only, totem-pole like output structure that pulls a High output
to a voltage level that is one threshold drop lower than VCC,
and a conv entional complementary output with a p-channel
transistor pulling to the positive supply rail. When driving
inputs that have a 1.4-V threshold, the lower VOH of the
totem-pole (“TTL”) output offers faster speed and more sym-
metrical switching delays.
These curves represent typical devices. Measurements
were taken at VCC= 5 V, T = 25°C. These characteristics
vary by manufacturing lot, and will be affected by future
changes in minimum device geometries. These character-
istics are not production-tested as part of the normal device
test procedure; they can, therefore, not be guaranteed.
Although these measurements show that the output sink
and source capability far exceeds the guaranteed data
sheet limits, continuous high-current operation beyond the
data sheet limits can cause metal migration of the on-chip
metal traces, permanently damaging the device. Output
currents in excess of the data-sheet limits are, therefore,
not recommended for continuous operation. These output
characteristics can, howe v er, be used to calculate or model
output transient behavior, especially when driving transmis-
sion lines or large capacitive loads.
XC4000 Series
Technical Information
June 1, 1996 (Version 1.0) Application Note
200
180
160
140
120
100
80
60
40
20
012345
Volts
mA
X5291
I
OL
I
OH
CMOS
TTL
Figure 1: Output Voltage/Current Characteristics
for XC4000E
200
180
160
140
120
100
80
60
40
20
012345
Volts
mA
X5292
I
OH
I
OL
Figure 2: Output Voltage/Current Characteristics
for XC4000L
XC4000 Series Technical Information
14-10 June 1, 1996 (Version 1.0)
Additional Output Delays When
Driving Capacitive Load
Xilinx Product Specifications in chapter 4 give guaranteed
worst-case output delays with a 50-pF load.
The values below are based on actual measurements on a
small number of mid-93 production XC4005-5, all in PQ208
packages , measured at room temperature and VCC = 5.5 V.
Listed is the additional output delay, measured crossing 1.5
V, relative to the delays specified in this Data Book.
These parameters are not part of the normal production
test flow, and can, therefore, not be guaranteed.
Table 1: Increase in Output Delay When Driving Light
Capacitive Loads (<150 pF)
Note: *Zero by definition
Table 2: Increase in Output Delay When Driving Heavy
Capacitive Loads (>150 pF)
Example:
∆T High-to-Low for XC4005-5 with Fast-mode output dr iv-
ing 250 pF:
1.2 ns (from Table 1) plus (250-100) pF • 1.5 ns/100 pF
= 1.2 ns + 2.25 ns = 3.45 ns
Total propagation delay, clock to pad:
TOKPOF + 3.45 ns = 7.0 ns + 3.45 ns = 10.45 ns
Ground Bounce in XC4000 Devices
Ground-bounce is a problem with high-speed digital ICs,
when multiple outputs change state simultaneously caus-
ing undesired transient behavior on an output, or in the
internal logic. This is also referred to as the Simultaneous
Switching Output (SSO) problem. Ground bounce is prima-
rily due to current changes in the combined inductance of
ground pins, bond wires, and ground metallization. The IC-
internal ground level deviates from the external system
ground level for a short duration (a few nanoseconds) after
multiple outputs change state simultaneously. Ground
bounce affects outputs that are supposed to be stab le Lo w,
and it also affects all inputs since they interpret the incom-
ing level by referencing it to the internal ground. If the
ground bounce amplitude exceeds the actual instanta-
neous noise margin, then a non-changing input will be
interpreted as a shor t pulse with a polar ity opposite to the
ground bounce.
VCC bounce is not as important as ground bounce,
because it is of lower magnitude due to the weaker pull-up
transistors. Also, the noise immunity in the High state is
usually better than in the Low state, and input le v els are ref-
erenced to ground, not VCC. All this is the result of our
industry’s TTL heritage.
Test Method
Data was taken on XC4005-5, devices in the PQ208 pack-
age, soldered to the Xilinx Ground Bounce Test Board. Pin
82, two pins aw ay from the nearest ground pin, was config-
ured as a permanently Low output driver, effectively moni-
toring the internal ground level. The simultaneously
switching outputs were on pins 80 and 83, for two outputs
switching; additionally, pins 80 and 86 were used for four
outputs switching. The closest ground pins are 79 and 90.
Four ground-bounce parameters were measured at room
temperature, with Vcc set at 5.5 V as shown in Figure 3.
•V
OLP-HLPeak ground noise when switching High-to-Low
•V
OLV-HLValle y g round noise when switching High-to-Low
•V
OLP-LHPeak ground noise switching Low-to-High
•V
OLV-LHValley ground noise switching Low-to-High
All four parameters can affect system reliability.
High-to-Low Low-to-High
Slew
Mode 10 50 100 10 50 100 pF
XC4000 Slow -1.6 0* 1.4 -1.4 0* 1.4 ns
Fast -1.6 0* 1.2 -1.2 0* 1.1 ns
Slew Mode High-to-
Low Low-to-
High
XC4000 Slow 1.7 1.2 ns/100 pF
Fast 1.5 1.2 ns/100 pF
Switching
Outputs
Non-Switching
Active-Low Output
VOH
VOL VOL
VOH
VOL
VOLV-LH
VOLP-LH
VOLP-HL
VOLV-HL
X5299
Figure 3: Ground Bounce
June 1, 1996 (Version 1.0) 14-11
The two positive peak values can cause problems with a
signal leaving the ground bounce chip , driving another chip .
The positive ground bounce voltage is added to the VOL,
and may exceed the receiving input’s noise margin. A con-
tinuously logic Low input may thus be interpreted as a
short-duration High pulse.
The two negative valley parameters can cause problems
with a signal arriving at the ground-bounce chip, reducing
the Low-level noise immunity. The incoming voltage may
not be Low enough, and ma y, therefore , be interpreted as a
short-duration High input pulse.
Table 3: Ground Bounce, 16 Outputs Switching, Each
With 50 or 150 pF Load, VCC = 5.5 V
Interpretation of the Results
Ground bounce is a linear phenomenon. When multiple out-
puts switch, the total ground bounce is the sum of the
ground-bounce values caused by individual outputs switch-
ing. Since the actual switching of multiple outputs is usually
not quite simultaneous, small timing diff erences between the
switching outputs, caused by routing delays, can indirectly
affect the amplitude . With low capacitiv e loading, < 50 pF, the
peaks and valleys might even partially cancel each other.
With larger capacitive loads, the tendency is for valleys to
combine with valleys and peaks to combine with peaks.
In most devices tested, the load capacitance does not
directly affect the ground-bounce amplitude, but it does
affect the duration of the ground-bounce signals.
On the fastest outputs, minimal load capacitance created a
ground-bounce resonant frequency of 340 MHz, with a
half-cycle time of 1.5 ns. Such a signal exceeds 90% of its
peak amplitude for about 0.4 ns.
With a 50 pF load on the switching outputs, the ground
bounce resonant frequency is 90 MHz, with a half-cycle
time of 5 ns, staying 1.7 ns above 90% of peak amplitude.
With a 150 pF load on the switching outputs, the ground
bounce resonant frequency is 40 to 60 MHz, with a half-
cycle time of 8 to 12 ns, staying 3 ns above 90% of peak
amplitude.
The main problem with large load capacitances is not an
increase in amplitude, but rather an increase in duration of
the ground-bounce signal. The amplitude is mainly aff ected
by the number of outputs switching simultaneously, and by
the slew-rate mode of these outputs. Switching outputs
closer to the monitoring output also cause larger peaks and
valleys than outputs further away.
Guidelines for Reducing Ground-Bounce
Effects
• Minimize the impedance of the system ground
distribution network and its connection to the IC pins.
PQFPs are best suited, PGAs are worst, and PLCCs are
in-between.
• Use PC-boards with ground- and VCC-planes, connected
directly to the ICs’ supply pins. Place decoupling
capacitors very close to these ground and VCC pins.
• Keep the g round plane as undisturbed as possible. A row
of vias can easily cause a dynamic ground-v oltage drop.
• Keep the clock inputs physically a w ay from the outputs
that create ground bounce, and connect clocks to input
pins that are close to a ground pin. Make sure that all
clock and asynchronous inputs ha ve ample noise
margin, especially in the Low state.
• If possible, av oid sim ultaneous switching by staggering
output delays, e.g. through additional local routing of
signals or clocks .
• Spread simultaneously switching outputs around the IC
periphery. For a 16-bit bus, use two outputs each on
either side of four g round pins.
Ground-Bounce vs Delay Trade-Off
After the external sources of ground bounce have been
reduced or eliminated. the designer can trade reduced
ground bounce for additional delay by selecting between
families and slew-rate options . Figure 4 shows the trade-off
for 16 outputs switching simultaneously High-to-Low.
Load Slew
Rate High-to-Low Low-to-High Unit
VOLP VOLV VOLP VOLV
16 x 50 pF Slow 670 480 240 240 mV
Fast 1,170 710 480 660 mV
16 x 150 pF Slow 740 330 210 280 mV
Fast 1,180 420 350 710 mV
2Additional
Delay (ns)
0
200
X5981
400
600
800
1000
1200
1400
1600
1800
3 4 5 6
FAST SLEW RATE
SLOW SLEW RATE
16 x 50 pF 16 x 150 pF
16 x 50 pF
Ground-Bounce Voltage (mV)
16 x 150 pF
Figure 4: Ground-Bounce vs. Delay Trade-off for 16
Outputs Switching 50 and 150 pF Each
XC4000 Series Technical Information
14-12 June 1, 1996 (Version 1.0)
XC4000 and XC4000E Power
Consumption
Below are the dynamic power consumption values for typi-
cal design elements in XC4000 and XC4000E.
The differences between XC4000 and XC4000E are too
small to be statistically relevant:
Global clocks in XC4000E are 3% higher, and Longlines
and unloaded outputs in XC4000E are 5 to 10% lower than
in XC4000.
Power consumption is given at nominal 5.0-V supply and
25˚C.
Power is proportional to the square of the supply voltage,
but is almost constant over temperature changes. Power is
given as “mW per million transitions per second”, since the
more commonly used “MHz” can be ambiguous. When a
10-MHz clock toggles a flip-flop, the clock line obviously
makes 20 MTps, the flip-flop output only 10 MTps.
The first six elements are device-siz e independent, i.e. they
are applicable to all XC4000 or XC4000E de vices operating
at 5-V Vcc.
• One CLB flip-flop driving nothing but a neighboring flip-
flop in the same or adjacent CLB (a typical shift register
design):
0.1 mW per million transitions per second =
0.1 mW/MTps
• One CLB flip-flop driving its neighbor plus 9 lines of
interconnect:
0.2 mW per million transitions per second =
0.2 mW/MTps
• One unloaded or unbonded TTL-level output:
0.25 mW per million transitions per second =
0.25 mW/MTps
• 50 pF on a TTL-level output: add 0.5 mW/MTps = 1.0
mW/MHz
• One unloaded or unbonded XC4000E CMOS-level
output:
0.31 mW per million transitions per second =
0.31 mW/MTps
• 50 pF on a CMOS-level output: add 0.625 mW/MTps =
1.25 mW/MHz
The following elements are obviously device-size depen-
dent:
• One Global Clock driving all CLB flip-flops, but no flip-
flop changing:
in XC4005: 4 mW/MTps = 8 mW/MHz
in XC4010: 8 mW/MTps = 16 mW/MHz
in XC4013: 12 mW/MTps = 24 mW/MHz
in XC4020: 16 mW/MTps = 32 mW/MHz
in XC4025: 20 mW/MTps = 40 mW/MHz
• One full-length horizontal or vertical Longline with one
driving CLB source and one driven CLB load:
in XC4005: 0.10 mW/MHz = 0.20 mW/MHz
in XC4010: 0.15 mW/MTps = 0.30 mW/MHz
in XC4013: 0.18 mW/MTps = 0.36 mW/MHz
in XC4020: 0.20 mW/MTps = 0.40 mW/MHz
in XC4025: 0.24 mW/MTps = 0.48 mW/MHz
These numbers do not account for the 10 mA of static
power consumption when all device inputs are configured
in TTL mode, which is always the default mode, and in
XC4000 is actually the only user-accessible mode.
These numbers assume short rise and fall times on all
inputs, avoiding the cross-current when both the n-channel
pull-down and the p-channel pull-up transistor in the input
buffer might conduct simultaneously.
Tutorial Comments:
In its pure form, a CMOS output driving a capacitive load
has a power consumption that is independent of drive
impedance or rise and fall time. For a full-swing signal, the
power consumed when charging the capacitor is C x V2 x f
where f is the frequency of charge operations. In each
charge operation, half the total energy consumed ends up
on the capacitor, and the other half of the energy is dissi-
pated in the current-limiting resistor or transistor, whatever
its value may be.
The subsequent discharge cycle does not take any new
energy from the power supply, but dissipates in the current-
limiting resistor/transistor all the energy that was formerly
stored in the capacitor.
It is assumed here that the frequency is low enough so that
the capacitors are completely charged and discharged in
each half-cycle.
June 1, 1996 (Version 1.0) 14-13
Summary
This Application Note contains additional information that may be of use when designing with the XC3000 series of FPGA
devices. This information supplements the data sheets, and is provided for guidance only.
Xilinx Family
XC3000/XC3000A/XC3000L/XC3100/XC3100A/XC3100L
Contents
CLBs
Function Generators
Flip-flops
Longline Access
IOBs
Inputs
Outputs
Routing
Horizontal Longlines
Bus contention
Vertical Longlines
Vertical Longlines
Clock Buffers
Vertical Longlines
Clock Buffers
Power Dissipation
Crystal Oscillator
CCLK Frequency Stability and Low-time restriction
Powerdown and Battery-Backup
Configuration and Start-Up
Reset
Beware of slow rise-time
Introduction
The background information provided in this Application
Note supplements the XC3000, XC3000A, XC3000L,
XC3100A and XC3100L data sheets. It covers a wide
range of topics, including a n umber of electrical parameters
not specified in the data sheets, and unless otherwise
noted, applies to all six families. These additional parame-
ters are sufficiently accurate for most design purposes;
unlike the parameters specified in the data sheets, how-
ever, they are not worst-case values over temperature and
voltage, and are not 100% production tested. They can,
therefore, not be guaranteed.
Configurable Logic Blocks
The XC3000/XC3100 CLB, shown in Figure 1, contains a
combinatorial function generator and two D-type flip-flops.
Two output pins ma y be driven b y either the function gener-
ators or the flip-flops. The flip-flop outputs may be routed
directly back to the function generator inputs without going
outside of the CLB.
The function generator consists of two 4-input look-up
tables that may be used separately or combined into a sin-
gle function. Figure 2 shows the three available options.
Since the CLB only has five inputs to the function genera-
tor, inputs must be shared between the two look-up tables.
In the FG mode, the function generator pro vides an y two 4-
input functions of A, B and C plus D or E; the choice
between D and E is made separately for each function. In
the F mode, all five inputs are combined into a single 5-
input function of A, B, C, D and E. Any 5-input function ma y
be emulated. The FGM mode is a superset of the F mode,
where two 4-input functions of A, B, C and D are multi-
plexed together according to the fifth variable, E.
In all modes, either of the B and C inputs ma y be selectively
replaced by QX and QY, the flip-flop outputs. In the FG
mode, this selection is made separately for the two look-up
tables, extending the functionality to any two functions of
four variables chosen from seven, provided two of the vari-
ables are stored in the flip-flops . This is particularly useful in
state-machine-like applications.
In the F mode, the function generators implement a single
function of five v ariables that may be chosen from se v en, as
described above. The selection of QX and QY is con-
strained to be the same for both look-up tables. The FGM
mode differs from the F mode in that QX and QY may be
selected separately f or the tw o look-up tables, as in the FG
mode. This added flexibility permits the emulation of
selected functions that can include all seven possible
inputs.
XC3000 Series
Technical Information
June 1, 1996 (Version 1.0) Application Note By Peter Alfke and Bernie New
XC3000 Series Technical Information
14-14 June 1, 1996 (Version 1.0)
Q
Combinatorial
Function
Logic
Variables
D
RD
G
F
QX
QY
QD
RD
Enable Clock
Clock
Reset
Direct
1 (Enable)
A
B
C
D
E
DI
EC
K
RD
Y
X
0 (Inhibit)
(Global Reset)
CLB Outputs
Data In 0
1
0
1
MUX
MUX
G
QY
QX
F
DIN
F
G
DIN
F
G
X3217
Figure 1: Configurable Logic
Block (CLB)
Function Generator Avoids Glitches
The combinatorial logic in all CLBs is implemented as a
function generator in the form of a multiplexer, built out
of transf er gates. The logic inputs form the select inputs
to this multiplexer, while the configuration bits drive the
data inputs to the multiplexer.
The Xilinx circuit designers were v ery careful to achieve
a balanced design with similar (almost equal) propaga-
tion delays from the various select inputs to the data
output.
The delay from the data inputs to the output is, of
course, immaterial, since the data inputs do not change
dynamically. They are only affected by configuration.
This balanced design minimizes the duration of possi-
ble decoding glitches when more than one select input
changes. Note that there can nev er be a decoding glitch
when only one select input changes. Even a non-over-
lapping decoder cannot generate a glitch problem,
since the node capacitance will retain the previous logic
level until the new transfer gate is activated about a
nanosecond later.
When more than one input changes “simultaneously,”
the user should analyze the logic output for any possi-
ble intermediate code. If any such code permutation
produces a different result, the user must assume that
such a glitch might occur and must make the system
design immune to it. The glitch might be only a few
nanoseconds long, but that is long enough to upset an
asynchronous design.
If none of the possible address sequences produces a
different result, the user can be sure that there will be
no glitch.
The designer of synchronous systems generally
doesn't worry about such glitches, since synchronous
designs are fundamentally immune to glitches on all
signals except clocks or direct SET/RESET inputs.
A
BQX
QY
E
D
C
F
A
BQX
QY
E
D
C
G
A
BQX
QY
E
D
C
A
BQX
QY
D
C
A
BQX
QY
E
D
C
F
G
F
G
X3218
2a
2b
2c
M
U
X
FGM
Mode
FG
Mode
F
Mode
Any Function
of Up To 4
Variables
Any Function
of Up To 4
Variables
Any Function
of 5 Variables
Any Function
of Up To 4
Variables
Any Function
of Up To 4
Variables
Figure 2: CLB Logic Options
June 1, 1996 (Version 1.0) 14-15
The automatic logic-par titioning software in the XACT
step
development system only uses the FG and F modes. How-
ev er , all three modes are a v ailable with manual partitioning,
which may be performed in the schematic. If FG or F
modes are required, it is simply a matter of including in the
schematic CLBMAP symbols that define the inputs and
outputs of the CLB.
The FGM mode is only slightly more complicated. Again, a
CLBMAP must be used, with the signal that multiplexes
between the two 4-input functions locked onto the E pin.
The CLB will be configured in the FGM mode if the logic is
drawn such that the gates forming the multiplexer are
shown explicitly with no additional logic merged into them.
The two D-type flip-flops share a common clock, a common
clock enable, and a common asynchronous reset signal.
An asynchronous preset can be achieved using the asyn-
chronous reset if data is stored in active-low form; the Low
created by reset corresponds to the bit being asserted. The
flip-flops cannot be used as latches.
If input data to a CLB flip-flop is derived directly from an
input pad, without an intervening flip-flop, the data-pad-to-
clock-pad hold time will typically be non-z ero. This hold time
is equal the delay from the clock pad to the CLB, but may
be reduced according to the 70% rule, described later in
the IOB Input section of this Application Note. Under this
rule, the hold time is reduced by 70% of the delay from the
data pad to the CLB, excluding the CLB set-up time. The
minimum hold time is zero, even when applying the 70%
rule results in a negative number.
The CLB pins to which Longlines have direct access are
shown in Table 1. Note that the clock enable pin (EC) and
the TBUF control pin are both driven from to the same ver-
tical Long Line. Consequently, EC cannot easily be used to
enable a register that must be 3-stated onto a bus. Simi-
larly, EC cannot easily be used in a register that uses the
Reset Direct pin (RD).
Table 1: Longline to CLB Direct Access
Input/Output Blocks
The XC3000/XC3100 IOB, sho wn in Figure 3, includes a 3-
state output driver that ma y be driven directly or registered.
The polarities of both the output data and the 3-state con-
trol are determined by configuration bits. Each output buff er
may be configured to have either a fast or a slow slew rate.
The IOB input may also be direct or registered. Additionally,
the input flip-flop may be configured as a latch. When an
IOB is used exclusively as an input, an optional pull-up
resistor is available, the value of which is 40-150 kΩ. This
resistor cannot be used when the IOB is configured as an
output or as a bidirectional pin.
Unused IOBs should be left unconfigured. They default to
inputs pulled High with the internal resistor.
Inputs
All inputs have limited hysteresis, typically in excess of 200
mV for TTL input thresholds and in excess of 100 mV for
CMOS thresholds. Exceptions to this are the PWRDWN
pin, and the XTL2 pin when it is configured as the crystal
oscillator input.
Experiments show that the input rise and fall times should
not exceed 250 ns. This value was established through a
worst-case test using internal ring oscillators to drive all I/O
pins except two, thus generating a maximum of on-chip
noise. One of the remaining I/O pins was configured as an
input, and tested for single-edge response; the other I/O
was used as an output to monitor the response.
These test conditions are, perhaps, overly demanding,
although it was assumed that the PC board had negligible
ground noise and good power-supply decoupling. While
conservative, the resulting specification is, in most
instances, easily satisfied.
IOB input flip-flops are guaranteed to operate correctly
without data hold times (with respect to the device clock-
input pad) provided that the dedicated CMOS clock input
pad and the GCLK buffer are used. The use of a TTL clock
or a different clock pad will result in a data-hold-time
requirement. The length of this hold time is equal to the
delay from the actual clock pad to the GCLK buffer minus
the delay from the dedicated CMOS cloc k pad to the GCLK
buffer.
To ensure that the input flip-flop has a zero hold time, delay
is incorporated in the D input of the flip-flop, causing it to
hav e a relatively long set-up time. How ever , the set-up time
specified in the data sheet is with respect to the clock
reaching the IOB. Since there is an unavoidable delay
between the clock pad and the IOB, the input-pad-to-cloc k-
pad set-up time is actually less than the data sheet number .
CLB TBUF
Longline A B C D E K EC RD T
Left Most Vertical
(GCLK) X
Left Middle Vertical XXXX
Right Middle Vertical XX
Right Most Vertical
(ACLK) X
Upper Horizontal X
Lower Horizontal XX
XC3000 Series Technical Information
14-16 June 1, 1996 (Version 1.0)
Par t of the clock delay can be subtracted from the internal
set-up time. Ideally, all of the clock delay could be sub-
tracted, but it is possible for the clock delay to be less than
its maximum while the internal set-up time is at its maxi-
mum value. Consequently, it is recommended that, in a
worst-case design, only 70% of the clock delay is sub-
tracted.
The clock delay can only be less than 70% of its maximum
if the internal set-up time requirement is also less than its
maximum. In this case, the pad-to-pad set-up time actually
required will be less than that calculated.
For example, in the XC3000-125, the input set-up time with
respect to the clock reaching the IOB is 16 ns. If the delay
from the clock pad to the IOB is 6 ns , then 70% of this delay,
4.2 ns, can be subtracted to arrive at a maximum pad-to-
pad set-up time of ~12 ns.
The 70% rule must be applied whenever one delay is sub-
tracted from another. However, it is recommended that
delay compensation only be used routinely in connection
with input hold times.
Delay compensation in asynchronous
circuits is specifically not recommended.
In any case, the
compensated delay must not become negative. If 70% of
the compensating delay is greater than the delay from
which it is deducted, the resulting delay is zero.
The 70% rule in no way defines the absolute minimum val-
ues delays that might be encountered from chip to chip,
and with temperature and power-supply variations.
It sim-
ply indicates the relative variations that might be found
within a specific chip ov er the range of operating conditions.
Typically, all delays will be less than their maximum, with
some delays being disproportionately faster than others.
The 70% rule describes the spread in the scaling factors;
the delay that decreases the most will be no less than 70%
of what it would have been if it had scaled in proportion to
the delay that decreased the least. In particular, in a worst-
case design where it is assumed that any delay might not
hav e scaled at all, and remains at its maximum v alue , other
delays will be no less than 70% of their maximum.
Outputs
All XC3000/XC3100 FPGA outputs are true CMOS with n-
channel transistors pulling down and p-channel transistors
pulling up. Unloaded, these outputs pull rail-to-rail. Some
additional ac characteristics of the output are listed in
Table 2. Figure 4 and Figure 5 show output current/voltage
curves for typical XC3000 and XC3100 devices.
Output-short-circuit-current values are given only to indi-
cate the capability to charge and discharge capacitive
Flip-
Flop
QD
R
Slew
Rate Passive
Pull Up
Output
Select
3-State
Invert
Out
Invert
Flip-
Flop
or
Latch
DQ
R
Registered In
Direct In
Out
3-State
(OUTPUT ENABLE)
TTL or
CMOS
Input
Threshold
Output
Buffer
(Global Reset)
CK1
I/O Pad
V
Program-Controlled Memory Cells
Programmable Interconnection Point or PIP
=
IKOK
Q
I
O
T
Program
Controlled
Multiplexer
CK2
CC
X3216
Figure 3: Input/Output Block (IOB)
June 1, 1996 (Version 1.0) 14-17
loads. In accordance with common industry practice for
other logic devices, only one output at a time may be shor t
circuited, and the duration of this short circuit to VCC or
ground ma y not e xceed one second. Xilinx does not recom-
mend a continuous output or clamp current in excess of 20
mA on any one output pin. The data sheet guarantees the
outputs for no more than 4 mA at 320 mV to a void prob lems
when many outputs are sinking current simultaneously.
The active-High 3-state control (T) is the same as an
active-Low output enable (OE). In other words, a High on
the T-pin of an OBUFZ places the output in a high imped-
ance state, and a Low enables the output. The same nam-
ing convention is used for TBUFs within the FPGA device.
I/O Clocks
Internally , up to eight distinct I/O cloc ks can be used, two on
each of the four edges of the die. While the IOB does not
provide programmable clock polarity, the two clock lines
serving an IOB can be used for true and inverted clock, and
the appropriate polarity connected to the IOB. This does,
however, limit all IOBs on that edge of the die to using only
the two edges of the one clock.
Table 2: Additional AC Output Characteristics
* Fast and Slow refer to the output programming option.
IOB latches hav e activ e-Low Latch Enab les; they are trans-
parent when the clock input is Lo w and are closed when it is
High. The latch captures data on what would otherwise be
the active clock edge, and is transparent in the half clock
period before the active clock edge.
Routing
Horizontal Longlines
As shown in Table 3, there are two horizontal Longlines
(HLLs) per row of CLBs. Each HLL is dr iven by one TBUF
for each column of CLBs , plus an additional TBUF at the left
end of the Longline. This additional TBUF is convenient for
driving IOB data onto the Longline. In general, the routing
resources to the T and I pins of TBUFs are somewhat lim-
ited.
Table 3: Number of Horizontal Longlines
Optionally, HLLs can be pulled up at either end, or at both
ends. The value of each pull-up resistor is 3-10 kΩ.
In addition, HLLs are permanently driven by low-powered
latches that are easily overridden by active outputs or pull-
up resistors. These latches maintain the logic levels on
HLLs that are not pulled up and temporarily are not driven.
The logic level maintained is the last level actively driven
onto the line.
When using 3-state HLLs for multiplexing, the use of fewer
than four TBUFs can waste resources. Multiplexers with
four or fewer inputs can be implemented more efficiently
using CLBs.
Internal Bus Contention
XC3000 and XC4000 Series devices have internal 3-state
bus drivers (TBUFs). As in any other bus design, such bus
drivers must be enabled carefully in order to avoid, or at
least minimize, bus contention. (Bus contention means that
one driver tries to drive the bus High while a second driver
tries to drive it Low).
Since the potential overlap of the enable signals is lay-out
dependent, bus contention is the responsibility of the FPGA
user. We can only supply the following information:
While two internal buff ers drive conflicting data, the y create
a current path of typically 6 mA. This current is tolerable,
but should not last indefinitely, since it exceeds our (conser-
vative) current density rules. A continuous contention
AC Parameters Fast* Slow*
Unloaded Output Slew Rate 2.8 V/ns 0.5 V/ns
Unloaded Transition Time 1.45 ns 7.9 ns
Additional rise time for 812 pF 100 ns 100 ns
normalized 0.12 ns/pF 0.12 ns/pF
Additional fall time for 812 pF 50 ns 64 ns
normalized 0.06 ns/pF 0.08 ns/pF
Figure 4: Output Current/Voltage Characteristics for
XC3000, XC3000A, XC3100 and XC3100A Devices
200
180
160
140
120
100
80
60
40
20
012345
Volts
mA
X5294
IOL
IOH
Part
Name Rows x
Columns CLBs Horizontal
Longlines TBUFs
per HLL
XC3020 8 x 8 64 16 9
XC3030 10 x 10 100 20 11
XC3042 12 x 12 144 24 13
XC3064 16 x 14 224 32 15
XC3090 20 x 16 320 40 17
XC3195 22 x 22 484 44 23
XC3000 Series Technical Information
14-18 June 1, 1996 (Version 1.0)
could, after thousands of hours, lead to metal migration
problems.
In a typical system, 10 ns of internal bus contention at 5
MHz would just result in a slight increase in Icc.
16 bits x 6 mA x 10 ns x 5 MHz x 50% probability = 2.5 mA.
There is a special use of the 3-state control input: When it is
directly driven by the same signal that drives the data input
of the buffer, i.e. when D and T are effectively tied together,
the 3-state buffer becomes an “open collector” driver. Multi-
ple drivers of this type can be used to implement the “wired-
AND” function, using resistive pull-up.
In this situation there cannot be any contention, since the 3-
state control input is designed to be slow in activating and
fast in deactivating the driv er. Connecting D to g round is an
obvious alternative, but may be more difficult to route.
Vertical Longlines
There are four ver tical Longlines per routing channel: two
general purpose, one for the global clock net and one for
the alternate clock net.
Clock Buffers
XC3000/XC3100 devices each contain two high-fan-out,
low-skew clock-distribution networks. The global-clock net
originates from the GCLK buffer in the upper left corner of
the die, while the alternate clock net originates from the
ACLK buffer in the lower right corner of the die.
The global and alternate clock networks each hav e optional
fast CMOS inputs, called TCLKIN and BCLKIN, respec-
tively. Using these inputs provides the fastest path from the
PC board to the internal flip-flops and latches. Since the
signal bypasses the input buffer, well-defined CMOS levels
must be guaranteed on these clock pins.
To specify the use of TCLKIN or BCLKIN in a schematic,
connect an IPAD symbol directly to the GCLK or ACLK
symbol. Placing an IBUF between the IPAD and the clock
buffer will prevent TCLKIN or BCLKIN from being used.
The clock buffer output nets only drive CLB and IOB clock
pins.
They do not drive any other CLB inputs.
In rare cases
where a clock needs to be connected to a logic input or a
device output, a signal should be tapped off the cloc k b uffer
input, and routed to the logic input. This is not possib le with
clocks using TCLKIN or BCLKIN.
The clock skew created by routing clocks through local
interconnect makes safe designs very difficult to achieve,
and this practice is not recommended. In general, the fe wer
clocks that are used, the safer the design. High fan-out
clocks should always use GCLK or ACLK. If more than two
clocks are required, the ACLK net can be segmented into
individual vertical lines that can be driven by PIPs at the top
and bottom of each column. Clock signals routed through
local interconnect should only be considered for individual
flip-flops.
Power Dissipation
As in most CMOS ICs, almost all FPGA power dissipation
is dynamic, and is caused by the charging and discharging
of internal capacitances. Each node in the device dissi-
pates power according to the capacitance in the node,
which is fixed for each type of node, and the frequency at
which the par ticular node is switching, which can be differ-
ent from the clock frequency. The total dynamic power is
the sum of the power dissipated in the individual nodes.
While the clock line frequency is easy to specify, it is usually
more difficult to estimate the average frequency of other
nodes. Two extreme cases are binary counters, where half
the total power is dissipated in the first flip-flop, and shift
registers with alternating zeros and ones, where the whole
circuit is exercised at the clocking speed.
A popular assumption is that, on av erage, each node is e x er-
cised at 20% of the clock rate; a major EPLD vendor uses a
16-bit counter as a model, where the effective percentage is
only 12%. Undoubtably, there are extreme cases, where the
ratio is much lower or much higher, but 15 to 20% may be a
valid approximation for most normal designs. Note that glo-
bal clock lines must always be entered with their real, and
obviously well-known, frequency.
Consequently, most power consumption estimates only
serve as guidelines based on gross approximations. Table
4 shows the dynamic pow er dissipation, in mW per MHz, for
different types of XC3000 nodes. While not precise, these
numbers are sufficiently accurate for the calculations in
which they are used, and may be used for any XC3000/
XC3100 device . Table 5 shows a sample pow er calculation.
Table 4: Dynamic Power Dissipation
Table 5: Sample Power Calculation for XC3020
XC3020 XC3090
One CLB driving three local inter-
connects 0.25 0.25 mW/MHz
One device output with a 50
pF load 1.25 1.25 mW/MHz
One Global Clock Buffer and line 2.00 3.50 mW/MHz
One Longline without driver 0.10 0.15 mW/MHz
Quantity Node MHz mW/MHz mW
1 Clock Buffer 40 2.00 80
5 CLBs 40 0.25 50
10 CLBs 20 0.25 50
40 CLBs 10 0.25 100
8 Longlines 20 0.10 16
20 Outputs 20 1.25 500
Total Power ~800
June 1, 1996 (Version 1.0) 14-19
Crystal Oscillator
XC3000 and XC3100 devices contain an on-chip crystal
oscillator circuit that connects to the ACLK buffer. This cir-
cuit, Figure 5, comprises a high-speed, high-gain inverting
amplifier with its input connected to the dedicated XTL2
pin, and its output connected to the XTL1 pin. An external
biasing resistor , R1, with a v alue of 0.5 to 1 MΩ is required.
A crystal, Y1, and additional phase-shifting components,
R2, C1 and C2, complete the circuit. The capacitors, C1
and C2, in series form the load on the cr ystal. This load is
specified by the crystal manufacturer, and is typically 20 pF.
The capacitors should be approximately equal: 40 pF each
for a 20 pF crystal.
Either series- or parallel-resonant crystals may be used,
since they differ only in their specification. Crystals con-
strain oscillation to a narrow band of frequencies , the width
of which is <<1% of the oscillating frequency; the exact fre-
quency of oscillation within this band depends on the com-
ponents surrounding the crystal. Series-resonant crystals
are specified by their manufacturers according to the lower
edge of the frequency band, parallel-resonant crystals
according to the upper edge.
The resistor R2 controls the loop gain and its value m ust be
established b y e xperimentation. If it is too small, the oscilla-
tion will be distor ted; if it is too large, the oscillation will fail
to star t, or only start slowly. In most cases, the value of R2
is non-critical, and typically is 0 to 1 kΩ.
Once the component values have been chosen, it is good
practice to test the oscillator with a resistor (~1 kΩ) in series
with the crystal. If the oscillator still starts reliably, indepen-
dent of whether the power supply turns on quickly or slo wly,
it will always work without the resistor.
For operation above 20 to 25 MHz, the crystal must be
operated at its third harmonic. The capacitor C2 is replaced
by a parallel-resonant LC tank circuit tuned to ~2/3 of the
desired frequency, i.e., twice the fundamental frequency of
the crystal. Table 6 shows typical component values for the
tank circuit.
T ab le 6: Third-Harmonic Crystal Oscillator T ank-Circuit
Crystal-Oscillator Considerations
There is nothing Xilinx-specific about the oscillator circuit.
It’s a wide-band inverting amplifier, as used in all popular
microcontrollers. When a crystal and some passive compo-
nents close the feedback path, this circuit becomes a reli-
able and stable clock source.
The path from XTAL2 to XTAL1 inside the LCA device is a
single-stage inverting amplifier, which means it has a low-
frequency phase response of 180˚, increasing by 45˚ at the
3-dB frequency.
Input impedance is 10-15 pF, input threshold is CMOS, but
dc bias must be supplied externally through a megohm
resistor from XTAL1 to XTAL2.
Low-frequency gain is about 10, rolling off 3dB at 125 MHz.
Output impedance is between 50 and 100 Ω and the capac-
itance on the output pin is 10 to 15 pF.
Pulse response is a delay of about 1.5 ns and a rise/fall
time of about 1.5 ns.
Frequency LC T ank
(MHz) L (µH) C2 (pF) Freq (MHz) R2 (Ω) C1 (pF)
32 1 60 20.6 430 23
35 1 44 24.0 310 23
49 1 31 28.6 190 23
72 1 18 37.5 150 12
XTAL_OUT
XTAL_IN
R1
R2
C1 C2
Y1
FPGA
3RD 
Overtone
Only
L
X6128
Figure 5: Crystal Oscillator
XC3000 Series Technical Information
14-20 June 1, 1996 (Version 1.0)
For stable oscillation,
• the loop gain must be e xactly one , i.e ., the internal gain
must be matched by external attenuation, and
• the phase shift around the loop must be 360˚ or an
integer multiple thereof. The external network must,
therefore, provide 180˚ of phase shift.
A crystal is a piezoelectric mechanical resonator that can
be modeled by a very high-Q ser ies LC circuit with a small
resistor representing the energy loss. In parallel with this
series-resonant circuit is unavoidab le par asitic capacitance
inside and outside the crystal package, and usually also
discrete capacitors on the board.
The impedance as a function of frequency of this whole
array starts as a small capacitor at low frequencies
(Figure 6). As the frequency increases, this capacitive
reactance decreases rapidly, until it reaches zero at the
series resonant frequency.
At slightly higher frequencies, the reactance is inductive,
starting with a zero at series resonance, and increasing
very rapidly with frequency. It reaches infinity when the
effective inductive impedance of the series LC circuit
equals the reactance of the parallel capacitor. The parallel
resonance frequency is a fraction of a percent above the
series-resonance frequency.
Over this very narrow frequency range between series and
parallel resonance, the crystal impedance is inductive and
changes all the way from zero to infinity. The energy loss
represented by the series resistor prevents the impedance
from actually reaching zero and infinity, but it comes very
close.
Microprocessor- and FPGA-based crystal oscillators all
operate in this narrow frequency band, where the crystal
impedance can be any inductive value. The circuit oscil-
lates at a frequency where the attenuation in the external
circuit equals the gain in the FPGA device, and where the
total phase shift, internal plus external, equals 360˚.
Figure 7 explains the function. At the frequency of oscilla-
tion, the series-resonant circuit is effectively an inductor,
and the two capacitors act as a capacitive voltage divider,
with the center-point grounded. This puts a virtual ground
somewhere along the inductor and causes the non-driven
end of the crystal to be 180˚ out of phase with the driven
end, which is the external phase shift required for oscilla-
tion. This circuit is commonly known as a Pierce oscillator.
Practical Considerations
• The series resonance resistor is a critical parameter. To
assure reliable operation with worst-case crystals, the
user should experiment with a discrete series resistor
roughly equal to the max internal resistance specified
by the crystal vendor. If the circuit tolerates this
additional loss, it should operate reliably with a worst-
case crystal without the additional resistor.
• The two capacitors affect the frequency of oscillation
and the start-up conditions. The series connection of
the two capacitors is the effective capacitive load seen
by the crystal, usually specified by the crystal vendor.
• The two capacitors also determine the minimum gain
required for oscillation. If the capacitors are too small,
more gain is needed, and the oscillator may be
unstable. If the capacitors are too large, oscillation is
stable b ut the required gain may again be higher. There
is an optimum capacitor value, where oscillation is
stable , and the required gain is at a minimum. For most
crystals, this capacitive load is around 20 pF, i.e., each
of the two capacitors should be around 40 pF.
• Crystal dissipation is usually around 1 mW, and thus of
no concern. Beware of crystals with “drive-level
dependence” of the series resistor. They may not start
up. Proper drive level can be checked by varying Vcc.
The frequency should increase slightly with an increase
in Vcc. A decreasing frequency or unstable amplitude
indicate an over-driven crystal. Excessive swing at the
X2818
Capacitive
j L
Frequency
Inductive
Parallel
Resonance
Series
Resonance
j C
1
ϖ
ϖ
R
CL
Figure 6: Reactance as a Function of Frequency
X5321
R
XTAL
C L
XC2000/XC3000
Figure 7: Pierce Oscillator
June 1, 1996 (Version 1.0) 14-21
XTAL2 input results in clipping near Vcc and ground. An
additional 1 to 2 kΩ series resistor at the XTAL1 output
usually cures that distortion problem. It increases the
amplifier output impedance and assures additional
phase margin, but results in slower start-up.
• Be especially careful when designing an oscillator that
must operate near the specified max frequency. The
circuit needs excess gain at small signal amplitudes to
supply enough energy into the crystal for rapid start-up.
High-frequency gain may be marginal, and start-up may
be impaired.
• Keep the whole oscillator circuit physically as compact
as possible, and provide a single ground connection.
Grounding the crystal can is not mandatory but may
improve stability.
CCLK Frequency Variation
The on-chip R-C oscillator that is brought out as CCLK also
performs several other internal functions. It generates the
power-on delay, 216 = 65,536 periods for a master,
214 = 16,384 periods for a sla ve or peripheral de vice. It gen-
erates the shift pulses for clearing the configuration array,
using one clock period per frame, and it is the clock source
for several small shift registers acting as low-pass filters for
a variety of input signals.
The nominal frequency of this oscillator is 1 MHz with a
max deviation of +25% to -10%. The cloc k frequency, there-
fore, is between 1.25 MHz and 0.5 MHz. In the XC4000
family, the 1-MHz clock is derived from an internal 8-MHz
clock that also can be used as CCLK source.
Xilinx circuit designers make sure that the internal clock fre-
quency does not get faster as devices are migrated to
smaller geometries and faster processes. Even the newest
and fastest Xilinx FPGA is compatible with the oldest and
slowest device ever manufactured. The CCLK frequency is
fairly insensitive to changes in VCC, v arying only 0.6% for a
10% change in VCC. It is, however, very temperature
dependent, increasing 40% as the temperature drops from
25°C to -30°C, (Table 7.)
CCLK Low-Time Restriction
When used as an input in Slave Serial and Readback
modes, CCLK does not tolerate a Low time in excess of 5
µs. For very low speed operation, the CCLK High time can
be stretched to any value, but the Low time must be kept
short. XC4000 and XC5200 devices do not have this
restriction.
Battery Back-up
Since SRAM-based FPGAs are manufactured using a
high-performance low-po wer CMOS process , they can pre-
serve the configuration data stored in the internal static
memory cells even during a loss of primar y power. This is
accomplished by forcing the device into a low-power non-
operational state, while supplying the minimal current
requirement of VCC from a battery.
Circuit techniques used in XC3100, XC4000 and XC5200
devices prevent ICC from being reduced to the level need
for battery back-up. Consequently, battery back-up should
only be used for XC2000, XC2000L, XC3000, XC3000A
and XC3000L devices.
There are two primary considerations for battery backup
which must be accomplished by external circuits.
• Control of the Power-Down (PWRDWN) pin
• Switching between the primary VCC supply and the
battery.
Important considerations include the following.
• Insure that PWRD WN is asserted logic Low prior to VCC
falling, is held Lo w while the primary V CC is absent, and
returned High after VCC has returned to a normal level.
PWRDWN edges must not rise or fall slowly.
• Insure “glitch-free” switching of the power connections
to the FPGA device from the primary VCC to the battery
and back.
• Insure that, during normal operation, the FPGA VCC is
maintained at an acceptable le v el, 5.0 V ± 5% (±10% f or
Industrial and Military).
Series Resonant or Parallel Resonant?
Crystal manufacturers label some crystals as series-
resonant, others as parallel-resonant, but there really is
no difference between these two types of crystals, they
all operate in the same way. Every cr ystal has a ser ies
resonance, where the impedance of the crystal is
extremely low, much lower than at any other frequency.
At a slightly higher frequency, the crystal is inductive
and in parallel resonance with the unavoidable stray
capacitance or the deliberate capacitance between its
pins.
The only difference between the two types of crystal is
the manuf acturer's choice of specifying either of the two
frequencies. If series resonance is specified, the actual
frequency of oscillation is a little higher than the speci-
fied value. If parallel resonance is specified, the fre-
quency of oscillation is a little lower. In most cases,
these small deviations are irrelevant.
Table 7: Typical CCLK Frequency Variation
VCC Temp Frequency
4.5 V 25°C 687 kHz
5.0 V 25°C 691 kHz
5.5 V 25°C 695 kHz
4.5 V -30°C 966 kHz
4.5 V +130°C 457 kHz
XC3000 Series Technical Information
14-22 June 1, 1996 (Version 1.0)
Figure 8 shows a power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2 V primary sup-
ply or a 3 V Lithium battery. A Seiko S8054 3-terminal
power
monitor circuit monitors VCC and pulls PWRDWN Low
whenev er VCC falls below 4 V.
Powerdown Operation
A Low level on the PWRDWN input, while Vcc remains
higher than 2.3 V, stops all internal activity, thus reducing
Icc to a very low level:
• All internal pull-ups (on Long lines as well as on the I/O
pads) are turned off.
• The crystal oscillator is turned off
• All package outputs are three-stated.
• All package inputs ignore the actual input level, and
present a High to the internal logic.
• All internal flip-flops or latches are permanently reset.
• The internal configuration is retained.
• When PWRDWN is returned High, after VCC is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and D/P as at the
completion of configuration.
Things to Remember
Powerdown retains the configuration, but loses all data
stored in the device. Powerdown three-states all outputs
and ignores all inputs. No clock signal will be recognized,
and the crystal oscillator is stopped. All internal flip-flops
and latches are permanently reset and all inputs are inter-
preted as High, but the internal combinatorial logic is fully
functional.
Things to Watch Out For
Make sure that the combination of all inputs High and all
internal flip-flop outputs Low in your design will not gener-
ate internal oscillations or create permanent bus contention
by activating internal bus drivers with conflicting data onto
the same Longline. These tw o situations are f arfetched, but
they are possib le and will result in consider ab le po w er con-
sumption. It is quite easy to sim ulate these conditions since
all inputs are stable and the internal logic is entirely combi-
natorial, unless latches have been made out of function
generators.
During powerdown, the Vcc monitoring circuit is disabled. It
is then up to the user to prev ent Vcc dips belo w 2.3 V, which
would corrupt the stored configuration.
During configuration, the PWRDWN pin must be High,
since configuration uses the internal oscillator. Whenever
Vcc goes below 4 V, PWRDWN must already be Low in
order to prevent automatic reconfiguration at low Vcc. For
the same reason, Vcc must first be restored to 4 V or more,
before PWRDWN can be made High.
PWRDWN has no pull-up resistor. A pull-up resistor would
draw supply current when the pin is Low, which would
defeat the idea of powerdown, where Icc is only microam-
peres.
Configuration and Start-up
Start-Up
Star t-up is the transition from the configuration process to
the intended user operation. This means a change from
one clock source to another, and a change from interfacing
parallel or serial configuration data where most outputs are
3-stated, to normal operation with I/O pins active in the
user-system. Start-up must make sure that the user-logic
“wakes up” gracefully, that the outputs become active with-
out causing contention with the configuration signals, and
that the internal flip-flops are released from the global
Reset or Set at the right time.
Figure 10 describes Start-up timing for the XC3000 f amilies
in detail.
DONE can be programmed to go High one CCLK period
before or after the I/O become active. Independent of
DONE, the internal global Reset is de-activated one CCLK
period before or after the I/O become active.
The default option, and the most pr actical one , is f or DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. Reset is then released another cloc k period
later to make sure that user-operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 11, but the designer can
modify it to meet particular requirements.
Until the chip goes active after configur ation, all I/O pins not
involved in the configuration process remain in a high-
impedance state with weak pull-up resistors; all internal
flip-flops and latches are held reset. Multiple FPGA devices
hooked up in a daisy chain will all go active simultaneously
FPGA
SEIKO
S 8054
3
21 PWRDWN
VCC
IN5817 IN5817
B35
Lithium
Battery
X5997
VCC
Seiko S8054 Specifications
Detect Voltage
4.305 V max
208 mV typ
0.52 mV/°C
2.6 µA typ
3.995 V min
Hysteresis
Temp. Coeff.
ICC @ + 6V
Figure 8: Battery Back-up Circuit
June 1, 1996 (Version 1.0) 14-23
on the same CCLK edge. This is well documented in the
data sheets.
Not documented, however, is how the internal combinato-
rial logic comes alive during configuration: As configuration
data is shifted in and reaches its destination, it activates the
logic and also “looks at” the IOB inputs. Even the crystal
oscillator starts operating as soon as it receiv es its configu-
ration data. Since all flip-flops and latches are being held
reset, and all outputs are being held in their high-imped-
ance state, there is no danger in this “staggered awaken-
ing” of the internal logic. The operation of the logic pr ior to
the end of configuration is e v en useful; it ensures that clock
enables and output enables are correctly defined before
the elements they control become active.
Once configuration is complete, the FPGA device is acti-
vated. This occurs on a rising edge of CCLK, when all out-
puts and clocks that are enabled become active
simultaneously. Since the activ ation is triggered by CCLK, it
is an asynchronous event with respect to the system clock.
To avoid start-up problems caused by this asynchronism,
some designs might require a reset pulse that is synchro-
nized to the system clock.
The circuit shown in Figure 10 generates a short Global
Reset pulse in response to the first system clock after the
end of configuration. It uses one CLB and one IOB, and
also precludes the use of the LDC pin as I/O.
During Configuration, LDC is asserted Low and holds the
D-input of the flip-flop High, while Q is held Low b y the inter-
nal reset, and RESET is kept High by internal and external
pull-up resistors. At the end of configuration, the LDC pin is
unasserted, but D remains High since the function genera-
tor acts as an R-S latch; Q stays Low, and RESET is still
pulled High by the external resistor. On the first system
clock after configuration ends, Q is clocked High, resetting
the latch and enabling the output driver. which forces
RESET Low. This resets the whole chip until the Low on Q
permits RESET to be pulled High again.
The whole chip has thus been reset by a short pulse insti-
gated by the system clock. No further pulses are gener-
ated, since the High on LDC prevents the R-S latch from
becoming set.
Beware of a Slow-Rising XC3000
Series RESET Input
It is a wide-spread habit to drive asynchronous RESET
inputs with a resistor-capacitor network to lengthen the
reset time after power-on. This can also be done with Xilinx
FPGAs, b ut the user should question the need, and should
beware of certain avoidable problems.
Xilinx FPGAs contain an internal voltage-monitoring circuit,
and start their internal housekeeping operation only after
VCC has reached ~3.5 V. The internal housekeeping and
configuration memory clearing operation then takes
between about 10 and 100 ms, depending on configur ation
mode and processing variations. Any RC delay shorter
than 40 ms for a device in master configuration mode, or
shorter than 10 ms f or a device in sla ve configuration mode ,
is clearly redundant.
A significantly longer RC delay can be used to hold off con-
figuration. Without the use of an external Schmitt trigger cir-
cuit, the rise time on the RESET input will be very slow , and
is likely to cross the threshold of ~1.4 V several times, due
to external or internal noise. This can cause the FPGA to
start configuration, then immediately abort it, then start it
again, after having automatically cleared the configuration
memory once more.
This is no problem for the FPGA, but it requires that the
source of configuration data, especially an XC1700 serial
PROM, be reset accordingly. This is another reason to use
the INIT output of the lead FPGA, instead of LDC, to drive
the RESET input of the XC1700 serial PROMs.
CCLK
DONE
Global Reset
I/O
CCLK Period
Length Count Match
F
X5967
Figure 9: Start-up Timing
D Q
Low
OE = High
T = Low
MR
VCC
RESET
IOB
IOB
High LDC
CLB
System Clock
X3222 Figure 10: Synchronous Reset
XC3000 Series Technical Information
14-24 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 14-25
Summary
These guidelines describe the configuration process for XC2000, XC3000 and XC4000-Series FPGA de vices . The a verage
user need not understand all details, but should refer to the debugging hints when problems occur.
The XC2000, XC3000, and XC4000 series FPGAs share a
basic configuration concept, and can be combined in a
common configuration bitstream, but there are small differ-
ences among the three families as described below.
Following their initial power-on configuration-memory initial-
ization, these Xilinx FPGAs are configured by a serial config-
uration bitstream. The byte-parallel configuration modes just
activate an internal parallel-to-serial conv erter , and then use
the serial bitstream internally. Express mode in XC4000EX
operates on 8 bits in parallel. This mode is not cov ered in this
application note. The software generates a bitstream that
starts with a 40-bit header, see Figure 1.
Each device uses a f ew of the leading 1s to prepare f or con-
figuration, then detects the 0010 pattern and stores the fol-
lowing 24 bits as a length-count value in an internal
register. The content of this register is continuously com-
pared against a running counter that increments on every
rising CCLK edge. CCLK is either an output (in Master and
Asynchronous Peripheral modes) or an input (in Slave
Serial and Synchronous P eripheral modes). In all modes, it
is the externally observable Low-to-High transition on the
CCLK pin that causes the internal action. Every CCLK ris-
ing edge that occurs while INIT and RESET are High is
counted, even dur ing the preamble. Note that XC2000 and
XC3000 use quasi-static circuitry which imposes a 5 µs
max limit on the CCLK Low time, while XC4000 is com-
pletely static and has no max CCLK time limit. This is, of
course, only of interest in XC2000 and XC3000 Slave
Serial mode, where CCLK is generated by the user.
While it is permissible, although not meaningful, to modify
the number of leading ones by adding additional ones, or
subtracting up to four ones, this would inevitably affect the
number of CCLK pulses received by the counter, and thus
change the moment when the internal counter is equal to
the value stored in the length-count register.
Don’t add or
delete preamble-leading ones!
Each device passes the incoming header, including the
length-count value, on to the DOUT pin, delayed by half a
CCLK period, i.e. the bits are clocked out on a f alling CCLK
edge. In this w ay, the header is passed on to all devices that
might be connected in a daisy-chain. After the length-count
data has been passed on, DOUT goes active High and
stays High until the de vice has been filled with the appropri-
ate number of configuration frames . After that, DOUT again
passes all incoming configuration data on to other devices
that might be part of the daisy chain.
DOUT is thus the best observation point to see whether the
configuration process has started properly.
Immediately following the header, configuration data is
received, formatted in a device-specific sequence of
frames. Each frame starts with a single 0 as star t bit, fol-
lowed by a device-specific number of configuration bits per
frame, followed by three 1s as stop bits (XC2000, XC3000)
or, in XC4000, by four bits that are either 0110, or four bits
of a running 16-bit CRC error-checking code. (The choice is
made in Makebits, where the default is “CRC disabled”).
The header is not included in the CRC calculation.
Each frame is physically shifted into a serial shift register
that had been preset to all ones. When the z ero start bit hits
the far end of this shift register , the data fr ame is transferred
in parallel into the configuration memory, as addressed by
the position of an internal token or pointer . The three stop or
four error-check bits provide ample time for this transfer,
even at the 10 MHz CCLK rate allowed for XC3000 and
XC4000 devices. After this transfer, the shift-in procedure
continues with the following frame. Note that there is no
counter for the n umber of bits in the frame or for the n umber
of frames. The operation is self-synchronized by detecting
the presence of a start bit at the f ar end of the shift register,
and by moving the frame pointer.
Each Xilinx FPGA requires a number of configuration bits
that is device-dependent, b ut independent of the configur a-
tion content, and independent of the configuration mode.
The number of configuration bits per device varies from
12,038 for the XC2064 to 422,168 for the XC4025, roughly
20 bits per gate. The exact numbers of configuration bits
are listed in the specific family data sheets.
FPGA Configuration Guidelines
June 1, 1996 (Version 1.0) Application Note By PETER ALFKE
11111111 0010 (MSB) 24-Bit Length Count (LSB) 1111 Data
X5553
Figure 1: 40-Bit Header
FPGA Configuration Guidelines
14-26 June 1, 1996 (Version 1.0)
Protection Against Data or Format
Errors
The serial configuration scheme has proven reliable in
thousands of designs and millions of devices, but there
have been cases where an erroneous bitstream was
loaded accidentally. The original XC2000 and XC3000
devices provide no effective protection against this type of
error. If long enough, any random sequence of 0s and 1s
will configure a device. This inevitably takes more CCLK
pulses than specified in the length-count value . This means
that the CCLK counter equals the length-count value bef ore
the FPGAs are filled. This comparison is, therefore,
ignored, and an additional 16 million CCLK pulses are
required to roll the 24-bit length counter and finish the con-
figuration. Such a configuration will, of course, be wrong
and might result in excessive power consumption due to
internal or external contentions.
XC3000A, XC3100A, XC3000L and XC3100L devices use
a simple and effective method to protect against erroneous
configuration files or against loss (or gain) of CCLK pulses:
All Xilinx FPGA devices recognize a new frame when its
leading zero reaches the end of the shift register. XC2000,
XC3000, and XC3100 devices do not check for the pres-
ence of valid stop bits, but XC3000A/XC3100A/XC3000L/
XC3100L devices always check whether the three bits at
the end of the defined frame length are 111. If this check
fails, INIT is pulled Low and the internal configuration is
stopped, although a master CCLK keeps running. The user
must recognize this state and start a new configuration by
applying a >6 µs Low level on RESET.
This simple check does not protect against single-bit ran-
dom errors, but it offers almost 100% protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, as well as PC-board defects, such as
broken lines or solder bridges.
The XC4000 series uses, optionally, four bits of a running
16-bit cyclic redundancy check code at the end of each
frame, combined with additional CRC bits at the end of the
bit stream. These error-detecting CRC codes provide
excellent protection against errors, even those that do not
change the frame structure. When an error is detected,
INIT goes Low and stays Low until the user initiates a
reconfiguration. (A master device does, however, continue
generating CCLK pulses and incrementing or decrement-
ing the parallel PROM address).
Daisy-Chain Operation
Multiple FPGAs can be configured by a single concate-
nated bitstream. The device daisy chain is formed by con-
necting DOUT to the next device’s DIN, and connecting all
CCLK pins in parallel. Since DOUT goes active on a falling
clock edge , and DIN is used on the subsequent rising clock
edge, each DOUT-to-DIN connection adds one extra bit of
delay to the bitstream. Since the header is passed through
all devices, they all receive this information almost simulta-
neously (staggered by one bit per device), but all devices
maintain perfect synchronism between their CCLK
counters.
Xilinx recognizes the need f or all de vices in a daisy chain to
finish their configuration and begin user operation simulta-
neously, as a result of one common CCLK edge. Therefore ,
all devices in a daisy-chain need a common timing refer-
ence. They cannot rely on the start pattern received
through the pipelined chain, but must all count the common
CCLK pulses exactly the same way. This explains the
importance of well-defined configuration clocking.
Start-Up Procedure
The transition from configuration to user operation faces
several difficulties. During configuration, all outputs that are
not involved in the configuration process are 3-stated,
although the crystal oscillator circuit is activated as soon as
possible. All internal flip-flops and latches are held reset
(set or reset in XC4000), and the DONE output is held Low.
At the end of configuration, these three conditions must
change: As shown in detail in Figure 2, the three families
offer different options:
XC2000 has no options; the I/Os go active one CCLK
period after length-count match. DONE goes activ e and the
global reset is released one CCLK period later.
XC3000 makes the I/Os go active two CCLK periods after
length-count match; but DONE and the release of the glo-
bal reset can each occur either one CCLK period before or
after the I/Os go active . The def ault is “early DONE and late
release of the global reset”. This makes the outputs go
active while the internal logic is still held reset. The other
Makebits option, “early release of global reset”, lets the
internal logic be clocked out of its reset state bef ore the out-
puts go active.
Normally, there is no defined timing relationship between
the last configuration events triggered by the rising edge of
CCLK, and the subsequent events that are controlled by
the system clock. The user must be aware of the potential
problems of this asynchronous relationship. See the
XC4000 solution described below.
XC4000 has more options for the relative timing of I/Os,
DONE and GSR, the release of the global set or reset.
June 1, 1996 (Version 1.0) 14-27
XC4000/
XC5200
UCLK_SYNC
XC4000/
XC5200
UCLK_NOSYNC
XC4000/
XC5200
CCLK_SYNC
XC4000/
XC5200
CCLK_NOSYNC
XC3000
XC2000
CCLK
GSR Active
UCLK Period
DONE IN
DONE IN
Di Di+1 Di+2
Di Di+1 Di+2
U2 U3 U4
U2 U3 U4
U2 U3 U4C1
Synchronization
Uncertainty
Di Di+1
Di Di+1
DONE
I/O
GSR Active
DONE
I/O
GSR Active
DONE
C1 C2
C1 U2
C3 C4
C2 C3 C4
C2 C3 C4
I/O
GSR Active
DONE
I/O
DONE
Global Reset
I/O
DONE
Global Reset
I/O
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
CCLK Period
Length Count Match
F
F
F
F
F
F
X5972
C1, C2 or C3
Note: Thick lines are default option
Figure 2: Start-up Timing
FPGA Configuration Guidelines
14-28 June 1, 1996 (Version 1.0)
XC4000 can also use DONE as an input to hold off the acti-
vation of the I/Os and the release of GSR, until DONE is no
longer pulled Low. The change then takes place either
immediately upon the release of DONE, or as a result of the
next CCLK rising edge. When all DONE pins in a daisy
chain are interconnected, this start-up mode guarantees
that all devices in the daisy chain will go active only when
all of them have reached the DONE state, another protec-
tion against configuration errors.
XC4000 can also be configured to employ the system
(user) clock instead of CCLK, again either using DONE as
an output, or as a bidirectional pin.
The user clock provides a properly synchronized and race-
free transition from the end of configuration to the begin-
ning of user operation. The unspecified on-chip dela y in the
release of GSR (about 100 ns in XC4013) requires some
caution, however, when using a high clock frequency for
configuration.
While XC2000, XC3000, and XC4000 can be arbitrarily
interspersed in a daisy-chain, there is one restriction: the
lead device m ust belong to the highest family in the chain. If
the chain contains XC4000 devices , the lead de vice cannot
be XC2000 or XC3000; if the chain contains XC3000, then
the lead device cannot be XC2000. The reason is sho wn in
Figure 2. Since all devices in the chain store the same
length-count value and generate or receive one common
sequence of CCLK pulses, they all recognize length-count
match on the same CCLK edge. The master device then
generates additional CCLK pulses until it reaches its finish
point F. As shown in Figure 2, the diff erent families generate
and require different numbers of additional CCLK pulses
until they reach F. Not reaching F means that the device
has not really finished its configuration process, although
DONE may have gone High, the outputs became active,
and the internal reset has been released. For XC4000, not
reaching F means that READBACK cannot be initiated, and
most boundary scan instr uctions cannot be used. This lim-
itation has been criticized by designers who w ant to use an
inexpensive lead device in Peripheral Mode, and save the
more precious XC4000 I/O pins. Here is a solution for that
case (Figure 3):
One CLB and one IOB in the lead XC3000 device are used
to generate the additional CCLK pulse required by the
XC4000 devices . When the lead device releases its internal
reset signal, the 2-bit shift register star ts responding to its
clock input, and it generates an activ e Lo w output signal f or
the duration of one clock period. An external connection
between this IOB pin and the CCLK pin thus creates the
extr a CCLK pulse. This solution requires one CLB , one IOB
and pin, and an internal clock source with a frequency of up
to 5 MHz. Obviously, the XC3000 lead device must be con-
figured with late internal reset, which happens to be the
default option.
Configuration Modes
There are six different configuration modes, hardware-
selected by applying logic levels to the three mode inputs,
M0, M1, and M2. The six modes are: Master Serial, Master
P ar allel Up, Master Parallel Do wn, Synchronous Peripheral
(XC4000 only), Asynchronous P eripheral, and Slav e Serial.
In Master modes, the FPGA addresses an external PROM
or EPROM storage device, and reads data from it. No addi-
tional timing or control signals are used.
In Peripheral mode, the FPGA accepts b yte-wide data (bit-
serial in XC2000), and interacts with the source of data,
usually a microprocessor, with a Ready/Busy handshake.
In Slave mode, the FPGA receives bit-serial data and a
clock from an e xternal data and timing source, either from a
microprocessor, or from the lead device in an FPGA-daisy
chain.
The modes are selected by putting the appropriate logic
levels on the three mode inputs, M0, M1, and M2 prior to
the beginning of configuration. These three pins can be
hardwired to VCC or Ground, but they can then never be
used as user I/O. It is better to force a mode pin Low with a
3 kΩ pull-down resistor to ground, acting against the 50 to
100 kΩ internal pull-up resistor, and to rely on the built-in
pull-up resistor to establish a High level on the M1, M2
mode pins, and a 50 kΩ external pull-up resistor on M0.
This eliminates the restrictions on using M2 as logic output
on XC2000 and XC3000, or M1 on XC4000, and the use of
M1 as readback data output in XC2000 and XC3000.
When mode pin levels are driven by external logic, these
levels must be established very soon after power-up.
Establishing a mode level later might eliminate the extra
master power-on delay that makes a master wait for slave
devices to be ready after power-on. Delaying mode levels
until the beginning of configuration will obviously cause the
configuration to fail. Note that some EPLD devices have
surprisingly long power-up delays. Be very careful when
controlling mode levels in creative ways.
Output
Connected
to CCLK
OE/T
0
1
1
0
0
0
0
1
1
1
Reset
X5552
etc
Active Low Output
Active High Output
3-Stated Output
3-Stated Output
Figure 3: Additional CCLK-Pulse Generator
June 1, 1996 (Version 1.0) 14-29
Selecting the Best Configuration Mode
The selection of the most appropriate configuration mode is
influenced by many factors, like
• the need for interface simplicity,
• the need for rapid configuration,
• the need for multiple configuration sources,
• the av ailability of a microprocessor-based configur ation
driver.
The simplest interface is Master Serial, using only two
FPGA pins, CCLK and DIN, and no external timing or con-
trol signals.
The fastest configuration mode is Slave Serial or XC4000
Synchronous P eripheral. In these modes , the user can sup-
ply a well-defined CCLK frequency of up to 10 MHz for all
XC3000 and XC4000 5-Volt devices . No other configuration
mode is that fast. For prototyping and rapid configuration
change, the PC can configure the FPGA directly in Slave
Serial mode, using the Xilinx-provided Download Cable or
XChecker.
Multiple configuration codes are most conveniently stored
in a microprocessor memory, using Peripheral mode to
configure the FPGA. For field upgrades, Peripheral mode
offers the greatest flexibility. New files can be supplied via
diskette or modem, and can be downloaded by the micro-
processor.
When Configuration Fails
General Debugging Hints for all Families
If the DONE output does not go High, there are several
things to check.
• Checking all supply and configuration-related pins with
an oscilloscope or logic analyzer can reveal wiring
errors, bad socket pins, noisy ground, noisy CCLK, a
serial configuration PROM VPP pin not connected to
VCC, PWRDWN not pulled High, poor or noisy RESET,
missing pull-up resistors on DONE (or INIT in the
XC3000), etc.
• Monitor the DOUT pin of the lead device, i.e. the FPGA
that is either configured alone, or f orms the beginning of
a daisy chain. At the start of configuration, you should
see the 40-bit header shown in Figure 1. After this
sequence, the DOUT pin remains High until the device
has received all its data. Then, the device becomes
transparent and passes additional data (provided there
is a daisy chain) through the DOUT pin to the Slave
devices. If you don’t see this pattern, you have a gross
error somewhere. Check the following items:
• INIT going Low again after configuration start indicates
a configuration bitstream or framing error in XC3000A,
XC3000L or XC4000 families.
• If RESET is used to delay configuration, make sure it
has a rise time of <100 ns and that it is glitch-free.
• Ringing on the CCLK line can cause spurious clocking
and loss of frame synchronization in the FPGA.
• Configuration functions can be disrupted by signal
contention between configuration inputs and the FPGA
user outputs which become active at the end of
configuration. This change is indicated by I/O pins going
active and HDC/LDC no longer at their configuration
levels. Contention can be avoided by rearranging pin-
outs, maintaining additional 3-state control of user-I/O
outputs, or matching start-up output levels to the
configuration input levels on inputs other than chip-
select. It is also possible to use a series resistor (1-10
kΩ) to provide isolation between conflicting signal
sources that could occur after configuration is complete.
• If an FPGA heats up significantly, this is usually the
result of applying the wrong bitstream, e.g. the
bitstream for a different device, causing contention.
• During reprogramming, user logic must generate a
time-out that insures all devices have completed the
Clear cycle before any configuration data is sent.
• Removing the FPGA supply voltage while externally
powered signals continue to drive input pins, might
keep the FPGA VCC pins at a 0.5-to-2.0 V level, which
can leave the FPGA in an invalid state. The FPGA
input-protection diodes are there to clamp input-voltage
excursions to the two supply connections. When the
FPGA supply voltage falls more than 0.5 V below an
active input signal, this input signal will supply
degenerate VCC levels. If the input signals are not
current-limited, the FPGA inputs can even be damaged
by the excessive input current.
• If extraneous CCLK pulses are applied after Clear but
before the beginning of the header, the internal clock
count will equal the stored length-count value bef ore the
configuration data is completely loaded. In this case,
the DONE output does not become active until the cloc k
counter equals length count a second time. This
requires 224 extra clocks, or about 20 s at the typical
rate of 0.7 MHz.
Whenever configuration takes 15 to 25 seconds, this is
due to a mismatch between length count and the num-
ber of CCLK pulses received
.
• XChecker or the XACT Download Cable provide an
alternate method of configuration to verify configuration
data and to isolate wiring errors, such as interchanged
or inverted configuration data or control signals.
• Try a different device. Although the chips are 100%
factory-tested, an individual device might have been
damaged later.
FPGA Configuration Guidelines
14-30 June 1, 1996 (Version 1.0)
General Debugging Hints for the XC2000
and XC3000 Families
• An undefined (floating) or active Low PWRDWN during
configuration can disturb the operation. A Low level on
PWRDWN immediately bef ore the start of configuration
causes problems in XC2000, forces XC3000 into Slave
mode, but is acceptable in XC3000A and L.
• In the XC2000 and XC3000 families, the configuration-
clock input signal drives quasi-static circuitry that does
not tolerate a Low time of more than 5 µs.
• At power-up, make sure VCC rises in 25 ms or less. If
this cannot be guaranteed, hold RESET active on the
FPGAs and on the serial PROMs until VCC has reached
4.5 V.
• A slowly rising or noisy RESET can cause multiple
FPGAs to get out of synchronization. Always debounce
reset switches.
General Debugging Hints for the XC4000
Family
• At power-up, make sure VCC rises in 25 ms or less. If
this cannot be guaranteed, hold PROGRAM or INIT
active Low on the FPGAs and hold the serial PROMs
reset until VCC has reached 4.5 V.
• The boundary scan input pins are active during
configuration, even if boundary scan is not used in the
design. Toggling TCK, TMS and TDI during
configuration might send the device into EXTEST
mode, which interferes with configuration. Keeping at
least one of these three inputs continuously High during
configuration avoids this problem.
Additional Mode-Specific Debugging Hints
for All Families
Master Parallel Up and Down Mode
• Review the general debugging hints.
• Check that the PROM data pins are connected to the
FPGA input pins D0-D7. Check that the PROM address
pins are connected to the FPGA output pins A0-A15.
Verify that all these connections are in the right order.
Monitor the FPGA pins, not the socket pins. Make sure
the socket is good.
• If the PROM is dedicated to the FPGA, the CS and OE
PROM inputs should be driven from the DONE or LDC
FPGA output.
• Verify that the FPGA is sending addresses to the
PROM. If it is not, check the FPGA mode pins.
M0 = 0, M1 = 0, M2 = 1 for Master Parallel Up
M0 = 0, M1 = 1, M2 = 1 for Master Parallel Down
Make sure VCC, RESET and PWRDWN are at 5 V and
all ground pins are at 0 V.
• Check that the PROM is receiving addresses and is
sending out data. If it is not, check that the PROM is
enabled and has VCC and ground connected, and verify
that the PROM is programmed with the correct data.
• Check for contention between the PROM address or
data pins and other signals on the board.
• Check that the FPGA is addressing the correct memory
segment. In Master Parallel Up mode, the FPGA starts
at address 0000 hex and counts up; in Master Parallel
Down mode it starts at address FFFF hex (3FFFF hex
in XC4000) and counts down. If the PROM requires
different addressing, that must be taken care of by
external hardware.
• Check for ringing and noise on address and data lines.
• Make sure the data in the PROM is correct. You can
check it against the Rawbits file.
Master Serial Mode
• Review the general debugging hints.
• Verify that the FPGA is generating a clock signal on its
CCLK pin and that this signal is reaching the CLK pin of
the XC1700-series Serial-Configuration PROM. If it is
not, check the mode pins.
M0 = 0, M1 = 0, M2 = 0 for Master Serial mode
• Verify that the XC1700-series Serial Configuration
PROM is sending data. If it is not, check that pow er and
ground are applied to the Serial PROM, and VPP is
connected to VCC.
Do Not Let the V
PP
Pin Float
A floating VPP pin results in temperature-dependent
operation, the most notorious cause of unreliable con-
figuration.
• Check that the DATA pin of the Serial PROM is
connected to the DIN pin of the FPGA, and that the
PROM is enab led with CE Low and OE activ e. Note that
the OE/RESET pin is programmable for either polarity.
• Verify that the PROM is programmed with the correct
data.
• At power-up , mak e sure VCC rises from 2.0 V to 4.5 V in
less than 25 ms. If it does not, hold the FPGA RESET and
the PROM RESET activ e until VCC reaches 4.5 V. A typical
result of a slow VCC rise time is that the FPGA sends out
CCLK continuously, the CEO pin on the PROM(s) goes
Low, but the DONE pin ne v er goes High.
• If you abort configuration by asserting XC3000 RESET
or by pulling XC4000 PROGRAM Low, you must also
reset the serial PROM by asserting its RESET. Note
that this pin can be programmed for either polarity.
June 1, 1996 (Version 1.0) 14-31
Asynchronous Peripheral Mode
• Review the general debugging hints.
• Check the mode pin levels.
M0 = 1, M1 = 0, M2 = 1 for Peripheral mode
• See schematics on pages 2-40 and 2-128.
• Verify that the FPGA is receiving data at its input pin(s)
and that it is receiving valid Write-Strobe and Chip-
Select signals. If not, check the device driving the
FPGA. Make sure that these signals meet the timing
requirements listed in the product family
documentation.
XC3000 Family: Check that the minimum Write-Strobe
active time (TCA min = 100 ns) is met and observe the
RDY/BUSY signal.
XC2000 Family: Be sure maximum and minimum
Write-Strobe active times (TCA max = 5.0 µs , min = 0.25
µs) are met.
• Make sure that the FPGA is ready to receive data.
XC3000 Family: On power up, make sure that the INIT
pin has gone High, or wait at least 34 ms before you
begin sending data to the FPGA. Make sure that the
RDY/BUSY signal is High before sending each data
byte.
XC2000 Family: On power up, make sure that the
FPGA has had time to “wake up,” at least 34 ms , before
sending it data.
• Check for contention between the Chip Select and
Write Strobe signals and monitor the levels on those
pins after configuration. It is best to use the Chip Select
pins only as inputs after configuration. Avoid contention
if they are used as outputs. With XC2000 family
devices, the I/Os become active before the FPGA
receives its final data bits and clocks, and also before
the DONE pin goes High. If the user function for any of
the Chip Selects or the Write Strobe become outputs
after configuration, they could contend and, in effect,
de-select the FPGA so that it never receives its final
data bits. See also next page, left column.
Beware of
contention!
• Check f or contention betw een the FPGA pins and other
signals on the board.
XC4000 and XC3000 Families: Data is received as
eight bits in parallel. Make sure bit 0 is connected to the
D0 pin, bit 1 to D1 pin, etc.
XC2000 Family: Data is received serially. If a PROM
file is used as a data source, chec k that data is properly
serialized LSB first. Data must be LSB first, although
length count is MSB first.
Slave Serial Mode
• Review the general debugging hints.
• Check the mode pin levels.
M0 =1, M1 = 1, M2 = 1 for Slave Serial mode
• See schematics on pages 2-35 and 2-130.
• Make sure Vcc, RESET, and PWRDWN are at 5 V, and
ground pins are at 0 V.
• Verify that the FPGA is receiving data on DIN and that it
is receiving a valid clock signal on CCLK.
Check the device sending the data.
Check the device sending the clock signal, and make
sure the clock meets the timing requirements specified
in the product family documentation. A CCLK generated
by a Master FPGA always meets the timing require-
ments.
Don’t violate the XC3000 and XC2000 CCLK Low time
specification of 5.0 µs.
• Make sure the FPGA is ready to receive data.
XC3000 Family: On power up, make sure the INIT pin
is High or wait at least 34 ms before you begin sending
data to the FPGA.
XC2000 Family: On power up, make sure that the
FPGA has had time to “wake up” at least 34 ms, before
sending it data.
• At power up, make sure V CC rises from 2.0 V to 4.5 V in
less than 25 ms. If it does not, hold RESET Low until
the VCC pins reach 4.5 V.
Daisy Chain Debugging Hints
• The key to debugging daisy-chain configurations is to
isolate the problem and attempt to configure a single
FPGA. Remove all but the first device from the board
and configure it. Then insert the second device and
configure both. Repeat as you add one device at a time
until they all configure.
• The first device in the chain can be in any of the
configuration modes. Debug it first, using the hints
provided for the appropriate mode.
• All devices after the first one are in Slave Serial mode,
so refer to the Sla ve Serial mode debugging hints abo ve
to solve any problems with Slave device.
• Monitor the DOUT pin of each device in the chain and
verify that the 40-bit header appears at the beginning of
configuration, staggered by one CCLK period per
device.
• If the Master device in the chain is an XC2000-family
device and the Slaves are XC3000-family, make sure
the XC3000-family devices are configured with early
DONE.
FPGA Configuration Guidelines
14-32 June 1, 1996 (Version 1.0)
Potential Length-Count Problem in Parallel
or Peripheral Modes
It is highly desirable that the complete change from config-
uration to user operation occur as the result of one single
byte-wide input. The activation of outputs and DONE, the
de-activation of the global reset (set/reset in XC4000), and
the progression to the “finished” state F (see Figure 2)
should all occur as a result of one common byte input.
Under normal circumstances, the software achie v es this b y
manipulating the length-count value appropriately, taking
into account the additional bits between devices, and
adjusting for the fact that byte-wide interfaces always leave
the last bit sitting in the P-S converter, shifting it out at the
beginning of the next byte. These complexities, combined
with the many possible daisy-chain arrangements have
occasionally led to problems, where the device outputs go
active before the last required byte had been received. This
can lead to contention on the address outputs or data
inputs and might prevent the device from going DONE, or
reaching the real end of its configuration sequence. Not
reaching this “finished” state limits the use of readback and
boundary scan. A ne w Mak ebits option solves this prob lem:
Since XACT 5.0, the default option is “Length-Count
aligned” which adjusts the length-count value such that
length-count match occurs during the first bit in the last
configuration byte. This assures sufficient CCLK pluses to
complete any selected type of start-up sequence. The other
option is “DONE-aligned”, which adjusts length count value
to make DONE go active at the end of a configuration data
byte, which can cause problems in Peripheral mode.
Only Peripheral modes seem to be sensitive to the dif-
ference between these two options.
Miscellaneous Notes
CCLK is the most impor tant configuration signal. Once the
INIT output is High, each device counts every Low-to-High
transition of this configuration clock. In all modes except
Slave Serial and XC4000 Synchronous Peripheral, CCLK is
a very fast output that cannot be made slew-rate limited.
When distributing this clock, the user should pay special
attention to glitches, overshoots, and undershoots. In sev ere
cases, a 33 Ω resistor in series with the CCLK output might
improv e the signal integrity. In other cases , it might be better
to provide a pull-up resistor at the far end of the CCLK net.
Since the clock net has a transmission-line characteristic
impedance of always less than 100 Ω, the limited output
drive capability of the CCLK output precludes proper parallel
termination.
DOUT is an excellent observation point, since every de vice
must output the preamble on this pin, irrespective of the
selected configuration mode, and irrespective of the posi-
tion in, or the existence of, a daisy chain.
INIT of all XC4000 and XC3000 devices in a daisy chain
should be interconnected to prevent the configuration from
starting before all devices are ready. A 10 kΩ pull-up resis-
tor is recommended. The parallel INIT of the daisy-chained
devices must be connected to the INIT of the lead XC4000
device, or to the RESET input of the lead XC3000 device.
This is especially impor tant for re-configuration, where the
master does not have a four-times longer wait period.
The DONE output indicates the end of the configuration
process. In XC2000 and XC3000 systems, it makes sense
to ground DONE permanently. The RESET input then
becomes the reconfiguration input, and cannot be used as
the dedicated asynchronous user RESET input. LDC can
be used to indicate end of configuration.
PWRDWN (on XC2000 and XC3000 de vices) must be High
before and during the configuration process.
Don’t let PWRDWN float!
June 1, 1996 (Version 1.0) 14-33
Xilinx FPGAs can be configured in a common daisy-chain
structure, where the lead device generates CCLK pulses
and feeds serial configuration information into the next
downstream device, which in turn feeds data into the next
downstream device, etc. There is no limit to the number of
devices in a daisy chain, and XC2000, XC3000, XC4000,
and XC5200 series devices can be mixed freely with only
one constraint: the lead device must be a member of the
highest-order family used in the chain. (For the purposes of
this discussion, there is no difference betw een the XC4000
series and the XC5200 family, when XC5200 is used in any
configuration mode e xcept Express Mode). The lead de vice
must generate a sufficient number of CCLK pulses after
length-count-match was achieved, but XC3000-series
devices generate fewer CCLK pulses than XC4000-series
or XC5200-family devices require, and XC2000 devices
generate even fewer CCLK pulses after length-count
match. See Figure 1.
In a daisy-chain, all CCLK pins are interconnected, and
DOUT of any upstream device feeds the DIN input of its
downstream neighbor. Those are the basic connections.
For control purposes, it is advisable to interconnect all the
slave INIT pins (the XC2000 does not have this pin) and
connect them to the INIT pin of the lead XC4000/XC5200
device or the RESET input of the lead XC3000 device.
Interconnected INIT pins prevent the master from starting
the configuration process until all slaves are ready. For
power-up this is assured automatically, since the master
uses four times as man y internal clocks f or the power-up as
any sla ve does, but, when re-configuring, master and slav e
devices consume the same number of clocks to clear a
frame, and a f ast master might be ready bef ore a slow slav e
is. Interconnecting INITs solves this problem.
The DONE/PROG (D/P) and RESET pins (XC2000,
XC3000) and the XC4000/XC5200 PROGRAM pins can be
used in different ways, depending on the designer’s prefer-
ences regarding reconfiguration, pin utilization, and need
for a global RESET input.
If there is no need for a global logic RESET input, then it is
best to permanently ground the XC2000/3000 D/P pin,
which means that the RESET input functions as the Recon-
figure input, and should be connected to all XC4000/
XC5200
PROGRAM
inputs.
Configuring Mixed FPGA
Daisy Chains
June 1, 1996 (Version 1.0) Application Note by PETER ALFKE
XC4000/
XC5200
UCLK_SYNC
XC4000/
XC5200
UCLK_NOSYNC
XC4000/
XC5200
CCLK_SYNC
XC4000/
XC5200
CCLK_NOSYNC
XC3000
XC2000
CCLK
GSR Active
UCLK Period
DONE IN
DONE IN
Di Di+1 Di+2
Di Di+1 Di+2
U2 U3 U4
U2 U3 U4
U2 U3 U4C1
Synchronization
Uncertainty
Di Di+1
Di Di+1
DONE
I/O
GSR Active
DONE
I/O
GSR Active
DONE
C1 C2
C1 U2
C3 C4
C2 C3 C4
C2 C3 C4
I/O
GSR Active
DONE
I/O
DONE
Global Reset
I/O
DONE
Global Reset
I/O
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
CCLK Period
Length Count Match
F
F
F
F
F
F
X5972
C1, C2 or C3
Note: Thick lines are default option
Figure 1: Start-up Timing
Configuring Mixed FPGA Daisy Chains
14-34 June 1, 1996 (Version 1.0)
If there is a need for a global logic RESET input that can
reset all flip-flops in the user logic without causing reconfig-
uration, then external logic must combine RESET and D/P
in such a way, that pulling Low RESET does not affect D/P,
but pulling Low D/P also pulls down RESET. See Figure 2.
The following simple recommendations guarantee a well-
defined beginning for an y FPGA configuration or reconfigu-
ration process, after the initialization and clearing of the
configuration memory in all FPGAs has been completed,
and the address counter in the serial PROM(s) has been
reset.
The connections described below guarantee reliable oper-
ation ev en under adv erse operating conditions such as V CC
glitches.
The lead device can use any configuration mode available.
In all modes except Slav e Serial, its CCLK pin is the output
that clocks all other devices.
Obviously, all CCLK and XC1700 CLK pins must be inter-
connected, the DATA outputs from multiple XC1700 serial
PROMs must be interconnected and connected to the DIN
input of the lead device , and the daisy-chain must be estab-
lished by connecting each DOUT output to the do wnstream
DIN input.
The following recommendations assume that there are no
XC2000 devices in the daisy chain (they lack the INIT out-
put) and that, if Serial mode is chosen for the lead device,
the XC1700 device(s) store only one configuration for the
whole daisy chain. The serial PROM(s) must, therefore, be
reset before the daisy chain is to be (re)programmed.
There are three possible types of daisy chains using
XC3000 and XC4000/XC5200 devices. Here are the rec-
ommended connections for the configuration control pins.
Case 1:
Daisy chain consists of nothing but XC3000-series
devices:
Use lead device’s LDC to drive XC1700 CE.
Use lead device’s INIT to drive XC1700 RESET.
Interconnect all slave INITs and connect them to the lead
RESET
input.
Interconnect all DONE pins.
Interconnect all slave RESET inputs
Instigate Reprogram by pulling the slave RESET net Low
for at least 6 µs while all DONE pins are Low.
(DONE can be permanently wired Low, but that sacrifices
the use of RESET as a global reset of the user logic. If
DONE is not wired Low, reprogram must pull DONE Low
with an open-collector or open-drain driver).
Case 2:
Lead device is XC4000-series or XC5200 family, driving
any mixture of XC3000, XC4000 and XC5200 devices:
Use lead device’s LDC to drive XC1700 CE.
Use lead device’s INIT to drive XC1700 RESET.
Interconnect all INIT pins.
Interconnect all DONE pins.
Interconnect all XC4000/XC5200 PROGRAM inputs.
Interconnect all XC3000 RESET inputs.
Combine these two nets into one PROGRAM/RESET net
Instigate Reprogram by pulling the combined PROGRAM/
RESET Low.
Case 3:
Daisy chain consists of nothing but XC4000/ and
XC5200-type devices:
Use lead device’s LDC to drive XC1700 CE.
Use lead device’s INIT to drive XC1700 RESET.
Interconnect all INIT pins.
Interconnect all DONE pins (only required for UCLK-SYNC
option).
Interconnect all XC4000/XC5200 PROGRAM inputs.
Instigate Reprogram by pulling PROGRAM Low.
Configuration control pins are:
XC3000, XC3000A, XC3000L, XC3100, XC3100A:
DONE/PROGRAM (open-drain output/input)
RESET (input)
INIT (open-drain output)
XC4000 Series (XC4000, XC4000A, XC4000D,
XC4000E, XC4000EX, XC4000H) and XC5200-family:
DONE (open-drain output / input)
PROGRAM (input)
INIT
(open-drain output / input)
XC1700:
RESET (input with programmable polarity)
REPROGRAM
5 KΩ
5 KΩTo All D/P 
Wired Together
To All RESET, Except
Lead Device
To RESET of
Lead Device
GLOBAL
RESET
From All INIT
Pins Wired
Together
VCC
VCC
X5982
Figure 2:
June 1, 1996 (Version 1.0) 14-35
Summary
This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power-
supply glitches? Is there any danger of picking up erroneous data and configuration? What can be done to maintain
configuration during loss of primary power? What can be done to secure a design against illegal reverse-engineering?
Xilinx Families
XC2000, XC3000, XC4000, XC5200
Power-Up
Here is a detailed description of XC3000 Series, XC4000
Series and XC5200 device beha vior during supply ramp-up
and ramp-down.
When Vcc is first applied and is still below about 3 V, the
device w akes up in the pre-initialization mode . HDC is High;
INIT, LDC and DONE or DONE/PROG (D/P) are Low, and
all other outputs are 3-stated with a weak pull-up resistor.
When VCC has risen to a value abov e ~3 V, and a 1 and a 0
have been successfully written into two special cells in the
configuration memory, the initialization power-on time dela y
is started. This delay compensates for differences in VCC
detect threshold and internal CCLK oscillator frequency
between diff erent de vices in a daisy chain. The initialization
delay counts clock periods of an on-chip oscillator (CCLK)
which has a 3:1 frequency uncertainty depending on pro-
cessing, voltage and temperature. Time-out, therefore,
takes between 11 and 33 ms for a slave device, four times
longer for a master device.
This factor of four makes sure that even the fastest master
will always take longer than any slave. We assume that the
worst- case difference between 33 ms and 4 x 11 ms is
enough to compensate for the VCC rise time spent between
threshold differences (max 2 V) of devices in a daisy chain.
Only in cases of very slow VCC rise time (>25 ms), must the
user hold RESET Low until VCC has reached a proper le v el.
Interconnecting the INIT pins of all de vices in a daisy-chain
is a better method of synchronizing star t-up, but cannot be
used with XC2000 devices, since they lack an INIT pin.
After the end of the initialization time-out, each device
clears its configuration memory in a fraction of a millisec-
ond, then tests for inactive RESET or PROGRAM, stores
the MODE value and starts the configuration process, as
described in the Data Sheet. After the de vice is configured,
the 5-V VCC may dip to about 3.5 V without any significant
consequences beyond an increase in delays (circuit speed
is proportional to Vcc), and a reduction in output driv e. If Vcc
drops into the 3-V range, it triggers a sensor that f orces the
device back to the pre-initialization mode described above.
All flip-flops are reset, HDC goes High; INIT, LDC and D/P
or DONE go Low, and all other outputs are 3-stated with a
weak resistive pull-up. If VCC dips substantially lower, the
active outputs become weaker, but the device stays in this
preinitialization mode. When VCC rises again, a normal
configuration process is initiated, as described above.
Sensitivity to VCC Glitches
The user need not be concerned about power supply dips:
The XC3000/XC4000/XC5200 devices stay configured for
small dips and they are “smart enough” to reconfigure
themselves (if a master) or to ask for reconfiguration by
pulling INIT and D/P or DONE Low (if a sla ve). The devices
will not lock up; the user can initiate re-configuration at any
time just by pulling D/P or PR OGRAM Low or, if D/P is Low,
by forcing a High-to-Low transition on RESET.
Any digital logic de vice with internal data storage in latches
or flip-flops is sensitive to power glitches. This includes
every RAM, microprocessor, microcontroller, and periph-
eral circuit. Only purely combinatorial circuits can be guar-
anteed to survive a severe power glitch without any
problem.
Xilinx SRAM-based FPGAs store their configuration in
latches that lose their data when the supply voltage drops
below a critical value (which is substantially below 3 V for
the 5-V devices), but configuration data is extremely robust
and reliable while VCC stays above 3 V. All Xilinx configura-
tion latches are implemented as cross-coupled comple-
mentary inverters with active pull-down n-channel
transistors and active pull-up p-channel transistors. Both
High and Low logic levels have an impedance of less than
5kΩ with respect to their respective supply rail.
Typical SRAM memory devices use passive poly-silicon
pull-up resistors with an impedance of about 5,000 MΩ. A
current of one nanoamp (!) is sufficient to upset the typical
SRAM cell, whereas it takes a million times more current to
upset the Xilinx configuration latch.
Configuration Issues:
Power-up, V olatility , Security ,
Battery Back-up
June 1, 1996 (Version 1.0) Application Note by PETER ALFKE
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
14-36 June 1, 1996 (Version 1.0)
This does not mean that SRAMs are unreliable, it just
shows that the levels in Xilinx configuration latches are six
orders of magnitude more resistant to upsets caused by
external events, like cosmic rays or alpha particles. Xilinx
has never heard about any occurrence of a spontaneous
change in the configuration store in any of its ~50 million
FPGA devices sold over the past twelve years.
Whereas most digital circuits rely on Vcc staying within
specification, Xilinx FPGAs have an internal voltage moni-
toring circuit. For example, in the 5-Volt devices, whenever
the supply voltage dips below 3 V, the internal monitoring
circuit causes the Xilinx FPGA to stop normal operation. All
outputs go 3-state, and the device waits for the supply volt-
age to rise closer to 4 V, when it either demands (slave or
peripheral mode) or initiates (master mode) a reconfigura-
tion. In the range between 5.5 and 3 V, all typical CMOS
devices maintain their functionality and their data storage,
they just get slower as the voltage goes down.
Xilinx has made sure that the FPGA cannot be corrupted by
a power glitch. The most sensitive circuit is the low-voltage
detector . It kicks in while all other configur ation storage and
user logic is still guaranteed to be functional. The voltage-
monitoring feature in the Xilinx device can even be used to
protect other circuitry, or it can be coordinated with external
monitoring circuits.
There is no possibility of a VCC dip causing the device to
malfunction, i.e., to operate with erroneous configuration
information.
• If VCC stays above the trip point, the device functions
normally, albeit at reduced speed, like any other CMOS
device.
• If VCC dips below the trip point, the device 3-states all
outputs and waits for reconfiguration.
Xilinx production-tests the VCC-dip tolerance of all XC3000
devices in the following way.
After the device is configured, VCC is reduced to 3.5 V, and
then raised back to 5.0 V. Configuration data is then read
back and compared against the original configuration bit
stream. Any discrepancy results in rejection of the device.
Subsequently, VCC is reduced to 1.5 V and then raised to
5.0 V. The device must first go 3-state, then respond with a
request for reconfiguration.
Both these tests are performed at high temperature (>85 °C
for commercial parts, >100°C for military). Any part failing
any of these tests is rejected as a functional failure.
As a result of these careful precautions, we contend that
Xilinx FPGAs are safer than all other types of circuitry
(except purely combinatorial circuits). A microprocessor
can loose the content of its address register, its accumula-
tor or other control register due to an undetected power
glitch, with disastrous consequences to the subsequent
operation. A Xilinx FPGA detects the power glitch and
always plays it safe by flagging the problem.
No complex system of any kind can function reliably when
Vcc is unreliable . Xilinx FPGAs do the safest thing possib le ,
whenever such problems occur.
Design Security
Some Xilinx customers are concerned about the security of
their designs. How can they protect their designs against
unauthorized copying or reverse-engineering?
We must distinguish between two very different situations:
• Configuration data in accessible from a serial or parallel
EPROM or in a microprocessor's memory. This is the
normal case.
• Configuration data is hidden from the user, since the
design does not permanently store a source of
configuration data. After the FPGA was configured, the
EPROM or other source w as remov ed from the system,
and configuration is kept alive in the FPGA through
battery-back-up.
Design Security when Configuration Data is
Accessible
In the first case, it is ob viously very easy to make an identi-
cal replica of the design by copying the configuration data
and the pc-board interconnect pattern of the standard
devices, but it is virtually impossible to interpret the bit-
stream in order to understand the design or make intelligent
modifications to it. Xilinx keeps the inter pretation of the bit-
stream a closely guarded secret. Reverse-engineering an
FPGA would require an enormously tedious analysis of
each individual configuration bit, which would still only gen-
erate an XACT view of the FPGA, not a usable schematic.
The best protection against a mindless copy is legal. The
bitstream is easily protected by copyright laws that have
proven to be more successfully enforced than the intellec-
tual property rights of circuit designs.
The combination of copyright protection, and the almost
insurmountable difficulty of creating any design v ariation for
the intended function, provides good design security. The
recent successes of small companies in reverse-engineer-
ing microprocessors and microprocessor support circuits
show that a non-programmable device can actually be
more vulnerable than an FPGA. For advice on legal protec-
tion of the configuration bitstream, see the following para-
graphs.
June 1, 1996 (Version 1.0) 14-37
Design Security by Hiding the
Configuration Data
If the design does not contain the source of configuration
data, but relies on battery-back-up of the FPGA configura-
tion, then there is no conceivable way of copying this
design. Opening up the package and probing thousands of
latches in undocumented positions to read out their data
without ever disturbing the configuration is impossible.
This mode of operation off ers the ultimate design security . It
is being used by sev er al Xilinx customers who ha v e reason
to be concerned about illegal pirating of their designs.
Battery Back-up and Powerdown
Since SRAM-based FPGAs are manufactured using a
high-performance low-po wer CMOS process , they can pre-
serve the configuration data stored in the internal static
memory cells even during a loss of primar y power. This is
accomplished by forcing the device into a low-power non-
operational state, while supplying the minimal current
requirement of VCC from a battery.
Circuit techniques used in XC3100, XC4000 and XC5200
devices pre v ent ICC from being reduced to the le v el needed
for battery back-up. Consequently, battery back-up should
only be used for XC2000, XC2000L, XC3000, XC3000A
and XC3000L devices.
There are two primary considerations for battery backup
which must be accomplished by external circuits.
• Control of the Power-Down (PWRDWN) pin
• Switching between the primary VCC supply and the
battery.
Important considerations include the following.
• Insure that PWRD WN is asserted logic Low prior to VCC
falling, is held Lo w while the primary V CC is absent, and
returned High after VCC has returned to a normal level.
PWRDWN edges must not rise or fall slowly.
• Insure “glitch-free” switching of the power connections
to the FPGA device from the primary VCC to the battery
and back.
• Insure that, during normal operation, the FPGA VCC is
maintained at an acceptable le v el, 5.0 V ± 5% (±10% f or
Industrial and Military).
Figure 1 shows a power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2 V primary sup-
ply or a 3 V Lithium battery. A Seiko S8054 3-terminal
power monitor circuit monitors VCC and pulls PWRDWN
Low whenever VCC falls below 4 V.
Legal Protection of Configuration Bit-Stream Pr ograms
The bit-stream program loaded into the FPGA may
qualify as a “computer program” as defined in Section
101, Title 17 of the United States Code, and as such
may be protectab le under the cop yright law. It ma y also
be protectable as a trade secret if it is identified as
such. We suggest that a user wishing to claim copy-
right and/or trade secret protection in the bit stream
program consider taking the following steps.
Place an appropriate copyright notice on the FPGA
device or adjacent to it on the PC board to give notice
to third parties of the copyright. For example, because
of space limitations, this notice on the FPGA device
could read “©1996 XYZ Company” or, if on the PC
board, could read “Bit Stream ©)1996 XYZ Company”.
File an application to register the copyright claim for the
bit-stream program with the U.S. Copyright Office.
If practicable, given the size of the PC board, notice
should also be given that the user is claiming that the
bit- stream program is the user's trade secret. A state-
ment could be added to the PC board such as: “Bit-
stream proprietary to XYZ Company. Copying or other
use of the bitstream program except as expressly au-
thorized by XYZ Company is prohibited.”
To the extent that documentation, data books, or other
literature accompanies the FPGA-based design, appro-
priate wording should be added to this literature provid-
ing third parties with notice of the user's claim of
copyright and trade secret in the bit-stream program.
For example, this notice could read: “Bit-Stream©)1996
XYZ Company. All rights reserved. The bit-stream pro-
gram is proprietary to XYZ Company and copying or
other use of the bit- stream program except as express-
ly authorized by XYZ Company is expressly prohibited.”
To help prove unauthorized copying by a third party, ad-
ditional nonfunctional code should be included at the
end of the bit-stream program. Therefore, should a third
party copy the bit-stream program without proper autho-
rization, if the non-functional code is present in the
copy, the copier cannot claim that the bit-stream pro-
gram was independently developed.
These are only suggestions, and Xilinx makes no rep-
resentations or warranties with respect to the legal
effect or consequences of the above suggestions.
Each user is advised to consult legal counsel with
respect to seeking protection of a bit-stream program
and to determine the applicability of these suggestions
to the specific circumstances.
If the user has any questions, contact the Xilinx legal
department at 408-879-4984.
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
14-38 June 1, 1996 (Version 1.0)
Powerdown Operation
A Low level on the PWRDWN input, while VCC remains
higher than 2.3 V, stops all internal activity, thus reducing
ICC to a very low level:
• All internal pull-ups (on Long lines as well as on the I/O
pads) are turned off.
• The crystal oscillator is turned off
• All package outputs are three-stated.
• All package inputs ignore the actual input level, and
present a High to the internal logic.
• All internal flip-flops or latches are permanently reset.
• The internal configuration is retained.
• When PWRDWN is returned High, after VCC is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and D/P as at the
completion of configuration.
Things to Remember:
Powerdown retains the configuration, but loses all data
stored in the device. Powerdown three-states all outputs
and ignores all inputs. No clock signal will be recognized,
and the crystal oscillator is stopped. All internal flip- flops
and latches are permanently reset and all inputs are inter-
preted as High, but the internal combinatorial logic is fully
functional.
Things to Watch Out for:
Make sure that the combination of all inputs High and all
internal flip-flop outputs Low in your design will not gener-
ate internal oscillations or create permanent bus contention
by activating internal bus drivers with conflicting data onto
the same long line. These two situations are farfetched, but
they are possib le and will result in consider ab le po w er con-
sumption. It is quite easy to sim ulate these conditions since
all inputs are stable and the internal logic is entirely combi-
natorial, unless latches have been made out of function
generators.
During powerdown, the VCC monitoring circuit is disabled. It
is then up to the user to prev ent VCC dips below 2.3 V, which
would corrupt the stored configuration.
During configuration, the PWRDWN pin must be High,
since configuration uses the internal oscillator. Whenever
VCC goes below 4 V, PWRDWN must already be Low in
order to prevent automatic reconfiguration at low VCC. F o r
the same reason, VCC m ust first be restored to 4 V or more ,
before PWRDWN can be made High.
PWRDWN has no pull-up resistor. A pull-up resistor would
draw supply current when the pin is Low, which would
defeat the idea of powerdown, where ICC is only microam-
peres.
FPGA
SEIKO
S 8054
3
21 PWRDWN
VCC
IN5817 IN5817
B35
Lithium
Battery
X5997
VCC
Seiko S8054 Specifications
Detect Voltage
4.305 V max
208 mV typ
0.52 mV/°C
2.6 µA typ
3.995 V min
Hysteresis
Temp. Coeff.
ICC @ + 6V
Figure 1: Battery Back-up Circuit
June 1, 1996 (Version 1.0) 14-39
All Xilinx SRAM-based FPGAs can be in-system config-
ured and re-configured an unlimited number of times. The
XC6200 family has additional f eatures that allow partial and
very fast (re-)configur ation from a microprocessor b us . See
the XC62000 product documentation for details.
This application note describes the procedures for reconfig-
uring the more traditional Xilinx FPGAs of the XC2000,
XC3000, XC3100, XC4000, and XC5200 families.
All configuration information is stored in latches that are
loaded serially, conceptually like a shift register. There are
sev eral diff erent bit-serial or byte-parallel configuration data
interfaces, selected by logic levels on three mode inputs,
but – with the exception of the XC5200 Express mode –
they all result in the bit-serial loading of the configuration
latches. The byte-parallel interfaces in Master Parallel and
Peripheral modes act just as an 8-bit parallel-to-serial con-
verter. Between devices in a daisy-chain, the configuration
information is transmitted bit-serially with a common Con-
figuration Clock (CCLK). In Master and Peripheral modes,
CCLK is generated by the lead FPGA device, in Slave
Serial mode, CCLK comes from an external source.
Reconfiguration of an operational device, or a daisy-chain
of devices, goes through the following sequence of events:
• Reconfiguration is initiated by pulling a specific device
pin Low.
• First, all outputs are 3-stated, except HDC = High, LDC
and DONE = Low
• Then, all internal registers, flip-flops and latches, as
well as the configuration storage latches are cleared.
During this time, the INIT output is being pulled Low.
• Then, the Mode inputs and RESET or PROGRAM
inputs are sampled to determine the selected
configuration mode and whether to start the new
configuration process, or to wait.
• Then configuration data is accepted and loaded into the
internal latches and distributed through the daisy-chain.
• When all configuration information has been entered,
the user outputs are activated, DONE goes High and
the internal reset is released, all in the order specified in
the configuration bitstream. All devices in a daisy-chain
perform each of these operations in synchronism.
Important Considerations
• Reconfiguration is “all or nothing”. There is no way to
restrict reconfiguration to a part of the chip (Note that
XC6200 devices do not have this limitation).
• Reconfiguration takes a specific time, determined only
by device type, size and clock speed, independent of
the particular configuration pattern. Configuration takes
from tens to hundreds of milliseconds. During that time,
all user-outputs of the device, or the whole daisy-chain
of devices, are 3-stated with weak internal pull-ups,
except for HDC and LDC, which are active High or Low
respectively.
• All user-data stored in registers, flip-flops or latches is
erased. There is no way to retain data inside the device
from one configuration to the next.
These limitations are absolute. If they are not acceptable,
the user must resort to creative solutions, like piggy-back-
ing multiple devices.
The designer of reconfigurable applications should be
familiar with the normal configuration process of each
device, as described in the individual product descriptions.
There is also pertinent information about daisy-chain oper-
ation, especially about mixed daisy chains, on previous
pages.
Interconnecting the INIT pins of all de vices in a daisy-chain
is mandatory for reconfiguration, since this is the only way
to guarantee that the master de vice does wait f or the rest of
the daisy-chain to be cleared, before starting the reconfigu-
ration. Only the first configuration after power-up mak es the
master device spend four times as many clock periods as
any sla v e during the initial clear operation, so that the mas-
ter cannot possibly get ahead of the slaves. Reconfigura-
tion, however, does not slow down the master this way, so
the interconnection of all INIT pins must serve that same
purpose.
Note that the XC2000-family devices do not have an INIT
pin.
In Master Serial mode, it is highly recommended that the
active Lo w le v el of INIT be used to reset the XC1700-f amily
Serial PROM.
Dynamic Reconfiguration
June 1, 1996 (Version 1.0) Application Note By PETER ALFKE
Dynamic Reconfiguration
14-40 June 1, 1996 (Version 1.0)
Reconfiguration Time
Reconfiguration time is usually more critical than the origi-
nal power-on configuration time, which is often masked by
the general power-on delays.
Here are some suggestions to reduce reconfiguration time.
• A daisy-chain is obviously not conducive to fast
configuration, it should be broken up into shorter blocks ,
perhaps single devices. Multiple devices can be
configured in parallel, but can still use a common
CCLK, and can also be made to start up together. If the
devices differ in size or family, they should all be given
the same length count as the largest device in the
group.
• Configuration Mode
Parallel and Peripheral modes are not any faster than
Master Serial mode, since all modes (with the exception
of XC4000EX and XC5200 Express mode) internally
operate on serial data. The internally generated CCLK
frequency is guard-banded to nev er approach the upper
limit of what the device can tolerate. Therefore, the fast-
est possible configuration mode for XC3000 and
XC4000-series devices is Sla v e Serial, with an e xternal
well-controlled source for CCLK. Its frequency can be
up to 10 MHz for all 5-V devices, and there are ways to
increase the average clock rate well beyond that, but
they require dynamic clock frequency changes and an
intimate understanding of the configuration frame struc-
ture.
At 10 MHz, configuration time per device ranges from
1.5 ms for the XC3020A to 42 ms for the XC4025E and
143 ms for the XC4062EX.
• Possible Contention Problems:
Certain user outputs become active during the configu-
ration process:
Address outputs during Master Parallel mode, Chip
Select and Ready/Busy during Peripheral modes.
The designer must make sure that these active outputs
do not cause contention with other logic that might use
the same pins as device inputs.
Initiating Reconfiguration in
Different Xilinx Device Families
XC2000 and XC3000 Series
There are three alternatives:
1. Pull RESET Low while DONE is permanently grounded
externally.
This is the simplest scheme, but it precludes the use of
RESET to clear the flip-flops and latches in the operating
user-design. RESET must be pulled Low for more than six
microseconds to overcome its internal low-pass filtering.
Configuration starts when RESET has gone High again.
2. Pull DONE Low with an open-drain (“open-collector”)
output. This assumes that DONE was High, i.e. that the
previous configuration was successful. Reconfiguration
starts as soon as the internal memory has been cleared.
DONE can be released anytime.
3. Pull DONE Low with an open-drain (“open-collector”)
output and pull RESET Low. Keep RESET Low for at least
six microseconds while DONE is Low. DONE can be
released anytime after that, or not released at all. See alter-
native 1.
XC4000 Series and XC5200 Family
Pull the PROGRAM input Lo w for at least 0.3 microseconds
to initiate clearing the configuration memory, then pull
PROGRAM up to start the new configuration process.
While PROGRAM is held Lo w , a Low le vel on INIT indicates
that the device is continuously clearing the configuration
memory. When PROGRAM has been pulled up, INIT stays
Low during one more clear operation, then goes High.
All device f amilies , e xcept the original XC4000, hav e a con-
tinuously active pull-up resistor on the PROGRAM pin.
June 1, 1996 (Version 2.0) 14-41
Whenever a clocked flip-flop synchronizes an asynchro-
nous input, there is a small probability that the flip-flop out-
put will exhibit an unpredictable delay. This happens when
the input transition not only violates the setup and hold-time
specifications, b ut actually occurs within the tiny timing win-
dow where the flip-flop accepts the new input. Under these
circumstances, the flip-flop can enter a symmetrically bal-
anced transitory state, called metastable (meta = between).
While the slightest deviation from perfect balance will
cause the output to rev ert to one of its two stable states, the
delay in doing so depends not only on the gain-bandwidth
product of the circuit, but also on how perfect the balance
is, and on the noise level within the circuit; the delay can,
therefore, only be described in statistical terms.
The problem for the system designer is not the illegal logic
level in the balanced state (it's easy enough to translate
that to either a 0 or a 1), but the unpredictable timing of the
final change to a valid logic state. If the metastable flip-flop
drives two destinations with differing path delays, one des-
tination might clock in the final data state while the other
does not.
With the help of a self-contained circuit, Xilinx ev aluated the
XC4000 and XC3000-series flip-flops. The result of this
evaluation shows the Xilinx flip-flop to be superior in meta-
stable perf ormance to many popular MSI and PLD de vices .
Since metastability can only be measured statistically, this
data was obtained by configuring several different Xilinx
FPGAs with a detector circuit shown in Figure 1. The flip-
flop under test receives the asynchronous ~1-MHz signal
on its D input, and is clocked by a much higher manually
adjustable frequency. The output QA feeds two flip-flops in
parallel, one (QB) being clocked by the same clock edge,
the other (QC) being clocked by the opposite clock edge.
When clocked at a low frequency, each input change gets
captured by the rising clock edge and appears first on QA,
then, after the falling clock edge, on QC, and finally, after
the subsequent rising clock edge, on QB.
If a metastable event in the first flip-flop increases the set-
tling time on QA so much that QC misses the change, but
QB still captures it on the next rising clock edge, this error
can be detected by feeding the XOR of QB and QC into a
falling-edge triggered flip-flop. Its output (QD) is normally
Metastable Recovery
June 1, 1996 (Version 2.0) Application Note By PETER ALFKE and BRIAN PHILOFSKY
Q
D16-Bit
Counter
16 LEDs
D
A
QB
QC
Q
DD D
Clock
Q
Q
Q
Clock
NO ERROR
ERROR
NO ERROR
ERROR
Asynchr, Input
Asynchr, Input
A
B
C
QD
X5985
Figure 1: Test Circuit and Timing Diagram
Metastable Recovery
14-42 June 1, 1996 (Version 2.0)
Low , b ut goes High for one cloc k period each time the asyn-
chronous input transition caused such a metastable delay
in QA. The frequency of metastable events can be
observed with a 16-bit counter driven by QD.
By changing the clock frequency, and thus the clock half-
period, the amount of acceptable metastable delay on the
QA output can be varied, and the resulting frequency of
metastable e vents can be observed on the counter outputs.
As expected, no metastable events were observed at clock
rates below 70 MHz for the XC4005-6, or below 100 MHz
for the XC4005E-3, since a half clock period at those fre-
quencies is adequate for almost any metastability-resolu-
tion delay. Increasing the clock rate slightly brought a
sudden burst of metastable events. Careful adjustment of
the clock frequency gave repeatable, reliable measure-
ments.
Metastability Measurements
The circuit of Figure 1 was implemented in f our different Xil-
inx devices: two cutting-edge devices using 0.5 micron, 3-
layer-metal technology, the XC4005E-3 and the XC3142A-
09, and, for comparison purposes, also in two older-tech-
nology devices, the XC4005-6 and the XC3042-70.
In each device two different implementations put QA, the
flip-flop under test, into an IOB and a CLB. The XC4000-
series devices showed little difference between IOB and
CLB behavior, but in the XC3000-series devices, the IOB
flip-flops showed dramatically better metastable perfor-
mance than the CLB flip-flops. This difference can be
traced to subtle diff erences in circuit design and la yout, and
will guide us to fur ther improvements in metastable perfor-
mance in future designs.
Metastable measurement results are listed in Table 1, and
are plotted in Figure 2. The results f or XC4000E-3 (IOB and
CLB) and for XC3100A-09 IOB flip-flops are outstanding,
far superior to most metastable data published anywhere
else. When granted 2 or 3 ns of extra settling delay, these
devices come close to eliminating the problems caused by
metastability, since their MTBF exceeds millions of years.
The older-technology devices are obviously less impres-
sive , b ut the y still show acceptab le performance, especially
in the IOB input flip-flops that are normally used to synchro-
nize asynchronous input signals.
Table 1 lists the experimental results from which the expo-
nential factor K2 was derived. The clock frequency was
adjusted manually, while obser ving the LSB and the MSB
of the 16-bit error counter. FL is the clock frequency that
generated a ~1 Hz error rate, FH generated a ~64,000 Hz
error rate.
K2 is derived by dividing ln 64,000 by the half-period differ-
ence.
Metastability Calculations
The Mean Time Between Failures (MTBF) can only be
defined statistically. It is inversely proportional to the prod-
uct of the two frequencies inv olv es, the clock frequency and
the average frequency of the asynchronous data changes,
provided that these two frequencies are independent and
have no correlation.
The generally accepted equation for MTBF is
K1 represents the metastability-catching set-up time win-
dow, which describes the likelihood of going metastable.
K2 is an exponent that describes the speed with which the
metastable condition is being resolved. K2 is an indication
of the gain-bandwidth product in the feedback path of the
master latch of the master-slave flip-flop. A small increase
in K2 results in an enormous improvement in MTBF.
With F1 = 1 MHz, F2 = 10 MHz and K1 = 0.1 ns = 10-10 s,
MTBF (in seconds) = 10–3 * eK2*t
Experimentally derived (see Table 1):
K2 = 16.1 per ns, for the XC4005E-3 IOB flip-flops
K2 = 19.4 per ns, for the XC4005E-3 CLB flip-flops
K2 = 8.5 per ns, for the XC4005-6 IOB flip-flops
K2 = 7.9 per ns, for the XC4005-6 CLB flip-flops
K2 = 12.7 per ns, for the XC3142A-09 IOB flip-flops
K2 = 4.8 per ns, for the XC3142A-09 CLB flip-flops
K2 = 4.2 per ns, for the XC3042-70 IOB flip-flops
K2 = 2.6 per ns, for the XC3042-70 CLB flip-flops
Table 1: Metastable Measurement Results
Device FL
(MHz) FH
(MHz) Half-period
Difference (ns) K2
(1/ ns)
XC4005E-3 IOB 111.5 131.6 0.685 16.1
XC4005E-3 CLB 109.0 124.4 0.568 19.4
XC4005-6 IOB 73.0 90.0 1.294 8.5
XC4005-6 CLB 71.2 88.8 1.392 7.9
XC3142A-09 IOB 152.2 206.6 0.87 12.7
XC3142A-09 CLB 107.4 211.3 2.29 4.8
XC3042-70 IOB 46.6 61.5 2.60 4.2
XC3042-70 CLB 41.9 64.8 4.22 2.6
MTBF = eK2 * t
F1 * F2 * K1
June 1, 1996 (Version 2.0) 14-43
For other oper ating conditions , divide MTBF by the product
of the two frequencies. For a ~10 MHz asynchronous input
synchronized by a 40 MHz clock, the MTBF is 40 times
shorter than plotted; f or a ~50 kHz signal synchronized b y a
1 MHz clock, the MTBF is 200 times longer than plotted
here.
1 2 3 4 5 6
0
1
-1
-2
-3
2
3
4
5
6
7
8
9
10
11
12
13 1M Years
1,000 Years
1 Year
XC4005E-3
CLB
XC4005E-3
IOB
XC3142A-09
IOB XC4005-6
IOB
XC4005-6
CLB
XC3142A-09
CLB
XC3042-70
IOB
XC3042-70
CLB
1 Day
1 Hour
1 Minute
Acceptable Extra Delay (ns)
Log Seconds
MTBF
X5986
Figure 2: Mean Time Between Failure for various IOB and CLB flip-flop outputs when synchronizing a ~1 MHz
asynchronous input with a 10 MHz clock.
Metastable Recovery
14-44 June 1, 1996 (Version 2.0)
June 1, 1996 (Version 1.0) 14-45
Beware of hold-time problems, because they can lead to
unreliable , temperature-sensitiv e designs that can fail even
at low clock rates.
“Set-up time” and “hold time” describe the timing require-
ments on the data input of a flip-flop or register with respect
to the clock input. The set-up and hold times describe a
window of time during which data must be stable in order to
guarantee predictable performance over the full range of
operating conditions and manufacturing tolerances.
A positive set-up time describes the length of time that the
data must be available and stable before the active clock
edge. A positive hold time, on the other hand, describes the
length of time that the data to be clocked into the flip-flop
must remain available and stable after the active clock
edge. A positive set-up time limits the maximum clock rate
of a system, but a positiv e hold time can cause malfunction
at any clock rate. Thus, chip designers and system design-
ers strive to eliminate hold-time requirements.
The IC design usually guarantees that any individual flip-
flop does not require a positive hold time with respect to the
clock signal at this flip-flop.
Hold-time requirements between flip-flops or registers on
the same chip can be avoided by careful design of the on-
chip clock distribution netw ork. If the worst-case clock-sk ew
value is shorter than the sum of minimum clock-to-Q plus
minimum interconnect delays, there is never any on-chip
hold-time problem.
It is, how e v er, far more difficult to a v oid a hold time prob lem
in the device input flip-flops , with respect to the device cloc k
input pin. When specifying the data pin-to-clock pin set-up
and hold times, the chip-internal clock distribution delay
must be taken into consideration. It effectively moves the
timing window to the right (see figure), thus subtracting
from the specified internal set-up time (which is good), but
adding to the hold time (which is very bad). If the clock dis-
tribution dela y is any longer than the data input delay – and
it easily might be – the device data input has a hold-time
requirement with respect to the clock input.
This means that the data source, usually another IC driven
by the same cloc k, must guarantee to maintain data bey ond
the clock edge. In other words, the data source is not
allowed to be very fast. If it is, the receiver might errone-
ously input the new data instead of the data created by the
previous clock, as it should. This is called a race condition,
and can be a fatal system failure.
If the receiving device has a hold time requirement, the
source of data must guarantee an equivalent minimum
value for its clock-to-output delay. Almost no IC manufac-
turer is willing to do this, and in the few cases where it is
done, the minimum value is usually a token 1 ns. Any input
hold time requirement is, therefore, an invitation to system
failure. Any clock distribution skew on the PC-board can
compound this issue and wipe out even the specified short
minimum delay.
Xilinx has addressed this problem by adding a deliberate
delay to every FPGA data input. In XC3000, and XC3100
FPGAs, this delay is fixed and always present; in XC4000
and XC5200 FPGAs, this delay is optional, and its value is
tailored to the clock distribution dela y (i.e . it is larger for big-
ger devices). As a result we can claim that no Xilinx FPGA
Data input has a hold-time problem (i.e., none has a posi-
tive hold time with respect to the exter nally applied clock),
when the design uses the internal global clock distribution
network (and, in XC4000 and XC5200, uses the delayed
input option). Most competitiv e de vices do not off er this fea-
ture.
Set-up and Hold Times
June 1, 1996 (Version 1.0) Application Brief By PETER ALFKE
External Clock
Internal Clock
Conventional Input Pin
Set-up and Hold Time SET-UP
Internal Clock Delay
Input Pin Set-up 
Time With Delay SET-UP
X5971
H
Set-up and Hold Times
14-46 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 1.0) 14-47
The “Absolute Maximum Ratings” table in the Xilinx Data
Book restricts the signal-pin voltage to a maximum 500 mV
excursion abo v e VCC and below g round. The reason for this
tight specification is to prevent uncontrolled current in the
input-clamping ESD-protection diodes. Such tight specifi-
cations are common in the industry; some manufacturers
limit the excursion to 300 mV.
This specification seems to be clean and simple, but it is
violated in almost every practical design. When users put
modern CMOS devices on PC boards, and interconnect
them with unterminated traces, there are reflections, com-
monly called “ringing”, that cause overshoots and under-
shoots of substantial amplitude (2 V and more). The recent
migration to smaller device geometries has made the IC
outputs even faster and increased the slew-rate, causing
more reflections even on short PC-board traces.
Fortunately, this problem has an easy solution:
The concern is not the input voltage, but rather the current
through the input protection diode and other input struc-
tures. Excessive current can cause latch-up if it exceeds
hundreds of milliamps AND if it lasts for microseconds
(shorter duration current spikes do not activate the SCR-
like latch-up mechanism).
PC-board reflections, on the other hand, usually have a
short duration of just a few nanoseconds, and have an
impedance of 40 to 100 Ω, which makes them incapable of
causing latch-up. They don’t drive enough current and they
don’t last long enough to cause any harm.
Here is the new Xilinx specification:
“Maximum DC overshoot or undershoot above VCC or
below GND must be limited to either 0.5 V or 10 mA, which-
ev er is easier to achieve. During transitions, the device pins
may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, pro-
vided this over- or undershoot lasts less than 20 ns”.
Overshoot and Undershoot
June 1, 1996 (Version 1.0) Application Brief By PETER ALFKE
Overshoot and Undershoot
14-48 June 1, 1996 (Version 1.0)
June 1, 1996 (Version 2.0) 14-49
Summary
XC4000 and XC5000 Series FPGA devices contain boundary-scan facilities that are compatib le with IEEE Standard 1149.1.
This Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA
design.
Xilinx Family
XC4000 Series, XC5200
Demonstrates
Boundary Scan
Introduction
In production, boards must be tested to assure the integrity
of the components and the interconnections. However, as
integrated circuits have become more complex and multi-
layer PC-boards have become more dense, it has become
increasingly difficult to test assembled boards.
Originally, manufacturers used functional tests, applying
input stimuli to the input connectors of the board, and
observing the results at the output. Later, “bed-of-nails”
testing became popular, where a customized fixture
presses sharp, nail-like stimulus- and test-probes into the
exposed traces on the board. These probes were used to
force signals onto the traces and observe the response.
However, increasingly dense multi-layer PC boards with
ICs surface-mounted on both sides have stretched the
capability of bed-of-nail testing to its limit, and the industry
is forced to look for a better solution. Boundary-scan tech-
niques provide that solution.
The inclusion of boundary-scan registers in ICs greatly
improves the testability of boards. Boundar y scan provides
a mechanism for testing component I/Os and inter-connec-
tions, while requiring as few as four additional pins and a
minimum of additional logic in each IC. Component testing
may also be supported in ICs with self-test capability.
Devices containing boundary scan have the capability of
driving or obser ving the logic levels on I/O pins. To test the
external interconnect, devices drive values onto their out-
puts and observe input values receiv ed from other devices.
A central test controller compares the received data with
expected results. Data to be driven onto outputs is distrib-
uted through a chain of shift registers, and observed input
data is returned through the same shift-register path.
Data is passed serially from one device to the next, thus
forming a boundary-scan path or loop that originates at the
test controller and returns there. Any device can be tempo-
rarily removed from the boundary-scan path by bypassing
its internal shift registers, and passing the serial data
directly to the next device.
XC4000/XC5000 FPGA devices contain boundary-scan
registers that are compatible with the IEEE Standard
1149.1, that was derived from a proposal by the Joint Test
Action Group (JTAG). Exter nal (I/O and interconnect) test-
ing is supported; there is also limited support for internal
self-test.
Overview of XC4000/XC5000
Boundary-Scan Features
XC4000/XC5000 devices support all the mandatory bound-
ary-scan instructions specified in the IEEE Standard
1149.1. A Test Access Port (TAP) and registers are pro-
vided that implement the EXTEST, SAMPLE/PRELOAD
and BYPASS instructions. The TAP can also support two
USERCODE instructions.
Note: If boundary scan is not used after the device is con-
figured, the user can use the special boundary scan pads
as input or output pins. And like the regular IOBs, these
input and output pins hav e pullups and pulldowns a vailab le.
The TDI, TMS, and TCK pads can be used as input pads.
The TDO pad can be used as an output pad.
Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
even after configuration affords tremendous flexibility for
interconnect testing.
Additionally, internal signals can be captured during
EXTEST by connecting them to unbonded IOBs, or to the
unused outputs in IOBs used as unidirectional input pins.
This partially compensates for the lack of INTEST support.
Boundary Scan in XC4000 and
XC5000 Series Devices
June 1, 1996 (Version 2.0)
Boundary Scan in XC4000 and XC5000 Series Devices
14-50 June 1, 1996 (Version 2.0)
The public boundary-scan instructions are always a v ailab le
prior to configuration. After configur ation, the public instruc-
tions and any USERCODE instructions are only av ailable if
specified in the design. While SAMPLE and BYPASS are
available during configuration, it is recommended that
boundary-scan operations not be performed during this
transitory period.
In addition to the test instructions outlined above, the
boundary-scan circuitr y can also be used to configure the
FPGA device, and readback the configuration data.
The following description assumes that the reader is famil-
iar with boundary-scan testing and the IEEE Standard.
Only issues specific to the XC4000/XC5000 implementa-
tion are discussed in detail. For general information on
boundary scan, please refer to the bibliography.
Deviations from the IEEE Standard
The XC4000/XC5000 boundary scan implementation devi-
ates from the IEEE standard in that three dedicated pins
(CCLK, PROGRAM and DONE) are not scanned.
It should also be noted that the Test Data Register contains
three Xilinx test bits (BSCANT.UPD, TDO.O and TDO.T)
and that bits of the register may correspond to unbonded or
unused pins.
Additionally, the EXTEST instr uction incor porates INTEST-
like functionality that is not specified in the standard, and
system clock inputs are not disabled during EXTEST, as
recommended in the standard.
The TAP pins (TMS, TCK, TDI and TDO) are scanned, but
connections to the TAP controller are made before the
boundary-scan logic. Consequently, the operation of the
TAP controller cannot be affected by boundary-scan test
data.
When the TAP is in the shift-DR state the contents of all
data registers are shifted; if y ou are in the middle of shifting
out data from the data register in a XC4000, complete shift-
ing out of all data first, before switching to the instruction or
bypass register.
1
X2680
TEST-LOGIC-RESET
0RUN-TEST/IDLE 1
SELECT-DR-SCAN
0
1
0
CAPTURE-DR CAPTURE-IR
0
1
0
0
SHIFT-DR SHIFT-IR
1
0
1
0
EXIT1-DR EXIT1-IR
0
1
0
PAUSE-DR PAUSE-IR
1
0
1
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
1
UPDATE-IR
1SELECT-IR-SCAN
0 1 0
00
1
1
0
NOTE: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
Figure 1: State Diagram for the TAP Controller
June 1, 1996 (Version 2.0) 14-51
Boundary-Scan Hardware
Description
Test Access Port
The boundary-scan logic is accessed through the Test
Access Port (TAP), which comprises four semi-dedicated
pins: Test Mode Select (TMS), Test Clock (TCK), Test Data
Input (TDI) and Test Data Output (TDO), as defined in the
IEEE specification.
The TAP pins are permanently connected to the boundary-
scan circuitry. However, once the device is configured, the
connections may be ignored unless the use of boundary
scan is specified in the design (See “Using Boundary
Scan”).
If the use of boundary scan is specified, the TAP input pins
(TMS, TCK and TDI) may still be shared with other logic,
subject to limitations imposed by external connections and
the operation of the TAP Controller. In designs that do not
use boundary scan after configuration, the TAP pins can be
used as inputs or outputs from the user logic in the FPGA
device. TMS, TCK and TDI are available as unrestricted
I/Os, while TDO only provides a 3-state output.
TAP Controller
The TAP Controller is a 16-state state machine that con-
trols the operation of the boundary-scan circuitry in
response to TMS. This state machine implements the state
diagram specified by the IEEE standard (Figure 1) and is
clocked by TCK.
Upon power-on, or if the boundary scan logic is not used in
the application, the TAP controller is forced into the Test-
Logic-Reset state. After configuration, the controller
remains disabled, unless its use is e xplicitly specified in the
user design. PROGRAM resets the latched decodes for
EXTEST, CONFIGURE, and READBACK instructions.
Loading a 3-bit instruction into the Instruction Register (IR)
determines the subsequent operation of the boundary-
scan logic, Table 1. The instruction selects the source of the
TDO pin, and selects the source of device input and output
data (boundary-scan register or input pin/user logic)
Note: In the XC4000, whenever the TAP Controller is in the
Shift-DR state, all data registers are shifted, regardless of
the instruction. DR data is modified even if a BYPASS
instruction is executed.
The instruction register is not used only to hold the current
instruction. If the TAP is in the capture-IR state and TCK
goes high, the instruction register captures the current
boundary-scan state of the device. I0 is 1 by default. I1 is 0
by default. I2 is 0 if the devices is in configure by boundary
scan mode. Before and after configure by boundary scan
mode, I2 will capture 1. Note that I0 is shifted out of TDO
first, then I1, and then I2.
Table 1: Boundary Scan Instructions.
IO is closest to DTO
The Boundary-Scan Data Register
The Data Register (DR) is a serial shift register imple-
mented in the IOBs of the FPGA device, (Figure 2). Poten-
tially, each IOB can be configured as an independently
controlled bidirectional pin. Therefore, three data register
bits are provided per IOB: for input data, output data and 3-
state control. In practice, many of these bits are redundant,
but they are not removed from the scan chain.
An update latch accompanies each bit of the DR, and is
used to hold injected test data stable during shifting. The
update latch is opened during the Update-DR state of the
TAP Controller when TCK is Low.
In a typical DR instruction, the DR captures data during the
Capture-DR state (on the rising edge of TCK). This data is
then shifted out and replaced with new test data. Subse-
quently, the update latch opens, and the new test data
becomes available for injection into the logic or the inter-
connect. The injection of data occurs only if an EXTEST
instruction is in progress.
Note: The update latch is opened whenever the TAP Con-
troller is in the Update-DR state, regardless of the instruc-
tion. Care must be exercised to ensure that appropriate
data is contained in the update latch prior to initiating an
EXTEST. Any DR instruction, including BYPASS, that is
executed after the test data is loaded, but before the
EXTEST commences, changes the test data.
The IEEE Standard does not require the ability to inject
data into the on-chip system logic and observe the results
during EXTEST. How ev er , this capability helps compensate
for the lack of INTEST. Logic inputs may be set to specific
lev els b y a SAMPLE/PRELOAD or EXTEST instruction and
the resulting logic outputs captured during a subsequent
EXTEST. It must be recognized, however, that all DR bits
are captured during an EXTEST and, therefore, may
change.
Pull-up and pull-down resistors remain active during
boundary scan. Before and during configuration, all pins
Instruction
I2 I1 I0
Test
Selected TDO
Source I/O Data
Source
0 0 0 EXTEST DR DR
0 0 1 SAMPLE/
PRELOAD DR Pin/Logic
0 1 0 USER 1 TDO1 Pin/Logic
0 1 1 USER 2 TDO2 Pin/Logic
1 0 0 READBACK Readback Data Pin/Logic
1 0 1 CONFIGURE DOUT Disabled
1 1 0 RESERVED — —
1 1 1 BYPASS Bypass Reg Pin/Logic
Boundary Scan in XC4000 and XC5000 Series Devices
14-52 June 1, 1996 (Version 2.0)
are pulled up. After configuration, the IOB can be config-
ured with a pull-up resistor, a pull-down resistor or neither.
Note: Internal pull-up/pull-down resistors must be taken
into account when designing test vectors to detect open cir-
cuit PC traces.
The primar y and secondary global clock inputs (PGCK1-4
and SGCK1-4) are taken directly from the pins , and cannot
be ov erwritten with boundary-scan data. Howe v er , if neces-
sary, it is possible to drive the clock input from boundary
scan. The exter nal clock source is 3-stated, and the clock
net is driven with boundary scan data through the output
driver in the clock-pad IOB. If the clock-pad IOBs are used
for non-cloc k signals , the data may be o v erwritten normally.
Figure 3 shows the data-register cell for a TAP pin. An OR-
gate permanently disables the output buffer if boundary-
scan operation is selected. Consequently, it is impossible
for the outputs in IOBs used by TAP inputs to conflict with
TAP operation. TAP data is taken directly from the pin, and
cannot be overwritten by injected boundary-scan data.
Table 2 lists, in data-stream order, the boundary-scan cells
that make up the DR. The cell closest to TDO corresponds
to the first bit of the data-stream, and is at the top of the
table. This order is consistent with the BSDL description.
Each IOB corresponds to three bits in the DR. The 3-state
control is first (closest to TDO), the output is next, and the
input is last. Other signals correspond to individual register
bits. IOB locations assume that the die is viewed from the
top, as in XDE.
Note: All IOBs remain in the DR, independent of whether
they are actually used, or even bonded. Three bits,
BSCANT.UPD, TDO.O and TDO.T, are included for Xilinx
test purposes, and may be ignored by other users. CCLK,
PROGRAM and DONE are not included in the boundary
scan.
IOB.I
(To FPGA Interconnect)
IOB.O
IOB.T
(From FPGA Interconnect)
D Q
D Q
D Q
1
0
1
0
1
0
Pull-Up
Pull-Down
VCC
To Global
Clock Buffer
(CLK Pad Only)
0
1
1
0
1
0
IOB
From TDI
Shift/Capture DRCK Update EXTEST
Towards TDO
X5998
D Q
D
D Q
Q
LE
sd
LE
sd
LE
sd
Test Logic
Reset
Figure 2: Boundary Scan Logic in a Typical IOB
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
B SCANT.UPD(TDI end)
X2674
Table 2: Boundary Scan Order
June 1, 1996 (Version 2.0) 14-53
Tables in the data sheet show the DR order for all XC4000
family devices. The DR also includes the following non-pin
bits: TDO .T and TDO.I, which are alw a ys bits 0 and 1 of the
DR, respectively, and BSCANT.UPD which is always the
last bit of the DR.
The Bypass Register
This is a 1-bit shift register that passes the serial data
directly to TDO when a bypass instruction is executed.
User Registers
The XC4000 boundary-scan instruction set includes two
USERCODE instructions, USER1 and USER2. Connec-
tions are provided to the TAP and TAP controller that,
together with direct connections to the TAP pins , permit the
user to include boundary-scan self-test features in the
design.
The boundary scan block has six connections for user reg-
isters: SEL1, SEL2, TDO1, TDO2, DRCK and IDLE. TDI is
available directly from the IOB that provides the TDI pin.
Note: The TDI signal supplied to user test logic is overwrit-
ten by boundary-scan test data during EXTEST. During
user tests, it is not altered.
SEL1, SEL2 – SEL1 and SEL2 enable user logic. They are
asserted (High) when the instruction register contains
instructions USER1 and USER2, respectively.
TDO1, TDO2 – TDO1 and TDO2 are inputs to the TDO out-
put multiplexer, permitting user access to the serial bound-
ary-scan output. They are selected when executing the
instructions USER1 and USER2, respectively. Input to user
data registers can be derived directly from the TDI pin, thus
completing the boundary-scan chain.
There is a one flip-flop delay betw een TDO1/TDO2 and the
TDO output. This flip-flop is clocked on the falling edge of
TCK.
DRCK – Data register clock (DRCK) is a gated and in verted
version of TCK. It is provided to clock user test-data regis-
ters. TDI data should be sampled with the falling edge of
DRCK (rising edge of TCK). The TDO output flip-flop
accepts data on the rising edge of DRCK (falling edge of
TCK). DRCK is active only during the Capture-DR and
Shift-DR states of the TAP controller.
IDLE – IDLE is a second gated and inverted version of
TCK. It is active during the Run-Test/Idle state of the TAP
controller, and may be used to clock user test logic a set
number of times, determined through TMS by the central
test controller.
D Q
IOB.I
(To FPGA Interconnect)
IOB.O
(From FPGA Interconnect)
IOB.T
D Q
D Q
1
0
1
0
1
0
Pull-Up
Pull-Down
V
CC
To Tap
Controller
1
0
1
0
IOB
From TDI
Shift/Capture DRCK Update EXTEST
Towards TDO
X5999
Device Not
Configured
Boundary
Scan Enabled
D Q
D Q
LE
sd
LE
sd
Test Logic
Reset
Figure 3: Boundary Scan Logic in a TAP Input (TMS, TCK, and TDI Only)
Boundary Scan in XC4000 and XC5000 Series Devices
14-54 June 1, 1996 (Version 2.0)
Using Boundary Scan
Full access to the built-in boundary-scan logic is always
available between power-up and the star t of configuration.
Optionally, the built-in logic is fully av ailab le after configur a-
tion if boundary scan is specified in the design. At this time ,
user test logic is also available, and may be accessed
through the boundary-scan port. During configuration, a
reduced boundary-scan capability remains available: the
SAMPLE/PRELOAD and BYPASS instructions only.
Figure 4 is a flow chart of the FPGA start-up sequence that
shows when the boundary-scan instructions are available.
Since PROGRAM resets the TAP controller, boundary-scan
operations cannot commence until PROGRAM has been
taken High.
Full boundary-scan capabilities are then availab le until INIT
is High. Without external intervention, INIT automatically
goes High after ~1 ms. If more time is required for bound-
ary-scan testing, INIT may be held Low beyond this period
by applying an e xternal Low signal to the INIT pin until test-
ing is complete.
Boundary scan can be accessed before the FPGA is con-
figured and after the FPGA is configured. If you want to
access boundary scan before the device is configured, then
when you power-up the device, hold the INIT pin low until
VCC has risen to Vcc(min). If y ou ha ve already started con-
figuring the device, data frames are already being sent to
the FPGA, then you have two choices. You can either
access full-boundary scan mode, or limited boundary scan
mode. If you want to access full-boundary scan mode, then
both INIT and PROGRAM must be brought low (Hold INIT
and PROG low for over 300 ns and then release PRO-
GRAM. After releasing PROGRAM, continue to hold INIT
low while sending signals to the TAP. If y ou can use the lim-
ited boundary scan mode (which means you only can use
the SAMPLE/PRELOAD and BYPASS instructions), then
just bring INIT low.
Accessing boundary scan after the device is configured
has one requirement. The BSCAN symbol must be instan-
tiated/inserted into your design with the correct syntax (see
Figure 5). In this case, activating boundary scan after con-
figuration amounts to toggling the TAP pins.
INIT
High? if
Master
Sample
Mode Lines
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
VCC
>3.5 V
No
Yes
Yes
No
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3 µs per Frame
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Master CCLK
Goes Active
F
Pull INIT Low
and Stop
X6076
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration Memory
Once More
LDC Output = L, HDC Output = H
Boundary Scan
Instructions
Available:
I/O Active
Keep Clearing
Configuration Memory
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms PROGRAM
= Low
No
Yes
Yes
Figure 4: Start-up Sequence
June 1, 1996 (Version 2.0) 14-55
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
IBUF
4k BSCAN Syntax for BSCAN after configure symbol
5k BSCAN Syntax for BSCAN after configure symbol
X5966
IBUF
IBUF
OBUF
Figure 5: Boundary-Scan Schematic
From
User
Logic OBUFT TDO
X2676
Figure 6: Typical Non-Boundary-Scan TDO
Connection
From
Previous
Cell
T
O
I
EXTEST
Update – DR
Test Data Register To
Next
Cell
Update Latch
Capture – DR
Update – DR
EN
System
Logic
X2677
DRCK
Figure 7: EXTEST Data Flow
Boundary Scan in XC4000 and XC5000 Series Devices
14-56 June 1, 1996 (Version 2.0)
The IEEE definition of EXTEST only requires that test data
be driven onto outputs, that 3-state output controls be o v er-
ridden, and that input data be captured. The capture of out-
put data and 3-state controls and the forcing of test data
into the system logic is normally performed during INTEST.
The XC4000 effectively performs EXTEST and INTEST
simultaneously. This added functionality permits the testing
of internal logic, and compensates for the absence of a
separate INTEST instruction. However, when performing
an EXTEST, care must be taken over what signals are
driven into the system logic; data captured from internal
system logic must be masked out of the test-data stream
before performing check-sum analysis.
SAMPLE/PRELOAD – The SAMPLE/PRELOAD instruc-
tion permits visibility into system operation by capturing the
state of the I/O. It also per mits valid data to be loaded into
the update register before commencing an EXTEST.
The DR and update latch operate exactly as in EXTEST
(see above). However, data flows through the I/O unmodi-
fied.
BYPASS – The BYPASS instruction permits data to be
passed synchronously to the next device in the boundar y-
scan path. There is a 1-bit shift register between the TDI
and TDO flip-flop .
USER1, USER2 – These instructions permit test logic,
designed by the user and implemented in CLBs, to be
accessed through the TAP. Test clocks and paths to TDO
are provided, together with two signals that indicate that
user instructions have been loaded. For details, see the
User Registers section above.
User tests depend upon CLBs and interconnect that must
be configured to operate. Consequently, they may only be
performed after configuration.
CONFIGURE – Steps to Follow to configure a Xilinx
XC4000, XC4000E, or XC5200 via JTAG:
1. Turn ‘on’ the boundary scan circuitry.
This can be done one of two ways, either via powerup
or via a configured device with boundary scan enabled.
If you want to do this via powerup, then just hold the
INIT pin low when power is turned on. When VCC has
reached VCC(min), then the TAP can be toggled to enter
JTAG instructions. If you want to do this from a config-
ured device, then just start toggling the JTAG port pins
to go from test-logic-reset to run-test-idle.
2. Load the Xilinx Configure instruction into the IR.
The Xilinx Configure instruction is 101(I2 I1 I0). I0 is the
bit shifted in first into the IR.
3. After shifting in the Xilinx Configure instruction, make
the Configure instruction the current JTAG instruction by
going to the update-IR state. When TCK goes low in the
update-IR state, the FPGA is now in the JTAG configu-
ration mode and will start clearing the configuration
memory.
At this point, the user should be in the update-IR state
in the TAP.
4. Once the Xilinx Configure instruction has been made
current, the user must go from the update-IR state to the
shift-DR state before the FPGA has finished clearing it's
configuration memory.
The approximate time it takes to clear an FPGA's con-
figuration memory is: 2 * 1 us * (# of frames per device
bitstream).
If the user doesn't get to the shift-dr state before INIT
goes high, then the bitstream will not be shifted into the
FPGA in the right sequence and the device will not con-
figure as expected.
5. Once INIT has gone high, the TAP should already be in
the shift-DR state.
In the shift-DR state, start shifting in the bitstream. Con-
tinue shifting in the bitstream until DONE has gone high
and the startup sequence has finished.
During the time you are shifting in the bitstream via the
TAP, the configuration pins LDC. HDC, INIT, PRO-
GRAM, etc. all function as they normally do during non-
JTAG configuration.
Some Additional Notes:
(a) If you want to power-up the FPGA in JTAG mode,
this can be done by placing a pulldo wn of appro ximately
4.7 Kohms on the INIT pin. This pulldown has the merit
of holding INIT low to allow the user to get into JTAG,
*and* allow the user during JTAG configuration to 'see'
the INIT pin; With the pulldown attached to INIT, the
user will see a drop of approximately 0.5V if INIT drops
low.
The alternative to using a pulldown on the INIT pin on
powerup is for the 'user' to hold INIT low during power-
up , and once the TAP is in run-test-idle, release the INIT
pin and pull it up to VCC.
(b) It is possible to configure se v eral 4K, 4KE, and/or 5K
devices in a JTAG chain. But unlike non-JTAG daisy-
chain configuration, this doesn't mean merging all the
bitstreams into one bitstream. In the case of JTAG con-
figuration of Xilinx devices in a JTAG chain, all devices,
except the one being configured, will be placed in
BYPASS mode. The one device in CONFIGURE will
have its bitstream downloaded to it. After configuring
this device it will be placed in BYPASS, and another
device will be taken out of BYPASS into CONFIGURE.
(c) In general for the XC4000, XC4000E, and XC5200,
if you are configuring these devices via JTAG, finish
configuring the device first before executing any other
June 1, 1996 (Version 2.0) 14-57
JTAG instructions. If the bitstream has not finished load-
ing, then if you decide to execute some other JTAG
instructions, then the configuration process via JTAG
must be re-started from test-logic-reset.
(d) If boundary scan is not available after the FPGA is
configured, then make sure that the release of I/Os is
the last event in the startup sequence.
If boundary scan is not available, the FPGA is config-
ured, and the I/Os are released before the startup
sequence is finished, the FPGA will not respond to
input signals and outputs won’t respond at all.
READBACK – Readback through the TAP allows the user
to access the readback features of the de vice , which w ould
normally need to be accessed through user-specified pins.
All limits of ‘nor mal’ readback are the same with readback
through the TAP. Like regular readback, readback through
the TAP is at a minimum of 10 KHz and at a maximum of 1
MHz. Like regular readback, the readback bistream
through boundary scan has the same format.
Unlike regular readback, which can be done over and over
again, readback through the TAP requires the following cir-
cuit:
1. In your schematic, or top-level synthesis design, instan-
tiate the BSCAN and READBACK symbols.
2. Connect the BSCAN symbol pins TDI, TMS, TCK, and
TDO to the boundary scan pads TDI, TMS, TCK, and
TDO, respectively.
3. Next, connect the net between the TCK pad and TCK
pin on the BSCAN symbol to an IBUF. Take the output of
the IBUF and connect it to the CLK pin of the READ-
BACK symbol. See Figure 8.
4. After entering the abo ve circuit, compile the design to an
.lca file.
5. Make the .bit file for the .lca file by using the following
option with makebits:
-f readclk:rdbk
For example, at a unix prompt:
% makebits -f readclk:rdbk designame
6. Now the FPGA is ready to perform consecutive read-
backs.
READBACK is performed by loading the IR with the
READBACK instruction and then shifting out the cap-
tured data from the shift-dr state in the TAP.
Perform the first readback by loading the IR with the
READBACK instruction. This first readback must be fin-
ished, which means shifting out the *entire* readback
bitstream. To be safe, shift out the entire bitstream and
then send three additional TCK's.
7. After performing the first readback, another readback
can be performed by going to the test-logic-reset state,
and re-loading the READBACK instruction and perf orm-
ing the READBACK as described in the previous para-
graph.
In summary, consecutive readbacks are performed by
starting from test-logic-reset, loading the IR with the
READBACK instruction, shifting out the readback bit-
stream plus three additional TCK's , and then going bac k
to the test-logic-reset state.
Alternatively, if you do not want to go back to the test-
logic-reset state, realize that after shifting out readback
bitstream, a minimum of 3 additional clocks are needed
on the readback register. So, after doing a readback,
instead of going back to test-logic-reset, a user can opt
to execute some other JTAG instruction, and then per-
form another readback.
Also, this above procedure is only needed if you intend
to do more than 1 readback. If you intend only to do a
readback once, then connection between the BSCAN
symbol and the READBACK symbol is not needed. In
that case, all that is needed is the BSCAN symbol
instantiated with the boundary scan pads (TDI, TMS,
TCK, & TDO) on the top-level of the design.
Boundary Scan Description
Language Files
Boundary Scan Description Language (BSDL) files
describe boundary-scan-capable parts in a standard for-
mat used by automated test-generation softw are. The order
and function of bits in the boundary-scan data register are
included in this description.
BSDL files are available via the Xilinx BBS (408-559-9327)
Bibliography
The following publications contains information about the
IEEE Standard 1149.1, and should be consulted for gen-
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
IBUF
TDO
BSCAN
• 4k BSCAN Symbol setup for multiple READBACKS through TAP
• For the 5k, add IBUFs to TDI, TMS, and TCK. For TDO, add an OBUF.
(see figure 5)
CLK
TRIG
DATA 
RIP
READBACK
X5968
Figure 8: Symbol Setup for Multiple Readbacks
Boundary Scan in XC4000 and XC5000 Series Devices
14-58 June 1, 1996 (Version 2.0)
eral boundary-scan information beyond the scope of this
application note.
Colin M. Maunder & Rodham E. Tulloss.
The Test Access
Port and Boundary Scan Architecture
. IEEE Computer
Society Press, 10662 Los Vaqueros Circle , P.O. BOX 3014,
Los Alamitos, CA 90720-1264.
John Fluke Mfg. Co. Inc.
The ABC of Boundary Scan Test
.
John Fluke Mfg. Co. Inc., P.O. BOX 9090, Everett, WA
98206.
GenRad Inc.
Meeting the Challenge of Boundary Scan
.
GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174.
Ken Parker.
The Boundary Scan Handbook
. Kluwer Aca-
demic Publications, (617) 871-6600.
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Index
1
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
Numerics
3-state buffer
XC3000 Series 4-293, 4-302, 14-17
XC4000 Series 4-29
XC5200 4-191
3-state net, global. See Global 3-State
5-input function
XC3000 Series 14-13
XC5200 4-188
70% rule 14-16
7400 equivalents
XC4000 Series 4-10
A
ABEL 2-6, 2-7
See also XABEL-CPLD
See also Xilinx ABEL
absolute maximum ratings
overshoot and undershoot 14-47
specifications
XC1700D 6-6
XC3000A 4-343
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-81
XC5200 4-207
XC5200L 4-250
XC6200 4-275
XC8100 5-33
ACLK symbol 14-18
adaptor selector for programmer 10-2
address pins
pin descriptions
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
XC6200 4-273
advance specifications, definition of 1-1, 4-80, 4-206
algorithms, programmer 10-1
Alliance Program 2-7
Alliance Series 2-6, 2-7, 2-11
Base System
OrCAD (PC) 2-16
Viewlogic (PC) 2-18
Viewlogic Stand-Alone (PC) 2-20
Extended System
Viewlogic Stand-Alone (PC) 2-22
Standard System
Cadence (Workstation) 2-26
Mentor V8 (Workstation) 2-24
OrCAD (PC) 2-17
Synopsys (Workstation) 2-25
third party 2-27
Viewlogic (PC) 2-19
Viewlogic (Workstation) 2-23
Viewlogic Stand-Alone (PC) 2-21
ALU, XC7300 3-74
antifuse 5-3, 5-13
AppLINX CD-ROM 13-1, 13-5
array data multiplexer, XC6200 4-264
asynchronous peripheral configuration mode
debugging hints 14-31
specifications
XC3000 Series 4-315
XC4000 Series 4-75
XC6200 4-278
XC3000 Series 4-314
XC4000 Series 4-49, 4-74
XC6200 4-268
asynchronous RAM 4-19
attribute
DECODE 4-31
INIT 4-19
LOC 4-41, 4-43, 4-45
MEDDELAY 4-26, 4-27
NODELAY 4-26, 4-27
available products
HardWire 8-3
high-reliability 9-1
software 2-1
XC1700D 6-10
XC3000 Series 4-339
XC3000A 4-348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-174
XC5200 4-248
XC6200 4-286
XC7300 3-71
XC8100 5-42
XC9500 3-4
B
bar code 11-22
Base System
Alliance Series
OrCAD (PC) 2-16
Viewlogic (PC) 2-18
Viewlogic Stand-Alone (PC) 2-20
Foundation Series (PC) 2-12
with VHDL 2-13
2
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
basic moisture life test 12-2
battery backup in XC3000 Series 14-21, 14-37
BBS bulletin board 1-5, 13-3
command summary 13-3
BCLKIN 14-18
pin description
XC3000 Series 4-324
BG packages
package drawings 11-45
thermal resistance 11-12
BG225 package
package drawing 11-45
pinout diagram
XC8100 5-32
pinout table
XC4000 Series 4-152
BG352 package
package drawing 11-46
pinout table
XC4000 Series 4-163
BG432 package
package drawing 11-47
pinout table
XC4000 Series 4-170
BGA packages
package drawings 11-45
thermal resistance 11-12
bidirectional (bidi) buffer
XC3000 Series 4-296
bitstream
combining with MakePROM 4-55, 4-305
copyrighting 14-37
format for configuration
XC4000 Series 4-56
XC5200 4-200
boundary scan
access to 14-54
avoiding inadvertent activation 4-53
bypass register 14-53
configuration with 4-64
daisy chain configuration 14-56
data register 14-51
effect on GTS 4-28
implementing in schematic 4-53
XC4000 Series 4-53
library symbol 4-48, 4-53
pin descriptions
XC4000 Series 4-48
XC5200 4-197
specifications
XC4000E 4-96
TAP controller 14-51
test access port (TAP) 14-51
user registers 14-53
XC4000 Series 4-29, 4-50, 14-49
XC5200 4-191, 14-49
XC8100 5-3, 5-11
XC9500 3-14
Boundary Scan Description Language. See BSDL
BSCAN symbol 4-48, 4-53
BSDL files
XC4000 Series 4-53, 14-57
XC5200 14-57
BUF1X symbol 5-7
BUFE symbol 5-6
BUFEDGE symbol 5-7
BUFFCLK symbol 4-45, 4-48
buffer, 3-state
XC3000 Series 4-293, 4-302, 14-17
XC4000 Series 4-29
XC5200 4-191
buffer, bidirectional
XC3000 Series 4-296
buffered switch matrix 4-36
BUFG symbol 4-194
BUFGE symbol 4-45, 4-48
BUFGLS symbol 4-43, 4-48
BUFGP symbol 4-41
BUFGS symbol 4-41
BUFROW symbol 5-7
BUFT symbol 4-30
bulletin board (BBS) 1-5, 13-3
command summary 13-3
bus contention, internal 14-17
bypass register 14-53
C
cableXChecker 2-8, 2-36
Cadence 2-2, 2-7
software 2-26
carry logic
XC4000 Series 4-21
XC5200 4-189
carry lookahead
XC7300 3-75
cascade logic
XC5200 4-190
XC8100 5-6
CB100 package
package drawing
XC3000 Series 11-61
XC4000 Series 11-62
CB164 package
package drawing
3
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC3000 Series 11-63
XC4000 Series 11-64
CB196 package
package drawing 11-65
CB228 package
package drawing 11-66
CC packages
package drawings 11-67
CC20 package
package drawing 11-67
CCLK
frequency variation
XC3000 Series 14-21
in configuration debug 14-32
low-time restriction in XC3000 Series 14-21
pin description
XC3000 Series 4-323
XC4000 Series 4-47
XC5200 4-197
setting frequency
XC4000 Series 4-56
use as configuration clock 14-25
XC3000 Series 4-307
XC4000 Series 4-54
XC5200 4-199
ceramic packages
brazed CQFP
package drawings 11-61
DIP package drawings 11-48
PGApackage drawings 11-49
windowed
package drawings 11-51
characterization data
XC7300 3-135
CLB. See configurable logic block
CLB-to-pad diagram
XC5200 4-212
XC5202 4-212
XC5204 4-214
XC5206 4-216
XC5210 4-218
XC5215 4-220
CLC. See configurable logic cell
CLCC packages
package drawings 11-67
clock diagram
XC4000E 4-42
XC4000EX 4-42
XC6200 4-261
CMOS input
XC3000 Series 4-293
XC4000 Series 4-24
XC5200 4-196
XC8100 5-9, 5-12
CMOS output
XC3000 Series 4-293, 14-16
XC4000 Series 4-27, 14-12
XC5200 4-196
XC8100 5-10
ConfigOK
pin description
XC6200 4-273
configurable logic block (CLB)
block diagram
XC3000 Series 4-294
XC4000 Series 4-12
XC5200 4-188
carry logic
XC4000 Series 4-21
XC5200 4-189
cascade logic
XC5200 4-190
flip-flop
XC3000 Series 4-294, 14-15
XC4000 Series 4-12
XC5200 4-188
function generator
XC3000 Series 4-295, 14-13
XC4000 Series 4-11
XC5200 4-188
latchXC4000EX 4-12
XC5200 4-188
RAM 4-14
routing associated with
XC3000 Series 14-15
XC4000 Series 4-32
specifications
XC3000A 4-344
XC3000L 4-352
XC3100A 4-360
XC3100L 4-368
XC4000E 4-84
XC5200 4-209
XC3000 Series 4-294, 14-13
XC4000 Series 4-11
XC5200 4-184, 4-188
differences from XC4000 and XC3000 4-182
XC6200. See function unit
configurable logic cell (CLC)
cascade logic 5-6
flip-flop 5-6
function generator 5-6
latch 5-6
4
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
specifications 5-35
XC8100 5-5
configuration 14-25, 14-39
asynchronous peripheral mode
debugging hints 14-31
XC3000 Series 4-314
XC3000 Series specifications 4-315
XC4000 Series 4-49, 4-74
XC4000 Series specifications 4-75
XC6200 4-268
bitstream copyrighting 14-37
bitstream format
XC4000 Series 4-56
XC5200 4-200
boundary scan pins, using 4-64, 14-56
clock. See CCLK
configuration sequence
XC4000 Series 4-59
XC5200 4-203
control pins 14-34
daisy chain 14-26
debugging hints 14-31
mixed family 4-55, 14-33
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
debugging 14-29
error protection 14-26
express mode
daisy chain 4-56, 4-200
XC4000 Series specifications 4-77
XC4000EX 4-47, 4-55, 4-56, 4-62, 4-76
XC5200 4-197, 4-200
XC5200 specifications 4-201
guidelines 14-25
initiating reconfiguration 14-40
length count 4-56, 4-62, 4-203, 4-305, 14-25, 14-29
master modes, general 14-28
XC3000 Series 4-304, 4-307
XC4000 Series 4-54, 4-62
XC4000 Series specifications 4-79
XC5200 4-199
XC5200 specifications 4-205
XC6200 4-271
XC6200 specifications 4-276
master parallel mode
debugging hints 14-30
XC3000 Series 4-312
XC3000 Series specifications 4-313
XC4000 Series 4-47, 4-70
XC4000 Series specifications 4-71
XC5200 4-197
master serial mode
debugging hints 14-30
XC3000 Series 4-310
XC3000 Series specifications 4-311
XC4000 Series 4-66
XC4000 Series specifications 4-67
memory cell 4-291, 14-35
mode 14-28
selection of 14-28, 14-29
modes, table of
XC3000 Series 4-304
XC4000 Series 4-54
XC5200 4-199
peripheral mode
XC3000 Series 4-314
XC3000 Series specifications 4-315
peripheral modes, general 14-28
debugging hints 14-32
XC3000 Series 4-307
XC4000 Series 4-47, 4-54
XC5200 4-197, 4-199
pin descriptions
XC3000 4-323
XC4000 Series 4-47
XC5200 4-197
pin functions during
XC3000 Series 4-325
XC4000 Series 4-78
XC5200 4-204
power-on reset
XC3000 Series 4-304
preamble 14-25
reducing time 14-40
slave serial mode 14-28
debugging hints 14-31
XC3000 Series 4-307, 4-316
XC3000 Series specifications 4-317
XC4000 Series 4-47, 4-55, 4-68
XC4000 Series specifications 4-69
XC5200 4-199
XC6200 4-271
specifications
XC3000 Series 4-310
XC4000 Series 4-66
start-up sequence 14-26
XC3000 Series 14-22
XC4000 Series 4-60
XC5200 4-203
switching characteristics
XC4000 Series 4-79
XC5200 4-205
synchronous peripheral mode
XC4000 Series 4-47, 4-72
XC4000 Series specifications 4-73
5
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC5200 4-197
XC3000 Series 4-304, 14-22
XC4000 Series 4-54
XC5200 4-199
differences from XC4000 and XC3000 4-183
XC6200 4-268
XC8100 5-13
copyrighting bitstream 14-37
CPLD
available I/O 11-1
core software 2-31
design flow 2-5
EPROM-based 14-5
FLASH-based 14-5
overview 1-3, 1-4, 14-5
product selection guide 1-8, 14-3, 14-5, 14-6
programmer 10-1
CQ packages
package drawings 11-61
CQ100 package
pinout table
XC3000 Series 4-331
CQFP packages
package drawings 11-61
CRC error checking
selecting with MakeBits 4-57
XC4000 Series 4-56, 4-57
crystal oscillator
XC3000 Series 4-303, 4-309, 14-19
CS in configuration debug 14-30
pin description
XC6200 4-273
CS0, CS1
pin descriptions
XC4000 Series 4-49
XC5200 4-198
CS0, CS1, CS2
pin descriptions
XC3000 Series 4-324
customer support. See technical support
cyclic redundancy check (CRC)
XC4000 Series 4-57
D
daisy chain 14-26
creating bitstream 4-55, 4-305
debugging hints 14-31
express mode
XC4000EX 4-56
XC5200 4-200
mixed family 4-55, 14-33
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
data integrity 12-6
data pins
pin descriptions
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
XC6200 4-273
data register 14-51
data stream. See bitstream
DBUF symbol 5-9, 5-10
DC characteristics
specifications
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC5200 4-206
XC5200L 4-250
XC6200 4-275
XC8100 at 3.3 V 5-34
XC8100 at 5 V 5-33
DD8 package
package drawing 11-48
debugging
configuration 14-29
DECODE attribute 4-31
decode logic. See cascade logic, edge decoder
decoupling capacitor
XC6200 4-274
delayinput delay 14-45
XC3000 Series 14-15
of configuration after power-up
XC4000 Series 4-60
optional input delay
XC4000 Series 4-26
output
XC4000 Series 14-10
with fast capture latch 4-27
demoboard
FPGA 2-8, 2-36
design flow
CPLD 2-5
DS-502 software package 2-4
DS-560 software package 2-5
FPGA 2-4
software 2-2
XC8100 5-2, 5-16
Design Manager 2-1
6
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
design security
XC7300 3-78
XC9500 3-14
development system 2-1
overview 1-5
DIN in daisy chain
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
pin description
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
DIP package
ceramic 11-48
plastic 11-27
direct interconnect
XC3000 Series 4-296
XC4000EX 4-37
XC5200 4-184, 4-192
XC6200 4-256
disk space requirements
programmer 10-1
See also hardware requirements
DONE
during power-up 14-35
express mode configuration 4-56
going High after configuration
XC3000 Series 4-308
XC4000 Series 4-62
in configuration debug 14-30
not going High after configuration 14-29
pin description
XC4000 Series 4-47
XC5200 4-197
DONE/PROG
during power-up 14-35
pin description
XC3000 Series 4-323
double-length routing
XC4000 Series 4-35
XC5200 4-194
DOUT 14-25
in daisy chain
express mode 4-56
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
pin description
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
dry bag 11-19
dry bake 11-19
DS-290 software package 2-32
DS-344 software package 2-32
DS-35 software package 2-32
DS-371 software package 2-33
DS-380 software package 2-32
DS-390 software package 2-32
DS-391 software package 2-32
DS-401 software package 2-35
DS-502 software package 2-30
design flow 2-4
DS-560 software package 2-31
design flow 2-5
DS-571 software package 2-34
dual-port RAM 4-17
E
edge decoder 4-31
edge-triggered RAM 4-16
advantages of 4-14
EDIF 2-6
EIAJ standards 11-4
electrical parameters
programmer 10-1
XC6200 4-274
electrostatic discharge (ESD) 12-7
E-mail addresses 13-4
endurance, XC9500 3-14
EPROM-based CPLD
overview 14-5
error checking, bitstream 4-57, 4-309
XC3000 Series 4-309
XC4000 Series 4-57
express configuration mode
CRC not supported 4-56
specifications
XC4000 Series 4-77
XC5200 4-201
synchronized to DONE
XC4000EX 4-62
XC4000EX 4-47, 4-55, 4-56, 4-62, 4-76
XC5200 4-197, 4-200
Extended System
Alliance Series
Viewlogic Stand-Alone (PC) 2-22
F
factory floor life 11-19
failure analysis 12-3, 12-6
7
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
failures in time 12-2
fast capture latch 4-26
fast carry logic. See carry logic
fast function blocks, XC7300 3-72
FastCLK buffer (BUFFCLK) 4-29, 4-45, 4-48
fast pin-to-pin path 4-28
with fast capture latch 4-26
FastCONNECT switch matrix 3-11
FastFlash technology
XC9500 3-16
fastlane routing, XC6200 4-256
FCLK1 - FCLK4
clock diagram 4-42
pin descriptions
XC4000EX 4-48
FD symbol 5-15
FD_SYNC symbol 5-15
FDC symbol 5-15
FDCE symbol 4-13
FDP symbol 5-6, 5-15
FIFOimplementing in XC4000 Series RAM 4-14
FITs 12-2
FLASH-based CPLD
overview 14-5
flip-flop
in CLB
XC3000 Series 4-294, 14-15
XC4000 Series 4-12, 4-13
XC5200 4-188
in IOB
metastability 14-41
none in XC5200 4-196
XC3000 Series 4-293, 14-15
XC4000 Series 4-24, 4-27
in XC6200 function unit 4-258
in XC8100 CLC 5-6
Floorplanner 2-1
Flow Engine 2-1
forced air cooling vendors 11-14
Foundation Series 2-6, 2-11
Base System (PC) 2-12
with VHDL 2-13
Standard System (PC) 2-14
with VHDL 2-15
FPGA
advantages of 14-3
available I/O 11-1
core software 2-30
data integrity 12-6
demoboard 2-8, 2-36
design flow 2-4
overview 1-3, 1-4
product selection guide 1-6, 14-3, 14-6
programmer 10-1
security 14-36
function block
XC7300 3-72, 3-74
XC9500 3-5
function generator
in CLB
XC3000 Series 4-295, 14-13
XC4000 Series 4-11
XC5200 4-188
in IOB
XC4000EX 4-28
in XC6200 function unit 4-258
in XC8100 CLC 5-6
using as RAM 4-14
function unit 4-257
block diagram 4-258
flip-flop 4-258
specifications 4-276
G
G1, G2 4-257
pin description
XC6200 4-273
gate array
advantages of FPGAs 1-3
advantages of HardWire 8-1
GCK1 - GCK4
pin descriptions 4-197
XC8100 5-7, 5-24
GCK1 - GCK8
clock diagram 4-42
pin descriptions
XC4000EX 4-48
GClk 4-257, 4-261, 4-268, 4-272
pin description
XC6200 4-273
GCLK symbol 14-18
GClr 4-257, 4-261
pin description
XC6200 4-273
general routing matrix (GRM)
XC5200 4-184, 4-185, 4-192, 4-194
glitchavoidance in XC3000 Series 14-14
power supply 14-35
Global 3-State (GTS)
XC4000 Series 4-28, 4-46
global buffer
specifications
XC3000A 4-343
8
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-81
XC5200 4-207
XC6200 4-276
XC8100 5-38
XC3000 Series 4-302, 14-18
XC4000 Series 4-41
XC4000E 4-41
XC4000EX 4-43
XC5200 4-194
XC6200 4-257, 4-261
XC8100 5-7
Global Early buffer (BUFGE) 4-29, 4-44, 4-48
fast pin-to-pin path 4-28
with fast capture latch 4-26
Global Low-Skew buffer (BUFGLS) 4-43, 4-48
with fast capture latch 4-26
Global Reset (GR)
in CLB
XC5200 4-191
in CLC 5-6
Global Set/Reset (GSR)
in CLB
XC4000 Series 4-13
in IOB
XC4000 Series 4-29
GR. See Global Reset
GRM. See general routing matrix
ground bounce
XC4000 Series 14-10
GRST symbol 5-6
GSR. See Global Set/Reset
GTS. See Global 3-state
H
Hardware Debugger 2-1
hardware requirements
Alliance Series
Base System OrCAD (PC) 2-16
Base System Viewlogic (PC) 2-18
Base System Viewlogic Stand-Alone (PC) 2-20
Extended System Viewlogic Stand-Alone
(PC) 2-22
Standard System Cadence (Workstation) 2-26
Standard System Mentor V8 (PC) 2-24
Standard System OrCAD (PC) 2-17
Standard System Synopsys (Workstation) 2-25
Standard System third party 2-27
Standard System Viewlogic (PC) 2-19
Standard System Viewlogic (Workstation) 2-23
Standard System Viewlogic Stand-Alone
(PC) 2-21
DS-502 software package 2-30
DS-560 software package 2-31
Foundation Series
Base System (PC) 2-12
Base System with VHDL (PC) 2-13
Standard System (PC) 2-14
Standard System with VHDL (PC) 2-15
XABEL-CPLD 2-34
X-BLOX 2-32
Xilinx ABEL 2-33
HardWire 8-1
advantages of 8-1
design verification 8-2
feature summary 8-1
guaranteed results 8-2
overview 1-4
packaging 8-3
product availability 8-3
HDCduring power-up 14-35
pin description
XC3000 Series 4-307, 4-323
XC4000 Series 4-48
XC5200 4-197
HDL 2-3, 2-7
heatsink vendors 11-14
hermeticity test 12-3
high temperature life test 12-2, 12-8
high-density function blocks
XC7300 3-74
high-reliability (Hi-Rel) 9-1
overview 1-5
product availability 9-1
hold time on data input 14-45
XC4000 Series 4-26
hotline, technical support 13-2
HQ packages 11-17
package drawings 11-32
thermal data 11-11
HQ100 package
package drawing 11-33
HQ160 package
package drawing 11-34
HQ208 package
package drawing 11-35
pinout table
XC4000 Series 4-146
HQ240 package
package drawing 11-36
pinout table
XC4000 Series 4-154
9
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
HQ304 package
package drawing 11-37
pinout table
XC4000 Series 4-160
HQFP packages
package drawings 11-32
HT packages
package drawings 11-38
HT100 package
package drawing 11-39
HT144 package
package drawing 11-40
HT176 package
package drawing 11-41
HTFP packages
package drawings 11-38
HW-130 programmer 10-1
hysteresis
XC3000 Series 14-15
I
I/O block
see also input/output block
see also input/output cell
XC7300 3-76
XC9500 3-12
I/O count 11-1
XC3000 Series 4-326
XC4000 Series 4-176
XC5200 4-248
XC8100 5-25
I/V characteristics. See V/I characteristics
IBUF symbol 5-9, 5-10
IEEE Standard 1149.1 14-57
IFD symbol 4-24
ILD symbol 4-24, 4-45
ILDFFDX symbol 4-27, 4-45
ILDFLDX symbol 4-27, 4-45
INFF symbol 4-45
INIT during power-up 14-35
in configuration debug 14-30, 14-32
in daisy chain 14-33
pin description
XC3000 Series 4-323
XC4000 Series 4-48
XC5200 4-197
INIT attribute 4-19
initializing RAM 4-19
input/output block (IOB)
clockXC3000 Series 14-17
CMOS input
XC3000 Series 4-293
XC4000 Series 4-24
XC5200 4-196
CMOS output
XC3000 Series 4-293, 14-16
XC4000 Series 4-27, 14-12
XC5200 4-196
delay on input 14-45
XC3000 Series 14-15
XC4000 Series 4-26
during configuration
XC3000 Series 4-308
XC4000 Series 4-46
XC6200 4-271
fast capture latch 4-26
flip-flop
metastability 14-41
function generator on output 4-28
maximum available I/O 11-1
XC3000 Series 4-326
XC4000 Series 4-176
XC5200 4-248
multiplexer on output 4-28
optional delay with fast capture latch 4-27
pull-down resistor
XC4000 Series 4-29
XC6200 4-271
pull-up resistor
XC3000 Series 4-293, 4-324
XC4000 Series 4-29
XC6200 4-271
rise/fall time
XC3000 Series 14-15
routing associated with
XC4000 Series 4-38
XC5200 4-185, 4-196
XC6200s 4-263
slew rate control
XC3000 Series 4-293
XC4000 Series 4-28
XC5200 4-196
specifications
XC3000A 4-346
XC3000L 4-354
XC3100A 4-362
XC3100L 4-370
XC4000E 4-92
XC5200 4-211
XC6200 4-277, 4-278
TTL input
XC3000 Series 4-293
XC4000 Series 4-24
10
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC5200 4-196
TTL output
none in XC5200 4-196
XC3000 Series 4-293
XC4000 Series 4-27
unused I/O
XC4000 Series 4-46
VersaRing
XC4000 Series 4-38
XC5200 4-185, 4-196
XC3000 Series 4-292, 14-15
clock 14-17
XC4000 Series 4-24
XC5200 4-196
differences from XC4000 and XC3000 4-183
XC6200 4-261
XC7300 3-76
XC9500 3-12
input/output cell (IOC)
CMOS input 5-9, 5-12
CMOS output 5-10
maximum available I/O 5-25
pull-up resistor 5-10, 5-12
slew rate control 5-10
specifications 5-39
TTL input 5-9, 5-12
TTL output not supported 5-10
XC8100 5-9
in-system programming
XC9500 3-14
interconnect. See routing
IOBUF symbol 5-10
IPAD symbol 4-45
ISO9002 1-5, 12-1
J
JEDEC standards 11-4
JTAG. See boundary scan
junction temperature
junction-to-ambient 11-7
junction-to-case 11-6
L
latchfast capture latch 4-26
in CLB
XC4000EX 4-12, 4-13
XC5200 4-188
in IOB
none in XC5200 4-196
XC3000 Series 4-293
XC4000 Series 4-24
in XC8100 CLC 5-6
latchup 12-8
LC. See logic cell
LDC during power-up 14-35
in configuration debug 14-30
pin description
XC3000 Series 4-307, 4-323
XC4000 Series 4-48
XC5200 4-197
LDCE symbol 4-13
LDE4 symbol 5-6
lead fatigue test 12-3
leakage current
XC8100 5-12
length count
configuration debugging hints 14-32
error in 14-29
XC3000 Series 4-305
XC4000 Series 4-56, 4-62, 4-74
XC5200 4-203
level-sensitive RAM 4-19
library symbol
3-state buffer
BUFE, XC8100 5-6
BUFT, XC4000 Series 4-30
WAND1 4-30
WOR2AND 4-30
3-state output buffer
OBUFE, XC8100 5-10
AND-gate in IOB
OAND2 4-28, 4-29
boundary scan
BSCAN 4-48, 4-53
TCK, TDI, TDO, TMS 4-48, 4-53
fast capture latch
ILDFFDX 4-27, 4-45
ILDFLDX 4-27, 4-45
flip-flop
FD, XC8100 5-15
FD_SYNC, XC8100 5-15
FDC, XC8100 5-15
FDCE, XC4000 Series CLB 4-13
FDP, XC8100 5-6, 5-15
IFD, XC4000 Series IOB 4-24
Global 3-State
STARTUP 4-28
global buffer
ACLK, XC3000 Series 14-18
BUF1X, XC8100 5-7
BUFEDGE, XC8100 5-7
11
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
BUFFCLK, XC4000EX 4-45, 4-48
BUFG, XC5200 4-194
BUFGE, XC4000EX 4-45, 4-48
BUFGLS, XC4000EX 4-43, 4-48
BUFGP, XC4000E 4-41
BUFGS, XC4000E 4-41
BUFROW, XC8100 5-7
GCLK, XC3000 Series 14-18
global reset
GRST, XC8100 5-6
Global Set/Reset
STARTUP 4-13
input buffer
DBUF, XC8100 5-9, 5-10
IBUF, XC8100 5-9, 5-10
input flip-flop
INFF, XC4000 Series 4-45
input latch
ILD, XC4000 Series 4-45
input pad
IPAD 4-45
input/output buffer
IOBUF, XC8100 5-10
latchILD, XC4000 Series IOB 4-24
LDCE, XC4000EX CLB 4-13
mode pins
MD0, MD1, MD2 4-54
oscillator
OSC4, XC4000 Series 4-31
OSC52, XC5200 4-191
output buffer
OBUF, XC8100 5-10
output multiplexer
OMUX2 4-29
readback
READBACK 4-64
register file
LDE4, XC8100 5-6
resistive 3-state output buffer
RBUFE, XC8100 5-10
resistive output buffer
RBUF, XC8100 5-10
resistor
PULLDOWN 4-29
PULLUP 4-29
synthesis library, XC8100 5-19
wide decoder
WAND1 4-31
LIM. See local interconnect matrix
LOC attribute 4-41, 4-43, 4-45
local interconnect matrix (LIM)
XC5200 4-184, 4-192
logic cell (LC)
XC5200 4-182, 4-184
longline
specifications
XC4000E 4-83
XC5200 4-208
XC3000 Series 4-300, 14-15, 14-17
XC4000 Series 4-37
XC5200 4-194
lookup table (LUT). See function generator
low voltage device
XC4000 Series 4-5, 4-6
XC4000 Series driven by 5V 4-24
XC4000 Series driving 5V TTL 4-27
XC8100 5-13
LPM 2-6
M
M0, M1, M2. See mode pins
M0/RTRIG
pin description
XC3000 Series 4-323
M1/RDATA
pin description
XC3000 Series 4-323
M2 pin description
XC3000 Series 4-323
macrocell
XC9500 3-6
magic interconnect
XC6200 4-257
MakeBits program
bitstream generation
XC3000 Series 4-306
XC4000 Series 4-57
CCLK frequency 4-56, 4-66
CRC error checking 4-57
crystal oscillator selection 4-309
express mode 4-56, 4-76
input thresholds
XC4000 Series 4-24
output voltage levels
XC4000 Series 4-27
pull-up on DONE pin 4-47, 4-63
readback options 4-65
start-up timing 4-60, 4-62
XC3000 Series 4-306
XC4000 Series 4-55
tie option 4-306
MakePROM program
combining bitstreams 4-55, 4-305, 4-306
12
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
manufacturers. See vendors
map register
XC6200 4-268
mask register
XC6200 4-268
mass, package 11-15
master configuration modes, general 14-28
XC3000 Series 4-304, 4-307
XC4000 Series 4-54, 4-62
XC4000 Series specifications 4-79
XC5200 4-199
XC5200 specifications 4-205
XC6200 4-271
XC6200 specifications 4-276
master parallel configuration mode
debugging hints 14-30
specifications
XC3000 Series 4-313
XC4000 Series 4-71
XC3000 Series 4-312
XC4000 Series 4-47, 4-70
XC5200 4-197
Master Reset (MR) 5-6
pin description 5-24
master serial configuration mode
debugging hints 14-30
specifications
XC3000 Series 4-311
XC4000 Series 4-67
XC3000 Series 4-310
XC4000 Series 4-66
maximum I/O 11-1
XC3000 Series 4-326
XC4000 Series 4-176
XC5200 4-248
XC8100 5-25
MD0, MD1, MD2 symbols 4-54
Mean Time Between Failures (MTBF)
metastability 14-42
MEDDELAY attribute 4-26, 4-27
memory cell, configuration 4-291, 12-6, 14-35
memory requirements
programmer 10-1
Mentor Graphics 2-2, 2-7
software 2-24, 2-32
metal quad packages
package drawings 11-71
metastability 14-41
XC8100 5-15
MicroVia 5-2, 5-12, 5-14
MIL-STD-883B 1-5
mode pins 14-28
pin descriptions
XC4000 Series 4-47
XC5200 4-197
XC3000 Series 4-304
XC4000 Series 4-54
XC5200 4-199
moisture sensitivity in surface mount packages 11-18
MQ packages
package drawings 11-71
MQ208 package
package drawing 11-71
MQ240 package
package drawing 11-72
MR. See Master Reset
multiplexer
XC4000EX IOB 4-28
XC6200 4-264
N
nearest neighbor routing. See direct interconnect
NODELAY attribute 4-26, 4-27
O
OAND2 symbol 4-28, 4-29
OBUF symbol 5-10
OBUFE symbol 5-10
octal routing 4-40
OE in configuration debug 14-30
pin description
XC6200 4-273
OMUX2 symbol 4-29
on-chip oscillator. See oscillator, on-chip
one-time programmable (OTP) 5-2
testing 5-15
open-drain output 4-28
operating conditions
specifications
XC1700D 6-6
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC5200 4-206
XC5200L 4-250
XC6200 4-275
XC8100 5-33
OrCAD 2-2, 2-7
software 2-16, 2-17, 2-32
ordering information
13
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
software 2-9
XC1700D 6-10
XC3000 Series 4-340
XC3000A 4-348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-178
XC5200 4-248
XC8100 5-42
OSC4 symbol 4-31
OSC52 symbol 4-191
oscillator
crystal
XC3000 Series 4-303, 4-309, 14-19
on-chip 14-35
XC3000 Series 14-21
XC4000 Series 4-31
XC5200 4-183, 4-191
OTP. See one-time programmable
output current
XC3000 Series 14-17
XC4000 Series 4-27, 4-46, 14-9
XC5200 4-196
XC8100 5-10
output multiplexer in XC4000EX IOB 4-28
output slew rate
XC3000 Series 4-293
XC4000 Series 4-28
XC5200 4-196
XC8100 5-10
overshoot 14-47
P
package availability
high-reliability 9-1
XC3000 Series 4-339
XC3000A 4-348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-174
XC5200 4-248
XC6200 4-286
XC8100 5-42
XC9500 3-5
package drawing
BG225 package 11-45
BG352 package 11-46
BG432 package 11-47
CB100 package
XC3000 Series 11-61
XC4000 Series 11-62
CB164 package
XC3000 Series 11-63
XC4000 Series 11-64
CB196 package 11-65
CB228 package 11-66
CC20 package 11-67
DD8 package 11-48
HQ100 package 11-33
HQ160 package 11-34
HQ208 package 11-35
HQ240 package 11-36
HQ304 package 11-37
HT100 package 11-39
HT144 package 11-40
HT176 package 11-41
MQ208 package 11-71
MQ240 package 11-72
PC20 package 11-31
PC28 package 11-31
PC44 package 11-31
PC68 package 11-31
PC84 package 11-31
PD48 package 11-28
PD8 package 11-27
PG120 package 11-52
PG132 package 11-53
PG144 package 11-54
PG156 package 11-55
PG175 package 11-56
PG191 package 11-57
PG223 package 11-58
PG299 package 11-59
PG411 package 11-60
PG68 package 11-49
PG84 package 11-50
PP132 package 11-68
PP175 package 11-69
PQ100 package 11-33
PQ160 package 11-34
PQ208 package 11-35
PQ240 package 11-36
PQ304 package 11-37
PQ44 package 11-32
SO8 package 11-29
TQ100 package 11-39
TQ144 package 11-40
TQ176 package 11-41
TQ44 package 11-38
VO8 package 11-30
VQ100 package 11-44
VQ44 package 11-42
VQ64 package 11-43
14
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
WC44 package 11-70
WC68 package 11-70
WC84 package 11-70
WG84 package 11-51
packaging 11-1
available I/O 11-1
bar code 11-22
data acquisition 11-7
dimensions 11-4
drawings 11-26
dry bag 11-19
dry bake 11-19
EIAJ standards 11-4
EIJ standard board layout 11-5
factory floor life 11-19
handling and storage 11-19
HardWire 8-3
JEDEC standards 11-4
mass 11-15
moisture sensitivity 11-18
options 11-3
orientation 11-5
physical dimensions 11-26
reflow soldering 11-23
tape & reel packing 11-21
thermal characteristics 11-6
thermal database 11-7
thermal management 11-6
thermal resistance
applying data 11-9
table of 11-8
thermally enhanced 11-17
vendors 11-14, 11-25
weight 11-15
PC packages
package drawings 11-31
PC20 package
package drawing 11-31
PC28 package
package drawing 11-31
PC44 package
package drawing 11-31
pinout diagram
XC8100 5-30
pinout table
XC3000 Series 4-327
PC68 package
package drawing 11-31
pinout table
XC3000 Series 4-329
PC84 package
package drawing 11-31
pinout diagram
XC8100 5-31
pinout table
XC3000 Series 4-330
XC4000 Series 4-133
PCI compatibility
XC4000 Series 4-8
PD48 package
package drawing 11-28
PD8 package
package drawing 11-27
performance
XC3000 Series 4-320
XC5200 4-185
XC8100 5-4
peripheral configuration mode
specifications
XC3000 Series 4-315
XC3000 Series 4-314
peripheral configuration modes, general 14-28
debugging hints 14-32
specifications
XC4000 Series 4-79
XC5200 4-205
XC6200 4-276
XC3000 Series 4-307
XC4000 Series 4-47, 4-54
XC5200 4-197, 4-199
peripheral configuration modes. See also asynchronous
peripheral, synchronous peripheral
PG packages
package drawings 11-49, 11-68
PG120 package
package drawing 11-52
pinout table
XC4000 Series 4-136
PG132 package
package drawing 11-53
pinout table
XC3000 Series 4-332
PG144 package
package drawing 11-54
PG156 package
package drawing 11-55
pinout table
XC4000 Series 4-140
PG175 package
package drawing 11-56
pinout table
XC3000 Series 4-335
PG191 package
package drawing 11-57
pinout table
XC4000 Series 4-149
15
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
PG223 package
package drawing 11-58
pinout table
XC4000 Series 4-149
PG299 package
package drawing 11-59
pinout table
XC4000 Series 4-157
thermal resistance 11-12
PG411 package
package drawing 11-60
pinout table
XC4000 Series 4-166
PG68 package
package drawing 11-49
PG84 package
package drawing 11-50
pinout table
XC3000 Series 4-329
PGA packages
package drawings 11-49, 11-68
PGCK1 - PGCK4
clock diagram 4-42
pin descriptions 4-48
physical dimensions of packages 11-26
pin descriptions
functions during configuration
XC3000 Series 4-325
XC4000 Series 4-78
XC5200 4-204
XC3000 Series 4-323
XC4000 Series 4-46
XC6200 4-273
pin locking
XC9500 3-13
pinout diagram
BG225 package
XC8100 5-32
PC44 package
XC8100 5-30
PC84 package
XC8100 5-31
PQ100 package
XC8100 5-31
PQ160 package
XC8100 5-32
VQ44 package
XC8100 5-30
XC8100 5-30
pinout table
BG225 package
XC4000 Series 4-152
BG352 package
XC4000 Series 4-163
BG432 package
XC4000 Series 4-170
CQ100 package
XC3000 Series 4-331
device-specific
XC3000 Series 4-338
XC4000 Series 4-97
XC5200 4-223
XC6200 4-282
XC8100 5-24
HQ208 package
XC4000 Series 4-146
HQ240 package
XC4000 Series 4-154
HQ304 package
XC4000 Series 4-160
package-specific
XC3000 Series 4-326
XC4000 Series 4-133
PC44 package
XC3000 Series 4-327
PC68 package
XC3000 Series 4-329
PC84 package
XC3000 Series 4-330
XC4000 Series 4-133
PG120 package
XC4000 Series 4-136
PG132 package
XC3000 Series 4-332
PG156 package
XC4000 Series 4-140
PG175 package
XC3000 Series 4-335
PG191 package
XC4000 Series 4-149
PG223 package
XC4000 Series 4-149
PG299 package
XC4000 Series 4-157
PG411 package
XC4000 Series 4-166
PG84 package
XC3000 Series 4-329
PQ100 package
XC3000 Series 4-331
XC4000 Series 4-134
PQ160 package
XC3000 Series 4-334
XC4000 Series 4-142
PQ208 package
XC3000 Series 4-337
16
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC4000 Series 4-146
PQ240 package
XC4000 Series 4-154
TQ100 package
XC3000 Series 4-331
TQ144 package
XC3000 Series 4-333
XC4000 Series 4-138
TQ176 package
XC3000 Series 4-336
XC4000 Series 4-144
VQ100 package
XC3000 Series 4-331
XC4000 Series 4-135
VQ64 package
XC3000 Series 4-328
XC3000 Series 4-326
XC3195 4-338
XC4000 Series 4-97
XC4003E 4-97
XC4005E/L 4-98
XC4006E 4-100
XC4008E 4-102
XC4010E/L 4-104
XC4013E/L 4-107
XC4020E 4-110
XC4025E 4-113
XC4028EX/XL 4-113
XC4036EX/XL 4-118
XC4044EX/XL 4-123
XC4052XL 4-128
XC5200 4-223
XC5202 4-223
XC5204 4-226
XC5206 4-230
XC5210 4-235
XC5215 4-241
XC6200 4-282
XC6216 4-282
XC73108 3-121
XC73144 3-132
XC7318 3-87
XC7336/Q 3-96
XC7354 3-105
XC7372 3-113
XC8100 5-24, 5-25
XC8101 5-26
XC8103 5-27
XC8106 5-28
XC8109 5-29
XC95108 3-31
XC95144 3-37
XC95180 3-43
XC95216 3-51
XC95288 3-59
XC9536 3-21
XC9572 3-25
pin-to-pin specifications
XC4000E 4-90
XC5200 4-210
XC6200 4-277
XC8100 5-40
plastic packages
DIP package drawings 11-27
PGApackage drawings 11-68
PLCC packages
package drawings 11-31
power consumption
reduction of 11-14
XC3000 Series 4-322, 14-18
XC4000 Series 14-12
XC6200 4-274
XC8100 5-12
power distribution
XC3000 Series 4-321
XC4000 Series 4-46
power-down mode
none in XC4000 Series 4-46
none in XC5200 4-183
XC3000 Series 4-304, 4-322, 14-21, 14-37
power-on reset
specifications
XC6200 4-276
XC3000 Series 4-304
XC6200 4-272
power-up 14-35
power-up. See also start-up after configuration
PP132 package
package drawing 11-68
PP175 package
package drawing 11-69
PQ packages
package drawings 11-32
thermal data 11-11
PQ100 package
package drawing 11-33
pinout diagram
XC8100 5-31
pinout table
XC3000 Series 4-331
XC4000 Series 4-134
PQ160 package
package drawing 11-34
pinout diagram
17
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC8100 5-32
pinout table
XC3000 Series 4-334
XC4000 Series 4-142
PQ208 package
package drawing 11-35
pinout table
XC3000 Series 4-337
XC4000 Series 4-146
PQ240 package
package drawing 11-36
pinout table
XC4000 Series 4-154
PQ304 package
package drawing 11-37
PQ44 package
package drawing 11-32
PQFP packages
package drawings 11-32
preliminary specifications, definition of 1-1, 4-80, 4-206
Primary Global Buffer (BUFGP) 4-41, 4-48
product availability
HardWire 8-3
high-reliability 9-1
XC3000 Series 4-339
XC3000A 4-348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-174
XC5200 4-248
XC6200 4-286
XC7300 3-71
XC8100 5-42
XC9500 3-4
product qualification requirements 12-4
product selection guide
CPLD 1-8, 14-3, 14-5, 14-6
FPGA 1-6, 14-3, 14-6
product term allocator
XC7300 3-74
XC9500 3-8
PROGRAM
during power-up 14-35
in configuration debug 14-30
inititating reconfiguration 14-40
pin description
XC4000 Series 4-47
XC5200 4-197
programmable switch matrix (PSM)
XC3000 Series 4-296
XC4000 Series 4-35
XC6200 4-259
programmer 10-1
algorithms 10-1
software 10-1
specifications 10-1
programming, in-system
XC9500 3-14
programming. See configuration
PROM
bitstream generation
XC4000 Series 4-55
configuration
XC3000 Series 4-310, 4-312
XC4000 Series 4-6, 4-66, 4-70, 4-74
in configuration debug 14-30
overview 1-5
programmer 10-1
size XC4000E 4-57
XC4000EX 4-58
PROM Formatter 2-1
pseudo daisy chain for express mode
XC4000EX 4-56
XC5200 4-200
pull-down resistor
enabling boundary scan 14-56
IOB XC4000 Series 4-29
XC6200 4-271
PULLDOWN symbol 4-29
pull-up resistor
IOB XC3000 Series 4-293, 4-324
XC4000 Series 4-29, 4-47
XC5200 4-197
XC6200 4-271
IOC 5-10, 5-12
longline
none in XC5200 4-194
XC3000 Series 4-302
XC4000 Series 4-37
PULLUP symbol 4-29
PWRDWN 14-21
battery backup mode 14-37
in configuration debug 14-30, 14-32
pin description
XC3000 Series 4-323
Q
quad routing 4-36
qualification requirements 12-4
quality assurance 12-1
18
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
R
RAMasynchronous 4-19
configuration options
XC4000 Series 4-14
dual-port 4-17
edge-triggered 4-16
in CLB 4-14
initialization of 4-19
level-sensitive 4-19
readback of contents 4-65
setting mode 4-14
specifications
XC4000E 4-86
synchronous 4-16
RBUF symbol 5-10
RBUFE symbol 5-10
RCLK
pin description
XC3000 Series 4-324
XC4000 Series 4-47
XC5200 4-197
Rd/Wr
pin description
XC6200 4-273
RDY/BUSY
in configuration debug 14-31
pin description
XC3000 Series 4-324
XC4000 Series 4-47
XC5200 4-197
readback
CRC error checking
XC4000 Series 4-57
specifications
XC3000 Series 4-318
XC3000 Series 4-308
XC4000 Series 4-47, 4-64
XC5200 4-197
XChecker cable 4-65
READBACK symbol 4-64
reconfiguration
XC4000 Series 4-7
reconfiguration. See also configuration
reflow soldering 11-23
register access
XC6200 4-267
Register Clear, XC6200 4-261
register, map, XC6200 4-268
register, mask, XC6200 4-268
reliability 12-2
RESET
during power-up 14-35
in configuration debug 14-30, 14-32
in daisy chain 14-33
inititating reconfiguration 14-40
pin description
XC3000 Series 4-323
XC6200 4-273
rise time requirement in XC3000 Series 14-23
resetXC3000 Series 4-309
XC4000 Series 4-46
See also Global Set/Reset
XC6200 4-261
resistance to solvents test 12-3
resistor
IOB XC3000 Series 4-293, 4-324
XC4000 Series 4-29
XC6200 4-271
IOC 5-10, 5-12
pull-up on longline
none in XC5200 4-194
XC3000 Series 4-302
XC4000 Series 4-37
with crystal oscillator 14-20
rise/fall time on input
XC3000 Series 14-15
routing
bidirectional (bidi) buffer 4-296
buffered switch matrix 4-36
direct interconnect
XC3000 Series 4-296
XC4000EX 4-37
XC5200 4-184, 4-192
XC6200 4-256
double-length
XC4000 Series 4-35
XC5200 4-194
fastlane, XC6200 4-256
global buffer
XC4000E 4-41
XC4000EX 4-43
IOB routing
XC6200 4-263
longline
XC3000 Series 4-300, 14-15, 14-17
XC4000 Series 4-37
XC5200 4-194
magic interconnect
XC6200 4-257
multiplexer, XC6200 4-264
octal 4-40
programmable switch matrix (PSM)
19
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC3000 Series 4-296
XC4000 Series 4-35
XC6200 4-259
quad 4-36
single-length
XC4000 Series 4-35
XC5200 4-194
VersaRing (IOB routing)
XC4000 Series 4-38
XC5200 4-185, 4-196
XC3000 Series 4-295, 14-15
XC4000 Series 4-32
XC5200 4-184, 4-192
differences from XC4000 and XC3000 4-183
XC6200 4-256
XC8100 5-6
RS pin description
XC4000 Series 4-49
XC5200 4-198
S
salt atmosphere test 12-3
SC7300
high-density function blocks 3-74
SECE
pin description
XC6200 4-273
SEClk
pin description
XC6200 4-273
Secondary Global Buffer (BUFGS) 4-41, 4-48
security 3-14, 3-78, 14-36
SEData
pin description
XC6200 4-273
selection guide
CPLD 1-8
FPGA 1-6
SEReset
pin description
XC6200 4-273
Serial
pin description
XC6200 4-273
Series 8000 software 5-2, 5-16
service
overview 1-5
setup time on data input 14-42, 14-45
XC3000 Series 14-15
XC4000 Series 4-26
SGCK1 - SGCK4
clock diagram 4-42
pin description 4-48
single-length routing
XC4000 Series 4-35
XC5200 4-194
sink current. See output current
slave serial configuration mode 14-28
debugging hints 14-31
specifications
XC3000 Series 4-317
XC4000 Series 4-69, 4-79
XC5200 4-205
XC6200 4-276
XC3000 Series 4-307, 4-316
XC4000 Series 4-47, 4-55, 4-68
XC5200 4-199
XC6200 4-271
slew rate
XC3000 Series 4-293
XC4000 Series 4-28
XC5200 4-196
XC73144 3-128
XC8100 5-10
SMD. See Standard Microcircuit Drawing
SO8 package
package drawing 11-29
socket vendors 11-25
soft startup
XC3000 Series 4-309
XC4000 Series 4-28
software 2-35
ABEL 2-6, 2-7
Alliance Program 2-7
Alliance Series 2-6, 2-7, 2-11
Base System OrCAD (PC) 2-16
Base System Viewlogic (PC) 2-18
Base System Viewlogic Stand-Alone (PC) 2-20
Extended System Viewlogic Stand-Alone
(PC) 2-22
Standard System Cadence (Workstation) 2-26
Standard System Mentor V8 (Workstation) 2-24
Standard System OrCAD (PC) 2-17
Standard System Synopsys (Workstation) 2-25
Standard System third party 2-27
Standard System Viewlogic (PC) 2-19
Standard System Viewlogic (Workstation) 2-23
Standard System Viewlogic Stand-Alone
(PC) 2-21
Cadence 2-2, 2-7, 2-26
CPLD core 2-31
design flow 2-2
Design Manager 2-1
DS-290 2-32
20
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
DS-344 2-32
DS-35 2-32
DS-371 2-33
DS-380 2-32
DS-390 2-32
DS-391 2-32
DS-401 2-35
DS-502 2-30
DS-502 design flow 2-4
DS-560 2-31
DS-560 design flow 2-5
DS-571 2-34
EDIF 2-6
Floorplanner 2-1
Flow Engine 2-1
Foundation Series 2-6, 2-11
Base System (PC) 2-12
Base System with VHDL (PC) 2-13
Standard System (PC) 2-14
Standard System with VHDL (PC) 2-15
FPGA core 2-30
Hardware Debugger 2-1
HDL 2-3, 2-7
LPM 2-6
Mentor Graphics 2-2, 2-7, 2-24, 2-32
OrCAD 2-2, 2-7, 2-16, 2-17, 2-32
ordering information 2-9
overview 1-5, 2-1
programmer 10-1
PROM Formatter 2-1
Synopsys 2-7, 2-25
interface (XSI) 2-35
synthesis 2-7
Timing Analyzer 2-1, 2-3
updates 2-5
Verilog 2-6, 2-35
VHDL 2-6, 2-7, 2-13, 2-15, 2-35
Viewlogic 2-2, 2-6, 2-7, 2-18, 2-19, 2-20, 2-21, 2-22,
2-23, 2-32
XABEL-CPLD 2-34
X-BLOX 2-3, 2-8, 2-32
XC6200 4-267
XC8000 Series 2-6, 2-8
Xilinx ABEL 2-2, 2-8, 2-33, 2-34
SOIC packages
package drawings 11-29
solderability test 12-3
specifications
absolute maximum ratings
XC1700D 6-6
XC3000A 4-343
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-81
XC5200E 4-207
XC5200L 4-250
XC6200 4-275
XC8100 5-33
advance, definition of 1-1, 4-80, 4-206
boundary scan
XC4000E 4-96
CLB XC3000A 4-344
XC3000L 4-352
XC3100A 4-360
XC3100L 4-368
XC4000E 4-84
XC5200 4-209
CLC XC8100 5-35
configuration
XC3000 Series 4-310
XC4000 Series 4-66
CPU interface
XC6200 4-278
DC characteristics
XC1700D 6-6
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC5200 4-206
XC5200L 4-250
XC6200 4-275
XC8100 at 3.3 V 5-34
XC8100 at 5 V 5-33
function unit 4-276
global buffer
XC3000A 4-343
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-81
XC5200 4-207
XC6200 4-276
XC8100 5-38
IOB XC3000A 4-346
XC3000L 4-354
XC3100A 4-362
XC3100L 4-370
XC4000E 4-92
XC5200 4-211
XC6200 4-277
21
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
IOC XC8100 5-39
longline
XC4000E 4-83
XC5200 4-208
operating conditions
XC1700D 6-6
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC5200 4-206
XC5200L 4-250
XC6200 4-275
XC8100 5-33
pin-to-pin
XC4000E 4-90
XC5200 4-210
XC6200 4-277
XC8100 5-40
power-on reset
XC6200 4-276
preliminary, definition of 1-1, 4-80, 4-206
programmer 10-1
RAMXC4000E 4-86
readback
XC3000 Series 4-318
routing
XC6200 4-278
wide edge decoder
XC4000E 4-82
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC4000EX
not yet available
XC4000L
not yet available
XC4000XL
not yet available
XC5200 4-206
XC5200L 4-250
XC6200 4-275
speed grades available
high-reliability 9-1
XC3000 Series 4-339
XC3000A 4-348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-174
XC5200 4-248
XC8100 5-42
SRAM. See FPGA
Standard Microcircuit Drawing (SMD) 1-5, 9-1
Standard System
Alliance Series
Cadence (Workstation) 2-26
Mentor V8 (Workstation) 2-24
OrCAD (PC) 2-17
Synopsys (Workstation) 2-25
third party 2-27
Viewlogic (PC) 2-19
Viewlogic (Workstation) 2-23
Viewlogic Stand-Alone (PC) 2-21
Foundation Series (PC) 2-14
with VHDL 2-15
start-up after configuration 14-26
XC3000 Series 14-22
XC4000 Series 4-60
XC5200 4-203
STARTUP symbol
implementing Global 3-State 4-28
implementing Global Set/Reset 4-13
support 13-1
technical support hotline 1-5, 13-2
training 13-6
support. See also technical support
surface mount packages
moisture sensitivity 11-18
switch matrix, programmable (PSM)
XC3000 Series 4-296
XC4000 Series 4-35
XC6200 4-259
synchronous peripheral configuration mode
specifications
XC4000 Series 4-73
XC4000 Series 4-47, 4-72
XC5200 4-197
synchronous RAM 4-16
advantages of 4-14
Synopsys 2-7
interface (XSI) 2-35
software 2-25
synthesis 2-7
synthesis symbols in XC8100 5-19
T
TAP controller 14-51
tape & reel packing 11-21
TCK,TDI,TDO,TMS. See boundary scan
22
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
TCLKIN 14-18
pin description
XC3000 Series 4-324
technical support 13-1
BBS 13-3
hotline 1-5, 13-2
overview 1-5
publications 13-5
Web site 13-3
XDOCS E-mail system 13-3
XFACTS FAX system 13-3
X-TALX Xilinx network 13-3
temperature cycling test 12-3
test access port (TAP) 14-51
testing 12-2
thermal characteristics 11-1, 11-6
thermal data
PQ/HQ packages 11-11
thermal management 11-6
thermal resistance
applying data 11-9
table of 11-8
thermal shock test 12-3
theta-JA 11-7
theta-JC 11-6
time-to-market 1-3
Timing Analyzer 2-1, 2-3
timing model
XC7300 3-78
XC9500 3-15
TQ packages
package drawings 11-38
TQ100 package
package drawing 11-39
pinout table
XC3000 Series 4-331
TQ144 package
package drawing 11-40
pinout table
XC3000 Series 4-333
XC4000 Series 4-138
TQ176 package
package drawing 11-41
pinout table
XC3000 Series 4-336
XC4000 Series 4-144
TQ44 package
package drawing 11-38
TQFP packages
package drawings 11-38
training 1-5, 13-1, 13-6
locations 13-8
TrueMap 5-2
TSOP packages
package drawings 11-30
TTL input
XC3000 Series 4-293, 4-308
XC4000 Series 4-24
XC5200 4-196
XC8100 5-9, 5-12
TTL output
none in XC5200 4-196
none in XC8100 5-10
XC3000 Series 4-293
XC4000 Series 4-27
U
unbiased pressure pot test 12-2
undershoot 14-47
universal interconnect matrix
XC7300 3-76
unused I/O
XC4000 Series 4-46
updates 2-5
user registers in boundary scan 14-53
V
V/I characteristics
XC3000 Series 14-16
XC4000 Series 14-9
XC8100 5-10
vendors
forced air cooling 11-14
heatsink 11-14
socket 11-25
Verilog 2-6, 2-35
VersaBlock 4-184
VersaRing
XC4000 Series 4-38
XC5200 4-185, 4-196
VHDL 2-6, 2-7
software 2-13, 2-15, 2-35
Viewlogic 2-2, 2-6, 2-7
software 2-18, 2-19, 2-20, 2-21, 2-22, 2-23, 2-32
VO8 package
package drawing 11-30
VPP in configuration debug 14-30
VQ packages
package drawings 11-42
VQ100 package
package drawing 11-44
pinout table
23
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
XC3000 Series 4-331
XC4000 Series 4-135
VQ44 package
package drawing 11-42
pinout diagram
XC8100 5-30
VQ64 package
package drawing 11-43
pinout table
XC3000 Series 4-328
VQFP packages
package drawings 11-42
W
Wait pin description
XC6200 4-273
WAND1 symbol 4-30, 4-31
WC packages
package drawings 11-70
WC44 package
package drawing 11-70
WC68 package
package drawing 11-70
WC84 package
package drawing 11-70
Web site for Xilinx 1-1, 1-5, 13-3
WebLINX 1-1, 1-5, 13-3
weight, package 11-15
WG84 package
package drawing 11-51
wide edge decoder 4-31
specifications
XC4000E 4-82
wildcard register, XC6200 4-270
windowed packages
ceramic 11-51
CLCC
package drawings 11-70
wire. See routing
WOR2AND symbol 4-30
World Wide Web site for Xilinx 1-1, 1-5, 13-3
WS pin description
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
X
XABEL-CPLD 2-34
XACT development system 2-1
XACTstep software
overview 1-5, 2-1
X-BLOX 2-3, 2-8, 2-32
XC1700
programmer 10-1
XC1700D data sheet 6-1
XC2000 14-3
overview 14-4
use not recommended 1-1
XC3000 14-3
overview 14-4
use not recommended 1-1
XC3000 Series 4-289, 4-309, 14-3, 14-13
3-state buffer 4-293, 4-302, 14-17
5-input function 14-13
available I/O 4-326
battery backup 14-21, 14-37
CCLK frequency variation 14-21
CMOS input 4-293
CMOS output 4-293, 14-16
configurable logic block (CLB) 4-294, 14-13
configuration 4-304, 14-22
debugging hints 14-30
specifications 4-310
crystal oscillator 4-303, 4-309, 14-19
feature summary 4-289
glitch avoidance 14-14
global buffer 4-302, 14-18
hysteresis 14-15
input/output block (IOB) 4-292, 14-15
internal bus contention 14-17
on-chip oscillator 14-21
ordering information 4-340
output current 14-17
overview 14-4
performance 4-320
pin descriptions 4-323
pinout tables 4-326
power consumption 4-322, 14-18
power distribution 4-321
power-down mode 4-304, 4-322
product availability 4-339
readback 4-308
rise/fall time 14-15
routing 4-295
soft startup 4-309
specifications
configuration 4-310
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
24
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
TTL input 4-293
TTL output 4-293
V/I characteristics 14-16
XC3000A 4-341
feature summary 4-341
ordering information 4-348
overview 4-290
product availability 4-348
specifications 4-342
XC3000L 4-349
feature summary 4-349
ordering information 4-356
overview 4-290
product availability 4-356
specifications 4-350
XC3100 14-3
overview 14-4
use not recommended 1-1
XC3100A 4-357
feature summary 4-357
ordering information 4-364
overview 4-290, 14-4
product availability 4-364
specifications 4-358
XC3100L 4-365
feature summary 4-365
ordering information 4-372
overview 4-290, 14-4
product availability 4-372
specifications 4-366
XC3195
pinout table 4-338
XC4000
overview 14-4
use not recommended 1-1
XC4000 Series 4-5, 4-57, 14-3
3-state buffer 4-29
available I/O 4-176
bitstream format 4-56
boundary scan 4-50, 14-49
BSDL files 14-57
carry logic 4-21
CMOS input 4-24
CMOS output 4-27, 14-12
configurable logic block (CLB) 4-11
configuration 4-54
debugging hints 14-30
specifications 4-66
CRC error checking 4-56
edge decoder 4-31
feature summary 4-5
global buffer 4-41
ground bounce 14-10
input/output block (IOB) 4-24
interconnect 4-32
internal bus contention 14-17
low voltage device 4-5
mixed-voltage I/O 4-24, 4-27
on-chip oscillator 4-31
ordering information 4-178
output current 4-27, 14-9
output delay 14-10
pin descriptions 4-46
pinout tables 4-97
power consumption 14-12
power distribution 4-46
product availability 4-174
RAM 4-14
readback 4-64
routing 4-32
soft startup 4-28
specifications 4-79
configuration 4-66
XC4000E 4-80
TTL input 4-24
TTL output 4-27
V/I characteristics 14-9
wide edge decoder 4-31
XC4000A
overview 14-4
XC4000D
use not recommended 1-1
XC4000E
clock diagram 4-42
compared to XC4000 4-8
global buffer 4-41
overview 14-4
Primary Global Buffer (BUFGP) 4-41
Secondary Global Buffer (BUFGS) 4-41
specifications 4-80
XC4000EX
buffered switch matrix 4-36
clock diagram 4-42
compared to XC4000 4-8, 4-9
fast capture latch on inputs 4-26
FastCLK buffer (BUFFCLK) 4-26, 4-45
function generator in IOB 4-28
global buffer 4-43
Global Early buffer (BUFGE) 4-26, 4-44
Global Low-Skew buffer (BUFGLS) 4-26, 4-43
interconnect 4-32
latch in CLB 4-12
multiplexer in IOB 4-28
octal routing 4-40
overview 14-5
quad routing 4-36
25
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
routing 4-32
specifications
not yet available
VersaRing (IOB routing) 4-38
XC4000H
overview 14-5
use not recommended 1-1
XC4000L 4-5, 4-6
specifications
not yet available
XC4000XL 4-5, 4-6
specifications not yet available
XC4003E
pinout table 4-97
XC4005E/L
pinout table 4-98
XC4006E
pinout table 4-100
XC4008E
pinout table 4-102
XC4010E/L
pinout table 4-104
XC4013E/L
pinout table 4-107
XC4020E
pinout table 4-110
XC4025E
pinout table 4-113
XC4028EX/XL
pinout table 4-113
XC4036EX/XL
pinout table 4-118
XC4044EX/XL
pinout table 4-123
XC4052XL
pinout table 4-128
XC5200 4-181, 14-3
3-state buffer 4-191
5-input function 4-188
available I/O 4-248
bitstream format 4-200
boundary scan 4-191, 14-49
BSDL files 14-57
carry logic 4-189
cascade logic 4-190
CLB-to-pad diagram 4-212
CMOS input 4-196
CMOS output 4-196
compared to XC4000 and XC3000 4-182
configurable logic block (CLB) 4-184, 4-188
differences from XC4000 and XC3000 4-182
configuration 4-199
differences from XC4000 and XC3000 4-183
feature summary 4-181
general routing matrix (GRM) 4-184, 4-185, 4-192,
4-194
global buffer 4-194
global reset (GR) 4-191
input/output block (IOB) 4-196
differences from XC4000 and XC3000 4-183
interconnect 4-184, 4-192
latch in CLB 4-188
local interconnect matrix (LIM) 4-184, 4-192
logic cell (LC) 4-182, 4-184
on-chip oscillator 4-191
ordering information 4-248
output current 4-196
overview 14-5
performance 4-185
pinout tables 4-223
product availability 4-248
routing 4-184, 4-192
differences from XC4000 and XC3000 4-183
specifications 4-205, 4-206
XC5200 4-206
XC5200L 4-250
TTL input 4-196
TTL output not supported 4-196
VersaBlock 4-184
VersaRing (IOB routing) 4-185, 4-196
XC5200L 4-249
feature summary 4-249
specifications 4-250
XC5202
CLB-to-pad diagram 4-212
pinout table 4-223
XC5204
CLB-to-pad diagram 4-214
pinout table 4-226
XC5206
CLB-to-pad diagram 4-216
pinout table 4-230
XC5210
CLB-to-pad diagram 4-218
pinout table 4-235
XC5215
CLB-to-pad diagram 4-220
pinout table 4-241
XC6200 4-253
clock diagram 4-261
configuration 4-268
decoupling capacitor 4-274
designing with 4-265
electrical parameters 4-274
feature summary 4-253
function unit 4-257
26
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
block diagram 4-258
global buffer 4-257, 4-261
input/output block (IOB) 4-261
interconnect 4-256
IOB routing 4-263
map register 4-268
mask register 4-268
overview 14-5
pin descriptions 4-273
pinout tables 4-282
power consumption 4-274
power-on reset 4-272
product availability 4-286
register 4-267
Register Clear 4-261
routing 4-256, 4-263
software 4-267
specifications 4-275
wildcard register 4-270
XC6216
pinout table 4-282
XC7000
programmer 10-1
XC7200A
overview 14-5
XC7236A 3-147
XC7272A 3-163
XC7300
3.3 V or 5.5 V interface 3-77
ALU 3-74
carry lookahead 3-75
characterization data 3-135
fast function blocks 3-72
I/O block 3-76
overview 3-71, 14-5
product availability 3-71
product term assignment 3-74
timing model 3-78
XC73108
pinout table 3-121
XC73144
pinout table 3-132
XC7318
pinout table 3-87
XC7336/Q
pinout table 3-96
XC7354
pinout table 3-105
XC7372
pinout table 3-113
XC8000 Series 2-6, 2-8
XC8100 5-1
antifuse 5-3
available I/O 5-25
boundary scan 5-3, 5-11
cascade logic 5-6
CMOS input 5-9, 5-12
CMOS output 5-10
configurable logic cell (CLC) 5-5
configuration 5-13
design flow 5-2, 5-16
feature summary 5-1
global buffer 5-7
global reset (GR) 5-6
input/output cell (IOC) 5-9
interconnect 5-6
latch in CLC 5-6
leakage current 5-12
low voltage device 5-13
master reset 5-6
metastability 5-15
MicroVia 5-2, 5-12
one-time programmable (OTP) 5-2
ordering information 5-42
output current 5-10
overview 14-5
performance 5-4
pinout diagrams 5-30
pinout table 5-24, 5-25
power consumption 5-12
product availability 5-42
programming 5-13, 10-1
routing 5-6
software 2-6, 2-8, 5-2, 5-16
targeted applications 5-3
testing programming 5-15
TTL input 5-9, 5-12
TTL output not supported 5-10
V/I characteristics 5-10
XC8101
pinout table 5-26
XC8103
pinout table 5-27
XC8106
pinout table 5-28
XC8109
pinout table 5-29
XC9500
design security 3-14
endurance 3-14
FastCONNECT switch matrix 3-11
function block 3-5
I/O block 3-12
in-system programming 3-14
overview 3-3, 14-6
package availability and device I/O pins 3-5
27
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
pin locking capability 3-13
product availability 3-4
product term allocator 3-8
timing model 3-15
XC95108
pinout table 3-31
XC95144
pinout table 3-37
XC95180
pinout table 3-43
XC95216
pinout table 3-51
XC95288
pinout table 3-59
XC9536
pinout table 3-21
XC95432 3-65
XC95576 3-67
XC9572
pinout table 3-25
XCELL newsletter 1-1, 13-5
XChecker cable 2-8, 2-36
readback
XC4000 Series 4-65
XDOCS E-mail system 13-3
XFACTS FAX system 13-3
Xilinxabout the company 1-2
Alliance Program 2-7
E-mail addresses 13-4
quality assurance and reliability 12-1
technical support 1-5, 13-2
Web site 1-1, 1-5, 13-3
XCELL newsletter 1-1
Xilinx ABEL 2-2, 2-8, 2-33, 2-34
XSI software package 2-35
xtal oscillator. See crystal oscillator
X-TALX Xilinx network 13-1, 13-3
XTL1pin description
XC3000 Series 4-324
XTL2pin description
XC3000 Series 4-324
28
Index
ABC HED FG I JKLMNOPQRSTUVWXYZ
1 Introduction
2 Development System Products
3 CPLD Products
4 SRAM-Based FPGA Products
5 OTP FPGA Products
6 SPROM Products
7 3V Products
8 HardWire Products
9 Military Products
10 Programming Support
11 Packages and Thermal Characteristics
12 Testing, Quality, and Reliability
13 Technical Support
14 Product T echnical Information
15 Index
16 Sales Offices, Sales Representatives, and Distributors
Sales Offices, Sales
Representatives, and Distributors
Sales Offices, Sales Representatives, and Distributors
Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Xilinx Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
U.S. Sales Representatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
International Sales Representatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Sales Offices, Sales
Representatives, and Distributors
Table of Contents
July 15, 1996 (Version 1.01) 16-1
Headquarters
XILINX, Inc.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114
Xilinx Sales Offices
NORTH AMERICA
XILINX, Inc.
1281 Oakmead Pkwy.
Suite 202
Sunnyvale, CA 94086
(408) 245-9850
FAX: 408-245-9865
XILINX, Inc.
5690 DTC Blvd.
Suite 490W
Englewood, CO 80111
(303) 220-7541
FAX: 303-220-8641
XILINX, Inc.
15615 Alton Parkway
Suite 280
Irvine, CA 92718
(714) 727-0780
FAX: 714-727-3128
XILINX, Inc.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
(603) 891-1098
FAX: 603-891-0890
XILINX, Inc.
905 Airport Rd.
Suite 200
West Chester, PA 19380
(610) 430-3300
FAX: 610-430-0470
XILINX, Inc.
939 North Plum Grove Road
Suite H
Schaumburg, IL 60173
(847) 605-1972
FAX: 847-605-1976
XILINX, Inc.
6080-C Six Forks Road
Raleigh, NC 27609
(919) 846-3922
FAX: 919-846-8316
XILINX, Inc.
4100 McEwen, Suite 237
Dallas, TX 75244
(214) 960-1043
FAX: 214-960-0927
EUROPE
XILINX, Ltd.
Benchmark House
203 Brooklands Road
Weybridge, Surrey KT13 ORH
United Kingdom
Tel: (44) 1-932-349401
FAX: (44) 1-932-349499
XILINX SARL
Espace Jouy Technology
21, rue albert Calmette, Bt. C
78353 Jouy En Josas, Cedex
France
Tel: (33)-1-3463-01-01
FAX: (33)-1-3463-01-09
XILINX GmbH
Dorfstr. 1
85609 Aschheim
Germany
Tel: (49) 89-991549-0
FAX: (49) 89-904-4748
JAPAN
XILINX K. K.
Daini-Nagaoka Bldg. 2F
2-8-5, Hatchobori, Chuo-ku
Tokyo 104
Japan
Tel: (81) 3-3297-9191
FAX: (81) 3-3297-9189
ASIA PACIFIC
XILINX Asia Pacific
Unit 4312, Tower II
Metroplaza
Hing Fong Road
Kwai Fong, N.T.
Hong Kong
Tel: 852-2-424-5200
FAX: 852-2494-7159
North American
Distributors
Hamilton Hallmark
Locations throughout
the U.S. and Canada.
1-800-332-8638
FAX: 1-800-257-0568
Marshall Industries
Locations throughout
the U.S. and Canada.
1-800-522-0084
FAX: 818 -307-6297
Insight Electronics
Locations throughout
the U.S.
1-800-677-7716
FAX: 619-587-1380
Nu Horizons
Electronics Corp.
Locations throughout
the U.S.
(516) 226-6000
FAX: 516-226-6262
U.S. Sales
Representatives
ALABAMA
Electro Source
4835 University Sq., Ste.11
Huntsville, AL 35816
Tel: 205-830-2533
FAX: 205-830-5567
ARIZONA
Quatra Associates
4645 S. Lakeshore Dr.
Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054
ARKANSAS
Bonser-Philhower Sales
689 W. Renner Road
Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
CALIFORNIA
Quest-Rep Inc.
6494 Weathers Pl, Suite 200
San Diego, CA 92121
(619) 622-5040
FAX: 619-622-5047
Norcomp
1267 Oakmead Pkwy
Sunnyvale, CA 94086
(408) 733-7707
FAX: 408-774-1947
Norcomp
8880 W agon W ay
Granite Bay, CA 95746
(916) 791-7776
FAX: 916-791-2223
Norcomp
30101 Agoura Ct. #234
Agoura, CA 91301
(818) 865-8330
FAX: 818-865-2167
Norcomp
30 corporate park #200
Irvine, CA 92714
(714) 260-9868
FAX: 714-260-9659
COLORADO
Luscombe Engineering, Inc.
1500 Kansas Ave. Suite 1B
Longmont, CO 80501
(303) 772-3342
FAX: 303-772-8783
CONNECTICUT
John E. Boeing, Co., Inc.
101 Harvest Park, Bldg. 1A
No. Plains Industrial Road
Wallingford, CT, 06492
(203) 265-1318
FAX: 203-265-0235
DELAWARE
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
FLORIDA
Semtronic Assoc., Inc.
657 Maitland Avenue
Altamonte Springs, FL 32701
(407) 831-8233
FAX: 407-831-2844
Semtronic Assoc., Inc.
3471 N. W. 55th Street
Ft. Lauderdale, FL 33309
(305) 731-2484
FAX: 305-731-1019
Semtronic Assoc., Inc.
1467 South Missouri Avenue
Clearwater, FL 34616
(813) 461-4675
FAX: 813-442-2234
Sales Offices, Sales
Representatives, and Distributors
July 15, 1996 (Version 1.01)
Sales Offices, Sales Representatives, and Distributors
16-2 July 15, 1996 (Version 1.01)
GEORGIA
Electro Source
3280 Pointe Parkway, #1500
Norcross, GA 30092
( 770)-734-9898
FAX: 770-734-9977
IDAHO (Southwest)
Thorson Pacific, Inc.
14575 Bel-Red Road #102
Bellevue , W A 98007
(206) 603-9393
FAX: 206-603-9380
Luscombe Engineering, Inc.
670 East 3900 South #103
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
ILLINOIS
Beta Technology Sales, Inc.
1009 Hawthorn Drive
Itasca, IL 60143
(708) 250-9586
FAX: 708-250-9592
Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314-291-7958
INDIANA
Gen II Marketing,Inc.
31 E. Main St.
Carmel, IN 46032
(317) 848-3083
FAX: 317-848-1264
Gen II Marketing, Inc.
1415 Magnavox Way
Sutie 130
Ft. Wayne, IN 46804
(219) 436-4485
FAX: 219-436-1977
IOWA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
KANSAS
Advanced Technical Sales
2012 Prairie Cir. Suite A
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641
KENTUCKY
Gen II Marketing, Inc.
861 Corporate Dr. #210
Lexington, KY 40503
(606) 223-9181
FAX: (606) 223-2864
LOUISIANA (Northern)
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
LOUISIANA (Southern)
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713-789-3072
MAINE
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
MARYLAND
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(410) 644-5700
FAX: 410-644-5707
MASSACHUSETTS
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
MICHIGAN
Miltimore Sales Inc.
22765 Heslip Drive
Novi, MI 48375
(810) 349-0260
FAX: 810-349-0756
Miltimore Sales Inc.
3684 44th St., Suite 100-J
Kentwood, MI 49512
(616)-554-9292
FAX: 616-554-9210
MINNESOTA
Beta Technology
18283 Minnetonka Blvd.
Suite C
Deephaven, MN 55391
(612) 473-2680
FAX: (612)473-2690
MISSISSIPPI
Electro Source
4835 University Sq., Ste.11
Huntsville, AL 35816
( 205)-830-2533
FAX: 205-830-5567
MISSOURI
Advanced Technical Sales
2012 Prairie Cir. Suite A
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641
Advanced Technical Sales
13755 St. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314-291-7958
MONTANA
Luscombe Engineering, Inc.
670 East 3900 South #103
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
NEBRASKA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
NEVADA
Norcomp
8880 W agon W ay
Granite Bay, CA 95748
(916) 791-7776
FAX: 916-791-2223
Quatra Associates
(Las V egas)
4645 S. Lakeshore Dr., Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054
NEW HAMPSHIRE
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
NEW JERSEY (Northern)
Parallax
734 W alt Whitman Road
Melville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW JERSEY (Southern)
Delta Technical Sales, Inc.
122 N. York Road, Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
NEW MEXICO
Quatra Associates
600 Autumwood Place, S. E.
Albuquerque, NM 87123
(505) 296-6781
FAX: 505-292-2092
NEW YORK (Metro)
Parallax
734 W alt Whitman Road
Melville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW YORK
Electra Sales Corp.
333 Metro Park
Suite M103
Rochester, NY 14623
(716) 427-7860
FAX: 716-427-0614
Electra Sales Corp.
6700 Old Collamer Rd.
E. Syracuse, NY 13057
(315) 463-1248
FAX: 315-463-1717
NORTH CAROLINA
Electro Source
6050 C Six Forks Rd.
Raleigh, NC 27609
( 919)-846-5888
FAX: 919-846-0408
NORTH DAKOTA
Beta Technology
18283 Minnetonka Blvd.
Suite C
Deepaven, MN 55391
(612) 473-2680
FAX: (612) 473-2690
OHIO
Bear Marketing, Inc.
3554 Brecksville Road
PO Box 427
Richfield, OH 44286-0427
(216) 659-3131
FAX: 216-659-4823
Bear Marketing, Inc.
270 Regency Ridge Drive
Suite 115
Dayton, OH 45459
(513) 436-2061
FAX: 513-436-9137
OKLAHOMA
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
OREGON
Thorson Pacific, Inc.
9600 S.W. Oak Street,
Suite 320
Portland, OR 97223
(503) 293-9001
FAX: 503-293-9007
July 15, 1996 (Version 1.01) 16-3
PENNSYLVANIA
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
Bear Marketing, Inc.
4284 Rt. 8, Suite 211
Allison Park, PA 15101
(412) 492-1150
FAX: 412-492-1155
PUERTO RICO
Semtronic Assoc., Inc
Crown Hills
125 Carite ST.
Esq. Avenue Parana
Rio Piedras, P.R. 00926
(809) 766-0700/0701
FAX: 809-763-8071
RHODE ISLAND
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
SOUTH CAROLINA
Electro Source
6050 C Six Forks Rd.
Raleigh NC 27609
(919)-846-5888
FAX: 919-846-0408
SOUTH DAKOTA
Beta Technology
18283 Minnetonka Blvd.
Suite C
Minnetonka, MN 55345
(612) 473-2680
FAX: (612) 473-2690
TENNESSEE
Electro Source
6050 C Six Forks Rd.
Raleigh, NC 27609
Tel: (919) 846-5888
FAX: 919-846-0408
TEXAS
Bonser-Philhower Sales
8240 MoPac Expwy.
Suite 295
Austin, TX 78759
(512) 346-9186
FAX: 512-346-2393
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713-789-3072
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
TEXAS (El Paso County)
Quatra Associates
600 Autumwood Place SE
Albuquerque, NM 87123
(505) 296-6781
FAX: 505-292-2092
UTAH
Luscombe Engineering Co.
670 East 3900 South #103
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
VERMONT
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
VIRGINIA
Micro Comp, Inc.
8811Timberlake Rd.
Suite 107
Lynchburg, VA 24502
(804) 239-2626
FAX: 804-239-1333
WASHINGTON
Thorson Pacific, Inc.
14575 Bel-Red Rd.
Suite 102
Bellevue , W A 98007
(206) 603-9393
FAX: 206-603-9380
WASHINGTON
(V ancouv er , W A only)
Thorson Pacific, Inc.
9600 S.W. Oak Street
Suite 320
Portland, OR 97223
(503) 293-9001
FAX: 503-993-9007
WASHINGTON D.C.
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(410) 644-5700
FAX: 410-644-5707
WEST VIRGINIA
Bear Marketing, Inc.
4284 Rt. 8 Suite 211
Allison Park, PA 15101
(412) 492-1150
FAX:412-492-1155
WISCONSIN (Western)
Beta Technology
18283 Minnetonka Blvd.
Suite C
Minnetonka, MN 55345
(612) 473-2680
FAX: 612-473-2690
WISCONSIN (Eastern)
Beta Technology Sales, Inc.
9401 N. Beloit, Suite 409
MIlwaukee , WI 53227
(414) 543-6609
FAX: 414-543-9288
WYOMING
Luscombe Engineering, Inc.
670 East 3900 South #103
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
International Sales
Representatives
ASEAN
(Singapore, Malaysia,
Indonesia, Thailand,
Phillippines, Brunei)
MEMEC Asia Pacific Ltd.
10 Anson Rd. #14-02
International Plaza
Singapore 0207
Tel: (65) 222-4962
FAX: (65) 222-4939
AUSTRALIA
Advanced Component Dist.
Suite 5, Level 1, "Metro Centre"
124 Forest Rd. Hurstville 2220
P.O.Box 574 Hurstville 2220
Australia
Tel: (61) 2-585-5030
FAX: (61) 2-580-1095
Advanced Component Dist.
Unit 1, 14 Melrich Road
Bays water VIC 3153
Melbourne, Australia
Tel: (61) 3-9762-4244
FAX: (61) 3-9761-1754
Advanced Component Dist.
Suite 8, 328 Albany Highway
Victoria Park, WA 6100
Australia
Tel: (61) 9-472-3232
FAX: (61) 9-470-2303
Advanced Component Dist.
20D William Street
Norwood SA 5067
Australia
Tel: (61)8-364-2844
FAX: (61)8-364-2811
Advanced Component Dist.
Ste. 1, 1048 Beaudesert Rd.
Cooper Plains
Queensland, 4108
Australia
Tel: (61) 7-246-5214
FAX: (61) 7-275-3662
AUSTRIA
SEI Elbatex GmbH
Eitnergasse 6
1230 Vienna
Austria
Tel: (43) 1-866-4220
FAX: (43) 1-866-42201
BELGIUM & LUXEMBURG
SEI Rodelco NV
Limburg Stirum 243
1780 Wemmel
Belgium
Tel: (32) 2-460-0560
FAX: (32) 2-460-0271
CANADA
(BRITISH COLUMBIA)
Thorson Pacific, Inc.
4170 Still Creek Dr. #200Burn-
aby BC V6C 6C6
Canada
Tel: (604) 294-3999
FAX: (604) 473-7755
CANADA (ALBERTA)
Electro Source
6875 Royal Oak Ave.
Burnaby BC V5J 4J3
Canada
Tel: (604) 435-2533
FAX: (604)-435-2538
CANADA (OTTAWA)
Electro Source, Inc.
300 March Road, Suite 203
Kanata, Ontario K2K 2E4
Canada
Tel: (613) 592-3214
FAX: (613)-592-4256
CANADA (QUEBEC)
Electro Source
6600 TransCanada Hwy
Suite 420
Point Claire Quebec H9R 4S2
Canada
Tel: (514) 630-7486
FAX: 514-630-7421
CANADA (TORONTO)
Electro Source, Inc.
230 Galaxy Blvd.
Rexdale Ontario M9W 5R8
Canada
Tel: (416) 675-4490
FAX: (416)-675-6871
Sales Offices, Sales Representatives, and Distributors
16-4 July 15, 1996 (Version 1.01)
CHINA PEOPLE'S
REPUBLIC
MEMEC (Beijing Rep Office)
Rm 5851, Blk 8, Xiynan Hotel
No. 1 Sarliha Rd.
Beijing 100046
Tel: (86) 10-8313388 X 5851
FAX: (86) 10-2564176
MEMEC Asia Pacific Ltd.
Shanghai Rep Office
Rm. 2363, West Building
Jim Jiang Hotel
59 Mao Ming Rd.
Shanghai 200020
Tel: (86) 21-2582582 x2362
FAX: (86) 21-4723388
CZECH REPUBLIC
SEI Eljapex/Elbatex GmbH
Prechodni 11
CZ-140 00 Praha 4
Czech Republic
Tel: (02)-692-8087
FAX: (02)-471-82-03
DENMARK
Micronor A/S
P.O.Box 929
Torvet 1
DK-8600 Silkenborg
Denmark
Tel: (45) 8681-6522
FAX: (45) 8681-2827
FINLAND
Memec Finland Oy
Vernissakatu 6
01300 V antaa
Finland
Tel: (358) 0-7001-9830
FAX: (358) 0-7001-9839
FRANCE
Rep'tronic
1 Bis, rue Marcel Paul
Z.I. La Bonde
91742 Massy
France
Tel: (33) 1-69536720
FAX: (33) 1-60139198
Axess Technology
49, rue de l'Esterl
Silic 600
94663 Rungis Cedex
France
Tel: (33) 1-49-78-94-94
FAX: (33)1-49-78-03-24
Axess Technology
Route Joseph Coynel
38360 Engins
France
Tel: (33) 76-94-49-72
FAX: (33) 76-94-49-06
Axess Technology
23 le Grand Francois
La Courbatiere
38140 Rives
France
Tel: (33)76-91-45-30
FAX: (33)76-91-45-34
AVNET/EMG.
79 Rue Pierre Sémard
92 320 Chatillon
France
Tel: (33) 1 49 65 25 00
FAX : (33) 1 49 65 27 39
AVNET Composant
Sud-Ouest
Technoparc
Bat.4, V oie 5-BP404
31314 Labège Cédex
France
Tel: (33) 61 39 21 12
FAX: (33) 61 39 21 40
AVNET Composant
Aquitaine
16 Rue François Arago
Zi du Phare
33700 Mérignac
France
Tel: (33) 56 55 92 92
FAX: (33) 56 34 39 99
AVNET Composant
Rhône-Auvergne
Parc Club du Moulin à Vent
Bât 32-33, rue du Dr-G.Levy
69693 Vénissieux Cede x
France
Tel: (33) 7800-1280
FAX: (33) 7875-9597
AVNET Composant
Saint Etienne
Le Chatelet-5 place Carnot
42000 Saint etienne
France
Tel: (33) 77 92 77 66
FAX: (33) 77 92 77 30
AVNET Composant
Ouest
Technoparc-Bât.E
4 Av. des Peupliers, B.P. 43
35511 Césson Sévigné Cedex
France
Tel: (33) 99 83 84 85
FAX: (33) 99 83 80 83
AVNET Composant
Rhône-Alpes
Zac des Béalières
23 Av. de Granier
38240 Meylan
France
Tel: (33) 76 90 11 88
FAX: (33) 76 41 04 90
AVNET Composant
Nantes
Le Sillon de Bretagne
23e étage-Aile C
8 Av.des Thébaudières
44800 Saint Herblain
France
Tel: (33) 40 63 23 00
FAX: (33) 40 63 22 88
AVNET Composant
Marsielle
17, bd. Andri Aune
13006 Marseille
France
Tel: (33) 91 54 15 28
GERMANY
Avnet E2000
Stahlgruberring 12
81829 München
Germany
Tel: (49) 89-45110-01
FAX: (49) 89-45110-729
Avnet E2000
Kurfürstenstr. 130
10785 Berlin
Germany
Tel: (49) 30-214882-0
FAX: (49) 30-2141728
Avnet E2000
Friedrich-Ebert-Damm 145
22047 Hamburg
Germany
Tel: (49) 40-696-9520
FAX: (49) 40-696-2787
Avnet E2000
Benzstr. 1
70826 Gerlingen
Stuttgart Germany
Tel: (49) 7156-356-0
FAX: (49) 7156-28084
Avnet E2000
Heinrich-Hertz-Str. 52
40699 Erkrath
Düsseldorf Germany
Tel: (49) 211-92003-0
FAX: (49) 211-92003-99
Avnet E2000
Schmidtstr. 49
60326 Frankfurt/M.
Germany
Tel: (49) 69-973804-0
FAX: (49) 69-7380712
Avnet E2000
Fûrther Str. 212
90429 Nürnberg
Germany
Tel: (49) 911-93149-0
FAX: (49) 911-320821
Metronik GmbH
Leonhardsweg 2
82008 Unterhaching
München Germany
Tel: (49) 89-611080
FAX: (49) 89-61108110
Metronik GmbH
Zum Lonnenhohl 38
44319 Dortmund
Germany
Tel: (49) 231-927110-0
FAX: (49) 231-927110-99
Metronik GmbH
Carl-Zeiss Str.6
25451 Quickborn
Hamburg Germany
Tel: (49) 4106-773050
FAX: (49) 4106-773052
Metronik GmbH
Osmiastr. 9
69221 Dossenheim
Mannheim Germany
Tel: (49) 6221-87044
FAX: (49) 6221-87046
Metronik GmbH
Pilotystr. 27/29
90408 Nürnberg
Germany
Tel: (49) 911-363536
FAX: (49) 911-353986
Metronik GmbH
Löwenstr. 37
70597 Stuttgart
Germany
Tel: (49) 711-7640333
FAX: (49) 711-7655181
Metronik GmbH
Schönauer Str. 113
04207 Leipzing
Germany
Tel: (49) 341-4239413
FAX: (49) 341-4239424
Metronik GmbH
Bahnstrasse 9
65205 Wiesbaden
Germany
Tel: (49) 611-97384-0
FAX: (49) 611-97384-18
Metronik GmbH
Franz-Schubert-Str.41
16548 Glienicke
Berlin Germany
Tel: (49) 33056-845-0
FAX: (49) 33056-845-50
Intercomp
Am Hochwald 42
D-82319
Starnberg Germany
Tel: (49) 8151-16044
FAX: (49) 8151-79270
July 15, 1996 (Version 1.01) 16-5
Intercomp
Kniebisstr. 40/1
78628 Rottweil
Stuttgart Germany
Tel: (49) 741-1 48 45
FAX: (49) 741-1 52 20
Intercomp
Schustergasse 35
55278 Köngernheim
Frankfurt Germany
Tel: (49) 6737-9881
FAX: (49) 6737-9882
Intercomp
Hans Ackermann Str.23
91322 Grâfenberg
Germany
Tel: (49) 9192-998917
FAX: (49) 9192-998918
GREECE
Peter Caritato & Assoc. S. A.
Llia Iliot, 31
Athens 11743 Greece
Tel: (30) 1-9020115
FAX: (30) 1-9017024
Semicon
104 Aeolu Str.
10564 Athens
Greece
Tel: (30)-1-325 3126
FAX: (30) 1-321-6063
HONG KONG
MEMEC Asia Pacific Ltd.
Unit No. 2308-2319, Tower I
Metroplaza, Hing Fong Road,
Kwai Fong, N.T.
Hong Kong
Tel: (852) 2410 2780
FAX: (852) 2401 2518
HUNGARY
SEI Dataware KFT/Elbate x GmbH
Angol Utca 22
1149 Budapest
Hungary
Tel: (36) 1-163-5081
FAX: (36) 1-251-5517
SEI Eljapex/Elbatex GmbH
Vaci u 202
1138 Budapest
Hungary
Tel: (36) 1-269-9093/95
FAX: (36) 1-269-9096
INDIA
Core El Micro Systems
45131 Manzanita Court
Fremont, California 94539
USA
Tel:(510) 770-1066
FAX: 510-657-1525
Core El Logic System
ETD, Crompton Greaves Ltd.
First Floor, Surya Bhawan
Fergusson College Rd.
Pune 411005 India
Tel: (91) 212-323982
FAX: (91) 212-332838
IRELAND
Memec Ireland Ltd.
Gardner House
Bank Place
Limerick
Ireland
Tel: (353) 61-411842
FAX: (353) 61-411888
ISRAEL
E.I.M International Ltd.
9 Hashiloach Street
P.O. Box 4000
Kiryat Matalon
P etach Tikva 49130
Israel
Tel: (972) 3-92 33257
FAX: (972) 3-924 4857
ITALY
ACSIS S.R.L.
Via Alberto Mario. 26
20149 Milano, Italy
Tel: (39) 2-48022522
FAX: (39) 2-48012289
Silverstar-Celdis
Viale Fulvio Testi 280
20126 Milano, Italy
Tel: (39) 2-66125 1
FAX: (39) 2-66101359
Silverstar-Celdis
Via Collamarini, 22
40138 Bologna, Italy
Tel: (39) 51-538500
FAX: (39) 538831
Silverstar-Celdis
Via Paisiello,30
00198 Roma, Italy
Tel: (39) 6-8848841
FAX: (39) 6-8553228
Silverstar-Celdis
Centro Direzionale Benelli
Via Del Monaco, 16
61100 Pesaro, Italy
Tel: (39) 721-26560
FAX: (39) 721-400896
Silverstar-Celdis
Via A.da Noli 6
50127 Firenze, Italy
Tel: (39) 55-43 5125
FAX: (39) 55-43 77184
Silverstar-Celdis
Centro Piero Della Francesca
Corso Svizzera, 185 Bis
10149 Torino, Italy
Tel: (39) 11 77 10082
FAX: (39) 11 77 64921
Silverstar-Celdis
Via G. Antonio Resti 63
00143 Roma, Italy
Tel: (39) 6 519 57527
FAX: (39) 6 504 3330
Silverstar-Celdis
Via.delle Indus.13
35010 Limena
Padova, Italy
Tel: (39) 49 88 40044
FAX: (39) 49 88 41079
Silverstar-Celdis
Via Famagosta 1/5
17100 Savona, Italy
Tel: (39) 19 81 5090
FAX: (39) 19 81 5091
JAPAN
Okura Electronics Co., Ltd.
3-6, Ginza 2-chome,
Chuo-ku,
Tokyo, 104 Japan
Tel: (81) 3-3564-6871
FAX: (81) 3-3564-6870
Okura Electronics
Service Co., Ltd.
Yokota Bldg
Ginza 2-11-5
Chuo-Ku,
Tokyo, 104 Japan
Tel: (81) 3-3545-2360
FAX: (81) 3-3545-2351
Tokyo Electron Ltd.
TBS Broadcasting Center
5-3-6- Akasaka, Mingto-Ku
Tokyo, 163 Japan
Tel: (81) 3-5561-7212
FAX: (81) 3-5561-7389
Towa Elex Co., Ltd.
Unity Bldg. 5F
6-5 Nihonbashi Tomisawa-cho
Chuo-Ku, Tokyo 103
Japan
Tel: (81) 3-5640-1241
FAX: (81) 3-5640-1240
Varex Co., Ltd.
Nippo Shin-Osaka No. 2 Bldg.
1-8-33, Nishimiyahara,
Yodogawa-ku,
Osaka, 532 Japan
Tel: (81) 6-394-5201
FAX: (81) 6-394-5449
Marubun Corporation
8-1 Odenma-cho, Nihonbashi
Chuo-ku Tokyo , 103
Japan
Tel: (81) 3-3639-5210
FAX: (81) 3-3639-3727
Kaga Electronics Co., Ltd.
1-26-1 Otowa
Bunkyo-ky
Tokay 112, Japan
Tel: (81) 3-3942-6224
FAX: (81) 3-3942-6215
THE NETHERLANDS
SEI Rodelco BV
P.O.Box 6824
Takkebijsters 2
4802 HV Breda
The Netherlands
Tel: (31) 76-5722700
FAX: (31) 76-5710029
NEW ZEALAND
Advanced Component Dist.
P.O.Box 24-500
Royal Oak, Auckland
New Zeland
Tel: (64) 9-636-5984
FAX: (64) 9-636-5985
Advanced Component Dist
2 Heath St.
W ainviomata, W ellington
New Zealand
Tel: (64) 4-564-4902
FAX: (64) 4-564-2243
Advanced Component Dist.
Worchester Chambers
69 Worcester St.
Christchurch
New Zeland
Tel: (64) 3-379-3889
FAX: (64) 3-379-3072
NORWAY
BIT Elektronikk AS
Smedsvingen 4
P.O. Box 194
1360 Nesbru
Norway
Tel: (47) 66-98 13 70
FAX: (47) 66-98 13 71
POLAND
SEI NEljapex/Elbatex GmbH
Ul. Wilcza 50/52
PL-00679 Warszawa
Poland
Tel: (48) 2621 7122
FAX: (48) 2623 0605
Sales Offices, Sales Representatives, and Distributors
16-6 July 15, 1996 (Version 1.01)
PORTUGAL
TECMIC
Taguspark
Edificio Inovacao 1, no 222
2780 Oeiras
Portugal
Tel: (351) 1-422-8800
FAX: (351) 1-422-8809
RUSSIA
Scan
10/32 "B" Druzhby St.
117330 Moskva
Russia
Tel: (7) 095-1436641
FAX: (7) 095-9382247
Scan
42 Ordjonikidze
196143 St. Petersburg
Russia
Tel: (7) 812 299 7028
FAX: (7) 812 264 6000
Vostorg
3 Rue des Acacias
91370 Verrieres le Buisson
France
Tel: (33) 1-6920-4613
FAX: (33) 1-6011-5543
SINGAPORE
MEMEC Asia Pacific Ltd.
Singapore
Representative Office
10 Anson Road #14-02
International Plaza
Singapore 079903
Tel: (65)-222-4962
FAX: (65)-222-4939
Frontline Technologies Ptc. Ltd
2 Science Park Dr. #57
The Faraday
Singapore Science Park
Singapore 118222
Tel: (65)-779111
FAX: (65) 779-4455
SLOVAK REPUBLIC
Elbatex Slovensko
Svrcia ul
SK 84104 Bratislava
Tel: (42) 7 722 137
FAX: (42) 7 722 139
SLOVENIA/CROATIA
SEI Eljapex/Elbatex GmbH
Stegne 19, PO Box 19
SLO-61-117 Ljubljana
Tel: (61) 191-126-507
FAX: (61) 192-398-507
SOUTH AFRICA
Avnet - ASD
P.O. Box 3853
Pretoria 2128
South Africa
Tel: (27) 11-444-2333
FAX: (27) 11-444-1706
SOUTH AMERICA
DTS Ltda.
Rosas 1444
Santiago
Chile
Tel: (56) 2-697-0991
FAX: (56) 2-699-3316
Reycom Electronica S.A.
Bdo. de Irigoyen
972 Piso 2do "B"
1304 Buenos Aires
Argentina
Tel: (54) 1-304-2018
FAX: (54) 1-304-2010
Hitech El. Indl. Coml. Ltda.
Rau Branco de Moraes 489
Ch. Santo Antônio São Paulo
04718-010 - SP - Brazil
Tel: (55) 11-882-4000
FAX: (55) 11-882-4100
SOUTH KOREA
MEMEC Asia Pacific Ltd.
4FL, Je Woong Bldg.,176-11
Nonhyun-dong
Kangnam-ku
Seoul,135-010, South Korea
Tel: (82) 2-518-8181
FAX: (82) 2-518-9419
Hyunmyung Electronics Co. Ltd.
Dukwha Bld. 401
44-17, Seogyu-dong
Mapo-Gu Seoul
South Korea
Tel: (02) 2-277-7061
FAX: (02) 2-277-8470
SOUTHEAST ASIA
MEMEC Asia Pacific Ltd.
Unit No.2308-2319, Tower I
Metroplaza, Hing Fong Road,
Kwai Fong, N.T.
Hong Kong
Tel: (852) 410-2780
FAX: (852) 401-2518
SPAIN
SEI ADM Electronica, SA
Calle Tomas Breton,
no 50, 3-2 Planta
28045 Madrid
Spain
Tel: (34) 1-5304121
FAX: (34) 1-5300164
SEI ADM Electronica, SA
Mallorca 1
08014 Barcelona
Spain
Tel: (34) 3 426 6892
FAX: (34) 3-4250544
email:amdelec@lander.es
SEI ADM Electronica, SA
Herriko Gudarien, 8-1B
48200 Durango (Vizcaya)
Spain
Tel: (34)-4-6201572
FAX: (34)-4- 6202331
SWEDEN
DipCom Electronics AB
Box 1230
Torshamnsgatan 35
S-164 28 Kista
Sweden
Tel: (46) 8 752 24 80
FAX: (46) 8 751 3649
SWITZERLAND
Fenner Elektronik AG
Abteilung Bauteile
Gewerbestr. 10
CH-4450 Sissach
Switzerland
Tel: (41) 61 975 00 00
FAX: (41) 61 971 5608
TAIWAN
MEMEC Asia Pacific Ltd.
14F, No. 46, Lane 11
Kuang Fu North Road
Taipei
Taiwan R.O.C.
Tel: (886) 2-760-2028
FAX: (886) 2-765-1488w
TURKEY
Aztech Electronics Corp
524 42nd St. #200
Union City,
New Jersey 07087
Tel: (201) 867-2271
FAX: (201) 867-2162
Aztech Electronik
Farabi Sokak No.44/4
06690 Cankaya
Ankara
Turkey
Tel: (90) 312 467-9952
FAX: (90) 312467-9828
UK
Microcall Ltd.
17 Thame Park Road
Thame
Oxon OX9 3XD
UK
Tel: (44) 1-844-261939
FAX: (44) 1-844-261678
Cedar Technologies
Unit One Old Barns
Roycote Lane Farm
Milton Common
Oxfordshire OX9 2NZ
UK
Tel: (44) 1-844-278278
FAX: (44)1-844-278-378
Cedar Technologies
32 Enterprise House
Springkerse Business Park
Striling SK7 7UF
UK
Tel: (44) 1786-446221
FAX: (44) 1786-278378
Avnet EMG Ltd.
Jubilee House
Jubilee Road
Letchworth
Hertfordshire SG6 1QH
UK
Tel: (44) 1-462-488500
FAX: (44) 1-462-488567
MEMEC PLC
17 Thame Park Road
Thame
Oxfordshire OX9 3XD
UK
Tel: (44) 1-1844 261919
FAX: (44) 1-1844 261683