74LVT273BQ,115 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at

3.3 V.

This device has eight edge-triggered D-type ﬂip-ﬂops with individual D inputs and Q

outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all ﬂip-ﬂops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the

LOW-to-HIGH clock transition, is transferred to the corresponding ﬂip-ﬂop’s Q output.

All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage

level on the MR input. The device is useful for applications where only the true output is

required and the CP and MR are common elements.

2. Features

nEight edge-triggered D-type ﬂip-ﬂops

nBuffered common clock and asynchronous master reset

nInput and output interface capability to systems at 5 V supply

nTTL input and output switching levels

nInput and output interface capability to systems at 5 V supply

nOutput capability: +64 mA/−32 mA

nLatch-up protection

uJESD78 Class II exceeds 500 mA

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

nBus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

nLive insertion/extraction permitted

nPower-up reset

nNo bus current loading when output is tied to 5 V bus

74LVT273

3.3 V octal D-type ﬂip-ﬂop

Rev. 03 — 10 September 2008 Product data sheet

Product data sheet Rev. 03 — 10 September 2008 2 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVT273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;

body width 7.5 mm SOT163-1

74LVT273DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;

body width 5.3 mm SOT339-1

74LVT273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

74LVT273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 20 terminals;

body 2.5 ×4.5 ×0.85 mm

SOT764-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

mna763

D7 MR

CP Q0

mna764

11 C1

1D 2

Product data sheet Rev. 03 — 10 September 2008 3 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

Fig 3. Logic diagram

001aae056

FF8

FF7

FF6

FF5

FF4

FF3

FF2

CPCPCPCP

FF1

Product data sheet Rev. 03 — 10 September 2008 4 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 4. Pin conﬁguration for SO20 and (T)SSOP20 Fig 5. Pin conﬁguration for DHVQFN20

74LVT273

MR VCC

Q0 Q7

D0 D7

D1 D6

Q1 Q6

Q2 Q5

D2 D5

D3 D4

Q3 Q4

GND CP

001aai737

001aai738

74LVT273

Transparent top view

GND(1)

D2 D5

Q2 Q5

Q1 Q6

D1 D6

D0 D7

Q0 Q7

GND

VCC

912

8 13

7 14

6 15

5 16

4 17

3 18

2 19

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

MR 1 master reset input (active LOW)

Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output

D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input

GND 10 ground (0 V)

CP 11 clock pulse input (active on rising edge)

VCC 20 positive supply voltage

Product data sheet Rev. 03 — 10 September 2008 5 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

6. Functional description

[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;

X = Don’t care; ↑ = LOW-to-HIGH clock transition; Q0 = output as it was.

7. Limiting values

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.

For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.

For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.

8. Recommended operating conditions

Table 3. Function selection

Inputs Outputs Operating mode

MR CP Dn Qn

L X X L Reset (clear)

H↑h H Load 1

H↑l L Load 0

H L X Q0 Retain state

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

VIinput voltage [1] −0.5 +7.0 V

VOoutput voltage Output in OFF or HIGH state [1] −0.5 +7.0 V

IIK input clamping current VI < 0 V −50 - mA

IOK output clamping current VO < 0 V −50 - mA

IOoutput current output in LOW state - 128 mA

output in HIGH state −64 - mA

Tstg storage temperature −65 +150 °C

Tjjunction temperature [2] - 150 °C

Ptot total power dissipation Tamb = −40 °C to +85 °C[3] 500 mW

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.7 - 3.6 V

VIinput voltage 0 - 5.5 V

IOH HIGH-level output current −32 - - mA

Product data sheet Rev. 03 — 10 September 2008 6 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

9. Static characteristics

IOL LOW-level output current - - 64 mA

Tamb ambient temperature in free air −40 - +85 °C

∆t/∆V input transition rise and fall rate;

output enabled - - 10 ns/V

Table 5. Recommended operating conditions

…continued

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

VIK input clamping voltage VCC = 2.7V; IIK = –18 mA −1.2 −0.9 - V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8

VOH HIGH-level output voltage VCC = 2.7 V to 3.6V; IOH =−100 µAV

CC − 0.2 VCC − 0.1 - V

VCC = 2.7 V; IOH =−8 mA 2.4 2.5 - V

VCC = 3.0 V; IOH =−32 mA 2.0 2.2 - V

VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 µA 0.1 0.2 V

VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V

VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V

VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V

VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V

VOL(pu) power-up LOW-level

output voltage VCC = 3.6 V; IO= 1 mA; VI= GND or VCC [2] - 0.13 0.55 V

IIinput leakage current input pins

VCC = 0 V or 3.6 V; VI= 5.5 V - 1 10 µA

control pins

VCC = 3.6 V; VI=V

CC or GND - ±0.1 ±1µA

data pins [3]

VCC = 3.6 V; VI=V

CC - 0.1 1 µA

VCC = 3.6 V; VI=0V −5−1−µA

IOFF power-off leakage current VCC = 0 V; VIor VO=0Vto4.5V - 1 ±100 µA

ILO output leakage current VCC = 3.0 V; VO = 5.5 V; output HIGH - 60 125 µA

IBHL bus hold LOW current VCC = 3.0 V; VI= 0.8 V [4] 75 150 - µA

IBHH bus hold HIGH current VCC = 3.0 V; VI= 2.0 V - −150 −75 µA

IBHHO bus hold HIGH overdrive

current VCC = 3.6 V; VI = 0 V to 3.6 V - - 500 µA

IBHLO bus hold LOW overdrive

current VCC = 3.6 V; VI = 0 V to 3.6 V −500 - - µA

Product data sheet Rev. 03 — 10 September 2008 7 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.

[2] For valid test results data must not be loaded into the ﬂip-ﬂops (or latches) after applying the power.

[3] Unused pins at VCC or GND.

[4] This is the bus hold overdrive current required to force the input to the opposite logic state.

[5] Increase in supply current for each input at the speciﬁed voltage level other than VCC or GND

10. Dynamic characteristics

ICC supply current VCC = 3.6 V; VI=V

CC or GND; IO=0A

outputs HIGH - 0.13 0.19 mA

outputs LOW - 3 12 mA

∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V;

one input = VCC −0.6 V

other inputs at VCC or GND

[5] - 0.1 0.2 mA

CIinput capacitance VI= 0 Vor 3.0 V - 4 - pF

Table 6. Static characteristics

…continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

tPLH LOW to HIGH propagation delay CP to Qn; Figure 6

VCC = 2.7 V - - 6.3 ns

VCC = 3.3 V ± 0.3 V 1.7 3.5 5.5 ns

tPHL HIGH to LOW propagation delay CP to Qn; Figure 6

VCC = 2.7 V - - 5.9 ns

VCC = 3.3 V ± 0.3 V 1.9 3.5 5.5 ns

MR to Qn; see Figure 7

VCC = 2.7 V - - 6.2 ns

VCC = 3.3 V ± 0.3 V 1.3 3.2 6.2 ns

tsu set-up time Dn to CP HIGH; see Figure 7 [2]

VCC = 2.7 V 2.7 - - ns

VCC = 3.3 V ± 0.3 V 2.3 1.0 - ns

Dn to CP LOW; see Figure 7

VCC = 2.7 V 2.7 - - ns

VCC = 3.3 V ± 0.3 V 2.3 1.0 - ns

thhold time Dn to CP HIGH; see Figure 8 [3]

VCC = 2.7 V 0 - - ns

VCC = 3.3 V ± 0.3 V 0 −0.6 - ns

Dn to CP LOW; see Figure 8

VCC = 2.7 V 0 - - ns

VCC = 3.3 V ± 0.3 V 0 −0.6 - ns

Product data sheet Rev. 03 — 10 September 2008 8 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

[1] Typical values are measured at Tamb =25°C and VCC = 3.3 V

[2] tsu is the same as tsu(L) and tsu(H)

[3] th is the same as th(L) and th(H)

[4] tW is the same as tWL and tWH

11. Waveforms

tWpulse width CP input HIGH or LOW; see Figure 6 [4]

VCC = 2.7 V 3.3 - - ns

VCC = 3.3 V ± 0.3 V 3.3 1.5 - ns

MR input LOW; see Figure 7

VCC = 2.7 V 3.3 - - ns

VCC = 3.3 V ± 0.3 V 3.3 1.5 - ns

trec recovery time see Figure 7

VCC = 2.7 V 3.2 - - ns

VCC = 3.3 V ± 0.3 V 2.7 1.0 - ns

fmax maximum frequency CP input; see Figure 7 150 - - MHz

Table 7. Dynamic characteristics

…continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

see Table 8 for measurement points.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 6. CP Input to Qn output propagation delays and clock pulse width and maximum frequency

001aai739

CP input

Qn output

tPHL tPLH

tWH

1/fmax

VOH

GND

VOL

tWL

Table 8. Measurement points

Input Output

VIVMVM

2.7 V 1.5 V 1.5 V

Product data sheet Rev. 03 — 10 September 2008 9 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

see Table 8 for measurement points.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7. MR pulse width, MR to CP recovery time and MR to Qn delay

001aai740

MR input

CP input

Qn output

tPHL

tWL trec

GND

VOL

GND

VOH

see Table 8 for measurement points.

VOL and VOH are typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predicable output performance.

Fig 8. Data set-up and hold times

001aai741

GND

th(H)

tsu(H) th(L)

tsu(L)

VOH

VOL

Qn output

CP input

Dn input

Product data sheet Rev. 03 — 10 September 2008 10 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

Test data is given in given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 9. Load circuitry for switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aaf615

VCC

VIVO

DUT

RTRL

PULSE

GENERATOR

Table 9. Test data

Input Load

VIRepetition rate tWtr, tfRLCL

2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω50 pF

Product data sheet Rev. 03 — 10 September 2008 11 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

12. Package outline

Fig 10. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 03 — 10 September 2008 12 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

Fig 11. Package outline SOT339-1 (SSOP20)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQ(1)

Zywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 7.4

7.0 5.4

5.2 0.65 7.9

7.6 0.9

0.7 0.9

0.5 8

0.131.25 0.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT339-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

110

20 11

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

max.

Product data sheet Rev. 03 — 10 September 2008 13 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

Fig 12. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 03 — 10 September 2008 14 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

Fig 13. Package outline SOT764-1 (DHVQFN20)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.6

4.4

3.15

2.85

2.6

2.4 1.15

0.85

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT764-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT764-1

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

19 12

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 03 — 10 September 2008 15 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

BiCMOS Integrated Bipolar junction transistors and CMOS

CDM Charged Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVT273_3 20080910 Product data sheet - 74LVT273_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Title changed to 3.3 V octal D-type ﬂip-ﬂop

•Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package

added.

•Table 4 “Limiting values” Tj and Ptot values added.

74LVT273_2 19980219 Product speciﬁcation - -

Product data sheet Rev. 03 — 10 September 2008 16 of 17

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

15. Legal information

16. Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.1 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.2 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

16.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LVT273

3.3 V octal D-type ﬂip-ﬂop

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 September 2008

Document identifier: 74LVT273_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

16.1 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16.2 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16.3 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

17 Contact information. . . . . . . . . . . . . . . . . . . . . 16

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17