HD74ALVCH162334T - Hitachi Semiconductor

HD74ALVCH162334

16-bit Universal Bus Driver with 3-state Outputs

ADE-205-210 (Z)

Preliminary

1st. Edition

December 1997

Description

This HD74ALVCH162334 is a 16-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation.

Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the

transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip

flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the

driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All

outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and

undershoot.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±12 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

• All outputs have equivalent 26 Ω series resistors, so no external resistors are required

HD74ALVCH162334

Function Table

Inputs Output Y

OE LE CLK A

HXXXZ

L LXLL

L LXHH

LH↑LL

LH↑HH

L H L or H X Y0 *1

H : High level

L : Low level

X : Immaterial

Z : High impedance

↑ : Low to high transition

Note: 1. Output level before the indicated steady state input conditions were established.

HD74ALVCH162334

Pin Arrangement

(Top view)

VCC

GND

Y10

GND

Y11

Y12

Y13

Y14

GND

Y16

Y15

24 25

A16

A15

GND

A14

A13

A12

A11

GND

A10

GND

CLK

GND

VCC

HD74ALVCH162334

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage VCC –0.5 to 4.6 V

Input voltage *1 VI–0.5 to 4.6 V

Output voltage *1, 2 VO–0.5 to VCC +0.5 V

Input clamp current IIK –50 mA VI < 0

Output clamp current IOK ±50 mA VO < 0 or VO > VCC

Continuous output current IO±50 mA VO = 0 to VCC

VCC, GND current / pin ICC or IGND ±100 mA

Maximum power dissipation

at Ta = 55°C (in still air) *3 PT0.85 W TSSOP

Storage temperature Tstg –65 to 150 °C

Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or

any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp

current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C

and a board trace length of 750 mils.

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage VCC 2.3 3.6 V

Input voltage VI0V

CC V

Output voltage VO0V

CC V

High level output current IOH —–6mAV

CC = 2.3 V

—–8 V

CC = 2.7 V

— –12 VCC = 3.0 V

Low level output current IOL — 6 mA VCC = 2.3 V

—8 V

CC = 2.7 V

—12 V

CC = 3.0 V

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V

Operating temperature Ta–40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

HD74ALVCH162334

Logic Diagram

To fifteen other channels

CLK

2Y1

HD74ALVCH162334

Electrical Characteristics (Ta = –40 to 85°C)

Item Symbo

lVCC (V) Min Max Unit Test Conditions

Input voltage VIH 2.3 to 2.7 1.7 — V

2.7 to 3.6 2.0 —

VIL 2.3 to 2.7 — 0.7

2.7 to 3.6 — 0.8

Output voltage VOH 2.3 to 3.6 VCC–0.2 — V IOH = –100 µA

2.3 1.9 — IOH = –4 mA, VIH = 1.7 V

2.3 1.7 — IOH = –6 mA, VIH = 1.7 V

3.0 2.4 — IOH = –6 mA, VIH = 2.0 V

2.7 2.0 — IOH = –8 mA, VIH = 2.0 V

3.0 2.0 — IOH = –12 mA, VIH = 2.0 V

VOL 2.3 to 3.6 — 0.2 IOL = 100 µA

2.3 — 0.4 IOL = 4 mA, VIL = 0.7 V

2.3 — 0.55 IOL = 6 mA, VIL = 0.7 V

3.0 — 0.55 IOL = 6 mA, VIL = 0.8 V

2.7 — 0.6 IOL = 8 mA, VIL = 0.8 V

3.0 — 0.8 IOL = 12 mA, VIL = 0.8 V

Input current IIN 3.6 — ±5µAV

IN = VCC or GND

IIN (hold) 2.3 45 — VIN = 0.7 V

2.3 –45 — VIN = 1.7 V

3.0 75 — VIN = 0.8 V

3.0 –75 — VIN = 2.0 V

3.6 — ±500 VIN = 0 to 3.6 V *1

Off state output current IOZ 3.6 — ±10 µAV

OUT = VCC or GND

Quiescent supply current ICC 3.6 — 40 µAV

IN = VCC or GND

∆ICC 3.0 to 3.6 — 750 µAV

IN = one input at (VCC–0.6) V,

other inputs at VCC or GND

Note: 1. This is the bus hold maximum dynamic current required to switch the input from one state to

another.

HD74ALVCH162334

Switching Characteristics (Ta = –40 to 85°C)

Item Symbol VCC (V) Min Typ Max Unit FROM

(Input) TO

(Output)

Maximum clock frequency fmax 2.5±0.2 150 — — MHz

2.7 150 — —

3.3±0.3 150 — —

Propagation delay time tPLH 2.5±0.2 1.0 — 3.9 ns A Y

tPHL 2.7 — — 4.5

3.3±0.3 1.1 — 3.9

2.5±0.2 1.0 — 5.0 LE Y

2.7 — — 6.0

3.3±0.3 1.3 — 5.0

2.5±0.2 1.0 — 4.9 CLK Y

2.7 — — 5.4

3.3±0.3 1.0 — 4.9

Output enable time tZH 2.5±0.2 1.0 — 5.4 ns OE Y

tZL 2.7 — — 6.4

3.3±0.3 1.1 — 5.4

Output disable time tHZ 2.5±0.2 1.0 — 5.0 ns OE Y

tLZ 2.7 — — 5.1

3.3±0.3 1.7 — 5.0

Input capacitance CIN 3.3 — 5.5 — pF Control inputs

3.3 — 6.0 — Data inputs

Output capacitance CO3.3 — 8.0 — pF Outputs

HD74ALVCH162334

Switching Characteristics (Ta = –40 to 85°C) (cont)

Item Symbol VCC (V) Min Typ Max Unit FROM (Input)

Setup time tsu 2.5±0.2 1.4 — — ns Data before CLK↑

2.7 1.7 — —

3.3±0.3 1.5 — —

2.5±0.2 1.2 — — Data before LE↑

2.7 1.6 — — CLK “H”

3.3±0.3 1.3 — —

2.5±0.2 1.4 — — Data before LE↑

2.7 1.5 — — CLK “L”

3.3±0.3 1.2 — —

Hold time th2.5±0.2 0.9 — — ns Data after CLK↑

2.7 0.8 — —

3.3±0.3 0.9 — —

2.5±0.2 1.2 — — Data after LE↑

2.7 1.1 — — CLK “H” or “L”

3.3±0.3 1.1 — —

Pulse width tw2.5±0.2 3.3 — — ns LE “L”

2.7 3.3 — —

3.3±0.3 3.3 — —

2.5±0.2 3.3 — — CLK “H” or “L”

2.7 3.3 — —

3.3±0.3 3.3 — —

HD74ALVCH162334

Test Circuit

500 ΩC = 50 pF

500 ΩS1

See under table

GND

OPEN

Load Circuit for Outputs

Symbol

t / t

PLH PHL OPEN

GND

2 × V 6.0 V

t / t

ZH HZ

t / t

ZL LZ

t / t / t

su h w OPEN

GND

Vcc=2.7V,

3.3±0.3V

Vcc=2.5±0.2V

Note: 1. CL includes probe and jig capacitance.

HD74ALVCH162334

Waveforms – 1

tPLH tPHL

VOH

VOL

GND

VIH

Vref Vref

Input

Output

10 %

90 %

trf

10 %

90 %

Waveforms – 2

tsu th

GND

VIH

GND

VIH

GND

VIH

Timing Input

Data Input

Input

10 %

90 %

Vref

Vref Vref

Vref

HD74ALVCH162334

Waveforms – 3

Vref1

Vref2

tZL tLZ

tZH tHZ VOH

VOL

VCC

V +0.15 V

V –0.15 V

V +0.3 V

V –0.3 V

VCC

Waveform - A

Output

Control

Waveform - B

GND

VIH

TEST

VIH

Vref

Vref1

Vref2

1/2 V 1.5 V

2.7 V

VOH1

VOL1

3.0 V

GND GND

Vcc=2.7V,

3.3±0.3V

Vcc=2.5±0.2V

10 % 10 %

90 % 90 %

Vref

≈VOH1

≈VOL1

Notes: 1. All input pulses are supplied by generators having the following characteristics :

PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)

PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)

2. Waveform – A is for an output with internal conditions such that the output is low except

when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high except

when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

HD74ALVCH162334

Package Dimensions

Unit : mm

0.08 M

0.20

124

2548

+0.1

–0.05

+0.3

–0.1

12.50

+0.3

–0.1

6.10

0.50

0.10

0.65 Max

1.20 max

0.05 Min

0.15 ± 0.05

8.10 ± 0.3

10° Max

0.50 ± 0.1

Hitachi code

EIAJ code

JEDEC code

TTP-48DC

—

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