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LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

LM4550B AC '97 Rev 2.1 Multi-Channel Audio Codec With Stereo Headphone Amplifier,

Sample Rate Conversion and TI 3D Sound

1 Features 2 Applications

1• AC '97 Rev 2.1 Compliant • Desktop PC Audio Systems on PCI Cards, AMR

Cards, or With Motherboard Chips Sets Featuring

• High Quality Sample Rate Conversion From 4 kHz AC Link

to 48 kHz in 1 Hz Increments • Portable PC Systems as on MDC Cards, or with a

• Supports up to 6 DAC Channel Systems With Chipset or Accelerator Featuring AC Link

Multiple LM4550Bs or With Other TI LM45xx

Codecs • General Audio Frequency Systems Requiring 2, 4

or 6 DAC Channels and/or up to 8 ADC Channels

• Unique TI Chaining Function Shares a Single

Controller SDATA_IN Pin Among Multiple Codecs • Automotive Telematics

• Stereo Headphone Amp With Separate Gain 3 Description

Control The LM4550B device is an audio codec for PC

• TI's 3D Sound Stereo Enhancement Circuitry systems which is fully PC99 compliant and performs

• Advanced Power Management Support the analog intensive functions of the AC '97 Rev 2.1

• External Amplifier Power-Down (EAPD) Control architecture. Using 18-bit Sigma-Delta ADCs and

DACs, the LM4550B provides 90 dB of Dynamic

• PC Beep Passthrough to Line Out During Range.

Initialization or Cold Reset The LM4550B was designed specifically to provide a

• Digital 3.3-V and 5-V Supply Options high quality audio path and provide all analog

• Extended Temperature: −40°C ≤TA≤85°C functionality in a PC audio system. It features full

• Key specifications duplex stereo ADCs and DACs and analog mixers

– Analog Mixer Dynamic Range, 97 dB (Typical) with access to 4 stereo and 4 mono inputs.

– DAC Dynamic Range, 89 dB (Typical) Device Information(1)

– ADC Dynamic Range, 90 dB (Typical) PART NUMBER PACKAGE BODY SIZE (NOM)

– Headphone Amp THD+N at 50 mW, 0.02% LM4550B LQFP (48) 7.00 mm × 7.00 mm

(Typical) into 32Ω(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

Table of Contents

8.3 Feature Description................................................. 15

1 Features.................................................................. 18.4 Device Functional Modes........................................ 20

2 Applications ........................................................... 18.5 Programming........................................................... 21

3 Description............................................................. 18.6 Register Maps......................................................... 28

4 Revision History..................................................... 29 Application and Implementation ........................ 35

5 Description (continued)......................................... 39.1 Application Information............................................ 35

6 Pin Configuration and Functions......................... 49.2 Typical Application ................................................. 36

7 Specifications......................................................... 89.3 System Examples .................................................. 37

7.1 Absolute Maximum Ratings ...................................... 810 Power Supply Recommendations ..................... 38

7.2 ESD Ratings.............................................................. 811 Layout................................................................... 38

7.3 Recommended Operating Comditions...................... 811.1 Layout Guidelines ................................................. 38

7.4 Thermal Information ................................................. 912 Device and Documentation Support................. 39

7.5 Electrical Characteristics........................................... 912.1 Community Resources.......................................... 39

7.6 Timing Requirements.............................................. 10 12.2 Trademarks........................................................... 39

7.7 Typical Characteristics............................................ 13 12.3 Electrostatic Discharge Caution............................ 39

8 Detailed Description............................................ 15 12.4 Glossary................................................................ 39

8.1 Overview................................................................. 15 13 Mechanical, Packaging, and Orderable

8.2 Functional Block Diagram....................................... 15 Information........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (April 2013) to Revision G Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

Product Folder Links: LM4550B

LM4550B

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SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

5 Description (continued)

Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono and 2 stereo

outputs, each with attenuation and mute control. The LM4550B provides a stereo headphone amplifier as one of

its stereo outputs and also supports TI's 3D sound stereo enhancement and a comprehensive sample rate

conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution

of 1 Hz to convert any rate from 4 kHz to 48 kHz. Sample timing from the ADCs and sample request timing for

the DACs are completely deterministic to ease task scheduling and application software development. These

features together with an extended temperature range also make the LM4550B suitable for non-PC codec

applications.

The LM4550B features the ability to connect several codecs together in a system to provide up to 6 simultaneous

channels of streaming data on output frames (controller to codec) for surround sound applications. Such systems

can also support up to 8 simultaneous channels of streaming data on input frames (codec to controller). Multiple

codec systems can be built either using the standard AC Link configuration (that is, of one serial data signal to

the controller per codec) or using a unique TI feature for chaining codecs together. This chain feature shares

only a single data signal to the controller among multiple codecs.

The AC '97 architecture separates the analog and digital functions of the PC audio system allowing both for

system design flexibility and increased performance.

Product Folder Links: LM4550B

DVDD1

XTL_OUT

SDATA_OUT

47 46

XTL_IN

DVSS1

CIN

EAPD

ID1#

ID0#

LM4550B

$&µ97 Rev 2.1

Codec

BIT_CLK

SDATA_IN

SYNC

RESET#

PC_BEEP

DVDD2

DVSS2

LINE_OUT_R

3DP

LINE_OUT_L

3DN

AVSS1

VREF

VREF_OUT

AVDD1

AVSS2

HP_OUT_R

HP_OUT_C

HP_OUT_L

AVDD2

MONO_OUT

PHONE

AUX_L

AUX_R

VIDEO_L

VIDEO_R

CD_L

CD_GND

CD_R

MIC1

MIC2

LINE_IN_L

LINE_IN_R

13 14 15 16 17 18 19 20 21 22 23 24

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

6 Pin Configuration and Functions

PR Package

48-Pin LQFP

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

Mono Input

This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix

signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level

can be muted or adjusted from 0 dB to –45 dB in 3-dB steps. The Stereo Mix signal feeds both the

PC_BEEP 12 I Line Out and Headphone Out analog outputs and is also selectable at the Record Select Mux. During

Initialization or Cold Reset, (reset pin held active low), PC_BEEP is switched directly to both channels

of the Line Out stereo output, bypassing all volume controls. This allows signals such as PC power-on

self-test tones to be heard through the PC's audio system before the codec registers are configured.

Mono Input

This line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for conversion by

either or both channels of the stereo ADC. It can also be mixed equally into both channels of the

PHONE 13 I Stereo Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can

be muted or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. The Stereo Mix signal feeds both the

Line Out and Headphone Out analog stereo outputs and is also selectable at the Record Select Mux.

Left Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux

for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D

AUX_L 14 I signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_L level can be muted

(along with AUX_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined

into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Right Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select

Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo

AUX_R 15 I Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_R level can be

muted (along with AUX_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is

combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone

Out.

Left Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux

for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D

VIDEO_L 16 I signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level can be muted

(along with VIDEO_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined

into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Product Folder Links: LM4550B

LM4550B

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SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

Right Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select

Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo

VIDEO_R 17 I Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_R level can be

muted (along with VIDEO_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is

combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone

Out.

Left Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux for

conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D

CD_L 18 I signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted (along

with CD_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is mixed into the

Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

AC Ground Reference

This input is the reference for the signals on both CD_L and CD_R. CD_GND is NOT a DC ground

and must be AC-coupled to the stereo source ground common to both CD_L and CD_R. The three

CD_GND 19 I inputs CD_GND, CD_L and CD_R act together as a quasi-differential stereo input with CD_GND

providing AC common-mode feedback to reject ground noise. This can improve the input SNR for a

stereo source with a good common ground but precision resistors may be needed in any external

attenuators to achieve the necessary balance between the two channels.

Right Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for

conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D

CD_R 20 I signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted (along

with CD_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the

Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Mono microphone input

Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit

D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20dB

bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and

0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the

MIC1 21 I right or left channels of the Record Select Mux for conversion on either or both channels of the stereo

ADC. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing

adjustments through Mic Volume register, 0Eh) where it is mixed equally into both left and right

channels of Stereo Mix 3D for access to the stereo outputs Line Out and Headphone Out. Access to

the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose

Mono microphone input

Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit

D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20 dB

bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and

0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the

MIC2 22 I right or left channels of the Record Select Mux for conversion on either or both channels of the stereo

ADC. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing

adjustments through Mic Volume register, 0Eh) where it is mixed equally into both left and right

channels of Stereo Mix 3D for access to the stereo outputs Line Out and Headphone Out. Access to

the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose

Left Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux

for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D

LINE_IN_L 23 I signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_L level can be

muted (along with LINE_IN_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is

combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone

Out.

Right Stereo Channel Input

This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for

conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D

LINE_IN_R 24 I signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_R level can be

muted (along with LINE_IN_L) or adjusted from 12 dB to –34.5 dB in 1.5 dB steps. Stereo Mix 3D is

combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone

Out.

Product Folder Links: LM4550B

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SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

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Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

Left Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2

LINE_OUT_L 35 O through the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along with

LINE_OUT_R) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps.

Right Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2

LINE_OUT_R 36 O through the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along with

LINE_OUT_L) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps.

Mono Output

This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2,

after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1.

MONO_OUT 37 O The optional TI 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in the

General Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register. MIX=0

selects a microphone input. Output level can be muted or adjusted from 0 dB to –46.5 dB in 1.5-dB

steps through the Mono Volume register, 06h.

Left Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2

HP_OUT_L 39 O through the Headphone Volume register, 04h. The HP_OUT_L amplitude can be muted (along with

HP_OUT_R) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps

AC Ground Reference

In normal use, this input is the AC ground reference for HP_OUT_L and HP_OUT_R. It must be

capacitively coupled to analog ground with short traces to maximize performance. It is not a DC

HP_OUT_C 40 I ground.

For non-stereo applications it may also be used to provide common-mode feedback with HP_OUT

configured as one differential output rather than as outputs for two single-ended stereo channels.

Right Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2

HP_OUT_R 41 O through the Headphone Volume register, 04h. The HP_OUT_R amplitude can be muted (along with

HP_OUT_L) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps

DIGITAL I/O AND CLOCKING

24.576 MHz crystal or external oscillator input

To complete the oscillator circuit use a fundamental mode crystal operating in parallel resonance and

connect a 1MΩresistor across pins 2 and 3. Choose the load capacitors (Figure 25,C1, C2) to suit

the load capacitance required by the crystal (that is, C1 = C2 = 33 pF for a 20 pF crystal. Assumes

XTL_IN 2 I that each Input + trace capacitance is 7 pF).

This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at standard

logic levels (VIH, VIL).

This pin is only used when the codec is in Primary mode. It may be left open (NC) for any Secondary

mode.

24.576 MHz crystal output

Used with XTAL_IN to configure a crystal oscillator.

XTL_OUT 3 O When the codec is used with an external oscillator this pin should be left open (NC).

When the codec is configured in a Secondary mode this pin is not used and may be left open (NC).

Input to codec

This is the input for AC Link Output Frames from an AC '97 Digital Audio Controller to the LM4550B

SDATA_OUT 5 I codec. These frames can contain both control data and DAC PCM audio data. This input is sampled

by the LM4550B on the falling edge of BIT_CLK.

AC Link clock

An OUTPUT when in Primary Codec mode. This pin provides a 12.288-MHz clock for the AC Link.

The clock is derived (internally divided by two) from the 24.576-MHz signal at the crystal input

BIT_CLK 6 I/O (XTL_IN).

This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and would

normally use the AC Link clock generated by a Primary Codec.

Output from codec

This is the output for AC Link Input Frames from the LM4550B codec to an AC '97 Digital Audio

SDATA_IN 8 O Controller. These frames can contain both codec status data and PCM audio data from the ADCs. The

LM4550B clocks data from this output on the rising edge of BIT_CLK.

Product Folder Links: LM4550B

LM4550B

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SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

AC Link frame marker and Warm Reset

This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In

normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is

sampled on the falling edge of BIT_CLK and the codec takes the first positive sample of SYNC as

SYNC 10 I defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK

periods of the frame start it will be ignored.

SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is

used to clear a power-down state on the codec AC Link interface.

Cold Reset

This active low signal causes a hardware reset which returns the control registers and all internal

circuits to their default conditions. RESET# MUST be used to initialize the LM4550B after Power On

RESET# 11 I when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test

modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the

LINE_OUT stereo output.

Codec Identity

ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the

codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted

polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID

ID0# 45 I register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will be set

to 1. Similarly, connection to DVDD will set the ID0 bit to 0. If left open (NC), ID0# is pulled high by an

internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See

the register description and the CIN pin description for details.

Codec Identity

ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configures the

codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted

polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID

ID1# 46 I register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit (D15, reg 28h) will be set

to 1. Similarly, connection to DVDD will set the ID1 bit to 0. If left open (NC), ID1# is pulled high by an

internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See

the register description and the CIN pin description for details.

External Amplifier Power-Down control signal

This output is set by the EAPD bit (bit D15) in the Power-down Control/Status register, 26h. As with

EAPD 47 O the other logic outputs, the output voltage is set by DVDD. This pin is intended to be connected to the

shutdown pin on an external power amplifier. For normal operation the default value of EAPD = 0 will

enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset.

Chain In

The codec can be instructed to disconnect its own SDATA_IN signal and instead pass the signal on

CIN through to the SDATA_IN output pin. This is achieved by changing the value of the two LSBs of

the Chain-In Control register (74h) so that they differ from the Codec Identity bits ID1, ID0. Those two

LSBs default to the value of the Codec Identity bits following Cold Reset thereby disabling the Chain In

CIN 48 I feature. Chain In can also be disabled by reading the Codec Identity from the Extended Audio ID

determined by the input pins ID1#, ID0#.

CIN can be left open (NC) provided that the chain feature is disabled. When the chain feature is used,

CIN should always be driven. Either connect the SDATA_IN pin from another codec or else ground

CIN to prevent the possibility of floating the SDATA_IN signal at the controller.

POWER SUPPLIES AND REFERENCES

AVDD1 25 I Analog supply

AVSS1 26 I Analog ground

AVDD2 38 I Analog supply 2

AVSS2 42 I Analog ground 2

DVDD1 1 I Digital supply

DVDD2 9 I Digital supply

DVSS1 4 I Digital ground

DVSS2 7 I Digital ground

Nominal 2.2-V internal reference

VREF 27 O Not intended to sink or source current. Use short traces to bypass (3.3 µF, 0.1 µF) this pin to

maximize codec performance. See text.

Nominal 2.2-V reference output

VREF_OUT 28 O Can source up to 5 mA of current and can be used to bias a microphone.

Product Folder Links: LM4550B

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Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

3D SOUND AND NO-CONNECTS (NC)

3DP 33 These pins are used to complete the TI 3D Sound stereo enhancement circuit. Connect a 0.022-µF

capacitor between pins 3DP and 3DN. TI 3D Sound can be turned on and off though the 3D bit (bit

O D13) in the General Purpose register, 20h. TI 3D Sound uses a fixed-depth type stereo enhancement

3DN 34 circuit hence the 3D Control register, 22h is read-only and is not programmable. If TI 3D Sound is not

needed, these pins should be left open (NC).

30 These pins are not used and should be left open (NC).

NC NC For second source applications these pins may be connected to a noise-free supply or ground (that is,

32 AVDD or AVSS), either directly or through a capacitor.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply Voltage 6 V

Storage Temperature –65 150 °C

Input Voltage –0.3 VDD 0.3 V

Junction Temperature 150 °C

Vapor Phase (60 sec.) 215

Soldering Information LQFP Package °C

Infrared (15 sec.) 220

Storage temperature, Tstg °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings VALUE UNIT

All pins except 3 ±2000

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001(1)(2) Pin 3 ±750

V(ESD) Electrostatic discharge V

All pins except 3 ±200

Machine Model(3) Pins 3 ±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Human body model, 100 pF discharged through a 1.5-kΩresistor.

(3) Machine Model, 220 pF to 240 pF discharged through all pins.

7.3 Recommended Operating Comditions MIN NOM MAX UNIT

Temperature Range (−40°C ≤TA≤85°C) TMIN TATMAX(1) °C

Analog Supply Range 4.2 AVDD 5.5 V

Digital Supply Range 3 DVDD 5.5 V

(1) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient temperature

TA. The maximum allowable power dissipation is PDMAX = (TJMAX– TA)/RθJA or the number given in Absolute Maximum Ratings,

whichever is lower. For the LM4550B, TJMAX = 150°C. The typical junction-to-ambient thermal resistance is 74°C/W for package number

PT.

Product Folder Links: LM4550B

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SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

7.4 Thermal Information LM4550B

THERMAL METRIC(1) PT (LQFP) UNIT

48 PINS

RθJA Junction-to-ambient thermal resistance 74 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for AVDD = 5V, DVDD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode)

unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.(1)(2)

PARAMETER TEST CONDITIONS MIN TYP(3) MAX(4) UNIT

AVDD Analog Supply Range 4.2 5.5 V

DVDD Digital Supply Range 3 5.5 V

DVDD = 5 V 34 mA

Digital Quiescent Power

DIDD Supply Current DVDD = 3.3 V 19 mA

Analog Quiescent Power

AIDD AVDD = 5 V 53 mA

Supply Current

IDSD Digital Shutdown Current PR6543210 = 1111111 19 µA

IASD Analog Shutdown Current PR6543210 = 1111111 70 µA

VREF Reference Voltage No pullup resistor 2.16 V

PSRR Power Supply Rejection Ratio 40 dB

ANALOG LOOPTHROUGH MODE(5)

CD Input to Line Output, –60 dB Input

Dynamic Range (6) 90 97 dB

THD+N

THD Total Harmonic Distortion VO= –3 dB, f = 1 kHz, RL= 10 kΩ0.013% 0.02%

ANALOG INPUT SECTION

LINE_IN, AUX, CD, VIDEO, PC_BEEP,

VIN Line Input Voltage 1 Vrms

PHONE

VIN Mic Input with 20-dB Gain 0.1 Vrms

VIN Mic Input with 0-dB Gain 1 Vrms

Xtalk Crosstalk CD Left to Right −95 dB

ZIN Input Impedance (6) All Analog Inputs 10 40 kΩ

CIN Input Capacitance(6) 3.7 7 pF

Interchannel Gain Mismatch CD Left to Right 0.10 dB

RECORD GAIN AMPLIFIER - ADC

ASStep Size 0 dB to 22.5 dB 1.5 dB

AMMute Attenuation (6) 86 dB

MIXER SECTION

ASStep Size 12 dB to –34.5 dB 1.5 dB

AMMute Attenuation(6) 86 dB

ANALOG TO DIGITAL CONVERTERS

Resolution 18 Bits

Dynamic Range (6) –60-dB Input THD+N, A-Weighted 86 90 dB

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(2) All voltages are measured with respect to the ground pin, unless otherwise specified.

(3) Typicals are measured at 25°C and represent the parametric norm.

(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

(5) Loopthrough Mode describes a path from an analog input through the analog mixers to an analog output.

(6) These specifications are ensured by design and characterization; they are not production tested.

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Electrical Characteristics (continued)

The following specifications apply for AVDD = 5V, DVDD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode)

unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.(1)(2)

PARAMETER TEST CONDITIONS MIN TYP(3) MAX(4) UNIT

Frequency Response –1-dB Bandwidth 20 kHz

DIGITAL TO ANALOG CONVERTERS

Resolution 18 Bits

Dynamic Range (6) –60-dB Input THD+N, A-Weighted 82 89 dB

THD Total Harmonic Distortion VIN = –3 dB, f = 1 kHz, RL= 10 kΩ0.01%

Frequency Response 20-21k Hz

Group Delay (6) Sample Freq. = 48 kHz 0.36 1 ms

Out of Band Energy (7) -40 dB

Stop Band Rejection 70 dB

DTDiscrete Tones -96 dB

ANALOG OUTPUT SECTION

ASStep Size 0 dB to –46.5 dB 1.5 dB

AMMute Attenuation(6) 86 dB

Headphone Amplifier Total Loopthrough Mode(5), RL= 32 Ω, f = 1 kHz,

THD+N 0.02%

Harmonic Distortion plus Noise Pout = 50 mW

ZOUT Output Impedance(6) HP_OUT_L, HP_OUT_R 0.65 2.75 Ω

ZOUT Output Impedance(6) LINE_OUT_L, LINE_OUT_R, MONO_OUT 220 500 Ω

DIGITAL I/O(6)

VIH High level input voltage 0.65 x DVDD V

0.35 x

VIL Low level input voltage V

DVDD

VOH High level output voltage IO= –2.5 mA. 0.90 x DVDD V

0.10 x

VOL Low level output voltage IO= 2.5 mA. V

DVDD

ILInput Leakage Current AC Link inputs ±10 µA

ILTri state Leakage Current High impedance AC Link outputs ±10 µA

Cin AC-Link I/O capacitance SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF

IDR Output drive current AC Link outputs 5 mA

(7) Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1 Vrms DAC output.

7.6 Timing Requirements MIN NOM MAX UNIT

DIGITAL TIMING SPECIFICATIONS(1)

12.2

FBC BIT_CLK frequency MHz

TBCP BIT_CLK period 81.4 ns

TCH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20%

FSYNC SYNC frequency 48 kHz

TSP SYNC period 20.8 µs

TSH SYNC high pulse width 1.3 µs

TSL SYNC low pulse width 19.5 µs

TDSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 10 3.5 ns

Hold time of SDATA_OUT from falling edge of

TDHOLD Hold Time for codec data input 10 5.3 ns

BIT_CLK(1)

TSSETUP Setup Time for codec SYNC input SYNC to falling edge of BIT_CLK(1) 10 3.8 ns

TSHOLD Hold Time for codec SYNC input Hold time of SYNC from falling edge of BIT_CLK 10 ns

(1) These specifications are ensured by design and characterization; they are not production tested.

Product Folder Links: LM4550B

SYNC

BIT_CLK

SDATA_IN

SDATA_OUT

TRISE TFALL

10%

90% 90%

10%

BIT_CLK

SDATA_IN

TCO

TDHOLD

TDSETUP

SYNC

THOLD

SDATA_OUT

SYNC

TSH

TSL

TSP

TBCH

TBCL

TBCP

BIT_CLK

LM4550B

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Timing Requirements (continued)

MIN NOM MAX UNIT

Output Delay of SDATA_IN from rising edge of

TCO Output Valid Delay 5.2 15 ns

BIT_CLK(1)

TRISE Rise Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns

TFALL Fall Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns

TRST_LOW RESET# active low pulse width For Cold Reset 1 µs

TRST2CLK RESET# inactive to BIT_CLK start-up For Cold Reset 162.8 271 ns

TSH SYNC active high pulse width For Warm Reset 1 µs

TSYNC2CLK SYNC inactive to BIT_CLK start-up For Warm Reset 162.8 ns

Delay from end of Slot 2 to BIT_CLK, SDATA_IN

TS2_PDOWN AC Link Power-Down Delay 1 µs

low

TSUPPLY2R Time from minimum valid supply levels to end of

Power On Reset 1 µs

ST Reset

TSU2RST Setup to trailing edge of RESET# For ATE Test Mode 15 ns

TRST2HZ Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns

Figure 1. Clocks

Figure 2. Data Delay, Setup and Hold

Figure 3. Digital Rise and Fall

Product Folder Links: LM4550B

SYNC

TSH TSYNC2CLK

BIT_CLK

RESET#

TRST_LOW TRST2CLK

BIT_CLK

RESET#

TRST_LOW TRST2CLK

BIT_CLK

DVDD, AVDD

TSUPPLY2RST

DVDD (min), AVDD (min)

Input: VIH Output: VOH

Input: VIL Output: VOL

LM4550B

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Figure 4. Legend

Figure 5. Power On Reset

Figure 6. Cold Reset

Figure 7. Warm Reset

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7.7 Typical Characteristics

Figure 8. ADC Noise Floor Figure 9. DAC Noise Floor

Figure 10. ADC Frequency Figure 11. DAC Frequency

Response Response

Figure 12. Line Out Noise Floor Figure 13. Headphone Amplifier Noise Floor

(Analog Loopthrough) (Analog Loopthrough)

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Typical Characteristics (continued)

Figure 14. Headphone Amplifier Figure 15. Headphone Amplifier

THD+N vs Frequency THD+N vs Output Power

Product Folder Links: LM4550B

DAC SAMPLE RATE

CONVERTER: 2Ch ADC SAMPLE RATE

CONVERTER: 32h

MIC1

AUX

MIC2 R

VIDEO

LINE_IN

PHONE

PC_BEEP

LINE_OUT

HP_OUT

MONO_OUT

EAPD

RESET#

SDATA_OUT

SYNC

BIT_CLK

SDATA_IN

CIN

XTAL_OUT

XTAL_IN

ID0#

ID1#

MIX2

MIX1

STEREO SIGNAL PATH

MONO SIGNAL PATH Gain Attenuation Mute

(Mute is default)

NN Address of Analog Input

Volume Control Register

NN (HEX)

G A M

*Asterisk denotes default

setting after Cold Reset

DIGITAL SIGNAL PATH

Control bit m in Register with

hexadecimal address NN

Dm, NNh

Control Register with

hexadecimal address NN

NNh

6'DAC

6'ADC

18h

GAIN: D6,0Eh

*0 dB/20 dB

$&¶97

REGISTERS

CODEC

IDENTITY

SELECT

AC LINK INTERFACE

D13, 20h

NATIONAL

3D SOUND

GAIN

ATTEN

MUTE

1Ch

GAIN

MUTE

Atten Mute

MONO

VOLUME: 06h

Atten Mute

HEADPHONE

VOLUME: 04h

Atten Mute

MASTER

VOLUME: 02h

POWER SUPPLY

and

REFERENCES

MONO

MIX

STEREO MIX

STEREO

MIX 3D

POP

LM4550B

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8 Detailed Description

8.1 Overview

The LM4550B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format)

inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog

outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital

interface simultaneously.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 ADC inputs and Outputs

All four of the stereo analog inputs and three of the mono analog inputs can be selected for conversion by the

18-bit stereo ADC. Digital output from the left and right channel ADCs is always located in AC Link Input Frame

slots 3 and 4 respectively. Input level to either ADC channel can be muted or adjusted from the Record Gain

together (D15). Input selection for the ADC is through the Record Select Mux controlled from the Record Select

20h. One of the stereo inputs, CD_IN, uses a quasi-differential 3-pin interface where both stereo channel inputs

are referenced to the third pin, CD_GND. CD_GND should be AC coupled to the source ground and provides

common-mode feedback to cancel ground noise. It is not a DC ground. The other three stereo inputs, LINE_IN,

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Feature Description (continued)

AUX and VIDEO are 2-pin interfaces, single-ended for each stereo channel, with analog ground (AVSS) as the

signal reference. Either of the two mono microphone inputs can be muxed to a programmable boost amplifier

before selection for either channel of the ADC. The Microphone Mux is controlled by the Microphone Selection

(MS) bit (D8) in the General Purpose register (20h) and the 20 dB programmable boost is enabled by the 20dB

bit (D6) in register 0Eh. The mono PHONE input may also be selected for either ADC channel.

8.3.2 Analog Mixing: MIX1

Five analog inputs are available for mixing at the stereo mixer, MIX1 – all four stereo and one mono, namely the

microphone input selected by MS (D8, reg 20h). Digital input to the codec can be directed to either MIX1 or to

MIX2 after conversion by the 18-bit stereo DAC and level adjustment by the PCM Out Volume control register

(18h). Each input to MIX1 may be muted or level adjusted using the appropriate Mixer Input Volume Register:

Mic Volume (0Eh), Line_In Volume (10h), CD Volume (12h), Video Volume (14h), Aux Volume (16h) and PCM

Out Volume (18h). The mono microphone input is mixed equally into left and right stereo channels but stereo

mixing is orthogonal, that is, left channels are only mixed with other left channels and right with right. The left and

right amplitudes of any stereo input may be adjusted independently however mute for a stereo input acts on both

left and right channels.

8.3.3 DAC Mixing and 3D Processing

Control of routing the DAC output to MIX1 or MIX2 is by the POP bit (D15) in the General Purpose register, 20h.

If MIX1 is selected (default, POP = 0) then the DAC output is available for processing by the TI 3D Sound

circuitry. If MIX2 is selected, the DAC output will bypass the 3D processing. This allows analog inputs to be

enhanced by the analog 3D Sound circuitry before mixing with digital audio. The digital audio may then use

alternative digital 3D enhancements. TI 3D Sound circuitry is enabled by the 3D bit (D13) in the General Purpose

(read-only). The 3D Sound circuitry defaults to disabled after reset.

8.3.4 Analog Mixing: MIX2

MIX2 combines the output of MIX1 (Stereo Mix 3D) with the two mono analog inputs, PHONE and PC_BEEP;

each are level-adjusted by the input control registers Phone Volume (0Ch) and PC_Beep Volume (0Ah)

respectively. If selected by the POP bit (D15, reg 20h), the DAC output is also summed into MIX2.

8.3.5 Stereo Mix

The output of MIX2 is the signal, Stereo Mix. Stereo Mix is used to drive both the Headphone output (HP_OUT)

and the Line output (LINE_OUT) and can also be selected as the input to the ADC at the Record Select Mux. In

addition, the two channels of Stereo Mix are summed to form a mono signal (Mono Mix) also selectable at the

Record Select Mux as an input to either channel of the ADC.

8.3.6 Stereo Outputs

The output volume from LINE_OUT and HP_OUT can be muted or adjusted by 0 dB to 45 dB in nominal 3-dB

steps under the control of the output volume registers Master Volume (02h) and Headphone Volume (04h)

respectively. As with the input volume registers, adjustments to the levels of the two stereo channels can be

made independently but both left and right channels share a mute bit (D15).

8.3.7 Mono Output

The mono output (MONO_OUT) is driven by one of two signals selected by the MIX bit (D9) in the General

Purpose register, 20h. The signal selected by default (MIX = 0) is the mono summation of the two channels of

Stereo Mix 3D, the stereo output of the mixer MIX1. Setting the control bit MIX = 1, selects a microphone input,

MIC1 or MIC2. The choice of microphone is controlled by the Microphone Select (MS) bit (D8) also in the

General Purpose register, 20h.

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Feature Description (continued)

8.3.8 Analog Loopthrough And Digital Loopback

Analog Loopthrough refers to an all-analog signal path from an analog input through the mixers to an analog

output. Digital Loopback refers to a mixed-mode analog and digital signal path from an analog input through the

ADC, looped-back (LPBK bit – D7, 20h) through the DAC and mixers to an analog output. This is an 18 bit digital

loopback, bypassing the SRC logic, even if a rate other than 48 kHz is selected.

8.3.9 Resets

COLD RESET is performed when RESET# (pin 11) is pulled low for > 1 µs. It is a complete reset. All registers

and internal circuits are reset to their default state. It is the only reset which clears the ATE and Vendor Test

Modes.

WARM RESET is performed when SYNC (pin 10) is held high for > 1 µs and the codec AC Link digital interface

is in power down (PR4 = 1, Power-down Control / Status register, 26h). It is used to clear PR4 and power up the

AC Link digital interface but otherwise does not change the contents of any registers nor reset any internal

circuitry.

their default state and will modify circuit configurations accordingly but does not reset any other internal circuits.

8.3.10 Multiple Codecs

8.3.10.1 Extended AC Link

Up to four codecs can be supported on the extended AC Link. These multiple codec implementations should run

off a common BIT_CLK generated by the Primary Codec. All codecs share the AC '97 Digital Controller output

signals, SYNC, SDATA_OUT, and RESET#. Each codec, however, supplies its own SDATA_IN signal back to

the controller, with the result that the controller requires one dedicated input pin per codec (Figure 16).

By definition there can be one Primary Codec and up to three Secondary Codecs on an extended AC Link. The

Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Secondary Codecs take identities equal to 01,

10 or 11 (see Table 1). The Codec Identity is also used as a chip select function. This allows the Command and

Status registers in any of the codecs to be individually addressed although the access mechanism for Secondary

Codecs differs slightly from that for a Primary.

The Identity control pins, ID1#, ID0# (pins 46 and 45) are internally pulled up to DVDD. The Codec may therefore

be configured as Primary either by leaving ID1#, ID0# open (NC) or by strapping them externally to DVDD (digital

supply).

The difference between Primary and Secondary codec modes is in their timing source; in the AMAP Slot-to-DAC

mapping used in Output Frames carried by SDATA_OUT; and in the Tag Bit handling in Output Frames for

Command/Status register access. For a timing source, a Primary codec divides down by 2 the frequency of the

signal on XTAL_IN and also generates this as the BIT_CLK output for the use of the controller and any

Secondary codecs. Secondary codecs use BIT_CLK as an input and as their timing source and do not use

XTAL_IN or XTAL_OUT, The AMAP mappings are given in Table 1 and the use of Tag Bits is described below.

8.3.10.2 Secondary Codec Register Access

For Secondary Codec access, the controller must set the tag bits for Command Address and Data in the Output

Frame as invalid (that is, equal to 0). The Command Address and Data tag bits are in slot 0, bits 14 and 13 and

Output Frames are those in the SDATA_OUT signal from controller to codec. The controller must also place the

non-zero value (01, 10, or 11) corresponding to the Identity (ID1, ID0) of the target Secondary Codec into the

Codec ID field (slot 0, bits 1 and 0) in that same Output Frame. The value set in the Codec ID field determines

which of the three possible Secondary Codecs is accessed. Unlike a Primary Codec, a Secondary Codec will

disregard the Command Address and Data tag bits when there is a match between the 2-bit Codec ID value (slot

0, bits 1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the Codec-ID/Identity match to indicate that the

Command Address in slot 1 and (if a write) the Command Data in slot 2 are valid.

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Feature Description (continued)

When reading from a Secondary Codec, the controller must send the correct Codec ID bits (that is, the target

Codec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address

(slot 1, bits 18 – 12). To write to a Secondary Codec, a controller must send the correct Codec ID bits when slot

1 contains a valid target register address and write indicator bit and slot 2 contains valid target register data. A

write operation is only valid if the register address and data are both valid and sent within the same frame. When

accessing the Primary Codec, the Codec ID bits are cleared and the tag bits 14 and 13 resume their role

indicating the validity of Command Address and Data in slots 1 and 2.

The use of the tag bits in Input Frames (carried by the SDATA_IN signal) is the same for Primary and Secondary

Codecs.

The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as the

value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h of the target codec.

In addition to the Codec Identity bits (ID1, ID0), the read-only Extended Audio ID register (28h) contains the

AMAP bit (D9). The AMAP bit indicates support for the (optional) AC '97 Rev. 2.1 compliant mappings from slots

in AC Link Output Frames to the audio DACs for each of the four Codec Identity modes. AMAP = 1 indicates that

the default mapping (as realized after reset) of Slots-to-DACs conforms to Table 1. Slots in AC Link Input Frames

are always mapped such that PCM data from the left ADC channel is carried by slot 3 and PCM data from the

right ADC channel by slot 4. Output Frames are those carried by the SDATA_OUT signal from the controller to

the codec while Input Frames are those carried by the SDATA_IN signal from the codec to the controller.

8.3.10.2.1 SLOT 0: TAG bits in Output Frames (Controller to Codec)

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Valid Slot 1 Slot 2 Slot 3 Slot 4 Slot 6 Slot 7 Slot 8 Slot 9

X X X X X ID1 ID0

Frame Valid Valid Valid Valid Valid Valid Valid Valid

8.3.10.2.2 Extended Audio ID Register (28h): Support for Multiple Codecs

RE D1 D1 D1 DEFA

NAME D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

G 5 4 3 ULT

Extended AMA

28h ID1 ID0 X X X X X X X X X X X X VRA X201h

Audio ID P

Table 1. AMAP Slot-to-DAC Audio Mapping

LEFT DAC DATA RIGHT DAC DATA

CODEC IDENTITY ID1 ID0 FROM SLOT 5.1 AUDIO FROM SLOT 5.1 AUDIO

MODE (D15, 28h) (D14, 28h) # CHANNEL(1) # CHANNEL(1)

Primary 0 0 3 Left 4 Right

Secondary 1 0 1 3 Left 4 Right

Secondary 2 1 0 7 Left Surround 8 Right Surround

Secondary 3 1 1 6 Center 9 LFE

(1) AC '97 Rev 2.1 specifies this allocation of 5.1 Audio channels to these slots in the AC Link Output Frame

Product Folder Links: LM4550B

AC ‘97 SECONDARY 2

L R SURROUND: ID = 10/

AC ‘97 SECONDARY 1

DOCKING: ID = 01

AC ‘97 SECONDARY 3

CENTER LFE: ID = 11/

AC ‘97 PRIMARY

MASTER: ID = 00

SDATA_IN1

SDATA_IN2

SYNC

SDATA_IN0

RESET#

SDATA_OUT

BIT_CLK

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 7 & 8

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 6 & 9

Line_Out_L

Line_Out_R

AC ‘97

DIGITAL CONTROLLER

SDATA_IN3

Line_Out_L

Line_Out_R

XTAL_IN

XTAL_OUT

LM4550B

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Figure 16. Multiple Codecs using Extended AC Link

8.3.10.2.3 CODEC Chaining

Using TI's unique feature for chaining together codecs, a multiple codec system can be built using fewer

interface pins. This Chain feature allows two, three or four codecs to share a single signal input pin at the

controller. By setting the two LSBs of the Chain-In Control register (74h) to a value other than the Codec Identity,

a controller can instruct a codec to disconnect its own SDATA_IN signal and discard its own Input Frame and

instead switch the signal connected to the CIN pin through to the SDATA_IN output pin allowing passage of an

SDATA_IN signal carrying the Input Frame from a codec further down the chain. The Chain-In Control register

(74h) is updated at the rising edge of SYNC therefore an instruction to enable or disable the Chain feature takes

effect in the next frame.

When the Chain feature is used the CIN pin should always be driven. Connect CIN to either the SDATA_IN pin

from another codec or else ground CIN to prevent the possibility of floating the SDATA_IN signal at the

controller.

Product Folder Links: LM4550B

AC ‘97 SECONDARY 2

L R SURROUND: ID = 10/

AC ‘97 SECONDARY 1

DOCKING: ID = 01

AC ‘97 SECONDARY 3

CENTER LFE: ID = 11/

AC ‘97 PRIMARY

MASTER: ID = 00

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 3 & 4

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 7 & 8

Line_Out_L

Line_Out_R

DVDD/NC

ID1#

ID0#

SYNC

SDATA_IN

RESET#

SDATA_OUT

BIT_CLK

Slots 6 & 9

Line_Out_R

AC ‘97

DIGITAL CONTROLLER

CIN

Line_Out_L

XTAL_IN

XTAL_OUT

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Figure 17. Multiple Codecs in a Chain

8.4 Device Functional Modes

8.4.1 Test Modes

AC '97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit

either of them. The ATE test mode is activated if SDATA_OUT is sampled high by the trailing edge (zero-to-one

transition) of RESET#. In ATE test mode, the codec AC Link outputs SDATA_IN and BIT_CLK are configured to

a high impedance state to allow tester control of the AC Link interface for controller testing. ATE test mode timing

parameters are given in the Electrical Characteristics table. The Vendor test mode is entered if SYNC is sampled

high by the zero-to-one transition of RESET#. Neither of these entry conditions can occur in normal AC Link

operation but care must be taken to avoid mistaken activation of the test modes when using non standard

controllers.

Product Folder Links: LM4550B

BIT_CLK

SDATA_OUT

SYNC

End of previous

Audio Frame

Valid

Frame

Slot

(1)

Slot

(9) Bit 19 Bit 0 Bit 19

Slot 2

Bit 0

Slot 12

SLOTS 2 to 12SLOT 1

ID0

Tag bits: &uv^o}^so]_], Codec ID

ID1

Tag Phase 20.8 Ps

(48 kHz)

Data Phase

Read / Write Request,

Command Address

Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM data

Codec ID = (ID1, ID0) - codec address for multiple codecs Data: Command and

Audio

SLOT #

SYNC

AC LINK

OUTPUT

FRAMES:

SDATA_OUT

0 1 2 3 4 65 7 1098 11 12

PCM

LFE

TAG CMD

ADR

CMD

DATA

PCM

LEFT

PCM

RIGHT

PCM

CNTR

RSRV PCM

L-SUR RSRV

PCM

R-SUR RSRV RSRV

AC LINK INPUT

FRAMES:

SDATA_IN

RSRVTAG STAT

ADR

STAT

DATA

PCM

LEFT

PCM

RIGHT RSRVRSRV RSRV RSRVRSRV RSRV RSRV

Codec ID: to select target codec in multiple codec configurations

Slot Request bits, 11-10, 8-5: to request data from Output Frame slots 3-4, 6-9

TAG

PHASE DATA PHASE

LM4550B

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8.5 Programming

8.5.1 AC Link Serial Interface Protocol

Figure 18. AC Link Bidirectional Audio Frame

Figure 19. AC Link Output Frame

8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4550B Input

The AC Link Output Frame carries control and PCM data to the LM4550B control registers and stereo DAC.

Output Frames are carried on the SDATA_OUT signal which is an output from the AC '97 Digital Controller and

an input to the LM4550B codec. As shown in Figure 18, Output Frames are constructed from thirteen time slots:

one Tag Slot followed by twelve Data Slots. Each Frame consists of 256 bits with each of the twelve Data Slots

containing 20 bits. Input and Output Frames are aligned to the same SYNC transition. The LM4550B only

accepts data in eight of the twelve Data Slots and, because it is a two channel codec only in 4 simultaneously –

2 for control, one each for PCM data to the left and right channel DACs. Data-Slot to DAC mappings are tied to

the codec mode selected by the Identity pins ID1#, ID0# and are given in Table 1.

A new Output Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the

controller on a rising edge of BIT_CLK and, as shown in Figure 19 and Figure 20, the first tag bit in the Frame

(“Valid Frame”) should be clocked from the controller by the next rising edge of BIT_CLK and sampled by the

LM4550B on the following falling edge. The AC '97 Controller should always clock data to SDATA_OUT on a

rising edge of BIT_CLK and the LM4550B always samples SDATA_OUT on the next falling edge. SYNC is

sampled with the falling edge of BIT_CLK.

The LM4550B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high

transition on SYNC) before 256 bits are received from the old Frame then the new Frame is ignored, that is, the

data on SDATA_OUT is discarded until a valid new Frame is detected.

The LM4550B expects to receive data MSB first, in an MSB justified format.

Product Folder Links: LM4550B

BIT_CLK

SDATA_OUT

SYNC

LM4550 samples

SYNC assertion

LM4550 samples

first bit of SDATA_OUT

End of previous

Audio Frame

Valid

Frame

Slot

(1)

Slot

(2)

LM4550B

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Programming (continued)

8.5.1.1.1 SDATA_OUT: Slot 0 – Tag Phase

The first bit of Slot 0 is designated the Valid Frame bit. If this bit is 1, it indicates that the current Output Frame

contains at least one slot of valid data and the LM4550B will check further tag bits for valid data in the expected

Data Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated

tag bit equal to 1. Because it is a two channel codec the LM4550B can only receive data from four slots in a

given frame and so only checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1

(Command Address), slot 2 (Command Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data for right

DAC).

The last two bits in the Tag contain the Codec ID used to select the target codec to receive the frame in multiple

codec systems. When the frame is being sent to a codec in one of the Secondary modes the controller does not

use bits 14 and 13 to indicate valid Command Address and Data in slots 1 and 2. Instead, this role is performed

by the Codec ID bits – operation of the Extended AC Link assumes that the controller would not access a

secondary codec unless it was providing valid Command Address and/or Data. When in one of the secondary

modes the LM4550B only checks the tag bits for the Codec ID and for valid data in the two audio data slots: slots

3 & 4 for Secondary mode 1, slots 7 & 8 for mode 2 and slots 6 & 9 for mode 3.

When sending an Output Frame to a Secondary mode codec, a controller should set tag bits 14 and 13 to zero.

Figure 20. Start of AC Link Output Frame

Table 2. Slot 0, Output Frame

BIT DESCRIPTION COMMENT

15 Valid Frame 1 = Valid data in at least one slot.

14 Control register address 1 = Valid Control Address in Slot 1 (Primary codec only)

13 Control register data 1 = Valid Control Data in Slot 2 (Primary codec only)

1 = Valid PCM Data in Slot 3

12 Left DAC data in Slot 3 (Primary & Secondary 1 modes; Left Channel audio)

1 = Valid PCM Data in Slot 4

11 Right DAC data in Slot 4 (Primary & Secondary 1 modes; Right Channel audio)

10 Not Used Controller should stuff this slot with “0”s

1 = Valid PCM Data in Slot 6

9 Left DAC data in Slot 6 (Secondary 3 mode; Center Channel audio)

1 = Valid PCM Data in Slot 7

8 Left DAC data in Slot 7 (Secondary 2 mode; Left Surround Channel audio)

1 = Valid PCM Data in Slot 8

7 Right DAC data in Slot 8 (Secondary 2 mode; Right Surround Channel audio)

1 = Valid PCM Data in Slot 9

6 Right DAC data in Slot 9 (Secondary 3 mode; LFE Channel audio)

5:2 Not Used Controller should stuff these slots with “0”s

Codec ID The Codec ID (Table 1) selects the target codec in a multi-codec system to

1,0 (ID1, ID0) receive the control address and data carried in the Output Frame

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8.5.1.1.2 SDATA_OUT: Slot 1 – Read/Write, Control Address

Slot 1 is used by a controller to indicate both the address of a target register in the LM4550B and whether the

access operation is a register read or register write. The MSB of slot 1 (bit 19) is set to 1 to indicate that the

current access operation is read. Bits 18 through 12 are used to specify the 7-bit register address of the read or

write operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC '97

controller.

Table 3. Slot 1, Output Frame

BIT DESCRIPTION COMMENT

1 = Read

19 Read/Write 0 = Write

18:12 Register Address Identifies the Status/Command register for read/write

11:0 Reserved Controller should set to 0

8.5.1.1.3 SDATA_OUT: Slot 2 – Control Data

Slot 2 is used to transmit 16-bit control data to the LM4550B when the access operation is write. The least

significant four bits should be stuffed with zeros by the AC '97 controller. If the access operation is a register

read, the entire slot, bits 19 through 0 should be stuffed with zeros.

Table 4. Slot 2, Output Frame

BIT DESCRIPTION COMMENT

19:4 Control Register Write Data Controller should stuff with zeros if operation is read

3:0 Reserved Set to 0

8.5.1.1.4 SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels

Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when

the codec is in Primary mode or Secondary mode 1. Any unused bits should be stuffed with zeros. The LM4550B

DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC

'97 Rev 2.1 specification allocates the Left channel of 5.1 Audio to slot 3 and the Right channel to slot 4.

Table 5. SLOTS 3 & 4, OUTPUT FRAME

BIT DESCRIPTION COMMENT

Slots used to stream data to DAC when codec is in Primary or Secondary 1

PCM Audio Data

19:0 modes.

(Left /Right Channels) Set unused bits to 0

8.5.1.1.5 SDATA_OUT: Slots 7 & 8 – PCM Playback Left/Right Surround

Slots 7 and 8 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when

the codec is in Secondary mode 2. Any unused bits should be stuffed with zeros. The LM4550B DACs have 18-

bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC '97 Rev 2.1

specification allocates the Left Surround channel of 5.1 Audio to slot 7 and the Right Surround channel to slot 8.

Table 6. Slots 7 and 8, Output Frame

BIT DESCRIPTION COMMENT

PCM Audio Data Slots used to stream data to DAC when codec is in Secondary 2 mode.

19:0 (Left/Right Surround) Set unused bits to 0

8.5.1.1.6 SDATA_OUT: Slots 6 & 9 – PCM Playback (Center/LFE)

Slots 6 and 9 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when

the codec is in Secondary mode 3. Any unused bits should be stuffed with zeros. The LM4550B DACs have 18-

bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC '97 Rev 2.1

specification allocates the Center channel of 5.1 Audio to slot 6 and the LFE (Low Frequency Enhancement)

channel to slot 9.

Product Folder Links: LM4550B

BIT_CLK

SDATA_IN

SYNC

End of previous

Audio Frame

Codec

Ready

Slot

(1)

Slot

(4) ^0_Bit 19 Bit 0 Bit 19

Slot 2

Bit 0

Slot 12

SLOTS 2 to 12SLOT 1

^0_

Tag bits: }ZÇv^o}^so]_]

Tag Phase 20.8 Ps

(48 kHz)

Data Phase

Status Address / Slot

Request bits for VSA

Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM data Data: Status and Audio

LM4550B

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Table 7. Slots 6 and 9, Output Frame

BIT DESCRIPTION COMMENT

PCM Audio Data Slots used to stream data to DAC when codec is in Secondary 3 mode.

19:0 (Center/ LFE Surround) Set unused bits to 0

8.5.1.1.7 SDATA_OUT: Slots 5, 10, 11, 12 – Reserved

These slots are unused by the LM4550B and should all be stuffed with zeros by the AC '97 Controller.

Figure 21. AC Link Input Frame

8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4550B Output

The AC Link Input Frame contains status and PCM data from the LM4550B control registers and stereo ADC.

Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and an

output from the LM4550B codec. As shown in Figure 18, Input Frames are constructed from thirteen time slots:

one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the

LM4550B. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the

validity of the data in the four of the twelve following Data Slots that are used by the LM4550B. Each Frame

consists of 256 bits with each of the twelve data slots containing 20 bits.

A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller

on a rising edge of BIT_CLK and, as shown in Figure 21 and Figure 22, the first tag bit in the Frame (Codec

Ready) is clocked from the LM4550B by the next rising edge of BIT_CLK. The LM4550B always clocks data to

SDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next falling

edge. The LM4550B samples SYNC on the falling edge of BIT_CLK.

Input and Output Frames are aligned to the same SYNC transition.

The LM4550B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high

transition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored, that is, no

valid data is sent on SDATA_IN until a valid new Frame is detected.

The LM4550B transmits data MSB first, in an MSB justified format. All reserved bits and slots are stuffed with 0s

by the LM4550B.

Product Folder Links: LM4550B

BIT_CLK

SDATA_IN

SYNC

LM4550B samples

SYNC assertion

LM4550B outputs

first bit of SDATA_IN

End of previous

Audio Frame

Codec

Ready

Slot

(1)

Slot

(2)

LM4550B

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Figure 22. Start of AC Link Input Frame

8.5.1.2.1 SDATA_IN: Slot 0 – Codec/Slot Status Bits

The first bit (bit 15, Codec Ready) of slot 0 in the AC Link Input Frame indicates when the codec's AC Link digital

interface and its status/control registers are fully operational. The digital controller is then able to read the LSBs

from the Power-down Control/Stat register (26h) to determine the status of the four main analog subsections. It is

important to check the status of these subsections after Initialization, Cold Reset or the use of the power-down

modes to minimize the risk of distorting analog signals passed before the subsections are ready.

The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1, 2, 3 and 4, respectively, are valid.

Table 8. Slot 0, Input Frame

BIT DESCRIPTION COMMENT

15 Codec Ready Bit 1 = AC Link Interface Ready

14 Slot 1 data valid 1 = Valid Status Address or Slot Request

13 Slot 2 data valid 1 = Valid Status Data

1 = Valid PCM Data

12 Slot 3 data valid (Left ADC)

1 = Valid PCM Data

11 Slot 4 data valid (Right ADC)

8.5.1.2.2 SDATA_IN: Slot 1 – Status Address / Slot Request Bits

This slot echoes (in bits 18 – 12) the 7-bit address of the codec control/status register received from the

controller as part of a read-request in the previous frame. If no read-request was received, the codec stuffs these

bits with zeros.

The 6 bits 11, 10, 8 – 5 are Slot Request bits that support the Variable Rate Audio (VRA) capabilities of the

LM4550B. Only two are used simultaneously. If the codec is in Primary mode or Secondary mode 1, then the left

and right channels of the DAC take PCM data from slots 3 and 4 in the Output Frame respectively (see Table 1).

The codec uses bits 11 and 10 to request DAC data from these two slots. If bits 11 and 10 are set to 0, the

controller should respond with valid PCM data in slots 3 and 4 of the next Output Frame. If bits 11 and 10 are set

to 1, the controller should not send data. Similarly, if the codec is in Secondary mode 2, bits 7 and 6 are used to

request data from slots 7 and 8 in the Output Frame. If in Secondary mode 3, bits 8 and 5 request data from

slots 6 and 9.

The codec has full control of the slot request bits. By default, data is requested in every frame, corresponding to

a sample rate equal to the frame rate (SYNC frequency) – 48 kHz when XTAL_IN = 24.576 MHz. To send

samples at a rate below the frame rate, a controller should set VRA = 1 (bit 0 in the Extended Audio

Control/Status register, 2Ah) and program the desired rate into the PCM DAC Rate register, 2Ch. Both DAC

channels operate at the same sample rate. Values for common sample rates are given in the Register

Descriptions section (Sample Rate Control Registers, 2Ch, 32h) but any rate between 4 kHz and 48 kHz (to a

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resolution of 1 Hz) is supported. Slot Requests from the LM4550B are issued completely deterministically. For

example if a sample rate of 8000 Hz is programmed into 2Ch then the LM4550B will always issue a slot request

in every sixth frame. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800

Hz will cause slot requests to be spaced alternately five and six frames apart. This determinism makes it easy to

plan task scheduling on a system controller and simplifies application software development.

The LM4550B will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. For

example, if the LM4550B is expecting data at a 8000 Hz rate yet the AC '97 Digital Audio Controller continues to

send data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the

DAC. The rest will be discarded.

Bits 9, 4, 3, and 2 are request bits for slots not used by the LM4550B and are stuffed with zeros. Bits 1 and 0 are

reserved and are also stuffed with zeros.

Table 9. SLOT 1, INPUT FRAME

BITS DESCRIPTION COMMENT

19 Reserved Stuffed with 0 by LM4550B

18:12 Status Register Index Echo of the requested Status Register address.

0 = Controller should send valid data in Slot 3 of the next Output

Slot 3 Request bit Frame.

11 (PCM Left Audio) 1 = Controller should not send Slot 3 data.

0 = Controller should send valid data in Slot 4 of the next Output

Slot 4 Request bit Frame.

10 (PCM Right Audio) 1 = Controller should not send Slot 4 data.

9 Slot 5 Request bit Unused - set to 0 by LM4550B

0 = Controller should send valid data in Slot 6 of the next Output

Slot 6 Request bit Frame.

8(PCM Center) 1 = Controller should not send Slot 6 data.

0 = Controller should send valid Slot 7 data in the next Output Frame.

Slot 7 Request bit

7(PCM Left Surround) 1 = Controller should not send Slot 7 data.

0 = Controller should send valid data in Slot 8 of next Output Frame.

Slot 8 Request bit

6(PCM Right Surround) 1 = Controller should not send Slot 8 data.

0 = Controller should send valid data in Slot 9 of next Output Frame.

Slot 9 Request bit

5(PCM LFE) 1 = Controller should not send Slot 9 data.

4:2 Unused Slot Request bits Stuffed with 0s by LM4550B

1,0 Reserved Stuffed with 0s by LM4550B

8.5.1.2.3 SDATA_IN: Slot 2 – Status Data

This slot returns 16-bit status data read from a codec control/status register. The codec sends the data in the

frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request was made

in the previous frame the codec will stuff this slot with zeros.

Table 10. SLOT 2, INPUT FRAME

BITS DESCRIPTION COMMENT

Data read from a codec control/status register.

19:4 Status Data Stuffed with 0s if no read-request in previous frame.

3:0 Reserved Stuffed with 0s by LM4550B

8.5.1.2.4 SDATA_IN: Slot 3 – PCM Record Left Channel

This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selected

using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record

Gain amplifier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2

LSBs are stuffed with zeros.

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Table 11. SLOT 3, INPUT FRAME

BITS DESCRIPTION COMMENT

19:2 PCM Record Left Channel data 18-bit PCM audio sample from left ADC

1:0 Reserved Stuffed with 0s by LM4550B

8.5.1.2.5 SDATA_IN: Slot 4 – PCM Record Right Channel

This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected

using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record

Gain amplifier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2

LSBs are stuffed with zeros.

Table 12. SLOT 4, INPUT FRAME

BITS DESCRIPTION COMMENT

19:2 PCM Record Right Channel data 18-bit PCM audio sample from right ADC

1:0 Reserved Stuffed with 0s by LM4550B

8.5.1.2.6 SDATA_IN: Slots 5 to 12 – Reserved

Slots 5 to 12 of the AC Link Input Frame are unused for data by the LM4550B and are always stuffed with zeros.

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8.6 Register Maps

8.6.1 LM4550B Register Map

DEFAUL

REG NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 T

00h Reset X 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0D50h

02h Master Volume Mute X ML5 ML4 ML3 ML2 ML1 ML0 X X MR5 MR4 MR3 MR2 MR1 MR0 8000h

Outp

ut 04h Headphone Volume Mute X ML5 ML4 ML3 ML2 ML1 ML0 X X MR5 MR4 MR3 MR2 MR1 MR0 8000h

Volu

me 06h Mono Volume Mute X X X X X X X X X MM5 MM4 MM3 MM2 MM1 MM0 8000h

0Ah PC_Beep Volume Mute X X X X X X X X X X PV3 PV2 PV1 PV0 X 0000h

0Ch Phone Volume Mute X X X X X X X X X X GN4 GN3 GN2 GN1 GN0 8008h

0Eh Mic Volume Mute X X X X X X X X 20dB X GN4 GN3 GN2 GN1 GN0 8008h

Input 10h Line In Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

Volu 12h CD Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

me 14h Video Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

16h Aux Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

18h PCM Out Volume Mute X X GL4 GL3 GL2 GL1 GL0 X X X GR4 GR3 GR2 GR1 GR0 8808h

ADC 1Ah Record Select X X X X X SL2 SL1 SL0 X X X X X SR2 SR1 SR0 0000h

Sour 1Ch Record Gain Mute X X X GL3 GL2 GL1 GL0 X X X X GR3 GR2 GR1 GR0 8000h

ces

20h General Purpose POP X 3D X X X MIX MS LPBK X X X X X X X 0000h

3D Control

22h X 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0101h

(Read Only)

X 24h Reserved X X X X X X X X X X X X X X X X 0000h

26h Power-down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh

28h Extended Audio ID ID1 ID0 X X X X AMAP 0 0 0 X X 0 X 0 VRA X201h

Extended Audio

2Ah X X X X X X X X X X X X X X X VRA 0000h

Control/Status

2Ch PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

32h PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

X 5Ah Vendor Reserved 1 X X X X X X X X X X X X X X X X 0000h

74h Chain-In Control X X X X X X X X X X X X X X ID1 ID0 000Xh

X 7Ah Vendor Reserved 2 X X X X X X X X X X X X X X X X 0000h

7Ch Vendor ID1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 4E53h

7Eh Vendor ID2 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 4350h

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8.6.2 Register Descriptions

Default settings are indicated by *.

8.6.3 Reset Register (00h)

Writing any value to this register causes a Register Reset which changes all registers back to their default

values. If a read is performed on this register, the LM4550B will return a value of 0D50h. This value can be

interpreted in accordance with the AC '97 specification to indicate that TI 3D Sound is implemented, 18-bit data is

supported for both the ADCs and DACs, and that headphone output is supported.

8.6.4 Master Volume Register (02h)

This output register allows the output level from either channel of the stereo LINE_OUT to be muted or

attenuated from 0 dB to 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for each channel

and both stereo channels can be individually attenuated. The mute bit (D15) acts simultaneously on both stereo

channels of LINE_OUT. The AC'97 specification states that “support for the MSB of the level is optional.” All six

bits may be written to the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0

11111. This will be the value when the register is read, allowing the software driver to detect whether the MSB is

supported or not.

MUTE Mx5:Mx0 FUNCTION

0 0 00000 0 dB attenuation

0 0 11111 46.5 dB attenuation

0 1 xxxxx As written

0 0 11111 As read back

1 X XXXXX *mute

Default: 8000h

8.6.5 Headphone Volume Register (04h)

This output register allows the level from both channels of HP_OUT to be muted or individually attenuated from 0

dB to 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for each channel plus one mute bit.

The mute bit (D15) acts on both channels. Operation of this register and HP_OUT matches that of the Master

Volume register and the LINE_OUT output. All six bits may be written to the register, but if the MSB is a 1, the

MSB is ignored and the register will be set to 0 11111. This will be the value when the register is read, allowing

the software driver to detect whether the MSB is supported or not

8.6.6 Mono Volume Register (06h)

This output register allows the level from MONO_OUT to be muted or attenuated from 0 dB to 46.5 dB in

nominal 1.5-dB steps. There are 6 bits of volume control and one mute bit (D15). All six bits may be written to the

when the register is read, allowing the software driver to detect whether the MSB is supported or not.

MUTE MM5:MM0 FUNCTION

0 0 00000 0 dB attenuation

0 0 11111 46.5 dB attenuation

0 1 xxxxx As written

0 0 11111 As read back

1 X XXXXX *mute

Default: 8000h

8.6.7 PC Beep Volume Register (0Ah)

This input register adjusts the level of the mono PC_BEEP input to the stereo mixer MIX2, where it is summed

equally into both channels of the Stereo Mix signal. PC_BEEP can be both muted and attenuated from 0 dB to

45 dB in nominal 3-dB steps.

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NOTE

The default setting for the PC_Beep Volume register is 0 dB attenuation rather than mute

MUTE PV3:PV0 FUNCTION

0 0000 *0-dB attenuation

0 1111 45-dB attenuation

1 XXXX mute

Default: 0000h

8.6.8 Mixer Input Volume Registers (Index 0Ch – 18h)

These input registers adjust the volume levels into the stereo mixers MIX1 and MIX2. Each channel may be

adjusted from 12-dB gain to 34.5-dB attenuation in 1.5-dB steps. For stereo ports, volumes of the left and right

channels can be independently adjusted. Muting a given port is accomplished by setting the MSB to 1. Setting

the MSB to 1 for stereo ports mutes both the left and right channels. The Mic Volume register (0Eh) controls an

additional 20 dB boost for the selected microphone input by setting the 20 dB bit (bit D6).

MUTE Gx4:Gx0 FUNCTION

0 0 0000 12-dB gain

0 0 1000 0-dB gain

0 1 1111 34.5-dB attenuation

1 X XXXX *mute

Default: 8008h (mono registers)

8808h (stereo registers)

8.6.9 Record Select Register (1Ah)

This register independently controls the sources for the right and left channels of the stereo ADC. The default

value of 0000h corresponds to selecting the (mono) Mic input for both channels.

SL2:SL0 SOURCE FOR LEFT CHANNEL ADC

0 *Mic input

1 CD input (L)

2 VIDEO input (L)

3 AUX input (L)

4 LINE_IN input (L)

5 Stereo Mix (L)

6 Mono Mix

7 PHONE input

Default: 0000h

SR2:SR0 SOURCE FOR RIGHT CHANNEL ADC

0 *Mic input

1 CD input (R)

2 VIDEO input (R)

3 AUX input (R)

4 LINE_IN input (R)

5 Stereo Mix (R)

6 Mono Mix

7 PHONE input

Default: 0000h

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8.6.10 Record Gain Register (1Ch)

This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record

Select Mux and are selected through the Record Select Control register, 1Ah. The gain of each channel can be

individually programmed from 0dB to 22.5dB in 1.5-dB steps. Both channels can also be muted by setting the

MSB to 1.

Table 13. Record Gain Register (1Ch)

MUTE Gx3:Gx0 FUNCTION

0 1111 22.5-dB gain

0 0000 0-dB gain

1 XXXX *mute

Default: 8000h

8.6.11 General Purpose Register (20h)

This register controls many miscellaneous functions implemented on the LM4550B. The miscellaneous control

bits include POP which allows the DAC output to bypass the TI 3D Sound circuitry, 3D which enables or disables

the TI 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which controls the Microphone

Selection mux and LPBK which connects the output of the stereo ADC to the input of the stereo DAC. LPBK

provides a mixed-mode analog-digital-analog loopback path between analog inputs and analog outputs. This is

an 18 bit digital loopback.

BIT FUNCTION

*0 = 3D allowed

POP PCM Out Path: 1 = 3D bypassed

*0 = off

3D TI 3D Sound: 1 = on

*0 = Mix

MIX Mono output select: 1 = Mic

*0 = MIC1

MS Mic Select: 1 = MIC2

*0 = No Loopback

LPBK ADC/DAC Loopback: 1 = Loopback

Default: 0000h

8.6.12 3D Control Register (22h)

This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depth

and center characteristics of the TI 3D Sound stereo enhancement.

8.6.13 Power-Down Control / Status Register (26h)

This read/write register is used both to monitor subsystem readiness and also to program the LM4550B power-

down states. The 4 LSBs indicate status and the 8 MSBs control power down.

The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage,

Analog mixers and amplifiers, DAC section, ADC section. When the Codec Ready indicator bit in the AC Link

Input Frame (SDATA_IN: slot 0, bit 15) is a 1, it indicates that the AC Link and AC '97 registers are in a fully

operational state and that control and status information can be transferred. It does not indicate that the codec is

ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determine

that readiness, the Controller must check that the 4 LSBs of this register are set to “1” indicating that the

appropriate audio subsections are ready.

The power-down bits PR0 – PR6 control internal subsections of the codec. They are implemented in compliance

with AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPI

and PCI Bus Power Management specification.

Product Folder Links: LM4550B

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

PR0 controls the power-down state of the ADC and associated sampling rate conversion circuitry. PR1 controls

power down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits

(MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixer

circuits as PR2. PR4 powers down the AC Link digital interface – see Figure 23 for signal power-down timing.

PR5 disables internal clocks. PR6 powers down the Headphone amplifier. EAPD controls the External Amplifier

Power-Down bit.

BIT# BIT FUNCTION: STATUS

0 ADC 1 = ADC section ready to transmit data

1 DAC 1 = DAC section ready to accept data

2 ANL 1 = Analog mixers ready

3 REF 1 = VREF is up to nominal level

BIT# BIT FUNCTION: POWER DOWN

8 PR0 1 = Power-down ADCs and Record Select Mux

9 PR1 1 = Power-down DACs

10 PR2 1 = Power-down Analog Mixer (VREF still on)

11 PR3 1 = Power-down Analog Mixer (VREF off)

12 PR4 1 = Power-down AC Link digital interface (BIT_CLK off)

13 PR5 1 = Disable Internal Clock

14 PR6 1 = Power-down Headphone Amplifier

External Amplifier Power Down

15 EAPD *0 = Set EAPD Pin to 0 (pin 47)

Default:000Fh if ready; otherwise 000Xh

8.6.14 Extended Audio Id Register (28h)

This read-only (X201h) register identifies which AC '97 Extended Audio features are supported. The LM4550B

features AMAP (Slot/DAC mappings based on Codec Identity), VRA (Variable Rate Audio) and ID1, ID0, the

Codec Identity bits used to support multi-codec systems. AMAP is indicated by a 1 in bit 9, VRA is indicated by a

1 in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#,

ID0#. The external logic connections to ID1#, ID0# (pins 46 and 45) are inverse in polarity to the value of the

Codec Identity (ID1, ID0) held in bits D15, D14. The AMAP Slot/DAC mappings are given in Table 1 in the

Multiple Codec section. Codec mode selections are shown in the table below.

PIN 46 PIN 45 D15,28h D14,28h CODEC IDENTITY

(ID1#) (ID0#) (ID1) (ID0) MODE

NC/DVDD NC/DVDD 0 0 Primary

NC/DVDD GND 0 1 Secondary 1

GND NC/DVDD 1 0 Secondary 2

GND GND 1 1 Secondary 3

8.6.15 Extended Audio Status/control Register (2Ah)

This read/write register provides status and control of the variable sample rate capabilities in the LM4550B.

Setting the LSB of this register to 1 enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample

rates to be programmed through registers 2Ch and 32h respectively.

BIT FUNCTION

VRA *0 = VRA off (Frame-rate sampling)

1 = VRA on

Default: 0000h

Product Folder Links: LM4550B

LM4550B

www.ti.com

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

8.6.16 Sample Rate Control Registers (2Ch, 32h)

These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DAC

Rate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled through bit 0 of the

Extended Audio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be

any value from 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample

rate, that is, 800010 = 1F40h. Below is a list of the most common sample rates and the corresponding register

(hex) values.

Table 14. Common Sample Rates

SR15:SR0 SAMPLE RATE (Hz)

1F40h 8000

2B11h 11025

3E80h 16000

5622h 22050

AC44h 44100

*BB80h *48000

8.6.17 Chain-in Control Register (74h)

This read/write register is only needed when using the Chain In feature. This feature goes beyond the AC '97

specification and is not required for standard AC Link operation. The two LSBs of this register default to the

Codec Identity (ID1, ID0) after reset. This default state corresponds to standard AC Link operation where the

output of codec pin 8 (SDATA_IN) carries the AC Link Input Frames back to the controller from the codec.

If the two LSBs differ from the Codec Identity (register 28h describes the Codec Identity), then the signal present

at CIN (pin 48) is switched through to the SDATA_IN (pin 8) output. In this fashion, Secondary codecs can be

chained together by connecting one codec's SDATA_IN pin to the next codec's CIN pin. This has the end result

of only requiring a single SDATA_IN pin at the controller rather than the standard one SDATA_IN pin per codec.

Note, however, that the chained codecs time-share the bandwidth of the SDATA_IN signal under allocation from

the controller.

The first codec in the chain (nearest the controller) will have access to the full bandwidth of SDATA_IN following

a system reset (Cold Reset for each codec). To access any other codec in the chain, the controller must write a

suitable value (that is, the Identity of the target codec) to the Chain-In Control register (74h) of each intervening

codec in the chain.

The last codec in the serial chain (furthest from the controller) should have its CIN pin connected to digital

ground. When writing software drivers, take care to avoid any problems that could occur when this last codec in

the chain is set to pass a CIN signal when there is none to pass. Different controllers may handle an input of all

0s differently and leaving the CIN pin floating should definitely be avoided.

BIT# FUNCTION

*(bit1,bit0) = (ID1,ID0): Chain-In off

1,0 (bit1,bit0) ≠(ID1,ID0): Chain-In on

8.6.18 Vendor ID Registers (7Ch, 7Eh)

These two read-only (4E53h, 4350h) registers contain TI's Vendor ID and TI's LM45xx codec version

designation. The first 24 bits (4Eh, 53h, 43h) represent the three ASCII characters that are the TI Vendor ID for

Microsoft's Plug and Play. The last 8 bits are the two binary coded decimal characters, 5, 0 and identify the

codec to be an LM4550 family part.

8.6.19 Reserved Registers

Do not write to reserved registers. In particular, do not write to registers 24h, 5Ah and 7Ah. All registers not listed

in the LM4550B Register Map are reserved. Reserved registers will return 0000h if read.

Product Folder Links: LM4550B

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

Slot 12

Prev. Frame TAG

TAG

Slot 0

Slot 12

Prev. Frame

Write to

REG. 26h

Data

PR4 = 1

Note: BIT_CLK and data transitions are not to scale TS2_PDOWN

Slot 1 Slot 2

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

8.6.20 Low Power Modes

The LM4550B provides 7 bits to control the power-down state of internal analog and digital subsections and

clocks. It also provides one bit intended to control an external analog power amplifier. These 8 bits (PR0 – PR6,

EAPD) are the 8 MSBs of the Power-Down Control/Status register, 26h. The status of the four main analog

subsections is given by the 4 LSBs in the same register, 26h.

The power-down bits are implemented in compliance with AC '97 Rev 2.1 to support the standard device power

management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification.

PR0 controls the power-down state of the ADC and associated sampling rate conversion circuitry. PR1 controls

power down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits

(MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down VREF in addition to all the same mixer

circuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 23 for signal power-down timing.

PR5 disables internal clocks but leaves the crystal oscillator and BIT_CLK running (needed for minimum Primary

mode power-down dissipation in multi-codec systems). PR6 powers down the Headphone amplifier. EAPD

controls the External Amplifier Power-Down pin (pin 47).

After a subsection has undergone a power-down cycle, the appropriate status bit(s) in the Power-down

Control/Status register (26h) must be polled to confirm readiness. In particular the startup time of the VREF

circuitry depends on the value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel is

recommended).

When the AC Link Digital Interface is powered down the codec output signals SDATA_IN and BIT_CLK (Primary

mode) are cleared to zero and no control data can be passed between controller and codec(s). This power-down

state can be cleared in two ways: Cold Reset (RESET# = 0) or Warm Reset (SYNC = 1, no BIT_CLK). Cold

Reset sets all registers back to their default values (including clearing PR4) whereas Warm Reset only clears the

PR4 bit and restarts the AC Link Digital Interface leaving all register contents otherwise unaffected. For Warm

Reset (see Timing Diagrams), the SYNC input is used asynchronously. The LM4550B codec allows the AC Link

digital interface power-down state to be cleared immediately so that its duration can essentially be as short as

TSH, the Warm Reset pulse width. However for conformance with AC '97 Rev 2.1, Warm Reset should not be

applied within 4 frame times of power down, that is, the AC Link power-down state should be allowed to last at

least 82.8 µs.

Figure 23. AC Link Power-Down Timing

Product Folder Links: LM4550B

LM4550B

www.ti.com

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM4550B is an audio codec used for PC systems. It is typically used in systems which are fully PC99

compliant and performs analog functions of the AC '97 Rev 2.1 architecture.

9.1.1 Improving System Performance

The audio codec is capable of dynamic range performance in excess of 90 dB., but the user must pay careful

attention to several factors to achieve this. A primary consideration is keeping analog and digital grounds

separate, and connecting them together in only one place. Some designers show the connection as a 0-Ω

resistor, which allows naming the nets separately. Although it is possible to use a two layer board, TI

recommends that a minimum of four layers be used, with the two inside layers being analog ground and digital

ground. If EMI is a system consideration, then as many as eight layers have been successfully used. The 12 and

25 MHz. clocks can have significant harmonic content depending on the rise and fall times. Bypass capacitors

should be very close to the package. The analog VDD pins should be supplied from a separate regulator to

reduce noise. By operating the digital portion on 3.3 V. instead of 5 V. an additional 0.5-0.7 dB improvement can

be obtained.

The bandgap reference and the anti-pop slow turnon circuit were improved in the LM4550B. A pullup resistor is

not required on VREF, pin 27. For an existing design, the 10-kΩresistor can be left on the PCB, but the

temperature coefficient will improve with no resistor on this pin. In addition, the THD will improve by 0.2–0.5 dB.

The external capacitor is charged by an internal current source, ramping the voltage slowly. This results in slow

turnon of the audio stages, eliminating “pops and clicks”. Thus, turnon performance is also improved. The pullup

resistor, in conjunction with the internal impedance and the external capacitor, form a frequency dependent

divider from the analog supply. Noise on the analog supply will be coupled into the audio path, with

approximately 30 dB. of attenuation. Although this is not a large amount if the noise on the supply is tens of

millivolts, it will prevent SNR from exceeding 80 dB.

In Figure 24 and Figure 25, the input coupling capacitors are shown as 1-µF capacitors. This is only necessary

for extending the response down to 20 Hz. for music applications. For telematics or voice applications, the lower

3 dB. point can be much higher. Using a specified input resistance of 10 kΩ, (40 kΩtypical), a 0.1-µF capacitor

may be used. The lower 3 dB point will still be less than 300 Hz. By using a smaller capacitor, the package size

may be reduced, leading to a lower system cost.

9.1.2 Backwards Compatibility

The LM4550B is improved compared with the LM4550. If it is required to build a board that will use either part, a

10 kΩresistor must be added from the VREF pin (pin 27) to AVDD for the LM4550. It is not required for the

LM4550B. Addition of this resistor will slightly increase the temperature coefficient of the internal bandgap

reference and slightly decrease the THD performance, but overall performance will still be better than the

LM4550.

The LM4550 requires that pins 1 and 9 (DVDD) connect directly to a 27 nH. inductor before going to the 3.3 Volt

digital supply and the bypass capacitors. The inductor is not required for the LM4550B and should not be used.

Product Folder Links: LM4550B

Line

Input

LM4550B

$&µ97 Rev 2.1

Codec

LINE_IN_R

24 LINE_IN_L

23 LINE_OUT_L 1.0 PF

35 Line

Output

AVDD1 DVDD1

DVSS1 DVSS2

DVDD2

AVSS1

Microphone

Inputs MIC2

22 MIC1

Input CD_GND

19 CD_L

CD_R

Video

Input VIDEO_R

17 VIDEO_L

Auxiliary

Input AUX_R

15 AUX_L

Mono

Inputs PHONE

PC_BEEP

BIT_CLK

6SDATA_OUT

SDATA_IN

SYNC

RESET#

XTAL_IN

XTAL_OUT

33 pF

1 M:

$&µ97

Digital

Controller

24.576 MHz

Analog

Ground Digital

Ground Connect Grounds at a single point

underneath or close to the package

LINE_OUT_R 1.0 PF

HP_OUT_L 220 PF

HP_OUT_C 1.0 PF

HP_OUT_R 220 PF

Headphone

Output

1.0 PF

MONO_OUT

VREF

3DN

VREF_OUT

0.1 PF 3.3 PF

3DP

34 0.022 PF

Optional: for

National 3D Sound

ID0#

ID1#

26 4 7

CIN

EAPD 47

NC Default setting:

Primary Codec (ID 00)

External Amplifier

Power Down

Mono

Output

1 PF

0.1 PF

5V Analog Supply

All NC pins should

normally be left floating.

See Pin Descriptions for

details

VREF Output

(For external

microphone bias)

1.0 PF

+++++++

AVDD 3.3V or 5V Digital Supply

1 PF

0.1 PF

AVSS2

AVDD2

0.1 PF 1 PF+

++++ +

See text for cap values

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

9.2 Typical Application

Figure 24. System Example

9.2.1 Design Requirements

• Single codec output

• 1-Vrms input

Product Folder Links: LM4550B

LM4550B

NC 30

VREF_OUT

SYNC

SDATA_OUT

BIT_CLK

RESET#

SDATA_IN

6.81k

R24

47k

HP_OUT_L

HP_OUT_C

HP_OUT_R

RESET#

AVDD1

AVSS1

HEADPHONE

JACK

R23

10k

220 pF

220pF

R22

10k

+ +

C31

C32

220 PF

220 pF

2.2k

SYNC 10

SDATA_IN 8

SDATA_OUT 5

BIT_CLK 6

EAPD

MONO_OUT 47

DVDD1

DVDD2

DVSS1

DVSS2

PC_BEEP

LINE_IN_L

LINE_IN_R

CD_L

CD_GND

CD_R

AUX_L

AUX_R

MIC1

MIC2

VIDEO_R

VIDEO_L

PHONE

ID0#

ID1#

VREF

3DN 3DP XTAL_OUTXTAL_IN

33 34

C8 0.022 PF

2 3

33 pF

R25

24.576 MHz

C28

1 PF

220PF

LINE_OUT_L

LINE_OUT_R 35

NC 32

1 M:

33 pF

C1 C2 R1

0:AGNDDGND

220 pF

R21

10k

C27

1 PF

220 pF

R20

10k

C26

1 PF

CIN 48

0.1 PF

C12

C13 3.3 PF

C30

0.1 PF

C18

1 PF

6.81k

C29

2.2 PF

C17

1 PF

6.81k

C19

1 PF

6.81k

MICROPHONE

JACK

LINE INPUT JACK

LINE_IN

LINE OUTPUT JACK

CD INPUT HEADER

AUXILIARY INPUT

HEADER

R15

6.81k

C23

1 PF

R16

6.81k

R17

6.81k

C24

1 PF

R18

6.81k

R11

6.81k

C21

1 PF

R12

6.81k

R13

6.81k

C22

1 PF

R14

6.81k

C20

1 PF

R10

6.81k

CD_IN

MIC1

LINE_OUT

HP_OUT

AUX_IN

PC_BEEP

+3.3V LM78M05 3

VIN VOUT

GND

+7.5V - +20V

C34

0.33 PFC33

0.1 PF

AVDD

Digital

Supply

NC 43

NC 44

  

 Optional for LM4550B. Will improve transient

response.

Optional. Not required if LM78M05 is < 4 in. from an

input filtering capacitor

C25

1 PF

C14

1 PF

C11

0.1 PF

AVSS2

42 AVDD2

38 25

C16

1 PF

0.1 PF

C39

1 PF

C38

0.1 PF

LM4550B

www.ti.com

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

Typical Application (continued)

9.2.2 Detailed Design Procedure

For all analog inputs a 1.0-µF capacitor should be tied to the input for proper decoupling. If the pin is unused

then a 1.0-µF capacitor should be used and tied to ground.

For analog input pins, a proper lowpass filter will be needed to filter out any high frequencies depending on the

application. See Figure 25.

Digital and analog voltage supplies should have proper decoupling capacitors that cover low and high frequency

spikes. In our application we chose to go with 1.0-µF and 0.1-µF capacitors.

9.3 System Examples

Figure 25. LM4550B Reference Design, Typical Application, Single Codec, 1 Vrms and 2 Vrms inputs,

EMC output filters

Product Folder Links: LM4550B

LM4550B

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

www.ti.com

10 Power Supply Recommendations

The LM4550B is designed to operate from a digital supply range between 3.0 V and 5.5 V. Analog supply range

is between 4.2 V and 5.5 V.

Connecting to 1-µF and 0.1-µF decoupling capacitors in series on both the analog and digital supply pins is

recommended.

In typical applications 3.3 V or 5 V is used for the digital supply and 5 V is used for the analog supply.

11 Layout

11.1 Layout Guidelines

• The LM4550B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On

Reset Timing Diagram

• Don't leave unused Analog inputs floating. Tie all unused inputs together and connect to Analog Ground

through a capacitor (for example, 0.1 µF)

• Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the

CD channels and should be connected to the CD source ground (Analog Ground may also be acceptable)

through a 1-µF capacitor

• If using a non-standard AC Link controller take care to keep the SYNC and SDATA_OUT signals low during

Cold Reset to avoid accidentally activating the ATE or Vendor test modes

• The PC_Beep input should be explicitly muted if not used because it defaults to 0-dB gain on reset, unlike the

mute default of the other analog inputs

Product Folder Links: LM4550B

LM4550B

www.ti.com

SNAS276G –MAY 2005–REVISED SEPTEMBER 2015

12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LM4550B

PACKAGE OPTION ADDENDUM

www.ti.com 13-May-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM4550BVH NRND LQFP PT 48 250 TBD Call TI Call TI -40 to 85 LM4550

BVH

LM4550BVH/NOPB ACTIVE LQFP PT 48 250 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LM4550

BVH

LM4550BVHX/NOPB ACTIVE LQFP PT 48 1000 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LM4550

BVH

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 13-May-2015

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM4550BVHX/NOPB LQFP PT 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM4550BVHX/NOPB LQFP PT 48 1000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-May-2015

Pack Materials-Page 2

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

4040052/C 11/96

0,13 NOM

0,17

0,27

6,80

7,20

5,50 TYP

0,25

0,45

0,75

0,05 MIN

9,20

8,80

1,35

1,45

1,60 MAX

Gage Plane

Seating Plane

0,10

0°–7°

0,50 M

0,08

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

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endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

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Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

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