September 1983
Revised February 1999
MM74HC595 8-Bit Shift Regi sters with Output Latches
© 1999 Fairchild Semicond uctor Corpor ation DS005342.prf www.fairchildsemi.com
MM74HC595
8-Bit Shift Registers with Output Latches
General Descript ion
The MM74HC595 high speed shift register utilizes
advanced s ilicon- gate CM OS techn ology. This devi ce pos-
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-over riding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge trig-
gered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 74HC lo gic fa mi ly i s spe ed, fun c tion , an d p in-o ut co m-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static di scharge by inte rnal
diode clamps to VCC and ground.
Features
■Low quiescen t curre nt: 80 µA maximum (74HC S erie s)
■Low input curre nt: 1 µA maximum
■8-bit serial-in, parallel-out shift register with storage
■Wide operat i ng voltage range: 2V–6 V
■Cascadable
■Shift register has direct clear
■Guaranteed shift frequency: DC to 30 MHz
Ordering Code:
Devices also ava ilable in Ta pe and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
Order Number Package Number Package Description
MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC595WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC595N N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
RCK SCK SCLR GFunction
XX XHQ
A thru QH = 3-STATE
X X L L Shift Register cleared
QH = 0
X↑H L Shift Register clocked
QN = Qn-1, Q0 = SER
↑X H L Contents of Shift
Register transferred
to output latches
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MM74HC595
Logic Diagram
(positive logic)
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MM74HC595
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute M aximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unles s ot herwise specified all v olt ages are referenc ed to ground.
Note 3: Power Dis sipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: F or a pow er sup ply of 5V ±1 0% the worst case output voltages (VOH, and V OL) occu r for HC a t 4.5V. Thus the 4.5V values shou ld be use d when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V a nd 4.5V respectiv ely. (The VIH v alue at 5. 5V is 3.8 5V.) The worst c as e leakage cur-
rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher volta ge and so th e 6. 0V values s hould be used.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)±20 mA
DC Output Current, per pin (IOUT)±35 mA
DC VCC or GND Current,
per pin (ICC)±70 mA
Storage Temperature Range (TSTG)−65°C to +150°C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Solder ing 10 seco nds) 260°C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operati ng Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) VCC
= 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
QHVIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V
QA thru QHVIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
QHVIN = VIH or VIL
|IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
QA thru QHVIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maxim um Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
IOZ Maxim um 3-STATE VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA
Output Leakage G = VIH
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA
Supply Current IOUT = 0 µA
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MM74HC595
AC Electrical Characteristics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-
age register sta t e w ill be one cloc k pulse be hind the sh if t re gis t er.
AC Electrical Characteristics
VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol Parameter Conditions Typ Guaranteed Units
Limit
fMAX Maximum Operating 50 30 MHz
Frequency of SCK
tPHL, tPLH Maximum Propagation CL = 45 pF 12 20 ns
Delay, SCK to QH’
tPHL, tPLH Maximum Propagation CL = 45 pF 18 30 ns
Delay, RCK to QA thru QH
tPZH, tPZL Maximum Output Enable RL = 1 kΩ
Time from G to QA thru QHCL = 45 pF 17 28 ns
tPHZ, tPLZ Maximum Output Disable RL = kΩ15 25 ns
Time from G to QA thru QHCL = 5 pF
tSMinimum Setup Time 20 ns
from SER to SCK
tSMinimum Setup Time 20 ns
from SCLR to SCK
tSMinimum Setup Time 40 ns
from SCK to RCK
(Note 5)
tHMinimum Hold Time 0ns
from SER to SCK
tWMinimum Pulse Width 16 ns
of SCK or RCK
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
fMAX Maximum Operating CL = 50 pF 2.0V 10 6 4.8 4.0 MHz
Frequency 4.5V 45 30 24 20 MHz
6.0V 50 35 28 24 MHz
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 58 210 265 315 ns
Delay from SCK to QHCL = 150 pF 2.0V 83 294 367 441 ns
CL = 50 pF 4.5V 14 42 53 63 ns
CL = 150 pF 4.5V 17 58 74 88 ns
CL = 50 pF 6.0V 10 36 45 54 ns
CL = 150 pF 6.0V 14 50 63 76 ns
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 70 175 220 265 ns
Delay from RCK to QA thru QHCL = 150 pF 2.0V 105 245 306 368 ns
CL = 50 pF 4.5V 21 35 44 53 ns
CL = 150 pF 4.5V 28 49 61 74 ns
CL = 50 pF 6.0V 18 30 37 45 ns
CL = 150 pF 6.0V 26 42 53 63 ns
tPHL, tPLH Maximum Propagation 2.0V 175 221 261 ns
Delay from SCLR to QH4.5V 35 44 52 ns
6.0V 30 37 44 ns
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MM74HC595
AC Electrical Characteristics (Continued)
Note 6: CPD determ ines the no load dynamic po w er c onsump ti on, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumptio n,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
tPZH, tPZL Maximum Output Enable RL = 1 kΩ
from G to QA thru QHCL = 50 pF 2.0V 75 175 220 265 ns
CL = 150 pF 2.0V 100 245 306 368 ns
CL = 50 pF 4.5V 15 35 44 53 ns
CL = 150 pF 4.5V 20 49 61 74 ns
CL = 50 pF 6.0V 13 30 37 45 ns
CL = 150 pF 6.0V 17 42 53 63 ns
tPHZ, tPLZ Maximum Output Disable RL = 1 kΩ2.0V 75 175 220 265 ns
Time fro m G to QA thru QHCL = 50 pF 4.5V 15 35 44 53 ns
6.0V 13 30 37 45 ns
tSMinimum Setup Time 2.0V 100 125 150 ns
from SER to SCK 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tRMinimum Removal Time 2.0V 50 63 75 ns
from SCLR to SCK 4.5V 10 13 15 ns
6.0V 9 11 13 ns
tSMinimum Setup Time 2.0V 100 125 150 ns
from SCK to RCK 4.5V 20 25 30 ns
6.0V 17 21 26 ns
tHMinimum Hold Time 2.0V 5 5 5 ns
SER to SCK 4.5V 5 5 5 ns
6.0V 5 5 5 ns
tWMinimum Pulse Width 2.0V 30 80 100 120 ns
of SCK or SCLR 4.5V 9 16 20 24 ns
6.0V 8 14 18 22 ns
tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time, Clock 4.5V 500 500 500 ns
6.0V 400 400 400 ns
tTHL, tTLH Maximum Output 2.0V 25 60 75 90 ns
Rise and Fall Time 4.5V 7 12 15 18 ns
QA–QH6.0V 6 10 13 15 ns
tTHL, tTLH Maximum Output 2.0V 75 95 110 ns
Rise & Fall Time 4.5V 15 19 22 ns
QH6.0V 13 16 19 ns
CPD Power Dissipation G = VCC 90 pF
Capacitance, Outputs G = GND 150 pF
Enabled (Note 6)
CIN Maximum Input 5 10 10 10 pF
Capacitance
COUT Maximum Output 15 20 20 20 pF
Capacitance
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MM74HC595
Timing Diagr am
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Packag e Num be r MTC 16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC595 8-Bit Shift Registers with Output Latches
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a life su pport
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual--Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
