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Understanding Clocked FIFOs
Introduction
This application note explains the basic operations and fea-
tures of Cypress clocked FIFO memories. Cypress clocked
FIFOs are ideally suited for applications requiring high data
throughput and asynchronous data buffering. The clocked
FIFO interface simplifies high-speed design and provides
greater noise immunity over indus try-standard asy nchronous
FIFOs.
Design considerations of the clocked FIFO architecture are
examined, including proper flag operation and decoding,
FIFO boundary operation, and resetting and programming
the FIFO. FIFO depth and width expans io n are also cove red .
The Cypress family of cloc ked FIFOs are available in several
densiti es with a variety of featur es.
Table 1
outlines the fea-
tures of Cypress’s clocked FIFOs. The entire clocked FIFO
family feature fully asynchronous operation at clock rates of
up to 70 MHz in non-depth expansion mode. Clocked FIFOs
cascaded for depth expansion can operate at frequencies of
up to 50 MHz.
The CY7C441 and CY7C443 feature 512 and 2K word by 9
bit memory arrays, respectively. These FIFOs feature
high-speed operation and Empty, AlmostEmpty, an d Almost-
Full flags, c enter power and ground pins, and width expand-
ability. Both FIFOs are available in either a 32-pin PLCC/LCC
package or a 28-pin DIP package.
The CY7C451 and CY7C453 clocked FIFOs have all of the
features of the 7 C44X FIFOs plus F ull and HalfFull flags, pro-
grammable AlmostEmpty and AlmostFull flags, parity gener-
ation and parity checking, output enable (OE), and depth ex-
pandability. The 7C451 features a 512 word by 9 bit memory
array and the 7C453 features a 2K word by 9 bit memory
array. Both FIFOs are available in either a 32-pin PLCC/LC C
package or a 32-pin DIP package.
Table 1. Features of Cypress Clocked FIFOs
FIFO Density Speed Flag
Architecture Parity Output
Enable Depth
Expandable Width
Expandable
7C441 512 x 9 71.4 MHz Synchronous No No No Ye s
7C443 2048 x 9 71.4 MHz S ynchronous No No No Yes
7C451 512 x 9 71.4 MHz Synchronous,
Programmable Programmable Yes Yes* Yes
7C453 2048 x 9 71.4 MHz S ynchronous,
Programmable Programmable Yes Yes* Yes
7C455 512 x 18 71.4 MHz Synchronous,
Programmable Programmable Yes Yes* Yes
7C456 1024 x 18 71.4 MHz Synchronous,
Programmable Programmable Yes Yes* Yes
7C457 2048 x 18 71.4 MHz Synchronous,
Programmable Programmable Yes Yes* Yes
* 50 MHz in this mo de
Understanding Clocked FIFOs
2
Clocked Architecture
The clocked FIFO architecture is designed to achieve maxi-
mum performance from FIFO memories while simplifying
their use in a system. T iming pulse s for the memory array are
generated internally from the read and write c locks thus elim-
inating the need for generating very narrow external read and
write pulses.
The read and write ports have separate clock inputs (CKR,
CKW), and read and write operations are enabled through
separate clock-enable pins (ENR, ENW). The read and write
clocks can be fully asynchronous.
Figure 1
demonstrates
asynchronous reading and writing to a clocked FIFO .
The clocked FIFO interface is ideally suited for state machine
control. A state machine can perfor m reads or writes by sim-
ply asserting the respective enable lines LOW. It is not nec-
essary to toggle the e nable lines to perform consecutive op-
erations.
FIFO Writes
Figure 2
shows a simplified block diagram of the clocked
FIFO data path. The internal wr ite control logic circuitry con-
trols the input register, t he write pointer, and the write p ort of
the dual-ported memory array.
This write operation is similar to writing to a standard 377
register. The FIFO input r egister is clocked by CKW and en-
abled by ENW. Data is clocked into the FIFO on the enabled
rising edge of CKW. The data is then written into the memory
location pointe d to by t he writ e pointer, provided the FIFO is
not full (Full = 1). The write pointer is then incremented. A full
FIFO will ignore any attempted write without upsetting the
memory array or the fla gs. The 70-MHz clocked FIFOs have
a data and enable set-up time (tSD and tSEN) of 7 ns.
FIFO Reads
The internal read control logic circuitry controls the output
reg ister , the read p ointer , and the read port of the dual-ported
memory array. The output register holds the word that was
last read from the FIFO memory array. This register is loaded
from the memory arr ay in a manner similar to loading a stan-
dard 377 register. The output register is clocked by CKR and
enabled by ENR. Note that the CY7C45X family of clocked
FIFOs feature a three-state output register controlled b y OE.
The re ad pointer points to a wor d in the memor y array. T hat
word is loaded into the output register on the enabl ed rising
edge of CKR, provided the FIFO is not empty (Empty
= 1),
and the read pointer is then increment ed. The word is avail-
able at the output pins tA after the clock edge. An empty FIFO
will ignore the attempted read and continue to hold the last
wor d in its output regist er. The set-up time for ENR (tSEN) is
7 ns and the data access time (tA) is 10 ns for a 70-MHz
clocked FIFO.
Flag Architectur e
Cypress clocked FIFOs feature a synchronous encoded flag
architecture that simplifies FIFO integration into a synchro-
nous s ystem. Synchronou s flags gua rantee that a flag update
is only trig gered by a rising clock edge. The state of a flag is
guaranteed to be valid tFD after the rising clock edge.
Unclocked asynchronous FIFOs can generate narrow flag
pulses with indeterminate timing based o n the timing relation-
ship of read and write pulses. External flag synchronization
Figure 1. Asynchrous Writing and Reading to a Clocked FIFO
CKW
ENW
D0-D8
CKR
ENR
Q0-Q8
WRITE WRITE WRITE WRITE
READ READ
tSD
tHD
tSEN
tHEN
tSEN
tHEN
tA
Understanding Clocked FIFOs
3
logic is required in synchronous designs using unclocked
FIFOs. The Clocked FIFO architecture eliminates these short
flag pulses and avoids the n eed for external flag synchroni-
zation logic.
A small pack age footprint is maintained by encoding the state
of the flags. Pin count and package size are reduced and
fewer PCB board signals req uire routing. Only two signa ls are
needed to encode four states of the 7C44X FIFOs and three
signals encode six states of the 7C45X FI FOs.
The FIFO flags are easily decoded inside a programmable
control unit or a state machine controller. Decoding the sig-
nals properly produces fla gs synchronized to a single clock.
Figures
3
and
4
show a block diagram o f the flag architecture
for both the 7C44X and 7C45X FIFOs. The diagrams also
show the external logic needed to decode and synchronize
the flags.
The decoded Empty-type flags are synchronized to the read
clock (CKR) and decoded Fu ll-type flags are synchronized to
the write clock (CKW). The CY7C45X family of Clocked FIFOs
features a Programmable Almost Full/Empty flag (P AFE) that
is synchronized to the re ad and write clocks. Reads and
Writes with Boundary Flags
The Empty and Full flags are considere d Boundary flags be-
cause they indicate that t he FIFO h as reached its boundary
of operation. Attention must be paid to the status of these
flags when operating the FIFO a t or near the b oundaries. The
internal FIFO write and read control logic uses the Boundary
flags to determ ine if an a ccess to the memory array is possi-
ble. The internal write control logic will not attempt to write to
the memory array or increment the write pointer i f the FIFO is
Full, as indicated by the registered Full flag. Similarly , the read
control logic will not load the output register or increment the
Read Pointer if the FIFO is empty, as indicated by the regis-
tered Empty flag ( s ee
Fi gures 2
,
3
, and
4
).
The boundary flags determine the state of the read and write
logic control circuits inside the Clocked FIFO. Design con sid-
erations with boundary flags are explored in the next two sec -
tions.
Boundary Latency C ycles
A write or a read can cause the FIFO memory array to exit
from an empty- or full-boundary condition. At the empty
boundary, the FIFO write control logic will allow an enabled
write clock to store a word in the memory array. Howev er, the
Empty flag synchronization register will not reflect the current
state of the FIFO memory array until it is clocked by the read
clock. Similarly, at the full boundary, the FIFO read control
logic will all ow an enabled read clock to remove a word fro m
the memory array, but the Full flag synchronization register
will not reflect the curre nt state of the FIFO until it is clocke d
by write cl ock.
Figure 2. Clocked FIFO Data Path
INPUT
REGISTER
OUTPUT
REGISTER
WRITE
POINTER READ
POINTER
WRITE
CONTROL
LOGIC
READ
CONTROL
LOGIC
FLAG
LOGIC
DUAL-PORT
RAM ARRAY
(512 x 9)
(2048 x 9)
D0-D8
Q0-Q8 OE
(45X only)
ENW
ENR
CKW
CKR
FLAGS
Full
Empty
Understanding Clocked FIFOs
4
A FIFO latency cycle (update cycle) refers to the clo ck cycle
that causes a b oundary flag register to be updated with the
current status of th e memory array. During this cycle, only a
boundary flag register is updated regardless of the state of
ENR or ENW. A rea d-clock latency cycle updates the Empty
flag register from LOW to HIGH regardless of the state of
ENR. When the Empty flag register is in the HIGH state, a n
enabled read clock can retrieve data from the memory array.
The overall effect is that after the FIFO memory becomes
non-empty, it takes two read cycles to get the first word fr om
the FIFO-one to update the f lag and one to read the data.
Similarly , a write clock latenc y c ycle up dates the Fu ll flag reg-
ister from LOW to HIGH regardless of the state of ENW.
When the Full flag register is in t he HIGH state, an enabled
write clock can store data in the memory array. The overall
result is that after the FIFO memory beco mes no n-full, it takes
two write cycles to put the first word in the FIFO.
This type of flag operation is desirable becau s e i t guarantees
that flags in the inactive (HIGH) state will be valid and usable
for at least one clock cycle. This arch itecture eliminates inde-
terminate short flag pulses characteristic of asynchronous
flag architectures.
Free-Running CKR and CKW Clock s
Boundary-operation timing and latency cycles should pose no
problem in designs that employ free-running read and write
clocks. Free-running cloc ks ins ure that flag update c ycles will
be performed automatically. The flag registers will be con-
stantly updated wit h the current FIFO status.
Designs that do not use free-running clocks must explicitly
issue a clock cycle near the FIFO boundaries in order to up-
date the flag registers. Absence of free-running clocks may
decrease system performance by causing the external c on-
trol circuitry to wait for one clock cycle during the flag update
cy cle before per forming an operation.
Figure 3. 7C45X Flag Architecture
Full
AlmostEmpty
Empty
CKW
CKR
CKR
Empty +
AlmostEmpty
Empty
Full +
AlmostFull
DQ
DQ
DQ
7C4 5X Inte rnal Flag Logic Exte rnal Flag Decode LogicPins
(synchronized to CKW)
(synchronized to CKR)
(synchronized to CKR)
(22v10,PLD,FPGA,etc.)
DQ
DQ
AlmostFull
CKW
CKW
HalfFull
(programmable)
(programmable)
E/F
HF
PAFE
Full
(synchronized to CKW)
S ynch ro ni zatio n Reg iste r s
To Write Control Logic
To Read Control Logic
Understanding Clocked FIFOs
5
Resetting and Programming Clocked FIFOs
Master Reset
Clocked FIFOs are reset by pulsing the MR (Master Reset)
pin LOW . Resetting the FIFO clears the read and write point-
ers so that they both point to location zero of the memory
array, ca using the FIFO to be Empty. The data o utput register
will contain al l 0s af ter the re set pulse occurs. Master Reset
also resets the internal read and write control logic cir cuits.
The 7 C45X family of clocke d FIFOs can also be programmed
during Master Rese t. P rogramming the FIFO causes the pro-
gram word to be stored in the FIFO program register.
Clocked FIFOs generate internal timing pulses off of the fall-
ing edge of MR in order to reset and program the internal
FIFO control logic. For this reason, it is very important that the
assertion of M R be glitch free. A nar row glitch of only a few
nanoseconds while MR is LOW can be interpreted as a false
edge and interrupt the reset timing sequence . As a res ult , th e
FIFO will not be fully reset or programmed.
To insure that Master Reset is glitch free, it is recommended
that MR be driven by a flip-flop. In applications requiring a
single Master Reset signal to reset or program multiple
FIFOs, the FIFO pin fart hest way from the flip-f lop may need
to be terminated in order to reduc e glitches caused by voltag e
reflections. The need for terminations is a function of trace
length, rise time, a nd PCB characteristi cs (see “System De-
sign Consid erations When Using Cypress CMOS Circuits,” in
the
Cypress Semiconductor Applications Handbook
).
The probability of improperly resetting a clocked FIFO due to
glitches induced by ground bounce or other sources of noise
can be reduc ed by using a Master Reset pulse that is as sho rt
as possible but is greater than tPMR. Long reset pulses in-
crease the chance that nois e from somewhere in the system
will be coupled to the MR pin through the ground plane.
Fig-
ure 5
sho ws a circuit for creating a short MR pulse from a long
re set pulse. The duration of the MR pulse can be increased
by adding more dela y registers before the AND gate.
The proper reset sequence requires that enabled read and
write cycles not be performed during or near the Master Reset
pulse. Clock cycles that are not enabled by ENR or ENW are
allowed during Master Reset. To insure that the clocks are
disabled, ENR and ENW should not glitch LOW. Exac t t iming
parameters are given in the data sheet. An easy way t o insure
that t iming restr ictions ar e met wi th a state m achine is t o in-
sert p ad states (cl ock enables HIGH) between the last read
and write before Master Reset and between the first read and
write after Master Reset.
Figure 4. 7C44X Flag Architecture
Full
AlmostEmpty
Empty
CKW
CKR
CKR
F1
F2 AlmostEmpty
Empty
Full
+
AlmostFull
DQ
DQ
DQ
7 C44X Internal Fla g Logic Extern al Flag Decode LogicPins
(synchronized to CKW)
(synchronized to CKR)
(synchronized to CKR)
(22v10,PLD,FPGA,etc.)
Synchronization Registers
AlmostFull
CKW DQ
To Write Control Logic
To Read Control Logic
Understanding Clocked FIFOs
6
Programmin g the 7C45X
Th e 7C45X family of clocked FIFOs can be programmed d ur-
ing the Master Reset cycle. Programming affects the Al-
mostEmpty and AlmostFull flags and sets the Parity. Pro-
gramming is accomplished by writing data to the FIFO while
asserting MR LOW. The program word is stored in the pro-
gram register. The programming informat ion may be verified
my reading the FIFO while MR is still asserted LOW. The
FIFO program register is programmed to its default value if
no write is perform e d during a M aster Reset.
Data lines D0−D5 are u sed to program the AlmostEmpty and
AlmostFull flags. The value of D0−D5, which is written into the
program register, determines the distance from the FIFO
boundary flags (Em pty and Full) that these flags become ac-
tive. The distance is programmable in 16-word increments
and is determined by 16•P where P is the value of D0−D5.
The PAFE pin encodes the programmable flag states.
Data lines D6-D8 program the FIFO parity option. D8 enables
the Parity feature when set HIGH. D7 selects between Parity
Generation and Parity Checking. Parity Generation is select-
ed when D7 is LOW. D6 selects even parity when set LOW
and odd parity when set HIGH.
Parity generation provides a simple means for systems to
detect data bit errors. When enabled, the FIFO parity checker
will examine bits D0-D7 being written into the FIFO before
writing th em into the memor y array. The ninth bit ( D8) will be
set accordin g to the par ity mode set in the program re gister.
Even-parity mode will set D8 such that the sum off all the bits
including D8 is even. Odd- par ity mode will set D8 such that
the sum is odd. D8 is available on output line Q8/PG/PE dur-
ing a read from the FIFO. Parity check e rs down stream in the
system can use D8 to determine when data has been corrupt-
ed.
The 7C 45X can be configured as a parity error checker. Dur-
ing a write, data bits D0−D8 are examined before being
store d in the memory arra y. D8 i s set LOW i f a parity error i s
detected. When set for even parity checking, a parity error
occurs if bits D0−D7 add to an odd number . Odd-parity check-
ing will detect an err or if D0−D8 a dd to an even number. D8
is wr itte n into the memory array wi th the rest of bit s D0−D8.
The parity-error bit (D8) is then available on Q8/PG/PE during
a read from the FIFO.
Depth Expansion
The 7C45X Family of Clocked FIFOs feature depth expand-
ability. Two or more 7C45Xs may be cascaded to achieve a
single, large FIFO memory array. Depth expansion may be
used in a pplications requiring buffering of large data packets,
using extremely disparate read and write rates, or having long
read latencies.
Depth expansion i s achieved by cascading s everal FIFOs us-
ing the expansion pins. Data is automatically multiplexed
from the FIFOs onto a single output bus using the FIFO’s
three-state output drivers. The flags must be combined to
form composite flags.
Figure 6
shows two FIFOs cascaded
for depth expansion.
The cascaded devices act as a single FIFO memory array.
Read and write control is passed from one FIFO to another
using the expansion pins. When a single FIFO has had all of
its memory locations writ ten to, it a sserts the E xpansion Out
pin (XO) signaling the ne xt FIFO to begin writing to it s arra y.
Similar l y, when the FIFO has had all of its memory locations
read from, it deasserts the Expansion Out pin to signal the
next FIFO to read data from its array. The FIFOs’ ex pansion
pins form a simple token ring.
Figure 5. MR Pul se Generation
DQ DQ
Reset MR
CLK
Reset
MR
CLK
> tPMR
Understanding Clocked FIFOs
7
The token-passing architecture necessitates the use of com-
posite flags in order to detect when composite FIFO is in a
boundary state (Full or Empty). In a long series of reads and
writes, it is difficult to track which of the individu al FIFOs pos-
sess the read and write tokens. The state of the composite
FIFO could be d etermined by looking a t the flags of the FIFOs
in possession of these tokens, but this is difficult and unnec-
essary. Composite flags, sh own in
Figure 6
, by pass this prob-
lem by looking at all the flags in parallel.
The Fi rst Load pin ( FL) indicates which de vice p osses ses the
read and write tokens following a Master Reset. Only one
device should have its FL pin tied to VSS. All other devices
should tie F L to VCC.
The Almost Empty and Almost Full flags are not usable in
depth expansion. The cascaded devices, however, can be
programmed for parity. All cascaded devices will be pro-
grammed the same since all control a nd data pins are com-
mon. Program read occurs automatically on the First Load
device only to a v oid b us cont ent ion.
Width Expansion
Both th e 7C44X and 7C45X family of Clocked FIFOs can be
width expanded for applications requiring data wi der than 9
bits.
Width expansion is achieved by wiring the FIFOs in parallel.
Figure 7
shows two FIFOs wired for widt h expansion. Com-
posite flags should be used to provide proper rea d and write
signaling near the FIFO Empty and Full boundaries. Process
variations betw een FIFOs can result in differences in tSKEW1
and tSKEW2. This can cause the update cycles to occur on
staggered clock cycles in different FIFOs . Data misalignment
can occur at the boundary condition if an operation is per-
formed before all FIFO flag registers are in the same state.
Composite flag signaling insures that all FIFOs are in the
same state so that an o peration at the bounda ry is performed
concurrently by all FIF Os.
The PAFE flag from either FIFO may be monitored and will
give the correct status, or each FIFO may be programmed
differently to give different PAFE flags. Parity genera-
tion/checking is performed in each device independently ac-
cording to how they are individually pro grammed.
Using a Clocked FIFO Like a
Standard FIFO
Applications that require high-speed unclocked asynchro-
nous FIFOs memory may use clocked FIFOs. Unclocked
asynchronous FIFOs operate at much lower frequenc ies than
clocke d FIFOs but feature read and write interfaces driven by
single read and write strobes.
Figure 6. Depth Expansion with CY 7C45X
CKW
ENW
MR
OE
CKR
ENR
HF
E/F
PAFE/XO
D0−D8 Q0−Q8
XI
FL
7C45X
CKW
ENW
MR
OE
CKR
ENR
HF
E/F
PAFE/XO
XI
FL
7C45X
CKW
ENW
MR
OE
ENR
CKR
EMPTY
FULL
VSS
VCC
D0−D8 Q0−Q8
D0−D8 Q0−Q8
Understanding Clocked FIFOs
8
Applications can use c loc ked FIFOs to emulate this operation
at high speeds by tying the clock to the appropriate enable
line. The enable lines should not be tied straight to ground.
Grounding the enable lines directly increases the probability
of violating enab le set-up times in a noisy env ironment. Ty ing
the enables to the clocks closes the timing window (when
noise can affect the enable pins) and filters out unwanted
ground noise. The zero hold-time feature of the enable makes
this co nfiguratio n possible.
Figure 8
shows a 7C45X config-
ured as a standard FIFO.
A caveat occurs at the boundary condition flag timing. Ab-
sence of a f ree running clock w ill prevent the flags from b eing
updated. As a consequence, the internal FIFO control logic
will inhibit read or write operations if the respective flag is not
updated. To avoid this problem, the FIFO in a boundary state
must be strobed in order to force a flag update cycle. Data is
not destroyed during the update cycle. The desired operation
may proceed once the flag is updated correctly.
For example, an em pty FIFO w ith its empty flag asserted is
written to by strobing the write port. The empty flag, however,
is only updated by the rising edge of CKR. Conseque n tly, the
read port must be strobed in order to force the flag to be
updated. While the empty flag is asserted, the attempted
reads are ignored (data remains i n the FIFO) and only serve
to updat e the empty flag. Once the empty fl ag is deasserted,
the data can be read from the FIFO in the normal manner.
It also possible to build a controller that forces an update cycle
at the FIFO boundary without checking the state of the flags.
When a read or a write strobe occu rs a f fec ting the state of the
memory array, the controller forces an update automatically
by toggle the other strobe l ine.
Figure 7. Width Expansion with CY7C45X
CKW
ENW
MR
OE
CKR
ENR
HF
E/F
PAFE/XO
D0−D8 Q0−Q8
XI
FL
7C45X
CKW
ENW
MR
OE
CKR
ENR
HF
E/F
PAFE/XO
XI
FL
7C45X
CKW
ENW
MR
OE
ENR
CKR
EMPTY
FULL
VSS
D9−D17 Q9−Q17
VSS
VCC
VCC
D0−D8
D0−D8
Q0−Q8
Q0−Q8
PAFE1
PAFE0
Understanding Clocked FIFOs
© Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufactur er assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Conclusion
Cypress 7C44X and 7C45X Clo cked FIFOs solve a wide va-
riety of data buffering and storage needs for telecommunica-
tions, interprocessor, and data gathering applications. The
clocked FIFO architecture offers 70-MHz performance and
avoids the timing a nd noise problems inherent in unclocked
asynchronous FIFOs.
Figure 8. Using a Clocked FIFO Like a Standard FIFFO
CKW
ENW
CKR
ENR
MR HF
E/F
D0-D8 Q0-Q8
MR
W R
7C45X
F
E
READ STROBEWRITE STROBE
FULL FLAG
EMPTY FLAG
D0-D8 Q0-Q8
