10 MHz, 14.5 nV/√Hz, Rail-to-Rail I/O,
Zero Input Crossover Distortion Amplifier
Data Sheet
ADA4500-2
Rev. A Document Feedback
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FEATURES
Power supply rejection ratio (PSRR): 98 dB minimum
Common-mode rejection ratio (CMRR): 95 dB minimum
Offset voltage: 120 µV maximum
Single-supply operation: 2.7 V to 5.5 V
Dual-supply operation: ±1.35 V to ±2.75 V
Wide bandwidth: 10 MHz
Rail-to-rail input and output
Low noise
2 µV p-p from 0.1 Hz to 10 Hz
14.5 nV/√Hz at 1 kHz
Very low input bias current: 2 pA maximum
APPLICATIONS
Pressure and position sensors
Remote security
Medical monitors
Process controls
Hazard detectors
Photodiode applications
PIN CONFIGURATION
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4500-2
TOP VIEW
(Not t o Scale)
10617-001
Figure 1. 8-Lead MSOP Pin Configuration
For more information on the pin connections, see the Pin
Configurations and Function Descriptions section
100
–100
–80
–60
–40
–20
0
20
40
60
80
0 54321
V
OS
(µV)
V
CM
(V)
ADA4500-2
V
SY
= 5.0V
10617-004
Figure 2. The ADA4500-2 Eliminates Crossover Distortion
Across its Full Supply Range
GENERAL DESCRIPTION
The ADA4500-2 is a dual 10 MHz, 14.5 nV/√Hz, low power
amplifier featuring rail-to-rail input and output swings while
operating from a 2.7 V to 5.5 V single power supply. Compatible
with industry-standard nominal voltages of +3.0 V, +3.3 V,
+5.0 V, and ±2.5 V.
Employing a novel zero-crossover distortion circuit topology, this
amplifier offers high linearity over the full, rail-to-rail input
common-mode range, with excellent power supply rejection ratio
(PSRR) and common-mode rejection ratio (CMRR) performance
without the crossover distortion seen with the traditional
complementary rail-to-rail input stage. The resulting op amp
also has excellent precision, wide bandwidth, and very low
bias current.
This combination of features makes the ADA4500-2 an ideal choice
for precision sensor applications because it minimizes errors due to
power supply variation and maintains high CMRR over the full
input voltage range. The ADA4500-2 is also an excellent amplifier
for driving analog-to-digital converters (ADCs) because the output
does not distort with the common-mode voltage, which enables
the ADC to use its full input voltage range, maximizing the
dynamic range of the conversion subsystem.
Many applications such as sensors, handheld instrumentation,
precision signal conditioning, and patient monitors can benefit
from the features of the ADA4500-2.
The ADA4500-2 is specified for the extended industrial temperature
range (−40°C to +125°C) and available in the standard 8-lead
MSOP and 8-lead LFCSP packages.
ADA4500-2 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
VSY = 2.7 V Electrical Characteristics ........................................ 3
VSY = 5.0 V Electrical Characteristics ........................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Rail-to-Rail Output .................................................................... 19
Rail-to-Rail Input (RRI) ............................................................ 19
Zero Cross-Over Distortion ..................................................... 19
Overload Recovery ..................................................................... 20
Power-On Current Profile ......................................................... 21
Applications Information .............................................................. 22
Resistance and Capacitance Sensor Circuit ............................ 22
Adaptive Single-Ended-to-Differential Signal Converter..... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
10/12–Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 24
10/12–Revision 0: Initial Version
Data Sheet ADA4500-2
Rev. A | Page 3 of 24
SPECIFICATIONS
VSY = 2.7 V ELECTRICAL CHARACTERISTICS
VSY = 2.7 V, V CM = VSY/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
Symbol
Test Conditions/Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
120 µV
−40°C < T
A
< +125°C 700 µV
Offset Voltage Drift TCV
OS
−40°C < T
A
< +125°C 0.8 5.5 µV/°C
Input Bias Current I
B
0.3 1 pA
−40°C < T
A
< +125°C 170 pA
Input Offset Current I
OS
0.3 1 pA
−40°C < T
A
< +125°C 20 pA
Input Voltage Range
IVR
−40°C < TA < +125°C
V−
V+
V
Common-Mode Rejection Ratio CMRR V
CM
= V− to V+ 95 110 dB
−40°C < T
A
< +125°C 90 dB
V
CM
= [(V−) − 0.2 V] to [(V+) + 0.2 V] 90 110 dB
−40°C < T
A
< +125°C 80 dB
Large Signal Voltage Gain
AVO
RL = 2 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
100
110
dB
−40°C < T
A
< +125°C 100 dB
R
L
= 10 kΩ, [(V−) + 0.05 V] < V
OUT
< [(V+) − 0.05 V] 105 120 dB
−40°C < T
A
< +125°C 105 dB
Input Capacitance
Common Mode C
INCM
5 pF
Differential C
INDM
1.7 pF
Input Resistance R
IN
Common mode and differential mode 400 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
R
L
= 10 kΩ to V− 2.685 2.695 V
−40°C < T
A
< +125°C 2.68 V
R
L
= 2 kΩ to V− 2.65 2.68 V
−40°C < T
A
< +125°C 2.65 V
Output Voltage Low
VOL
RL = 10 kΩ to V+
3
5
mV
−40°C < TA < +125°C
10
mV
R
L
= 2 kΩ to V+ 13 20 mV
−40°C < T
A
< +125°C 25 mV
Short Circuit Limit I
SC
Sourcing, V
OUT
shorted to V− 26 mA
Sinking, V
OUT
shorted to V+ −48 mA
Closed-Loop Impedance Z
OUT
f = 10 MHz, A
V
= 1 70 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
SY
= 2.7 V to 5.5 V 98 119 dB
−40°C to +125°C 94 dB
Supply Current per Amplifier I
SY
I
O
= 0 mA 1.5 1.65 mA
−40°C < T
A
< +125°C 1.7 mA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 kΩ, C
L
= 30 pF, A
V
= +1, V
IN
= V
SY
5.5 V/µs
R
L
= 10 kΩ, C
L
= 30 pF, A
V
= −1, V
IN
= V
SY
8.7 V/µs
Gain Bandwidth Product GBP V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= +100 10.1 MHz
Unity Gain Crossover UGC V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= +1 10.3 MHz
−3 dB Bandwidth −3 dB V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= −1 18.4 MHz
Phase Margin ΦM V
IN
= 5 mV p-p, R
L
= 10 kΩ, C
L
= 20 pF, A
V
= +1 52 Degrees
Settling Time to 0.1% t
s
V
IN
= 2 V p-p, R
L
= 10 kΩ, C
L
= 10 pF, A
V
= −1 1 µs
ADA4500-2 Data Sheet
Rev. A | Page 4 of 24
Parameter Symbol Test Conditions/Conditions Min Typ Max Unit
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD+N G = 1, f = 10 Hz to 20 kHz, V
IN
= 0.7 V rms at 1 kHz
Bandwidth = 80 kHz 0.0006 %
Bandwidth = 500 kHz 0.001 %
Peak-to-Peak Noise
en p-p
f = 0.1 Hz to 10 Hz
3
µV p-p
Voltage Noise Density e
n
f = 1 kHz 14.5 nV/√Hz
Current Noise Density i
n
f = 1 kHz <0.5 fA/√Hz
Data Sheet ADA4500-2
Rev. A | Page 5 of 24
VSY = 5.0 V ELECTRICAL CHARACTERISTICS
VSY = 5.0 V, V CM = VSY/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
120 µV
−40°C < T
A
< +125°C 700 µV
Offset Voltage Drift TCV
OS
−40°C < T
A
< +125°C 0.9 5.5 µV/°C
Input Bias Current I
B
0.7 2 pA
−40°C < T
A
< +125°C 190 pA
Input Offset Current I
OS
0.3 3 pA
−40°C < T
A
< +125°C 20 pA
Input Voltage Range IVR −40°C < T
A
< +125°C V− V+ V
Common-Mode Rejection Ratio CMRR V
CM
= V− to V+ 95 115 dB
−40°C < T
A
< +125°C 95 dB
V
CM
= [(V−) − 0.2 V] to [(V+) + 0.2 V] 95 115 dB
−40°C < T
A
< +125°C 84 dB
Large Signal Voltage Gain A
VO
R
L
= 2 kΩ, [(V−) + 0.05 V] < V
OUT
< [(V+) − 0.05 V] 105 110 dB
−40°C < T
A
< +125°C 80 dB
RL = 10 kΩ, [(V−) + 0.05 V] < VOUT < [(V+) − 0.05 V]
110
120
dB
−40°C < T
A
< +125°C 110 dB
Input Capacitance
Common Mode C
INCM
5 pF
Differential C
INDM
1.7 pF
Input Resistance R
IN
Common mode and differential mode 400 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
R
L
= 10 kΩ to V− 4.975 4.99 V
−40°C < T
A
< +125°C 4.97 V
R
L
= 2 kΩ to V− 4.95 4.97 V
−40°C < T
A
< +125°C 4.95 V
Output Voltage Low V
OL
R
L
= 10 kΩ to V+ 7 15 mV
−40°C < T
A
< +125°C 20 mV
R
L
= 2 kΩ to V+ 24 40 mV
−40°C < TA < +125°C
50
mV
Short Circuit Limit I
SC
Sourcing, V
OUT
shorted to V− 75 mA
Sinking, V
OUT
shorted to V+ −75 mA
Closed-Loop Impedance Z
OUT
f = 10 MHz, A
V
= +1 60 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
SY
= 2.7 V to 5.5 V 98 119 dB
−40°C to +125°C 94 dB
Supply Current per Amplifier I
SY
I
O
= 0 mA 1.55 1.75 mA
−40°C < T
A
< +125°C 1.8 mA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 kΩ, C
L
= 30 pF, A
V
= +1, V
IN
= V
SY
5.5 V/µs
R
L
= 10 kΩ, C
L
= 30 pF, A
V
= −1, V
IN
= V
SY
8.7 V/µs
Gain Bandwidth Product GBP V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= +100 10 MHz
Unity Gain Crossover UGC V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= +1 10.5 MHz
−3 dB Bandwidth −3 dB V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= −1 19.2 MHz
Phase Margin ΦM V
IN
= 5 mV p-p, R
L
= 10 kΩ, C
L
= 20 pF, A
V
= +1 57 Degrees
Settling Time to 0.1% t
s
V
IN
= 4 V p-p, R
L
= 10 kΩ, C
L
= 10 pF, A
V
= −1 1 µs
ADA4500-2 Data Sheet
Rev. A | Page 6 of 24
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD+N G = 1, f = 20 Hz to 20 kHz, V
IN
= 1.4 V rms at 1 kHz
Bandwidth = 80 kHz 0.0004 %
Bandwidth = 500 kHz 0.0008 %
Peak-to-Peak Noise
en p-p
f = 0.1 Hz to 10 Hz
2
µV p-p
Voltage Noise Density e
n
f = 1 kHz 14.5 nV/√Hz
Current Noise Density i
n
f = 1 kHz <0.5 fA/√Hz
Data Sheet ADA4500-2
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage (V−) − 0.2 V to (V+) + 0.2 V
Differential Input Voltage
1
(V−) − 0.2 V to (V+) + 0.2 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec)
300°C
1 Differential input voltage is limited to 5.6 V or the supply voltage + 0.6 V,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
8-Lead MSOP (RM-8)1 142 45 °C/W
8-Lead LFCSP (CP-8-12)
2, 3
85
2
°C/W
1 Thermal numbers were simulated on a 4-layer JEDEC printed circuit board (PCB).
2 Thermals numbers were simulated on a 4 layer JEDEC PCB with the exposed
pad soldered to the PCB.
3 θJC was simulated at the exposed pad on the bottom of the package.
ESD CAUTION
ADA4500-2 Data Sheet
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4500-2
TOP VIEW
(Not t o Scale)
10617-400
Figure 3. 8-Lead MSOP Pin Configuration
10617-200
3+IN A
4V–
1OUT A
2–I N A
6–IN B
5+IN B
8 V+
7OUT B
ADA4500-2
TOP VI EW
(No t t o Scal e)
NOTES
1. CONNECT THE E X P OSE D P AD TO V –
OR LEAVE IT UNCONNECTED.
Figure 4. 8-Lead LFCSP Pin Configuration
Table 5. 8-Lead MSOP and 8-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A.
2
−IN A
Inverting Input, Channel A.
3 +IN A Noninverting Input, Channel A.
4 V− Negative Supply Voltage.
5 +IN B Noninverting Input, Channel B.
6 −IN B Inverting Input, Channel B.
7 OUT B Output, Channel B.
8 V+ Positive Supply Voltage.
EPAD For the LFCSP package only, connect the exposed pad to V− or leave it unconnected.
Data Sheet ADA4500-2
Rev. A | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
–120 –100 –80 –60 –40 –20 020 40 60 80 100 120
NUMBER OF UNIT S
VOS (µV)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
10617-002
Figure 5. Input Offset Voltage Distribution, VSY = 2.7 V
35
30
25
20
15
10
5
008.757.506.255.003.752.501.25
NUMBER OF UNIT S
TCV
OS
(µV/°C)
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
–40°C ≤ T
A
≤ +125°C
10617-006
Figure 6. Input Offset Voltage Drift Distribution, VSY = 2.7 V
100
–100
–80
–60
–40
–20
0
20
40
60
80
–0.2 2.82.31.81.30.80.3
VOS (µV)
VCM (V)
ADA4500-2
VSY = 2.7V
10617-007
Figure 7. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 2.7 V
100
90
80
70
60
50
40
30
20
10
0
–120 –100 –80 –60 –40 –20 020 40 60 80 100 120
NUMBER OF UNIT S
VOS (µV)
ADA4500-2
VSY = 5.0V
VCM = VSY/2
10617-005
Figure 8. Input Offset Voltage Distribution, VSY = 5.0 V
35
30
25
20
15
10
5
008.757.506.255.003.752.501.25
NUMBER OF UNIT S
TCV
OS
(µV/°C)
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
–40°C ≤ T
A
≤ +125°C
10617-003
Figure 9. Input Offset Voltage Drift Distribution, VSY = 5.0 V
–0.2 2.8 4.83.81.80.8
100
–100
–80
–60
–40
–20
0
20
40
60
80
V
OS
(µV)
V
CM
(V)
ADA4500-2
V
SY
= 5.0V
10617-004
Figure 10. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5.0 V
ADA4500-2 Data Sheet
Rev. A | Page 10 of 24
TA = 25°C, unless otherwise noted.
100
–40
–20
0
20
40
60
80
–50 –25 025 50 75 100 125 150
IB (p A)
TEMPERATURE (°C)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
IB+
IB–
10617-008
Figure 11. Input Bias Current (IB) vs. Temperature, VSY = 2.7 V
03.02.52.01.51.00.5
I
B
(p A)
V
CM
(V)
ADA4500-2
V
SY
= 2.7V
10617-012
100
–40
–20
0
20
40
60
80
Figure 12. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 2.7 V
10k
1k
100
10
1
0.1
0.001 100
1010.10.01
OUTPUT (VOH) TO SUPPLY (mV)
LOAD CURRENT ( mA)
ADA4500-2
VSY = 2.7V
SO URCING OUT P UT CURRENT
10617-010
–40°C +25°C
+125°C
Figure 13. Output Voltage (VOH) to Supply Rail vs. Load Current, VSY = 2.7 V
100
–40
–20
0
20
40
60
80
–50 –25 025 50 75 100 125 150
IB (p A)
TEMPERATURE (°C)
ADA4500-2
VSY = 5.0V
VCM = VSY/2
IB+
IB–
10617-011
Figure 14. Input Bias Current (IB) vs. Temperature, VSY = 5.0 V
100
–40
–20
0
20
40
60
80
0 5432
1
IB (p A)
VCM (V)
ADA4500-2
VSY = 5.0V
10617-009
Figure 15. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 5.0 V
10k
1k
100
10
1
0.1
0.001 1001010.10.01
OUTPUT (VOH) TO SUPPLY (mV)
LOAD CURRENT ( mA)
ADA4500-2
VSY = 5.0V
SO URCING OUT P UT CURRENT
10617-013
–40°C
+25°C
+125°C
Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current, VSY = 5.0 V
Data Sheet ADA4500-2
Rev. A | Page 11 of 24
TA = 25°C, unless otherwise noted.
10k
1k
100
10
1
0.1
0.001 10010
10.1
0.01
OUTPUT (VOL) TO SUPPLY (mV)
LOAD CURRENT ( mA)
ADA4500-2
VSY = 2.7V
SI NKING OUT P UT CURRENT
10617-014
–40°C
+25°C
+125°C
Figure 17. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 2.7 V
50
40
30
20
10
0
–50 –25 025 50 75 100 125 150
OUTPUT (VOH) TO SUPPLY (mV)
TEMPERATURE (°C)
ADA4500-2
VSY = 2.7V
RL = 2kΩ
RL = 10kΩ
10617-015
Figure 18. Output Voltage (VOH) to Supply Rail vs. Temperature, VSY = 2.7 V
20
15
10
5
0
–50 –25 025 50 75 100 125 150
OUTPUT (VOL) TO SUPPLY (mV)
TEMPERATURE (°C)
ADA4500-2
VSY = 2.7V
RL = 2kΩ
RL = 10kΩ
10617-016
Figure 19. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 2.7 V
10k
1k
100
10
1
0.1
0.001 100
10
10.1
0.01
OUTPUT (VOL) TO SUPPLY (mV)
LOAD CURRENT ( mA)
ADA4500-2
VSY = 5.0V
SI NKING OUT P UT CURRENT
10617-017
–40°C
+25°C
+125°C
Figure 20. Output Voltage (VOL) to Supply Rail vs. Load Current, VSY = 5.0 V
50
40
30
20
10
0
–50 –25 025 50 75 100 125 150
OUTPUT (VOH) TO SUPPLY (mV)
TEMPERATURE (°C)
ADA4500-2
VSY = 5.0V
RL = 2kΩ
RL = 10kΩ
10617-018
Figure 21. Output Voltage (VOH) to Supply Rail vs. Temperature, VSY = 5.0 V
50
40
30
20
10
0
–50 –25 025 50 75 100 125 150
OUTPUT (VOL) TO SUPPLY (mV)
TEMPERATURE (°C)
ADA4500-2
VSY = 5.0V
RL = 2kΩ
RL = 10kΩ
10617-019
Figure 22. Output Voltage (VOL) to Supply Rail vs. Temperature, VSY = 5.0 V
ADA4500-2 Data Sheet
Rev. A | Page 12 of 24
TA = 25°C, unless otherwise noted.
1.75
1.50
1.25
1.00
0.75
0.50
0.25
005.55.04.54.03.53.02.52.01.51.00.5
SUPP LY CURRENT PE R AM P ( mA)
SUPPLY VOLT AGE (V)
+25°C
+85°C
–40°C
ADA4500-2
+125°C
10617-020
Figure 23. Supply Current per Amp vs. Supply Voltage
GAIN (d B)
PHASE ( Degrees)
FRE QUENCY ( Hz )
RL = 10kΩ
CL = 20pF
VSY = 2.7V
VCM = VSY/2
ADA4500-2
150
100
50
0
–50
–100
150
100
50
0
–50
–100
100 1k 10k 100k 1M 10M 100M
PHASE
GAIN
10617-021
Figure 24. Open-Loop Gain and Phase vs. Frequency, VSY = 2.7 V
60
40
20
0
–20
50
30
10
–10
10 100 1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FRE QUENCY ( Hz )
ADA4500-2
VSY = 2.7V
VCM = VSY/2
AV = +100
AV = +10
AV = +1
10617-022
Figure 25. Closed Loop Gain vs. Frequency, VSY = 2.7 V
2.0
1.8
1.6
1.4
1.2
1.0
–50 –25 025 50 75 100 150125
SUPP LY CURRENT PE R AM P ( mA)
TEMPERATURE (°C)
VSY = ± 2.5V
VSY = ± 1.35V
10617-023
ADA4500-2
Figure 26. Supply Current per Amp vs. Temperature
GAIN (d B)
PHASE ( Degrees)
FRE QUENCY ( Hz )
RL = 10kΩ
CL = 20pF
VSY = 5.0V
VCM = VSY/2
PHASE
GAIN
10617-024
ADA4500-2
150
100
50
0
–50
–100
150
100
50
0
–50
–100
100 1k 10k 100k 1M 10M 100M
Figure 27. Open-Loop Gain and Phase vs. Frequency, VSY = 5.0 V
60
40
20
0
–20
50
30
10
–10
10 100 1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FRE QUENCY ( Hz )
ADA4500-2
VSY = 5.0V
VCM = VSY/2
AV = +100
AV = +10
AV = +1
10617-025
Figure 28. Closed-Loop Gain vs. Frequency, VSY = 5.0 V
Data Sheet ADA4500-2
Rev. A | Page 13 of 24
TA = 25°C, unless otherwise noted.
CMRR (dB)
FRE QUENCY ( Hz )
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
160
140
120
100
80
60
40
20
0
100 1k 10k 100k 1M 10M 100M
10617-100
Figure 29. CMRR vs. Frequency, VSY = 2.7 V
PSRR ( dB)
FRE QUENCY ( Hz )
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
140
120
100
80
60
40
20
–20
0
100 1k 10k 100k 1M 10M 100M
PSRR+
PSRR–
10617-026
Figure 30. PSRR vs. Frequency, VSY = 2.7 V
1k
100
10
1
0.1
0.001
0.01
100 100M10M1M100k10k1k
ZOUT (Ω)
FRE QUENCY ( Hz )
ADA4500-2
VSY = 2.7V
VCM = VSY/2
10617-027
AV = +100
AV = +10 AV = +1
Figure 31. Closed Loop Output Impedance (ZOUT) vs. Frequency, VSY = 2.7 V
CMRR (dB)
FRE QUENCY ( Hz )
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
140
120
100
80
60
40
20
0
100 1k 10k 100k 1M 10M 100M
10617-101
Figure 32. CMRR vs. Frequency, VSY = 5.0 V
PSRR ( dB)
FRE QUENCY ( Hz )
140
120
100
80
60
40
20
–20
0
100 1k 10k 100k 1M 10M 100M
PSRR+
PSRR–
10617-029
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
Figure 33. PSRR vs. Frequency, VSY = 5.0 V
1k
100
10
1
0.1
0.001
0.01
100 100M10M1M100k10k1k
ZOUT (Ω)
FRE QUENCY ( Hz )
ADA4500-2
VSY = 5.0V
VCM = VSY/2
10617-030
AV = +100
AV = +10
AV = +1
Figure 34. Closed Loop Output Impedance (ZOUT) vs. Frequency, VSY = 5.0 V
ADA4500-2 Data Sheet
Rev. A | Page 14 of 24
TA = 25°C, unless otherwise noted.
VOLTAGE (0.5V/DIV)
TIME ( 400ns/ DIV)
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
V
IN
= 2V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
10617-028
Figure 35. Large Signal Transient Response, VSY = 2.7 V
VOLTAGE (50mV/DIV)
TIME ( 200ns/ DIV)
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
10617-032
Figure 36. Small Signal Transient Response, VSY = 2.7 V
OVERSHOOT (%)
LOAD CAPACI TANCE ( pF )
80
70
60
50
40
30
20
0
10
110 100
OS+
OS–
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
10617-033
Figure 37. Small Signal Overshoot vs. Load Capacitance, VSY = 2.7 V
VOLTAGE (1V/DIV)
TIME ( 200ns/ DIV)
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
V
IN
= 4V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
10617-031
Figure 38. Large Signal Transient Response, VSY = 5.0 V
VOLTAGE (50mV/DIV)
TIME ( 200ns/ DIV)
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
10617-035
Figure 39. Small Signal Transient Response, VSY = 5.0 V
OVERSHOOT (%)
LOAD CAPACI TANCE ( pF )
80
70
60
50
40
30
20
0
10
110 100
OS+
OS–
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
10617-036
Figure 40. Small Signal Overshoot vs. Load Capacitance, VSY = 5.0 V
Data Sheet ADA4500-2
Rev. A | Page 15 of 24
TA = 25°C, unless otherwise noted.
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
ADA4500-2
V
SY
= ±1. 35V
V
IN
= 50mV p - p
A
V
= –100
R
L
= 10kΩ
C
L
= 100pF
0.05
0
–0.05
–0.10
1.5
1.0
0.5
0
–0.5
INPUT
OUTPUT
10617-034
Figure 41. Positive Overload Recovery, VSY = ±1.35 V
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
ADA4500-2
VSY = ± 1.35V
VIN = 50mV p-p
AV = –100
RL = 10kΩ
CL = 100pF
0.10
0.05
0
–0.05
0.5
0
–0.5
–1.0
–1.5
INPUT
OUTPUT
10617-038
Figure 42. Negative Overload Recovery, VSY = ±1.35 V
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
ADA4500-2
V
SY
= ±2. 5V
V
IN
= 100mV p - p
A
V
= –100
R
L
= 10kΩ
C
L
= 100pF
0.1
0
–0.1
–0.2
3
2
1
0
–1
INPUT
OUTPUT
10617-037
Figure 43. Positive Overload Recovery, VSY = ±2.5 V
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
ADA4500-2
V
SY
= ±2. 5V
V
IN
= 100mV p - p
A
V
= –100
R
L
= 10kΩ
C
L
= 100pF
0.2
0.1
0
–0.1
1
0
–1
–2
–3
INPUT
OUTPUT
10617-041
Figure 44. Negative Overload Recovery, VSY = ±2.5 V
ADA4500-2 Data Sheet
Rev. A | Page 16 of 24
TA = 25°C, unless otherwise noted.
INPUT VOLTAGE (1V/DIV)
TIME ( 400ns/ DIV)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT A V = –1
ERRO R BAND
POST GAIN = 20
INPUT
OUTPUT
–20mV
0
+20mV
10617-039
Figure 45. Positive Settling Time to 0.1%, VSY = 2.7 V
INPUT VOLTAGE (1V/DIV)
TIME ( 400ns/ DIV)
ADA4500-2
VSY = 2.7V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT A V = –1
ERRO R BAND
POST GAIN = 20
INPUT
OUTPUT
–20mV
0
+20mV
10617-040
Figure 46. Negative Settling Time to 0.1%, VSY = 2.7 V
INPUT VOLTAGE (2V/DIV)
TIME ( 400ns/ DIV)
ADA4500-2
VSY = 5.0V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
DUT A V = –1
ERRO R BAND
POST GAIN = 20
INPUT
OUTPUT
–40mV
0
+40mV
10617-042
Figure 47. Positive Settling Time to 0.1%, VSY = 5.0 V
INPUT VOLTAGE (2V/DIV)
TIME ( 400ns/ DIV)
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
R
L
= 10kΩ
C
L
= 10pF
DUT A
V
= –1
ERRO R BAND
POST GAIN = 20
INPUT
OUTPUT
–40mV
0
+40mV
10617-043
Figure 48. Negative Settling Time to 0.1%, VSY = 5.0 V
Data Sheet ADA4500-2
Rev. A | Page 17 of 24
TA = 25°C, unless otherwise noted.
VOLT AGE NOI SE DENSITY (n V/ Hz)
FRE QUENCY ( Hz )
1k
100
10
110 100 1k 10k 10M
1M100k
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
10617-044
Figure 49. Voltage Noise Density vs. Frequency, VSY = 2.7 V
(10 Hz to 10 MHz)
VOLT AGE NOI SE DENSITY (n V/ Hz)
FRE QUENCY ( Hz )
1k
100
10
110 100 1k 10k 100M10M1M100k
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
10617-300
Figure 50. Voltage Noise Density vs. Frequency, VSY = 2.7 V
(10 Hz to 100 MHz)
INP UT REF E RRE D V OL TAG E ( 500nV/DIV )
TIME (1s/DIV)
ADA4500-2
VSY = 2.7V, AV = +100
VCM = VSY/2
10617-045
Figure 51. 0.1 to 10 Hz Noise, VSY = 2.7 V
VOLT AGE NOI SE DENSITY (n V/ Hz)
FRE QUENCY ( Hz )
1k
100
10
1
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
10617-047
10 100 1k 10k 10M
1M
100k
Figure 52. Voltage Noise Density vs. Frequency, VSY = 5.0 V
(10 Hz to 10 MHz)
10 100 1k 10k 100M
10M1M
100k
VOLT AGE NOI SE DENSITY (n V/ Hz)
FRE QUENCY ( Hz )
1k
100
10
1
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
10617-301
Figure 53. Voltage Noise Density vs. Frequency, VSY = 5.0 V
(10 Hz to 100 MHz)
INP UT REF E RRE D V OL TAG E ( 500nV/DIV )
TIME (1s/DIV)
ADA4500-2
VSY = 5.0V
AV = +100
VCM = VSY/2
10617-048
Figure 54. 0.1 to 10 Hz Noise, VSY = 5.0 V
ADA4500-2 Data Sheet
Rev. A | Page 18 of 24
TA = 25°C, unless otherwise noted.
THD + NOI S E ( %)
V
IN
(V rms)
100
10
1
0.1
0.01
0.001
0.0001
0.001 100101
0.10.01
ADA4500-2
V
SY
= 2.7V
V
CM
= V
SY
/2
A
V
= +1
80kHz LOW-PASS FI L T ER
R
L
= 10kΩ
10617-046
Figure 55. THD + Noise vs. Amplitude, VSY = 2.7 V
THD + NOI S E ( %)
FRE QUENCY ( Hz )
1
0.0001
0.001
0.01
0.1
10 100k10k
1k
100
ADA4500-2
VSY = 2.7V
AV = +1
80kHz LOW-PASS FI L T ER
R
L
= 10kΩ
V
IN
= 0.7V rms
10617-050
Figure 56. THD + Noise vs. Frequency, VSY = 2.7 V
THD + NOI S E ( %)
V
IN
(V rms)
100
10
1
0.1
0.01
0.001
0.0001
0.001 100
101
0.10.01
ADA4500-2
V
SY
= 5.0V
V
CM
= V
SY
/2
A
V
= +1
80kHz LOW-PASS FI L T ER
R
L
= 10kΩ
10617-049
Figure 57. THD + Noise vs. Amplitude, VSY = 5.0 V
THD + NOI S E ( %)
FRE QUENCY ( Hz )
1
0.0001
0.001
0.01
0.1
10 100k10k1k100
ADA4500-2
VSY = 5.0V
AV = +1
80kHz LOW-PASS FI L T ER
R
L
= 10kΩ
V
IN
= 1.4V rms
10617-051
Figure 58. THD + Noise vs. Frequency, VSY = 5.0 V
Data Sheet ADA4500-2
Rev. A | Page 19 of 24
THEORY OF OPERATION
RAIL-TO-RAIL OUTPUT
When processing a signal through an op amp to a load, it is often
desirable to have the output of the op amp swing as close to the
voltage supply rails as possible. For example, when an op amp is
driving an ADC and both the op amp and ADC are using the
same supply rail voltages, the op amp must drive as close to the
V+ and V− rails as possible so that all codes in the ADC are
usable. A non-rail-to-rail output can require as much as 1.5 V
or more between the output and the rails, thus limiting the
input dynamic range to the ADC, resulting in less precision
(number of codes) in the converted signal.
The ADA4500-2 can drive its output to within a few millivolts
of the supply rails (see the output voltage high and output voltage
low specifications in Table 1 and Table 2). The rail-to-rail output
maximizes the dynamic range of the output, increasing the range
and precision, and often saving the cost, board space, and added
error of the additional gain stages.
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonrail-to-rail input stage (that is, a single
differential pair) limits the input voltage to approximately one gate-
source voltage (VGS) away from one of the supply lines. Because
VGS for normal operation is commonly more than 1 V, a single
differential pair, input stage op amp greatly restricts the allowable
input voltage. This can be quite limiting with low supply voltages
supplies. To solve this problem, RRI stages are designed to allow
the input signal to range to the supply voltages (see the input
voltage range specifications in Table 1 and Table 2). In the case
of the ADA4500-2, the inputs continue to operate 200 mV beyond
the supply rails (see Figure 7 and Figure 10).
ZERO CROSS-OVER DISTORTION
A typical rail-to-rail input stage uses two differential pairs (see
Figure 59). One differential pair amplifies the input signal when
the common-mode voltage is on the high end, and the other
pair amplifies the input signal when the common-mode voltage
is on the low end. This classic dual-differential pair topology
does have a potential drawback. If the signal level moves through
the range where one input stage turns off and the other input
stage turns on, noticeable distortion occurs. Figure 60 shows the
distortion in a typical plot of VOS (voltage difference between the
inverting and the noninverting input) vs. VCM (input voltage).
10617-103
VDD
M10
M9
M12
M11
M8
M7
M6
M5
VSS
BIAS5
BIAS4
BIAS3
–A
V
OUT
VSS
BIAS2
M3 M4
VDD
BIAS1
M1 M2
V
IN
+V
IN
–
Figure 59. Typical PMOS-NMOS Rail-to-Rail Input Structure
10617-060
V
CM
(V)
V
OS
(µV)
0
–300
–100
100
300
1.5 3.5 5.0
1.00.5 2.5 4.54.03.02.0
–200
–150
–250
–50
0
50
150
200
250 V
SY
= 5V
T
A
= 25° C
Figure 60. Typical Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM)
Response in a Dual Differential Pair Input Stage Op Amp (Powered by a 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
This distortion in the offset error forces the designer to live with
the bump in the common-mode error or devise impractical ways
to avoid the crossover distortion areas, thereby narrowing the
common-mode dynamic range of the op amp.
ADA4500-2 Data Sheet
Rev. A | Page 20 of 24
The ADA4500-2 solves the crossover distortion problem by using
an on-chip charge pump in its input structure to power the input
differential pair (see Figure 61). The charge pump creates a
supply voltage higher than the voltage of the supply, allowing
the input stage to handle a wide range of input signal voltages
without using a second differential pair. With this solution, the
input voltage can vary from one supply voltage to the other with
no distortion, thereby restoring the full common-mode dynamic
range of the op amp.
VCP
VDD
VSS
VDD
VSS
BIAS6
BIAS5
BIAS4
BIAS3
M1 M2
V
IN
+ V
IN
–
–A
V
OUT
10617-102
CHARGE
PUMP
Figure 61. ADA4500-2 Input Structure
Some charge pumps are designed to run in an open-loop
configuration. Disadvantages of this design include: a large ripple
voltage on the output, no output regulation, slow start-up, and a
large power-supply current ripple. The charge pump in this op
amp uses a feedback network that includes a controllable clock
driver and a differential amplifier. This topology results in a low
ripple voltage; a regulated output that is robust to line, load, and
process variations; a fast power-on startup; and lower ripple on
the power supply current.1 The charge pump ripple does not
show up on an oscilloscope; however, it can be seen at a high
frequency on a spectrum analyzer. The charge pump clock speed
adjusts between 3.5 MHz (when the supply voltage is 2.7 V) to
5 MHz (at VSY = 5 V). The noise and distortion are limited only by
the input signal and the thermal or flicker noise.
Figure 62 shows the elimination of the crossover distortion in
the ADA4500-2. This solution improves the CMRR performance
tremendously. For example, if the input varies from rail to rail
on a 5 V supply rail, using a part with a CMRR of 70 dB minimum,
an input-referred error of 1581 µV is introduced. The ADA4500-2,
with its high CMRR of 90 dB minimum (over its full operating
temperature) reduces distortion to a maximum error of 158 µV
with a 5 V supply. The ADA4500-2 eliminates crossover distortion
without unnecessary circuitry complexity and increased cost.
300
–300
–240
–180
–120
–60
0
60
120
180
240
0 54321
V
OS
(µV)
V
CM
(V)
ADA4500-2
V
SY
= 5.0V
10617-108
Figure 62. Charge Pump Design Eliminates Crossover Distortion
OVERLOAD RECOVERY
When the output is driven to one of the supply rails, the
ADA4500-2 is in an overload condition. The ADA4500-2 recovers
quickly from the overload condition. Typical op amp recovery
times can be in the tens of microseconds. The ADA4500-2 typically
recovers from an overload condition in 1 µs from the time the
overload condition is removed until the output is active again.
This is important in, for example, a feedback control system. The
fast overload recovery of the ADA4500-2 greatly reduces loop
delay and increases the response time of the control loop (see
Figure 41 to Figure 44).
1 Oto, D.H.; Dham, V.K.; Gudger, K.H.; Reitsma, M.J.; Gongwer, G.S.; Hu, Y.W.; Olund, J.F.; Jones, H.S.; Nieh, S.T.K.; "High-Voltage Regulation and Process
Considerations for High-Density 5 V-Only E2PROM's," IEEE Journal of Solid-State Circuits, Vol. SC-18, No.5, pp.532-538, October 1983.
Data Sheet ADA4500-2
Rev. A | Page 21 of 24
POWER-ON CURRENT PROFILE
The ADA4500-2 powers up with a smooth current profile, with
no supply current overshoot (see Figure 63). When powering up
a system, spikes in the power-up current are undesirable (see
Figure 64). The overshoot requires a designer to source a large
enough power supply (such as a voltage regulator) to supply the
peak current, even though a heavier supply is not necessary once
the system is powered up. If multiple amplifiers are pulling a
spike in current, the system can go into a current limit state and
not power up. This is all avoided with the smooth power up of
the ADA4500-2.
10617-107
5
0
1
2
3
4
0246810 12 14 16 18 20 22 24 26 28 30
SUPPLY VOLT AGE (V)
SUPP LY CURRE NT (mA)
TIME (µs)
60
0
5
10
15
20
25
30
35
40
45
50
55
Figure 63. ISY and VSY vs. Time for ADA4500-2 with No Spike
10617-106
5
0
60
0
5
10
15
20
25
30
35
40
45
50
55
1
2
3
4
0246 8 10 12 14 16 18 20 22 24 26 28 30
SUPPLY VOLT AGE (V)
SUPP LY CURRE NT (mA)
TIME (µs)
Figure 64. ISY and VSY vs. Time with a Power-Up Spike
For systems that are frequently switching off and on, the power-
up overshoot results in excess power use. As the amplifier switches
off and on, the power consumed by the large spike is repeated
on each power-up, increasing the total power consumption by
magnitudes. As an example, if a battery-powered sensor system
periodically powers up the sensor and signal path, takes a reading,
and shuts down until the next reading, the ADA4500-2 enables
much longer battery life because there is no excess charge being
consumed at each power-up.
ADA4500-2 Data Sheet
Rev. A | Page 22 of 24
APPLICATIONS INFORMATION
RESISTANCE AND CAPACITANCE SENSOR CIRCUIT
The application shown in Figure 65 generates a square-wave
output in which the period is proportional to the value of RX
and CX by Equation 1. By fixing the CX and measuring the
period of the output signal, RX can be determined. Fixing RX
allows for the measurement of CX.
Period = 4.80 × RX × CX (1)
U1A takes advantage of the high input impedance and large rail-
to-rail input dynamic range of the ADA4500-2 to measure a
wide range of resistances (RX).
U1B is used as a comparator; with the noninverting input
swinging between (1/12) × VPOS and (11/12) × VPOS, and the
output swinging from rail to rail. Because the accuracy of the
circuit depends on the propagation time through the amplifers,
the fast recovery of U1B from the output overload conditions
makes it ideal for this application.
10617-104
V
POS
U1A
ADA4500-2
V
POS
U1B
ADA4500-2 OUTPUT
R1
10kΩ
V
POS
R3
100kΩ
R2
100kΩ
Rx
Cx
Figure 65. A Resistance/Capacitance Sensor
ADAPTIVE SINGLE-ENDED-TO-DIFFERENTIAL
SIGNAL CONVERTER
The Challenge
When designing a signal path in systems that have a single voltage
supply, the biggest challenge is how to represent the full range of
an input signal that may have positive, zero, and negative values.
By including zero in the output, the output signal must go
completely to ground, which single-supply amplifiers cannot do.
Converting the single-ended input signal to a differential signal
(through a single-ended-to-differential signal converter circuit)
allows zero to be represented as the positive and negative outputs
being equal, requiring neither amplifier to go to ground.
There are other benefits of the single-ended-to-differential signal
conversion, such as doubling the amplitude of the signal for
better signal-to-noise ratio, rejecting common-mode noise, and
driving the input of a high precision differential ADC.
In addition to converting to a differential signal, the circuit must set
the common-mode dc level of its output to a level that gives the ac
signal maximum swing at the load (like the input to an ADC).
Three key challenges are encountered often when designing a
single-ended-to-differential signal converter circuit with a
single supply:
• When the supply is limited to a single voltage, the input
signal level to the circuit is generally limited to operate
from ground to the supply voltage (VSY). This limitation
on the input dynamic range can require attenuation and/or
level-shifting of the source signal before it even gets to the
single-ended-to-differential signal converter. This results in
reduced signal-to-noise ratio (SNR) and additional error.
• The dc part of the input signal, on which the ac signal rides, is
generally not known during system operation. For example, if
multiple input signals from varying sources are multiplexed
into the single-ended-to-differential signal converter circuit,
each one could have a different dc level. Accommodating
multiple dc input levels means that the system design must
compromise the maximum allowed peak voltage of the ac
part of the input so that it does not clip against the rails.
• The system processor does not know what the dc level is of the
original signal so it cannot make adjustments accordingly.
The Solution
These challenges are solved with the adaptive single-ended to
differential converter shown in Figure 66. This circuit operates
off a single supply from 2.7 V to 5.5 V, it automatically adjusts the
dc common mode of the output to a desired level, and it provides
the ability to measure the dc component of the input signal. This
circuit uses two voltage sources: a positive supply rail (VSY) and
a reference voltage (VREF). U1A buffers the input signal, while
U1B integrates that signal and feeds the integrated (dc) voltage
back to U1A to center the output signal on VREF. Resistors R10
and R11 are set to equal the impedance of the resistors R8 and R9
for a matched ac response and for balancing the effects of the
bias current.
The input frequency can range from 10 Hz to 1 MHz. Peak-to-peak
amplitude of the input signal can be as large as VSY − 100 mV.
The dc common mode (VCM) of the input signal can be as high
as +1.5 × VSY and −0.5 × VSY; therefore, a system with a +5 V supply
voltage can take a common mode from as high as +7.5 V and as
low as −2.5 V with a signal amplitude of 5 V p-p. The wide range of
VCM above and below ground, along with a signal amplitude as
large as the supply, eliminates the need to reduce the amplitude
of the input signal and sacrifice SNR. When measuring both the
ac and the dc parts of the signal, a capacitor cannot be in the signal
path. Figure 66 shows examples of the voltage ranges of the single-
ended-to-differential signal converter circuit.
Data Sheet ADA4500-2
Rev. A | Page 23 of 24
Besides converting the ac signal from single-ended to differential,
this circuit separates the ac and dc part of the input signal and
automatically adjusts the common-mode dc level of the output
signal to the same voltage as VREF. The output signal is then a
differential version of the input signal with its common-mode
voltage set to an optimal value (such as, ½ the full-scale input
range to the ADC). The noninverted ac part of the signal is
output at OUTP, and the inverted ac signal is output at OUTN.
The differential output signal (OUTP to OUTN) is centered on
the voltage applied to REF. In this design, R3 and R4 set REF to
½VPOS for maximum signal peak-to-peak swing; however, these
resistors can be eliminated, and the REF input can be driven
from an external source, such as a reference or the output of a
digital-to-analog converter (DAC).
The dc common-mode part of the input signal (VDC) was measured
using the voltage applied at REF and the voltage measured at the
feedback (FB) output using Equation 2. With VCM of the input
signal known to the system, it can respond appropriately to, for
example, a situation when the common mode is getting too close to
the rails.
VDC = (2 × FB) − (REF) (2)
10617-105
VSY
OUTP
VSY
U1A
ADA4500-2
R1B
1kΩ
R1A
1kΩ
C1
100pF
R2
2kΩ
C2
10pF
VSY
U2A
ADA4500-2
R11
5kΩ
INPUT
R6
10kΩ
R5
10kΩ
C5
0.01µF C3
1µF
C7
1µF
C6
1µF
REF
OUTN
FB
R10
5kΩ
VSY
R9
5kΩ
R8
5kΩ
VSY
R4
100kΩ
R3
100kΩ
U2B
U1B
VREF VPP
OUTPUT
VCM VPP
INPUT
VCM_MAX = 1.5 × VSY
VCM_MIN = –0. 5 × VSY
VPP_MAX = VSY – 0.1V
EXAMPLES (VSY = 5V)
+2.5V
0V
+5V
VPP
+7.5V
+5V
+10V
–2.5V
–5V
0V
OR
OUTP
OUTN
OUTP
OUTN
Figure 66. Single-Ended-to-Differential Conversion Circuit Separates the AC and DC Part of the Signal
ADA4500-2 Data Sheet
Rev. A | Page 24 of 24
OUTLINE DIMENSIONS
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PI N 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60 S Q
1.50
0.203 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
3.10
3.00 S Q
2.90
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC S TANDARDS MO-229- WEE D
07-06-2011-A
PI N 1
INDICATOR
(R 0. 15)
Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead
(CP-8-12)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Package Description Package Option Branding
ADA4500-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-12 A2Z
ADA4500-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-12 A2Z
ADA4500-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Z
ADA4500-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Z
ADA4500-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Z
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10617-0-10/12(A)
