AD6652
Rev. 0 | Page 12 of 76
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type Function
POWER SUPPLY
A13, B13, C13, D13, E13, F13, G13, H13, J13, K13, L13, M13, N13, P13, R13,
T13, A14, B14, C14, D14, E14, M14, N14, P14, R14
AVDD Power 3.0 V Analog Supply, 25 Pins.
D4, D5, D6, D7, E4, E5, E6, E7, M8, M9, M10, M11, N8, N9, N10, N11 VDD Power 2.5 V Digital Core Supply, 16 Pins.
D8, D9, D10, D11, D12, E8, E9, E10, E11, E12, F12, G12, H12, J12, K12, L12,
M4, M5, M6, M7, M12, N4, N5, N6, N7, N12, P6
VDDIO Power 3.3 V Digital I/O Supply, 27 Pins.
A1, B5, F2, F4, F5, F6, F7, F8, F9, F10, F11, G4, G5, G6, G7, G8, G9, G10, G11,
H4, H5, H6, H7, H8, H9, H10, H11, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, K4,
K5, K6, K7, K8, K9, K10, K11, L3, L4, L5, L6, L7, L8, L9, L10, L11, P1, T1
DGND Ground Digital Ground, 56 Pins.
A15, A16, B15, B16, C15, D15, E15, E16, F14, F15, F16, G14, H14, H15, J14,
J15, K14, L14, L15, L16, M15, M16, N15, P15, R15, R16, T15, T16
AGND Ground Analog Ground, 28 Pins.
MISCELLANEOUS
E3, P9, P10, P12, R7, R8, R9, R10, R11, T7, T8, T9, T10 NC N/A No Connect, 13 Pins.
B1 DNC N/A Do Not Connect.
Pin No. Mnemonic Type Function
ADC INPUTS
P16 VIN+A Input Differential Analog Input Pin (+) for Channel A.
N16 VIN−A Input Differential Analog Input Pin (−) for Channel A.
C16 VIN+B Input Differential Analog Input Pin (+) for Channel B.
D16 VIN−B Input Differential Analog Input Pin (−) for Channel B.
J16 VREF I/O Voltage Reference Input/Output.
H16 SENSE Input Voltage Reference Mode Select.
T14 ACLK Input ADC Master Clock.
B12 DUTYEN Input Duty Cycle Stabilizer, Active High.
A12, R12 PDWN1Input Power-Down Enable, Active High.
T12 SHRDREF Input Shared Voltage Reference Select, Low = Independent, High = Shared.
ADC OUTPUTS
A11 OTRA Output Out-of-Range Indicator for Channel A, High = Overrange.
P11 OTRB Output Out-of-Range Indicator for Channel B, High = Overrange.
K16 REFTA Output Top Reference Voltage, Channel A.
G16 REFTB Output Top Reference Voltage, Channel B.
K15 REFBA Output Bottom Reference Voltage, Channel A.
G15 REFBB Output Bottom Reference Voltage, Channel B.
DDC INPUTS
A8 RESET Input Master Reset, Active Low.
T11 DCLK Input DDC Master Clock.
T2 PCLK I/O Link Port Clock Output or Parallel Port Clock Input.
D3 PACH1_LACLKIN 2 I/O Channel ID Output Bit, MSB, for Parallel Port A, or Link Port A Data Ready Input.
Function depends on logic state of 0x1B:7 of output port control register.
N2 PBCH1_LBCLKIN2 I/O Channel ID Output Bit, MSB, for Parallel Port B, or Link Port B Data Ready Input.
Function depends on logic state of 0x1D:7 of output port control register.
B10 SYNCA3Input Hardware Sync, Pin A, Routed to All Receiver Channels.
C10 SYNCB3 Input Hardware Sync, Pin B, Routed to All Receiver Channels.
B9 SYNCC3 Input Hardware Sync, Pin C, Routed to All Receiver Channels.
A10 SYNCD3 Input Hardware Sync, Pin D, Routed to All Receiver Channels.
K3, J1, M1,
K1
CHIP_ID[3:0]3 Input Chip ID Selector, Four Pins, Used in Conjunction with Access Control Register
Bits 5–2.