9 052913-1.0 (while in progress)
Revision 1.0 (final document)
Functional Description
VIN
The input supply provides power to the internal
MOSFETs gate drive an d contr ols circu itry for the s witch-
mode r egulator. The operat ing input volta ge rang e is f rom
2.7V to 5.5V. A 2.2µF low-ESR ceramic input capacitor
should be conn ected from VIN to AGND2 as close to the
MIC2871 as pos sib le to ens ure a clean s uppl y voltage for
the device. The minimum voltage rating of 10V is
recom m ended for the input c apac itor.
SW
The MIC2871 has internal low-side and synchronous
MOSFET switches. The switch node (SW) between the
internal MOSFET switches connects directly to one end
of the inductor and provides the current paths during
switching cycles.
The other end of the inductor is connected to the input
supply voltage. Due to the high-speed switching on this
pin, the switch node should be routed away from
sensitive nod es wherever possible.
AGND1
This is the ground path of the LED current sink . It should
be connec ted to the AGND 2, but not via ex posed pad , on
the PCB. The current loop of the analog ground should
be separ ated from that of the power gro und (PGN D1 and
PGND2). AGND1 and AGND2 should be connected to
PGND1 and PGND2 at a single point.
AGND2
This is the gr ound path f or the int erna l biasi ng an d c ont r ol
circuitr y. AG ND2 s hou ld be c onnected to the PCB pad f or
the package exposed pad. AGND2 should be connected
to the AGND1 direc tly without go ing through the expos ed
pad. The current loop of the analog ground should be
separated from that of the power ground (PGND1 and
PGND2). The AGND2 and AGND1 should be connected
to PGND1 and PGND2 at a single point.
PGND1 and PGND2
The power ground pins are the ground path for the high
current in the boost switch and they are internally
connected together. The current loop for the power
ground s hould be as sm all as possib le and s eparat e f rom
the analog ground (AGND) loop as applicable.
OUT
Boost converter output pin which is connected to the
anode of t he LED. A lo w-ESR ceram ic capac itor of 4.7µF
or larger should be connected from OUT to PGND1 as
close as possible to the MIC2871. The minimum voltage
rating of 10V is recommended for the output capacitor.
LED
The current sink pin for the LED. The LED anode is
connected to the OUT pin and the LED cathode is
connecte d to this pin.
DC
The DC is a single multiplexed device enable and serial
data control pin used for functional control and
communication in GPIO-limited applications. When the
DC pin is used as a hardware device enable pin, a logic
high sign al on the DC pin enab les the device , and a lo gic
low signal on the DC pin disables the device. When the
DC pin is used as the single-wire serial interface digital
control pin, a combination of bit edges and the period
between edges is used to communicate a variable length
data word across the single wire. Each word is
transmitted as a series of pulses, each pulse
incrementing an internal data counter. A stop sequence
consisting of an inactive period is used to latch the data
word internally. The data word received is then used to
set the value of the corresponding register for controlling
specific function. The MIC2871 supports five writeable
registers for controlling flash mode, torch mode, safety
timer duration, safety timer threshold current, and low-
battery threshold.
An address/data frame is used to improve protection
against erroneous writes where communications are in
error. W hen DC is in a low state and no data is detec ted
for an extended period of time, the MIC2871 will
automatically go into a low-power SHUTDOWN state,
simultaneously resetting all internal registers to their
default states.
FEN1 and FEN2
FEN1 and FEN2 are hardware enable pins for flash
mode. FEN1 is logic-OR with FEN2. A logic low-to-high
transition on either FEN1 pin or FEN2 pin can initiate the
MIC2871 in f lash mode. If F EN1 or F E N2 is l ef t f loatin g, it
is pulled down internally by a built-in 1µA current source
when the device is enabled. Flash mode is terminated
when both F EN1 and FE N2 are pull ed low or lef t floating,
and the flash register is cleared.