74ALVT16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
IC23 Data Handbook 1998 Jan 30
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
2
1998 Jan 30 853-2046-18918
FEATURES
•ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
•Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
•Distributed VCC and GND pin configuration minimizes high-speed
switching noise.
•Output capability (–32mA IOH, 64mA IOL).
•Bus hold inputs eliminate the need for external pull-up resistors.
•5V I/O compatible
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up Reset
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to VCC through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C; GND = 0V 2.5V 3.3V
UNIT
tPLH Propagation delay
C=50
p
F
3.5 2.8
ns
tPHL nAx to nBx nBx to nAx
C
L =
50
pF
3.3 2.6
ns
CIN Input capacitance VI = 0 V or VCC 4 4 pF
COUT Output capacitance VI/O = 0 V or 5.0 V 9 9 pF
ICCZ Total supply current Outputs disabled 100 80 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C74ALVT16260 DL AV16260 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C74ALVT16260 DGG AV16260 DGG SOT364-1
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 3
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 An Data inputs/outputs (A)
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 1Bn Data inputs/outputs (B1)
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 2Bn Data inputs/outputs (B2)
1, 29, 56 OEA, OE1B, OE2B Output enable input (active low)
2, 27, 30, 55 LE1B, LE2B, LEA1B, LEA2B Latch enable inputs
28 SEL B1/B2 input select input
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 VCC Positive supply voltage
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12 45
46
47
48
49
50
51
52
53
54
55
56OEA
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B8
2B7
2B9
GND
2B10A4
13
14
15
16
17
18 39
40
41
42
43
44A5
A6
A7
A8
A9
2B11
1B12
2B12
1B11
1B10
GND
19 38
GND
A10
20
21
22
23
24
25 32
33
34
35
36
37A11
A12
VCC
1B1
1B2
1B9
VCC
1B8
1B6
1B5
GNDGND
26 31 1B41B3
27 30 LEA1BLE2B
28 29SEL OE1B
LE1B
1B7
SA00435
FUNCTION TABLES
B to A (OEB = H)
INPUTS OUTPUT
1B 2B SEL LE1B LE2B OEA A
H X H H X L H
L X H H X L L
X X H L X L A0
X H L X H L H
X L L X H L L
X X L X L L A0
X X X X X H Z
A to B (OEA = H)
INPUTS OUTPUT
A LEA1B LEA2B OE1B OE2B 1B 2B
H H H L L H H
L H H L L L L
H H L L L H 2B0
L H L L L L 2B0
H L H L L 1B0 H
L L H L L 1B0 L
X L L L L 1B0 2B0
X X X H H Z Z
X X X L H Active Z
X X X H L Z Active
X X X L L Active Active
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 4
LOGIC DIAGRAM (POSITIVE LOGIC)
G1
1
1
C1
1D
C1
1D
C1
1D
C1
1D
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
8
2B1
1B1
23
6
TO 11 OTHER CHANNELS
SA00436
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 5
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
IIK DC input diode current VI < 0 –50 mA
VIDC input voltage3–0.5 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3Output in Off or High state –0.5 to +7.0 V
IO
DC out
p
ut current
Output in Low state 128
mA
I
OUT
DC
o
u
tp
u
t
c
u
rrent
Output in High state –64
mA
Tstg Storage temperature range –65 to +150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
2.5V RANGE LIMITS 3.3V RANGE LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX MIN MAX
UNIT
VCC DC supply voltage 2.3 2.7 3.0 3.6 V
VIInput voltage 0 5.5 0 5.5 V
VIH High-level input voltage 1.7 2.0 V
VIL Input voltage 0.7 0.8 V
IOH High-level output current –8 –32 mA
IOL
Low-level output current 8 32
mA
I
OL Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64
mA
∆t/∆vInput transition rise or fall rate; Outputs enabled 10 10 ns/V
Tamb Operating free-air temperature range –40 +85 –40 +85 °C
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 6
DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE) LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VIK Input clamp voltage VCC = 3.0V ; IIK = –18mA –0.85 1.2 V
VOH
High-level out
p
ut voltage
VCC = 3.0 to 3.6V ; IOH = –100µA VCC–0.2 VCC
V
V
OH
High
-
level
out ut
voltage
VCC = 3.0V ; IOH = –32mA 2.0 2.3
V
VCC = 3.0V ; IOL = 100µA 0.07 0.2
VOL
Low–level out
p
ut voltage
VCC = 3.0V ; IOL = 16mA 0.25 0.4
V
V
OL
Low
–
level
out ut
voltage
VCC = 3.0V ; IOL = 32mA 0.3 0.5
V
VCC = 3.0V ; IOL = 64mA 0.4 0.55
VRST Power-up output low voltage6VCC = 3.6V; IO = 1mA; VI = VCC or GND 0.55 V
VCC = 3.6V ; V I = VCC or GND Control pins 0.1 ±1
II
In
p
ut leakage current
VCC = 0 or 3.6V ; V I = 5.5V 0.1 10
µA
I
I
In ut
leakage
current
VCC = 3.6V ; V I = VCC
Data
p
ins4
0.1 1
µA
VCC = 3.6V ; V I = 0V
Data
ins4
0.1 -5
IOFF Off current VCC = 0V ; VI or VO = 0 to 4.5V 0.1 ±100 µA
Bus Hold current
VCC = 3V ; VI = 0.8V 75 130
IHOLD
Bus
Hold
current
Data in
p
uts7
VCC = 3V ; VI = 2.0V –75 –140 µA
Data
inputs7
VCC = 0V to 3.6V ; V CC = 3.6V ±500
IEX Current into an output in the
High state when VO > VCC VO = 5.5V ; V CC = 3.0V 10 125 µA
IPU/PD Power up/down 3-State output
current3VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC
OE/OE = Don’t care 1±100 µA
IOZH 3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5µA
IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 5µA
ICCH VCC = 3.6V ; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1
ICCL Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3.7 6 mA
ICCZ VCC = 3.6V ; Outputs Disabled; VI = GND or VCC, IO = 050.04 0.1
∆ICC Additional supply current per
input pin2VCC = 3V to 3.6V ; One input at V CC–0.6V,
Other inputs at VCC or GND 0.04 0.4 mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ±0.2V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 7
AC ELECTRICAL CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V ; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL PARAMETER Tamb = –40°C to +85°C
VCC = +3.3V ± 0.3V UNIT
FROM (INPUT) TO (OUTPUT) MIN TYP MAX
tPLH
AorB
BorA
1 2.8 4.8 ns
tPHL
A
or
B
B
or
A
1 2.6 4.6 ns
tPLH
LE
AorB
1.1 2.9 4.6 ns
tPHL
LE
A
or
B
1.1 3.1 4.7 ns
t
SEL (B1) A 1.3 2.3 3.4 ns
t
PLH SEL (B2) A 1.1 2.4 3.8 ns
t
SEL (B1) A 1.5 2.4 3.6 ns
t
PHL SEL (B2) A 1.6 2.4 3.6 ns
tPZH
OE
AorB
1 2.3 4.2 ns
tPZL
OE
A
or
B
1.6 2.3 4.0 ns
tPHZ
OE
AorB
2.2 4.4 6.0 ns
tPLZ
OE
A
or
B
1.3 3.1 5.0 ns
AC SETUP CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V ; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL PARAMETER Tamb = –40°C to +85°C
VCC = +3.3V ± 0.3V UNIT
MIN MAX
twPulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 ns
tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓1 ns
thHold time, data after LE1B, LE2B, LEA1B, or LEA2B↓1 ns
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 8
DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE) LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VIK Input clamp voltage VCC = 2.3V ; IIK = –18mA –0.85 –1.2 V
VOH
High-level out
p
ut voltage
VCC = 2.3 to 3.6V ; IOH = –100µA VCC–0.2 VCC
V
V
OH
High
-
level
out ut
voltage
VCC = 2.3V ; IOH = –8mA 1.8 2.1
V
VOL
Low-level out
p
ut voltage
VCC = 2.3V ; IOL = 100µA 0.07 0.2
V
OL
Low
-
level
out ut
voltage
VCC = 2.3V ; IOL = 24mA 0.3 0.5
VRST Power-up output low voltage7VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 V
VCC = 2.7V ; V I = VCC or GND Control pins 0.1 ±1
II
In
p
ut leakage current
VCC = 0 or 2.7V ; V I = 5.5V 0.1 10
µA
I
I
In ut
leakage
current
VCC = 2.7V ; V I = VCC
Data
p
ins4
0.1 1
µA
VCC = 2.7V ; V I = 0
Data
ins4
0.1 -5
IOFF Off current VCC = 0V ; VI or VO = 0 to 4.5V 0.1 100 µA
IH
O
LD Bus Hold current VCC = 2.3V; VI = 0.7V 90
µA
HOLD
Data inputs6VCC = 2.3V ; V I = 1.7V –10
µA
IEX Current into an output in the
High state when VO > VCC VO = 5.5V ; V CC = 2.3V 10 125 µA
IPU/PD Power up/down 3-State output
current3VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care 1 100 µA
IOZH 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5µA
IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA
ICCH VCC = 2.7V ; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1
ICCL Quiescent supply current VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 2.7 4.5 mA
ICCZ VCC = 2.7V ; Outputs Disabled; VI = GND or VCC, IO = 050.04 0.1
∆ICC Additional supply current per
input pin2VCC = 2.3V to 2.7V ; One input at VCC–0.6V,
Other inputs at VCC or GND 0.04 0.4 mA
NOTES:
1. All typical values are at VCC = 2.5V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ±0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 9
AC ELECTRICAL CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V ; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL PARAMETER Tamb = –40°C to +85°C
VCC = +2.5V ± 0.2V UNIT
FROM (INPUT) TO (OUTPUT) MIN TYP MAX
tPLH
AorB
BorA
1 3.5 5.3 ns
tPHL
A
or
B
B
or
A
1 3.3 5.4 ns
tPLH
LE
AorB
1.1 3.9 6.0 ns
tPHL
LE
A
or
B
1.1 4.2 6.2 ns
t
SEL (B1) A 1.3 2.9 4.5 ns
t
PLH SEL (B2) A 1.1 3.3 4.8 ns
t
SEL (B1) A 1.5 3.0 4.5 ns
t
PHL SEL (B2) A 1.6 3.2 4.6 ns
tPZH
OE
AorB
1 3.1 5.0 ns
tPZL
OE
A
or
B
1.6 2.0 3.0 ns
tPHZ
OE
AorB
2.2 4.0 6.6 ns
tPLZ
OE
A
or
B
1.3 2.0 3.4 ns
AC SETUP CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V ; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
SYMBOL PARAMETER Tamb = –40°C to +85°C
VCC = +2.5V ± 0.2V UNIT
MIN MAX
twPulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 ns
tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓1 ns
thHold time, data after LE1B, LE2B, LEA1B, or LEA2B↓1 ns
Philips Semiconductors Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30 10
AC WAVEFORMS
VM = 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
tw
VMVM
3V
0V
INPUT
SA00437
Figure 1. Pulse duration
VMVM
3V
0V
INPUT
tPLH
VMVM
VOH
VOL
tPHL
VOH
VOL
VM
VM
tPHL tPLH
OUTPUT
OUTPUT
SA00438
All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr ≤ 2.5ns, tf ≤ 2.5ns.
Figure 2. Propagation delay times;
inverting and non-inverting outputs
VMVM
3V
0V
DATA INPUT
0V
3V
TIMING INPUT VM
tsu th
SA00439
Figure 3. Setup and hold times
VMVM
3V
0V
OUTPUT
CONTROL
tPZL
VMVOL + 0.3V
3.5V
VOL
tPLZ
VOH
≈0V
VOH – 0.3V
tPZH tPHZ
OUTPUT
WAVEFORM 1
S1 AT 7V
VM
OUTPUT
WAVEFORM 2
S1 AT OPEN
SA00440
W aveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
CL = 50pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
500Ω
500Ω
FROM OUTPUT UNDER TEST S1
7V
OPEN
GND
Load Circuit for Outputs
TEST S1
tPLH/tPHL Open
tPLZ/tPZL 7V
tPHZ/tPZH Open
SA00441
Figure 5. Test load circuit
Philips Semiconductors Product specification
74ALVT16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1988 Jan 30 11
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
Philips Semiconductors Product specification
74ALVT16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1988 Jan 30 12
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
Philips Semiconductors Product specification
74ALVT16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1988 Jan 30 13
NOTES
Philips Semiconductors Product specification
74ALVT16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1988 Jan 30 14
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03337
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Philips Semiconductors - PIP - 74ALVT16260; 12-bit to 24-bit multiplexed D-type latches (3-State)
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74ALVT16260; 12-
bit to 24-bit
multiplexed D-type
latches (3-State)
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General description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must
be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or
demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank
control in the A to B direction.
Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B,
and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the
latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is
returned high.
To ensure the high-impedance state during power-up or power-down, OE should be tied to Vcc through a pull-up resistor;
the minimum value of the resistor is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline Package (SSOP) and 56-pin Thin Shrink Small Outline
Package (TSSOP).
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Features
● ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model
● Latch-up protection exceeds 500mA per JEDEC Standard JESD-17.
● Distributed Vcc and GND pin configuration minimizes high-speed switching noise.
● Output capability (-32mA I OH , 64mA I OL ).
● Bus hold inputs eliminate the need for external pull-up resistors.
● 5V I/O compatible
● Live insertion/extraction permitted
● Power-up 3-State
● Power-up Reset
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Philips Semiconductors - PIP - 74ALVT16260; 12-bit to 24-bit multiplexed D-type latches (3-State)
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Applications
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PDF
File
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
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PDF
File
AN214_2: 74F extended octal-plus family applications (date 01-Jun-88)
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PDF
File
AN215_2: 74FXXXX Light Load input products (date 01-Apr-88)
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PDF
File
AN220_1: Synchronizing and clock driving solutions - using the 74F50XXX family (date 01-Sep-89)
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PDF
File
AN2301: Simulation Support for Philips' Advanced BiCMOS Products
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PDF
File
AN240: Interfacing 3 Volt and 5 Volt Applications
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File
AN243: LVT (Low Voltage Technology) and ALVT (Advanced LVT) (date 01-Jan-98)
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AN246: Transmission Lines and Terminations with Philips Advanced Logic Families
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Datasheet
Type number Title Publication release
date Datasheet status Page
count File size
(kB) Datasheet
74ALVT16260 12-bit to 24-bit
multiplexed D-type
latches (3-State)
1/30/1998 Product specification 14 101
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Blockdiagram(s)
Block diagram of
74ALVT16260DGG
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Parametrics
Type number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74ALVT16260DGG SOT364-1
(TSSOP56)
2.5/3.3V 12-
Bit to 24-Bit
Multiplexed
D-Type
Latch with
Bus Hold (3-
State)
4~6 Low 56 None TTL High
74ALVT16260DL SOT371-1
(SSOP56)
2.5/3.3V 12-
Bit to 24-Bit
Multiplexed
D-Type
Latch with
Bus Hold (3-
State)
4~6 Low 56 None TTL High
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Philips Semiconductors - PIP - 74ALVT16260; 12-bit to 24-bit multiplexed D-type latches (3-State)
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Products, packages, availability and ordering
Type number North American
type number Ordering code
(12NC) Marking/Packing
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File
IC packing info Package Device
status Buy online
74ALVT16260DGG 74ALVT16260DG 9352 603 44112 Standard Marking
* Tube
SOT364-1
(TSSOP56)
Full production
order this
product
online
-
74ALVT16260DG-
T 9352 603 44118 Standard Marking
* Reel Pack,
SMD, 13"
SOT364-1
(TSSOP56)
Full production
order this
product
online
-
74ALVT16260DL 74ALVT16260DL 9352 603 45112 Standard Marking
* Tube SOT371-1
(SSOP56) Full production
order this
product
online
-
74ALVT16260DL-
T 9352 603 45118 Standard Marking
* Reel Pack,
SMD, 13"
SOT371-1
(SSOP56) Full production
order this
product
online
-
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Similar products
Products
similar
to
74ALVT16260
74ALVT16260 links to the similar products page containing an overview of products that are similar in function or
related to the type number(s) as listed on this page. The similar products page includes products from the same catalog
tree(s), relevant selection guides and products from the same functional category.
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Support & tools
Download
PDF
File
Innovative Low Voltage Logic Solutions(date 01-Aug-00)
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PDF
File
Introduction to Advanced BiCMOS Logic Products(date 01-Mar-98)
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PDF
File
Family specifications ALVT16, family characteristics(date 01-Mar-98)
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PDF
File
Introduction to Advanced Low-Voltage Technology(date 01-Mar-98)
Download
PDF
File
Advanced BiCMOS features(date 01-Jan-98)
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