© 2009 Microchip Technology Inc. DS22184A-page 1
24AA32AF/24LC32AF
Device Selection Table
Features:
• Single Supply with Operation down to 1.7V for
24AA32AF devices, 2.5V for 24LC32AF devices
• Low-Power CMOS Technology:
- Read current 400 μA, max.
- Standby current 1 μA, max. (I-temp)
• 2-Wire Serial Interface, I2C™ Compatible
• Package s with 3 Addre ss Pins a re Casc adable up
to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slop e Control t o El im ina te G ro und Bo unc e
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect for 1/4 Array
(C00h-FFFh)
• ESD Protection > 4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, TSSOP,
MSOP, TDFN and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA32AF/24LC32AF
(24XX32AF*) is a 32 Kbit Electrically Erasable PROM.
The device is organized as a single block of 4K x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and read currents of only 1 μA and 400 μA,
respect ive ly. It has been deve loped for advan ced , low-
power applications such as personal communications
or data acquisition. The 24XX32AF also has a page
write capability for up to 32 bytes of data. Functional
address lines allow up to eight devices on the same
bus, f or up to 256 Kbits add ress space. The 24XX32AF
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, TDFN and MSOP packages. The
24XX32AF is also available in the 5-lead SOT-23
package.
Block Diagram
Package Types
Part
Number VCC
Range Max. Clock
Frequency Temp.
Ranges
24AA32AF 1.7-5.5 400 kHz(1) I
24LC32AF 2.5-5.5 400 kHz I, E
Note 1: 100 kHz for VCC <2.5V.
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
I/O
Control
Logic
I/O
Memory
Control
Logic
A0
A1
WP
A2
SCL
SDA
Vcc
V
SS
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP, SOIC, TSSOP SOT-23
1
2
34
5WP
VCC
SCL
VSS
SDA
TDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
8
7
6
5
1
2
3
4
32K I2C™ Serial EEPROM with Quarter-A rray Write-Protect
*24XX32AF is used in this document as a generic part number for the 24AA32AF/24LC32AF devices.
24AA32AF/24LC32AF
DS22184A-page 2 © 2009 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins......................................................................................................................................................≥ 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to max imum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
D1 — A0, A1, A2, WP, SCL
and SDA pins —————
D2 VIH High-level input voltage 0.7 VCC ——V—
D3 VIL Low-level input voltage — — 0.3 VCC
0.2 VCC V
VVCC ≥ 2.5V
VCC < 2.5V
D4 VHYS Hysteresis of Schmitt
Trigger inputs (SDA,
SCL p ins)
0.05 VCC ——VVCC ≥ 2.5V (Note 1)
D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, Vcc = 2. 5V
D6 ILI Input leakage current ——±1μAVIN = VSS or VCC
D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC
D8 CIN,
COUT Pin capacitance
(all inputs/ou tpu t s) ——10pFVCC = 5.0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D9 ICC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz
D10 ICC read — 0.05 400 μA
D11 ICCS Standby current —
—0.01
—1
5μA
μAIndustrial
Automotive
SDA = SCL = VCC = 5.5V
A0, A1, A2, WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
© 2009 Microchip Technology Inc. DS22184A-page 3
24AA32AF/24LC32AF
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—100
400 kHz 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2THIGH Clock high time 4000
600 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
3TLOW Clock low time 4700
1300 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
4T
RSDA and SCL rise time
(Note 1) —
—1000
300 ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
5TFSDA and SCL fall time
(Note 1) —300ns
6T
HD:STA Start condition hold time 4000
600 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
7T
SU:STA Start condition setup time 4700
600 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
8THD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 250
100 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
10 TSU:STO Stop condition setup time 4000
600 —
—ns 1.7 V ≤ VCC < 2.5V
2.5 V ≤ VCC ≤ 5.5V
11 TSU:WP WP setup time 4000
600 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
12 THD:WP WP hold time 4700
1300 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
13 TAA Output valid from clock
(Note 2) —
—3500
900 ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can star t
4700
1300 —
—ns 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
15 TOF Output fall time from VIH
minimum to VIL maxim um
CB ≤ 100 pF
10 +
0.1CB250 ns (Note 1)
16 TSP Input filter spike suppression
(SDA and S CL pins) —50ns(Notes 1 and 3)
17 TWC Write cycle time (byte or
page) —5ms—
18 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The com bined TSP and VHYS specif ications are d ue to new Schmitt T rigger in puts, w hich provide i mproved
noise spike suppression. This eliminates the need for a TI speci fic ati on for st a nda rd opera tio n.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
applic ation, pleas e consult the Total Endurance™ Mod el, which can be obt ained fro m Microchip’ s web s ite
at www.microchip.com.
24AA32AF/24LC32AF
DS22184A-page 4 © 2009 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D4 4
10
11 12
14
© 2009 Microchip Technology Inc. DS22184A-page 5
24AA32AF/24LC32AF
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX32AF
for multiple device operation. The levels on these
inputs are compared with the corresponding bits in the
slave address . The ch ip is s elected if th e comp arison is
true.
Up to eigh t devi ce s ma y be conn ected to th e sam e bu s
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or V SS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microc ontroller or oth er programmabl e device, th e chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 package.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz)
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL in put is u sed to sy nc hro niz e th e da t a tra nsfer
to and from the device.
2.4 Wr it e-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited for the upper 1/4 of the
array (C00h-FFFh), but read operations are not
affected.
Name PDIP SOIC TSSOP TDFN MSOP SOT-23 Description
A0 1 1 1 1 1 — Chip Address Input
A1 2 2 2 2 2 — Chip Address Input
A2 3 3 3 3 3 — Chip Address Input
VSS 4 4 4 4 4 2 Ground
SDA 5 5 5 5 5 3 Serial Address/Data I/O
SCL 6 6 6 6 6 1 Serial Clock
WP 7 7 7 7 7 5 Write-Protect Input
VCC 8 8 8 8 8 4 +1.7V to 5.5V Power Supply
24AA32AF/24LC32AF
DS22184A-page 6 © 2009 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX32AF supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the S tart and S top conditi ons, while the 24XX32AF
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimi ted (althoug h only the las t th irty -two bytes wi ll b e
stored when doing a write operation). When an over-
write doe s occu r, it wi ll re pla ce da t a in a fi rst-in firs t-o ut
(FIFO) fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Th e mast er device mus t ge nera te a n ex tra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line du ring the Acknow ledge cl ock puls e in such a
way that the SDA line is stable low during the high
period of the Acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to t he sla ve by no t ge nerati ng an Ack nowl edge b it
on the las t by te tha t has be en c locked out of th e sl av e.
In this case, the slave (24XX32AF) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 4-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX32AF does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
© 2009 Microchip Technology Inc. DS22184A-page 7
24AA32AF/24LC32AF
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The con trol by te co nsi sts of a four-bi t c ontro l c od e. F or
the 24XX3 2AF, th is i s se t as ‘1010’ bin ary for re ad an d
write op erat ions. The ne xt th ree bit s of th e co ntro l by te
are t he C hip Sele ct b its (A 2, A1 , A0) . Th e C hip S ele ct
bits all o w the us e o f up to e i gh t 24X X 32A F de vices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
corresp ond to the logic lev els on the corresp onding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
For the SOT-23 package, the address pins are not
available. During device addressing, the A1, A2, and
A0 Chip Select bits (Figure 5-2) should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A11 to A0 are used, the upper four address bit s are
“don’t c are” bits. Th e upper addre ss bits ar e transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX32AF monitors
the SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code and
appropria te d evic e sele ct bit s, th e slav e devi ce out put s
an Ackno wled ge sig nal on the SDA li ne. De pendi ng on
the state of the R/W bit, the 24XX32AF will select a
read or write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24XX32AF devices on the
same bus . In this case, sof tware can use A0 of th e con-
trol byte as address b it A12; A1 a s address bit A13; an d
A2 as ad dres s bi t A14 . It is no t p oss ib le to sequentia ll y
read across device boundaries.
The SOT-23 pa ck ag e do es not sup port mu ltip le device
addressing on the same bus.
FIGURE 5-2: ADDRES S SEQUENCE BI T ASSIGN MENTS
1010A2 A1 A0SACK
R/W
Control Code Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1010A
2A
1A
0R/W xxxxA
11 A
10 A
9A
7A
0
A
8••••••
Control Byte Address High Byte Address Low Byte
Control
Code Chip
Select
Bits x = “don’t care” bit
24AA32AF/24LC32AF
DS22184A-page 8 © 2009 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (4 bits), the Chip Select (3 bits), and the
R/W bi t (wh ich is a lo gic low) ar e clo cke d on to t he b us
by the master transmitter. This indicates to the
addressed slave receiver that the address high byte
will follow once it has generated an Acknowledge bit
during the ni nth cloc k cycle. Theref ore, the next b yte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointe r of the 24XX32AF. The next b yte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX32AF, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX32AF acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and,
during this time, the 24XX32AF will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high,
the device will acknowledge the command, but no
write cycle will occur. No data will be written and the
device will immediately accept a new command. After
a byte Write command, the internal address counter
will point to the address location following the one that
was just written.
6.2 Page Write
The write control byte, word address and the first data
byte are tra nsmitted to the 24XX3 2AF in the same wa y
as in a byte write. However, instead of generating a
S top conditio n, the master tra nsmit s up to 31 additiona l
bytes wh ich are temporarily stored in the on-ch ip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
inc rem en t ed b y ‘ 1’. If the master should transmit more
than 32 byt es prior to generating the S top condition, the
address counter will roll over and the previously
receive d dat a will be overwri tten. As w ith the by te write
operation, once the Stop condition is received, an
internal write cy cle wil l begin (Figure 6-2). If an attem pt
is made to wri te t o th e array wi th t he W P pi n he ld h ig h,
the devic e will acknowled ge the command , but no wri te
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect 1/4 of the
array (C 00h-FFFh) wh en the pi n is tie d to VCC. If tie d to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 4-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page siz e’ ) an d end at ad dres s es that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to the next p a ge as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
© 2009 Microchip Technology Inc. DS22184A-page 9
24AA32AF/24LC32AF
FIGURE 6-1: BYTE W RITE
FIGURE 6-2: PAGE W RITE
xxx
Bus Acti vi ty
Master
SDA Line
Bus Acti vi ty
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Data S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
x
xxx
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte Address
High Byte Address
Low Byte Data Byte 0 S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 31
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
x
24AA32AF/24LC32AF
DS22184A-page 10 © 2009 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by t he contro l
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the S tart b it and control byte must
be re-sent. If the cycle is complete, the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram of this operation.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
© 2009 Microchip Technology Inc. DS22184A-page 11
24AA32AF/24LC32AF
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
control by te is se t to ‘1’. There are three basic types of
read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX32 AF conta ins an address c ounter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next curren t addre ss read operati on would access da ta
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX32AF issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer , but do es generate a S top condition and the
24XX 32AF disc ontinues tran smis sion (Figure 8 -1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must
first be set. This is accomplished by sending the word
address to the 24XX32AF as part of a wri te operation
(R/W bit set to ‘0’). Once t he word addres s is se nt, th e
master generates a Start condition following the
acknowledge. This terminates the write operation, but
not before the internal Address Pointer is set. The
master issues the control byte again, but with the R/W
bit set to a ‘1’. The 24XX32AF will then issue an
acknowledge and transmit the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition which causes the
24XX32AF to discontinue transmission (Figure 8-2).
After a rando m Read command, the inter nal addr ess
counter will point to the address location following the
one that w as just rea d.
8.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX32AF trans-
mits the first data byte, the master issues an acknowl-
edge as opposed to the Stop condition used in a
random read . This ackno wledge direc ts the 24XX32 AF
to transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the m aster w ill NOT generate an ackn owledg e,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX32AF contains an internal Address
Pointer w h ich i s inc rem en ted by ‘1’ u pon c om pl etio n of
each operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The internal Address Pointer will automati-
cally roll over from address FFF to address 000 if the
master ac kn owledges the byte recei ve d from the arra y
address FFF.
FIGURE 8-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
KN
O
A
C
K
S
T
A
R
T
24AA32AF/24LC32AF
DS22184A-page 12 © 2009 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGU RE 8-3 : S EQ U ENT I AL RE A D
xxx
Bus Activity
Master
SDA Line
Bus Activity A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
TControl
Byte Address
High Byte Address
Low Byte Control
Byte Data
Byte
S
T
A
R
T
x = “don’t care” bit
S1010AAA0
210 S1010AAA1
210 P
x
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data n Data n + 1 Data n + 2 Data n + x
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
© 2009 Microchip Technology Inc. DS22184A-page 13
24AA32AF/24LC32AF
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC32AF
I/P 13F
0527
4LC32AFI
SN 0527
13F
4LAF
I527
13F
8-Lead MSOP Example:
XXXXXT
YWWNNN 4L32FI
52713F
XXXX
TYWW
NNN
3
e
3
e
8-Lead 2x3 TDFN
Example:
AH4
527
I3
XXX
YWW
NN
5-Lead SOT-23 Example:
XXNN 6QNN
24AA32AF/24LC32AF
DS22184A-page 14 © 2009 Microchip Technology Inc.
Part Number 1st Line Marking Codes
TSSOP MSOP TDFN SOT-23
I Temp. E Temp. I Temp. E Temp.
24AA32A 4AAF 4A32FT AH1 — 6PNN —
24LC32A 4LAF 4L32FT AH4 AH5 6QNN 6RNN
Note: T = Temperature grade (I, E).
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of Janu ary 1 is we ek ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event th e full Mi croch ip pa rt numbe r can not be ma rked on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
© 2009 Microchip Technology Inc. DS22184A-page 15
24AA32AF/24LC32AF
24AA32AF/24LC32AF
DS22184A-page 16 © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. DS22184A-page 17
24AA32AF/24LC32AF
 ! ""#$%& !'
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
24AA32AF/24LC32AF
DS22184A-page 18 © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. DS22184A-page 19
24AA32AF/24LC32AF
,$*-./00%12(,
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
24AA32AF/24LC32AF
DS22184A-page 20 © 2009 Microchip Technology Inc.
,$*-./00%12(,
 3&'!&"&4#*!(!!&4%&&#&
&&255***''54
© 2009 Microchip Technology Inc. DS22184A-page 21
24AA32AF/24LC32AF
24AA32AF/24LC32AF
DS22184A-page 22 © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. DS22184A-page 23
24AA32AF/24LC32AF
APPENDIX A: REVISION HISTORY
Revision A (05/09)
Original Release.
24AA32AF/24LC32AF
DS22184A-page 24 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22184A-page 25
24AA32AF/24LC32AF
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchi p.c om . Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip con sultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and even ts, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is a vailable through the web si te
at: http://support.microchip.com
24AA32AF/24LC32AF
DS22184A-page 26 © 2009 Microchip Technology Inc.
READER RESP ONSE
It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-
uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS22184A24AA32AF/24LC32AF
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2009 Microchip Technology Inc. DS22184A-page 27
24AA32AF/24LC32AF
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA32AF: 1.7V, 32 Kbit I2C Serial EEPRO M
with half-array write-protect
24AA32AFT:1.7V, 32 Kbit I2C Serial EE PRO M
with half-array write-protect (Tape and Reel)
24LC32AF: 2.5V, 32 Kbit I2C Serial EEPR O M
with half-array write-protect
24LC32AFT:2.5V, 32 Kbit I2C Serial EE PRO M
with half-array write-protect (Tape and Reel)
Temperature
Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
MNY(1)= TDFN (2x3x0.75mm body), 8-lead
OT = SOT-23 (Tape and Reel only), 5-lead
Examples:
a) 24AA32AF-I/P : Industrial Temperatur e,1.7V,
PDIP package
b) 24AA32AF-I/SN: Industrial Temperature,1.7V,
SOIC package
c) 24AA32AF-I/SM: Industrial Tempera-
ture.,1.7V, SOIC (5.28 mm) package
d) 24AA32AF-I/ST: Industrial Temperature.,1.7V,
TSSO P package
e) 24LC32AF-I/P: Industrial Temperature, 2.5V,
PDIP package
f) 24LC32AF-E/SN: Automotive Temperature,
2.5V SOIC package
g) 24LC32AF-E/ SM : Automot ive Te mper ature,
2.5V SOIC (5.28 mm) package
h) 24LC32AFT-I/ST: Industrial Temperature,
2.5V, TSSOP package, Tape and Reel
Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
24AA32AF/24LC32AF
DS22184A-page 28 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS22184A-page 29
Information contained in this publication regarding device
applications a nd the lik e is p rovided on ly for your c on ve nience
and may be supers eded by updat es . I t is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTA RT, rfPI C, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Inc orporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDE V,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming , IC SP, ICEPIC , Mi n d i , M iW i , MPASM , MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, P ICDEM.net, PICtail , PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Inc orporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22184A-page 30 © 2009 Microchip Technology Inc.
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03/26/09