S1C33221F00A - Seiko Epson Corporation

MF1419-01

Technical Manual

CMOS 32-BIT SINGLE CHIP MICROCOMPUTER

S1C33209/221/222 PRODUCT PART

S1C33209/221/222 FUNCTION PART

S1C33209/221/222

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written

permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material

or due to its application or use in any product or circuit and, further, there is no representation that this material

is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any

intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that

anything made in accordance with this material will be free from any patent or copyright infringement of a third

party. This material or portions thereof may contain technology or the subject relating to strategic products under

the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

S1C33209/221/222 Technical Manual

This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer

S1C33209/221/222.

S1C33209/221/222 PRODUCT PART

Describes the hardware specifications of the S1C33209/221/222 except for details of the peripheral circuits.

S1C33209/221/222 FUNCTION PART

Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.

R e f e r t o t he " S 1C 33 000 C or e C P U M a nua l " f or de t a i l s of t he S 1C 330 00 32- bi t R I S C C P U .

New configuration of product number

Starting April 1, 2001, the configuration of product number descriptions will be changed as listed

below. To order from April 1, 2001 please use these product numbers. For further information, please

contact Epson sales representative.

Devices

S1 C33104 F0A01

Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C33L01 D1 1

Packing specification

Version (1: Version 1)

Tool type (D1: Development Tool)

Corresponding model number (33L01: for S1C33L01)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

TABLE OF CONTENTS

EPSON i

S1C33209/221/222 PRODUCT PART

Table of Contents

1 Outline.....................................................................................................................A-1

1.1 Features...............................................................................................................................................................A-1

1.2 Block Diagram...................................................................................................................................................A-3

1.3 Pin Description..................................................................................................................................................A-4

1.3.1 Pin Layout Diagram (plastic package)...................................................................................A-4

1.3.2 Pin Functions...................................................................................................................................A-6

2 Power Supply........................................................................................................ A-12

2.1 Power Supply Pins.........................................................................................................................................A-12

2.2 Operating Voltage (VDD, VSS)....................................................................................................................A-12

2.3 Power Supply for I/O Interface (VDDE)...................................................................................................A-13

2.4 Power Supply for Analog Circuits (AVDDE)...........................................................................................A-13

3 Internal Memory ....................................................................................................A-14

3.1 ROM and Boot Address...............................................................................................................................A-14

3.2 RAM.....................................................................................................................................................................A-15

4 Peripheral Circuits................................................................................................ A-16

4.1 List of Peripheral Circuits............................................................................................................................A-16

4.2 I/O Memory Map .............................................................................................................................................A-17

5 Power-Down Control.............................................................................................A-59

6 Basic External Wiring Diagram..............................................................................A-62

7 Precautions on Mounting......................................................................................A-63

8 Electrica l Characteristics...................................................................................... A-65

8.1 Absolute Maximum Rating..........................................................................................................................A-65

8.2 Recommended Operating Conditions....................................................................................................A-66

8.3 DC Characteristics..........................................................................................................................................A-67

8.4 Current Consumption....................................................................................................................................A-69

8.5 A/D Converter Characteristics ...................................................................................................................A-70

8.6 AC Characteristics..........................................................................................................................................A-72

8.6.1 Symbol Description.....................................................................................................................A-72

8.6.2 AC Characteristics Measurement Condition......................................................................A-72

8.6.3 C33 Block AC Characteristic Tables.....................................................................................A-73

8.6.4 C33 Block AC Characteristic Timing Charts.......................................................................A-80

8.7 Oscillation Characteristics...........................................................................................................................A-87

8.8 PLL Characteristics........................................................................................................................................A-88

9 Package ................................................................................................................A-89

9.1 Plastic Package...............................................................................................................................................A-89

10 Pad Layout............................................................................................................ A-91

10.1 Pad Layout Diagram.....................................................................................................................................A-91

10.2 Pad Coordinate (S1C33209 only) ............................................................................................................A-92

TABLE OF CONTENTS

ii EPSON

Appendix A <Reference> External Device Interface Timings......................................A-94

A.1 DRAM (70ns)....................................................................................................................................................A-95

A.2 DRAM (60ns)....................................................................................................................................................A-98

A.3 ROM and Burst ROM.................................................................................................................................A-102

A.4 SRAM (55ns).................................................................................................................................................A-104

A.5 SRAM (70ns).................................................................................................................................................A-106

A.6 8255A...............................................................................................................................................................A-108

Appendix B Pin Characteristics................................................................................A-109

TABLE OF CONTENTS

EPSON iii

S1C33209/221/222 FUNCTION PART

Table of Contents

I OUTLINE

I-1 INTRODUCTION............................................................................................... B-I-1-1

I-2 BLOCK DIAGRAM............................................................................................ B-I-2-1

I-3 LIST OF PINS ...................................................................................................B-I-3-1

List of External I/O Pins .....................................................................................................................................B-I-3-1

II CORE BLOCK

II-1 INTRODUCTION.............................................................................................. B-II-1-1

II-2 CPU AND OPERATING MODE.........................................................................B-II-2-1

CPU.........................................................................................................................................................................B-II-2-1

Standby Mode.....................................................................................................................................................B-II-2-2

HALT Mode ............................................................................................................................................B-II-2-2

SLEEP Mode .........................................................................................................................................B-II-2-2

Notes on Standby Mode...................................................................................................................B-II-2-3

Test Mode.............................................................................................................................................................B-II-2-3

Debug Mode.........................................................................................................................................................B-II-2-3

Trap Table.............................................................................................................................................................B-II-2-4

II-3 INITIAL RESET................................................................................................B-II-3-1

Pins for Initial Reset...........................................................................................................................................B-II-3-1

Cold Start and Hot Start..................................................................................................................................B-II-3-1

Power-on Reset..................................................................................................................................................B-II-3-2

Reset Pulse..........................................................................................................................................................B-II-3-2

Boot Address........................................................................................................................................................B-II-3-3

Notes Related to Initial Reset........................................................................................................................B-II-3-3

II-4 BCU (BUS CONTROL UNIT) ............................................................................B-II-4-1

Pin Assignment for External System Interface.......................................................................................B-II-4-1

I/O Pin List..............................................................................................................................................B-II-4-1

Combination of System Bus Control Signals............................................................................B-II-4-3

Memory Area........................................................................................................................................................B-II-4-4

Memory Map..........................................................................................................................................B-II-4-4

External Memory Map and Chip Enable.....................................................................................B-II-4-5

Using Internal Memory on External Memory Area..................................................................B-II-4-7

Exclusive Signals for Areas.............................................................................................................B-II-4-7

Area 10....................................................................................................................................................B-II-4-8

Area 3 ......................................................................................................................................................B-II-4-9

System Configuration in Emulation Mode ................................................................................B-II-4-10

Setting External Bus Conditions .................................................................................................................B-II-4-11

Setting Device Type and Size......................................................................................................B-II-4-11

Setting SRAM Timing Conditions.................................................................................................B-II-4-12

Setting Timing Conditions of Burst ROM..................................................................................B-II-4-13

Bus Operation....................................................................................................................................................B-II-4-14

Data Arrangement in Memory.......................................................................................................B-II-4-14

Bus Operation of External Memory.............................................................................................B-II-4-14

TABLE OF CONTENTS

iv EPSON

Bus Clock.............................................................................................................................................................B-II-4-18

Bus Speed Mode...............................................................................................................................B-II-4-19

Bus Clock Output...............................................................................................................................B-II-4-19

Bus Cycles in External System Interface................................................................................................B-II-4-20

SRAM Read Cycles...........................................................................................................................B-II-4-20

Bus Timing............................................................................................................................................B-II-4-21

SRAM Write Cycles...........................................................................................................................B-II-4-22

Burst ROM Read Cycles.................................................................................................................B-II-4-24

DRAM Direct Interface....................................................................................................................................B-II-4-25

Outline of DRAM Interface..............................................................................................................B-II-4-25

DRAM Setting Conditions...............................................................................................................B-II-4-26

DRAM Read/Write Cycles...............................................................................................................B-II-4-29

DRAM Refresh Cycles.....................................................................................................................B-II-4-32

Releasing External Bus.................................................................................................................................B-II-4-33

Power-down Control by External Device................................................................................................B-II-4-34

I/O Memory of BCU.........................................................................................................................................B-II-4-35

II-5 ITC (Interrupt Controller) .................................................................................B-II-5-1

Outline of Interrupt Functions.........................................................................................................................B-II-5-1

Maskable Interrupts.............................................................................................................................B-II-5-1

Interrupt Factors and Intelligent DMA...........................................................................................B-II-5-3

Nonmaskable Interrupt (NMI) ..........................................................................................................B-II-5-3

Interrupt Processing by the CPU....................................................................................................B-II-5-3

Clearing Standby Mode by Interrupts...........................................................................................B-II-5-3

Trap Table.............................................................................................................................................................B-II-5-4

Control of Maskable Interrupts......................................................................................................................B-II-5-5

Structure of the Interrupt Controller...............................................................................................B-II-5-5

Processor Status Register (PSR)...................................................................................................B-II-5-5

Interrupt Factor Flag and Interrupt Enable Register...............................................................B-II-5-6

Interrupt Priority Register and Interrupt Levels.........................................................................B-II-5-8

IDMA Invocation..................................................................................................................................................B-II-5-9

HSDMA Invocation...........................................................................................................................................B-II-5-11

I/O Memory of Interrupt Controller.............................................................................................................B-II-5-12

Programming Notes.........................................................................................................................................B-II-5-25

II-6 CLG (Clock Generator) ....................................................................................B-II-6-1

Configuration of Clock Generator.................................................................................................................B-II-6-1

I/O Pins of Clock Generator...........................................................................................................................B-II-6-2

High-Speed (OSC3) Oscillation Circuit.......................................................................................................B-II-6-2

PLL .........................................................................................................................................................................B-II-6-3

Controlling Oscillation .......................................................................................................................................B-II-6-3

Setting and Switching Over the CPU Operati ng Clock ........................................................................B-II-6-3

Power-Control Register Protection Flag....................................................................................................B-II-6-4

Operation in Standby Mode...........................................................................................................................B-II-6-5

I/O Memory of Clock Generator....................................................................................................................B-II-6-6

Programming Notes...........................................................................................................................................B-II-6-9

II-7 DBG (Debug Unit)............................................................................................B-II-7-1

Debug Circuit........................................................................................................................................................B-II-7-1

I/O Pins of Debug Circuit.................................................................................................................................B-II-7-1

TABLE OF CONTENTS

EPSON v

III PERIPHERAL BLOCK

III-1 INTRODUCTION............................................................................................B-III-1-1

III-2 PRESCALER................................................................................................. B-III-2-1

Configuration of Prescaler..............................................................................................................................B-III-2-1

Source Clock.......................................................................................................................................................B-III-2-1

Selecting Division Ratio and Output Control for Prescaler...............................................................B-III-2-2

Source Clock Output to 8-Bit Programmable Timer.............................................................................B-III-2-2

I/O Memory of Prescaler.................................................................................................................................B-III-2-3

Programming Notes..........................................................................................................................................B-III-2-7

III-3 8-BIT PROGRAMMABLE TIMERS .................................................................B-III-3-1

Configuration of 8-Bit Programmable Timer............................................................................................B-III-3-1

Output Pins of 8-Bit Programmable Timers.............................................................................................B-III-3-1

Uses of 8-Bit Programmable Timers...........................................................................................................B-III-3-2

Control and Operation of 8-Bit Programmable Timer..........................................................................B-III-3-4

Control of Clock Output...................................................................................................................................B-III-3-7

8-Bit Programmable Timer Interrupts and DMA.....................................................................................B-III-3-8

I/O Memory of 8-Bit Programmable Timers...........................................................................................B-III-3-10

Programming Notes........................................................................................................................................B-III-3-17

III-4 16-BIT PRO GRAMMABLE TIMERS ................................................................ B-III-4-1

Configuration of 16-Bit Programmable Timer..........................................................................................B-III-4-1

I/O Pins of 16-Bit Programmable Timers..................................................................................................B-III-4-2

Uses of 16-Bit Programmable Timers........................................................................................................B-III-4-3

Control and Operation of 16-Bit Programmable Timer........................................................................B-III-4-4

Controlling Clock Out put................................................................................................................................B-III-4-7

16-Bit Programmable Timer Interrupts and DMA..................................................................................B-III-4-9

I/O Memory of 16-Bit Programmable Timers.........................................................................................B-III-4-12

Programming Notes........................................................................................................................................B-III-4-25

III-5 WATCHDOG TIMER ......................................................................................B-III-5-1

Configuration of Watchdog Timer................................................................................................................B-III-5-1

Control of Watchdog Timer............................................................................................................................B-III-5-1

Operation in Standby Modes........................................................................................................................B-III-5-2

I/O Memory of Watchdog Timer...................................................................................................................B-III-5-3

Programming Notes..........................................................................................................................................B-III-5-3

III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT...............................................B-III-6-1

Configuration of Low-Speed (OSC1) Oscillation Circuit......................................................................B-III-6-1

I/O Pins of Low-Speed (OSC1) Oscillation Circuit................................................................................B-III-6-1

Oscillator Types.................................................................................................................................................B-III-6-2

Controlling Oscillation ......................................................................................................................................B-III-6-3

Switching Over the CPU Operating Clock................................................................................................B-III-6-3

Power-Control Register Protection Flag...................................................................................................B-III-6-3

Operation in Standby Mode..........................................................................................................................B-III-6-4

OSC1 Clock Output to External Devices..................................................................................................B-III-6-4

I/O Memory of Clock Generator...................................................................................................................B-III-6-5

Programming Notes..........................................................................................................................................B-III-6-8

TABLE OF CONTENTS

vi EPSON

III-7 CLOCK TIMER ...............................................................................................B-III-7-1

Configuration of Clock Timer.........................................................................................................................B-III-7-1

Control and Operation of the Clock Timer...............................................................................................B-III-7-2

Interrupt Function..............................................................................................................................................B-III-7-4

Examples of Use of Clock Timer.................................................................................................................B-III-7-6

I/O Memory of Clock Timer............................................................................................................................B-III-7-7

Programming Notes........................................................................................................................................B-III-7-12

III-8 SERIAL INTERFACE......................................................................................B-III-8-1

Configuration of Serial Interfaces................................................................................................................B-III-8-1

Features of Serial Interfaces...........................................................................................................B-III-8-1

I/O Pins of Serial Interface.............................................................................................................................B-III-8-2

Setting Transfer Mode .......................................................................................................................B-III-8-3

Clock-Synchronized Interface.......................................................................................................................B-III-8-4

Outline of Clock-Synchronized Interface....................................................................................B-III-8-4

Setting Clock-Synchronized Interface.........................................................................................B-III-8-5

Control and Operation of Clock-Synchronized Transfer ......................................................B-III-8-7

Asynchronous Interface................................................................................................................................B-III-8-12

Outline of Asynchronous Interface.............................................................................................B-III-8-12

Setting Asynchronous Interface..................................................................................................B-III-8-13

Control and Operation of Asynchronous Transfer................................................................B-III-8-16

IrDA Interface....................................................................................................................................................B-III-8-21

Outline of IrDA Interface.................................................................................................................B-III-8-21

Setting IrDA Interface......................................................................................................................B-III-8-21

Control and Operation of IrDA Interface...................................................................................B-III-8-23

Serial Interface Interrupts and DMA.........................................................................................................B-III-8-24

I/O Memory of Serial Interface....................................................................................................................B-III-8-28

Programming Notes........................................................................................................................................B-III-8-46

III-9 INPUT/OUTPUT PORTS.................................................................................B-III-9-1

Input Ports (K Ports).........................................................................................................................................B-III-9-1

Structure of Input Port.......................................................................................................................B-III-9-1

Input-Port Pins.....................................................................................................................................B-III-9-2

Notes on Use........................................................................................................................................B-III-9-2

I/O Memory of Input Ports...............................................................................................................B-III-9-3

I/O Ports (P Ports).............................................................................................................................................B-III-9-4

Structure of I/O Port...........................................................................................................................B-III-9-4

I/O Port Pins.........................................................................................................................................B-III-9-4

I/O Control Register and I/O Modes............................................................................................B-III-9-5

I/O Memory of I/O Ports...................................................................................................................B-III-9-6

Input I nterrupt...................................................................................................................................................B-III-9-12

Port Input Interrupt...........................................................................................................................B-III-9-12

Key Input Interrupt............................................................................................................................B-III-9-14

Control Registers of the Interrupt Controller...........................................................................B-III-9-16

I/O Memory for Input Interrupts...................................................................................................B-III-9-18

Programming Notes.........................................................................................................................B-III-9-24

TABLE OF CONTENTS

EPSON vii

IV ANALOG BLOCK

IV-1 INTRODUCTION............................................................................................B-IV-1-1

IV-2 A/D CONVERTER..........................................................................................B-IV-2-1

Features and Structure of A/D Converter................................................................................................B-IV-2-1

I/O Pins of A/D Converter..............................................................................................................................B-IV-2-2

Setting A/D Converter.....................................................................................................................................B-IV-2-3

Control and Operation of A/D Conversion ...............................................................................................B-IV-2-5

A/D Converter Interrupt and DMA...............................................................................................................B-IV-2-7

I/O Memory of A/D Converter.......................................................................................................................B-IV-2-9

Programming Notes.......................................................................................................................................B-IV-2-15

V DMA BLOCK

V-1 INTRODUCTION.............................................................................................B-V-1-1

V-2 HSDMA (HIGH-SPEED DMA) ..........................................................................B-V-2-1

Functional Outline of HSDMA........................................................................................................................B-V-2-1

I/O Pins of HSDMA............................................................................................................................................B-V-2-2

Programming Control Information................................................................................................................B-V-2-3

Setting the Registers in Dual-Address Mode ............................................................................B-V-2-3

Setting the Registers in Single-Address Mode........................................................................B-V-2-6

Enabling/Disabling DMA Transfer.................................................................................................................B-V-2-7

Trigger Factor.......................................................................................................................................................B-V-2-8

Operation of HSDMA.........................................................................................................................................B-V-2-9

Operation in Dual-Address Mode..................................................................................................B-V-2-9

Operation in Single-Address Mode............................................................................................B-V-2-12

Timing Chart........................................................................................................................................B-V-2-13

Interrupt Function of HSDMA......................................................................................................................B-V-2-15

I/O Memory of HSDMA..................................................................................................................................B-V-2-17

Programming Notes........................................................................................................................................B-V-2-36

V-3 IDMA (Intelligent DMA)...................................................................................B-V-3-1

Functional Outline of IDMA.............................................................................................................................B-V-3-1

Programming Control Information................................................................................................................B-V-3-1

IDMA Invocation..................................................................................................................................................B-V-3-5

Operation of IDMA..............................................................................................................................................B-V-3-8

Linking.................................................................................................................................................................B-V-3-12

Interrupt Function of Intelligent DMA........................................................................................................B-V-3-13

I/O Memory of Intelligent DMA...................................................................................................................B-V-3-14

Programming Notes........................................................................................................................................B-V-3-17

APPENDIX I/O MAP....................................................................................B-Appendix-1

S1C33209/221/222

PRODUCT PART

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-1

1 Outline

The S1C33209/221/222 is a Seiko Epson original 32-bit microcomputer. It features high speed, low power

consumption, and low-voltage operation, and is ideal for portable products that require high-speed data processing.

The S1C33209/221/222 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral circuits including a bus

control unit, DMA controller, interrupt controller, timers, serial interface, and A/D converter, and also ROM and

RAM. A high-speed oscillation circuit and PLL, and a low-speed clock input circuit, are also included, supporting

advanced operation, power-saving operation, and high-speed realtime cl ock functions. Use of the internal MAC

(multiplication and accumulation) function in combination with the A/D converter also facilitates the design of

systems requiring DSP functions, such as speech recognition and synthesis applications.

Table 1.1 shows the various models. The package and data bus interface vary according to the model.

Table 1.1 Model Lineup

Model Package Internal RAM Internal ROM Data bus I/F

S1C33209F00A*QFP5-128pin 8K bytes None TTL

S1C33209F01A*QFP15-128pin 8K bytes None TTL

S1C33209F00E*QFP5-128pin 8K bytes None CMOS/LVTTL

S1C33209F01E*QFP15-128pin 8K bytes None CMOS/LVTTL

S1C33221***** QFP5-128pin 8K bytes 128K bytes TTL/CMOS/LVTTL

QFP15-128pin 8K bytes 128K bytes TTL/CMOS/LVTTL

S1C33222***** QFP5-128pin 8K bytes 64K bytes TTL/CMOS/LVTTL

QFP15-128pin 8K bytes 64K bytes TTL/CMOS/LVTTL

Notes: • The S1C33221/222 subcode ("*****" in the above table) is defined individually by the user. The

package and data bus I/F are specified by the user.

• The end of the S1C33209 subcode is not related to model identification.

The S1C33209F0xA0, in which the data bus interface is set to TTL level, should be used in systems with a 5 V

interface data bus.

Except where functions differ, the descriptions in this manual refer to model na mes S1C33209/221/222. Note that

functions described with reference to an individual model name apply only to that model.

1.1 Features

Core CPU

Seiko Epson original 32-bit RISC CPU S1C33000 built-in

• Basic instruction set: 105 instructions (16-bit fixed size)

• Sixteen 32-bit general-purpose register

• 32-bit ALU and 8-bit shifter

• Multiplication/division instructions and MAC (multiplication and accumulation) instruction are available

• 16.7 ns of minimum instruction execution time at 60 MHz operation

Internal memory

ROM: 128K bytes (S1C33221)

64K bytes (S1C33222)

None (S1C33209)

RAM: 8K bytes

Internal peripheral circuits

Oscillation circuit: High-speed (OSC3) oscillation circuit 33 MHz max.

Crystal/ceramic oscillator or external clock input

Low-speed (OSC1) oscillation circuit 32.768 kHz typ.

Crystal oscillator or external clock input

Timers: 8-bit timer 6 channels

16-bit timer 6 channels

Watchdog timer (16-bit timer 0's function)

Clock timer 1 channel (with alarm function)

1 OUTLINE

A-2 EPSON S1C33209/221/222 PRODUCT PART

Serial interface: 4 channels (clock-synchronous system, asynchronous system and IrDA

interface are selectable)

A/D converter: 10 bits × 8 channels

DMA controller: High-speed DMA 4 channels

Intelligent DMA 128 channels

Interrupt controller: Possible to invoke DMA

Input interrupt 10 types (programmable)

DMA controller interrupt 5 types

16-bit programmable timer interrupt 12 types

8-bit programmable timer interrupt 4 types

Serial interface interrupt 6 types

A/D converter interrupt 1 type

Clock timer interrupt 1 type

General-purpose input Shared with the I/O pins for internal peripheral circuits

and output ports: Input port 13 bits

I/O port 29 bits

External bus interface

BCU (bus control unit) built-in

• 24-bit address bus (internal 28-bit processing)

• 16-bit data bus

Data size is selectable from 8 bits and 16 bits in each area.

• Little-endian memory access; big-endian may be set in each area.

• Memory mapped I/O

• Chip enable and wait control circuits built-in

• DRAM direct interface functio n built-in

Supports fast page mode and EDO page mode.

Supports self-refresh and CAS-before RAS refresh.

• Supports burst ROM.

Operating conditions and power consumption

Operating voltage: Core (V DD) 1.8 V to 3.6 V

I/O (VDDE) 1.8 V to 5.5 V

Operating clock frequency: CPU 60 MHz max. (S1C33209; when core voltage = 3.3 V ±0.3 V)

50 MHz max. (S1C33221/222; when core voltage = 3.3 V ±0.3 V)

Operating temperature: -40 to 85°C

Power consumption: During SLEEP 4 µW typ.

During HALT 100 mW typ.

(3.3 V, 50 MHz)

During execution 230 mW typ.

(3.3 V, 50 MHz)

Note: • The values of power consumption during execution were measured when a test

program that consisted of 55% load instructions, 23% arithmetic operation

instructions, 1% mac instruction, 12% branch instructions and 9% ext

instruction was being continuously executed.

Supply form

QFP5-128 pin or QFP15-128 pin plastic package, or chip.

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-3

1.2 Block Diagram

VDD

VSS

VDDE

A[23:0]

D[15:0]

#RD

#WRL/#WR/#WE

#WRH/#BSH

#HCAS

#LCAS

#CE10IN, #CE10EX #CE[9:3]

#EMEMRD

#WAIT(P30)

#DRD(P20)

#DWE(P21)

#GAAS(P21)

#GARD(P31)

OSC3

OSC4

PLLS[1:0]

PLLC

OSC1

OSC2

FOSC1(P14)

#DMAREQx(K50, K51, K53, K54)

#DMAACKx(P32, P33, P04, P06)

#DMAENDx(P15, P16, P05, P07)

AD0–7(K60–67)

#ADTRG(K52)

AVDDE

K50–54

K60–67

#RESET

#NMI

#X2SPD

ICEMD

DSIO

EA10MD[1:0]

BCLK

#BUSREQ(P34)

#BUSACK(P35)

#BUSGET(P31)

DST[2:0](P10–12)

DPCO(P13)

DCLK(P14)

T8UFx(P10–13)

SINx(P00, P04, P27, P33)

SOUTx(P01, P05, P26, P16)

#SCLKx(P02, P06, P25, P15)

#SRDYx(P03, P07, P24, P32)

P00–07

P10–16

P20–27

P30–35

Note: None in S1C33209

128KB in S1C33221

64KB in S1C33222

S1C33209/221/222

EXCLx(P10–13, P15, P16)

TMx(P22–27)

16-bit

Programmable

Timer (6 ch.)

S1C33000

Bus Control Unit

CPU Core

Interrupt

Controller

Prescaler

OSC3/PLL

OSC1

Clock

Timer

RAM

8KB

Intelligent

DMA (128 ch.)

High-speed

DMA (4 ch.)

8-bit

Programmable

Timer (6 ch.)

Serial Interface

(4 ch.)

A/D Converter

(8 ch.)

Input Port

I/O Port

ROM

(Note*)

Figure 1.2.1 S1C33209/221/222 Block Diagram

1 OUTLINE

A-4 EPSON S1C33209/221/222 PRODUCT PART

1.3 Pin Description

1.3.1 Pin Layout Diagram (plastic package)

QFP5-128pin

65102

INDEX

381

128

103

No.

Pin name

P24/TM2/#SRDY2

P25/TM3/#SCLK2

P26/TM4/SOUT2

P15/EXCL4/#DMAEND0/#SCLK3

P27/TM5/SIN2

BCLK

P00/SIN0

P01/SOUT0

D15

P03/#SRDY0

D14

P31/#BUSGET/#GARD

D13

P32/#DMAACK0/#SRDY3

D12

P33/#DMAACK1/SIN3

D11

K54/#DMAREQ3

D10

K53/#DMAREQ2

K52/#ADTRG

K51/#DMAREQ1

P02/#SCLK0

DDE

K67/AD7

K66/AD6

No.

Pin name

K65/AD5

K50/#DMAREQ0

K64/AD4

K63/AD3

K62/AD2

DDE

K61/AD1

K60/AD0

P35/#BUSACK

DDE

#CE9/#CE17/#CE17&18

OSC2

#CE7/#RAS0/#CE13/#RAS2

OSC1

#CE6/#CE7&8

#RD

#WRL/#WR/#WE

#WRH/#BSH

#CE10EX/#CE9&10EX

#CE8/#RAS1/#CE14/#RAS3

#CE5/#CE15/#CE15&16

#CE4/#CE11/#CE11&12

P30/#WAIT/#CE4&5

No.

Pin name

#RESET

#NMI

A0/#BSL

P34/#BUSREQ/#CE6

#CE10IN

#EMEMRD

#HCAS

#LCAS

P16/EXCL5/#DMAEND1/SOUT3

A10

A20

A11

A21

A12

A22

A13

A23

A14

A15

DDE

No.

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

Pin name

A16

ICEMD

A17

A18

A19

P04/SIN1/#DMAACK2

P05/SOUT1/#DMAEND2

P06/#SCLK1/DMAACK3

PLLC

PLLS1

PLLS0

P07/#SRDY1/#DMAEND3

#X2SPD

EA10MD0

EA10MD1

(No Connection)

OSC4

P20/#DRD

OSC3

P21/#DWE/#GAAS

#CE3

P22/TM0

P23/TM1

DSIO

P10/EXCL0/T8UF0/DST0

P11/EXCL1/T8UF1/DST1

P12/EXCL2/T8UF2/DST2

P13/EXCL3/T8UF3/DPCO

P14/FOSC1/DCLK

Figure 1.3.1 Pin Layout Diagram (QFP5-128pin)

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-5

QFP15-128pin

6596

INDEX

321

128

No.

Pin name

P26/TM4/SOUT2

P15/EXCL4/#DMAEND0/#SCLK3

P27/TM5/SIN2

BCLK

P00/SIN0

P01/SOUT0

D15

P03/#SRDY0

D14

P31/#BUSGET/#GARD

D13

P32/#DMAACK0/#SRDY3

D12

P33/#DMAACK1/SIN3

D11

K54/#DMAREQ3

D10

K53/#DMAREQ2

K52/#ADTRG

K51/#DMAREQ1

P02/#SCLK0

DDE

K67/AD7

K66/AD6

K65/AD5

K50/#DMAREQ0

K64/AD4

No.

Pin name

K63/AD3

K62/AD2

DDE

K61/AD1

K60/AD0

P35/#BUSACK

DDE

#CE9/#CE17/#CE17&18

OSC2

#CE7/#RAS0/#CE13/#RAS2

OSC1

#CE6/#CE7&8

#RD

#WRL/#WR/#WE

#WRH/#BSH

#CE10EX/#CE9&10EX

#CE8/#RAS1/#CE14/#RAS3

#CE5/#CE15/#CE15&16

#CE4/#CE11/#CE11&12

P30/#WAIT/#CE4&5

#RESET

#NMI

A0/#BSL

No.

Pin name

P34/#BUSREQ/#CE6

#CE10IN

#EMEMRD

#HCAS

#LCAS

P16/EXCL5/#DMAEND1/SOUT3

A10

A20

A11

A21

A12

A22

A13

A23

A14

A15

DDE

A16

ICEMD

A17

No.

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

Pin name

A18

A19

P04/SIN1/#DMAACK2

P05/SOUT1/#DMAEND2

P06/#SCLK1/DMAACK3

PLLC

PLLS1

PLLS0

P07/#SRDY1/#DMAEND3

#X2SPD

EA10MD0

EA10MD1

(No Connection)

OSC4

P20/#DRD

OSC3

P21/#DWE/#GAAS

#CE3

P22/TM0

P23/TM1

DSIO

P10/EXCL0/T8UF0/DST0

P11/EXCL1/T8UF1/DST1

P12/EXCL2/T8UF2/DST2

P13/EXCL3/T8UF3/DPCO

P14/FOSC1/DCLK

P24/TM2/#SRDY2

P25/TM3/#SCLK2

Figure 1.3.2 Pin Layout Diagram (QFP15-128pin)

1 OUTLINE

A-6 EPSON S1C33209/221/222 PRODUCT PART

1.3.2 Pin Functions

Table 1.3.1 List of Pins for Power Supply System

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

VDD 11,77,114 8,74,111 – – Power supply (+) for the internal logic

VSS 2,25,42,57,

70,93,105,

107

127,22,39,

54,67,90,

102,104

– – Power supply (-); GND

VDDE 30,50,96 27,47,93 – – Power supply (+) for the I/O block

AVDDE 38 35 – – Analog system power supply (+); AVDDE = V DDE

Table 1.3.2 List of Pins for External Bus Interface Signals

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

#BSL 67 64 O – A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)

#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"

A[23:1] 68,71–75,

79,81,83,

85–92,94,

95,97,

99–101

65,68–72,

76,78,80,

82–89,91,

92,94,96–98

O – Address bus (A1 to A23)

D[15:0] 10,13,15,17,

19,21,23,28,

29,41,43–48

7,10,12,14,

16,18,20,25,

26,38,40–45

I/O – Data bus (D0 to D15)

#CE10EX 60 57 O – Area 10 chip enable for external memory

* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.

#CE10IN 76 73 O – Area 10 chip enable for internal ROM emulation

#CE9

#CE17 51 48 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

(default)

#CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.

#CE8

#RAS1

#CE14

#RAS3

61 58 O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

and A8D RA(D8/0x48128) = "0" (default)

#RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"00" and A8DRA(D8/0x48128) = "1"

#CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" or

"1x" and A14DRA(D8/0x48122) = "0"

#RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"01"or "1x" and A14DRA(D8/0x48122) = "1"

#CE7

#RAS0

#CE13

#RAS2

53 50 O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

and A7DRA(D7/0x48128) = "0" (default)

#RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"00" and A7DRA(D7/0x48128) = "1"

#CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" or

"1x" and A13DRA(D7/0x48122) = "0"

#RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"01" or "1x" and A13DRA(D7/0x48122) = "1"

#CE6 55 52 O – Area 6 chip enable

* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.

#CE5

#CE15 62 59 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

(default)

#CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-7

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

#CE4

#CE11 63 60 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

(default)

#CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.

#CE3 120 117 O – Area 3 chip enable

#RD 56 53 O – Read signal

#EMEMRD 78 75 O – Read signal for internal ROM emulation memory

#WRL

#WR

#WE

58 55 O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#WR: Write signal when SBUSST(D3/0x4812E) = "1"

#WE: DRAM write signal

#WRH

#BSH 59 56 O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"

#HCAS 80 77 O – #HCAS: DRAM column address strobe (high byte) signal

#LCAS 82 79 O – #LCAS: DRAM column address strobe (low byte) signal

BCLK 7 4 O – Bus clock output

P34

#BUSREQ

#CE6

69 66 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"

#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

IOC34(D4/0x402DE) = "1"

P35

#BUSACK 49 46 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1"

P30

#WAIT

#CE4&5

64 61 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"

#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

IOC30(D0/0x402DE) = "1"

P20

#DRD 117 114 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1"

P21

#DWE

#GAAS

119 116 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF)

= "0" (default)

#DWE: DRAM read signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"

#GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

P31

#BUSGET

#GARD

14 11 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and

CFEX3(D3/0x402DF) = "0" (default)

#BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1"

and CFEX3(D3/0x402DF) = "0"

#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"

EA10MD1 113 110 I Pull-up Area 10 boot mode selection

EA10MD1 EA10MD0 Mode

1 1 External ROM mode

EA10MD0 112 109 I – 1 0 Internal ROM mode

0 1 OTP mode

0 0 Internal ROM emulation mode

1 OUTLINE

A-8 EPSON S1C33209/221/222 PRODUCT PART

Table 1.3.3 List of Pins for HSDMA Control Signals

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

K50

#DMAREQ0 34 31 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)

#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"

K51

#DMAREQ1 26 23 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)

#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"

K53

#DMAREQ2 22 19 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)

#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"

K54

#DMAREQ3 20 17 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)

#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"

P32

#DMAACK0

#SRDY3

16 13 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" (default)

#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) =

"1"

#SRDY3: Serial I/F Ch.3 ready signal input/output when SSRDY3

(D3/0x402D7) = "1" and CFP32(D2/0x402DC) = "0"

P33

#DMAACK1

SIN3

18 15 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" (default)

#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) =

"1"

SIN3: Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1" and

CFP33(D3/0x402DC) = "0"

P04

SIN1

#DMAACK2

102 99 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and

CFEX4(D4/0x402DF) = "0" (default)

SIN1: Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) =

"1"

P06

#SCLK1

#DMAACK3

104 101 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and

CFEX6(D6/0x402DF) = "0" (default)

#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) =

"1" and CFEX6(D6/0x402DF) = "0"

#DMAACK3: HSDMA Ch. 3 ac knowledge output when CFEX6(D6/0x402DF) =

"1"

P15

EXCL4

#DMAEND0

#SCLK3

5 2 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1"

and IOC15(D5/0x402D6) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when

CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6) = "1"

#SCLK3: Serial I/F Ch.3 clock input/output when SSCLK3(D2/0x402D7) =

"1" and CFP15(D5/0x402D4) = "0"

P16

EXCL5

#DMAEND1

SOUT3

84 81 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1"

and IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when

CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch.3 data output when SSOUT3(D1/0x402D7) = "1" and

CFP16(D6/0x402D4) = "0"

P05

SOUT1

#DMAEND2

103 100 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and

CFEX5(D5/0x402DF) = "0" (default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when

CFEX5(D5/0x402DF) = "1"

P07

#SRDY1

#DMAEND3

110 107 I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and

CFEX7(D7/0x402DF) = "0" (default)

#SRDY1: Serial I/F Ch. 1 ready signal input/output when

CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when

CFEX7(D7/0x402DF) = "1"

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-9

Table 1.3.4 List of Pins for Internal Peripheral Circuits

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

K52

#ADTRG 24 21 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)

#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"

K60

AD0 40 37 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)

AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"

K61

AD1 39 36 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)

AD1: A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"

K62

AD2 37 34 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)

AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"

K63

AD3 36 33 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)

AD3: A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"

K64

AD4 35 32 I – K64: Input port when CFK64(D4/0x402C3) = "0" (default)

AD4: A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"

K65

AD5 33 30 I – K65: Input port when CFK65(D5/0x402C3) = "0" (default)

AD5: A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"

K66

AD6 32 29 I – K66: Input port when CFK66(D6/0x402C3) = "0" (default)

AD6: A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1"

K67

AD7 31 28 I – K67: Input port when CFK67(D7/0x402C3) = "0" (default)

AD7: A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"

P00

SIN0 8 5 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)

SIN0: Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"

P01

SOUT0 9 6 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)

SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"

P02

#SCLK0 27 24 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)

#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) =

"1"

P03

#SRDY0 12 9 I/O – P03: I/O port when CFP03(D3/0x402D0) = "0" (default)

#SRDY0: Serial I/F Ch. 0 ready signal input/output when

CFP03(D3/0x402D0) = "1"

P04

SIN1

#DMAACK2

102 99 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and

CFEX4(D4/0x402DF) = "0" (default)

SIN1: Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) =

"1"

P05

SOUT1

#DMAEND2

103 100 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and

CFEX5(D5/0x402DF) = "0"(default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when

CFEX5(D5/0x402DF) = "1"

P06

#SCLK1

#DMAACK3

104 101 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and

CFEX6(D6/0x402DF) = "0"(default)

#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) =

"1" and CFEX6(D6/0x402DF) = "0"

#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) =

"1"

P07

#SRDY1

#DMAEND3

110 107 I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and

CFEX7(D7/0x402DF) = "0"(default)

#SRDY1: Serial I/F Ch. 1 ready signal input/output when

CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when

CFEX7(D7/0x402DF) = "1"

P10

EXCL0

T8UF0

DST0

124 121 I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) =

"1", IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1",

IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)

1 OUTLINE

A-10 EPSON S1C33209/221/222 PRODUCT PART

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

P11

EXCL1

T8UF1

DST1

125 122 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) =

"1", IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1",

IOC11(D1/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DST1: DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)

P12

EXCL2

T8UF2

DST2

126 123 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and

CFEX0(D0/0x402DF) = "0"

EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) =

"1", IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"

T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1",

IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0"

DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)

P13

EXCL3

T8UF3

DPCO

127 124 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) =

"1", IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1",

IOC13(D3/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DPCO: DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)

P14

FOSC1

DCLK

128 125 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and

CFEX0(D0/0x402DF) = "0"

FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and

CFEX0(D0/0x402DF) = "0"

DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)

P15

EXCL4

#DMAEND0

#SCLK3

5 2 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1"

and IOC15(D5/0x402D6) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when

CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6) = "1"

#SCLK3: Serial I/F Ch.3 clock input/output when SSCLK3(D2/0x402D7) =

"1" and CFP15(D5/0x402D4) = "0"

P16

EXCL5

#DMAEND1

SOUT3

84 81 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1"

and IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when

CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch.3 data output when SSOUT3(D1/0x402D7) = "1" and

CFP16(D6/0x402D4) = "0"

P20

#DRD 117 114 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1"

P21

#DWE

#GAAS

119 116 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF)

= "0" (default)

#DWE: DRAM read signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"

#GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

P22

TM0 121 118 I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)

TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"

P23

TM1 122 119 I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)

TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"

P24

TM2

#SRDY2

1 126 I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)

TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1"

#SRDY2: Serial I/F Ch.2 ready signal input/output when

SSRDY2(D3/0x402DB) = "1" and CFP24 (D4/0x402D8) = "0"

P25

TM3

#SCLK2

3 128 I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)

TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1"

#SCLK2: Serial I/F Ch.2 clock input/output when SSCLK2(D2/0x402DB) =

"1" and CFP25(D5/0x402D8) = "0"

1 OUTLINE

S1C33209/221/222 PRODUCT PART EPSON A-11

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

P26

TM4

SOUT2

4 1 I/O – P26: I/O port when CFP26(D6/0x402D8) = "0" (default)

TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1"

SOUT2: Serial I/F Ch.2 data output when SSOUT2(D1/0x402DB) = "1" and

CFP26(D6/0x402D8) = "0"

P27

TM5

SIN2

6 3 I/O – P27: I/O port when CFP27(D7/0x402D8) = "0" (default)

TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1"

SIN2: Serial I/F Ch.2 data input when SSIN2(D0/0x402DB) = "1" and

CFP27(D7/0x402D8) = "0"

Table 1.3.5 List of Pins for Clock Generator

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128

OSC1 54 51 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock

input)

OSC2 52 49 O – Low-speed (OSC1) oscillation output

OSC3 118 115 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock

input)

OSC4 116 113 O – High-speed (OSC3) oscillation output

PLLS[1:0] 108,109 105,106 I – PLL set-up pins

PLLS1 PLLS0 fin (fOSC3) fout (fPSCIN)

1 1 10–30MHz 20–60MHz *1

10–25MHz 20–50MHz *2

0 1 10–15MHz 40–60MHz *1

10–12.5MHz 40–50MHz *2

0 0 PLL is not used L

*1: ROM-less model with 3.3 V ± 0.3 V operating voltage

*2: ROM built-in model, or 3.0 V ± 0.3 V operating voltage

PLLC 106 103 – – Capasitor connecting pin for PLL

Table 1.3.6 List of Other Pins

Pin name Pin No. I/O Pull-up Function

QFP5-128 QFP15-128 /down

ICEMD 98 95 I Pull-

down High-impedance control input pin

When this pin is set to High, all the output pins go into high-impedance state. This

makes it possible to disable the S1C33 chip on the board.

DSIO 123 120 I/O Pull-up Serial I/O pin for debugging

This pin is used to communicate with the debugging tool S5U1C33000H.

#X2SPD 111 108 I – Clock doubling mode set-up pin1: CPU clock = bus clock × 1, 0: CPU clock = bus

clock × 2

#NMI 66 63 I Pull-up NMI request input pin

#RESET 65 62 I Pull-up Initial reset input pin

Note:"#" in the pin names indicates that the signal is low active.

2 POWER SUPPLY

A-12 EPSON S1C33209/221/222 PRODUCT PART

2 Power Supply

This chapter explains the operating voltage of the S1C33209/221/222.

2.1 Power Supply Pins

The S1C33209/221/222 has the power supply pins shown in Table 2.1.1.

Table 2.1.1 Power Supply Pins

Pin name Pin No. Function

QFP5-128 QFP15-128

VDD 11, 77, 114 8, 74, 111 Power supply (+) for the internal logic

VSS 2, 25, 42, 57,

70, 93, 105,

107

127, 22, 39,

54, 67, 90,

102, 104

Power supply (-); GND

VDDE 30, 50, 96 27, 47, 93 Power supply (+) for the I/O block

AVDDE 38 35 Analog system power supply (+); AVDDE = V DDE

I/O

interface circuit

CPU core Internal

peripheral

circuit

VDD

1.8 to 3.6 V

1.8 to 5.5 V

GND

VDDE

I/O pins

Analog circuits

(A/D converter)

AVDDE

VSS

Figure 2.1.1 Power Supply System

2.2 Operating Voltage (V

, V

)

The core CPU and internal peripheral circuits operate with a voltage supplied between the VDD and VSS pins. The

following operating voltage can be used:

VDD = 1.8 V to 3.6 V (V SS = GND)

Note: The S1C33209/221/222 has 3 VDD pins and 8 VSS pins. Be sure to supply the operating voltage to

all the pins. Do not open any of them.

The operating clock frequency range (OSC3) is 5 MHz to 60 MHz with this voltage.

2 POWER SUPPLY

S1C33209/221/222 PRODUCT PART EPSON A-13

2.3 Power Supply for I/O Interface (V

DDE

)

The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33209/221/222,

the V DDE voltage is used as high level and the V SS voltage as low level.

Normally, supply the same voltage level as VDD. It can be supplied separately from VDD for 5 V interface. The VSS

pin is used for the ground common with VDD.

The following voltage is enabled for V DDE:

VDDE = 1.8 V to 5.5 V (V SS = GND)

Notes: • The S1C33209/221/222 has 3 VDDE pins. Be sure to supply a voltage to all the pins. Do not

open any of them.

• When an external clock is input to the OSC1 or OSC3 pin, the clock signal level must be VDD.

• The interface voltage level of the DSIO, P10, P11, P12, P13 and P14 pins is VDD.

2.4 Power Supply for Analog Circuits (AV

DDE

)

The analog power supply pin (AVDDE) is provided separately from the V DD and VDDE pins in order that the digital

circuits do not affect the analog circuit (A/D converter). The AVDDE pin is used to supply an analog power voltage

and the VSS pin is used as the analog ground.

Supply the same voltage level as the VDDE to the AVDDE pin.

AVDDE = VDDE, V SS = GND

Note: Be sure to supply VDDE to the AVDDE pin even if the analog circuit is not used.

Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make

the board pattern with consideration given to that.

3 INTERNAL MEMORY

A-14 EPSON S1C33209/221/222 PRODUCT PART

3 Internal Memory

This chapter explains the internal memory configuration.

Figure 3.1 shows the S1C33209/221/222 memory map.

Area

Areas 18–11

Area 10

Areas 9–7

Area 6

Areas 5–4

Area 3

Area 2

Area 1

Area 0

Address

0xFFFFFFF

0x1000000

0x0FFFFFF

0x0C20000

0x0C1FFFF

0x0C10000

0x0C0FFFF

0x0C00000

0x0BFFFFF

0x0400000

0x03FFFFF

0x0380000

0x037FFFF

0x0300000

0x02FFFFF

0x0100000

0x00FFFFF

0x0080000

0x007FFFF

0x0060000

0x005FFFF

0x0050000

0x004FFFF

0x0040000

0x003FFFF

0x0030000

0x0002FFF

0x0002000

0x0001FFF

0x0000000

S1C33209 S1C33221 S1C33222

External Memory

External I/O (16-bit device)

External I/O (8-bit device)

External Memory

(Reserved)

For middleware use

(Reserved)

For CPU, debug mode

(Mirror of internal

peripheral circuits) (Mirror of internal

peripheral circuits)

(Mirror of internal

peripheral circuits) (Mirror of internal

peripheral circuits)

Internal peripheral circuits

(Mirror of internal RAM)

Internal RAM (8KB)

External Memory

Internal ROM (128KB)

External Memory

External I/O (16-bit device)

External I/O (8-bit device)

External Memory

(Reserved)

For middleware use

(Reserved)

For CPU, debug mode

Internal peripheral circuits

(Mirror of internal RAM)

Internal RAM (8KB)

External Memory

Internal ROM (64KB)

External Memory

External I/O (16-bit device)

External I/O (8-bit device)

External Memory

(Reserved)

For middleware use

(Reserved)

For CPU, debug mode

Internal peripheral circuits

(Mirror of internal RAM)

Internal RAM (8KB)

Figure 3.1 Memory Map

Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status).

3.1 ROM and Boot Address

The S1C33209 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash

should be used in Area 10.

The S1C33221 has a built-in 128KB ROM, and the S1C33222 has a built-in 64KB ROM. The ROM is allocated to

Area 10, starting at address 0xC00000 (0xC00000 to 0x0C1FFFF in the S1C33221, and 0xC00000 to 0x0C0FFFF in

the S1C33222). The boot address is fixed at 0xC00000 (start address of the built-in ROM).

The built-in ROM can be used when the EA10MD[1:0] pins are set to "10" (internal ROM boot mode) and can be read

in 1 cycle.

For setting up Area 10, refer to the "BCU (Bus Controller Unit)" in "S1C33209/221/222 FUNCTION PART" in this

manual.

3 INTERNAL MEMORY

S1C33209/221/222 PRODUCT PART EPSON A-15

3.2 RAM

The S1C33209/221/222 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address

0x0001FFF.

The internal RAM is a 32-bit sized device and data can be read/writ ten in 1 cycle regardless of data size (byte, half-

word or word).

4 PERIPHERAL CIRCUITS

A-16 EPSON S1C33209/221/222 PRODUCT PART

4 Peripheral Circuits

This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the

"S1C33209/221/222 FUNCTION PART".

4.1 List of Peripheral Circuits

The S1C33209/221/222 consists of the C33 Core Block, C33 Peripheral Block, C33 DMA Block and C33 Analog

Block.

C33 Core Block

CPU S1C33000 32-bit RISC type CPU

BCU (Bus Control Unit) 24-bit external address bus and 16-bit data bus

All the BCU functions can be used.

ITC (Interrupt Controller) 39 types of interrupts are available.

CLG (Clock Generator) OSC3 oscillation circuit (33 MHz Max.), PLL and OSC1 oscillation circuit

(32.768 kHz Typ.) built-in

DBG (Debug Unit) Functional block for debugging with the S5U1C33000H (In-Circuit Debugger

for S1C33 Family)

C33 Peripheral Block

Prescaler Programmable clock generator for peripheral circuits

8-bit programmable timer 6 channels with clock output function

16-bit programmable timer 6 channels with event counter, clock output and watchdog timer functions

Serial interface 4 channels (asynchronous mode, clock synchronous mode and IrDA are

selectable.)

Input and I/O ports 13 bits of input ports and 29 bits of I/O ports (used for peripheral I/O)

Clock timer 1 channel with alarm function

C33 DMA Block

HSDMA (High-Speed DMA) 4 channels

IDMA (Intelligent DMA) 128 channels

C33 Analog Block

A/D converter 10-bit A/D converter with 8 input channels

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-17

4.2 I/O Memory Map

Table 4.2.1 I/O Memory Map

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

P8TPCK5

P8TPCK4

D7–2

reserved

8-bit timer 5 clock selection

8-bit timer 4 clock selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040140

(B) 1θ/1 0 Divided clk.

1θ/1 0 Divided clk.

8-bit timer 4/5

clock select

–

1 On 0 OffP8TON5

P8TS52

P8TS51

P8TS50

P8TON4

P8TS42

P8TS41

P8TS40

8-bit timer 5 clock control

8-bit timer 5

clock division ratio selection

8-bit timer 4 clock control

8-bit timer 4

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 5 can

generate the clock for

the serial I/F Ch.3.

θ: selected by

Prescaler clock select

8-bit timer 4 can

generate the clock for

the serial I/F Ch.2.

0040145

(B) 1

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

1 On 0 Off

θ/4096

θ/2048

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 4/5

clock control

––

P8TPCK3

P8TPCK2

P8TPCK1

P8TPCK0

D7–4

reserved

8-bit timer 3 clock selection

8-bit timer 2 clock selection

8-bit timer 1 clock selection

8-bit timer 0 clock selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040146

(B) 1θ/1 0 Divided clk.

1θ/1 0 Divided clk.

8-bit timer

clock select

––

P16TON0

P16TS02

P16TS01

P16TS00

D7–4

reserved

16-bit timer 0 clock control

16-bit timer 0

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

16-bit timer 0 can be

used as a watchdog

timer.

0040147

(B) 1 On 0 Off

P16TS0[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 0

clock control

––

P16TON1

P16TS12

P16TS11

P16TS10

D7–4

reserved

16-bit timer 1 clock control

16-bit timer 1

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040148

(B) 1 On 0 Off

P16TS1[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 1

clock control

––

P16TON2

P16TS22

P16TS21

P16TS20

D7–4

reserved

16-bit timer 2 clock control

16-bit timer 2

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040149

(B) 1 On 0 Off

P16TS2[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 2

clock control

(B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register.

The meaning of the symbols described in [Init.] are listed be low:

0, 1: Initial values that are set at initial reset.

(However, the registers for the bus and input/output ports are not initialized at hot start.)

X: Not initialized at initial reset.

–: Not set in the circuit.

4 PERIPHERAL CIRCUITS

A-18 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

––

P16TON3

P16TS32

P16TS31

P16TS30

D7–4

reserved

16-bit timer 3 clock control

16-bit timer 3

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014A

(B) 1 On 0 Off

P16TS3[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 3

clock control

––

P16TON4

P16TS42

P16TS41

P16TS40

D7–4

reserved

16-bit timer 4 clock control

16-bit timer 4

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014B

(B) 1 On 0 Off

P16TS4[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 4

clock control

––

P16TON5

P16TS52

P16TS51

P16TS50

D7–4

reserved

16-bit timer 5 clock control

16-bit timer 5

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014C

(B) 1 On 0 Off

P16TS5[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 5

clock control

1 On 0 OffP8TON1

P8TS12

P8TS11

P8TS10

P8TON0

P8TS02

P8TS01

P8TS00

8-bit timer 1 clock control

8-bit timer 1

clock division ratio selection

8-bit timer 0 clock control

8-bit timer 0

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 1 can

generate the OSC3

oscillation-stabilize

waiting period.

θ: selected by

Prescaler clock select

8-bit timer 0 can

generate the DRAM

refresh clock.

004014D

(B) 1

P8TS1[2:0] Division ratio

θ/4096

θ/2048

θ/1024

θ/512

θ/256

θ/128

θ/64

θ/32

1 On 0 Off

P8TS0[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 0/1

clock control

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-19

NameAddressRegister name Bit Function Setting Init. R/W Remarks

1 On 0 OffP8TON3

P8TS32

P8TS31

P8TS30

P8TON2

P8TS22

P8TS21

P8TS20

8-bit timer 3 clock control

8-bit timer 3

clock division ratio selection

8-bit timer 2 clock control

8-bit timer 2

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 3 can

generate the clock for

the serial I/F Ch.1.

θ: selected by

Prescaler clock select

8-bit timer 2 can

generate the clock for

the serial I/F Ch.0.

004014E

(B) 1

P8TS3[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

1 On 0 Off

P8TS2[2:0] Division ratio

θ/4096

θ/2048

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 2/3

clock control

–

PSONAD

PSAD2

PSAD1

PSAD0

D7–4

reserved

A/D converter clock control

A/D converter clock division ratio

selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014F

(B)

A/D clock

control register

1 On 0 Off

P8TS0[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

–

TCRST

TCRUN

D7–2

reserved

Clock timer reset

Clock timer Run/Stop control

–

R/W

0 when being read.

0040151

(B) 1 Reset 0 Invalid

1 Run 0 Stop

–Clock timer

Run/Stop

TCISE2

TCISE1

TCISE0

TCASE2

TCASE1

TCASE0

TCIF

TCAF

Clock timer interrupt factor

selection

Clock timer alarm factor selection

Interrupt factor generation flag

Alarm factor generation flag

R/W

R/W Reset by writing 1.

Reset by writing 1.

0040152

(B)

1 Generated 0

Not generated

1 Generated 0

Not generated

TCISE[2:0] Interrupt factor

None

Day

Hour

Minute

1 Hz

2 Hz

8 Hz

32 Hz

TCASE[2:0] Alarm factor

Day

Hour

Minute

None

Clock timer

interrupt

control register

TCD7

TCD6

TCD5

TCD4

TCD3

TCD2

TCD1

TCD0

Clock timer data 1 Hz

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

Clock timer data 32 Hz

Clock timer data 64 Hz

Clock timer data 128 Hz

0040153

(B) 1 High 0 Low

1 High 0 Low

Clock timer

divider register

–

TCMD5

TCMD4

TCMD3

TCMD2

TCMD1

TCMD0

D7–6

reserved

Clock timer second counter data

TCMD5 = MSB

TCMD0 = LSB

–

R0 when being read.0040154

(B) –

0 to 59 seconds

Clock timer

second

4 PERIPHERAL CIRCUITS

A-20 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

TCHD5

TCHD4

TCHD3

TCHD2

TCHD1

TCHD0

D7–6

reserved

Clock timer minute counter data

TCHD5 = MSB

TCHD0 = LSB

–

R/W 0 when being read.0040155

(B) –

0 to 59 minutes

Clock timer

minute register

0 to 23 hours

–

TCDD4

TCDD3

TCDD2

TCDD1

TCDD0

D7–5

reserved

Clock timer hour counter data

TCDD4 = MSB

TCDD0 = LSB

–

R/W 0 when being read.0040156

(B)

Clock timer

hour register –

0 to 65535 days

(low-order 8 bits)

TCND7

TCND6

TCND5

TCND4

TCND3

TCND2

TCND1

TCND0

Clock timer day counter data

(low-order 8 bits)

TCND0 = LSB

R/W0040157

(B)

Clock timer

day (low-order)

0 to 65535 days

(high-order 8 bits) X

R/WTCND15

TCND14

TCND13

TCND12

TCND11

TCND10

TCND9

TCND8

Clock timer day counter data

(high-order 8 bits)

TCND15 = MSB

0040158

(B)

Clock timer

day (high-

order) register

0 to 59 minutes

(Note) Can be set within 0–63.

–

TCCH5

TCCH4

TCCH3

TCCH2

TCCH1

TCCH0

D7–6

reserved

Clock timer minute comparison

data

TCCH5 = MSB

TCCH0 = LSB

–

R/W 0 when being read.0040159

(B) –Clock timer

minute

comparison

0 to 23 hours

(Note) Can be set within 0–31.

–

TCCD4

TCCD3

TCCD2

TCCD1

TCCD0

D7–5

reserved

Clock timer hour comparison data

TCCD4 = MSB

TCCD0 = LSB

–

R/W 0 when being read.004015A

(B) –Clock timer

hour

comparison

0 to 31 days

–

TCCN4

TCCN3

TCCN2

TCCN1

TCCN0

D7–5

reserved

Clock timer day comparison data

TCCN4 = MSB

TCCN0 = LSB

–

R/W 0 when being read.

Compared with

TCND[4:0].

004015B

(B) –Clock timer

day

comparison

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-21

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PTOUT0

PSET0

PTRUN0

D7–3

reserved

8-bit timer 0 clock output control

8-bit timer 0 preset

8-bit timer 0 Run/Stop control

–

R/W

0 when being read.

0040160

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 0

control register

0 to 255RLD07

RLD06

RLD05

RLD04

RLD03

RLD02

RLD01

RLD00

8-bit timer 0 reload data

RLD07 = MSB

RLD00 = LSB

R/W0040161

(B)

8-bit timer 0

reload data

0 to 255PTD07

PTD06

PTD05

PTD04

PTD03

PTD02

PTD01

PTD00

8-bit timer 0 counter data

PTD07 = MSB

PTD00 = LSB

R0040162

(B)

8-bit timer 0

counter data

–

PTOUT1

PSET1

PTRUN1

D7–3

reserved

8-bit timer 1 clock output control

8-bit timer 1 preset

8-bit timer 1 Run/Stop control

–

R/W

0 when being read.

0040164

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 1

control register

0 to 255RLD17

RLD16

RLD15

RLD14

RLD13

RLD12

RLD11

RLD10

8-bit timer 1 reload data

RLD17 = MSB

RLD10 = LSB

R/W0040165

(B)

8-bit timer 1

reload data

0 to 255PTD17

PTD16

PTD15

PTD14

PTD13

PTD12

PTD11

PTD10

8-bit timer 1 counter data

PTD17 = MSB

PTD10 = LSB

R0040166

(B)

8-bit timer 1

counter data

–

PTOUT2

PSET2

PTRUN2

D7–3

reserved

8-bit timer 2 clock output control

8-bit timer 2 preset

8-bit timer 2 Run/Stop control

–

R/W

0 when being read.

0040168

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 2

control register

0 to 255RLD27

RLD26

RLD25

RLD24

RLD23

RLD22

RLD21

RLD20

8-bit timer 2 reload data

RLD27 = MSB

RLD20 = LSB

R/W0040169

(B)

8-bit timer 2

reload data

0 to 255PTD27

PTD26

PTD25

PTD24

PTD23

PTD22

PTD21

PTD20

8-bit timer 2 counter data

PTD27 = MSB

PTD20 = LSB

R004016A

(B)

8-bit timer 2

counter data

4 PERIPHERAL CIRCUITS

A-22 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PTOUT3

PSET3

PTRUN3

D7–3

reserved

8-bit timer 3 clock output control

8-bit timer 3 preset

8-bit timer 3 Run/Stop control

–

R/W

0 when being read.

004016C

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 3

control register

0 to 255RLD37

RLD36

RLD35

RLD34

RLD33

RLD32

RLD31

RLD30

8-bit timer 3 reload data

RLD37 = MSB

RLD30 = LSB

R/W004016D

(B)

8-bit timer 3

reload data

0 to 255PTD37

PTD36

PTD35

PTD34

PTD33

PTD32

PTD31

PTD30

8-bit timer 3 counter data

PTD37 = MSB

PTD30 = LSB

R004016E

(B)

8-bit timer 3

counter data

–

PTOUT4

PSET4

PTRUN4

D7–3

reserved

8-bit timer 4 clock output control

8-bit timer 4 preset

8-bit timer 4 Run/Stop control

–

R/W

0 when being read.

0040174

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 4

control register

0 to 255RLD47

RLD46

RLD45

RLD44

RLD43

RLD42

RLD41

RLD40

8-bit timer 4 reload data

RLD47 = MSB

RLD40 = LSB

R/W0040175

(B)

8-bit timer 4

reload data

0 to 255PTD47

PTD46

PTD45

PTD44

PTD43

PTD42

PTD41

PTD40

8-bit timer 4 counter data

PTD47 = MSB

PTD40 = LSB

R0040176

(B)

8-bit timer 4

counter data

–

PTOUT5

PSET5

PTRUN5

D7–3

reserved

8-bit timer 5 clock output control

8-bit timer 5 preset

8-bit timer 5 Run/Stop control

–

R/W

0 when being read.

0040178

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 5

control register

0 to 255RLD57

RLD56

RLD55

RLD54

RLD53

RLD52

RLD51

RLD50

8-bit timer 5 reload data

RLD57 = MSB

RLD50 = LSB

R/W0040179

(B)

8-bit timer 5

reload data

0 to 255PTD57

PTD56

PTD55

PTD54

PTD53

PTD52

PTD51

PTD50

8-bit timer 5 counter data

PTD57 = MSB

PTD50 = LSB

R004017A

(B)

8-bit timer 5

counter data

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-23

NameAddressRegister name Bit Function Setting Init. R/W Remarks

WRWD

–

D6–0 EWD write protection

–0

–R/W

–0 when being read.

0040170

(B) –

Write enabled

Write-protect

Watchdog

timer write-

protect register

–

EWD

–

D7–2

–

Watchdog timer enable

–

R/W

–

0 when being read.

0040171

(B) 1

NMI enabled

NMI disabled

Watchdog

timer enable

4 PERIPHERAL CIRCUITS

A-24 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

CLKDT1

CLKDT0

PSCON

–

CLKCHG

SOSC3

SOSC1

D4–3

System clock division ratio

selection

Prescaler On/Off control

reserved

CPU operating clock switch

High-speed (OSC3) oscillation On/Off

Low-speed (OSC1) oscillation On/Off

1 On 0 Off

1 OSC3 0 OSC1

1 On 0 Off

R/W

–

R/W

Writing 1 not allowed.

0040180

(B) 1

CLKDT[1:0] Division ratio

1/8

1/4

1/2

1/1

–

Power control

–

PSCDT0

D7–1

D0 reserved

Prescaler clock selection 0

0–

R/W

0040181

(B) –Prescaler clock

select register 1 OSC1 0 OSC3/PLL

–

HLT2OP

8T1ON

–

PF1ON

D7–4

–

HALT clock option

OSC3-stabilize waiting function

reserved

OSC1 external output control

–

R/W

–

R/W

0 when being read.

Do not write 1.

0040190

(B) 1 On 0 Off

1 Off 0 On

1 On 0 Off

–

Clock option

Writing 10010110 (0x96)

removes the write protection of

the power control register

(0x40180) and the clock option

Writing another value set the

write protection.

CLGP7

CLGP6

CLGP5

CLGP4

CLGP3

CLGP2

CLGP1

CLGP0

Power control register protect flag 0

R/W004019E

(B)

Power control

protect register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-25

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0x0 to 0xFF(0x7F)TXD07

TXD06

TXD05

TXD04

TXD03

TXD02

TXD01

TXD00

Serial I/F Ch.0 transmit data

TXD07(06) = MSB

TXD00 = LSB

R/W 7-bit asynchronous

mode does not use

TXD07.

00401E0

(B)

Serial I/F Ch.0

transmit data

0x0 to 0xFF(0x7F)RXD07

RXD06

RXD05

RXD04

RXD03

RXD02

RXD01

RXD00

Serial I/F Ch.0 receive data

RXD07(06) = MSB

RXD00 = LSB

R 7-bit asynchronous

mode does not use

RXD07 (fixed at 0).

00401E1

(B)

Serial I/F Ch.0

receive data

–

TEND0

FER0

PER0

OER0

TDBE0

RDBF0

D7–6

–

Ch.0 transmit-completion flag

Ch.0 flaming error flag

Ch.0 parity error flag

Ch.0 overrun error flag

Ch.0 transmit data buffer empty

Ch.0 receive data buffer full

–

R/W

0 when being read.

Reset by writing 0.

00401E2

(B) –

1 Error 0 Normal

Transmitting

0 End

1 Error 0 Normal

1 Empty 0 Buffer full

1 Buffer full 0 Empty

Serial I/F Ch.0

status register

TXEN0

RXEN0

EPR0

PMD0

STPB0

SSCK0

SMD01

SMD00

Ch.0 transmit enable

Ch.0 receive enable

Ch.0 parity enable

Ch.0 parity mode selection

Ch.0 stop bit selection

Ch.0 input clock selection

Ch.0 transfer mode selection 1

SMD0[1:0] Transfer mode

8-bit asynchronous

7-bit asynchronous

Clock sync. Slave

Clock sync. Master

R/W

Valid only in

asynchronous mode.

00401E3

(B) 1 Enabled 0 Disabled

1 Enabled 0 Disabled

1 With parity 0 No parity

1 Odd 0 Even

1 2 bits 0 1 bit

1 #SCLK0 0

Internal clock

Serial I/F Ch.0

control register

–

DIVMD0

IRTL0

IRRL0

IRMD01

IRMD00

D7–5

–

Ch.0 async. clock division ratio

Ch.0 IrDA I/F output logic inversion

Ch.0 IrDA I/F input logic inversion

Ch.0 interface mode selection 1

IRMD0[1:0]

–

I/F mode

reserved

IrDA 1.0

reserved

General I/F

–

R/W

0 when being read.

Valid only in

asynchronous mode.

00401E4

(B) 1 1/8 0 1/16

1 Inverted 0 Direct

Serial I/F Ch.0

IrDA register

4 PERIPHERAL CIRCUITS

A-26 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0x0 to 0xFF(0x7F)TXD17

TXD16

TXD15

TXD14

TXD13

TXD12

TXD11

TXD10

Serial I/F Ch.1 transmit data

TXD17(16) = MSB

TXD10 = LSB

R/W 7-bit asynchronous

mode does not use

TXD17.

00401E5

(B)

Serial I/F Ch.1

transmit data

0x0 to 0xFF(0x7F)RXD17

RXD16

RXD15

RXD14

RXD13

RXD12

RXD11

RXD10

Serial I/F Ch.1 receive data

RXD17(16) = MSB

RXD10 = LSB

R 7-bit asynchronous

mode does not use

RXD17 (fixed at 0).

00401E6

(B)

Serial I/F Ch.1

receive data

–

TEND1

FER1

PER1

OER1

TDBE1

RDBF1

D7–6

–

Ch.1 transmit-completion flag

Ch.1 flaming error flag

Ch.1 parity error flag

Ch.1 overrun error flag

Ch.1 transmit data buffer empty

Ch.1 receive data buffer full

–

R/W

0 when being read.

Reset by writing 0.

00401E7

(B) –

1 Error 0 Normal

Transmitting

0 End

1 Error 0 Normal

1 Empty 0 Buffer full

1 Buffer full 0 Empty

Serial I/F Ch.1

status register

TXEN1

RXEN1

EPR1

PMD1

STPB1

SSCK1

SMD11

SMD10

Ch.1 transmit enable

Ch.1 receive enable

Ch.1 parity enable

Ch.1 parity mode selection

Ch.1 stop bit selection

Ch.1 input clock selection

Ch.1 transfer mode selection 1

SMD1[1:0] Transfer mode

8-bit asynchronous

7-bit asynchronous

Clock sync. Slave

Clock sync. Master

R/W

Valid only in

asynchronous mode.

00401E8

(B)

Serial I/F Ch.1

control register 1 Enabled 0 Disabled

1 Enabled 0 Disabled

1 With parity 0 No parity

1 Odd 0 Even

1 2 bits 0 1 bit

1 #SCLK1 0

Internal clock

–

DIVMD1

IRTL1

IRRL1

IRMD11

IRMD10

D7–5

–

Ch.1 async. clock division ratio

Ch.1 IrDA I/F output logic inversion

Ch.1 IrDA I/F input logic inversion

Ch.1 interface mode selection 1

IRMD1[1:0]

–

I/F mode

reserved

IrDA 1.0

reserved

General I/F

–

R/W

0 when being read.

Valid only in

asynchronous mode.

00401E9

(B) 1 1/8 0 1/16

1 Inverted 0 Direct

Serial I/F Ch.1

IrDA register

0x0 to 0xFF(0x7F)TXD27

TXD26

TXD25

TXD24

TXD23

TXD22

TXD21

TXD20

Serial I/F Ch.2 transmit data

TXD27(26) = MSB

TXD20 = LSB

R/W00401F0

(B)

Serial I/F Ch.2

transmit data

0x0 to 0xFF(0x7F)RXD27

RXD26

RXD25

RXD24

RXD23

RXD22

RXD21

RXD20

Serial I/F Ch.2 receive data

RXD27(26) = MSB

RXD20 = LSB

R00401F1

(B)

Serial I/F Ch.2

receive data

–

TEND2

FER2

PER2

OER2

TDBE2

RDBF2

D7–6

reserved

Ch.2 transmit-completion flag

Ch.2 flaming error flag

Ch.2 parity error flag

Ch.2 overrun error flag

Ch.2 transmit data buffer empty

Ch.2 receive data buffer full

–

R/W

0 when being read.

Reset by writing 0.

00401F2

(B) –

1 Error 0 Normal

Transmitting

0 End

1 Error 0 Normal

1 Empty 0 Buffer full

1 Buffer full 0 Empty

Serial I/F Ch.2

status register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-27

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TXEN2

RXEN2

EPR2

PMD2

STPB2

SSCK2

SMD21

SMD20

Ch.2 transmit enable

Ch.2 receive enable

Ch.2 parity enable

Ch.2 parity mode selection

Ch.2 stop bit selection

Ch.2 input clock selection

Ch.2 transfer mode selection 1

SMD2[1:0] Transfer mode

8-bit asynchronous

7-bit asynchronous

Clock sync. Slave

Clock sync. Master

R/W

Valid only in

asynchronous mode.

00401F3

(B)

Serial I/F Ch.2

control register 1 Enabled 0 Disabled

1 Enabled 0 Disabled

1 With parity 0 No parity

1 Odd 0 Even

1 2 bits 0 1 bit

1 #SCLK2 0

Internal clock

–

DIVMD2

IRTL2

IRRL2

IRMD21

IRMD20

D7–5

reserved

Ch.2 async. clock division ratio

Ch.2 IrDA I/F output logic inversion

Ch.2 IrDA I/F input logic inversion

Ch.2 interface mode selection 1

IRMD2[1:0]

–

I/F mode

reserved

IrDA 1.0

reserved

General I/F

–

R/W

0 when being read.

Valid only in

asynchronous mode.

00401F4

(B) 1 1/8 0 1/16

1 Inverted 0 Direct

Serial I/F Ch.2

IrDA register

0x0 to 0xFF(0x7F)TXD37

TXD36

TXD35

TXD34

TXD33

TXD32

TXD31

TXD30

Serial I/F Ch.3 transmit data

TXD37(36) = MSB

TXD30 = LSB

R/W00401F5

(B)

Serial I/F Ch.3

transmit data

0x0 to 0xFF(0x7F)RXD37

RXD36

RXD35

RXD34

RXD33

RXD32

RXD31

RXD30

Serial I/F Ch.3 receive data

RXD37(36) = MSB

RXD30 = LSB

R00401F6

(B)

Serial I/F Ch.3

receive data

–

TEND3

FER3

PER3

OER3

TDBE3

RDBF3

D7–6

reserved

Ch.3 transmit-completion flag

Ch.3 flaming error flag

Ch.3 parity error flag

Ch.3 overrun error flag

Ch.3 transmit data buffer empty

Ch.3 receive data buffer full

–

R/W

0 when being read.

Reset by writing 0.

00401F7

(B) –

1 Error 0 Normal

Transmitting

0 End

1 Error 0 Normal

1 Empty 0 Buffer full

1 Buffer full 0 Empty

Serial I/F Ch.3

status register

TXEN3

RXEN3

EPR3

PMD3

STPB3

SSCK3

SMD31

SMD30

Ch.3 transmit enable

Ch.3 receive enable

Ch.3 parity enable

Ch.3 parity mode selection

Ch.3 stop bit selection

Ch.3 input clock selection

Ch.3 transfer mode selection 1

SMD3[1:0] Transfer mode

8-bit asynchronous

7-bit asynchronous

Clock sync. Slave

Clock sync. Master

R/W

Valid only in

asynchronous mode.

00401F8

(B)

Serial I/F Ch.3

control register 1 Enabled 0 Disabled

1 Enabled 0 Disabled

1 With parity 0 No parity

1 Odd 0 Even

1 2 bits 0 1 bit

1 #SCLK3 0

Internal clock

–

DIVMD3

IRTL3

IRRL3

IRMD31

IRMD30

D7–5

reserved

Ch.3 async. clock division ratio

Ch.3 IrDA I/F output logic inversion

Ch.3 IrDA I/F input logic inversion

Ch.3 interface mode selection 1

IRMD3[1:0]

–

I/F mode

reserved

IrDA 1.0

reserved

General I/F

–

R/W

0 when being read.

Valid only in

asynchronous mode.

00401F9

(B) 1 1/8 0 1/16

1 Inverted 0 Direct

Serial I/F Ch.3

IrDA register

4 PERIPHERAL CIRCUITS

A-28 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

A/D converted data

(low-order 8 bits)

ADD0 = LSB

0x0 to 0x3FF

(low-order 8 bits) 0

R0040240

(B)

A/D conversion

result (low-

order) register

0x0 to 0x3FF

(high-order 2 bits)

––

ADD9

ADD8

D7–2

–

A/D converted data

(high-order 2 bits) ADD9 = MSB

–

R0 when being read.0040241

(B)

A/D conversion

result (high-

order) register

–

TS1

TS0

CH2

CH1

CH0

D7–6

–

A/D conversion mode selection

A/D conversion trigger selection

A/D conversion channel status

TS[1:0]

–

Trigger

#ADTRG pin

8-bit timer 0

16-bit timer 0

Software

CH[2:0] Channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

–

R/W

0 when being read.0040242

(B) 1 Continuous 0 Normal

A/D trigger

–

CE[2:0] End channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

CS[2:0] Start channel

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

–

CE2

CE1

CE0

CS2

CS1

CS0

D7–6

–

A/D converter

end channel selection

A/D converter

start channel selection

–

R/W

0 when being read.0040243

(B)

A/D channel

–

ADF

ADE

ADST

OWE

D7–4

–

Conversion-complete flag

A/D enable

A/D conversion control/status

Overwrite error flag

– –

–

R/W

0 when being read.

Reset when ADD is read.

Reset by writing 0.

0040244

(B)

A/D enable

1 Completed 0

Run/Standby

1 Start/Run 0 Stop

1 Error 0 Normal

–

ST1

ST0

D7–2

–

Input signal sampling time setup –

ST[1:0] Sampring time

9 clocks

7 clocks

5 clocks

3 clocks

–

R/W 0 when being read.

Use with 9 clocks.

0040245

(B)

A/D sampling

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-29

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

0 to 7

–

PP1L2

PP1L1

PP1L0

–

PP0L2

PP0L1

PP0L0

reserved

Port input 1 interrupt level

reserved

Port input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040260

(B)

Port input 0/1

interrupt

priority register

–

0 to 7

–

PP3L2

PP3L1

PP3L0

–

PP2L2

PP2L1

PP2L0

reserved

Port input 3 interrupt level

reserved

Port input 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040261

(B)

Port input 2/3

interrupt

priority register

–

0 to 7

–

PK1L2

PK1L1

PK1L0

–

PK0L2

PK0L1

PK0L0

reserved

Key input 1 interrupt level

reserved

Key input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040262

(B)

Key input

interrupt

priority register

–

0 to 7

–

PHSD1L2

PHSD1L1

PHSD1L0

–

PHSD0L2

PHSD0L1

PHSD0L0

reserved

High-speed DMA Ch.1

interrupt level

reserved

High-speed DMA Ch.0

interrupt level

–

R/W

–

R/W

0 when being read.

0040263

(B)

High-speed

DMA Ch.0/1

interrupt

priority register

–

0 to 7

–

PHSD3L2

PHSD3L1

PHSD3L0

–

PHSD2L2

PHSD2L1

PHSD2L0

reserved

High-speed DMA Ch.3

interrupt level

reserved

High-speed DMA Ch.2

interrupt level

–

R/W

–

R/W

0 when being read.

0040264

(B)

High-speed

DMA Ch.2/3

interrupt

priority register

–

0 to 7

–

PDM2

PDM1

PDM0

D7–3

reserved

IDMA interrupt level –

–

R/W 0 when being read.0040265

(B)

IDMA interrupt

priority register

–

0 to 7

–

P16T12

P16T11

P16T10

–

P16T02

P16T01

P16T00

reserved

16-bit timer 1 interrupt level

reserved

16-bit timer 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040266

(B)

16-bit timer 0/1

interrupt

priority register

–

0 to 7

–

P16T32

P16T31

P16T30

–

P16T22

P16T21

P16T20

reserved

16-bit timer 3 interrupt level

reserved

16-bit timer 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040267

(B)

16-bit timer 2/3

interrupt

priority register

–

0 to 7

–

P16T52

P16T51

P16T50

–

P16T42

P16T41

P16T40

reserved

16-bit timer 5 interrupt level

reserved

16-bit timer 4 interrupt level

–

R/W

–

R/W

0 when being read.

0040268

(B)

16-bit timer 4/5

interrupt

priority register

4 PERIPHERAL CIRCUITS

A-30 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

0 to 7

–

PSIO02

PSIO01

PSIO00

–

P8TM2

P8TM1

P8TM0

reserved

Serial interface Ch.0

interrupt level

reserved

8-bit timer 0–3 interrupt level

–

R/W

–

R/W

0 when being read.

0040269

(B)

8-bit timer,

serial I/F Ch.0

interrupt

priority register

–

0 to 7

–

PAD2

PAD1

PAD0

–

PSIO12

PSIO11

PSIO10

reserved

A/D converter interrupt level

reserved

Serial interface Ch.1

interrupt level

–

R/W

–

R/W

0 when being read.

004026A

(B)

Serial I/F Ch.1,

A/D interrupt

priority register

–

0 to 7

–

PCTM2

PCTM1

PCTM0

D7–3

reserved

Clock timer interrupt level –

–

R/W Writing 1 not allowed.004026B

(B)

Clock timer

interrupt

priority register

–

0 to 7

–

PP5L2

PP5L1

PP5L0

–

PP4L2

PP4L1

PP4L0

reserved

Port input 5 interrupt level

reserved

Port input 4 interrupt level

–

R/W

–

R/W

0 when being read.

004026C

(B)

Port input 4/5

interrupt

priority register

–

0 to 7

–

PP7L2

PP7L1

PP7L0

–

PP6L2

PP6L1

PP6L0

reserved

Port input 7 interrupt level

reserved

Port input 6 interrupt level

–

R/W

–

R/W

0 when being read.

004026D

(B)

Port input 6/7

interrupt

priority register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-31

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

EK1

EK0

EP3

EP2

EP1

EP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

– –

–

R/W

0 when being read.0040270

(B) 1 Enabled 0 Disabled

Key input,

port input 0–3

interrupt

enable register

–

EIDMA

EHDM3

EHDM2

EHDM1

EHDM0

D7–5

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

– –

–

R/W

0 when being read.0040271

(B) 1 Enabled 0 Disabled

DMA interrupt

enable register

E16TC1

E16TU1

–

E16TC0

E16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040272

(B) 1 Enabled 0 Disabled

16-bit timer 0/1

interrupt

enable register –

1 Enabled 0 Disabled

–

E16TC3

E16TU3

–

E16TC2

E16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040273

(B) 1 Enabled 0 Disabled

16-bit timer 2/3

interrupt

enable register –

1 Enabled 0 Disabled

–

E16TC5

E16TU5

–

E16TC4

E16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040274

(B) 1 Enabled 0 Disabled

16-bit timer 4/5

interrupt

enable register –

1 Enabled 0 Disabled

–

E8TU3

E8TU2

E8TU1

E8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040275

(B) 1 Enabled 0 Disabled

8-bit timer

interrupt

enable register

–

ESTX1

ESRX1

ESERR1

ESTX0

ESRX0

ESERR0

D7–6

reserved

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

SIF Ch.1 receive error

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

SIF Ch.0 receive error

– –

–

R/W

0 when being read.0040276

(B) 1 Enabled 0 Disabled

Serial I/F

interrupt

enable register

–

EP7

EP6

EP5

EP4

ECTM

EADE

D7–6

reserved

Port input 7

Port input 6

Port input 5

Port input 4

Clock timer

A/D converter

– –

–

R/W

0 when being read.0040277

(B) 1 Enabled 0 Disabled

Port input 4–7,

clock timer,

A/D interrupt

enable register

4 PERIPHERAL CIRCUITS

A-32 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

FK1

FK0

FP3

FP2

FP1

FP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

– –

–

R/W

0 when being read.0040280

(B) 1 Factor is

generated 0 No factor is

generated

Key input,

port input 0–3

interrupt factor

flag register

–

FIDMA

FHDM3

FHDM2

FHDM1

FHDM0

D7–5

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

– –

–

R/W

0 when being read.0040281

(B)

DMA interrupt

factor flag

generated 0 No factor is

generated

F16TC1

F16TU1

–

F16TC0

F16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040282

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 0/1

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC3

F16TU3

–

F16TC2

F16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040283

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 2/3

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC5

F16TU5

–

F16TC4

F16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040284

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 4/5

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F8TU3

F8TU2

F8TU1

F8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040285

(B) 1 Factor is

generated 0 No factor is

generated

8-bit timer

interrupt factor

flag register

–

FSTX1

FSRX1

FSERR1

FSTX0

FSRX0

FSERR0

D7–6

reserved

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

SIF Ch.1 receive error

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

SIF Ch.0 receive error

– –

–

R/W

0 when being read.0040286

(B) 1 Factor is

generated 0 No factor is

generated

Serial I/F

interrupt factor

flag register

–

FP7

FP6

FP5

FP4

FCTM

FADE

D7–6

reserved

Port input 7

Port input 6

Port input 5

Port input 4

Clock timer

A/D converter

– –

–

R/W

0 when being read.0040287

(B) 1 Factor is

generated 0 No factor is

generated

Port input 4–7,

clock timer, A/D

interrupt factor

flag register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-33

NameAddressRegister name Bit Function Setting Init. R/W Remarks

R16TC0

R16TU0

RHDM1

RHDM0

RP3

RP2

RP1

RP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040290

(B) 1 IDMA

request 0 Interrupt

request

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA request

R16TC4

R16TU4

R16TC3

R16TU3

R16TC2

R16TU2

R16TC1

R16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040291

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 1–4

IDMA request

RSTX0

RSRX0

R8TU3

R8TU2

R8TU1

R8TU0

R16TC5

R16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040292

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA request

RP7

RP6

RP5

RP4

–

RADE

RSTX1

RSRX1

Port input 7

Port input 6

Port input 5

Port input 4

reserved

A/D converter

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

–

R/W

–

R/W

0 when being read.

0040293

(B) 1 IDMA

request 0 Interrupt

request

1 IDMA

request 0 Interrupt

request

–

Serial I/F Ch.1,

A/D,

port input 4–7

IDMA request

DE16TC0

DE16TU0

DEHDM1

DEHDM0

DEP3

DEP2

DEP1

DEP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040294

(B) 1 IDMA

enabled 0 IDMA

disabled

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA enable

DE16TC4

DE16TU4

DE16TC3

DE16TU3

DE16TC2

DE16TU2

DE16TC1

DE16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040295

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 1–4

IDMA enable

DESTX0

DESRX0

DE8TU3

DE8TU2

DE8TU1

DE8TU0

DE16TC5

DE16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040296

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA enable

DEP7

DEP6

DEP5

DEP4

–

DEADE

DESTX1

DESRX1

Port input 7

Port input 6

Port input 5

Port input 4

reserved

A/D converter

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

–

R/W

–

R/W

0 when being read.

0040297

(B) 1 IDMA

enabled 0 IDMA

disabled

1 IDMA

enabled 0 IDMA

disabled

–

Serial I/F Ch.1,

A/D,

port input 4–7

IDMA enable

4 PERIPHERAL CIRCUITS

A-34 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

HSD1S3

HSD1S2

HSD1S1

HSD1S0

HSD0S3

HSD0S2

HSD0S1

HSD0S0

High-speed DMA Ch.1

trigger set-up

High-speed DMA Ch.0

trigger set-up

R/W

0040298

(B) 0

Software trigger

K51 input (falling edge)

K51 input (rising edge)

Port 1 input

Port 5 input

8-bit timer Ch.1 underflow

16-bit timer Ch.1 compare B

16-bit timer Ch.1 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

Software trigger

K50 input (falling edge)

K50 input (rising edge)

Port 0 input

Port 4 input

8-bit timer Ch.0 underflow

16-bit timer Ch.0 compare B

16-bit timer Ch.0 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.0/1

trigger set-up

HSD3S3

HSD3S2

HSD3S1

HSD3S0

HSD2S3

HSD2S2

HSD2S1

HSD2S0

High-speed DMA Ch.3

trigger set-up

High-speed DMA Ch.2

trigger set-up

R/W

0040299

(B) 0

Software trigger

K54 input (falling edge)

K54 input (rising edge)

Port 3 input

Port 7 input

8-bit timer Ch.3 underflow

16-bit timer Ch.3 compare B

16-bit timer Ch.3 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

Software trigger

K53 input (falling edge)

K53 input (rising edge)

Port 2 input

Port 6 input

8-bit timer Ch.2 underflow

16-bit timer Ch.2 compare B

16-bit timer Ch.2 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.2/3

trigger set-up

–

HST3

HST2

HST1

HST0

D7–4

reserved

HSDMA Ch.3 software trigger

HSDMA Ch.2 software trigger

HSDMA Ch.1 software trigger

HSDMA Ch.0 software trigger

–

0 when being read.004029A

(B) –

1 Trigger 0 Invalid

High-speed

DMA software

trigger

–

DENONLY

IDMAONLY

RSTONLY

D7–3

reserved

IDMA enable register set method

selection

IDMA request register set method

selection

Interrupt factor flag reset method

selection

– –

–

R/W

004029F

(B)

Flag set/reset

method select

1 Set only 0 RD/WR

1 Reset only 0 RD/WR

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-35

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

CFK54

CFK53

CFK52

CFK51

CFK50

D7–5

reserved

K54 function selection

K53 function selection

K52 function selection

K51 function selection

K50 function selection

– –

–

R/W

0 when being read.00402C0

(B) 1

#DMAREQ3

0 K54

#DMAREQ2

0 K53

1 #ADTRG 0 K52

#DMAREQ1

0 K51

#DMAREQ0

0 K50

K5 function

select register

–

K54D

K53D

K52D

K51D

K50D

D7–5

reserved

K54 input port data

K53 input port data

K52 input port data

K51 input port data

K50 input port data

– –

–

0 when being read.00402C1

(B) 1 High 0 Low

K5 input port

data register

CFK67

CFK66

CFK65

CFK64

CFK63

CFK62

CFK61

CFK60

K67 function selection

K66 function selection

K65 function selection

K64 function selection

K63 function selection

K62 function selection

K61 function selection

K60 function selection

R/W

00402C3

(B) 1 AD7 0 K67

1 AD6 0 K66

1 AD5 0 K65

1 AD4 0 K64

1 AD3 0 K63

1 AD2 0 K62

1 AD1 0 K61

1 AD0 0 K60

K6 function

select register

K67D

K66D

K65D

K64D

K63D

K62D

K61D

K60D

K67 input port data

K66 input port data

K65 input port data

K64 input port data

K63 input port data

K62 input port data

K61 input port data

K60 input port data

–

00402C4

(B) 1 High 0 LowK6 input port

data register

4 PERIPHERAL CIRCUITS

A-36 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

T8CH5S0

SIO3TS0

T8CH4S0

SIO3RS0

SIO2TS0

SIO3ES0

SIO2RS0

SIO2ES0

8-bit timer 5 underflow

SIO Ch.3 transmit buffer empty

8-bit timer 4 underflow

SIO Ch.3 receive buffer full

SIO Ch.2 transmit buffer empty

SIO Ch.3 receive error

SIO Ch.2 receive buffer full

SIO Ch.2 receive error

R/W

00402C5Interrupt factor

FP function

switching

1 SIO Ch.3

TXD Emp. 0 FP6

1 SIO Ch.3

RXD Full 0 FP4

1 SIO Ch.2

TXD Emp. 0 FP3

1 SIO Ch.3

RXD Err. 0 FP2

1 SIO Ch.2

RXD Full 0 FP1

1 SIO Ch.2

RXD Err. 0 FP0

1 T8 Ch.5 UF 0 FP7

1 T8 Ch.4 UF 0 FP5

SPT31

SPT30

SPT21

SPT20

SPT11

SPT10

SPT01

SPT00

FPT3 interrupt input port selection

FPT2 interrupt input port selection

FPT1 interrupt input port selection

FPT0 interrupt input port selection

R/W

00402C6

(B)

Port input

interrupt select

11 10 01 00

P23 P03 K53 K63

11 10 01 00

P22 P02 K52 K62

11 10 01 00

P21 P01 K51 K61

11 10 01 00

P20 P00 K50 K60

11 10 01 00

P27 P07 P33 K67

11 10 01 00

P26 P06 P32 K66

11 10 01 00

P25 P05 P31 K65

11 10 01 00

P24 P04 K54 K64

SPT71

SPT70

SPT61

SPT60

SPT51

SPT50

SPT41

SPT40

FPT7 interrupt input port selection

FPT6 interrupt input port selection

FPT5 interrupt input port selection

FPT4 interrupt input port selection

R/W

00402C7

(B)

Port input

interrupt select

1 High level

Rising edge

0 Low level

Falling

edge

SPPT7

SPPT6

SPPT5

SPPT4

SPPT3

SPPT2

SPPT1

SPPT0

FPT7 input polarity selection

FPT6 input polarity selection

FPT5 input polarity selection

FPT4 input polarity selection

FPT3 input polarity selection

FPT2 input polarity selection

FPT1 input polarity selection

FPT0 input polarity selection

R/W

00402C8

(B)

Port input

interrupt

input polarity

select register

1 Edge 0 LevelSEPT7

SEPT6

SEPT5

SEPT4

SEPT3

SEPT2

SEPT1

SEPT0

FPT7 edge/level selection

FPT6 edge/level selection

FPT5 edge/level selection

FPT4 edge/level selection

FPT3 edge/level selection

FPT2 edge/level selection

FPT1 edge/level selection

FPT0 edge/level selection

R/W

00402C9

(B)

Port input

interrupt

edge/level

select register

–

SPPK11

SPPK10

SPPK01

SPPK00

D7–4

reserved

FPK1 i

nterrupt input port selection

FPK0 i

nterrupt input port selection

–

R/W

0 when being read.00402CA

(B)

Key input

interrupt select

–

11 10 01 00

P2[7:4] P0[7:4] K6[7:4] K6[3:0]

11 10 01 00

P2[4:0] P0[4:0] K6[4:0] K5[4:0]

T8CH5S1

T8CH4S1

SIO3ES1

SIO2ES1

SIO3TS1

SIO3RS1

SIO2TS1

SIO2RS1

8-bit timer 5 underflow

8-bit timer 4 underflow

SIO Ch.3 receive error

SIO Ch.2 receive error

SIO Ch.3 transmit buffer empty

SIO Ch.3 receive buffer full

SIO Ch.2 transmit buffer empty

SIO Ch.2 receive buffer full

R/W

00402CBInterrupt factor

TM16 function

switching

RXD Err. 0 TM16 Ch.3

comp.A

1 SIO Ch.2

RXD Err. 0 TM16 Ch.3

comp.B

1 SIO Ch.3

TXD Emp. 0 TM16 Ch.4

comp.A

1 SIO Ch.3

RXD Full 0 TM16 Ch.4

comp.B

1 SIO Ch.2

TXD Emp. 0 TM16 Ch.5

comp.A

1 SIO Ch.2

RXD Full 0 TM16 Ch.5

comp.B

1 T8 Ch.5 UF 0 TM16 Ch.2

comp.A

1 T8 Ch.4 UF 0 TM16 Ch.2

comp.B

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-37

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

SCPK04

SCPK03

SCPK02

SCPK01

SCPK00

D7–5

reserved

FPK04 input comparison

FPK03 input comparison

FPK02 input comparison

FPK01 input comparison

FPK00 input comparison

– –

–

R/W

0 when being read.00402CC

(B) 1 High 0 Low

Key input

interrupt

(FPK0) input

comparison

–

SCPK13

SCPK12

SCPK11

SCPK10

D7–4

reserved

FPK13 input comparison

FPK12 input comparison

FPK11 input comparison

FPK10 input comparison

– –

–

R/W

0 when being read.00402CD

(B) 1 High 0 Low

Key input

interrupt

(FPK1) input

comparison

–

SMPK04

SMPK03

SMPK02

SMPK01

SMPK00

D7–5

reserved

FPK04 input mask

FPK03 input mask

FPK02 input mask

FPK01 input mask

FPK00 input mask

– –

–

R/W

0 when being read.00402CE

(B) 1 Interrupt

enabled 0 Interrupt

disabled

Key input

interrupt

(FPK0) input

mask register

–

SMPK13

SMPK12

SMPK11

SMPK10

D7–4

reserved

FPK13 input mask

FPK12 input mask

FPK11 input mask

FPK10 input mask

– –

–

R/W

0 when being read.00402CF

(B) 1 Interrupt

enabled 0 Interrupt

disabled

Key input

interrupt

(FPK1) input

mask register

CFP07

CFP06

CFP05

CFP04

CFP03

CFP02

CFP01

CFP00

P07 function selection

P06 function selection

P05 function selection

P04 function selection

P03 function selection

P02 function selection

P01 function selection

P00 function selection

R/W

Extended functions

(0x402DF)

00402D0

(B) 1 #SRDY1 0 P07

1 #SCLK1 0 P06

1 SOUT1 0 P05

1 SIN1 0 P04

1 #SRDY0 0 P03

1 #SCLK0 0 P02

1 SOUT0 0 P01

1 SIN0 0 P00

P0 function

select register

P07D

P06D

P05D

P04D

P03D

P02D

P01D

P00D

P07 I/O port data

P06 I/O port data

P05 I/O port data

P04 I/O port data

P03 I/O port data

P02 I/O port data

P01 I/O port data

P00 I/O port data

R/W

00402D1

(B) 1 High 0 LowP0 I/O port data

IOC07

IOC06

IOC05

IOC04

IOC03

IOC02

IOC01

IOC00

P07 I/O control

P06 I/O control

P05 I/O control

P04 I/O control

P03 I/O control

P02 I/O control

P01 I/O control

P00 I/O control

R/W

00402D2

(B) 1 Output 0 InputP0 I/O control

–

CFP16

CFP15

CFP14

CFP13

CFP12

CFP11

CFP10

reserved

P16 function selection

P15 function selection

P14 function selection

P13 function selection

P12 function selection

P11 function selection

P10 function selection

–

R/W

0 when being read.

Extended functions

(0x402DF)

00402D4

(B) 1 EXCL5

#DMAEND1

0 P16

1 EXCL4

#DMAEND0

0 P15

1 EXCL3

T8UF3 0 P13

1 EXCL2

T8UF2 0 P12

1 EXCL1

T8UF1 0 P11

1 EXCL0

T8UF0 0 P10

–P1 function

select register

1 FOSC1 0 P14

–

P16D

P15D

P14D

P13D

P12D

P11D

P10D

reserved

P16 I/O port data

P15 I/O port data

P14 I/O port data

P13 I/O port data

P12 I/O port data

P11 I/O port data

P10 I/O port data

–

R/W

0 when being read.00402D5

(B) 1 High 0 Low

–

P1 I/O port data

4 PERIPHERAL CIRCUITS

A-38 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

IOC16

IOC15

IOC14

IOC13

IOC12

IOC11

IOC10

reserved

P16 I/O control

P15 I/O control

P14 I/O control

P13 I/O control

P12 I/O control

P11 I/O control

P10 I/O control

–

R/W

0 when being read.00402D6

(B) 1 Output 0 Input

–P1 I/O control

–

SSRDY3

SSCLK3

SSOUT3

SSIN3

D7–4

reserved

Serial I/F Ch.3 SRDY selection

Serial I/F Ch.3 SCLK selection

Serial I/F Ch.3 SOUT selection

Serial I/F Ch.3 SIN selection

– –

–

R/W

00402D7Port SIO

function

extension

1 #SRDY3 0

P32/

#DMAACK0

1 #SCLK3 0

P15/EXCL4/

#DMAEND0

1 SOUT3 0

P16/EXCL5/

#DMAEND1

1 SIN3 0

P33/

#DMAACK1

CFP27

CFP26

CFP25

CFP24

CFP23

CFP22

CFP21

CFP20

P27 function selection

P26 function selection

P25 function selection

P24 function selection

P23 function selection

P22 function selection

P21 function selection

P20 function selection

R/W

R/W Ext. func.(0x402DF)

00402D8

(B) 1 TM5 0 P27

1 TM4 0 P26

1 TM3 0 P25

1 TM2 0 P24

1 TM1 0 P23

1 TM0 0 P22

1 #DWE 0 P21

1 #DRD 0 P20

P2 function

select register

P27D

P26D

P25D

P24D

P23D

P22D

P21D

P20D

P27 I/O port data

P26 I/O port data

P25 I/O port data

P24 I/O port data

P23 I/O port data

P22 I/O port data

P21 I/O port data

P20 I/O port data

R/W

00402D9

(B) 1 High 0 LowP2 I/O port data

IOC27

IOC26

IOC25

IOC24

IOC23

IOC22

IOC21

IOC20

P27 I/O control

P26 I/O control

P25 I/O control

P24 I/O control

P23 I/O control

P22 I/O control

P21 I/O control

P20 I/O control

R/W

00402DA

(B) 1 Output 0 InputP2 I/O control

–

SSRDY2

SSCLK2

SSOUT2

SSIN2

D7–4

reserved

Serial I/F Ch.2 SRDY selection

Serial I/F Ch.2 SCLK selection

Serial I/F Ch.2 SOUT selection

Serial I/F Ch.2 SIN selection

–

R/W

00402DB 1 #SRDY2 0 P24/TM2

1 #SCLK2 0 P25/TM3

1 SOUT2 0 P26/TM4

1 SIN2 0 P27/TM5

Port SIO

function

extension

–

CFP35

CFP34

CFP33

CFP32

CFP31

CFP30

D7–6

reserved

P35 function selection

P34 function selection

P33 function selection

P32 function selection

P31 function selection

P30 function selection

–

R/W

0 when being read.

Ext. func.(0x402DF)

00402DC

(B) –P3 function

select register 1 #BUSACK 0 P35

1 #BUSREQ

#CE6 0 P34

#DMAACK0

0 P32

1 #BUSGET 0 P31

1 #WAIT

#CE4/#CE5 0 P30

#DMAACK1

0 P33

–

P35D

P34D

P33D

P32D

P31D

P30D

D7–6

reserved

P35 I/O port data

P34 I/O port data

P33 I/O port data

P32 I/O port data

P31 I/O port data

P30 I/O port data

–

R/W

0 when being read.00402DD

(B) 1 High 0 Low

–

P3 I/O port data

–

IOC35

IOC34

IOC33

IOC32

IOC31

IOC30

D7–6

reserved

P35 I/O control

P34 I/O control

P33 I/O control

P32 I/O control

P31 I/O control

P30 I/O control

–

R/W

0 when being read.00402DE

(B) 1 Output 0 Input

–P3 I/O control

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-39

NameAddressRegister name Bit Function Setting Init. R/W Remarks

CFEX7

CFEX6

CFEX5

CFEX4

CFEX3

CFEX2

CFEX1

CFEX0

P07 port extended function

P06 port extended function

P05 port extended function

P04 port extended function

P31 port extended function

P21 port extended function

P10, P11, P13 port extended

function

P12, P14 port extended function

R/W

00402DF

(B)

Port function

extension

#DMAEND3

0 P07, etc.

#DMAACK3

0 P06, etc.

#DMAEND2

0 P05, etc.

#DMAACK2

0 P04, etc.

1 #GARD 0 P31, etc.

1 #GAAS 0 P21, etc.

1 DST0

DST1

DPC0

0 P10, etc.

P11, etc.

P13, etc.

1 DST2

DCLK 0 P12, etc.

P14, etc.

–

A18SZ

A18DF1

A18DF0

–

A18WT2

A18WT1

A18WT0

–

A16SZ

A16DF1

A16DF0

–

A16WT2

A16WT1

A16WT0

reserved

Areas 18–17 device size selection

Areas 18–17

output disable delay time

reserved

Areas 18–17 wait control

reserved

Areas 16–15 device size selection

Areas 16–15

output disable delay time

reserved

Areas 16–15 wait control

–

1 8 bits 0 16 bits

1 8 bits 0 16 bits –

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

0048120

(HW)

Areas 18–15

set-up register

A18DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A16DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A18WT[2:0] Wait cycles

A16WT[2:0] Wait cycles

–

A14DRA

A13DRA

A14SZ

A14DF1

A14DF0

–

A14WT2

A14WT1

A14WT0

DF–9

reserved

Area 14 DRAM selection

Area 13 DRAM selection

Areas 14–13 device size selection

Areas 14–13

output disable delay time

reserved

Areas 14–13 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

0 when being read.

0048122

(HW)

A14DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A14WT[2:0] Wait cycles

Areas 14–13

set-up register

4 PERIPHERAL CIRCUITS

A-40 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A12SZ

A12DF1

A12DF0

–

A12WT2

A12WT1

A12WT0

DF–7

reserved

Areas 12–11 device size selection

Areas 12–11

output disable delay time

reserved

Areas 12–11 wait control

–

1 8 bits 0 16 bits –

–

R/W

–

R/W

0 when being read.

0048124

(HW)

Areas 12–11

set-up register

A18DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A18WT[2:0] Wait cycles

–

A10IR2

A10IR1

A10IR0

–

A10BW1

A10BW0

A10DRA

A9DRA

A10SZ

A10DF1

A10DF0

–

A10WT2

A10WT1

A10WT0

reserved

Area 10 internal ROM size

selection

reserved

Areas 10–9

burst ROM

burst read cycle wait control

Area 10 burst ROM selection

Area 9 burst ROM selection

Areas 10–9 device size selection

Areas 10–9

output disable delay time

reserved

Areas 10–9 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

–

R/W

0 when being read.

0048126

(HW)

A10BW[1:0] Wait cycles

A10DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A10IR[2:0] ROM size

2MB

1MB

512KB

256KB

128KB

64KB

32KB

16KB

A10WT[2:0] Wait cycles

Areas 10–9

set-up register

–

A8DRA

A7DRA

A8SZ

A8DF1

A8DF0

–

A8WT2

A8WT1

A8WT0

DF–9

reserved

Area 8 DRAM selection

Area 7 DRAM selection

Areas 8–7 device size selection

Areas 8–7

output disable delay time

reserved

Areas 8–7 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

0 when being read.

0048128

(HW)

Areas 8–7

set-up register

A8DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A8WT[2:0] Wait cycles

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-41

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A6DF1

A6DF0

–

A6WT2

A6WT1

A6WT0

–

A5SZ

A5DF1

A5DF0

–

A5WT2

A5WT1

A5WT0

DF–E

reserved

Area 6

output disable delay time

reserved

Area 6 wait control

reserved

Areas 5–4 device size selection

Areas 5–4

output disable delay time

reserved

Areas 5–4 wait control

–

1 8 bits 0 16 bits

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

004812A

(HW)

Areas 6–4

set-up register 1

A6DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A5DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A6WT[2:0] Wait cycles

A5WT[2:0] Wait cycles

TBRP7

TBRP6

TBRP5

TBRP4

TBRP3

TBRP2

TBRP1

TBRP0

TTBR register write protect 0

W Undefined in read.004812D

(B) Writing 01011001(0x59)

removes the TTBR (0x48134)

write protection.

Writing other data sets the

write protection.

TTBR write

protect register

RBCLK

–

RBST8

REDO

RCA1

RCA0

RPC2

RPC1

RPC0

RRA1

RRA0

–

SBUSST

SEMAS

SEPD

SWAITE

BCLK output control

reserved

Burst ROM burst mode selection

DRAM page mode selection

Column address size selection

Refresh enable

Refresh method selection

Refresh RPC delay setup

Refresh RAS pulse width

selection

reserved

External interface method selection

External bus master setup

External power-down control

#WAIT enable

–

1 Fixed at H 0 Enabled

8-successive

4-successive

1 Enabled 0 Disabled

1 Self-refresh 0

CBR-refresh

1 2.0 0 1.0

1 #BSL 0 A0

1 Existing 0 Nonexistent

1 Enabled 0 Disabled

1 EDO 0 Fast page

R/W

–

R/W

–

R/W

Writing 1 not allowed.

004812E

(HW)

RCA[1:0] Size

RRA[1:0] Number of cycles

Bus control

4 PERIPHERAL CIRCUITS

A-42 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

1 Successive 0 Normal

–

A3EEN

CEFUNC1

CEFUNC0

CRAS

RPRC1

RPRC0

–

CASC1

CASC0

–

RASC1

RASC0

DF–C

reserved

Area 3 emulation

#CE pin function selection

Successive RAS mode setup

DRAM

RAS precharge cycles selection

reserved

DRAM

CAS cycles selection

reserved

DRAM

RAS cycles selection

– –

–

R/W

–

R/W

–

R/W

0 when being read.

0048130

(HW)

CFFUNC[1:0]

#CE output

#CE7/8..#CE17/18

#CE6..#CE17

#CE4..#CE10

RPRC[1:0] Number of cycles

–

CASC[1:0] Number of cycles

–

RASC[1:0] Number of cycles

DRAM timing

set-up register 1

Internal ROM

0 Emulation

–

1 Internal

access 0 External

access

1 Internal

access 0 External

access

1 Big endian 0

Little endian

A18IO

A16IO

A14IO

A12IO

–

A8IO

A6IO

A5IO

A18EC

A16EC

A14EC

A12EC

A10EC

A8EC

A6EC

A5EC

Area 18, 17 internal/external access

Area 16, 15 internal/external access

Area 14, 13 internal/external access

Area 12, 11 internal/external access

reserved

Area 8, 7 internal/external

access

Area 6 internal/external

access

Area 5, 4 internal/external

access

Area 18, 17 endian control

Area 16, 15 endian control

Area 14, 13 endian control

Area 12, 11 endian control

Area 10, 9 endian control

Area 8, 7 endian control

Area 6 endian control

Area 5, 4 endian control

R/W

–

R/W

0 when being read.

0048132

(HW)

Access control

TTBR15

TTBR14

TTBR13

TTBR12

TTBR11

TTBR10

TTBR09

TTBR08

TTBR07

TTBR06

TTBR05

TTBR04

TTBR03

TTBR02

TTBR01

TTBR00

Trap table base address [15:10]

Trap table base address [9:0] Fixed at 0

R/W

R0 when being read.

Writing 1 not allowed.

0048134

(HW)

TTBR low-

order register

TTBR33

TTBR32

TTBR31

TTBR30

TTBR2B

TTBR2A

TTBR29

TTBR28

TTBR27

TTBR26

TTBR25

TTBR24

TTBR23

TTBR22

TTBR21

TTBR20

Trap table base address [31:28]

Trap table base address [27:16]

Fixed at 0

0x0C0

R/W

0 when being read.

Writing 1 not allowed.

0048136

(HW)

TTBR high-

order register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-43

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

1 Enabled 0 Disabled

A18AS

A16AS

A14AS

A12AS

–

A8AS

A6AS

A5AS

A18RD

A16RD

A14RD

A12RD

–

A8RD

A6RD

A5RD

Area 18, 17 address strobe signal

Area 16, 15 address strobe signal

Area 14, 13 address strobe signal

Area 12, 11 address strobe signal

reserved

Area 8, 7 address strobe signal

Area 6 address strobe signal

Area 5, 4 address strobe signal

Area 18, 17 read signal

Area 16, 15 read signal

Area 14, 13 read signal

Area 12, 11 read signal

reserved

Area 8, 7 read signal

Area 6 read signal

Area 5, 4 read signal

R/W

–

R/W

–

R/W

0 when being read.

0048138

(HW)

G/A read signal

control register

–

1 Enabled 0 Disabled

–

A1X1MD

–

BCLKSEL1

BCLKSEL0

D7–4

reserved

Area 1 access-speed

reserved

BCLK output clock selection 1

BCLKSEL[1:0]

–

–BCLK

PLL_CLK

OSC3_CLK

BCU_CLK

CPU_CLK

–

R/W

–

R/W

0 when being read.

x2 speed mode only

0 when being read.

004813A

(B)

BCLK select

4 PERIPHERAL CIRCUITS

A-44 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR0A15

CR0A14

CR0A13

CR0A12

CR0A11

CR0A10

CR0A9

CR0A8

CR0A7

CR0A6

CR0A5

CR0A4

CR0A3

CR0A2

CR0A1

CR0A0

16-bit timer 0 comparison data A

CR0A15 = MSB

CR0A0 = LSB

R/W0048180

(HW)

16-bit timer 0

comparison

0 to 65535CR0B15

CR0B14

CR0B13

CR0B12

CR0B11

CR0B10

CR0B9

CR0B8

CR0B7

CR0B6

CR0B5

CR0B4

CR0B3

CR0B2

CR0B1

CR0B0

16-bit timer 0 comparison data B

CR0B15 = MSB

CR0B0 = LSB

R/W0048182

(HW)

16-bit timer 0

comparison

0 to 65535TC015

TC014

TC013

TC012

TC011

TC010

TC09

TC08

TC07

TC06

TC05

TC04

TC03

TC02

TC01

TC00

16-bit timer 0 counter data

TC015 = MSB

TC00 = LSB

R0048184

(HW)

16-bit timer 0

counter data

–

SELFM0

SELCRB0

OUTINV0

CKSL0

PTM0

PRESET0

PRUN0

reserved

16-bit timer 0 fine mode selection

16-bit timer 0 comparison buffer

16-bit timer 0 output inversion

16-bit timer 0 input clock selection

16-bit timer 0 clock output control

16-bit timer 0 reset

16-bit timer 0 Run/Stop control

–

R/W

0 when being read.

0048186

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 0

control register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-45

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR1A15

CR1A14

CR1A13

CR1A12

CR1A11

CR1A10

CR1A9

CR1A8

CR1A7

CR1A6

CR1A5

CR1A4

CR1A3

CR1A2

CR1A1

CR1A0

16-bit timer 1 comparison data A

CR1A15 = MSB

CR1A0 = LSB

R/W0048188

(HW)

16-bit timer 1

comparison

0 to 65535CR1B15

CR1B14

CR1B13

CR1B12

CR1B11

CR1B10

CR1B9

CR1B8

CR1B7

CR1B6

CR1B5

CR1B4

CR1B3

CR1B2

CR1B1

CR1B0

16-bit timer 1 comparison data B

CR1B15 = MSB

CR1B0 = LSB

R/W004818A

(HW)

16-bit timer 1

comparison

0 to 65535TC115

TC114

TC113

TC112

TC111

TC110

TC19

TC18

TC17

TC16

TC15

TC14

TC13

TC12

TC11

TC10

16-bit timer 1 counter data

TC115 = MSB

TC10 = LSB

R004818C

(HW)

16-bit timer 1

counter data

–

SELFM1

SELCRB1

OUTINV1

CKSL1

PTM1

PRESET1

PRUN1

reserved

16-bit timer 1 fine mode selection

16-bit timer 1 comparison buffer

16-bit timer 1 output inversion

16-bit timer 1 input clock selection

16-bit timer 1 clock output control

16-bit timer 1 reset

16-bit timer 1 Run/Stop control

–

R/W

0 when being read.

004818E

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 1

control register

4 PERIPHERAL CIRCUITS

A-46 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR2A15

CR2A14

CR2A13

CR2A12

CR2A11

CR2A10

CR2A9

CR2A8

CR2A7

CR2A6

CR2A5

CR2A4

CR2A3

CR2A2

CR2A1

CR2A0

16-bit timer 2 comparison data A

CR2A15 = MSB

CR2A0 = LSB

R/W0048190

(HW)

16-bit timer 2

comparison

0 to 65535CR2B15

CR2B14

CR2B13

CR2B12

CR2B11

CR2B10

CR2B9

CR2B8

CR2B7

CR2B6

CR2B5

CR2B4

CR2B3

CR2B2

CR2B1

CR2B0

16-bit timer 2 comparison data B

CR2B15 = MSB

CR2B0 = LSB

R/W0048192

(HW)

16-bit timer 2

comparison

0 to 65535TC215

TC214

TC213

TC212

TC211

TC210

TC29

TC28

TC27

TC26

TC25

TC24

TC23

TC22

TC21

TC20

16-bit timer 2 counter data

TC215 = MSB

TC20 = LSB

R0048194

(HW)

16-bit timer 2

counter data

–

SELFM2

SELCRB2

OUTINV2

CKSL2

PTM2

PRESET2

PRUN2

reserved

16-bit timer 2 fine mode selection

16-bit timer 2 comparison buffer

16-bit timer 2 output inversion

16-bit timer 2 input clock selection

16-bit timer 2 clock output control

16-bit timer 2 reset

16-bit timer 2 Run/Stop control

–

R/W

0 when being read.

0048196

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 2

control register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-47

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR3A15

CR3A14

CR3A13

CR3A12

CR3A11

CR3A10

CR3A9

CR3A8

CR3A7

CR3A6

CR3A5

CR3A4

CR3A3

CR3A2

CR3A1

CR3A0

16-bit timer 3 comparison data A

CR3A15 = MSB

CR3A0 = LSB

R/W0048198

(HW)

16-bit timer 3

comparison

0 to 65535CR3B15

CR3B14

CR3B13

CR3B12

CR3B11

CR3B10

CR3B9

CR3B8

CR3B7

CR3B6

CR3B5

CR3B4

CR3B3

CR3B2

CR3B1

CR3B0

16-bit timer 3 comparison data B

CR3B15 = MSB

CR3B0 = LSB

R/W004819A

(HW)

16-bit timer 3

comparison

0 to 65535TC315

TC314

TC313

TC312

TC311

TC310

TC39

TC38

TC37

TC36

TC35

TC34

TC33

TC32

TC31

TC30

16-bit timer 3 counter data

TC315 = MSB

TC30 = LSB

R004819C

(HW)

16-bit timer 3

counter data

–

SELFM3

SELCRB3

OUTINV3

CKSL3

PTM3

PRESET3

PRUN3

reserved

16-bit timer 3 fine mode selection

16-bit timer 3 comparison buffer

16-bit timer 3 output inversion

16-bit timer 3 input clock selection

16-bit timer 3 clock output control

16-bit timer 3 reset

16-bit timer 3 Run/Stop control

–

R/W

0 when being read.

004819E

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 3

control register

4 PERIPHERAL CIRCUITS

A-48 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR4A15

CR4A14

CR4A13

CR4A12

CR4A11

CR4A10

CR4A9

CR4A8

CR4A7

CR4A6

CR4A5

CR4A4

CR4A3

CR4A2

CR4A1

CR4A0

16-bit timer 4 comparison data A

CR4A15 = MSB

CR4A0 = LSB

R/W00481A0

(HW)

16-bit timer 4

comparison

0 to 65535CR4B15

CR4B14

CR4B13

CR4B12

CR4B11

CR4B10

CR4B9

CR4B8

CR4B7

CR4B6

CR4B5

CR4B4

CR4B3

CR4B2

CR4B1

CR4B0

16-bit timer 4 comparison data B

CR4B15 = MSB

CR4B0 = LSB

R/W00481A2

(HW)

16-bit timer 4

comparison

0 to 65535TC415

TC414

TC413

TC412

TC411

TC410

TC49

TC48

TC47

TC46

TC45

TC44

TC43

TC42

TC41

TC40

16-bit timer 4 counter data

TC415 = MSB

TC40 = LSB

R00481A4

(HW)

16-bit timer 4

counter data

–

SELFM4

SELCRB4

OUTINV4

CKSL4

PTM4

PRESET4

PRUN4

reserved

16-bit timer 4 fine mode selection

16-bit timer 4 comparison buffer

16-bit timer 4 output inversion

16-bit timer 4 input clock selection

16-bit timer 4 clock output control

16-bit timer 4 reset

16-bit timer 4 Run/Stop control

–

R/W

0 when being read.

00481A6

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 4

control register

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-49

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR5A15

CR5A14

CR5A13

CR5A12

CR5A11

CR5A10

CR5A9

CR5A8

CR5A7

CR5A6

CR5A5

CR5A4

CR5A3

CR5A2

CR5A1

CR5A0

16-bit timer 5 comparison data A

CR5A15 = MSB

CR5A0 = LSB

R/W00481A8

(HW)

16-bit timer 5

comparison

0 to 65535CR5B15

CR5B14

CR5B13

CR5B12

CR5B11

CR5B10

CR5B9

CR5B8

CR5B7

CR5B6

CR5B5

CR5B4

CR5B3

CR5B2

CR5B1

CR5B0

16-bit timer 5 comparison data B

CR5B15 = MSB

CR5B0 = LSB

R/W00481AA

(HW)

16-bit timer 5

comparison

0 to 65535TC515

TC514

TC513

TC512

TC511

TC510

TC59

TC58

TC57

TC56

TC55

TC54

TC53

TC52

TC51

TC50

16-bit timer 5 counter data

TC515 = MSB

TC50 = LSB

R00481AC

(HW)

16-bit timer 5

counter data

–

SELFM5

SELCRB5

OUTINV5

CKSL5

PTM5

PRESET5

PRUN5

reserved

16-bit timer 5 fine mode selection

16-bit timer 5 comparison buffer

16-bit timer 5 output inversion

16-bit timer 5 input clock selection

16-bit timer 5 clock output control

16-bit timer 5 reset

16-bit timer 5 Run/Stop control

–

R/W

0 when being read.

00481AE

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 5

control register

4 PERIPHERAL CIRCUITS

A-50 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

DBASEL15

DBASEL14

DBASEL13

DBASEL12

DBASEL11

DBASEL10

DBASEL9

DBASEL8

DBASEL7

DBASEL6

DBASEL5

DBASEL4

DBASEL3

DBASEL2

DBASEL1

DBASEL0

IDMA base address

low-order 16 bits

(Initial value: 0x0C003A0)

R/W0048200

(HW)

IDMA base

address low-

order register

––

DBASEH11

DBASEH10

DBASEH9

DBASEH8

DBASEH7

DBASEH6

DBASEH5

DBASEH4

DBASEH3

DBASEH2

DBASEH1

DBASEH0

DF–C

reserved

IDMA base address

high-order 12 bits

(Initial value: 0x0C003A0)

–

R/W Undefined in read.0048202

(HW)

IDMA base

address

high-order

0 to 127

DSTART

DCHN

D6–0 IDMA start

IDMA channel number 1 IDMA start 0 Stop 0

0R/W

R/W

0048204

(B)

IDMA start

––

IDMAEN

D7–1

D0 reserved

IDMA enable 1 Enabled 0 Disabled –

0–

R/W

0048205

(B)

IDMA enable

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-51

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TC0_L7

TC0_L6

TC0_L5

TC0_L4

TC0_L3

TC0_L2

TC0_L1

TC0_L0

BLKLEN07

BLKLEN06

BLKLEN05

BLKLEN04

BLKLEN03

BLKLEN02

BLKLEN01

BLKLEN00

Ch.0 transfer c

ounter[7:0]

(block transfer mode)

Ch.0 transfer counter[15:8]

(single/successive transfer mode)

Ch.0 block length

(block transfer mode)

Ch.0 transfer counter[7:0]

(single/successive transfer mode)

R/W

0048220

(HW)

High-speed

DMA Ch.0

transfer

counter

–

DUALM0

D0DIR

–

TC0_H7

TC0_H6

TC0_H5

TC0_H4

TC0_H3

TC0_H2

TC0_H1

TC0_H0

DD–8

Ch.0 address mode selection

D) Invalid

S) Ch.0 transfer direction control

reserved

Ch.0 transfer counter[15:8]

(block transfer mode)

Ch.0 transfer counter[23:16]

(single/successive transfer mode)

1 Dual addr 0 Single addr

Memory WR

Memory RD

–

R/W

–

R/W

–

R/W Undefined in read.

0048222

(HW)

High-speed

DMA Ch.0

control register

Note:

D) Dual address

mode

S) Single

address

mode

S0ADRL15

S0ADRL14

S0ADRL13

S0ADRL12

S0ADRL11

S0ADRL10

S0ADRL9

S0ADRL8

S0ADRL7

S0ADRL6

S0ADRL5

S0ADRL4

S0ADRL3

S0ADRL2

S0ADRL1

S0ADRL0

D) Ch.0 source address[15:0]

S) Ch.0 memory address[15:0] X

R/W0048224

(HW)

High-speed

DMA Ch.0

low-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

–

DATSIZE0

S0IN1

S0IN0

S0ADRH11

S0ADRH10

S0ADRH9

S0ADRH8

S0ADRH7

S0ADRH6

S0ADRH5

S0ADRH4

S0ADRH3

S0ADRH2

S0ADRH1

S0ADRH0

reserved

Ch.0 transfer data size

D) Ch.0 source address control

S) Ch.0 memory address control

D) Ch.0 source address[27:16]

S) Ch.0 memory address[27:16]

–

R/W

0048226

(HW) 1 Half word 0 Byte

High-speed

DMA Ch.0

high-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

S0IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

–

4 PERIPHERAL CIRCUITS

A-52 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D0ADRL15

D0ADRL14

D0ADRL13

D0ADRL12

D0ADRL11

D0ADRL10

D0ADRL9

D0ADRL8

D0ADRL7

D0ADRL6

D0ADRL5

D0ADRL4

D0ADRL3

D0ADRL2

D0ADRL1

D0ADRL0

D) Ch.0 destination address[15:0]

S) Invalid X

R/W0048228

(HW)

High-speed

DMA Ch.0

low-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D0MOD1

D0MOD0

D0IN1

D0IN0

D0ADRH11

D0ADRH10

D0ADRH9

D0ADRH8

D0ADRH7

D0ADRH6

D0ADRH5

D0ADRH4

D0ADRH3

D0ADRH2

D0ADRH1

D0ADRH0

Ch.0 transfer mode

D) Ch.0 destination address

control

S) Invalid

D) Ch.0 destination

address[27:16]

S) Invalid

R/W

004822A

(HW)

High-speed

DMA Ch.0

high-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D0MOD[1:0] Mode

Invalid

Block

Successive

Single

D0IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

––

HS0_EN

DF–1

reserved

Ch.0 enable 1 Enable 0 Disable

–

R/W

Undefined in read.004822C

(HW)

High-speed

DMA Ch.0

enable register

––

HS0_TF

DF–1

reserved

Ch.0 trigger flag clear (writing)

Ch.0 trigger flag status (reading) 1 Clear 0

No operation

1 Set 0 Cleared

–

R/W

Undefined in read.004822E

(HW)

High-speed

DMA Ch.0

trigger flag

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-53

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TC1_L7

TC1_L6

TC1_L5

TC1_L4

TC1_L3

TC1_L2

TC1_L1

TC1_L0

BLKLEN17

BLKLEN16

BLKLEN15

BLKLEN14

BLKLEN13

BLKLEN12

BLKLEN11

BLKLEN10

Ch.1 transfer c

ounter[7:0]

(block transfer mode)

Ch.1 transfer counter[15:8]

(single/successive transfer mode)

Ch.1 block length

(block transfer mode)

Ch.1 transfer counter[7:0]

(single/successive transfer mode)

R/W

0048230

(HW)

High-speed

DMA Ch.1

transfer

counter

–

DUALM1

D1DIR

–

TC1_H7

TC1_H6

TC1_H5

TC1_H4

TC1_H3

TC1_H2

TC1_H1

TC1_H0

DD–8

Ch.1 address mode selection

D) Invalid

S) Ch.1 transfer direction control

reserved

Ch.1 transfer counter[15:8]

(block transfer mode)

Ch.1 transfer counter[23:16]

(single/successive transfer mode)

1 Dual addr 0 Single addr

Memory WR

Memory RD

–

R/W

–

R/W

–

R/W Undefined in read.

0048232

(HW)

High-speed

DMA Ch.1

control register

Note:

D) Dual address

mode

S) Single

address

mode

S1ADRL15

S1ADRL14

S1ADRL13

S1ADRL12

S1ADRL11

S1ADRL10

S1ADRL9

S1ADRL8

S1ADRL7

S1ADRL6

S1ADRL5

S1ADRL4

S1ADRL3

S1ADRL2

S1ADRL1

S1ADRL0

D) Ch.1 source address[15:0]

S) Ch.1 memory address[15:0] X

R/W0048234

(HW)

High-speed

DMA Ch.1

low-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

–

DATSIZE1

S1IN1

S1IN0

S1ADRH11

S1ADRH10

S1ADRH9

S1ADRH8

S1ADRH7

S1ADRH6

S1ADRH5

S1ADRH4

S1ADRH3

S1ADRH2

S1ADRH1

S1ADRH0

reserved

Ch.1 transfer data size

D) Ch.1 source address control

S) Ch.1 memory address control

D) Ch.1 source address[27:16]

S) Ch.1 memory address[27:16]

–

R/W

0048236

(HW) 1 Half word 0 Byte

High-speed

DMA Ch.1

high-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

S1IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

–

4 PERIPHERAL CIRCUITS

A-54 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D1ADRL15

D1ADRL14

D1ADRL13

D1ADRL12

D1ADRL11

D1ADRL10

D1ADRL9

D1ADRL8

D1ADRL7

D1ADRL6

D1ADRL5

D1ADRL4

D1ADRL3

D1ADRL2

D1ADRL1

D1ADRL0

D) Ch.1 destination address[15:0]

S) Invalid X

R/W0048238

(HW)

High-speed

DMA Ch.1

low-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D1MOD1

D1MOD0

D1IN1

D1IN0

D1ADRH11

D1ADRH10

D1ADRH9

D1ADRH8

D1ADRH7

D1ADRH6

D1ADRH5

D1ADRH4

D1ADRH3

D1ADRH2

D1ADRH1

D1ADRH0

Ch.1 transfer mode

D) Ch.1 destination address

control

S) Invalid

D) Ch.1 destination

address[27:16]

S) Invalid

R/W

004823A

(HW)

High-speed

DMA Ch.1

high-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D1MOD[1:0] Mode

Invalid

Block

Successive

Single

D1IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

––

HS1_EN

DF–1

reserved

Ch.1 enable 1 Enable 0 Disable

–

R/W

Undefined in read.004823C

(HW)

High-speed

DMA Ch.1

enable register

––

HS1_TF

DF–1

reserved

Ch.1 trigger flag clear (writing)

Ch.1 trigger flag status (reading) 1 Clear 0

No operation

1 Set 0 Cleared

–

R/W

Undefined in read.004823E

(HW)

High-speed

DMA Ch.1

trigger flag

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-55

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TC2_L7

TC2_L6

TC2_L5

TC2_L4

TC2_L3

TC2_L2

TC2_L1

TC2_L0

BLKLEN27

BLKLEN26

BLKLEN25

BLKLEN24

BLKLEN23

BLKLEN22

BLKLEN21

BLKLEN20

Ch.2 transfer c

ounter[7:0]

(block transfer mode)

Ch.2 transfer counter[15:8]

(single/successive transfer mode)

Ch.2 block length

(block transfer mode)

Ch.2 transfer counter[7:0]

(single/successive transfer mode)

R/W

0048240

(HW)

High-speed

DMA Ch.2

transfer

counter

–

DUALM2

D2DIR

–

TC2_H7

TC2_H6

TC2_H5

TC2_H4

TC2_H3

TC2_H2

TC2_H1

TC2_H0

DD–8

Ch.2 address mode selection

D) Invalid

S) Ch.2 transfer direction control

reserved

Ch.2 transfer counter[15:8]

(block transfer mode)

Ch.2 transfer counter[23:16]

(single/successive transfer mode)

1 Dual addr 0 Single addr

Memory WR

Memory RD

–

R/W

–

R/W

–

R/W Undefined in read.

0048242

(HW)

High-speed

DMA Ch.2

control register

Note:

D) Dual address

mode

S) Single

address

mode

S2ADRL15

S2ADRL14

S2ADRL13

S2ADRL12

S2ADRL11

S2ADRL10

S2ADRL9

S2ADRL8

S2ADRL7

S2ADRL6

S2ADRL5

S2ADRL4

S2ADRL3

S2ADRL2

S2ADRL1

S2ADRL0

D) Ch.2 source address[15:0]

S) Ch.2 memory address[15:0] X

R/W0048244

(HW)

High-speed

DMA Ch.2

low-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

–

DATSIZE2

S2IN1

S2IN0

S2ADRH11

S2ADRH10

S2ADRH9

S2ADRH8

S2ADRH7

S2ADRH6

S2ADRH5

S2ADRH4

S2ADRH3

S2ADRH2

S2ADRH1

S2ADRH0

reserved

Ch.2 transfer data size

D) Ch.2 source address control

S) Ch.2 memory address control

D) Ch.2 source address[27:16]

S) Ch.2 memory address[27:16]

–

R/W

0048246

(HW) 1 Half word 0 Byte

High-speed

DMA Ch.2

high-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

S2IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

–

4 PERIPHERAL CIRCUITS

A-56 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D2ADRL15

D2ADRL14

D2ADRL13

D2ADRL12

D2ADRL11

D2ADRL10

D2ADRL9

D2ADRL8

D2ADRL7

D2ADRL6

D2ADRL5

D2ADRL4

D2ADRL3

D2ADRL2

D2ADRL1

D2ADRL0

D) Ch.2 destination address[15:0]

S) Invalid X

R/W0048248

(HW)

High-speed

DMA Ch.2

low-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D2MOD1

D2MOD0

D2IN1

D2IN0

D2ADRH11

D2ADRH10

D2ADRH9

D2ADRH8

D2ADRH7

D2ADRH6

D2ADRH5

D2ADRH4

D2ADRH3

D2ADRH2

D2ADRH1

D2ADRH0

Ch.2 transfer mode

D) Ch.2 destination address

control

S) Invalid

D) Ch.2 destination

address[27:16]

S) Invalid

R/W

004824A

(HW)

High-speed

DMA Ch.2

high-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D2MOD[1:0] Mode

Invalid

Block

Successive

Single

D2IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

––

HS2_EN

DF–1

reserved

Ch.2 enable 1 Enable 0 Disable

–

R/W

Undefined in read.004824C

(HW)

High-speed

DMA Ch.2

enable register

––

HS2_TF

DF–1

reserved

Ch.2 trigger flag clear (writing)

Ch.2 trigger flag status (reading) 1 Clear 0

No operation

1 Set 0 Cleared

–

R/W

Undefined in read.004824E

(HW)

High-speed

DMA Ch.2

trigger flag

4 PERIPHERAL CIRCUITS

S1C33209/221/222 PRODUCT PART EPSON A-57

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TC3_L7

TC3_L6

TC3_L5

TC3_L4

TC3_L3

TC3_L2

TC3_L1

TC3_L0

BLKLEN37

BLKLEN36

BLKLEN35

BLKLEN34

BLKLEN33

BLKLEN32

BLKLEN31

BLKLEN30

Ch.3 transfer c

ounter[7:0]

(block transfer mode)

Ch.3 transfer counter[15:8]

(single/successive transfer mode)

Ch.3 block length

(block transfer mode)

Ch.3 transfer counter[7:0]

(single/successive transfer mode)

R/W

0048250

(HW)

High-speed

DMA Ch.3

transfer

counter

–

DUALM3

D3DIR

–

TC3_H7

TC3_H6

TC3_H5

TC3_H4

TC3_H3

TC3_H2

TC3_H1

TC3_H0

DD–8

Ch.3 address mode selection

D) Invalid

S) Ch.3 transfer direction control

reserved

Ch.3 transfer counter[15:8]

(block transfer mode)

Ch.3 transfer counter[23:16]

(single/successive transfer mode)

1 Dual addr 0 Single addr

Memory WR

Memory RD

–

R/W

–

R/W

–

R/W Undefined in read.

0048252

(HW)

High-speed

DMA Ch.3

control register

Note:

D) Dual address

mode

S) Single

address

mode

S3ADRL15

S3ADRL14

S3ADRL13

S3ADRL12

S3ADRL11

S3ADRL10

S3ADRL9

S3ADRL8

S3ADRL7

S3ADRL6

S3ADRL5

S3ADRL4

S3ADRL3

S3ADRL2

S3ADRL1

S3ADRL0

D) Ch.3 source address[15:0]

S) Ch.3 memory address[15:0] X

R/W0048254

(HW)

High-speed

DMA Ch.3

low-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

–

DATSIZE3

S3IN1

S3IN0

S3ADRH11

S3ADRH10

S3ADRH9

S3ADRH8

S3ADRH7

S3ADRH6

S3ADRH5

S3ADRH4

S3ADRH3

S3ADRH2

S3ADRH1

S3ADRH0

reserved

Ch.3 transfer data size

D) Ch.3 source address control

S) Ch.3 memory address control

D) Ch.3 source address[27:16]

S) Ch.3 memory address[27:16]

–

R/W

0048256

(HW) 1 Half word 0 Byte

High-speed

DMA Ch.3

high-order

source address

set-up register

Note:

D) Dual address

mode

S) Single

address

mode

S3IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

–

4 PERIPHERAL CIRCUITS

A-58 EPSON S1C33209/221/222 PRODUCT PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D3ADRL15

D3ADRL14

D3ADRL13

D3ADRL12

D3ADRL11

D3ADRL10

D3ADRL9

D3ADRL8

D3ADRL7

D3ADRL6

D3ADRL5

D3ADRL4

D3ADRL3

D3ADRL2

D3ADRL1

D3ADRL0

D) Ch.3 destination address[15:0]

S) Invalid X

R/W0048258

(HW)

High-speed

DMA Ch.3

low-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D3MOD1

D3MOD0

D3IN1

D3IN0

D3ADRH11

D3ADRH10

D3ADRH9

D3ADRH8

D3ADRH7

D3ADRH6

D3ADRH5

D3ADRH4

D3ADRH3

D3ADRH2

D3ADRH1

D3ADRH0

Ch.3 transfer mode

D) Ch.3 destination address

control

S) Invalid

D) Ch.3 destination

address[27:16]

S) Invalid

R/W

004825A

(HW)

High-speed

DMA Ch.3

high-order

destination

address set-up

Note:

D) Dual address

mode

S) Single

address

mode

D3MOD[1:0] Mode

Invalid

Block

Successive

Single

D3IN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

––

HS3_EN

DF–1

reserved

Ch.3 enable 1 Enable 0 Disable

–

R/W

Undefined in read.004825C

(HW)

High-speed

DMA Ch.3

enable register

––

HS3_TF

DF–1

reserved

Ch.3 trigger flag clear (writing)

Ch.3 trigger flag status (reading) 1 Clear 0

No operation

1 Set 0 Cleared

–

R/W

Undefined in read.004825E

(HW)

High-speed

DMA Ch.3

trigger flag

5 POWER-DOWN CONTROL

S1C33209/221/222 PRODUCT PART EPSON A-59

5 Power-Down Control

This chapter describes the controls used to reduce power consumption of the device.

Points on power saving

The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used,

and the peripheral circuits operated.

Current consumption low←→high

CPU/BCU SLEEP HALT2 Operating HALT2 HALT(basic) Operating

System clock – OSC1 OSC1 OSC3 OSC3 OSC3

OSC3 oscillation circuit OFF OFF OFF ON ON ON

Prescaler/peripheral circuit STOP RUN

To reduce power consumption of the device, it is important that as many unnecessary circuits as possible be

turned off. In particular, peripheral circuits operating at a fast-clock rate consume a large amount of current, so

design the program so that these circuits are turned off whenever unnecessary.

Power-saving in standby modes

When CPU processing is unnecessary, such as when waiting for an interrupt from key entries or peripheral

circuits, place the device in standby mode to reduce current consumption.

Standby mode Method to enter the mode Circuits/functions stopped

Basic HALT mode Execute the halt instruction after setting

HLT2OP (D3)/Clock option register

(0x40190) to "0".

When the #BUSREQ signal is asserted from

an external bus master while SEPD (D1)/Bus

control register (0x4812E) = "1".

CPU and DMA

HALT2 mode Execute the halt instruction after setting

HLT2OP to "1". CPU, BCU, bus clock, and DMA

SLEEP mode Execute the slp instruction. CPU, BCU, bus clock, DMA, high-speed

(OSC3) oscillation circuit, prescaler, and

peripheral circuits that use the prescaler

output clocks

HLT2OP (D3)/Clock option register (0x40190) that is used to select a HALT mode is set to "0" (basic HALT

mode) at initial reset.

Notes: • In systems in which DRAM is connected directly to the device, the refresh function is turned off

during HALT2 and SLEEP modes.

• The standby mode is cleared by interrupt generation (except for the basic HALT mode, which is

set using an external bus master). Therefore, before entering standby mode, set the related

registers to allow an interrupt to be used to clear the standby mode to be generated.

• When clearing the standby mode with an interrupt from port input, the interrupt operates as a

level interrupt regardless of the interrupt trigger setting. When edge trigger is set for the interrupt

trigger, attention must be paid to the port level during standby mode.

The low-speed (OSC1) oscillation circuit and clock timer continue operating even during SLEEP mode. If they

are unnecessary, these circuits can also be turned off.

Function Control bit "1" "0" Default

Low-speed (OSC1) oscillation ON/OFF control SOSC1(D0)/

Power control register(0x40180) ON OFF ON

5 POWER-DOWN CONTROL

A-60 EPSON S1C33209/221/222 PRODUCT PART

Switching over the system clocks

Normally, the system is clocked by the high-speed (OSC3) oscillation clock. If high-speed operation is

unnecessary, switch the system clock to the low-speed (OSC1) oscillation clock and turn off the high-speed

(OSC3) oscillation circuit. This helps to reduce current consumption. However, if DRAM is connected directly

to the device, note that the refresh function is also turned off.

Even during operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved

through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8).

Function Control bit "1" "0" Default

System clock switch over CLKCHG(D2)/

Power control register(0x40180) OSC3 OSC1 OSC3

High-speed (OSC3) oscillation ON/OFF control SOSC3(D1)/

Power control register(0x40180) ON OFF ON

System clock division ratio selection CLKDT(D[7:6])/

Power control register(0x40180) "11" = 1/8

"10" = 1/4

"01" = 1/2

"00" = 1/1

1/1

Turning off the prescaler and peripheral circuits

Current consumption can be reduced by turning off the peripheral circuits operating at high speed as much as

possible. The circuits listed below are operated using a clock generated by the prescaler:

• 16-bit programmable timers 0 to 5 (watchdog timer)

• 8-bit programmable timers 0 to 5 (DRAM refresh, serial interface)

• A/D converter

If none of these circuits need to be used, turn off the prescaler. If some of these circuits need to be used, turn off

all other unnecessary circuits and stop clock supply from the prescaler to those circuits.

Function Control bit "1" "0" Default

Prescaler ON/OFF PSCON(D5)/Power control register(0x40180) ON OFF ON

16-bit timer 0 clock control P16TON0(D3)/16-bit timer 0 clock control register(0x40147) ON OFF OFF

16-bit timer 0 Run/Stop PRUN0(D0)/16-bit timer 0 control register(0x48186) RUN STOP STOP

16-bit timer 1 clock control P16TON1(D3)/16-bit timer 1 clock control register(0x40148) ON OFF OFF

16-bit timer 1 Run/Stop PRUN1(D0)/16-bit timer 1 control register(0x4818E) RUN STOP STOP

16-bit timer 2 clock control P16TON2(D3)/16-bit timer 2 clock control register(0x40149) ON OFF OFF

16-bit timer 2 Run/Stop PRUN2(D0)/16-bit timer 2 control register(0x48196) RUN STOP STOP

16-bit timer 3 clock control P16TON3(D3)/16-bit timer 3 clock control register(0x4014A) ON OFF OFF

16-bit timer 3 Run/Stop PRUN3(D0)/16-bit timer 3 control register(0x4819E) RUN STOP STOP

16-bit timer 4 clock control P16TON4(D3)/16-bit timer 4 clock control register(0x4014B) ON OFF OFF

16-bit timer 4 Run/Stop PRUN4(D0)/16-bit timer 4 control register(0x481A6) RUN STOP STOP

16-bit timer 5 clock control P16TON5(D3)/16-bit timer 5 clock control register(0x4014C) ON OFF OFF

16-bit timer 5 Run/Stop PRUN5(D0)/16-bit timer 5 control register(0x481AE) RUN STOP STOP

8-bit timer 0 clock control P8TON0(D3)/8-bit timer 0/1 clock control register(0x4014D) ON OFF OFF

8-bit timer 0 Run/Stop PTRUN0(D0)/8-bit timer 0 control register(0x40160) RUN STOP STOP

8-bit timer 1 clock control P8TON1(D7)/8-bit timer 0/1 clock control register(0x4014D) ON OFF OFF

8-bit timer 1 Run/Stop PTRUN1(D0)/8-bit timer 1 control register(0x40164) RUN STOP STOP

8-bit timer 2 clock control P8TON2(D3)/8-bit timer 2/3 clock control register(0x4014E) ON OFF OFF

8-bit timer 2 Run/Stop PTRUN2(D0)/8-bit timer 2 control register(0x40168) RUN STOP STOP

8-bit timer 3 clock control P8TON3(D7)/8-bit timer 2/3 clock control register(0x4014E) ON OFF OFF

8-bit timer 3 Run/Stop PTRUN3(D0)/8-bit timer 3 control register(0x4016C) RUN STOP STOP

8-bit timer 4 clock control P8TON4(D3)/8-bit timer 4/5 clock control register(0x40145) ON OFF OFF

8-bit timer 4 Run/Stop PTRUN4(D0)/8-bit timer 4 control register(0x40174) RUN STOP STOP

8-bit timer 5 clock control P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) ON OFF OFF

8-bit timer 5 Run/Stop PTRUN5(D0)/8-bit timer 5 control register(0x40178) RUN STOP STOP

A/D converter clock control PSONAD(D3)/A/D clock control register(0x4014F) ON OFF OFF

A/D conversion enable ADE(D2)/A/D enable register(0x40244) RUN STOP STOP

5 POWER-DOWN CONTROL

S1C33209/221/222 PRODUCT PART EPSON A-61

The same clock source must be used for the prescaler operating clock and the CPU operating clock. Therefore,

when operating the CPU in low-speed with the OSC1 clock, the prescaler input clock must be switched

according to the CPU operating clock. In this case, in order to prevent a malfunction in the peripheral circuit,

the prescaler should be turned off before switching the CPU operating clock. After the CPU operating clock has

been switched, switch the prescaler operating clock and then turn the prescaler on.

Function Control bit "1" "0" Default

Prescaler operating clock

switch over PSCDT0 (D0)/Prescaler clock select register(0x40181) OSC1 OSC3/

PLL OSC3/

PLL

6 BASIC EXTERNAL WIRING DIAGRAM

A-62 EPSON S1C33209/221/222 PRODUCT PART

6 Basic External Wiring Diagram

S1C33209/221/222

[The potential of the substrate

(back of the chip) is VSS.]

External

Bus

HSDMA

Serial I/O

A/D input

Input

I/O

Timer

input/output

X'tal1

CG1

CD1

Rf1

X'tal2

CG2

CD2

Rf2

Crystal oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Crystal oscillator

Ceramic oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Resistor

Capacitor

32.768 kHz, CI(Max.) = 34 kΩ

10 pF

10 MΩ

33 MHz (Max.)

10 pF

1 MΩ

4.7 kΩ

100 pF

5 pF

Note: The above table is simply an example, and is not guaranteed to work.

∗1: When the PLL is not used,

leave the PLLC pin open.

VDD

VDDE

AVDDE

DSIO

ICEMD

EA3MD

EA10MD0

EA10MD1

#X2SPD

PLLC

PLLS0

PLLS1

OSC3

OSC4

OSC1

OSC2

#RESET

VSS

CD2

3.3V

X'tal2

CR Rf

A[23:0]

D[15:0]

#RD

#EMEMRD

#DRD

#GARD

#GAAS

#WRL/#WR/#WE

#WRH/#BSH

#DWR

#HCAS

#LCAS

#CExx/#RASx

#CE10EX

#CE10IN

#WAIT

BCLK

#BUSREQ

#BUSACK

#BUSGET

#NMI

#DMAREQx

#DMAACKx

#DMAENDx

SINx

SOUTx

#SCLKx

#SRDYx

#ADTRG

ADx

EXCLx

TMx

T8UFx

Kxx

Pxx

CG2

∗1

CD1

X'tal1 Rf1CG1

7 PRECAUTIONS ON MOUNTING

S1C33209/221/222 PRODUCT PART EPSON A-63

7 Precautions on Mounting

The following shows the precautions when designing the board and mounting the IC.

Oscillation Circuit

• Oscillation characteristics change depending on conditions (board pattern, components used, etc.).

In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's

recommended values for constants such as capacitance and resistance.

• Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to

prevent this:

(1) Components which are connected to the OSC3 (OSC1), OSC4 (OSC2) and PLLC pins, such as oscillators,

resistors and capacitors, should be connected in the shortest line.

(2) As shown in the figure below, make a V SS pattern as large as possible at circumscription of the OSC3

(OSC1) and OSC4 (OSC2) pins and the components connected to these pins. The same applies to the

PLLC pin.

Furthermore, do not use this VSS pattern to connect other components than the oscillation system.

OSC4

OSC3

Sample V

pattern

OSC3 and OSC4

PLLC

(3) When supplying an external clock to the OSC3 (OSC1) pin, the clock source should be connected to the

OSC3 (OSC1) pin in the shortest line.

Furthermore, do not connect anything else to the OSC4 (OSC2) pin.

• In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 (OSC1) and

VDD, please keep enough distance between OSC3 (OSC1) and V DD or other signals on the board pattern.

Reset Circuit

• The power-on reset signal which is input to the #RESET pin changes depending on conditions (power rise time,

components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests

have been completed with the application product.

• In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components

such as capacitors and resistors should be connected to the #RESET pin in the shortes t line.

Power Supply Circuit

• Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent

this:

(1) The power supply should be connected to the V DD, V DDE, V SS and AVDDE pins with patterns as short and

large as possible.

In particular, the power supply for AVDDE affects A/D conversion precision.

7 PRECAUTIONS ON MOUNTING

A-64 EPSON S1C33209/221/222 PRODUCT PART

(2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as

short as possible.

VDD

VSS

Bypass capacitor connection example

VDD

VSS

A/D Converter

• When the A/D converter is not used, the power supply pin AVDDE for the analog system should be connected to

VDDE.

Arrangement of Signal Lines

• In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange

a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input

unit.

• When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may

generated by mutual interference between the signals and it may cause a malfunction.

Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation

unit and analog input unit.

K60 (AD0)

Large current signal line

High-speed signal line

OSC4

OSC3

VSS

Large current signal line

High-speed signal line

Prohibited pattern

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-65

8 Electrical Characteristics

8.1 Absolute Maximum Rating

(VSS=0V)

Item Symbol Condition Rated value Unit ∗

Supply voltage VDD -0.3 to +4.0 V

C33 I/O power voltage VDDE1 -0.3 to +7.0 V

Input voltage VI-0.3 to VDDE+0.5 V

High-level output current IOH 1 pin -10 mA

Total of all pins -40 mA

Low-level output current IOL 1 pin 10 mA

Total of all pins 40 mA

Analog power voltage AVDDE -0.3 to +7.0 V

Analog input voltage AVIN -0.3 to AVDDE+0.3 V

Storage temperature TSTG -65 to +150 °C

8 ELECTRICAL CHARACTERISTICS

A-66 EPSON S1C33209/221/222 PRODUCT PART

8.2 Recommended Operating Conditions

1) 3.3 V/5.0 V dual power source (VSS=0V)

Item Symbol Condition Min. Typ. Max. Unit ∗

Supply voltage (high voltage) VDDE 4.50 5.00 5.50 V

Supply voltage (low voltage) VDD 2.70 – 3.60 V

Input voltage HVIVSS –VDDE V

LVIVSS –VDD V

CPU operating clock frequency fCPU – – 50 MHz

Low-speed oscillation frequency fOSC1 – 32.768 – kHz

Operating temperature Ta -40 25 85 °C

Input rise time (normal input) tri – – 50 ns

Input fall time (normal input) tfi – – 50 ns

Input rise time (schmitt input) tri – – 5 ms

Input fall time (schmitt input) tfi – – 5 ms

2) 3.3 V single power source (VDDE=VDD, VSS=0V)

Item Symbol Condition Min. Typ. Max. Unit ∗

Supply voltage VDD 2.70 – 3.60 V

Input voltage VIVSS –VDD V

CPU operating clock frequency fCPU – – 50 MHz

Low-speed oscillation frequency fOSC1 – 32.768 – kHz

Operating temperature Ta -40 25 85 °C

Input rise time (normal input) tri – – 50 ns

Input fall time (normal input) tfi – – 50 ns

Input rise time (schmitt input) tri – – 5 ms

Input fall time (schmitt input) tfi – – 5 ms

3) 2.0 V single power source (VDDE=VDD, VSS=0V)

Item Symbol Condition Min. Typ. Max. Unit ∗

Supply voltage VDD 1.80 2.00 2.20 V

Input voltage VIVSS –VDD V

CPU operating clock frequency fCPU – – 20 MHz

Low-speed oscillation frequency fOSC1 – 32.768 – kHz

Operating temperature Ta -40 25 85 °C

Input rise time (normal input) tri – – 100 ns

Input fall time (normal input) tfi – – 100 ns

Input rise time (schmitt input) tri – – 10 ms

Input fall time (schmitt input) tfi – – 10 ms

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-67

8.3 DC Characteristics

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Input leakage current ILI -1 – 1 µA

Off-state leakage current IOZ -1 – 1 µA

High-level output voltage VOH IOH=-3mA (Type1), IOH=-12mA (Type3),

VDDE=Min. VDDE

-0.4 ––V

Low-level output voltage VOL IOL=3mA (Type1), IOL=12mA (Type3),

VDDE=Min. – – 0.4 V

High-level input voltage VIH CMOS level, VDDE=Max. 3.5 – – V

Low-level input voltage VIL CMOS level, VDDE=Min. – – 1.0 V

Positive trigger input voltage V T+ CMOS schmitt 2.0 – 4.0 V

Negative trigger input voltage VT- CMOS schmitt 0.8 – 3.1 V

Hysteresis voltage VHCMOS schmitt 0.3 – – V

High-level input voltage VIH2 TTI level, VDDE=Max. 2.0 – – V

Low-level input voltage VIL2 TTL level, VDDE=Min. – – 0.8 V

Pull-up resistor RPU VI=0V 60 120 288 kΩ

Pull-down resistor RPD VI=VDDE (#ICEMD) 30 60 144 kΩ

Input pin capacitance CIf=1MHz, VDDE=0V – – 10 pF

Output pin capacitance COf=1MHz, VDDE=0V – – 10 pF

I/O pin capacitance CIO f=1MHz, VDDE=0V – – 10 pF

2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Static current consumption I DDS Static s tate, Tj=85°C––90µA

Input leakage current ILI -1 – 1 µA

Off-state leakage current IOZ -1 – 1 µA

High-level output voltage VOH IOH=-2mA (Type1), IOH=-6mA (Type2),

IOH=-12mA (Type3), VDD=Min. VDD

-0.4 ––V

Low-level output voltage VOL IOL=2mA (Type1), IOL=6mA (Type2),

IOL=12mA (Type3), VDD=Min. – – 0.4 V

High-level input voltage VIH CMOS level, VDD=Max. 2.4 – – V

Low-level input voltage VIL CMOS level, V DD=Min. – – 0.4 V

Positive trigger input voltage V T+ LVTTL schmitt 1.1 – 2.4 V

Negative trigger input voltage VT- LVTTL schmitt 0.6 – 1.8 V

Hysteresis voltage VHLVTTL schmitt 0.1 – – V

Pull-up resistor RPU VI=0V Other than DSIO 80 200 480 kΩ

DSIO 40 100 240 kΩ

Pull-down resistor RPD VI=VDD (#ICEMD) 40 100 240 kΩ

Input pin capacitance CIf=1MHz, VDD=0V – – 10 pF

Output pin capacitance COf=1MHz, VDD=0V – – 10 pF

I/O pin capacitance CIO f=1MHz, VDD=0V – – 10 pF

Note:See Appendix B for pin characteristics.

8 ELECTRICAL CHARACTERISTICS

A-68 EPSON S1C33209/221/222 PRODUCT PART

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2V±0.2V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Static current consumption I DDS Static state, T j=85°C––80µA

Input leakage current ILI -1 – 1 µA

Off-state leakage current IOZ -1 – 1 µA

High-level output voltage VOH IOH=-0.6mA (Type1), IOH=-2mA (Type2),

IOH=-4mA (Type3), VDD=Min. VDD

-0.2 ––V

Low-level output voltage VOL IOL=0.6mA (Type1), IOL=2mA (Type2), IOL=4mA

(Type3), VDD=Min. – – 0.2 V

High-level input voltage VIH CMOS level, VDD=Max. 1.6 – – V

Low-level input voltage VIL CMOS level, V DD=Min. – – 0.3 V

Positive trigger input voltage V T+ CMOS schmitt 0.4 – 1.6 V

Negative trigger input voltage VT- CMOS schmitt 0.3 – 1.4 V

Hysteresis voltage VHCMOS schmitt 0––V

Pull-up resistor RPU VI=0V Other than DSIO 120 480 1200 kΩ

DSIO 60 240 600 kΩ

Pull-down resistor RPD VI=VDD (#ICEMD) 60 240 600 kΩ

Input pin capacitance CIf=1MHz, VDD=0V – – 10 pF

Output pin capacitance COf=1MHz, VDD=0V – – 10 pF

I/O pin capacitance CIO f=1MHz, VDD=0V – – 10 pF

Note:See Appendix B for pin characteristics.

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-69

8.4 Current Consumption

1) 3.3 V power source

(Unless otherwise specified: VDDE=2.7V to 5.5V, V DD=2.7V to 3.6V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Operating current IDD1 When CPU is operating 20MHz – 25 35 mA 1

33MHz – 45 60

50MHz – 60 85

IDD2 HALT mode 20MHz – 13 16 mA 2

33MHz – 23 30

50MHz – 30 45

IDD3 HALT2 mode 20MHz – 4 7 mA 3

33MHz – 6 10

50MHz – 8 13

IDD4 SLEEP mode – 1 30 µA4

Clock timer operating current IDDCT When clock timer only is operating

OSC1 oscillation: 32kHz –7–µA5

2) 2.0 V power source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Operating current IDD1 When CPU is operating, 20MHz – 12 17 mA 1

IDD2 HALT mode, 20MHz – 7 10 mA 2

IDD3 HALT2 mode, 20MHz – 1.8 2.5 mA 3

IDD4 SLEEP mode – 1 30 µA4

Clock timer operating current IDDCT When clock timer only is operating

OSC1 oscillation: 32kHz – 1.5 – µA5

3) Analog power current (Unless otherwise specified: VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

A/D converter operating current AI DD1 VDD=3.6V, VDDE=AVDD=5.0V±0.5V – 800 1400 µA6

VDD=VDDE=AVDD=2.7V to 3.6V – 500 800

Current consumption measurement condition: VIH=VDD, V IL=0V, output pins are open, VDDE current is not included

∗ note) No. OSC3 OSC1 CPU Clock timer Other peripheral circuits

1 On Off Normal operation ∗1 Stop Stop

2 On Off HALT mode Stop Stop

3 On Off HALT2 mode Stop Stop

4 Off Off SLEEP mode Stop Stop

5 Off On HALT mode Run Stop

6 On Off HALT mode Stop A/D converter only operated,

conversion clock frequency=2MHz

∗1:The values of current consumption while the CPU is operating were measured when a test program that

consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch

instructions and 9% ext instruction is being executed in the built-in ROM continuously.

8 ELECTRICAL CHARACTERISTICS

A-70 EPSON S1C33209/221/222 PRODUCT PART

8.5 A/D Converter Characteristics

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=AVDD=4.5V to 5.5V, V DD=2.7V to 3.6V, VSS=0V, Ta=-40 °C to +85°C, ST[1:0]=11)

Item Symbol Condition Min. Typ. Max. Unit ∗

Resolution – – 10 – bit

Conversion time – 5 – – µs1

Zero scale error EZS 024LSB

Full scale error E FS -2 – 2 LSB

Integral linearity error EL-3 – 3 LSB

Differential linearity error E D-3 – 3 LSB

Permissible signal source impedance – – – 5 kΩ

Analog input capacitance – – – 45 pF

∗ note 1) Indicates the minimum value when A/D clock = 4MHz (maximum clock frequency in 5V system).

Indicates the maximum value when A/D clock = 32 kHz (minimum clock frequency in 5V system).

2) 3.3 V single power source

(Unless otherwise specified: VDDE=AVDD=VDD=2.7V to 3.6V, VSS=0V, Ta=-40 °C to +85°C, ST[1:0]=11)

Item Symbol Condition Min. Typ. Max. Unit ∗

Resolution – – 10 – bit

Conversion time – 10 – 625 µs1

Zero scale error EZS 024LSB

Full scale error E FS -2 – 2 LSB

Integral linearity error EL-3 – 3 LSB

Differential linearity error E D-3 – 3 LSB

Permissible signal source impedance – – – 5 kΩ

Analog input capacitance – – – 45 pF

∗ note 1) Indicates the minimum value when A/D clock = 2MHz (maximum clock frequency in 3V system).

Indicates the maximum value when A/D clock = 32 kHz (minimum clock frequency in 3V system).

Note: • Be sure to use as VDDE = AVDD.

• The A/D converter cannot be used when the S1C33209/221/222 is used with a 2V power source.

A/D conversion error

V[000]h = Ideal voltage at zero-scale point (=0.5LSB)

V'[000]h = Actual voltage at zero-scale point

V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB)

V'[3FF]h = Actual voltage at full-scale point

1LSB =

1LSB' =

- V

- 1

V'[3FF]h - V'[000]h

- 2

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-71

V[000]h

(=0.5LSB)

V'[000]h

004

003

002

001

000

Zero scale error

Zero scale error E

= [LSB]

(V'[000]h - 0.5LSB') - (V[000]h - 0.5LSB)

1LSB

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

V[3FF]h (=1022.5LSB)

V'[3FF]h

3FF

3FE

3FD

3FC

3FB

Full scale error

Full scale error E

= [LSB]

(V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB)

1LSB

Digital output (hex)

Analo

input

Ideal conversion characteristic

Actual conversion characteristic

V'[000]h

3FF

3FE

3FD

003

002

001

000V

Integral linearity error E

= [LSB]

' - V

1LSB'

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

V'[3FF]h

V'[N]h

V'[N-1]h

N+1

N-1

N-2

Integral linearity error

Differential linearity error

Differential linearity error E

= - 1 [LSB]

V'[N]h - V'[N-1]h

1LSB'

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

8 ELECTRICAL CHARACTERISTICS

A-72 EPSON S1C33209/221/222 PRODUCT PART

8.6 AC Characteristics

8.6.1 Symbol Description

tCYC: Bus-clock cycle time

• In x1 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 20-MHz clock

tCYC = 30 ns (33 MHz) when the CPU is operated with a 33-MHz clock

• In x2 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 40-MHz clock

tCYC = 40 ns (25 MHz) when the CPU is operated with a 50-MHz clock

tCYC = 33 ns (30 MHz) when the CPU is operated with a 60-MHz clock

WC: Number of wait cycles

Up to 7 cycles can be set for the number of cycles using the BCU control register. Furthermore, it can be

extended to a desired number of cycles by setting the #WAIT pin from outside of the IC.

The minimum number of read cycles with no wait (0) inserted is 1 cycle.

The minimum number of write cycles with no wait cycle (0) inserted is 2 cycles. It does not change even if

1-wait cycle is set. The write cycle is actually extended when 2 or more wait cycles are set.

When inserting wait cycles by controlling the #WAIT pin from outside of the IC, pay attention to the timing of

the #WAIT signal sampling. Read cycles are terminated at the cycle in which the #WAIT signal is negated.

Write cycles are terminated at the following cycle after the #WAIT signal is negated.

C1, C2, C3, Cn: Cycle number

C1 indicates the first cycle when the BCU transfers data from/to an external memory or another device.

Similarly, C2 and Cn indicate the second cycle and nth cycle, respectively.

Cw: Wait cycle

Indicates that the cycle is wait cycle inserted.

8.6.2 AC Characteristics Measurement Condition

Signal detection level: Input signal High level VIH = V DDE - 0.4 V

Low level VIL = 0.4 V

Output signal High level V OH = 1/2 V DDE

Low level VOL = 1/2 V DDE

The following applies when OSC3 is external clock input:

Input signal High level V IH = 1/2 V DD

Low level VIL = 1/2 V DD

Input signal waveform: Rise time (10% → 90% V DD)5 ns

Fall time (90% → 10% V DD)5 ns

Output load capacitance: CL = 50 pF

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-73

8.6.3 C33 Block AC Characteristic Tables

External clock input characteristics

(Note) These AC characteristics apply to input signals from outside the IC.

The OSC3 input clock must be within VDD to V SS voltage range.

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

High-speed clock cycle time tC3 30 ns

OSC3 clock input duty tC3ED 45 55 %

OSC3 clock input rise time tIF 5ns

OSC3 clock input fall time tIR 5ns

BCLK high-level output delay time tCD1 35 ns

BCLK low-level output delay time tCD2 35 ns

Minimum reset pulse width tRST 6·tCYC ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

High-speed clock cycle time tC3 30 ns

OSC3 clock input duty tC3ED 45 55 %

OSC3 clock input rise time tIF 5ns

OSC3 clock input fall time tIR 5ns

BCLK high-level output delay time tCD1 35 ns

BCLK low-level output delay time tCD2 35 ns

Minimum reset pulse width tRST 6·tCYC ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

High-speed clock cycle time tC3 50 ns

OSC3 clock input duty tC3ED 45 55 %

OSC3 clock input rise time tIF 5ns

OSC3 clock input fall time tIR 5ns

BCLK high-level output delay time tCD1 60 ns

BCLK low-level output delay time tCD2 60 ns

Minimum reset pulse width tRST 6·tCYC ns

BCLK clock output characteristics

(Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used.

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

BCLK clock output duty tCBD 40 60 %

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

BCLK clock output duty tCBD 40 60 %

3) 2.0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

BCLK clock output duty tCBD 40 60 %

8 ELECTRICAL CHARACTERISTICS

A-74 EPSON S1C33209/221/222 PRODUCT PART

Common characteristics

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Address delay time tAD – 8 ns 1

#CEx delay time (1) tCE1 –8ns

#CEx delay time (2) tCE2 –8ns

Wait setup time tWTS 15 – ns

Wait hold time tWTH 0–ns

Read signal delay time (1) tRDD1 8ns2

Read data setup time tRDS 12 ns

Read data hold time tRDH 0ns

Write signal delay time (1) tWRD1 8ns3

Write data delay time (1) tWDD1 10 ns

Write data delay time (2) tWDD2 010ns

Write data hold time tWDH 0ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Address delay time tAD –10ns1

#CEx delay time (1) tCE1 –10ns

#CEx delay time (2) tCE2 –10ns

Wait setup time tWTS 15 – ns

Wait hold time tWTH 0–ns

Read signal delay time (1) tRDD1 10 ns 2

Read data setup time tRDS 15 ns

Read data hold time tRDH 0ns

Write signal delay time (1) tWRD1 10 ns 3

Write data delay time (1) tWDD1 10 ns

Write data delay time (2) tWDD2 010ns

Write data hold time tWDH 0ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Address delay time tAD –20ns1

#CEx delay time (1) tCE1 –20ns

#CEx delay time (2) tCE2 –20ns

Wait setup time tWTS 40 – ns

Wait hold time tWTH 0–ns

Read signal delay time (1) tRDD1 20 ns 2

Read data setup time tRDS 40 ns

Read data hold time tRDH 0ns

Write signal delay time (1) tWRD1 20 ns 3

Write data delay time (1) tWDD1 20 ns

Write data delay time (2) tWDD2 020ns

Write data hold time tWDH 0ns

∗ note1) This applies to the #BSH and #BSL timings.

2) This applies to the #GAAS and #GARD timings.

3) This applies to the #GAAS timing.

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-75

SRAM read cycle

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Read signal delay time (2) tRDD2 8ns

Read signal pulse width tRDW tCYC(0.5+WC)-8 ns

Read address ac cess time (1) tACC1 tCYC(1+WC)-20 ns

Chip enable access time (1) tCEAC1 tCYC(1+WC)-20 ns

Read signal access time (1) tRDAC1 tCYC(0.5+WC)-20 ns

2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Read signal delay time (2) tRDD2 10 ns

Read signal pulse width tRDW tCYC(0.5+WC)-10 ns

Read address access time (1) tACC1 tCYC(1+WC)-25 ns

Chip enable access time (1) tCEAC1 tCYC(1+WC)-25 ns

Read signal access time (1) tRDAC1 tCYC(0.5+WC)-25 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Read signal delay time (2) tRDD2 10 ns

Read signal pulse width tRDW tCYC(0.5+WC)-10 ns

Read address access time (1) tACC1 tCYC(1+WC)-60 ns

Chip enable access time (1) tCEAC1 tCYC(1+WC)-60 ns

Read signal access time (1) tRDAC1 tCYC(0.5+WC)-60 ns

SRAM write cycle

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Write signal delay time (2) tWRD2 8ns

Write signal pulse width tWRW tCYC(1+WC)-10 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Write signal delay time (2) tWRD2 10 ns

Write signal pulse width tWRW tCYC(1+WC)-10 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Write signal delay time (2) tWRD2 20 ns

Write signal pulse width tWRW tCYC(1+WC)-20 ns

8 ELECTRICAL CHARACTERISTICS

A-76 EPSON S1C33209/221/222 PRODUCT PART

DRAM access cycle common characteristics

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

#RAS signal delay time (1) tRASD1 10 ns

#RAS signal delay time (2) tRASD2 10 ns

#RAS signal pulse width tRASW tCYC(2+WC)-10 ns

#CAS signal delay time (1) tCASD1 10 ns

#CAS signal delay time (2) tCASD2 10 ns

#CAS signal pulse width tCASW tCYC(0.5+WC)-5 ns

Read signal delay time (3) tRDD3 10 ns

Read signal pulse width (2) tRDW2 tCYC(2+WC)-10 ns

Write signal delay time (3) tWRD3 10 ns

Write signal pulse width (2) tWRW2 tCYC(2+WC)-10 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

#RAS signal delay time (1) tRASD1 10 ns

#RAS signal delay time (2) tRASD2 10 ns

#RAS signal pulse width tRASW tCYC(2+WC)-10 ns

#CAS signal delay time (1) tCASD1 10 ns

#CAS signal delay time (2) tCASD2 10 ns

#CAS signal pulse width tCASW tCYC(0.5+WC)-10 ns

Read signal delay time (3) tRDD3 10 ns

Read signal pulse width (2) tRDW2 tCYC(2+WC)-10 ns

Write signal delay time (3) tWRD3 10 ns

Write signal pulse width (2) tWRW2 tCYC(2+WC)-10 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

#RAS signal delay time (1) tRASD1 20 ns

#RAS signal delay time (2) tRASD2 20 ns

#RAS signal pulse width tRASW tCYC(2+WC)-20 ns

#CAS signal delay time (1) tCASD1 20 ns

#CAS signal delay time (2) tCASD2 20 ns

#CAS signal pulse width tCASW tCYC(0.5+WC)-20 ns

Read signal delay time (3) tRDD3 20 ns

Read signal pulse width (2) tRDW2 tCYC(2+WC)-20 ns

Write signal delay time (3) tWRD3 20 ns

Write signal pulse width (2) tWRW2 tCYC(2+WC)-20 ns

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-77

DRAM random access cycle and DRAM fast-page cycle

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCF tCYC(1+WC)-25 ns

#RAS access time tRACF tCYC(1.5+WC)-25 ns

#CAS access time tCACF tCYC(0.5+WC)-25 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCF tCYC(1+WC)-25 ns

#RAS access time tRACF tCYC(1.5+WC)-25 ns

#CAS access time tCACF tCYC(0.5+WC)-25 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCF tCYC(1+WC)-60 ns

#RAS access time tRACF tCYC(1.5+WC)-60 ns

#CAS access time tCACF tCYC(0.5+WC)-60 ns

EDO DRAM random access cycle and EDO DRAM page cycle

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCE tCYC(1.5+WC)-25 ns

#RAS access time tRACE tCYC(2+WC)-25 ns

#CAS access time tCACE tCYC(1+WC)-15 ns

Read data setup time tRDS2 20 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCE tCYC(1.5+WC)-25 ns

#RAS access time tRACE tCYC(2+WC)-25 ns

#CAS access time tCACE tCYC(1+WC)-20 ns

Read data setup time tRDS2 20 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Column address access time tACCE tCYC(1.5+WC)-60 ns

#RAS access time tRACE tCYC(2+WC)-60 ns

#CAS access time tCACE tCYC(1+WC)-60 ns

Read data setup time tRDS2 20 ns

8 ELECTRICAL CHARACTERISTICS

A-78 EPSON S1C33209/221/222 PRODUCT PART

Burst ROM read cycle

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Read address access time (2) tACC2 tCYC(1+WC)-20 ns

Chip enable access time (2) tCEAC2 tCYC(1+WC)-20 ns

Read signal access time (2) tRDAC2 tCYC(0.5+WC)-20 ns

Burst address access time tACCB tCYC(1+WC)-20 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Read address access time (2) tACC2 tCYC(1+WC)-25 ns

Chip enable access time (2) tCEAC2 tCYC(1+WC)-25 ns

Read signal access time (2) tRDAC2 tCYC(0.5+WC)-25 ns

Burst address access time tACCB tCYC(1+WC)-25 ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Read address access time (2) tACC2 tCYC(1+WC)-60 ns

Chip enable access time (2) tCEAC2 tCYC(1+WC)-60 ns

Read signal access time (2) tRDAC2 tCYC(0.5+WC)-60 ns

Burst address access time tACCB tCYC(1+WC)-60 ns

External bus master and NMI

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

#BUSREQ signal setup time tBRQS 15 ns

#BUSREQ signal hold time tBRQH 0ns

#BUSACK signal output delay time tBAKD 10 ns

High-impedance → output delay time tZ2E 10 ns

Output → high-impedance delay time tB2Z 10 ns

#NMI pulse width tNMIW 30 ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

#BUSREQ signal setup time tBRQS 15 ns

#BUSREQ signal hold time tBRQH 0ns

#BUSACK signal output delay time tBAKD 10 ns

High-impedance → output delay time tZ2E 10 ns

Output → high-impedance delay time tB2Z 10 ns

#NMI pulse width tNMIW 30 ns

3) 2. 0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

#BUSREQ signal setup time tBRQS 40 ns

#BUSREQ signal hold time tBRQH 0ns

#BUSACK signal output delay time tBAKD 20 ns

High-impedance → output delay time tZ2E 20 ns

Output → high-impedance delay time tB2Z 20 ns

#NMI pulse width tNMIW 90 ns

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-79

Input, Output and I/O port

1) 3.3 V/5.0 V dual power source

(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V , V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Input data setup time tINPS 20 ns

Input data hold time tINPH 10 ns

Output data delay time tOUTD 20 ns

K-port interrupt SLEEP, HALT2 mode tKINW 30 ns

input pulse width Others 2 × tCYC ns

2) 3.3 V single power source(Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, V SS=0V, Ta=-40°C to +85°C)

Item Symbol Min. Max. Unit ∗

Input data setup time tINPS 20 ns

Input data hold time tINPH 10 ns

Output data delay time tOUTD 20 ns

K-port interrupt SLEEP, HALT2 mode tKINW 30 ns

input pulse width Others 2 × tCYC ns

3) 2.0 V single power source (Unless otherwise specified: V DDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40 °C to +85°C)

Item Symbol Min. Max. Unit ∗

Input data setup time tINPS 40 ns

Input data hold time tINPH 20 ns

Output data delay time tOUTD 30 ns

K-port interrupt SLEEP, HALT2 mode tKINW 90 ns

input pulse width Others 2 × tCYC ns

8 ELECTRICAL CHARACTERISTICS

A-80 EPSON S1C33209/221/222 PRODUCT PART

8.6.4 C33 Block AC Characteristic Timing Charts

Clock

OSC3

(High-speed clock)

BCLK

(Clock output)

C3H

C3ED

C3H

CBD

CBH

BCLK

(Clock output)

CBH

CD1

CD2

(1) When an external clock is input (in x1 speed mode):

(2) When the high-speed oscillation circuit is used for the operating clock:

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-81

SRAM read cycle (basic cycle: 1 cycle)

BCLK

A[23:0]

#CEx

#RD

D[15:0]

#WAIT

tC3

tAD

tCE1 tCE2

tRDD2tRDD1

tRDAC1

tRDS

tWTS tWTH tRDH

tCEAC1

tACC1

tRDW

tAD

,,,,,,,

,,,,,,

,,,,

∗1

*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0]

signals.

SRAM read cycle (when a wait cycle is inserted)

BCLK

A[23:0]

#CEx

#RD

D[15:0]

#WAIT

C1 Cw

(wait cycle)

(last cycle)

tAD

tCE1 tCE2

tRDD2tRDD1

(C1 only)

tRDAC1

tRDS

tWTS tWTHtWTS tWTH tRDH

tCEAC1

tACC1

tRDW

tAD

,,,,,,,,,,,,,,,,,,,,,,,

,,,,,,,,

,,,,,,,

,,,,

∗1

tWTS tWTH

*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0]

signals.

8 ELECTRICAL CHARACTERISTICS

A-82 EPSON S1C33209/221/222 PRODUCT PART

SRAM write cycle (basic cycle: 2 cycles)

BCLK

A[23:0]

#CEx

#WR

D[15:0]

#WAIT

C1 C2

tAD

tCE1 tCE2

tWRD2tWRD1

tWTS tWTH

tWDD1 tWDH

tWRW

tAD

,,,,,,

,,,,

SRAM write cycle (when wait cycles are inserted)

BCLK

A[23:0]

#CEx

#WR

D[15:0]

#WAIT

C1 Cw(wait cycle) Cw(wait cycle) Cn(last cycle)

tAD

tCE1 tCE2

tWRD2tWRD1

tWTS tWTH tWTS tWTStWTH tWTH

tWDD1 tWDH

tWRW

tAD

,,,,,,,,,,,,,,

,,,,,

,,,

Wait cycle follows Last cycle follows

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-83

DRAM random access cycle (basic cycle)

BCLK

A[23:0]

#RAS

#HCAS/

#LCAS

#RD

D[15:0]

#WE

D[15:0]

RAS1

Data transfer #1 Next data transfer

CAS1 PRE1(precharge) RAS1' CAS1'

tAD tAD tAD

tCASD2tCASD1

tRDS

tACCF

tRACF

tRDH

tRASD2tRASD1 tRASW

tRDD3tRDD1 tRDW2

tWRD3tWRD1 tWRW2

;;;;;;;;;

;;;;;;;;;;

;;;;;;;

;;;;;

tWDD1 tWDD2

;;;;;

tCASW

tCACF

∗1

∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.

DRAM fast-page access cycle

BCLK

A[23:0]

#RAS

#HCAS/

#LCAS

#RD

D[15:0]

#WE

D[15:0]

RAS1

Data transfer #1 Data transfer #2 Next data transfer

CAS1 CAS2 PRE1(precharge) RAS1'

tAD tAD tAD

tRDS

tACCF

tRACF

tRDH

tRASD2tRASD1

tRDD3tRDD1

tWRD3tWRD1

tWDD1 tWDD2 tWDD2

tCACF tACCF

tRASW

tRDW2

tCASD2tCASD1

tRDS tRDH

tCASW

tWRW2

∗1∗1

∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.

8 ELECTRICAL CHARACTERISTICS

A-84 EPSON S1C33209/221/222 PRODUCT PART

EDO DRAM random access cycle (basic cycle)

BCLK

A[23:0]

#RAS

#HCAS/

#LCAS

#RD

D[15:0]

#WE

D[15:0]

RAS1

Data transfer #1 Next data transfer

CAS1 PRE1

(precharge)

RAS1' CAS1'

CASD2

CASD1

RDS2

ACCE

RACE

RDH

RASD2

RASD1

RASW

RDD3

RDD1

RDW2

WRD3

WRD1

WRW2

,,,,,,,,,

,,,,,,,,,,

,,,

WDD1

WDD2

,,,,,

CASW

CACE

∗1

∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals.

EDO DRAM page access cycle

BCLK

A[23:0]

#RAS

#HCAS/

#LCAS

#RD

D[15:0]

#WE

D[15:0]

RAS1

Data transfer #1 Data transfer #2 Next data transfer

CAS1 CAS2 PRE1

(precharge)

RAS1'

RDS

ACCE

RACE

RASD2

RASD1

RDD3

RDD1

WRD3

WRD1

,,,,,,,,,

,,,,,,,,,,,,,,

,,,,,

,,,,

WDD1

WDD2

,,,,,

CACE

ACCE

RASW

RDW2

CASD2

CASD1

,,,,

CASW

WRW2

RDH

RDS

RDH ∗1

∗1tRDH is measured with respect to the first signal change from among the #RD (negation), #RASx (negation)

and #CAS (fall) signals.

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-85

DRAM CAS-before-RAS refresh cycle

BCLK

#RAS

#HCAS/

#LCAS

#WE

CBR refresh cycle

CBR1

CBR2

CBR3

RASD2

RASD1

CASD2

CASD1

,,,,,,,,

,,,,,,

,,,,,,,,

,,,,,,

DRAM self-refresh cycle

BCLK

#RAS

#HCAS/

#LCAS

Self-refresh mode setup Self-refresh mode

tCASD2

,,,,,,,

,,,,

Self-refresh mode canceration

tRASD2tRASD1

tCASD1

6-cycle precharge

(Fixed)

Burst ROM read cycle

BCLK

A[23:2]

A[1:0]

#CEx

#RD

D[15:0]

SRAM read cycle Burst cycle Burst cycle Burst cycle

RDS

RDAC2

CEAC

RDH

CE2

CE1

RDD2

RDD1

,,,,,

ACC2

RDS

RDH

,,,,,

ACCB

RDS

RDH

,,,,,

ACCB

RDS

RDH

,,,,,

ACCB

∗1

∗1tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0]

signals.

8 ELECTRICAL CHARACTERISTICS

A-86 EPSON S1C33209/221/222 PRODUCT PART

#BUSREQ, #BUSACK and #NMI timing

BCLK

#BUSREQ

#BUSACK

eBUS_OUT signals ∗1

#NMI

tBRQS

Valid input

tNMIW

tBRQH

,,,,,

tBAKD

tZ2E

tB2Z

,,,

∗1 eBUS_OUT indicates the following pins:

A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0]

Input, output and I/O port timing

BCLK

Kxx, Pxx

(input: data read

from the port)

Pxx, Rxx (output)

Kxx

(K-port interrupt input)

tINPS

Valid input

tKINW

tINPH

,,,,,

tOUTD

,,,

8 ELECTRICAL CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-87

8.7 Oscillation Characteristics

Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following

characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator

manufacturer recommended values for constants such as capacitance and resistance.

OSC1 crystal oscillation

(Unless otherwise specified: crystal=Q11C02RX#1 32.768kHz, Rf1=20MΩ, CG1=CD1=15pF#2)

Item Symbol Condition Min. Typ. Max. Unit ∗

Operating temperature Ta VDD=2.7V to 3.6V -40 85 °C

VDD=1.9V to 2.2V -40 85 °C

VDD=1.8V to 2.2V 0 70 °C

#1 Q11C02RX: Crystal resonator made by Seiko Epson

#2 "CG1=CD1=15pF" includes board capacitance.

(Unless otherwise specified: VDD=3.3V, VSS=0V, crystal=Q11C02RX#1 32.768kHz,

Rf1=20MΩ, CG1=CD1=15pF#2, Ta=25°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Oscillation start time tSTA1 3 sec

External gate/drain capacitance CG1, CD1 CG1=CD1,

including board capacitance 525pF

Frequency/IC deviation ∆f/∆IC -10 10 ppm

Frequency/power voltage deviation ∆f/∆V -10 10 ppm/V

Frequency adjustment range ∆f/∆CGCG=CD1= 5 to 25pF 50 ppm

#1 Q11C02RX: Crystal resonator made by Seiko Epson

#2 "CG1=CD1=15pF" includes board capacitance.

(Unless otherwise specified: VDD=2.0V, VSS=0V, crystal=Q11C02RX#1 32.768kHz,

Rf1=20MΩ, CG1=CD1=15pF#2, Ta=25°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Oscillation start time tSTA1 20 sec

External gate/drain capacitance CG1, CD1 CG1=CD1,

including board capacitance 525pF

Frequency/IC deviation ∆f/∆IC -10 10 ppm

Frequency/power voltage deviation ∆f/∆V -10 10 ppm/V

Frequency adjustment range ∆f/∆CGCG1=CD1= 5 to 25pF 50 ppm

#1 Q11C02RX: Crystal resonator made by Seiko Epson

#2 "CG1=CD1=15pF" includes board capacitance.

OSC3 crystal oscillation

Note:A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit.

(Unless otherwise specified: VSS=0V, crystal=Q22MA306#1 33.8688MHz,

Rf2=1MΩ, CG1=CD1=15pF#2, Ta=25°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Oscillation start time tSTA3 VDD=3.3V 10 ms

VDD=2.0V 25 ms

#1 Q22MA306: Crystal resonator made by Seiko Epson

#2 "CG1=CD1=15pF" includes board capacitance.

8 ELECTRICAL CHARACTERISTICS

A-88 EPSON S1C33209/221/222 PRODUCT PART

OSC3 ceramic oscillation (Unless otherwise specified: VSS=0V, Ta=25°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Oscillation start time tSTA3 10MHz ceramic oscillator 10 ms 1

16MHz ceramic oscillator 10 ms 2

20MHz ceramic oscillator 10 ms 3

25MHz ceramic oscillator 5 ms 4

33MHz ceramic oscillator 5 ms 5

∗ note) No. Ceramic Recommended constants Power voltage Remarks

oscillator CG2 (pF) CD2 (pF) Rf2 (M Ω) range (V) (Manufacturer)

1 CST10.0MTW 30 30 1 1.8 to 2.2 (Murata Mfg. corporation) ∗1

2 CST16.00MXW0C1 5 5 1 1.8 to 2.2 (Murata Mfg. corporation)

3 CST20.00MXW0H1 5 5 1 1.8 to 2.2 (Murata Mfg. corporation)

4 CST25.00MXW0H1 5 5 1 2.7 to 3.6 (Murata Mfg. corporation)

5 CST33.00MXZ040 Open Open 1 2.7 to 3.6 (Murata Mfg. corporation)

∗1 This oscillator has a tendency to rise to the frequency of 0.3%.

8.8 PLL Characteristics

Setting the PLLS0 and PLLS1 pins (recommended operating condition)

VDD=2.7V to 3.6V

PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout

1 1 x2 10 to 25MHz 20 to 50MHz

0 1 x4 10 to 12.5MHz 40 to 50MHz

0 0 PLL not used – –

VDD=2.0V±0.2V

PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout

1 1 x2 10MHz 20MHz

0 0 PLL not used – –

PLL characteristics (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, crystal oscillator=Q3204DC#1,

R1=4.7kΩ, C1=100pF, C2=5pF, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Jitter (peak jitter) tpj -1 1 ns

Lockup time tpll 1 ms

#1 Q3204DC: Crystal oscillator made by Seiko Epson

(Unless otherwise specified: VDD=2.0V±0.2V, VSS=0V, crystal oscillator=Q3204DC #1,

R1=4.7kΩ, C1=100pF, C2=5pF, Ta=-40°C to +85°C)

Item Symbol Condition Min. Typ. Max. Unit ∗

Jitter (peak jitter) tpj -2 2 ns

Lockup time tpll 2 ms

#1 Q3204DC: Crystal oscillator made by Seiko Epson

9 PACKAGE

S1C33209/221/222 PRODUCT PART EPSON A-89

9 Package

9.1 Plastic Package

QFP5-128pin (Unit: mm)

20±0.1

23.6±0.4

65102

14±0.1

17.6±0.4

INDEX

0.2±0.05 381

128

103

2.7±0.1

0.1

3max

1.8

0.8±0.2

0°

10°

0.15±0.05

0.5

Limit of power consumption

The chip temperature of an LSI rises according to power consumption. The chip temperature can be calculated

from environment temperature (Ta), thermal package resistance ( θ) and power consumption (PD).

Chip temperature (Tj) = Ta + (PD × θ) (°C)

As a guide, normally keep the chip temperature (Tj) lower than 85°C.

The thermal resistance of the QFP5-128pin package is as follows:

Thermal resistance (°C/W) = 105 to 115 °C (75 to 85°C for Cu lead frame)

This thermal resistance is a value under the condition that the measured device is hanging in the air and has no

air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air-cooling

condition.

9 PACKAGE

A-90 EPSON S1C33209/221/222 PRODUCT PART

QFP15-128pin (Unit: mm)

14±0.1

16±0.4

6596

14±0.1

16±0.4

INDEX

0.16 321

128

1.4±0.1

0.1

1.7max

0.5±0.2

0°

10°

0.125

0.4 +0.1

–0.05

+0.05

–0.025

Limit of power consumption

The chip temperature of an LSI rises according to power consumption. The chip temperature can be calculated

from environment temperature (Ta), thermal package resistance ( θ) and power consumption (PD).

Chip temperature (Tj) = Ta + (PD × θ) (°C)

As a guide, normally keep the chip temperature (Tj) lower than 85°C.

The thermal resistance of the QFP15-128pin package is as follows:

Thermal resistance (°C/W) = 110 to 120 °C (90 to 100°C for Cu lead frame)

This thermal resistance is a value under the condition that the measured device is hanging in the air and has no

air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air-cooling

condition.

10 PAD LAYOUT

S1C33209/221/222 PRODUCT PART EPSON A-91

10 Pad Layout

10.1 Pad Layout Diagram

(0, 0)

TBD mm

1 5 10 15 20 25 30 35 40 45 50 55

100

105110115120125130135140145150155

160

165

170

175

180

185

190

195

200

Die No.

10 PAD LAYOUT

A-92 EPSON S1C33209/221/222 PRODUCT PART

10.2 Pad Coordinate (S1C33209 only)

(Unit: µm)

No. Pad name X Y No. Pad name X Y

1 P24/TM2 -2,373 -2,288 51 N.C. 1,890 -2,288

2 N.C. -2,247 -2,288 52 K63/AD3 1,974 -2,288

3VSS -2,142 -2,288 53 N.C. 2,058 -2,288

4 N.C. -2,058 -2,288 54 K62/AD2 2,142 -2,288

5 P25/TM3 -1,974 -2,288 55 N.C. 2,247 -2,288

6 N.C. -1,890 -2,288 56 AVDDE 2,373 -2,288

7 P26/TM4 -1,806 -2,288 57 K61/AD1 2,855 -1,806

8 P15/EXCL4/#DMAEND0 -1,722 -2,288 58 N.C. 2,855 -1,722

9 N.C. -1,638 -2,288 59 K60/AD0 2,855 -1,638

10 P27/TM5 -1,554 -2,288 60 N.C. 2,855 -1,554

11 N.C. -1,470 -2,288 61 D6 2,855 -1,470

12 BCLK -1,386 -2,288 62 N.C. (VDD) 2,855 -1,386

13 N.C. -1,302 -2,288 63 VSS 2,855 -1,302

14 P00/SIN0 -1,218 -2,288 64 N.C. 2,855 -1,218

15 N.C. -1,134 -2,288 65 D5 2,855 -1,134

16 P01/SOUT0 -1,050 -2,288 66 N.C. 2,855 -1,050

17 N.C. -966 -2,288 67 D4 2,855 -966

18 D15 -882 -2,288 68 N.C. 2,855 -882

19 N.C. -798 -2,288 69 D3 2,855 -798

20 VDD -714 -2,288 70 N.C. 2,855 -714

21 P03/#SRDY0 -630 -2,288 71 D2 2,855 -630

22 D14 -546 -2,288 72 N.C. 2,855 -546

23 P31/#BUSGET/#GARD -462 -2,288 73 D1 2,855 -462

24 D13 -378 -2,288 74 N.C. (VSS) 2,855 -378

25 P32/#DMAACK0 -294 -2,288 75 D0 2,855 -294

26 D12 -210 -2,288 76 P35/#BUSACK 2,855 -210

27 P33/#DMAACK1 -126 -2,288 77 VDDE 2,855 -126

28 D11 -42 -2,288 78 #CE9/#CE17 2,855 -42

29 K54/#DMAREQ3 42 -2,288 79 OSC2 2,855 42

30 D10 126 -2,288 80 #CE7/#RAS0/#CE13/#RAS2 2,855 126

31 K53/#DMAREQ2 210 -2,288 81 OSC1 2,855 210

32 D9 294 -2,288 82 #CE6 2,855 294

33 K52/#ADTRG 378 -2,288 83 N.C. 2,855 378

34 VSS 462 -2,288 84 #RD 2,855 462

35 K51/#DMAREQ1 546 -2,288 85 N.C. 2,855 546

36 P02/#SCLK0 630 -2,288 86 VSS 2,855 630

37 D8 714 -2,288 87 N.C. 2,855 714

38 N.C. 798 -2,288 88 #WRL/#WR/#WE/#LWE 2,855 798

39 D7 882 -2,288 89 N.C. 2,855 882

40 N.C. 966 -2,288 90 #WRH/#BSH/#UWE 2,855 966

41 VDDE 1,050 -2,288 91 N.C. 2,855 1,050

42 N.C. 1,134 -2,288 92 #CE10EX 2,855 1,134

43 K67/AD7 1,218 -2,288 93 N.C. 2,855 1,218

44 N.C. 1,302 -2,288 94 #CE8/#RAS1/#CE14/#RAS3 2,855 1,302

45 K66/D6 1,386 -2,288 95 N.C. 2,855 1,386

46 N.C. 1,470 -2,288 96 #CE5/#CE15 2,855 1,470

47 K65/AD5 1,554 -2,288 97 N.C. (VDD) 2,855 1,554

48 N.C. 1,638 -2,288 98 #CE4/#CE11 2,855 1,638

49 K50/#DMAREQ0 1,722 -2,288 99 N.C. 2,855 1,722

50 K64/AD4 1,806 -2,288 100 P30/#WAIT/#CE4&5 2,855 1,806

10 PAD LAYOUT

S1C33209/221/222 PRODUCT PART EPSON A-93

No. Pad name X Y No. Pad name X Y

101 #RESET 2,373 2,288 151 N.C. -1,890 2,288

102 N.C. 2,247 2,288 152 A18 -1,974 2,288

103 #NMI 2,142 2,288 153 N.C. -2,058 2,288

104 N.C. 2,058 2,288 154 A19 -2,142 2,288

105 A0/#BSL 1,974 2,288 155 N.C. -2,247 2,288

106 N.C. 1,890 2,288 156 P04/SIN1/#DMAACK2 -2,373 2,288

107 A1 1,806 2,288 157 P05/SOUT1/#DMAEND2 -2,855 1,806

108 P34/#BUSREQ/#CE6 1,722 2,288 158 N.C. -2,855 1,722

109 N.C. 1,638 2,288 159 P06/#SCLK1/DMAACK3 -2,855 1,638

110 VSS 1,554 2,288 160 N.C. -2,855 1,554

111 N.C. 1,470 2,288 161 VSS -2,855 1,470

112 A2 1,386 2,288 162 N.C. -2,855 1,386

113 N.C. 1,302 2,288 163 PLLC -2,855 1,302

114 A3 1,218 2,288 164 N.C. -2,855 1,218

115 N.C. 1,134 2,288 165 VSS -2,855 1,134

116 A4 1,050 2,288 166 N.C. -2,855 1,050

117 N.C. 966 2,288 167 PLLS1 -2,855 966

118 A5 882 2,288 168 N.C. -2,855 882

119 N.C. 798 2,288 169 PLLS0 -2,855 798

120 A6 714 2,288 170 VDD -2,855 714

121 #CE10IN 630 2,288 171 P07/#SRDY1/#DMAEND3 -2,855 630

122 VDD 546 2,288 172 N.C. -2,855 546

123 #EMEMRD 462 2,288 173 #X2SPD -2,855 462

124 A7 378 2,288 174 N.C. -2,855 378

125 #HCAS/#UWE 294 2,288 175 EA10MD0 -2,855 294

126 A8 210 2,288 176 EA10MD1 -2,855 210

127 #LCAS/#CAS 126 2,288 177 VDD -2,855 126

128 A9 42 2,288 178 N.C. -2,855 42

129 P16/EXCL5/#DMAEND1 -42 2,288 179 OSC4 -2,855 -42

130 A10 -126 2,288 180 P20/#DRD -2,855 -126

131 A20 -210 2,288 181 OSC3 -2,855 -210

132 A11 -294 2,288 182 P21/#DWE/#GAAS -2,855 -294

133 A21 -378 2,288 183 N.C. -2,855 -378

134 A12 -462 2,288 184 #CE3 -2,855 -462

135 A22 -546 2,288 185 N.C. (BSTB) -2,855 -546

136 A13 -630 2,288 186 P22/TM0 -2,855 -630

137 A23 -714 2,288 187 N.C. -2,855 -714

138 N.C. -798 2,288 188 P23/TM1 -2,855 -798

139 VSS -882 2,288 189 N.C. -2,855 -882

140 N.C. -966 2,288 190 DSIO -2,855 -966

141 A14 -1,050 2,288 191 N.C. -2,855 -1,050

142 N.C. -1,134 2,288 192 P10/EXCL0/T8UF0/DST0 -2,855 -1,134

143 A15 -1,218 2,288 193 N.C. -2,855 -1,218

144 N.C. -1,302 2,288 194 P11/EXCL1/T8UF1/DST1 -2,855 -1,302

145 VDDE -1,386 2,288 195 N.C. -2,855 -1,386

146 N.C. -1,470 2,288 196 P12/EXCL2/T8UF2/DST2 -2,855 -1,470

147 A16 -1,554 2,288 197 N.C. -2,855 -1,554

148 N.C. -1,638 2,288 198 P13/EXCL3/T8UF3/DST3 -2,855 -1,638

149 ICEMD -1,722 2,288 199 N.C. -2,855 -1,722

150 A17 -1,806 2,288 200 P14/FOSC1/DCLK -2,855 -1,806

Note: The S1C33209 is constructed with 0.35 µm process technology. Since the pad pitch is to small, it is

impossible to use all pads when mounting the chip (die form) on the board. When mounting the

chip use the pads other than "N.C." and "N.C. (xxxx)". The pads which is indicated with "N.C.

(xxxx)" in the table is available in the QFP5-128pin/QFP15-128pin package.

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-94 EPSON S1C33209/221/222 PRODUCT PART

Appendix A <Reference> External Device Interface Timings

This section shows setup examples for setting timing conditions of the external system interface as a reference

material used when configuring a system with external devices.

Pay attention to the following precautions when using this material.

• The described AC characteristic values of external devices are standard values. They may differ from those of the

devices actually used, so the actual setup values (number of cycles) should be determined by referring the manual or

specification of the device to be used.

• It is necessary to set the timing values allowing ample margin according to the load capacitance of the bus and

signal lines, number of devices to be connected, operating temperature range, I/O levels and other conditions. The

number of cycles described in this section is an example and the conditions are not conside red.

• The values described in "Time" column of the tables are simply calculated by multiplying the number of cycles by

the cycle time. Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and

input setup time are not considered.

• The described contents are reference data and cannot be guaranteed to work.

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-95

A.1 DRAM (70ns)

DRAM interface setup examples – 70ns

Operating

frequency RAS precharge

cycle RAS cycle CAS cycle Refresh RAS pulse

width Refresh RPC delay

20MHz 2 1 2 2 1

25MHz 2 1 2 2 1

33MHz 2 2 3 3 1

DRAM interface timing – 70ns

DRAM interface Unit: ns 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Random read/random write cycle time tRC 130 – 7 210 5 200 5 250

#RAS precharge time tRP 50 – 2 60 2 80 2 100

#RAS pulse width tRAS 70 10000 5 150 3 120 3 150

#CAS pulse width tCAS 20 10000 2.5 75 1.5 60 1.5 75

Row address setup time tASR 0 – 0.5 15 0.5 20 0.5 25

Row address hold time tRAH 10 – 1.5 45 0.5 20 0.5 25

Column address setup time tASC 0 – 0.5 15 0.5 20 0.5 25

#RAS→#CAS delay time tRCD 20 – 2.0 60 1.0 40 1.0 50

#RAS→column address delay time tRAD 15 – 1.5 45 0.5 20 0.5 25

<Read-cycle parameters>

#RAS access time tRAC – 70 4.5 135 2.5 100 2.5 125

#CAS access time tCAC – 20 2.5 75 1.5 60 1.5 75

Address access time tAA – 35 3.0 90 2.0 80 2.0 100

#OE access time tOAC – 20 4.5 135 2.5 100 2.5 125

Output buffer turn-off time tOFF 0 20 2 60 2 80 2 100

<Write-cycle parameters>

Data input hold time tDH 15 – 2.5 75 1.5 60 1.5 75

<Fast-page mode>

Fast-page mode cycle time tPC 45 – 3.0 90 2.0 80 2.0 100

Fast-page mode #CAS precharge time tCP 10 – 0.5 15 0.5 20 0.5 25

Access time after #CAS precharge tACP – 40 3.0 90 2.0 80 2.0 100

#CAS setup time tCSR 10 – 1.0 30 1.0 40 1.0 50

#CAS hold time tCHR 10 – 2.5 75 1.5 60 1.5 75

#RAS precharge→#CAS hold time tPPC 10 – 1.0 30 1.0 40 1.0 50

#RAS pulse width (only in refresh cycle) tRAS 70 10000 3.0 90 2.0 80 2.0 100

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-96 EPSON S1C33209/221/222 PRODUCT PART

DRAM: 70ns, CPU: 33MHz, random read/write cycle

RAS cycle CAS cycle RAS precharge

RAD

RAH

RCD

RAC

OAC

CAC

OFF

CAS

ASC

RAS

ASR

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

ROW #2

,,,,,,,,,

,,,,

WR data

,,,

COL #1

DRAM: 70ns, CPU: 33MHz, page-mode read/write cycle

RAS cycle CAS cycle RAS precharge

CAS cycle

tPC

tACP

tCP

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,

,,,,,,,,,

RD data

,,,,,,,,,

WR data

,,,

WR data

COL #1 COL #2

DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle

1 1

RPC delay Fixed Refresh RAS pulse width

RAS precharge

RPC

CSR

CHR

RAS

BCLK

#RAS

#CAS

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-97

DRAM: 70ns, CPU: 25/20MHz, random read/write cycle

RAS cycle CAS cycle RAS precharge

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

ROW #2

,,,,,

WR data

,,,

COL #1

DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle

RAS cycle CAS cycle RAS precharge

2CAS cycle

2 2

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

,,,,,

RD data

,,,,,

WR data

,,,

WR data

COL #1 COL #2

DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle

1 1

RPC delay Fixed Refresh RAS pulse width

2RAS precharge

tRPC tCSR tCHR

tRAS

BCLK

#RAS

#CAS

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-98 EPSON S1C33209/221/222 PRODUCT PART

A.2 DRAM (60ns)

DRAM interface setup examples – 60ns

Operating

frequency RAS precharge

cycle RAS cycle CAS cycle Refresh RAS pulse

width Refresh RPC delay

20MHz 1 1 2 2 1

25MHz 2 1 2 2 1

33MHz 2 2 2 3 1

DRAM interface timing – 60ns

DRAM interface Unit: ns 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Random read/random write cycle time tRC 110 – 6 180 5 200 4 200

#RAS precharge time tRP 40 – 2 60 2 80 1 50

#RAS pulse width tRAS 60 10000 4 120 3 120 3 150

#CAS pulse width tCAS 15 10000 1.5 45 1.5 60 1.5 75

Row address setup time tASR 0 – 0.5 15 0.5 20 0.5 25

Row address hold time tRAH 10 – 1.5 45 0.5 20 0.5 25

Column address setup time tASC 0 – 0.5 15 0.5 20 0.5 25

#RAS→#CAS delay time tRCD 20 – 2.0 60 1.0 40 1.0 50

#RAS→column address delay time tRAD 15 – 1.5 45 0.5 20 0.5 25

<Read-cycle parameters>

#RAS access time tRAC – 60 3.5 105 2.5 100 2.5 125

#CAS access time tCAC – 15 1.5 45 1.5 60 1.5 75

Address access time tAA – 30 2.0 60 2.0 80 2.0 100

#OE access time tOAC – 15 3.5 105 2.5 100 2.5 125

Output buffer turn-off time tOFF 015260 280 150

<Write-cycle parameters>

Data input hold time tDH 10 – 1.5 45 1.5 60 1.5 75

<Fast-page mode>

Fast-page mode cycle time tPC 40 – 2.0 60 2.0 80 2.0 100

Fast-page mode #CAS precharge time tCP 10 – 0.5 15 0.5 20 0.5 25

Access time after #CAS precharge tACP – 35 2.0 60 2.0 80 2.0 100

#CAS setup time tCSR 10 – 1.0 30 1.0 40 1.0 50

#CAS hold time tCHR 10 – 2.5 75 1.5 60 1.5 75

#RAS precharge→#CAS hold time tPPC 10 – 1.0 30 1.0 40 1.0 50

#RAS pulse width (only in refresh cycle) tRAS 60 10000 3.0 90 2.0 80 2.0 100

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-99

DRAM: 60ns, CPU: 33MHz, random read/write cycle

RAS cycle CAS cycle RAS precharge

RAD

RAH

RCD

RAC

OAC

CAC

OFF

CAS

ASC

RAS

ASR

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

ROW #2

,,,,,

,,,,

WR data

,,,

COL #1

DRAM: 60ns, CPU: 33MHz, page-mode read/write cycle

RAS cycle CAS cycle RAS precharge

CAS cycle

ACP

RAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,

,,,,,

RD data

,,,,,

WR data

,,,

WR data

COL #1 COL #2

DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle

1 1

RPC delay Fixed Refresh RAS pulse width

RAS precharge

RPC

CSR

CHR

RAS

BCLK

#RAS

#CAS

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-100 EPSON S1C33209/221/222 PRODUCT PART

DRAM: 60ns, CPU: 25MHz, random read/write cycle

RAS cycle CAS cycle RAS precharge

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

ROW #2

,,,,,

WR data

,,,

COL #1

DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle

RAS cycle CAS cycle RAS precharge

2CAS cycle

2 2

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,,,,

,,,,,

RD data

,,,,,

WR data

,,,

WR data

COL #1 COL #2

DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle

1 1

RPC delay Fixed Refresh RAS pulse width

2RAS precharge

tRPC tCSR tCHR

tRAS

BCLK

#RAS

#CAS

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-101

DRAM: 60ns, CPU: 20MHz, random read/write cycle

RAS cycle CAS cycle RAS precharge

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,

ROW #2

,,,,,

WR data

,,,

COL #1

DRAM: 60ns, CPU: 20MHz, page-mode read/write cycle

RAS cycle CAS cycle RAS precharge

2CAS cycle

2 1

tRAS

BCLK

A[11:0]

#RAS

#CAS

#RD

D[15:0](RD)

#WE

D[15:0](WR)

ROW #1

RD data

,,,,,,

,,,,,

RD data

,,,,,

WR data

,,,

WR data

COL #1 COL #2

DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle

1 1

RPC delay Fixed Refresh RAS pulse width

2RAS precharge

tRPC tCSR tCHR

tRAS

BCLK

#RAS

#CAS

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-102 EPSON S1C33209/221/222 PRODUCT PART

A.3 ROM and Burst ROM

Burst ROM and mask ROM interface setup examples

Operating Normal read cycle Burst read cycle Output disable

frequency Wait cycle Read cycle Wait cycle Read cycle delay cycle

20MHz 2 3 1 2 1.5

25MHz 3 4 1 2 1.5

33MHz 4 5 2 3 1.5

Burst ROM and mask ROM interface timing

Burst ROM and mask ROM interface 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Access time tACC – 100 5 150 4 160 3 150

#CE output delay time tCE – 100 5 150 4 160 3 150

#OE output delay time tOE – 50 4.5 135 3.5 140 2.5 125

Burst access time tBAC – 50 3 90 2 80 2 100

Output disable delay time tDF 0 40 1.5 45 1.5 60 1.5 75

ROM: 100ns, CPU: 33MHz, normal read

tACC

tCE

tOE

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,,,

,,,,,,,,,,,,,,,

,,,,

tDF

ROM: 100ns, CPU: 33MHz, burst read

Normal read cycle Burst read cycle

tBAC tBAC tBAC

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,

,,,,,,,,

,,,

RD data

,,,,,

RD data

,,,,,

RD data

,,,,,

tDF

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-103

ROM: 100ns, CPU: 25MHz, normal read

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,,,

,,,,,,,,,,,

,,,,

ROM: 100ns, CPU: 25MHz, burst read

Normal read cycle Burst read cycle

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,

,,,,,,

,,,

RD data

,,,

RD data

,,,

RD data

,,,

ROM: 100ns, CPU: 20MHz, normal read

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,,,

,,,,,,,

,,,,

ROM: 100ns, CPU: 20MHz, burst read

Normal read cycle Burst read cycle

BCLK

A[23:0]

#CE9, 10

#RD

D[15:0] RD data

,,,

,,,,

,,,

RD data

,,,

RD data

,,,

RD data

,,,

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-104 EPSON S1C33209/221/222 PRODUCT PART

A.4 SRAM (55ns)

SRAM interface setup examples – 55ns

Operating Read cycle Write cycle Output disable

frequency Wait cycle Read cycle delay time

20MHz 1 2 2 1.5

25MHz 2 3 3 1.5

33MHz 2 3 3 1.5

SRAM interface timing – 55ns

SRAM interface 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Read cycle time tRC 55 – 3 90 3 120 2 100

Address access time tACC – 55 3 90 3 120 2 100

#CE access time tACS – 55 3 90 3 120 2 100

#OE access time tOE – 30 2.5 75 2.5 100 1.5 75

Output disable delay time tOHZ 0 30 1.5 45 1.5 60 1.5 75

Write c ycle time tWC 55 – 3 90 3 120 2 100

Address enable time tAW 50 – 2.5 75 2.5 100 1.5 75

Write pulse width tWP 45 – 2 60 2 80 1 50

Input data setup time tDW 30 – 2 60 2 80 1 50

Input data hold time tDH 0 – 0.5 15 0.5 20 0.5 25

SRAM: 55ns, CPU: 33/25MHz , read cycle

tRC

tACC

tACS

tOE

BCLK

A[23:0]

#CEx

#RD

D[15:0] RD data

,,,,,

,,,,,,,,,

,,,,

tOHZ

SRAM: 55ns, CPU: 33/25MHz, write cycle

tWC

tAW

tWP

tDW

BCLK

A[23:0]

#CEx

#WP

D[15:0] WR data

,,,,,

,,,

tDH

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-105

SRAM: 55ns, CPU: 20MHz, read cycle

BCLK

A[23:0]

#CEx

#RD

D[15:0] RD data

,,,,,

,,,,

SRAM: 55ns, CPU: 20MHz, write cycle

BCLK

A[23:0]

#CEx

#WP

D[15:0] WR data

,,,,,

,,,

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-106 EPSON S1C33209/221/222 PRODUCT PART

A.5 SRAM (70ns)

SRAM interface setup examples – 70ns

Operating Read cycle Write cycle Output disable

frequency Wait cycle Read cycle delay time

20MHz 2 3 3 1.5

25MHz 2 3 3 1.5

33MHz 3 4 4 1.5

SRAM interface timing – 70ns

SRAM interface 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Read cycle time tRC 70 – 4 120 3 120 3 150

Address access time tACC – 70 4 120 3 120 3 150

#CE access time tACS – 70 4 120 3 120 3 150

#OE access time tOE – 40 3.5 105 2.5 100 2.5 125

Output disable delay time tOHZ 0 30 1.5 45 1.5 60 1.5 75

Write cycle time tWC 70 – 4 120 3 120 3 150

Address enable time tAW 60 – 3.5 105 2.5 100 2.5 125

Write pulse width tWP 55 – 3 90 2 80 2 100

Input data setup time tDW 30 – 3 90 2 80 2 100

Input data hold time tDH 0 – 0.5 15 0.5 20 0.5 25

SRAM: 70ns, CPU: 33MHz, read cycle

tRC

tACC

tACS

tOE

BCLK

A[23:0]

#CEx

#RD

D[15:0] RD data

,,,,,

,,,,,,,,,,,,,

,,,,

tOHZ

SRAM: 70ns, CPU: 33MHz, write cycle

tWC

tAW

tWP

tDW

BCLK

A[23:0]

#CEx

#WP

D[15:0] WR data

,,,,,

,,,

tDH

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

S1C33209/221/222 PRODUCT PART EPSON A-107

SRAM: 70ns, CPU: 25/20MHz, read cycle

BCLK

A[23:0]

#CEx

#RD

D[15:0] RD data

,,,,,

,,,,,,,,,

,,,,

SRAM: 70ns, CPU: 25/20MHz, write cycle

BCLK

A[23:0]

#CEx

#WP

D[15:0] WR data

,,,,,

,,,

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-108 EPSON S1C33209/221/222 PRODUCT PART

A.6 8255A

8255A interface setup examples

Operating Read cycle Write cycle Output disable

frequency Wait cycle Read cyc le delay time

20MHz 9 ∗110103.5

25MHz 11 12 12 3.5

33MHz 14 15 15 3.5 ∗2

8255A interface timing

SRAM interface 33MHz 25MHz 20MHz

Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time

Read cycle time tRC 300 – 15 450 12 480 10 500

Address access time tACC – 250 15 450 12 480 10 500

#CE access time tACS – 250 15 450 12 480 10 500

#OE access time tOE – 250 14.5 435 11.5 460 9.5 475

Output disable delay time tOHZ 10 150 3.5 105 3.5 140 3.5 175

Write cycle time tWC 430 – 15 450 12 480 10 500

Address enable time tAW 400 – 14.5 435 11.5 460 9.5 475

Write pulse width tWP 400 – 14 420 11 440 9 450

Input data setup time tDW 100 – 14 420 11 440 9 450

Input data hold time

∗3tDH 30 – 0.5 15 0.5 20 0.5 25

∗1 The S1C33209/221/222 enables up to 7 cycles of wait-cycle insertion. If a number of wait cycles more than 7

cycles needs to be inserted, input the #WAIT signal from external hardware. Note that the interface must be set for

SRAM type devices to insert wait cycles using the #WAIT pin. (Refer to "BCU (Bus Control Unit)" in the

"S1C33209/221/222 FUNCTION PART", for more information.)

∗2 This setting cannot satisfy the 150 ns of output-disable delay time specification required for the 8255A. When

implementing such a low-speed device in the system, the external bus must be separated by inserting a 3-state bus

buffer at the output side (when viewed from the CPU) of the external system bus.

∗3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the

external data bus D[15:0] or by inserting a latch at the output side of the external system interface.

APPENDIX B PIN CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-109

Appendix B Pin Characteristics

Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks

QFP5 QFP15 name Input Output down supply

1 126 P24/TM2/#SRDY2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

2 127 VSS XVSS

3 128 P25/TM3/#SCLK2 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

4 1 P26/TM4/SOUT2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

5 2 P15/EXCL4/#DMAEND0/

#SCLK3 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

6 3 P27/TM5/SIN2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

7 4 BCLK XHTB1T Type1 VDDE

8 5 P00/SIN0 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

9 6 P01/SOUT0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

10 7 D15 XHBC1T CMOS/LVTTL Type1 VDDE note 1

11 8 VDD XLVDD

12 9 P03/#SRDY0 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

13 10 D14 XHBC1T CMOS/LVTTL Type1 VDDE note 1

14 11 P31/#BUSGET/#GARD XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

15 12 D13 XHBC1T CMOS/LVTTL Type1 VDDE note 1

16 13 P32/#DMAACK0/#SRDY3 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

17 14 D12 XHBC1T CMOS/LVTTL Type1 VDDE note 1

18 15 P33/#DMAACK1/SIN3 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

19 16 D11 XHBC1T CMOS/LVTTL Type1 VDDE note 1

20 17 K54/#DMAREQ3 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE

21 18 D10 XHBC1T CMOS/LVTTL Type1 VDDE note 1

22 19 K53/#DMAREQ2 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE

23 20 D9 XHBC1T CMOS/LVTTL Type1 VDDE note 1

24 21 K52/#ADTRG XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE

25 22 VSS XVSS

26 23 K51/#DMAREQ1 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE

27 24 P02/#SCLK0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

28 25 D8 XHBC1T CMOS/LVTTL Type1 VDDE note 1

29 26 D7 XHBC1T CMOS/LVTTL Type1 VDDE note 1

30 27 VDDE XHVDD

31 28 K67/AD7 XHIBCLIN CMOS/LVTTL AVDDE note 2

32 29 K66/AD6 XHIBCLIN CMOS/LVTTL AVDDE note 2

33 30 K65/AD5 XHIBCLIN CMOS/LVTTL AVDDE note 2

34 31 K50/#DMAREQ0 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up AVDDE note 2

35 32 K64/AD4 XHIBCLIN CMOS/LVTTL AVDDE note 2

36 33 K63/AD3 XHIBCLIN CMOS/LVTTL AVDDE note 2

37 34 K62/AD2 XHIBCLIN CMOS/LVTTL AVDDE note 2

38 35 AVDDE

39 36 K61/AD1 XHIBCLIN CMOS/LVTTL AVDDE note 2

40 37 K60/AD0 XHIBCLIN CMOS/LVTTL AVDDE note 2

41 38 D6 XHBC1T CMOS/LVTTL Type1 VDDE note 1

42 39 VSS XVSS

43 40 D5 XHBC1T CMOS/LVTTL Type1 VDDE note 1

44 41 D4 XHBC1T CMOS/LVTTL Type1 VDDE note 1

45 42 D3 XHBC1T CMOS/LVTTL Type1 VDDE note 1

46 43 D2 XHBC1T CMOS/LVTTL Type1 VDDE note 1

47 44 D1 XHBC1T CMOS/LVTTL Type1 VDDE note 1

48 45 D0 XHBC1T CMOS/LVTTL Type1 VDDE note 1

49 46 P35/#BUSACK XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

50 47 VDDE XHVDD

APPENDIX B PIN CHARACTERISTICS

A-110 EPSON S1C33209/221/222 PRODUCT PART

Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks

QFP5 QFP15 name Input Output down supply

51 48 #CE9/#CE17 XHBC1T note 4 Type1 V DDE

52 49 OSC2 XLLOT VDD

53 50 #CE7/#RAS0/#CE13/

#RAS2 XHBC1T note 4 Type1 V DDE

54 51 OSC1 XLLIN VDD note 3

55 52 #CE6 XHBC1T note 4 Type1 VDDE

56 53 #RD XHBC1T note 4 Type1 V DDE

57 54 VSS XVSS

58 55 #WRL/#WR/#WE XHBC1T note 4 Type1 VDDE

59 56 #WRH/#BSH XHBC1T note 4 Type1 V DDE

60 57 #CE10EX XHBC1T note 4 Type1 V DDE

61 58 #CE8/#RAS1/#CE14/

#RAS3 XHBC1T note 4 Type1 V DDE

62 59 #CE5/#CE15 XHBC1T note 4 Type1 V DDE

63 60 #CE4/#CE11 XHBC1T note 4 Type1 V DDE

64 61 P30/#WAIT/#CE4&5 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

65 62 #RESET XHIBHP2 CMOS/LVTTL SCHMITT Pull-up V DDE

66 63 #NMI XHIBHP2 CMOS/LVTTL SCHMITT Pull-up V DDE

67 64 A0/#BSL XHBC1T note 4 Type1 V DDE

68 65 A1 XHBC1T note 4 Type1 V DDE

69 66 P34/#BUSREQ/#CE6 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

70 67 VSS XVSS

71 68 A2 XHBC1T note 4 Type1 V DDE

72 69 A3 XHBC1T note 4 Type1 V DDE

73 70 A4 XHBC1T note 4 Type1 V DDE

74 71 A5 XHBC1T note 4 Type1 V DDE

75 72 A6 XHBC1T note 4 Type1 V DDE

76 73 #CE10IN XHTB1T Type1 VDDE

77 74 VDD XLVDD

78 75 #EMEMRD XHTB1T Type1 VDDE

79 76 A7 XHBC1T note 4 Type1 V DDE

80 77 #HCAS/#UWE XHTB1T Type1 VDDE

81 78 A8 XHBC1T note 4 Type1 V DDE

82 79 #LCAS/#CAS XHTB1T Type1 VDDE

83 80 A9 XHBC1T note 4 Type1 V DDE

84 81 P16/EXCL5/#DMAEND1/

SOUT3 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

85 82 A10 XHBC1T note 4 Type1 V DDE

86 83 A20 XHBC1T note 4 Type1 V DDE

87 84 A11 XHBC1T note 4 Type1 V DDE

88 85 A21 XHBC1T note 4 Type1 V DDE

89 86 A12 XHBC1T note 4 Type1 V DDE

90 87 A22 XHBC1T note 4 Type1 V DDE

91 88 A13 XHBC1T note 4 Type1 V DDE

92 89 A23 XHBC1T note 4 Type1 V DDE

93 90 VSS XVSS

94 91 A14 XHBC1T note 4 Type1 V DDE

95 92 A15 XHBC1T note 4 Type1 V DDE

96 93 VDDE XHVDD

97 94 A16 XHBC1T note 4 Type1 V DDE

98 95 ICEMD XITST1 Pull-down Test pin

99 96 A17 XHBC1T note 4 Type1 V DDE

100 97 A18 XHBC1T note 4 Type1 V DDE

APPENDIX B PIN CHARACTERISTICS

S1C33209/221/222 PRODUCT PART EPSON A-111

Pin No. Signal name I/O cell Characteristic Pull-up/ Power Remarks

QFP5 QFP15 name Input Output down supply

101 98 A19 XHBC1T note 4 Type1 V DDE

102 99 P04/SIN1/#DMAACK2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

103 100 P05/SOUT1/#DMAEND2 XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

104 101 P06/#SCLK1/#DMAACK3 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

105 102 VSS XVSS

106 103 PLLC XLLIN

107 104 VSS XVSS

108 105 PLLS1 XHIBC CMOS/LVTTL VDDE

109 106 PLLS0 XHIBC CMOS/LVTTL VDDE

110 107 P07/#SRDY1/#DMAEND3 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

111 108 #X2SPD XHIBC CMOS/LVTTL VDDE

112 109 EA10MD0 XHIBC CMOS/LVTTL VDDE

113 110 EA10MD1 XHIBCP2 CMOS/LVTTL Pull-up VDDE

114 111 VDD XLVDD

115 112 (No Connection)

116 113 OSC4 XLLOT VDD

117 114 P20/#DRD XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

118 115 OSC3 XLLIN VDD note 3

119 116 P21/#DWE/#GAAS XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE

120 117 #CE3 XHTB1T Type1 VDDE

121 118 P22/TM0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

122 119 P23/TM1 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE

123 120 DSIO XLBH2P2T CMOS/LVTTL SCHMITT Type2 Pull-up VDD note 3

124 121 P10/EXCL0/T8UF0/DST0 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 3

125 122 P11/EXCL1/T8UF1/DST1 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 3

126 123 P12/EXCL2/T8UF2/DST2 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 3

127 124 P13/EXCL3/T8UF3/DPCO XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 3

128 125 P14/FOSC1/DCLK XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 3

note 1) In the S1C33209F00A *, the pins for the data bus are set for the TTL interface (I/O cell name: XHBT1T,

output characteristics: Type1).

note 2) The voltage applied to this pin must be 0V ≤ VIN ≤ AVDDE.

Note that the input voltage range for the K50 pin differs from other K5 pins.

note 3) The voltage applied to this pin must be 0V ≤ VIN ≤ VDD.

note 4) This pin is set as an input pin during device testing. Normally it is an output pin.

The following table lists output current characteristics.

Output current (IOL/IOH)5.0V 3.3V 2.0V

Type1 3mA 2mA 0.6mA

Type2 – 6mA 2mA

S1C33209/221/222

FUNCTION PART

S1C33209/221/222 FUNCTION PART

I OUTLINE

I OUTLINE: INTRODUCTION

S1C33209/221/222 FUNCTION PART EPSON B-I-1-1

I-1 INTRODUCTION

The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original

32-bit microcomputer S1C33209/221/222.

The S1C33209/221/222 employs a RISC type CPU, and has a powerful instruction set capable of compilation into

compact code, despite the small CPU core size.

The S1C33209 has the following features:

• Small CPU core: 25K gates

• Fast and high performance: DC to 60 MHz operation

• Strong instruction set: 16-bit fixed length, 105 basic instructions

• Execution cycle: Major instructions are executed in 1 cycle per instruction

• MAC function: 16 bits × 16 bits + 64 bits, 2 clock per MAC (25 MOPS in 50 MHz)

• Registers: 32 bits × 16 general registers and 32 bits × 5 special registers

• Memory space: 256M bytes (28 bits) linear space, code-data-IO shared type

• External bus I/F: 15 configurable memory areas

Direct connection to external memory

• Interrupts: Reset, NMI, up to 128 external interrupts, 4 software interrupts, 2 exceptions

• Reset, boot: Cold reset, hot reset

• Power down mode: Sleep, Halt

• Others: Little endian (partial big endian can be configured)

Harvard architecture (fetch, load/store parallel execution)

• User logic interface: Programmable wait state (up to 7 cycles)

#WAIT pin hand shake is possible.

Large memory space for the user logic (up to 16M bytes)

BCU configuration registers allow internal use of the external areas (Areas 4 to 18).

Many interrupt requests from the user logic are acceptable.

I OUTLINE: INTRODUCTION

B-I-1-2 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

I OUTLINE: BLOCK DIAGRAM

S1C33209/221/222 FUNCTION PART EPSON B-I-2-1

I-2 BLOCK DIAGRAM

The S1C33209/221/222 consists of five major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block,

C33 DMA Block and C33 Internal Memory Block.

Figure 2.1 shows the configuration of the S1C33 blocks.

CORE_PAD

Pads

C33_SBUS

Internal RAM

(Area 0) Internal ROM

(Area 10)

C33 Core Block

C33 Internal Memory BlockC33 DMA Block

PERI_PAD

Pads

C33_PERI

(Prescaler, 8-bit timer, 16-bit timer,

Clock timer, Serial interface, Ports)

C33 Peripheral BlockC33 Analog Block

C33_CORE

(CPU, BCU, ITC, CLG, DBG)

C33_ADC

(A/D converter)

C33_DMA

(IDMA, HSDMA)

Figure 2.1 Block Configuration

Note: Internal ROM is not provided in th e S1C33209.

I OUTLINE: BLOCK DIAGRAM

B-I-2-2 EPSON S1C33209/221/222 FUNCTION PART

C33 Core Block

The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC

(Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface,

and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.

The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU.

C33 Peripheral Block

The C33 Peripheral Block consists of a prescaler, six channels of 8-bit programmable timer, six channels of

16-bit programmable timer including watchdog timer function, four channels of serial interface, input and I/O

ports, and a clock timer.

C33 Analog Block

The analog block consists of an A/D converter with eight inp ut channels.

C33 DMA Block

The DMA block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-

chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory

area for storing DMA command information.

C33 Memory Block

The following internal memory area are provided;

S1C33209: 8 KB SRAM

S1C33221: 8 KB SRAM and 128 KB ROM

S1C33222: 8 KB SRAM and 64 KB ROM

For details of the blocks, refer to the respective section in this manual.

I OUTLINE: LIST OF PINS

S1C33209/221/222 FUNCTION PART EPSON B-I-3-1

I-3 LIST OF PINS

List of External I/O Pins

The following lists the external I/O pins of the C33 Core Block and Peripheral Block. Note that some pins are listed

in two or more tables.

Table 3.1 List of Pins for External Bus Interface Signals

Pin name I/O Pull-up Function

#BSL O – A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)

#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"

A[23:1] O – Address bus (A1 to A23)

D[15:0] I/O – Data bus (D0 to D15)

#CE10EX O – Area 10 chip enable for external memory

* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.

#CE10IN O – Area 10 chip enable for internal ROM emulation

#CE9

#CE17 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default)

#CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.

#CE8

#RAS1

#CE14

#RAS3

O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" and A8DRA(D8/0x48128) = "0"

(default)

#RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) = "00" and

A8DRA(D8/0x48128) = "1"

#CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" or "1x" and

A14DRA(D8/0x48122) = "0"

#RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) = "01"or "1x" and

A14DRA(D8/0x48122) = "1"

#CE7

#RAS0

#CE13

#RAS2

O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" and A7DRA(D7/0x48128) = "0"

(default)

#RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) = "00" and

A7DRA(D7/0x48128) = "1"

#CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" or "1x" and

A13DRA(D7/0x48122) = "0"

#RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) = "01" or "1x" and

A13DRA(D7/0x48122) = "1"

#CE6 O – Area 6 chip enable

* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.

#CE5

#CE15 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default)

#CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.

#CE4

#CE11 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default)

#CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.

#CE3 O – Area 3 chip enable

#RD O – Read signal

#EMEMRD O – Read signal for internal ROM emulation memory

#WRL

#WR

#WE

O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#WR: Write signal when SBUSST(D3/0x4812E) = "1"

#WE: DRAM write signal

#WRH

#BSH O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"

#HCAS O – #HCAS: DRAM column address strobe (high byte) signal

#LCAS O – #LCAS: DRAM column address strobe (low byte) signal

BCLK O – Bus clock output

P34

#BUSREQ

#CE6

I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"

#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1"

P35

#BUSACK I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1"

I OUTLINE: LIST OF PINS

B-I-3-2 EPSON S1C33209/221/222 FUNCTION PART

Pin name I/O Pull-up Function

P30

#WAIT

#CE4&5

I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"

#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

IOC30(D0/0x402DE) = "1"

P20

#DRD I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1"

P21

#DWE

#GAAS

I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF) = "0" (default)

#DWE: DRAM read signal output for successive RAS mode when CFP21(D1/0x402D8) = "1" and

CFEX2(D2/0x402DF) = "0"

#GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

P31

#BUSGET

#GARD

I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default)

#BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF)

= "0"

#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"

EA10MD1 I Pull-up Area 10 boot mode selection

EA10MD1 EA10MD0 Mode

1 1 External ROM mode

EA10MD0 I – 1 0 Internal ROM mode

0 1 OTP mode

0 0 Internal ROM emulation mode

Table 3.2 List of Pins for HSDMA Control Signals

Pin name I/O Pull-up Function

K50

#DMAREQ0 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)

#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"

K51

#DMAREQ1 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)

#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"

K53

#DMAREQ2 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)

#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"

K54

#DMAREQ3 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)

#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"

P32

#DMAACK0

#SRDY3

I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" (default)

#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1"

#SRDY3: Serial I/F Ch.3 ready signal input/output when SSRDY3 (D3/0x402D7) = "1" and

CFP32(D2/0x402DC) = "0"

P33

#DMAACK1

SIN3

I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" (default)

#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1"

SIN3: Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1" and CFP33(D3/0x402DC) = "0"

P04

SIN1

#DMAACK2

I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default)

SIN1: Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"

P06

#SCLK1

#DMAACK3

I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0" ( default)

#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and

CFEX6(D6/0x402DF) = "0"

#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"

P15

EXCL4

#DMAEND0

#SCLK3

I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6)

= "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1" and

IOC15(D5/0x402D6) = "1"

#SCLK3: Serial I/F Ch.3 clock input/output when SSCLK3(D2/0x402D7) = "1" and CFP15(D5/0x402D4)

= "0"

P16

EXCL5

#DMAEND1

SOUT3

I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6)

= "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and

IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch.3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0"

I OUTLINE: LIST OF PINS

S1C33209/221/222 FUNCTION PART EPSON B-I-3-3

Pin name I/O Pull-up Function

P05

SOUT1

#DMAEND2

I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1"

P07

#SRDY1

#DMAEND3

I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" (default)

#SRDY1: Serial I/F Ch. 1 ready signal input/output when CFP07(D7/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1"

Table 3.3 List of Pins for Internal Peripheral Circuits

Pin name I/O Pull-up Function

K52

#ADTRG I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)

#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"

K60

AD0 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)

AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"

K61

AD1 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)

AD1: A/ D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"

K62

AD2 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)

AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"

K63

AD3 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)

AD3: A/ D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"

K64

AD4 I – K64: Input port when CFK64(D4/0x402C3) = "0" (default)

AD4: A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"

K65

AD5 I – K65: Input port when CFK65(D5/0x402C3) = "0" (default)

AD5: A/ D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"

K66

AD6 I – K66: Input port when CFK66(D6/0x402C3) = "0" (default)

AD6: A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1"

K67

AD7 I – K67: Input port when CFK67(D7/0x402C3) = "0" (default)

AD7: A/ D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"

P00

SIN0 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)

SIN0: Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"

P01

SOUT0 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)

SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"

P02

#SCLK0 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)

#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1"

P03

#SRDY0 I/O – P03: I/O port when CFP03(D3/0x 402D0) = "0" (default)

#SRDY0: Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1"

P04

SIN1

#DMAACK2

I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default)

SIN1: Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"

P05

SOUT1

#DMAEND2

I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"(default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1"

P06

#SCLK1

#DMAACK3

I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"(default)

#SCLK1: Ser ial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and CFEX6(D6/0x402DF)

= "0"

#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"

P07

#SRDY1

#DMAEND3

I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"(default)

#SRDY1: Serial I/F Ch. 1 ready signal input/output when CFP07(D7/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1"

P10

EXCL0

T8UF0

DST0

I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "0"

and CFEX1(D1/0x402DF) = "0"

T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and

CFEX1(D1/0x402DF) = "0"

DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)

I OUTLINE: LIST OF PINS

B-I-3-4 EPSON S1C33209/221/222 FUNCTION PART

Pin name I/O Pull-up Function

P11

EXCL1

T8UF1

DST1

I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "0"

and CFEX1(D1/0x402DF) = "0"

T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "1" and

CFEX1(D1/0x402DF) = "0"

DST1: DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)

P12

EXCL2

T8UF2

DST2

I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"

EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "0"

and CFEX0(D0/0x402DF) = "0"

T8UF2: 8-bit timer 2 output whe n CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "1" and

CFEX0(D0/0x402DF) = "0"

DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)

P13

EXCL3

T8UF3

DPCO

I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "0"

and CFEX1(D1/0x402DF) = "0"

T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "1" and

CFEX1(D1/0x402DF) = "0"

DPCO: DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)

P14

FOSC1

DCLK

I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"

FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and CFEX0(D0/0x402DF) = "0"

DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)

P15

EXCL4

#DMAEND0

#SCLK3

I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6)

= "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1" and

IOC15(D5/0x402D6) = "1"

#SCLK3: Serial I/F Ch.3 clock input/output when SSCLK3(D2/0x402D7) = "1" and CFP15(D5/0x402D4)

= "0"

P16

EXCL5

#DMAEND1

SOUT3

I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6)

= "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and

IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch.3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0"

P20

#DRD I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1"

P21

#DWE

#GAAS

I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF) = "0" (default)

#DWE: DRAM read signal output for successive RAS mode when CFP21(D1/0x402D8) = "1" and

CFEX2(D2/0x402DF) = "0"

#GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

P22

TM0 I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)

TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"

P23

TM1 I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)

TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"

P24

TM2

#SRDY2

I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)

TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1"

#SRDY2: Serial I/F Ch.2 ready signal input/output when SSRDY2(D3/0x402DB) = "1" and CFP24

(D4/0x402D8) = "0"

P25

TM3

#SCLK2

I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)

TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1"

#SCLK2: Serial I/F Ch.2 clock input/output when SSCLK2(D2/0x402DB) = "1" and

CFP25(D5/0x402D8) = "0"

P26

TM4

SOUT2

I/O – P26: I/O port when CFP26(D6/0x402D8) = "0" (default)

TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1"

SOUT2: Serial I/F Ch.2 data output when SSOUT2(D1/0x402DB) = "1" and CFP26(D6/0x402D8) = "0"

P27

TM5

SIN2

I/O – P27: I/O port when CFP27(D7/0x402D8) = "0" (default)

TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1"

SIN2: Serial I/F Ch.2 data input when SSIN2(D0/0x402DB) = "1" and CFP27(D7/0x402D8) = "0"

I OUTLINE: LIST OF PINS

S1C33209/221/222 FUNCTION PART EPSON B-I-3-5

Table 3.4 List of Pins for Clock Generator

Pin name I/O Pull-up Function

OSC1 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input)

OSC2 O – Low-speed (OSC1) oscillation output

OSC3 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input)

OSC4 O – High-speed (OSC3) oscillation output

PLLS[1:0] I – PLL set-up pins

PLLS1 PLLS0 fin (fOSC3) fout (fPSCIN)

1 1 10–30MHz 20–60MHz *1

10–25MHz 20–50MHz *2

0 1 10–15MHz 40–60MHz *1

10–12.5MHz 40–50MHz *2

0 0 PLL is not used L

*1: ROM-less model with 3.3 V ± 0.3 V operating voltage

*2: ROM built-in model, or 3.0 V ± 0.3 V operating voltage

PLLC – – Capasitor connecting pin for PLL

Table 3.5 List of Other Pins

Pin name I/O Pull-up Function

/down

ICEMD I Pull-

down High-impedance control input pin

When this pin is set to High, all the output pins go into high-impedance state. This makes it possible to disable

the S1C33 chip on the board.

DSIO I/O Pull-up Serial I/O pin for debugging

This pin is used to communicate with the debugging tool S5U1C33000H.

#X2SPD I – Clock doubling mode set-up pin1: CPU clock = bus clock x 1, 0: CPU clock = bus clock x 2

#NMI I Pull-up NMI request input pin

#RESET I Pull-up Initial reset input pin

Note:"#" in the pin names indicates that the signal is low active.

I OUTLINE: LIST OF PINS

B-I-3-6 EPSON S1C33209/221/222 FUNCTION PART

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S1C33209/221/222 FUNCTION PART

II CORE BLOCK

II CORE BLOCK: INTRODUCTION

S1C33209/221/222 FUNCTION PART EPSON B-II-1-1

II-1 INTRODUCTION

The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt

Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS

(Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.

CORE_PAD

Pads

C33_SBUS

Internal RAM

(Area 0)

C33 Core Block

C33 Internal Memory BlockC33 DMA Block

PERI_PAD

Pads

C33_PERI

(Prescaler, 8-bit timer, 16-bit timer,

Clock timer, Serial interface, Ports)

C33 Peripheral BlockC33 Analog Block

C33_CORE

(CPU, BCU, ITC, CLG, DBG)

C33_ADC

(A/D converter)

C33_DMA

(IDMA, HSDMA) Internal ROM

(Area 10)

Figure 1.1 Core Block

Note: Internal ROM is not provided in the S1C33209.

II CORE BLOCK: INTRODUCTION

B-II-1-2 EPSON S1C33209/221/222 FUNCTION PART

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II CORE BLOCK: CPU AND OPERATING MODE

S1C33209/221/222 FUNCTION PART EPSON B-II-2-1

II-2 CPU AND OPERATING MODE

CPU

The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. Since it has a built-in multiplier,

all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication and

accumulation) instruction and the multiplication/division instructions are available.

All the internal registers of the S1C33000 can be used. The CPU registers and CPU address bus can handle 28-bit

addresses. However, the core block has a 24-bit external address bus (A[0:23]), so the low-order 24 bits of address

data can only be delivered to the external address bus and the internal address bus which is connected to the User

Logic Block.

Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000.

II CORE BLOCK: CPU AND OPERATING MODE

B-II-2-2 EPSON S1C33209/221/222 FUNCTION PART

Standby Mode

The CPU supports three standby modes: two HALT modes and a SLEEP mode.

By setting the CPU in the standby mode, power consumption can greatly be reduced.

HALT Mode

When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode.

The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected using

the HLT2OP (D3) / Clock option register (0x40190).

The CPU stops operating in basic HALT mode, so the amount of current consumption can be reduced. The internal

peripheral circuits including the oscillation circuit keep operating in basic HALT mode.

HALT2 mode stops the external bus control functions including DMA and the bus clock as well as the CPU similar to

basic HALT mode. Consequently, HALT2 mode realizes more power saving than the basic HALT mode.

The HALT mode is canceled by an initial reset or an inte rrupt including NMI. This mode is useful for saving power

when waiting for an external input or completion of the peripheral circuit operations that do not need to execute the

CPU.

The CPU transits to program execution status through trap processing when the HALT mode is canceled by an

interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the

instruction that follows the executed halt instruction into the stack. Therefore, when the interrupt processing routine

is terminated by the reti instruction, the program flow returns to the instruction that follows the halt instruction.

Note that the HALT mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into

interrupt disabled status.

SLEEP Mode

When the CPU executes the slp instruction, it suspends the program execution and enters SLEEP mode.

In SLEEP mode, the CPU and the internal peripheral circuits including the high-speed (OSC3) oscillation circuit stop

operating. Thus SLEEP mode can greatly reduce current consumption in comparison to HALT mode. Moreover, the

low-speed (OSC1) oscillation circuit and clock timer do not stop operating. The clock function keeps operating in

SLEEP mode.

SLEEP mode is canceled by an initial reset or an interrupt (NMI, clock timer interrupt, external interrupt such as a

key entry). Note that other interrupts by the internal peripheral circuits that use the OSC3 clock cannot be used for

canceling SLEEP mode.

The CPU transits to program execution status through trap processing when the SLEEP mode is canceled by an

interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the

instruction that follows the executed slp instruction into the stack. T herefore, when the interrupt processing routine is

terminated by the reti instruction, the program flow returns to the instruction that follows the slp instruction.

Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into

interrupt disabled status.

II CORE BLOCK: CPU AND OPERATING MODE

S1C33209/221/222 FUNCTION PART EPSON B-II-2-3

Notes on Standby Mode

Interrupts

The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used

for canceling the standby mode before setting the CPU in t he standby mode. It is also necessary to set the IE

(interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt. Otherwise,

the standby mode cannot be canceled even when an interrupt occurs. Refer to "ITC (Interrupt Controller)", for

interrupt settings.

Oscillation circuit

The high-speed (OSC3) oscillation circuit stops in SLEEP mode and restarts oscillating when SLEEP mode is

canceled. If the CPU had operated with the OSC3 clock before entering SLEEP mode, the CPU restarts

operating with the OSC3 clock immediately after canceling SLEEP mode. However, the OSC3 oscillation

needs appropriate stabilization time (10 ms max. under the standard condition in 3.3 V). To restart the CPU

after the oscillation stabilizes, a programmable interval can be inserted between cancellation of SLEEP mode

and starting the CPU operation. Refer to "CLG (Clock Generator)", for details.

The oscillation start time of the high-speed (OSC3) oscillation circuit varies according to the components to be

used, board pattern and operating environment. The interval must be set to allow enough margin.

BCUWhen the CPU enters the standby mode, the BCU (bus control unit) stops after the current bus cycle has

completed. All the chip enable signals are negated.

In basic HALT mode, the BCLK (bus clock) signal is output and DRAM refresh cycles are generated. DMA

also operates.

In HALT2 or SLEEP mode, the BCLK signal stops, therefore DRAM refresh cycles cannot be generated and

DMA stops.

Additional

The contents of the CPU registers and input/output port status are retained in the standby mode. Almost all

control and data registers of the internal peripheral circuits are also retained, note, however, some registers may

be changed at the transition to SLEEP mode. Refer to the section of each peripheral circuit for other

precautions.

Test Mode

The C33 Core Block has the ICEMD pin for testing the chip. When this pin is set to High, the IC enters the following

state:

• All output pins go into high-impeda nce state except for the clock output pins (OSC2: H, OSC4 H, PLLC: L).

• Clock inputs are disabled. OSC1, OSC3 and PLL stop operating. OSC2: H, OSC4 H, PLLC: L

• All the pull-up and pull-down resistors enter an inactive state.

Leave this pin open or connect to VSS for normal operation. The ICEMD pin has a built-in pull-down resistor.

Debug Mode

The C33 Core Block supports the debug mode.

The debug mode is a CPU function, and realizes single step operation and break functions in the chip itself. Refer to

the "S1C33000 Core CPU Manual" for details of the debug mode and the functions.

Area 2 in the memory map can only be accessed in the debug mode.

In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed

(OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the

debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating.

II CORE BLOCK: CPU AND OPERATING MODE

B-II-2-4 EPSON S1C33209/221/222 FUNCTION PART

Trap Table

Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions

and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts.

Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-b it timer interrupts.

Refer to Section III-8, "Serial Interface", for details of the settings.

Table 2.1 Trap Table

HEX

No. Vector number

(Hex address) Exception/interrupt name Exception/interrupt factor IDMA

Ch. Priority

0 0(Base) Reset Low input to the reset pin – High

1–3 reserved – – ↑

4 4(Base+10) Zero division Division instruction –

5 5 reserved – –

6 6(Base+18) Address error exception Memory access instruction –

7 0x0 or 0x60000 Debugging exception brk instruction, etc. –

8 8(Base+1C) NMI Low input to the NMI pin –

9–11 reserved – –

C 12(Base+30) Software exception 0 int instruction –

D 13(Base+34) Software exception 1 int instruction –

E 14(Base+38) Software exception 2 int instruction –

F 15(Base+3C) Software exception 3 int instruction –

10 16(Base+40) Port input interrupt 0 Edge (rising or falling) or level (High or Low) 1

11 17(Base+44) Port input interrupt 1 Edge (rising or falling) or level (High or Low) 2

12 18(Base+48) Port input interrupt 2 Edge (rising or falling) or level (High or Low) 3

13 19(Base+4C) Port input interrupt 3 Edge (rising or falling) or level (High or Low) 4

14 20(Base+50) Key input interrupt 0 Rising or falling edge –

15 21(Base+54) Key input interrupt 1 Rising or falling edge –

16 22(Base+58) High-speed DMA Ch.0 High-speed DMA Ch.0, end of transfer 5

17 23(Base+5C) High-speed DMA Ch.1 High-speed DMA Ch.1, end of transfer 6

18 24(Base+60) High-speed DMA Ch.2 High-speed DMA Ch.2, end of transfer –

19 25(Base+64) High-speed DMA Ch.3 High-speed DMA Ch.3, end of transfer –

1A 26(Base+68) IDMA Intelligent DMA, end of transfer –

27–29 reserved – –

1E 30(Base+78) 16-bit programmable timer 0 Timer 0 comparison B 7

1F 31(Base+7C) Timer 0 comparison A 8

32–33 reserved – –

22 34(Base+88) 16-bit programmable timer 1 Timer 1 comparison B 9

23 35(Base+8C) Timer 1 comparison A 10

36–37 reserved – –

26 38(Base+98) 16-bit programmable timer 2 Timer 2 comparison B 11

27 39(Base+9C) Timer 2 comparison A 12

40–41 reserved – –

2A 42(Base+A8) 16-bit programmable timer 3 Timer 3 comparison B 13

2B 43(Base+AC) Timer 3 comparison A 14

44–45 reserved – –

2E 46(Base+B8) 16-bit programmable timer 4 Timer 4 comparison B 15

2F 47(Base+BC) Timer 4 comparison A 16

48–49 reserved – –

32 50(Base+C8) 16-bit programmable timer 5 Timer 5 comparison B 17

33 51(Base+CC) Timer 5 comparison A 18

34 52(Base+D0) 8-bit programmable timer Timer 0 underflow 19

35 53(Base+D4) Timer 1 underflow 20

36 54(Base+D8) Timer 2 underflow 21 ↓

37 55(Base+DC) Timer 3 underflow 22 Low

II CORE BLOCK: CPU AND OPERATING MODE

S1C33209/221/222 FUNCTION PART EPSON B-II-2-5

HEX

No. Vector number

(Hex address) Exception/interrupt name Exception/interrupt factor IDMA

Ch. Priority

38 56(Base+E0) Serial interface Ch.0 Receive error – High

39 57(Base+E4) Receive buffer ful l 23 ↑

3A 58(Base+E8) Transmit buffer empty 24

59 reserved – –

3C 60(Base+F0) Serial interface Ch.1 Receive error –

3D 61(Base+F4) Receive buffer full 25

3E 62(Base+F8) Transmit buffer empty 26

63 reserved – –

40 64(Base+100) A/D converte r A/D converter, end of conversion 27

41 65(Base+104) Clock timer Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal

1-minuet, 1-hour or specified time count up –

66–67 reserved – –

44 68(Base+110) Port input interrupt 4 Edge (rising or falling) or le vel (High or Low) 28

45 69(Base+114) Port input interrupt 5 Edge (rising or falling) or level (High or Low) 29

46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 30 ↓

47 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) 31 Low

∗ Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default.

II CORE BLOCK: CPU AND OPERATING MODE

B-II-2-6 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

II CORE BLOCK: INITIAL RESET

S1C33209/221/222 FUNCTION PART EPSON B-II-3-1

II-3 INITIAL RESET

Pins for Initial Reset

Table 3.1 shows the pins used for initial reset.

Table 3.1 Pins for Initial Reset

Pin name I/O Function

#RESET I Initial reset input pin (Low active)

Low: Resets the CPU.

#MNI I NMI request input pin

This pin is also used for selecting a reset method.

High: Cold start

Low: Hot start

The chip is reset when the #RESET pin goes low and starts operating at the rising edge of the reset signal. The CPU

and internal peripheral circuits are initialized while the #RESET pin is low.

Cold Start and Hot Start

The CPU supports two initial reset methods: cold start and hot start. The #MNI pin is used with the #RESET pin to

set this condition.

The differences between cold start and hot start are shown in Table 3.2.

Table 3.2 Differences between Cold Start and Hot Start

Setup contents Cold start Hot start

Reset condition #RESET = low & #MNI = high #RESET = low & #MNI = low

CPU: PC The vector at the boot address is loaded to the PC.

CPU: PSR All the PSR bits are reset to 0.

CPU: Other registers Undefined

CPU: Operating clock The CPU operates with the OSC3 clock.

External bus status (0x48120–0x4813F) Initialized Status is retained.

Oscillation circuit Both the OSC1 and OSC3 circuits start oscillating.

I/O pin status (0x402C0–0x402DF) Initialized Status is retained.

Other peripheral circuit Initialized or undefined

Since cold start initializes all the internal peripheral circuits as well as the CPU, it is useful as a power-on reset.

Hot start initializes the CPU and peripheral circuits, but does not reset the bus control unit and the input, output and

I/O port status. It is therefore useful as a reset that maintains the external bus and I/O pin status during operation.

The #NMI pin that specifies the reset method should be set following the timing chart shown in Figure 3.1.

(1) Cold start (2) Hot start

#NMI

#RESET

Cold start is generated

(#RESET = low & #NMI = high)

#NMI must be set to high longer than

the reset pulse width.

#NMI

#RESET

Hot start is generated

(#RESET = low & #NMI = low)

#NMI must be set to low longer than

the reset pulse width.

Figure 3.1 Setup of #RESET and #NMI Pins

II CORE BLOCK: INITIAL RESET

B-II-3-2 EPSON S1C33209/221/222 FUNCTION PART

Power-on Reset

Be sure to reset (cold start) the chip after turning on the power to start operating.

Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside

the chip.

An initial reset (#RESET = low) turns the high-speed (OSC3) oscillation circuit on. The CPU starts operating with

the OSC3 clock at the rising edge of the reset signal. The high-speed (OSC3) oscillation circuit takes time (10 ms

max. under the standard condition in 3.3 V) for the oscillation to stabilize, therefore initial reset must be released after

an appropriate oscillation-stabilization time has passed in order to start up the CPU without fault. The initial reset

pulse width must be exceeded the oscillation-stabilization time.

Figure 3.2 shows a power-on reset timing chart.

#RESET

STA3

(OSC3 oscillation start time) or more

3.0 V (V

= 3.3 V)

0.5V

0.1V

Power on

Figure 3.2 Power-on Reset Timing

Maintain the #RESET pin at 0.1•VDD or less (low level) after turning the power on until the supply voltage rises at

least to the oscillation start voltage (3.0 V). Furthermore, maintain the #RESET pin at 0.5•VDD or less until the

high-speed (OSC3) oscillation circuit stabilizes oscillating.

Note:The OSC3 oscillation start time varies due to the elements used, board pattern and operating

environment, therefore allow enough margin for the reset-release time. Refer to "Oscillation

Characteristics", in which an example of oscillation start time is provided.

Reset Pulse

A low pulse can be input to the #RESET pin for resetting the chip being operated.

The minimum reset pulse width is provided in "AC Characteristics". Be sure to input a pulse that has a pulse width

longer than the minimum value.

To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended

until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an

operation error.

II CORE BLOCK: INITIAL RESET

S1C33209/221/222 FUNCTION PART EPSON B-II-3-3

Boot Address

When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address

(0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from the

address when the #RESET pin goes high.

The trap table in which trap vectors for interrupts and other trap factors are written also begins from the boot address

by the default setting. (Refer to the "S1C33000 Core CPU Manual" for details of the trap table.)

The trap table base address can also be changed to a 1KB boundary address using the TTBR register (0x48134 to

0x48137).

Notes Related to Initial Reset

Core CPU

Since the all registers except for the PC and PSR are indeterminate at initial reset, they should be initialized by

a program. In particular, the SP (stack pointer) must be initialized before accessing the stack area. NMI requests

are disabled until any value is written to the SP. The initialization is necessary when the CPU is cold-started.

Internal RAM

The contents of the internal RAM are indeterminate at initial reset. Initialize the area to be used if necessary.

High-speed (OSC3) oscillation circuit

An initial reset activates the high-speed (OSC3) oscillation circuit and the CPU starts operating with the OSC3

clock after the initial reset is released. In order to prevent a malfunction of the CPU due to an unstabilized clock,

the #RESET pin must be maintained at low until the OSC3 oscillation stabilizes when performing a power-on

reset or resetting while the high-speed (OSC3) oscillation circuit is stopped.

Low-speed (OSC1) oscillation circuit

A power-on reset or an initial reset when the low-speed (OSC1) oscillation circuit is off starts the OSC1

oscillation. The low-speed (OSC1) oscillation circuit takes a longer stabilization time (3 sec max. under the

standard condition) than the high-speed (OSC3) osci llation circuit. In order to prevent a malfunction due to an

unstabilized clock, do not use the OSC1 clock until the stabilization time has passed.

BCU (Bus Control Unit)

Cold-start initializes the control registers for the BCU (bus control unit). Therefore, it is necessary to set up all

the bus conditions.

Hot-start retains the previous bus conditions before an initial reset.

Input/output ports and input/output pins

Cold start initializes the control and data registers for the input and I/O ports.

Hot start retains the contents of the control registers and input/output pin status before an initial reset. However,

when the pins are used for the internal peripheral circuits, it is necessary to set up the control registers of the

peripheral circuit beca use they are initialized by an initial reset.

Other internal peripheral circuits

The control and data registers of peripheral circuits other than those listed above are initialized with the

predefined values or become indeterminate regardless of the reset method (cold start or hot start). Therefore, it

is necessary to set up the peripheral circuit conditions.

Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral

circuits.

II CORE BLOCK: INITIAL RESET

B-II-3-4 EPSON S1C33209/221/222 FUNCTION PART

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II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-1

II-4 BCU (Bus Control Unit)

The BCU (Bus Control Unit) provides an interface for external devices and on-chip user logic block. The types

and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled

directly by the BCU. This unit also supports a direct interface for DRAM and burst ROM. This chapter describes how

to control the external and internal system interface, and how it operates.

Note: The control registers of the external system interface shown in this chapter are mapped to the

internal 16-bit I/O area. Therefore, the addresses of these control registers are indicated by half-

word (16-bit) addresses unless otherwise specified. Note that the control registers can be accessed

in bytes, half-words, or words.

Pin Assignment for External System Interface

I/O Pin List

External I/O pins

Table 4.1 lists the pins used for the external system interface.

Table 4.1 I/O Pin List

Pin name I/O Function

A[0]/#BSL O Address bus (A0) / Bus strobe (Low-byte)

A[23:1] O Address bus (A1–A23)

D[15:0] I/O Data bus (D0–D15)

#CE10EX O Area 10 external memory chip enable

#CE10IN O Area 10 chip enable for internal ROM emulation mode

#CE9/#CE17 O Area 9/17 chip enable

#CE8/#RAS1/#CE14/#RAS3 O Area 8/14 chip enable / DRAM Row strobe

#CE7/#RAS0/#CE13/#RAS2 O Area 7/13 chip enable / DRAM Row strobe

#CE6 O Area 6 chip enable

#CE5/#CE15 O Area 5/15 chip enable

#CE4/#CE11 O Area 4/11 chip enable

#CE3 O Area 3 chip enable for ROM emulation mode

#RD O Read signal

#EMEMRD O Read signal for area 3/10 emulation mode

#WRL/#WR/#WE O Write (Low-byte) / Write / DRAM write

#WRH/#BSH O Write (High-byte) / Bus strobe (High-byte)

#HCAS O DRAM column address strobe (High-byte)

#LCAS O DRAM column address strobe (Low-byte)

BCLK O Bus clock output

#BUSREQ/#CE6/P34 I/O Bus release request / Area 6 chip enable / I/O port

#BUSACK/P35 O Bus request acknowledge / I/O port

#WAIT/#CE4&5/P30 I/O Wait cycle request / Areas 4&5 chip enable / I/O port

#DRD/P20 O DRAM read signal / I/O port

#DWE/P21 O DRAM write (Low-byte) / I/O por t

#X2SPD I CPU - BCLK clock ratio

1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2

EA10MD[1:0] I Area 10 boot mode selection

11: External ROM, 10: Internal ROM, 01: OTP, 00: Internal ROM emulation

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-2 EPSON S1C33209/221/222 FUNCTION PART

User interface signals

Table 4.2 List of User Interface Signals

Signal name I/O Function

Internal_addr0 O • Address bus (a0) when SBUSST(D3/0x4812E) = "0" (default)

• Bus strobe (low byte) signal (#BSL) when SBUSST(D3/0x4812E) = "1"

Internal_addr[23:1] O Address bus (a1 to a23)

Internal_dout[15:0] O Output data bus (dout0 to dout15)

This data bus is used when the CPU writes data to the on-chip user logic.

Internal_din[15:0] I Input data bus (din0 to din15)

This data bus is used when the CPU reads data from the on-chip user logic.

Internal_ce4_x

Internal_ce5_x

Internal_ce6_x

O Areas 6–4 chip enable signals

These signals go low when the CPU accesses the user logic circuits that are mapped to Areas 6–4.

Internal_rd_x O Read signal

This signal goes low when the CPU reads data from the user logic.

Internal_wrl_x O • Write (low byte) signal (#WRL) when SBUSST(D3/0x4812E) = "0" (default)

• Write signal (#WR) when SBUSST(D3/0x4812E) = "1"

This signal goes low when the CPU write 8 low-order bit data to the user logic.

Internal_wrh_x O • Write (high byte) signal (#WRH) when SBUSST(D3/0x4812E) = "0" (default)

• Bus strobe (high byte) signal (#BSH) when SBUSST(D3/0x4812E) = "1"

This signal goes low when the CPU write 8 high-order bit data to the user logic.

Internal_osc3_clk O High-speed (OSC3) oscillation clock output

This can be used as a source clock for the user logic.

Internal_pll_clk O PLL output clock

This can be used as a source clock for the user logic.

Internal_wait_x I Wait cycle request input

The user logic can request to insert wait cycles by setting this signal to low.

Internal_irrd_x O Instruction fetch indicator signal

This signal goes low when the CPU is in an instruction fetch cycle.

Internal_k60-k67 I Input signals

These signals are connected to the input ports K60 –K67. The user logic can request HSDMA, IDMA and

interrupts using these signals. The user logic can also be used as input ports with these signals.

The internal bus signals are available when an internal access area is set using the BCU register.

The bus conditions can be programmed using the BCU registers similar to the external bus.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-3

Combination of System Bus Control Signals

The bus control signal pins that have two or more functions have their functionality determined when an interface

method is selected by a program. The BCU contains an ordinary external system interface (two interface method are

supported) and a DRAM interface.

Table 4.3 Interface Selection

Interface type Interface method Control bit

External system interface A0 system (default) SBUSST(D3/0x4812E) = "0"

#BSL system SBUSST(D3/0x4812E) = "1"

DRAM interface 2CAS system (fixed) None

SBUSST is initialized to "0" at cold start.

When the IC is hot-started, these bits retain their status before the chip was reset.

Table 4.4 shows combinations of control signals classified by each interface method.

Table 4.4 Combinations of Bus Control Signals

External system interface DRAM interface

A0 system #BSL system 2CAS system

A0 #BSL (little endian) /

#BSH (big endian) ∗1–

#WRL #WR #WE

#WRH #BSH (little endian) /

#BSL (big endian) ∗1–

– – #HCAS

– – #LCAS

#CEx #CEx #RASx ∗2

∗1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or

big endian).

∗2 When using DRAM, the #CE output pins in areas 7 –8 (areas 13–14) function as the #RAS1 –2 (#RAS3–4)

pins.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-4 EPSON S1C33209/221/222 FUNCTION PART

Memory Area

Memory Map

Figure 4.1 shows the memory map supported by the BCU.

Internal RAM

Internal I/O

(Mirror of internal I/O)

(Reserved)

For CPU core or debug mode

(Reserved)

For middleware use

0x0BFFFFF

0x0800000

0x07FFFFF

0x0600000

0x05FFFFF

0x0400000

0x03FFFFF

0x0380000

0x037FFFF

0x0300000

0x02FFFFF

0x0200000

0x01FFFFF

0x0100000

0x00FFFFF

0x0080000

0x007FFFF

0x0060000

0x005FFFF

0x0050000

0x004FFFF

0x0040000

0x003FFFF

0x0030000

0x002FFFF

0x0000000

Area

Area 9

SRAM type

Burst ROM type

8 or 16 bits

Area 8

SRAM type

DRAM type

8 or 16 bits

Area 7

SRAM type

DRAM type

8 or 16 bits

Area 6

SRAM type

Area 5

SRAM type

8 or 16 bits

Area 4

SRAM type

8 or 16 bits

Area 3

16 bits

Fixed at 1 cycle

Area 2

16 bits

Fixed at 3 cycles

Area 1

8, 16 bits

2 or 4 cycles

Area 0

32 bits

Fixed at 1 cycle

Address

External memory (1MB)

External memory (2MB)

External memory (4MB)

External I/O (8-bit device)

External I/O (16-bit device)

0xFFFFFFF

0xD000000

0xCFFFFFF

0xC000000

0xBFFFFFF

0x9000000

0x8FFFFFF

0x8000000

0x7FFFFFF

0x7000000

0x6FFFFFF

0x6000000

0x5FFFFFF

0x5000000

0x4FFFFFF

0x4000000

0x3FFFFFF

0x3000000

0x2FFFFFF

0x2000000

0x1FFFFFF

0x1800000

0x17FFFFF

0x1000000

0x0FFFFFF

0x0C00000

Area

Area 18

SRAM type

8 or 16 bits

Area 17

SRAM type

8 or 16 bits

Area 16

SRAM type

8 or 16 bits

Area 15

SRAM type

8 or 16 bits

Area 14

SRAM type

DRAM type

8 or 16 bits

Area 13

SRAM type

DRAM type

8 or 16 bits

Area 12

SRAM type

8 or 16 bits

Area 11

SRAM type

8 or 16 bits

Area 10

SRAM type

Burst ROM type

8 or 16 bits

Address

External memory (8MB)

External memory (16MB)

Figure 4.1 Memory Map

Basically, Areas 0 to 3 are internal memory areas and Areas 4 to 18 are external memory areas.

Area 0 is normally used for a built-in RAM. The built-in memory is mapped from the beginning of the area.

Area 1 is reserved for the I/O memory of the on-chip functional blocks. Address 0x0040000 to address 0x004FFFF

are used as the control registers and address 0x0050000 to 0x005FFFF are used as the mirror area.

Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status).

Area 3 is reserved for S1C33 middlewares.

Area 4 to 18 can also be configured as internal memory areas using the control register and they can be used for user

logic circuits.

However, in the S1C33221/S1C33222, Area 10 is used as a built-in ROM area.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-5

External Memory Map and Chip Enable

The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit ex ternal data bus (D[15:0]), allowing an address

space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11

areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each provided

with an independent chip-enable pin (#CE[10:4]).

The C33 Core Block is limited to 24 available pins for the address bus and 7 pins for the #CE output due to its

package structure. However, the #CE[4:10] output pins can be switched to the high-order area chip enable output

pins as shown in Table 4.5 using software. CEFUNC[1:0] (D[A:9]) / DRAM timing set-up register (0x48130) is used

for this switching.

Table 4.5 Switching of #CE Output

Pin CEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"

#CE4 #CE4 #CE11 #CE11+#CE12

#CE5 #CE5 #CE15 #CE15+#CE16

#CE6 #CE6 #CE6 #CE7+#CE8

#CE7/#RAS0 #CE7/#RAS0 #CE13/#RAS2 #CE13/#RAS2

#CE8/#RAS1 #CE8/#RAS1 #CE14/#RAS3 #CE14/#RAS3

#CE9 #CE9 #CE17 #CE17+#CE18

#CE10EX #CE10EX #CE10EX #CE9+#CE10EX

(Default: CEFUNC = "00")

The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the default

low-order areas. For exampl e, when using DRAM in default settings, the available space is 4 MB in areas 7 and 8.

However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other areas.

Furthermore, when CEFUNC is set to "10" or "11", five chip en able signals are expanded into two area size.

Although the C33 Core Block has only 24 address output pins, it features 28-bit internal address processing.

Figure 4.2 shows a memory map for an external system.

0x0FFFFFF

0x0C00000

0x0BFFFFF

0x0800000

0x07FFFFF

0x0600000

0x05FFFFF

0x0400000

0x03FFFFF

0x0380000

0x037FFFF

0x0300000

0x02FFFFF

0x0200000

0x01FFFFF

0x0100000

Area

Area 10

(#CE10)

SRAM type

Burst ROM type

8 or 16 bits

Area 9

(#CE9)

SRAM type

Burst ROM type

8 or 16 bits

Area 8

(#CE8/#RAS1)

SRAM type

DRAM type

8 or 16 bits

Area 7

(#CE7/#RAS0)

SRAM type

DRAM type

8 or 16 bits

Area 6

(#CE6)

SRAM type

Area 5

(#CE5)

SRAM type

8 or 16 bits

Area 4

(#CE4)

SRAM type

8 or 16 bits

Area

Area 17

(#CE17)

SRAM type

8 or 16 bits

Area 15

(#CE15)

SRAM type

8 or 16 bits

Area 14

(#CE14/#RAS3)

SRAM type

DRAM type

8 or 16 bits

Area 13

(#CE13/#RAS2)

SRAM type

DRAM type

8 or 16 bits

Area 11

(#CE11)

SRAM type

8 or 16 bits

Area 10

(#CE10)

SRAM type

Burst ROM type

8 or 16 bits

Area 6

(#CE6)

SRAM type

Address

External memory 1 (1MB)

External memory 2 (1MB)

External memory 3 (2MB)

External memory 4 (2MB)

External memory 5 (4MB)

External memory 6 (4MB)

External I/O (8-bit device)

External I/O (16-bit device)

0xBFFFFFF

0x9000000

0x8FFFFFF

0x8000000

0x5FFFFFF

0x5000000

0x4FFFFFF

0x4000000

0x3FFFFFF

0x3000000

0x2FFFFFF

0x2000000

0x17FFFFF

0x1000000

0x0FFFFFF

0x0C00000

0x03FFFFF

0x0380000

0x037FFFF

0x0300000

Address

External memory 3 (16MB)

External memory 4 (16MB)

External memory 5 (16MB)

External memory 6 (16MB)

(Mirror of External memory 6)

(Mirror of External memory 5)

External I/O (8-bit device)

External I/O (16-bit device)

External memory 1 (4MB)

External memory 2 (8MB)

CEFUNC = "00" CEFUNC = "01"

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-6 EPSON S1C33209/221/222 FUNCTION PART

Area

Area 17+18

(#CE17+18)

SRAM type

8 or 16 bits

Areas 15–16

(#CE15+16)

SRAM type

8 or 16 bits

Area 14

(#CE14/#RAS3)

SRAM type

DRAM type

8 or 16 bits

Area 13

(#CE13/#RAS2)

SRAM type

DRAM type

8 or 16 bits

Areas 11–12

(#CE11+12)

SRAM type

8 or 16 bits

Areas 9–10

(#CE9+10EX)

SRAM type

Burst ROM type

8 or 16 bits

Areas 7–8

(#CE7+8)

SRAM type

8 or 16 bits

0xFFFFFFF

0xD000000

0xCFFFFFF

0xC000000

0xBFFFFFF

0x9000000

0x8FFFFFF

0x8000000

0x7FFFFFF

0x7000000

0x6FFFFFF

0x6000000

0x5FFFFFF

0x5000000

0x4FFFFFF

0x4000000

0x3FFFFFF

0x3000000

0x2FFFFFF

0x2000000

0x1FFFFFF

0x1000000

0x0FFFFFF

0x0800000

0x07FFFFF

0x0400000

Address

External memory 4 (16MB)

External memory 5 (16MB)

External memory 2 (8MB)

External memory 3 (16MB)

External memory 1 (4MB)

CEFUNC = "10" or "11"

External memory 7 (16MB)

External memory 7' (16MB)

(Mirror of External memory 7')

(Mirror of External memory 7)

External memory 6 (16MB)

External memory 6' (16MB)

(Mirror of External memory 6')

(Mirror of External memory 6)

Figure 4.2 External System Memory Map

Furthermore, the #CE4+#CE5 and #CE6 signals can be output from the P30 and P34 terminals, respectively.

This function expands the accessible area when CEFUNC is set to "01, "10" or "11".

To output the #CE4+#CE5 signal from the P30 terminal:

CFP30 (D0)/P3 function select register (0x402DC) = "1"

IOC30 (D0)/P3 I/O control register (0x402DE) = "1"

To output the #CE6 signal from the P34 terminal:

CFP34 (D4)/P3 function select register (0x402DC) = "1"

IOC34 (D4)/P3 I/O control register (0x402DE) = "1"

The P30 and P34 terminals are set for the general I/O ports at initial reset.

The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore,

when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-7

Using Internal Memory on External Memory Area

The BCU allows using of an internal memory in the external memory areas.

The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access.

When "1" is written, the internal device will be accessed and when "0" is written, the external device is accessed

(external access by default). The bit names and the corresponding areas are as follows:

A18IO (DF): Areas 17 and 18

A16IO (DE): Areas 15 and 16

A14IO (DD): Areas 13 and 14

A12IO (DC): Areas 11 and 12

A8IO (DA): Areas 7 and 8

A6IO (D9): Area 6

A5IO (D8): Areas 4 and 5

Exclusive Signals for Areas

Areas can be accessed using the exclusive signals (address strobe and read signals) as well as the common control

signals.

To use these exclusive signals, they should be configured using G/A read signal control register (0x48138).

The AxxAS bit is used to enable /disable the address strobe signal, and the AxxRD bit is used to enable/disable the

read signal. When "1" is written to the bit, the exclusive signal for the corresponding area(s) is enabled and when "0"

is written, it is disabled (disabled by default). The bit names and the corresponding areas are as follows:

A18AS (DF), A18RD (D7): Areas 17 and 18

A16AS (DE), A16RD (D6): Areas 15 and 16

A14AS (DD), A14RD (D5): Areas 13 and 14

A12AS (DC), A12RD (D4): Areas 11 and 12

A8AS (DA), A8RD (D2): Areas 7 and 8

A6AS (D9), A6RD (D1): Area 6

A5AS (D8), A5RD (D0): Areas 4 and 5

#CE selected with AxxAS (ORed)

#WRH

#WRL

#RD

#CE selected with AxxRD (ORed)

#GAAS P21

#GAAS P31

Figure 4.3 #GAAS and #GARD Signals

The address strobe signal and the read signal are output from the P21 pin and P31 pin, respectively. Therefore, when

using these signals, the pin(s) must be configured for exclusive signal output using the port function select register

and port function extension register.

To output the exclusive address strobe signal #GAAS:

CFEX2 (D2)/Port function extension register (0x402DF) = "1"

To output the exclusive address strobe signal #GARD:

CFEX3 (D3)/Port function extension register (0x402DF) = "1"

These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive

signal, OR condition is applied.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-8 EPSON S1C33209/221/222 FUNCTION PART

Area 10

Area 10 is an external memory area that includes the boot address (0xC00000). This area supports four boot modes.

For the S1C33221/S1C33222, a setting must be made according to the internal ROM size.

Note: Internal ROM is not provided in the S1C33209.

Area 10 boot mode

The boot mode can be configured using the external pins EA10MD[1:0].

Table 4.6 Area 10 Boot Mode Selection

EA10MD[1:0] pins Area 10 boot mode

00 Internal ROM emulation mode

01 OTP and internal ROM emulation mode

10 Internal ROM boot mode

11 External ROM boot mode

Internal ROM boot mode

The CPU boots by the internal ROM mapped to area 10. The internal ROM size should be selected from among

eight types (min. 16 KB, max. 2 MB) using the A10IR[2:0] (D[E:C])/Areas 10– 9 set-up register (0x48126).

This ROM begins with address 0xC00000 and can be read in one cycle the same as that of area 3. For the

remained area within area 10, the external memory will be accessed if it is available.

Internal ROM emulation mode

The CPU boots by the external memory that emulates an internal ROM. This mode accesses the ROM

emulation memory set by the A10IR[2:0] (D[E:C])/Areas 10– 9 set-up register (0x48126) using the same

condition as internal ROM boot mode. The emulation memory is accessed using the #CE10IN chip enable

signal.

∗Internal ROM emulation mode can only be used for debugging, and cannot be used in mass production.

OTP and internal ROM emulation mode

In this mode, channel 0 of IDMA starts up for transferring the program codes in the Flash memory to the

high-speed SRAM immediately after an initial reset is released. Then the system boots by the SRAM. After that,

this mode functions the same as internal ROM emulation mode.

Since the Flash memory and SRAM are mapped to the same address range, the Flash memory is accessed using

the #CE10EX chip enable signal and the SRAM is accessed using the #CE10IN chip enable signal.

External ROM boot mode

The CPU boots by the external ROM (ROM, Flash, SRAM, etc.). This mode uses the bus condition set by the

BCU registers for area 10.

Setting the internal ROM size

When a boot mode other than external ROM boot mode is used, the internal ROM or emulation memory size

should be set using A10IR[2:0] (D[E:C)/Areas 10– 9 set-up register (0x48126).

Table 4.7 Area 10 Internal ROM Size

A10IR2 A10IR1 A10IR0 ROM size

0 0 0 16 KB

0 0 1 32 KB

0 1 0 64 KB

0 1 1 128 KB

1 0 0 256 KB

1 0 1 512 KB

1 1 0 1 MB

1 1 1 2 MB (default)

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-9

Area 10 memory map

Figure 4.4 shows the memory map of area 10.

Area 10

External ROM boot mode

0x0C00000

0x0FFFFFF

External memory

is accessed.

Set-up example

25 MHz

5 wait

Area 10

Other modes

0x0C00000

0x0FFFFFF

External memory

is accessed.

Set-up example

25 MHz

5 wait

Internal or

emulation memory

is accessed.

Set-up example

25 MHz (#X2SPD = "1")

25 MHz (#X2SPD = "0")

No wait

16KB, 32KB, 64KB, 128KB

256KB, 512KB, 1MB or 2MB

selected by A10IR[2:0]

Figure 4.4 Area 10 Memory Map

Area 3

Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used.

When external emulation memory is used, A3EEN (DB/0x48130) must be set to "1".

Table 4.8 Area 3 Mode Selection

A3EEN Area 3 mode

0 Emulation mode

1 Unused

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-10 EPSON S1C33209/221/222 FUNCTION PART

System Configuration in Emulation Mode

Figure 4.5 shows a development environment example using the emulation mode.

S1C33 Area 3 emulation memory

(High-speed SRAM)

G/A

Data bus

buffer

Data

A[23:0]

#CE3 ∗1

#EMEMRD ∗2

#WRL

#WRH

D[15:0]

#CE10IN

#CE10EX

#RD ∗3

EA10MD1

EA10MD0

Address

#CE

#RD

#WRL

#WRH

Area 10 emulation memory

(High-speed SRAM)

Data

Address

#RD

#WRL

#WRH

#CE

Data

DRAM

Data

Area 10 external memory

(Flash)

Data

Address

#CE

#RD

#WRL

#WRH

∗4

∗1: Available when A3EEN (D8/0x48130) = "0"

∗2: Available only for emulation mode

∗3: General read signal for external devices

∗4: Data is transferred from Flash to SRAM when booting with OTP mode.

Figure 4.5 Development Environment Example

The emulation memory is accessed without wait state as shown in Figure 4.6.

BCLK

External address

#CE10IN/#CE3

#EMEMRD

External Data

10 ns

td1(3 ns)

tacc tsetup

(7 ns)

td1 + tsetup = 10 ns or less

td2 + tsetup = 15 ns or less

tsetup = 7 ns

td1 = 3 ns

td2 = 8 ns

5 ns

10 ns

td2(8 ns)

Figure 4.6 Read Timing in Emulation Mode

In the emulation mode, the exclusive read signal #EMEMRD is used.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-11

Setting External Bus Conditions

The type, size, and wait conditions of a device connected to the external bus can be individually set for each area using

the control register (0x48120 to 0x48130). The following explains the available setup conditions individually for

each area. For details on how to set the DRAM interface conditions, refer to "DRAM Direct Interface".

The control register used to set bus conditions is initialized at cold start. Therefore, please set up these registers again

using software according to the external device configuration and specifications.

When the IC is hot-started, the setup contents and pins retain their previous status before a reset.

Setting Device Type and Size

Table 4.9 shows the types of devices that can be connected directly to each area.

Table 4.9 Device Type

Area SRAM type DRAM type Burst ROM type Control bit

18–15 ●X X None

14 ● ● X A14DRA(D8)/Areas 14–13 set-up register(0x48122)

13 ● ● X A13DRA(D7)/Areas 14–13 set-up register(0x48122)

12,11 ●X X None

10 ●X●A10DRA(D8)/Areas 10–9 set-up register(0x48126)

9●X●A9DRA(D7)/Areas 10–9 set-up register(0x48126)

8● ● X A8DRA(D8)/Areas 8–7 set-up register(0x48128)

7● ● X A7DRA(D7)/Areas 8–7 set-up register(0x48128)

6–4 ●X X None

●: Can be connected X: Cannot be connected

When connecting burst ROM or DRAM, write "1" to each corresponding control bit. These control bits are reset to "0"

(SRAM type) at cold start.

The device size can be set to 8 or 16 bits once every two areas except for area 6. Area 6 alone has its first half

(0x300000– 0x37FFFF) fixed to an 8-bit device and the second half (0x380000– 0x3FFFFF) fixed to a 16-bit device.

Table 4.10 Device Size Control Bits

Area Control bit

18, 17 A18SZ(DE)/Areas 18– 15 set-up register(0x48120)

16, 15 A16SZ(D6)/Areas 18–15 set-up register(0x48120)

14, 13 A14SZ(D6)/Areas 14–13 set-up register(0x48122)

12, 11 A12SZ(D6)/Areas 12–11 set-up register(0x48124)

10, 9 A10SZ(D6)/Areas 10– 9 set-up register(0x48126)

8, 7 A8SZ(D6)/Areas 8–7 set-up register(0x48128)

5, 4 A5SZ(D6)/Areas 6–4 set-up register(0x4812A)

At cold start, each area by default is set to 16 bits.

When using an 8-bit device, write "1" to the control bit.

Note: The BCU supports 16-bit burst ROM. Therefore, when connecting burst ROM to area 10 or area 9,

do not set the device size to 8 bits (A10SZ = "1").

For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External

Memory".

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-12 EPSON S1C33209/221/222 FUNCTION PART

Setting SRAM Timing Conditions

The areas set for the SRAM allow wait cycles and output disable delay time to be set.

Number of wait cycles: 0 to 7 (incremented in units of one cycle)

Output disable delay time: 0.5, 1.5, 2.5, 3.5 cycles

This selection can be made once every two areas except for area 6.

Table 4.11 Timing Condition Setting Bits (for SRAM type)

Area Number of wait cycles Output disable delay time Control register

18, 17 A18WT[2:0](D[A:8]) A18DF[1:0](D[D:C]) Areas 18–15 set-up register(0x48120)

16, 15 A16WT[2:0](D[2:0]) A16DF[1:0](D5:4]) Areas 18– 15 set-up register(0x48120)

14, 13 A14WT[2:0](D[2:0]) A14DF[1:0](D5:4]) Areas 14– 13 set-up register(0x48122)

12, 11 A12WT[2:0](D[2:0]) A12DF[1:0](D5:4]) Areas 12– 11 set-up register(0x48124)

10, 9 A10WT[2:0](D[2:0]) A10DF[1:0](D5:4]) Areas 10– 9 set-up register(0x48126)

8, 7 A8WT[2:0](D[2:0]) A8DF[1:0](D[5:4]) Areas 8–7 set-up register(0x48128)

6 A6WT[2:0](D[A:8]) A6DF[1:0](D[D:C]) Areas 6 –4 set-up register(0x4812A)

5, 4 A5WT[2:0](D[2:0]) A5DF[1:0](D[5:4]) Areas 6–4 set-up register(0x4812A)

At cold start, the number of wait cycles is set to 7 and the output disable delay time is set to 3.5 cycles. Reset up these

parameters as necessary using software according to specifications of the connected device.

At hot start, these parameters retain their previous settings before a reset.

Wait cycles

When the number of wait cycles is set for an area using the control bit, the BCU extends the bus cycle for a

duration equivalent to the wait cycles set when it accesses the area. Set the desired wait cycles according to the

bus clock frequency and the external device's access time. Separately from the wait cycles set here, a wait

request from an external device can also be accepted using the #WAIT pin. Since the settings of wait cycles

using software are made o nce every two areas, use this external wait request function if you want the wait cycles

to be controlled individually in each area or if you need 7 or more wait cycles. The #WAIT pin is shared with the

P30 I/O port. For an external wait request to be accepted, write "1" to CFP30 (D0) / P3 function select register

(0x402DC [Byte]) and write "1" (default = "0") to SWAIT (D0) / Bus control register (0x4812E) to enable the

#WAIT pin.

For timing charts for bus cycles and when wait cycles are inserted, refer to " Bus Cycles in External System

Interface".

If the number of wait cycles is set to 0 and no external wait is requested, the basic read cycle (read in byte or

half-word) for the SRAM external device consists of one cycle. If wait cycles are set, because these cycles are

added, the bus read cycle consists of [number of wait cycles + 1] (providing that there is no external wait).

On the other hand, the basic write cycle consists of at least two cycles. This does not change regardless of

whether zero or one wait cycle is set. If the number of wait cycles set is 2 or more, the bus cycle is actually

extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles

(providing that there is no external wait).

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-13

Output disable delay time

In cases when a device having a long output disable time is connected, if a read cycle for that device is followed

by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus is not

placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus

contention. This is accomplished by inserting a specified number of cycles between a read cycle and the next

bus operation. Care is required with the CEx signals, however, since different areas may be asserted

consecutively. There are gaps between command signals such as #RD and #WRL/#WRH.

Check the specifications of the device to be connected before setting the output d isable delay time.

By default, the output disable delay time is inserted only in the following cases:

• when a read cycle from the external device that has had an output disable delay time set is followed by a

write cycle performed by the CPU; and

• when a read cycle from the external device that has had an output disable delay time set is followed by a read

cycle for a different area (including the internal device).

Conversely, no output disable delay time is inserted in the following conditions:

• immediately after a write cycle, and

• during a successive read from the same external device.

Setting Timing Conditions of Burst ROM

Wait cycles

If burst ROM is selected for area 10 or 9, the wait cycles to be inserted in the burst read cycle can be selected in

a range from 0 to 3 cycles. A10BW[1:0] (D[A:9]) / Areas 10–9 set-up register (0x48126) is used for this

selection. This selection is applied simultaneously to areas 10 and 9, so wait cycles can not be chosen

individually for each area. The wait cycles set at cold start is 0.

Even for a burst read, the SRAM settings of wait cycles in the first bus operation are valid. (Refer to

A10WT[2:0] in the foregoing section.)

The wait cycles set by A10BW[1:0] are inserted into the burst cycles aft er the first bus operation.

In addition, when burst ROM is selected, no wait cycles can be inserted into the read cycle via the #WAIT pin.

For writing to an area that has had burst ROM selected, an SRAM write cycle is executed. In this case, both the

SRAM settings of wait cycles and those input via the #WAIT pin are valid.

Burst mode

The burst mode can be selected between an eight-consecutive-burst and a four-consecutive-burst mode. RBST8

(DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected

by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start,

the four-consecutive-burst mode is set by default.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-14 EPSON S1C33209/221/222 FUNCTION PART

Bus Operation

Data Arrangement in Memory

The S1C33 Family of devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing

data in memory, it is necessary to specify a boundary address that conforms to the data size involved. Specification

of an invalid address causes an address error exception. For instructions (e.g., stack manipulation or branch

instructions) that rewrite the SP (stack pointer) or PC (program counter), the specified addresses are forcibly modified

to appropriate boundary addresses. Therefore, no address error exception occurs in this type of instruction. For

details about the address error exception, refer to the "S1C33000 Core CPU Manual".

Table 4.12 shows the data arrangement in memory, classified by data type.

Table 4.12 Data Arrangement in Memory

Data type Arranged location

Byte data Byte boundary address (all addresses)

Half-word data Half-word boundary address (A[0]="0")

Word data Word boundary addre ss (A[1:0]="00")

The half-word and word data in memory area accessed in little-endian format by default. It can be changed to big-

endian format using AxxEC (D[7:0])/Access control register (0x48132). When "1" is written to AxxEC, the

corresponding area i s accessed in big-endian method. The bit names and the corresponding areas are as follows:

A18EC (D7): Areas 17 and 18

A16EC (D6): Areas 15 and 16

A14EC (D5): Areas 13 and 14

A12EC (D4): Areas 11 and 12

A10EC (D3): Areas 9 and 10 ... Fixed at "0" (little-endian) for booting.

A8EC (D2): Areas 7 and 8

A6EC (D1): Area 6

A5EC (D0): Areas 4 and 5

To increase memory efficiency, try to locate the same type of data at continuous locations on exact boundary

addresses in order to minimize invalid areas.

Bus Operation of External Memory

The external data bus is 16-bits wide. For this reason, more than one bus operation occurs depending on the device

size and the data size of the instruction executed, as shown in Table 4.13.

Table 4.13 Number of Bus Operation Cycles

Data size to

be accessed Devise

size Number of bus

operation cycles Remarks

32 bits 16 bits 2

16 bits 16 bits 1

8 bits 16 bits 1 In little-endian method, the low-order b yte is accessed when the LSB of

the address (A[0]) is "0" or the #BSL signal is L. The high-order byte is

accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is

In big-endian method, the high-order byte is accessed when the LSB of the

address (A[0]) is "0" or the #BSL signal is L. The low-order byte is

accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is

32 bits 8 bits 4 In little-endian method, the 8-bit device must be connected to the low-order

8 bits of the data bus. In big-endian method, the 8-bit device must be

connected to the high-order 8 bits of the data bus.

16 bits 8 bits 2 In little-endian method, the 8-bit device must be connected to the low-

order 8 bits of the data bus. In big-endian method, the 8-bit device must be

connected to the high-order 8 bits of the data bus.

8 bits 8 bits 1 In little-endian method, the 8-bit device must be connected to the low-

order 8 bits of the data bus. In big-endian method, the 8-bit device must be

connected to the high-order 8 bits of the data bus.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-15

These bus operations are shown in the figure below, taking the example of the A0 method.

With the BSL method, the following adjustments should be made when reading the figure.

(1) For data reads, the operation is as shown in the figure below.

(2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH.

(3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH.

For information on memory connection, see Figure 4.20.

Byte 1

Data bus

0#WRL

#WRH

No.

2Byte 0

Byte 3 Byte 2

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=10 A[1:0]=00

15 0

12 150

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Little-endian

Byte 3

Data bus

0#WRL

#WRH

No.

2Byte 2

Byte 1 Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=00 A[1:0]=10

15 0

21 150

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Big-endian

Figure 4.7 Word Data Writing to a 16-bit Device

Byte 1

Data bus

0#WRL

#WRH

No.

2Byte 0

Byte 3 Byte 2

Bus operation

Byte 3 Byte 2 Byte 1 Byte 0

31 0

Destination (general-purpose register)

A[1:0]=10 A[1:0]=00

Source (16-bit device)

15 0150

Little-endian

Byte 3

Data bus

0#WRL

#WRH

No.

2Byte 2

Byte 1 Byte 0

Bus operation

Byte 3 Byte 2 Byte 1 Byte 0

31 0

Destination (general-purpose register)

A[1:0]=00 A[1:0]=10

Source (16-bit device)

15 0150

Big-endian

Figure 4.8 Word Data Reading from a 16-bit Device

Byte 1

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Little-endian

Byte 1

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Big-endian

Figure 4.9 Half-word Data Writing to a 16-bit Device

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-16 EPSON S1C33209/221/222 FUNCTION PART

Byte 1

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Bus operation

Sign or Zero extension Byte 1 Byte 0

31 0

Destination (general-purpose register)

A[1:0]=

∗

Source (16-bit device)

015

Little-endian

Byte 1

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Bus operation

Sign or Zero extension Byte 1 Byte 0

31 0

Destination (general-purpose register)

A[1:0]=

∗

Source (16-bit device)

015

Big-endian

Figure 4.10 Half-word Data Reading from a 16-bit Device

Byte 0

Data bus

0#WRL

#WRH

∗

No.

1' Data retained

Byte 0Data retained

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗

0A[1:0]=

∗

1'1

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Little-endian

Byte 0

Data bus

0#WRL

#WRH

∗

No.

1' Data retained

Byte 0Data retained

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗

1A[1:0]=

∗

1'1

Source (general-purpose register)

Destination (16-bit device)

Bus operation

Big-endian

Figure 4.11 Byte Data Writing to a 16-bit Device

RD byte

Data bus

0#WRL

#WRH

∗

No.

1' Ignored

RD byteIgnored

RD byte

31 0

A[1:0]=

∗

0A[1:0]=

∗

1'1

Bus operation

Sign or Zero extension

Destination (general-purpose register)

Source (16-bit device)

Little-endian

RD byte

Data bus

0#WRL

#WRH

∗

No.

1' Ignored

RD byteIgnored

RD byte

31 0

A[1:0]=

∗

1A[1:0]=

∗

1'1

Bus operation

Sign or Zero extension

Destination (general-purpose register)

Source (16-bit device)

Big-endian

Figure 4.12 Byte Data Reading from a 16-bit Device

Data retained

Data bus

0#WRL

#WRH

No.

Byte 0

Data retained Byte 1

Data retained Byte 2

Data retained Byte 3

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=10 A[1:0]=00A[1:0]=11 A[1:0]=01

888000

Source (general-purpose register)

Destination (8-bit device)

3 2

Bus operation

(X: Not connected/Unused)

Little-endian

Byte 3

Data bus

0#WRL

#WRH

No.

Data retained

Byte 2 Data retained

Byte 1 Data retained

Byte 0 Data retained

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=01 A[1:0]=11A[1:0]=00 A[1:0]=10

888000

Source (general-purpose register)

Destination (8-bit device)

2 3

Bus operation

Big-endian

Figure 4.13 Word Data Writing to an 8-bit Device

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-17

Ignored

Data bus

0#WRL

#WRH

No.

Byte 0

Ignored Byte 1

Ignored Byte 2

Ignored Byte 3

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=10 A[1:0]=00A[1:0]=11 A[1:0]=01

888000

Bus operation

(X: Not connected/Unused)

Destination (general-purpose register)

Source (8-bit device)

Little-endian

Byte 3

Data bus

0#WRL

#WRH

No.

Ignored

Byte 2 Ignored

Byte 1 Ignored

Byte 0 Ignored

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=01 A[1:0]=11A[1:0]=00 A[1:0]=10

888000

Bus operation

Destination (general-purpose register)

Source (8-bit device)

Big-endian

Figure 4.14 Word Data Reading from an 8-bit Device

Data retained

Data bus

0#WRL

#WRH

∗

No.

2Byte 0

Data retained Byte 1

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=∗0A[1:0]=∗1

880

Source (general-purpose register)

Destination (8-bit device)

Bus operation

(X: Not connected/Unused)

Little-endian

Byte 1

Data bus

0#WRL

#WRH

∗

No.

2Data retained

Byte 0 Data retained

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=∗1A[1:0]=∗0

880

Source (general-purpose register)

Destination (8-bit device)

Bus operation

(∗: Uniformly 1 or 0)

Big-endian

Figure 4.15 Half-word Data Writing to an 8-bit Device

Ignored

15 Data bus 0#WRL

#WRH

∗

No.

2Byte 0

Ignored Byte 1

Byte 1 Byte 0

31 0

A[1:0]=∗0A[1:0]=∗10

880

Bus operation

(X: Not connected/Unused)

Destination (general-purpose register)

Source (8-bit device)

Sign or Zero extension

Little-endian

Byte 1

15 Data bus 0#WRL

#WRH

∗

No.

2Ignored

Byte 0 Ignored

Byte 1 Byte 0

31 0

A[1:0]=∗1A[1:0]=∗00

880

Bus operation

Destination (general-purpose register)

Sign or Zero extension

Big-endian

(∗: Uniformly 1 or 0)

Figure 4.16 Half-word Data Reading from an 8-bit Device

Data retained

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗∗ 0

Source (general-purpose register)

Destination (8-bit device)

Bus operation

(X: Not connected/Unused)

Little-endian

Byte 0

Data bus

0#WRL

#WRH

∗

No.

1Data retained

Byte 3 Byte 2 Byte 1 Byte 0

31 0

A[1:0]=

∗∗ 0

Source (general-purpose register)

Destination (8-bit device)

Bus operation

Big-endian

Figure 4.17 Byte Data Writing to an 8-bit Device

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-18 EPSON S1C33209/221/222 FUNCTION PART

Ignored

Data bus

0#WRL

#WRH

∗

No.

1Byte 0

Byte 0

31 0

A[1:0]=∗∗

Bus operation

(X: Not connected/Unused)

Destination (general-purpose register)

Source (8-bit device)

Sign or Zero extension

Little-endian

Byte 0

Data bus

0#WRL

#WRH

∗

No.

1Ignored

Byte 0

31 0

A[1:0]=∗∗

Bus operation

Destination (general-purpose register)

Source (8-bit device)

Sign or Zero extension

Big-endian

Figure 4.18 Byte Data Reading from an 8-bit Device

Bus Clock

The bus clock is generated by the BCU using the CPU system clock output from the clock generator.

Figure 4.19 shows the clock system.

High-speed (OSC3)

oscillation circuit

CLKCHGCLKDT[1:0] BCLKSEL[1:0]

PLLS[1:0] pins #X2SPD pin To CPU

OSC3_CLK

OSC3_CLK (PLL: off)

PLL_CLK (PLL: x2 mode)

PLL_CLK (PLL: x4 mode)

CPU_CLK (CLKDT = 1/1)

CPU_CLK (CLKDT = 1/2)

CPU_CLK (CLKDT = 1/4)

CPU_CLK (CLKDT = 1/8)

CPU_CLK

BCU_CLK(#X2SPD=H, x1 speed mode)

BCU_CLK(#X2SPD=L, x2 speed mode)

(when the CPU system clock source is OSC3)

∗1

∗1 Access to the internal RAM

∗2 Access to the external memory

∗1

∗2∗1∗2

PLL_CLK

ACPU_CLK BCU_CLK

Bus clock

PLL

Low-speed (OSC1)

oscillation circuit

CLG BCU

1/1 or 1/2

1/2-1/8

BCLK pin

Figure 4.19 Clock System

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-19

Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus clock:

1. Selection of an oscillation circuit (OSC3 or OSC1)

2. PLL configuration (OSC3_CLK x 1, x2 or x4)

3. CPU clock division ratio for power saving (1/8, 1/4, 1/2, or 1/1 of OSC3_CLK or PLL_CLK)

Items 2 and 3 apply when the high-speed (OSC3) oscillation circuit is selected as the CPU clock source.

For details about the settings of the system clock, refer to "CLG (Clock Generator)".

Bus clock operation during standby is as follows:

Basic HALT mode:the BCU and bus clock continue operating. DRAM can be refreshed.

HALT2 mode: the BCU and bus clock are stopped.

SLEEP mode: the BCU and bus clock are stopped.

Bus Speed Mode

The CPU - bus clock ratio can be set using the #X2SPD pin as follows:

When #X2SPD = High, x1 speed mode (CPU - bus clock ratio is 1 : 1) is set. The bus clock and the CPU system clock

will be the same.

When #X2SPD = Low, x2 speed mode (CPU - bus clock ratio is 2 : 1) is set. In x2 speed mode, the bus clock will be

dynamically varied according to the memory to be accessed.

• When an external memory area is accessed, the b us clock frequency becomes half of the CPU system clock.

• When the internal RAM/ROM area is accessed, the bus clock frequency becomes equal to the CPU system clock.

In x1 speed mode, area 1 (internal I/O area) is accessed in 4 cycles of the CPU system cl ock, while in x2 speed mode,

the number of access cycles can be selected using A1X1MD (D3) / BCLK select register (0x4813A).

When A1X1MD = "1", area 1 is accessed in 2 cycles of the CPU system clock.

When A1X1MD = "0", area 1 is accessed in 4 cycles of the CPU system clock. (default)

Bus Clock Output

The bus clock is also output from the BCLK pin to an external device. The BCLK output clock can be selected from

among four types using BCLKSEL[1:0] (D[1:0]) / BCLK select register (0x4813A).

Table 4.14 Selection of BCLK Output Clock

BCLKSEL1 BCLKSEL0 Output clock

1 1 PLL_CLK (PLL output clock)

1 0 OSC3_CLK (OSC3 oscillation clock)

0 1 BCU_CLK (BCU operating clock)

0 0 CPU_CLK (CPU operating clock)

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-20 EPSON S1C33209/221/222 FUNCTION PART

Bus Cycles in External System Interface

The following shows a sample SRAM connection the basic bus cycles.

A[9:1]

D[15:0]

#RD

#WRH

#WRL

#CE

S1C33

(1) A0 system (little endian/big endian)

A[8:0]

I/O[15:0]

#RD

#WRH

#WRL

#CE

SRAM

A[9:1]

D[15:0]

#WRH

#WRL

#CE

#RD

S1C33

(2) #BSL system (little endian)

A[8:0]

I/O[15:0]

#LB

#UB

#WE

#OS

#OE

SRAM

A[9:1]

D[15:0]

#WRH

#WRL

#CE

#RD

S1C33

(3) #BSL system (big endian)

A[8:0]

I/O[15:0]

#LB

#UB

#WE

#OS

#OE

SRAM

Figure 4.20 Sample DRAM Connection

SRAM Read Cycles

Basic read cycle with no wait mode

BCLK

A[23:0]

#CExx

D[15:0]

#RD

#WAIT

,,,

addr

data

Figure 4.21 Basic Read Cycle with No Wait

Read cycle with wait mode

Example: When the BCU has no internal wait mode and 2 wait cycles via #WAIT pin are inserted

,,,,,,

,,,,,

BCLK

A[23:0]

#CExx

D[15:0]

#RD

#WAIT

C1 CW CW

,,,

,,,,,,,,,,,,,,

addr

data

Figure 4.22 Read Cycle with Wait

The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock) and when it is sampled

on an inactive (high level), the read cycle is terminated.

Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set

for SRAM, and SWAIT (D0) / Bus control register (0x4812E) is enabled for waiting.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-21

The above example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode

consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also be

used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling

edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait cycles set by

the wait control bits are terminated, the read cycle is not terminated at that time.

Precaution

#CE and address hold times at the rising edge of the #RD signal

In read cycles of this BCU, the rise of the #RD signal, negating the chip enable (#CExx) signal and

changing the address (A[23:0]) occur simultaneously at the same clock edge. No hold time is

inserted to the chip enable and address signals. The same applies even when an output disable

delay time is inserted.

Therefore when connecting a peripheral circuit, which changes its internal state by reading, to the

bus, take a measure to insert a delay to the address and chip enable signals.

BCLK

A[23:0]

#CE4

#CE7

#RD

addr

Hazard occurrence.

This hazard causes an erroneous

RD operation on the next area.

Figure 4.23 Trouble Case

Output disable cycle

When an output disable cycle (set with output disable delay time parameter) is inserted, the chip enable

(#CExx) signal temporarily goes high. This makes an interval between the next read cycle.

Note, however, that no output dis able cycle is inserted when reading is continuously performed to the area that

is accessed with the same chip enable signal.

Bus Timing

In read cycles, the rise of the #RD signal and changing the chip enable setting (#CE4 to #CE10) and address (A23 to

A0) occur at the same clock edge.

This timing is the same even if a long setting is made for the output disable cycle by the bus controller, for example,

and changeover occurs simultaneously.

Therefore, when an I/O peripheral circuit whose internal information is changed by a read operation is connected to

the C33 bus, appropriate measures must be taken to insert a delay for the address and chip enable signals.

With an output disable cycle, there is normally a gap between one read cycle and the next. Note, h owever, that this

output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip

enable signal is output.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-22 EPSON S1C33209/221/222 FUNCTION PART

SRAM Write Cycles

Basic write cycle with no wait mode

BCLK

A[23:0]

#CExx

D[15:0]

#WRH/#WRL

#WAIT

#WR

#BSL/#BSH

,,,

addr

data

C1 C2

Figure 4 .24 Half-word Write Cycle with No Wait

BCLK

A[23:0]

#CExx

#WRH

#WRL

D[15:8]

D[7:0]

C1 C2 C3 C4

,,,

addr

Undefined Valid

Valid Undefined

Figure 4 .25 Byte Write Cycle with No Wait (A0 system, little endian)

BCLK

A[23:0]

#CExx

#BSH

#BSL

#WRL

D[15:8]

D[7:0]

C1 C2 C3 C4

,,,

addr

Undefined Valid

Valid Undefined

Figure 4 .26 Byte Write Cycle with No Wait (#BSL system, little endian)

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-23

Write cycle with wait mode

Example: When the BCU has no internal wait mode, and 1 wait cycle is inserted via the #WAIT pin

BCLK

A[23:0]

#CExx

D[15:0]

#WRH/#WRL

#WAIT

#WR

#BSL/#BSH

C1 CW C2

,,,

addr

data

Figure 4.27 Half-word Write Cycle with Wait

The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock), and the write cycle is

terminated in the cycle immediately following the cycle in which the #WAIT signal was sampled in an

inactive (high level).

Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set

to SRAM and SWAIT (D0) / Bus control register (0x4812E) is enabled for waiting.

The above example shows a write cycle when a wait mode is inserted via the #WAIT signal. A w ait mode

consisting of 2 to 7 cycles can also be inserted using the wait control bits. The settings of these bits also can be

used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling

edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait cycles set by

the wait control bits are terminated, the write cycle is not terminated at that time.

Note: The basic write cycle consists of at least two cycles. This does not change regardless of whether

zero or one wait cycle is set by the wait control bits. If the number of wait cycles set is 2 or more,

the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait

cycles + 1], as in the case of read cycles (providing that there is no external wait).

II CORE BLOCK: BCU (Bus Control Unit)

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Burst ROM Read Cycles

Burst read cycle

Example: When 4-consecutive-burst and 2-wait cycles are set during the first access

BCLK

A[23:2]

A[1:0]

#CE10(9)

D[15:0]

#RD

,,,

addr[23:2]

,,,

"11""10""01""00"

,,,,

IR3IR2

,,,,

IR1

,,,,,,,,,,,,,,

IR0

Figure 4.28 Burst Read Cycle

A burst read cycle occurs when area 10 or 9 is set for burst ROM and one of those areas is accessed for the

following reasons:

1) Instruction fetch

The burst read cycle is executed as long as a instruction fetch from contiguous addresses continues until

A[2:1] = "11" (for 4-consecutive bursts); or

A[3:1] = "111" (for 8-consecutive bursts)

2) Word (32-bit) data read out

Note: A 16-bit output is supported for the burst ROM. Set the device size to 16 bits.

Wait cycles during burst read

In the first bus operation, 0 to 7 wait cycles can be inserted using the wait control bits A10WT[2:0] (D[2:0]) /

Areas 10–9 set-up register (0x48126) in the same way as for ordinary SRAM. For the wait cycles to be inserted

in the burst cycle that follows, use a dedicated wait control bits, A10BW[1:0], which is only used for reading

bursts. The wait cycles can be set in the range from 0 to 3 using these bits.

Note that no wait cycle via the #WAIT pin can be inserted into the burst-read cycle.

Write cycle to burst ROM area

If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In

this case, wait cycles via the #WAIT pin can be inserted.

II CORE BLOCK: BCU (Bus Control Unit)

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DRAM Direct Interface

Outline of DRAM Interface

The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or areas

14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11 bits. In

addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to areas) as

well as random cycles. The refresh method (CAS-before-RAS refresh or self-refresh) and timing conditions (e.g.,

number of RAS/CAS cycles and number of precharge cycles) can be programmed using a control bit.

When selecting areas 8 and 7 or areas 14 and 13 to be used for DRAM, it depends on chip-enable settings using

CEFUNC (D9) / DRAM timing set-up register (0x48130).

CEFUNC = "00": DRAM can be connected to areas 8 and 7 (default)

#CE8 and #CE7 function as #RAS0 and #RAS1, respectively.

CEFUNC ≠ "00": DRAM can be connected to areas 14 and 13.

#CE14 and #CE13 function as #RAS2 and #RAS3, respectively.

Figure 4.29 shows a sample DRAM connection. Table 4.15 and Table 4.16 show examples of connectable DRAMs

and typical configurations.

A[9:1]

D[15:0]

#RD

#RASx(#CEx)*

#HCAS

#LCAS

#WE

S1C33

A[8:0]

I/O[15:0]

#OE

#RAS

#HCAS

#LCAS

#WE

4M DRAM

(256K x 16)

∗ x: 14, 13, 8 or 7

Figure 4.29 Sample DRAM Connection

Table 4.15 Connectable DRAM Example

DRAM Number of

devices Number of

Row bits Number of

Column bits Memory size

1M (64K x 16) 1 8 8 128K bytes

4M (256K x 16) 1 9 9 512K bytes

16M (1M x 16) 1 12 8 2M bytes

Table 4.16 DRAM Configuration Example (areas 7 and 8 only)

Area 7 Area 8 Total memory size

1 I/O DRAM (1M) 1M bits (128K bytes)

2 I/O DRAM (4M) 4M bits (512K bytes)

3 I/O DRAM (16M) 16M bits (2M bytes)

4 DRAM (1M) DRAM (1M) 2M bits (256K bytes)

5 DRAM (4M) DRAM (4M) 8M bits (1M bytes)

6 DRAM (16M) DRAM (16M) 32M bits (4M bytes)

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DRAM Setting Conditions

The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or

areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area.

Table 4.17 DRAM Interface Parameters

Parameter Selectable condition Initial setting Control bits

Page mode EDO page mode

or Fast page mode Fast page mode REDO(DC)/Bus control register(0x4812E)

RAS mode Successive RAS mode

or Normal mode Normal mode CRAS(D8)/DRAM timing set-up register(0x48130)

Column address size 8, 9, 10 or 11 bits 8 bits RCA[1:0](D[B:A])/Bus control register(0x4812E)

Refresh enable Enabled or Disabled Disabled RPC2(D9)/Bus control register(0x4812E)

Refresh method Self-refresh

or CAS-before-RAS

refresh

CBR refresh RPC1(D8)/Bus control register(0x4812E)

Refresh RPC delay 2.0 or 1.0 1.0 RPC0(D7)/Bus control register(0x4812E)

Refresh RAS pulse width 2, 3, 4 or 5 cycles 2 cycles RRA[1:0](D[6:5])/Bus control register(0x4812E)

Number of RAS precharge cycles 1, 2, 3 or 4 cycles 1 cycle RPRC[1:0](D[7:6])/DRAM timing set-up register(0x48130)

CAS cycle control 1, 2, 3 or 4 cycles 1 cycle CASC[1:0](D[4:3])/DRAM timing set-up register(0x48130)

RAS cycle control 1, 2, 3 or 4 cycles 1 cycle RASC[1:0](D[1:0])/DRAM timing set-up register(0x48130)

Page mode

The DRAM interface allows EDO DRAM to be connected directly. Therefore, the EDO-page mode is

supported along with the fast-page mode.

Use REDO to choose the desired page mode that suits the DRAM to be used.

REDO = "1": EDO page mode

REDO = "0": Fast page mode (default)

Successive RAS mode

For applications that require high-speed DRAM access, the DRAM interface supports a successive RAS mode.

In this mode, even when successive accesses to the DRAM are not requested by the CPU or DMA, the #RAS

signal is kept low and operation is continued without inserting any precharge cycle. Therefore, when accessing

the same page (row address) of the DRAM that has been accessed previously, the page mode remains active,

allowing read/write to be performed at high speeds.

However, to maintain the rated AC ch aracteristics, one idle cycle is inserted when access in the page mode is

begun and when finished.

CRAS is used to set the successive RAS mode.

CRAS = "1": Successive RAS mode

CRAS = "0": Normal mode (default)

The successive RAS mode is suspended by one of the following causes:

• a refresh cycle has occurred;

• bus control is requested by an external bus master;

• the requested device and page are not compatible with DRAM memory; and

• the slp or halt instruction is executed.

If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins.

Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE

for the low-byte write signal.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-27

Column address size

When accessing DRAM, addresses are divided into a row address and a column address as they are output.

Choose the size of this column address using RCA, as shown below.

Table 4.18 Column Address Size

RCA1 RCA0 Column address size

11 11

10 10

01 9

00 8

The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be

used.

The row addresses output synchronously with falling edges of the #RAS signal are derived from the CPU's

internal 28-bit addresses by logically shifting them to the right by an amount equal to the column address size.

The MSB contains a 1. The column addresses are output to the address bus along with the falling edges of the

#CAS signal. These addresses are derived directly from the CPU's internal 28-bit addresses.

Figure 4.30 shows the contents of the row addresses thus output.

28-bit CPU internal address

T = "1", 0–27: Bit number of CPU internal address

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(1) Row address when column address is set to 8 bits

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8T T T T T T T T

(2) Row address when column address is set to 9 bits

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9T T T T T T T T

(3) Row address when column address is set to 10 bits

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10T T T T T T T T

(4) Row address when column address is set to 11 bits

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11T T T T T T T T

T T

Figure 4.30 Example of Row/Column Address Mapping

Refresh enable

Use RPC2 to enable or disable the internal refresh function.

RPC2 = "1": Enabled

RPC2 = "0": Disabled (default)

After choosing the desired refresh method using RPC1, write "1" to RPC2.

Refresh method

The DRAM interface supports both a CAS-before-RAS refresh cycle and a self-refresh cycle. Choose the

desired method using RPC1.

RPC1 = "1": Self-refresh

RPC1 = "0": CAS-before-RAS refresh

The generation interval of the CAS-before-RAS refresh is determined by the underflow signal of an 8-bit

programmable timer 0. Consequently, before the CAS-before-RAS refresh can be executed, the 8-bit

programmable timer 0 must be set to obtain the necessary underflow timing. When this method is selected and

RPC2 is enabled, the refresh cycle is generated each time the 8-bit programmable timer 0 underflows.

The self-refresh is started by writing "1" to RPC2 while RPC1 = "1" and is terminated by clearing RPC1 or

RPC2 to "0".

If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So

be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method.

II CORE BLOCK: BCU (Bus Control Unit)

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Refresh RPC delay

Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding precharge

to the fall of #CAS).

RPC0 = "1": 2 cycles

RPC0 = "0": 1 cycle

Refresh RAS pulse width

Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle.

Table 4.19 Refresh RAS Pulse Width

RRA1 RRA0 Pulse width

1 1 5 cycles

1 0 4 cycles

0 1 3 cycles

0 0 2 cycles

The initial default value is 2 cycles.

Number of RAS precharge cycles

Use RPRC to choose the number of RAS precharge cycles.

Table 4.20 Number of RAS Precharge Cycles

RPRC1 RPRC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The initial default value is 1 cycle.

CAS cycle control

Use CASC to choose the number of CAS cycles when accessing DRAM.

Table 4.21 Number of CAS Cycles

CASC1 CASC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The initial default value is 1 cycle.

RAS cycle control

Use RASC to choose the number of RAS cycles when accessing DRAM.

Table 4.22 Number of RAS Cycles

RASC1 RASC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The initial default value is 1 cycle.

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DRAM Read/Write Cycles

The following shows the basic bus cycles of DRAM.

The DRAM interface does not accept wait cycles inserted via the #WAIT pin.

DRAM random read cycle

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#RD

D[15:0]

,,,,,,,

,,,,,,,,,,,,,

,,,,

ROW COL

data

RAS cycle CAS cycle Precharge

cycle

Figure 4.31 DRAM Random Read Cycle

DRAM read cycle (fast page mode)

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#RD

D[15:0]

,,,,,,,

,,,,,,,,,,,,,

,,,,,,,,,

ROW COL #1 COL #2

data

,,,,

data

RAS cycle CAS cycle #1 CAS cycle #2 Precharge

cycle

Figure 4.32 DRAM Read Cycle (fast page mode)

DRAM read cycle (EDO page mode)

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#RD

D[15:0]

,,,,,,,

,,,,,,,,,,,,,,,,

,,,,,,,,,

ROW COL #1 COL #2

data

RAS cycle CAS cycle #1 CAS cycle #2 Precharge

cycle

Figure 4.33 DRAM Read Cycle (EDO page mode)

The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode.

II CORE BLOCK: BCU (Bus Control Unit)

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DRAM random write cycle

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#WE

D[15:0]

,,,,,,,

,,,,,

ROW COL

write data

RAS cycle CAS cycle Precharge

cycle

Figure 4.34 2CAS Type DRAM Random Write Cycle

DRAM write cycle (fast page or EDO page mode)

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; word-write sample

,,,,,,,

ROW COL #1 COL #2

write data

RAS cycle CAS cycle #1 CAS cycle #2 Precharge

cycle

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#WE

D[15:0]

,,,,,

write data

Figure 4.35 DRAM Word-Write Cycle (fast page or EDO page mode)

Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian)

,,,,,,,

ROW COL

write data

BCLK

A[11:0]

#RASx

#HCAS

#LCAS

#WE

D[15:8]

D[7:0]

,,,,,

Undefined

,,,,,

write data

RAS cycle CAS cycle #1 CAS cycle #2 Precharge

cycle

Figure 4.36 DRAM Byte-Write Cycle (fast page or EDO page mode)

II CORE BLOCK: BCU (Bus Control Unit)

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Operation in successive RAS mode

Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#DRD

#DWE

RAS

cycle

Accsess to other

device than DRAM Not asserted for areas

other than DRAM

Precharge

cycle

Deassert

cycle Assert

cycle

CAS cycles

in page mode RAS

cycle CAS

cycles

CAS cycles

in page mode

(1) (2) (3) (4)

Figure 4.37 Operation in Successive RAS Mode

(1) When accessing the DRAM area, an ordinary RAS cycle is executed first.

(2) If access to the same DRAM is suspended during a page mode, #RASx remains asserted while some other

device is accessed. In this case, a cycle to temporarily deassert # DRD/#DWE is inserted before accessing the

other device.

(3) If access to the same page in the same DRAM area as in (1) is requested after (2), #DRD/#DWE is asserted

back again to restart the page mode.

(4) A precharge cycle is executed when one of the following conditions that cause the page mode to suspend is

encountered:

• access to different DRAM is requested;

• access to a different page in the same DRAM area is requested;

• access to some other device than DRAM is requested;

• CAS-before-RAS refresh is requested; and

• relinquishing of bus control is requested by an external bus master.

Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE

for the low-byte write signal.

II CORE BLOCK: BCU (Bus Control Unit)

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DRAM Refresh Cycles

The DRAM interface supports a CAS-before-RAS refresh cycle and a self-refresh cycle.

CAS-before-RAS refresh cycle

Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the

DRAM refresh function. Once this is done, the BCU executes a CAS-before-RAS refresh by using the

underflow signal that is output by the 8-bit programmable timer 0 as a trigger. Therefore, refresh generation

timing can be programmed using the internal prescaler and 8-bit programmable timer 0.

For details on how to control the prescaler and 8-bit programmable timer 0, refer to "Prescaler and Operating

Clock for Peripheral Circuits", and "8-Bit Programmable Timers".

Example: RPC delay: 1 cycle; Refresh RAS pulse width: 2 cycles; Precharge: 1 cycle

CAS-before-RAS refresh cycle

Refresh

RPC delay Fixed at

1 cycle Refresh

RPC pulse width Precharge

cycle

BCLK

#RAS

#HCAS/

#LCAS

,,,,,,,

,,,,

Figure 4.38 CAS-Before-RAS Refresh

When the refresh cycle is terminated, the #HCAS/#LCAS signal boot timing is 0.5 cycles before that of #RAS.

Consequently, the pulse width of #HCAS/#LCAS is determined by the refresh RAS pulse width that was set

using RRA. The number of precharge cycles after the refresh cycle is defined by the value that was set using

RPRC, the same value that is used for both random cycles and page mode accesses.

Self-refresh

To support DRAM chips equipped with a self-refresh function, the BCU has a function to generate a self-

refresh cycle.

To start a self-refresh cycle, set RPC2 to "1" after setting RPC1 to "1". To deactivate a self-refresh cycle, write

"0" to RPC1 or RPC2.

Example: RPC delay: 1 cycle

Self-refresh mode set up Self-refresh mode

deactivationSelf-refresh mode

Refresh

RPC delay Fixed at

1 cycle Precharge cycle

(6 cycles)

BCLK

#RAS

#HCAS/

#LCAS

,,,,,,,

,,,,

Figure 4.39 Self-Refresh

For a self-refresh function as well, the RPC delay is determined by setting RPC0 in the same way as for a

CAS-before-RAS refresh.

The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and is

unaffected by settings of RRA.

#RAS and #HCAS/#LCAS are booted up simultaneously upon completion of a self-refresh and the precharge

duration that follows is fixed at 6 cycles.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-33

Normally, DRAM specifications require that the contents of all row addresses be refreshed within a certain time

before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is executed by

a program. In this case, set the 8-bit programmable timer 0 so that the contents of all row addresses are

refreshed within a predetermined time.

Note: If read from or write to the DRAM under a self-refresh is attempted, the BCU keeps #RAS and

#HCAS/#LCAS low as it executes a read/write cycle. Other bus signals than #RAS and

#HCAS/#LCAS (e.g., address, data, and control signals) change their state according to the

specified conditions. Since said attempt initiates an invalid access to the DRAM, do not read from

or write to the D RAM during a self-refresh.

Releasing External Bus

The external bus is normally controlled by the CPU, but the BCU is designed to release control of the bus ownership

to an external device. This function is enabled by writing "1" to SEMAS (D2) / Bus control register (0x4812E)

(disabled by default). The #BUSREQ (P34) and #BUSACK (P35) pins are used for control of the bus ownership.

To direct the P34 and P35 pins for input/output of the #BUSREQ and #BUSACK signals, write "1" to CFP34 (D4)

and CFP35 (D5) / P3 function select register (0x402DC [Byte]).

Sequence in which control of the bus is released

This sequence is described below.

1. The external bus master device requesting control of the bus ownership lowers the #BUSREQ pin.

2. The CPU keeps monitorin g the status of the #BUSREQ pin, so that when this pin is lower, the CPU

terminates the bus cycle being executed and places the signals listed below in high-impedance state one

cycle later:

A[23:0], D[15:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CExx

Then the CPU lowers the #BUSACK pin to inform the external device that control of the bus ownership has

been released.

3. One cycle later, the external bus starts its own bus cycle. The external bus master must hold the #BUSREQ

pin low until the bus cycle is completed.

4. After completing the necessary bus cycles, the external bus master places the bus in high-impedance state

and releases the #BUSREQ pin back high.

5. After confirming that the #BUSREQ pin is raised again, the CPU raises the #BUSACK pin one cycle later

and resumes the processing that has been suspended.

BCLK

#BUSREQ

#BUSACK

D[15:0]

A[23:0]

#RD, #WR

Synchronization

The S1C33

terminates the bus

cycle being executed. The S1C33

controls bus cycles.1 cycle 1 cycle

Hi-Z

1 cycle

The external bus master

controls bus cycles.

Figure 4.40 External Bus Release Timing

If control of the bus ownership is requested during a DMA transfer by the internal DMA controller, the DMA

transfer under way is suspended at a break in data to accept the request for bus ownership control. The DMA

transfer that has been kept pending is restarted when the CPU gains control of the bus ownership.

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DRAM refresh when bus ownership control is released

In systems where DRAM is connected directly, a refresh request could arise while control of the bus ownership

is released from the CPU. In such a case, take one of the corrective measures described below.

• Monitoring the output signal of the 8-bit programmable timer 0

The underflow signal (DRAM refresh request) of the 8-bit programmable timer 0 can be output from the P10

I/O port pin.

If a refresh request arises while the external bus master is monitoring this output, release #BUSREQ back high

to drop the request for bus ownership control.

Start a DRAM refresh cycle when control of the bus ownership is returned to the CPU.

To direct the P10 pin in order to output the underflow signal of the 8-bit programmable timer 0, write "1" to

CFP10 (D0) / P1 function select register (0x402D4 [Byte]) and IOC10 (D0) / P1 I/O control register (0x402D6

[Byte]). Also, to output the underflow signal to an external device, write "1" to PTOUT0 (D2) / 8-bit Timer 0

control register (0x40160 [Byte]). For details about output control, refer to "8-Bit Programmable Timers".

• Monitoring the #BUSGET signal

The #BUSGET signal can be output from the P31 I/O port pin.

The #BUSGET signal is derived from logical sum of the following signals:

1. DRAM refresh request signal (output from the 8-bit programmable timer 0)

2. Interrupt request signal from the interrupt controller to the CPU

3. Startup request signal from the interrupt controller to the IDMA

If the #BUSGET signal is found to be active when the external bus master is monitoring it, release #BUSREQ

back high to drop the request for bus ownership control.

When using the #BUSGET signal to only monitor a refresh request, set the interrupt controller in such a way

that no interrupt request or IDMA startup request will be generated.

To direct the P31 pin for output of the #BUSGET signal, write "1" to CFEX3 (D3) / Port function extension

Power-down Control by External Device

In addition to requesting the releasing of bus ownership co ntrol described above, it is possible to place the CPU in a

HALT state by using the #BUSREQ signal. This allows the CPU to be stopped during bus operation by an external

bus master in order to conserve power.

This function is enabled by writing "1" to SEPD (D1) / Bus control register (0x4812E).

If SEPD = "1", the CPU and the BCU stop operating when the #BUSREQ pin is lowered, thus entering a HALT state.

This HALT state is not cleared by an interrupt from the internal peripheral circuits and remains set until the

#BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address

bus and bus control signals are not placed in high-impedance state.

For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above.

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I/O Memory of BCU

Table 4.23 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following

addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or

words, as well as in half-words.

For the control bits of the external system interface pins assigned to the I/O ports, and for details on how to control

the 8-bit programmable timer 0 in order to generate a DRAM refresh cycle, refer to each corresponding section in

this manual.

Table 4.23 Control Bits of External System Interface

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A18SZ

A18DF1

A18DF0

–

A18WT2

A18WT1

A18WT0

–

A16SZ

A16DF1

A16DF0

–

A16WT2

A16WT1

A16WT0

reserved

Areas 18–17 device size selection

Areas 18–17

output disable delay time

reserved

Areas 18–17 wait control

reserved

Areas 16–15 device size selection

Areas 16–15

output disable delay time

reserved

Areas 16–15 wait control

–

1 8 bits 0 16 bits

1 8 bits 0 16 bits –

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

0048120

(HW)

Areas 18–15

set-up register

A18DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A16DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A18WT[2:0] Wait cycles

A16WT[2:0] Wait cycles

–

A14DRA

A13DRA

A14SZ

A14DF1

A14DF0

–

A14WT2

A14WT1

A14WT0

DF–9

reserved

Area 14 DRAM selection

Area 13 DRAM selection

Areas 14–13 device size selection

Areas 14–13

output disable delay time

reserved

Areas 14–13 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

0 when being read.

0048122

(HW)

A14DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A14WT[2:0] Wait cycles

Areas 14–13

set-up register

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B-II-4-36 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A12SZ

A12DF1

A12DF0

–

A12WT2

A12WT1

A12WT0

DF–7

reserved

Areas 12–11 device size selection

Areas 12–11

output disable delay time

reserved

Areas 12–11 wait control

–

1 8 bits 0 16 bits –

–

R/W

–

R/W

0 when being read.

0048124

(HW)

Areas 12–11

set-up register

A18DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A18WT[2:0] Wait cycles

–

A10IR2

A10IR1

A10IR0

–

A10BW1

A10BW0

A10DRA

A9DRA

A10SZ

A10DF1

A10DF0

–

A10WT2

A10WT1

A10WT0

reserved

Area 10 internal ROM size

selection

reserved

Areas 10–9

burst ROM

burst read cycle wait control

Area 10 burst ROM selection

Area 9 burst ROM selection

Areas 10–9 device size selection

Areas 10–9

output disable delay time

reserved

Areas 10–9 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

–

R/W

0 when being read.

0048126

(HW)

A10BW[1:0] Wait cycles

A10DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A10IR[2:0] ROM size

2MB

1MB

512KB

256KB

128KB

64KB

32KB

16KB

A10WT[2:0] Wait cycles

Areas 10–9

set-up register

–

A8DRA

A7DRA

A8SZ

A8DF1

A8DF0

–

A8WT2

A8WT1

A8WT0

DF–9

reserved

Area 8 DRAM selection

Area 7 DRAM selection

Areas 8–7 device size selection

Areas 8–7

output disable delay time

reserved

Areas 8–7 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

0 when being read.

0048128

(HW)

Areas 8–7

set-up register

A8DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A8WT[2:0] Wait cycles

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-37

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A6DF1

A6DF0

–

A6WT2

A6WT1

A6WT0

–

A5SZ

A5DF1

A5DF0

–

A5WT2

A5WT1

A5WT0

DF–E

reserved

Area 6

output disable delay time

reserved

Area 6 wait control

reserved

Areas 5–4 device size selection

Areas 5–4

output disable delay time

reserved

Areas 5–4 wait control

–

1 8 bits 0 16 bits

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

004812A

(HW)

Areas 6–4

set-up register 1

A6DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A5DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A6WT[2:0] Wait cycles

A5WT[2:0] Wait cycles

RBCLK

–

RBST8

REDO

RCA1

RCA0

RPC2

RPC1

RPC0

RRA1

RRA0

–

SBUSST

SEMAS

SEPD

SWAITE

BCLK output control

reserved

Burst ROM burst mode selection

DRAM page mode selection

Column address size selection

Refresh enable

Refresh method selection

Refresh RPC delay setup

Refresh RAS pulse width

selection

reserved

External interface method selection

External bus master setup

External power-down control

#WAIT enable

–

1 Fixed at H 0 Enabled

8-successive

4-successive

1 Enabled 0 Disabled

1 Self-refresh 0

CBR-refresh

1 2.0 0 1.0

1 #BSL 0 A0

1 Existing 0 Nonexistent

1 Enabled 0 Disabled

1 EDO 0 Fast page

R/W

–

R/W

–

R/W

Writing 1 not allowed.

004812E

(HW)

RCA[1:0] Size

RRA[1:0] Number of cycles

Bus control

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-38 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

1 Successive 0 Normal

–

A3EEN

CEFUNC1

CEFUNC0

CRAS

RPRC1

RPRC0

–

CASC1

CASC0

–

RASC1

RASC0

DF–C

reserved

Area 3 emulation

#CE pin function selection

Successive RAS mode setup

DRAM

RAS precharge cycles selection

reserved

DRAM

CAS cycles selection

reserved

DRAM

RAS cycles selection

– –

–

R/W

–

R/W

–

R/W

0 when being read.

0048130

(HW)

CFFUNC[1:0]

#CE output

#CE7/8..#CE17/18

#CE6..#CE17

#CE4..#CE10

RPRC[1:0] Number of cycles

–

CASC[1:0] Number of cycles

–

RASC[1:0] Number of cycles

DRAM timing

set-up register 1

Internal ROM

0 Emulation

–

1 Internal

access 0 External

access

1 Internal

access 0 External

access

1 Big endian 0

Little endian

A18IO

A16IO

A14IO

A12IO

–

A8IO

A6IO

A5IO

A18EC

A16EC

A14EC

A12EC

A10EC

A8EC

A6EC

A5EC

Area 18, 17 internal/external access

Area 16, 15 internal/external access

Area 14, 13 internal/external access

Area 12, 11 internal/external access

reserved

Area 8, 7 internal/external

access

Area 6 internal/external

access

Area 5, 4 internal/external

access

Area 18, 17 endian control

Area 16, 15 endian control

Area 14, 13 endian control

Area 12, 11 endian control

Area 10, 9 endian control

Area 8, 7 endian control

Area 6 endian control

Area 5, 4 endian control

R/W

–

R/W

0 when being read.

0048132

(HW)

Access control

–

1 Enabled 0 Disabled

A18AS

A16AS

A14AS

A12AS

–

A8AS

A6AS

A5AS

A18RD

A16RD

A14RD

A12RD

–

A8RD

A6RD

A5RD

Area 18, 17 address strobe signal

Area 16, 15 address strobe signal

Area 14, 13 address strobe signal

Area 12, 11 address strobe signal

reserved

Area 8, 7 address strobe signal

Area 6 address strobe signal

Area 5, 4 address strobe signal

Area 18, 17 read signal

Area 16, 15 read signal

Area 14, 13 read signal

Area 12, 11 read signal

reserved

Area 8, 7 read signal

Area 6 read signal

Area 5, 4 read signal

R/W

–

R/W

–

R/W

0 when being read.

0048138

(HW)

G/A read signal

control register

–

1 Enabled 0 Disabled

–

A1X1MD

–

BCLKSEL1

BCLKSEL0

D7–4

reserved

Area 1 access-speed

reserved

BCLK output clock selection 1

BCLKSEL[1:0]

–

–BCLK

PLL_CLK

OSC3_CLK

BCU_CLK

CPU_CLK

–

R/W

–

R/W

0 when being read.

x2 speed mode only

0 when being read.

004813A

(B)

BCLK select

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-39

A18SZ: Areas 18–17 device size selection (DE) / Areas 18–15 set-up register (0x48120)

A16SZ: Areas 16–15 device size selection (D6) / Areas 18–15 set-up register (0x48120)

A14SZ: Areas 14–13 device size selection (D6) / Areas 14–13 set-up register (0x48122)

A12SZ: Areas 12–11 device size selection (D6) / Areas 12–11 set-up register (0x48124)

A10SZ: Areas 10–9 device size selection (D6) / Areas 10–9 set-up register (0x48126)

A8SZ: Areas 8–7 device size selection (D6) / Areas 8–7 set-up register (0x48128)

A5SZ: Areas 5–4 device size selection (D6) / Areas 6–4 set-up register (0x4812A)

Select the size of the device connected to each area.

Write "1": 8 bits

Write "0": 16 bits

Read: Valid

A device size can be selected for every two areas.

An 8-bit size is selected by writing "1" to AxxSZ and a 16-bit size is selected by writing "0" to AxxSZ.

Area 6 has its first half (0x300000 through 0x37FFFF) fixed to an 8-bit device and the last half (0x380000 through

0x3FFFFF) fixed to a 16-bit device.

At cold start, these bits are set to "0" (16 bits). At hot start, these bits retain their status before being initialized.

A18DF1–A18DF0:Areas 18–17 output disable delay time (D[D:C]) / Areas 18–15 set-up register (0x48120)

A16DF1–A16DF0:Areas 16–15 output disable delay time (D[5:4]) / Areas 18–15 set-up register (0x48120)

A14DF1–A14DF0:Areas 14–13 output disable delay time (D[5:4]) / Areas 14–13 set-up register (0x48122)

A12DF1–A12DF0:Areas 12–11 output disable delay time (D[5:4]) / Areas 12–11 set-up register (0x48124)

A10DF1–A10DF0:Areas 10–9 output disable delay time (D[5:4]) / Areas 10–9 set-up register (0x48126)

A8DF1–A8DF0:Areas 8– 7 output disable delay time (D[5:4]) / Areas 8–7 set-up register (0x48128)

A6DF1–A6DF0:Area 6 output disable delay time (D[D:C]) / Areas 6–4 set-u p register (0x4812A)

A5DF1–A5DF0:Areas 5– 4 output disable delay time (D[5:4]) / Areas 6–4 set-up register (0x4812A)

Set the output-disable delay time. Table 4.24 Output Disable Delay Time

AxxDF1 AxxDF0 Delay time

1 1 3.5 cycles

1 0 2.5 cycles

0 1 1.5 cycles

0 0 0.5 cycles

When using a device that has a long output-disable time, set a delay time to ensure that no contention for the data bus

occurs during the bus operation immediately after a device is read.

At cold start, these bits are set to "11" (3.5 cycles). At hot start, the bits retain their status before being initialized.

A18WT2–A18WT0:Areas 18–17 wait control (D[A:8]) / Areas 18–15 set-up register (0x48120)

A16WT2–A16WT0:Areas 16–15 wait control (D[2:0]) / Areas 18–15 set-up register (0x48120)

A14WT2–A14WT0:Areas 14–13 wait control (D[2:0]) / Areas 14–13 set-up register (0x48122)

A12WT2–A12WT0:Areas 12–11 wait control (D[2:0]) / Areas 12–11 set-up register (0x48124)

A10WT2–A10WT0:Areas 10–9 wait control (D[2:0]) / Areas 10–9 set-up register (0x48126)

A8WT2–A8WT0: Areas 8–7 wait control (D[2:0]) / Areas 8–7 set-up register (0x48128)

A6WT2–A6WT0: Area 6 wait control (D[A:8]) / Areas 6–4 set-up register (0x4812A)

A5WT2–A5WT0: Areas 5–4 wait control (D[2:0]) / Areas 6–4 set-up register (0x4812A)

Set the number of wait cycles to be inserted when accessing an SRAM device.

The values 0 through 7 written to the control bits equal the number of wait cycles inserted.

Note that the write cycle consists of a minimum of two cycles, so that a writing 0 or 1 is invalid.

When an SRAM device is connected, wait cycles derived via the #WAIT pin can also be inserted. In this case too, the

wait cycles set by AxxWT are valid.

The DRAM read/write cycles do not have wait cycles inserted that are set by AxxWT or derived from the #WAIT pin.

The burst read cycle of a burst ROM (except for the first access) also does not have any wait cycle inserted. The first

read cycle of a burst ROM and the write cycle to the burst RO M area have wait cycles inserted that are set by

AxxWT . Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area.

At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-40 EPSON S1C33209/221/222 FUNCTION PART

A14DRA:Area 14 DRAM selection (D8) / Areas 14–13 set-up register (0x48122)

A13DRA:Area 13 DRAM selection (D7) / Areas 14–13 set-up register (0x48122)

A8DRA: Area 8 DRAM selection (D8) / Areas 8–7 set-up register (0x48128)

A7DRA: Area 7 DRAM selection (D7) / Areas 8–7 set-up register (0x48128)

Select the DRAM direct interface.

Write "1": DRAM is used

Write "0": DRAM is not used

Read: Valid

When DRAM is used by connecting it directly to the BCU, write "1" to this bit. The ordinary SRAM interface is

selected by writing "0" to the control bit.

The areas to which DRAM can be connected are areas 8 and 7 when the CEFUNC = "0", or areas 14 and 13 when the

bit = "1".

At cold start, these bits are set to "0" (DRAM not used ). At hot start, the bits retain their status before being

initialized.

A10IR2–A10IR0: Area 10 internal ROM size selection (D[D:B]) / Areas 10–9 set-up register (0x48126)

Select an area 10 internal/emulation memory size.

Table 4.25 Area 10 Internal ROM Size

A10IR2 A10IR1 A10IR0 ROM size

0 0 0 16 KB

0 0 1 32 KB

0 1 0 64 KB

0 1 1 128 KB

1 0 0 256 KB

1 0 1 512 KB

1 1 0 1 MB

1 1 1 2 MB

At cold start, A10IR is set to "111" (2 MB). At hot start, A10IR retains its status before being initialized.

A10BW1–A10BW0: Burst read cycle wait control (D[A:9]) / Areas 10–9 set-up register (0x48126)

Set the number of wait cycles inserted during a burst read.

The values 0 to 3 written to the bits constitute the number of wait cycles inserted. The contents set here are applied to

both areas 10 and 9. The wait cycles set by AxxWT are inserted in the first read cycle of burst ROM and in the burst

ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used.

At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-41

A10DRA:Area 10 burst ROM selection (D8) / Areas 10–9 set-up register (0x48126)

A9DRA: Area 9 burst ROM sele ction (D7) / Areas 10–9 set-up register (0x48126)

Set areas 10 and 9 for use of burst ROM.

Write "1": Burst ROM is used

Write "0": Burst ROM is not used

Read: Valid

When using burst ROM, write "1" to the control bit. The ordinary SRAM interface is se lected by writing "0" to the

bit.

Area 9 can only be used when the CEFUNC = "00".

At cold start, these bits are set to "0" (burst ROM not used). At hot start, the bits retain their status before being

initialized.

RBCLK: BCLK output control (DF) / Bus control register (0x4812E)

Control the bus clock BCLK to enable or disable external output.

Write "1": Fixed at high level

Write "0": Output enabled

Read: Valid

To stop outputting the bus clock from the BCLK pin, write "1" to RBCLK. When the clock output is stopped, the

BCLK pin is fixed at high level. The bus clock output from the BCLK pin is enabled by writing "0" to RBCLK.

The bus clock output from the BCLK pin also is stopped in the HALT2 and the SLEEP modes.

At cold start, the RBCLK is set to "0" (output enabled). At hot start, RBCLK retains its status before being

initialized.

RBST8: Burst mode selection (DD) / Bus control register (0x4812E)

Set the operation mode during a burst read.

Write "1": 8-successive-burst mode

Write "0": 4-successive-burst mode

Read: Valid

The 8-successive-burst mode is selected by writing "1" to RBST8 and the 4-successive-burst mode is selected by

writing "0" to RBST8. This setting is valid when areas 10 and 9 are set for burst ROM, and the setting is applied to

both areas simultaneously.

At cold start, RBST8 is set to "0" (4-successive-burst mode). At hot start, RBST8 retains its status before being

initialized.

REDO: Page mode selection (DC) / Bus control register (0x4812E)

Select the page mode of DRAM.

Write "1": EDO-page mode

Write "0": Fast-page mode

Read: Valid

When using EDO DRAM, write "1" to REDO to select the EDO-page mode.

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-42 EPSON S1C33209/221/222 FUNCTION PART

RCA1–RCA0: Column address size selection (D[B:A]) / Bus control register (0x4812E)

Select the column address size of DRAM.

Table 4.26 Column Address Size

RCA1 RCA0 Column address size

11 11

10 10

01 9

00 8

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

RCA can be read to obtain its set value.

At cold start, RCA is set to "0" (8 bits). At hot start, RCA retain its status before being initialized.

RPC2: Refresh enable (D9) / Bus control register (0x4812E)

Control the DRAM refresh function.

Write "1": Enabled

Write "0": Disabled

Read: Valid

When DRAM is connected directly, a refresh cycle is generated by writing "1" to RPC2. The internal refresh

function is disabled by writing "0" to RPC2.

Since the BCU stops operating in the HALT2 and the SLEEP modes, no refresh cycle is generated regardless of how

this bit is set.

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RPC2 is set to "0" (disabled). At hot start, RPC2 retains its status before being initialized.

RPC1: Refresh method selection (D8) / Bus control register (0x4812E)

Select the DRAM refresh method.

Write "1": Self-refresh

Write "0": CAS-before-RAS refresh

Read: Valid

To perform a CAS-before-RAS refresh, set RPC1 to "0" and then RPC2 to "1". This causes the underflow output

signal of the 8-bit programmable timer 0 is fed to the DRAM interface, at which timing a refresh cycle is generated.

To start a self-refresh, set RPC1 to "1" and then RPC2 to "1". The self-refresh is disabled by writing "0" to RPC2.

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RPC1 is set to "0" (CAS-before-RAS refresh). At hot start, RPC1 retains its status before being

initialized.

RPC0: Refresh RPC delay (D7) / Bus control register (0x4812E)

Set a RPC delay when at start of refresh.

Write "1": 2 cycles

Write "0": 1 cycle

Read: Valid

Set a time from the immediately preceding precharge to the falling transition of #HCAS/#LCAS necessary in order to

perform a refresh. This time is 2 cycles when RPC0 = "1" or 1 cycle when RPC0 = "0".

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-43

RRA1–RRA0: Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E)

Select the RAS pulse width of a CAS-before-RAS refresh.

Table 4 . 27 Refresh RAS Pulse Width

RRA1 RRA0 Pulse width

1 1 5 cycles

1 0 4 cycles

0 1 3 cycles

0 0 2 cycles

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

The RRA can be read to obtain their set value.

At cold start, RRA is set to "0" (2 cycles). At hot start, RRA retains its status before being initialized.

SBUSST: External interface method select register (D3) / Bus control register (0x4812E)

Select the interface method of an SRAM device.

Write "1": #BSL system

Write "0": A0 system

Read: Valid

When using the #BSL system, write "1" to SBUSST.

The contents set here are applied to all areas that are set for the SRAM type.

At cold start, SBUSST is set to "0" (A0 system). At hot start, SBUSST retains its status before being initialized.

SEMAS: External bus master setup (D2) / Bus control register (0x4812E)

Specify whether an external bus master exists.

Write "1": Existing

Write "0": Nonexistent

Read: Valid

A request for bus ownership control via the #BUSREQ pin is made acceptable by writing "1" to SEMAS. If the

system does not have any external bus master, fix this register at "0".

At cold start, SEMAS is set to "0" (nonexistent). At hot start, SEMAS retains its status before being initialized.

SEPD: External power-down control (D1) / Bus control register (0x4812E)

Enable or disable the CPU's power-down control by an external bus master.

Write "1": Enabled

Write "0": Disabled

Read: Valid

Power-down control via an external pin (#BUSREQ) is enabled by writing "1" to SEPD. If the #BUSREQ pin is

lowered when external power-down control i s thus enabled, the CPU is placed in a HALT state, allowing for

reduction in power consumption.

At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-44 EPSON S1C33209/221/222 FUNCTION PART

SWAITE: #WAIT enable (D0) / Bus control register (0x4812E)

Enable or disable wait cycle control via the #WAIT pin.

Write "1": Enabled

Write "0": Disabled

Read: Valid

A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input

from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle. Wait

cycles are inserted until the wait request signal is sampled and detected as high (inactive).

Wait control for 0 to 7 cycles can be accomplished by AxxWT without using the #WAIT pin. However, since the

setting via AxxWT is applied to every two areas, the number of wait cycles may be controlled individually in each area

or more than 7 wait cycles may be set. In such a case, use an external wait request via the #WAIT pin.

Wait requests from the #WAIT pin are ignored when SWAITE = "0".

The contents set here are applied to all areas that are set for SRAM, and are also effective for write cycles in the areas

that are set for burst ROM.

At cold start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized.

A3EEN: Area 3 emulation (DB) / DRAM timing set-up register (0x48130)

Select area 3 emulation mode.

Write "1": Internal ROM mode

Write "0": Emulation mode

Read: Valid

When "0" is written to A3EEN, internal ROM emulation mode is selected and the external device will be accessed

with the same condition as the internal ROM. When "1" is written, the internal ROM will be used for accessing area

3. This bit functions the same as the EA3MD pin. The bit status and the pin status are logically ORed.

At cold start, A3EEN is set to "1" (internal ROM mode). At hot start, A3EEN retains its status before being

initialized.

CEFUNC1–CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130)

Change the #CE pin-assigned area.

Table 4.28 #CE Output Assignment

Pin CEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"

#CE4 #CE4 #CE11 #CE11+#CE12

#CE5 #CE5 #CE15 #CE15+#CE16

#CE6 #CE6 #CE6 #CE7+#CE8

#CE7/#RAS0 #CE7/#RAS0 #CE13/#RAS2 #CE13/#RAS2

#CE8/#RAS1 #CE8/#RAS1 #CE14/#RAS3 #CE14/#RAS3

#CE9 #CE9 #CE17 #CE17+#CE18

#CE10EX #CE10EX #CE10EX #CE9+#CE10EX

(Default: CEFUNC = "00")

The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the default

low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7 and 8.

However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other areas.

Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size.

At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialize d.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-45

CRAS: Successive RAS mode (D8) / DRAM timing set-up register (0x48130)

Set the successive RAS mode.

Write "1": Successive RAS mode

Write "0": Normal mode

Read: Valid

In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write

operations can be performed in page mode even when DRAM accesses do not occur back-to-back.

When using the successive RAS mode, be sure to use #DRD for the read signal and #DWE for the write signal for

low-byte.

When CRAS = "0", random read/write cycles are used for non-successive DRAM accesses.

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, CRAS is set to "0" (normal mode). At hot start, CRAS retains its status before being initialized.

RPRC1–RPRC0: Number of RAS precharge cycles (D[7:6]) / DRAM timing set-up register (0x48130)

Select the number of precharge cycles during a DRAM access.

Table 4.29 Number of RAS Precharge Cycles

RPRC1 RPRC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RPRC is set to "0" (1 cycle). At hot start, RPRC retains its status before being initialized.

CASC1–CASC0: Number of CAS cycles (D[4:3]) / DRAM timing set-up register (0x48130)

Select the number of CAS cycles during a DRAM access.

Table 4.30 Number of CAS Cycles

CASC1 CASC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, CASC is set to "0" (1 cycle). At hot start, CASC retains its status before being initialized.

RASC1–RASC0: Number of RAS cycles (D[1:0]) / DRAM timing set-up register (0x48130)

Select the number of RAS cycles during a DRAM access.

Table 4.31 Number of RAS Cycles

RASC1 RASC0 Number of cycles

1 1 4 cycles

1 0 3 cycles

0 1 2 cycles

0 0 1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before bein g initialized.

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-46 EPSON S1C33209/221/222 FUNCTION PART

A18IO: Areas 18–17 internal/external access selection (DF) / Access control register (0x48132)

A16IO: Areas 16–15 internal/external access selection (DE) / Access control register (0x48132)

A14IO: Areas 14–13 internal/external access select ion (DD) / Access control register (0x48132)

A12IO: Areas 12–11 internal/external access selection (DC) / Access control register (0x48132)

A8IO: Areas 8–7 internal/external access selection (DA) / Access control register (0x48132)

A6IO: Area 6 internal/ex ternal access selection (D9) / Access control register (0x48132)

A5IO: Areas 5–4 internal/external access selection (D8) / Access control register (0x48132)

Select either internal access or external access for each area.

Write "1": Internal access

Write "0": External access

Read: Valid

When AxxIO is set to "1", the internal device that mapped to the corresponding area is accessed. When AxxIO is set

to "0", the external device is accessed.

At cold start, these bits are set to "0" (external access). At hot start, these bits retain their status before being

initialized.

A18EC: Areas 18–17 little/big endian method selection (D7) / Access control register (0x48132)

A16EC: Areas 16–15 little/big endian method selection (D6) / Access control register (0x481 32)

A14EC: Areas 14–13 little/big endian method selection (D5) / Access control register (0x48132)

A12EC: Areas 12–11 little/big endian method selection (D4) / Access control register (0x48132)

A10EC: Areas 10–9 little/big endian method selection (D3) / Access control register (0x48132)

A8EC: Areas 8–7 little/big endian method selection (D2) / Access control register (0x48132)

A6EC: Area 6 little/big endian method selection (D1) / Access control register (0x48132)

A5EC: Areas 5–4 little/big endian method se lection (D0) / Access control register (0x48132)

Select either little endian or big-endian method for accessing each area.

Write "1": Big-endian

Write "0": Little-endian

Read: Valid

When AxxEC is set to "1", the corresponding area is accessed in big- endian method. When AxxEC is set to "0", the

area is accessed in little-endian method. When using area 10 as the boot area, fix A10EC at "0" (little-endian).

At cold start, these bits are set to "0" (little-endian). At hot start, these bits retain their status before being initialized.

A18AS: Areas 18–17 address strobe signal (DF) / G/A read signal control register (0x48138)

A16AS: Areas 16–15 address strobe signal (DE) / G/A read signal control register (0x48138)

A14AS: Areas 14–13 address strobe signal (DD) / G/A read signal control register (0x48138)

A12AS: Areas 12–11 address strobe signal (DC) / G/A read signal control register (0x48138)

A8AS: Areas 8–7 address strobe signal (DA) / G/A read signal control register (0x48138)

A6AS: Area 6 address strobe signal (D9) / G/A read signal control register (0x48138)

A5AS: Areas 5–4 address strobe signal (D8) / G/A read signal control register (0x48138)

Enable/disable the exclusive address strobe signal output.

Write "1": Enabled

Write "0": Disabled

Read: Valid

If AxxAS is set to "1", the exclusive address strobe signal is output from #GAAS (P21) pin when the corresponding

area is accessed. If AxxAS is set to "0", the signal output is disabled.

At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized.

II CORE BLOCK: BCU (Bus Control Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-4-47

A18RD: Areas 18–17 read signal (D7) / G/A read signal control register (0x48138)

A16RD: Areas 16–15 read signal (D6) / G/A read signal control register (0x48138)

A14RD: Areas 14–13 read signal (D5) / G/A read signal control register (0x48138)

A12RD: Areas 12–11 read signal (D4) / G/A read signal control register (0x48138)

A8RD: Areas 8–7 read signal (D2) / G/A read signal control register (0x48138)

A6RD: Area 6 read signal (D1) / G/A read signa l control register (0x48138)

A5RD: Areas 5–4 read signal (D0) / G/A read signal control register (0x48138)

Enable/disable the exclusive read signal output.

Write "1": Enabled

Write "0": Disabled

Read: Valid

If AxxRD is set to "1", the exclusive read signal is output from #GARD (P31) pin when the corresponding area is

read. If AxxRD is set to "0", the signal output is disabled.

At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized.

BCLKSEL1–BCLKSEL0: BCLK output clock selection (D[1:0]) / BCLK select register (0x4813A)

Select a clock to be output from the BCLK pin.

Table 4.32 Selection of BCLK Output Clock

BCLKSEL1 BCLKSEL0 Output clock

1 1 PLL_CLK (PLL output clock)

1 0 OSC3_CLK (OSC3 oscillation clock)

0 1 BCU_CLK (BCU operating clock)

0 0 CPU_CLK (CPU operating clock)

PLL_CLK: PLL output clock. This clock is stable and kept as output except in the following cases:

1. When the PLL i s off by setting the PLLS[1:0] pins.

2. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction.

3. When the OSC3 (high-speed) oscillation is stopped using the CLG register.

Note that the PLL_CLK clock is out of phase with the CPU operating clock.

OSC3_CLK: OSC3 (high-speed) oscillation circuit output clock. This clock is stable and kept as output except in the

following cases:

1. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction.

2. When the OSC3 (high-speed) oscillation is stopped using the CLG register.

Note that the OSC3_CLK clock is out of phase with the CPU operating clock.

BCU_CLK: Bus clock in the bus controller. This clock varies according to the bus cycle speed. Furthermore, the

clock frequency changes dynamically in x2 speed mode as follows:

1. When the internal RAM/ROM is accessed, x2 clock (e.g., 50 MHz same as the CPU operating

clock) is output.

2. When an external device is accessed via the external bus, x1 clock (e.g., 25 MHz) is output.

This dynamic change (e.g., between 50 MHz and 25 MHz) does not affect the external memory access

timing, such as position relationship between the rising or falling edge of the 25 MHz clock and the

falling edge of the #WR signal. (It is the same as that in the x1 speed mode with 25 MHz clock.)

CPU_CLK: The CPU operating clock. The clock frequency is as follows:

1. Equals to the PLL output clock frequency when the PLL is on.

2. Equals to the OSC3 (high-speed) oscillation circuit output clock frequency when the PLL is off.

3. However, it equals to the divided frequency when the CLG is set to generate the CPU operating

clock by dividing the source clock.

4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped.

This clock is almost in phase with the bus clock.

At initial reset, BCLKSEL is set to "0" (CPU_CLK).

II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-48 EPSON S1C33209/221/222 FUNCTION PART

A1X1MD: Area 1 access speed (D3) / BCLK select register (0x4813A)

Select a number of access cycles for area 1 in x2 speed mode.

Write "1": 2 cycles

Write "0": 4 cycles

Read: Valid

When x2 speed mode is set (#X2SPD pin = L) and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU

system clock.

When A1X1MD = "0", area 1 is read/written in 4 cycles.

When x1 speed mode is set (#X2SPD pin = H), area 1 is always accessed in 2 cycles regardless of the A1X1MD

value.

At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized.

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-1

II-5 ITC (Interrupt Controller)

The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by the

internal peripheral circuits. This section explains the functions of this interrupt controller centering around the

method for controlling maskable interrupts. For details about the various factors and conditions under which

interrupts are ge nerated, refer to the description of each peripheral circuit in this manual.

Outline of Interrupt Functions

Maskable Interrupts

The ITC can handle 39 kinds of maskable interrupts as shown in the table below.

Table 5.1 List of Maskable Interrupts

No. HEX

No. Vector number

(Hex address) Interrupt system

(Peripheral circuit) Interrupt factor IDMA

Ch. Priority

ase

rt inp

t int

dge

(

r f

llin

r l

(

r L

)

1Hi

21117

(

ase

+44

)

rt inp

t int

pt 1 E

dge

(

r f

llin

r l

(

r L

)

2↑

12 1

ase

rt inp

t int

pt 2 E

dge

(

r f

llin

r l

(

r L

)

ase

rt inp

t int

dge

(

r f

llin

r l

(

r L

)

14 2

ase

50)

inp

t int

r f

llin

edge

–

(

ase

)

inp

t int

pt 1 Ri

r f

llin

edge

–

(

ase

58)

eed

DMA

eed

DMA

f tr

17 2

ase

5C)

eed

DMA

h.1 Hi

eed

DMA

h.1

f tr

(

ase

60)

eed

DMA

h.2 Hi

eed

DMA

h.2

f tr

r–

ase

)

eed

DMA

eed

DMA

f tr

r–

11 1A 2

ase

68)

IDMA Int

lli

nt DMA

f tr

r–

–27–2

ese

––

12 1E

30(

ase

it pr

tim

Tim

n B 7

(

ase

Tim

n A

–

2–

ese

––

14 22

(

ase

88)

it pr

tim

r 1 Tim

r 1

n B

35(

ase

8C)

Tim

r 1

n A 1

–

ese

––

38(

ase

98)

it pr

tim

r 2 Tim

r 2

n B 11

17 27

39(

ase

9C)

Tim

r 2

n A 12

–4

–41 r

ese

––

2A 42

(

ase

it pr

tim

Tim

n B 1

2B 4

ase

Tim

n A 14

–44–4

ese

––

2E 4

ase

it pr

tim

r 4 Tim

r 4

n B 1

21 2F 47

(

ase

Tim

r 4

n A 1

–4

ese

––

50(

ase

C8)

it pr

tim

Tim

n B 17

(

ase

CC)

Tim

n A 1

(

ase

it pr

tim

r Tim

rfl

53(

ase

+D4

)

Tim

r 1

rfl

(

ase

Tim

r 2

rfl

w21

55(

ase

Tim

rfl

w22

56(

ase

l int

ace

ece

r–

(

ase

+E4

)

ece

r f

ll 2

58(

ase

mit

mpt

–

ese

––

60(

ase

l int

ace

h.1 R

ece

r–

(

ase

+F4

)

ece

r f

ll 2

(

ase

mit

mpt

–

ese

––

(

ase

00)

n27

35 41 65(Base+104) Clock timer Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal

1-minuet, 1-hour or specified time count up –

–

ese

––

68(

ase

+11

rt inp

t int

pt 4 E

dge

(

r f

llin

r l

(

r L

)

69(

ase

+114

)

rt inp

t int

dge

(

r f

llin

r l

(

r L

)

ase

+11

rt inp

t int

dge

(

r f

llin

r l

(

r L

)

↓

47 71

(

ase

+11

rt inp

t int

pt 7 E

dge

(

r f

llin

r l

(

r L

)

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-2 EPSON S1C33209/221/222 FUNCTION PART

Contents of table

"Hex No." indicates an interrupt number in hexadecimal value.

"Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an

offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table

by defa ult is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR

For details about the trap table contents including exception factors, etc., refer to the "S1C33000 Core CPU

Manual".

" Interrupt system (Peripheral circuit)" indicates that interrupt levels can be programmed for each peripheral

circuit written.

"Interrupt factor" indicates the factor of the interrupt occurring in each interrupt system.

"IDMA Ch." indicates that an interrupt factor which has a numeric value in this column can start up the

intelligent DMA (IDMA) to transfer data when an interrupt factor occurs. The numeric value indicates the

IDMA's channel number. Interrupt factors that do not have a numeric value here cannot start up the IDMA.

"Priority" indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt

level. If two or more interrupt factors occur simultaneously, interrupt requests are accepted in order of highest

priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the

priorities of interrupt factors in the same interrupt system are fixed in the order that they are written here.

Maskable interrupt generating conditions

A maskable interrupt to the CPU occurs when all of the conditions described below are met.

• The interrupt enable register for the interrupt factor that has occurred is set to "1".

• The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to "1".

• The interrupt factor that has occurred has a higher priority level than the value that is set in the PSR's

Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt

system.)

• No other trap factor having higher priority, such as NMI, has occurred.

• The interrupt factor does not invoke IDMA (the IDMA request bit is set to "0").

When an interrupt factor occurs, the corresponding interrupt factor flag is set to "1" and the flag remains set

until it is reset in the software program. Therefore, in no cases can the generated interrupt factor be

inadvertently cleared even if the above conditions are not met when the interrupt factor has occurred. The

interrupt will occur when the above conditions are met.

However, when the interrupt factor invokes IDMA, the interrupt factor is reset if the following condition is

met.

• The IDMA transfer counter is not "0".

• Interrupts are disabled in the IDMA control information even if the transfer counter is "0".

If two or more maskable interrupt factors occur simultaneously, the interrupt factor that has the highest priority

is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept pending

until the above conditions are met.

The PSR and interrupt control register will be detailed later.

For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this

manual.

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-3

Interrupt Factors and Intelligent DMA

Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors occurs,

IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated afte r

IDMA is completed. (The interrupt request can be disabled by a program.)

IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation".

Nonmaskable Interrupt (NMI)

The nonmaska ble interrupt (NMI) can be generated by pulling the #NMI pin low or using the internal watchdog timer.

The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes.

This interrupt is prioritized over other int errupts and is unconditionally accepted by the CPU.

However, since this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked in

hardware until a write to the SP is completed after an initial reset.

Interrupt Processing by the CPU

The CPU keeps sampling interrupt requests every cycle. When the CPU accepts an interrupt request, it enters trap

processing after completing execution of the instruction that was being executed.

The following lists the contents executed in trap processing.

(1) The PSR and the current program counter (PC) value are saved to the stack.

(2) The IE bit of the PSR is reset to "0" (following maskable interrupts are disabled).

(3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level

changed).

(4) The vector of the generated interrupt factor is loaded into the PC, thus executing the interrupt processing

routine.

Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts

can also be handled by setting the IE bit to "1" in the interrupt processing routine. In this case, since the IL has been

changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is accepted.

When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status

before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one

that was being executed when the interrupt occurred.

Clearing Standby Mode by Interrupts

The standby modes (HALT and SLEEP) are cleared by an NMI or a maskable interrupt.

All maskable interrupts can be used to clear HALT mode. However, if the bus clock has stopped in HALT2 mode, a

DMA interrupt cannot be used.

In SLEEP mode, since the high-speed (OSC3) oscillation circuit is deactivated, interrupts from the peripheral circuits

that operate with the OSC3 clock cannot be used.

Interrupts that can be used to clear basic HALT mode:NMI and all maskable interrupts

Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts)

Interrupts that can be used to clear SLEEP mode: NMI, input port interrupts, and clock timer interrupts

Clearing of the standby modes is accomplished by an interrupt request to the CPU. Therefore, this requires that the

PSR be set in such a way that the requested interrupt will be accepted, and that the interrupt enable register for the

interrupt factor be set to accept the interrupt.

When standby mode is cleared and the CPU has accepted the interrupt, it returns to the instruction next to the halt or

slp instruction after executing the interrupt processing routine.

Note: If the interrupt factor used to restart from the standby mode has been set to invoke the IDMA, the

IDMA is started up by that interrupt.

In the case of SLEEP mode, the high-speed (OSC3) oscillation circuit also starts operating.

If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side,

no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt

request is generated.

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-4 EPSON S1C33209/221/222 FUNCTION PART

Trap Table

The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register.

TTBR0 (D[9:0]) / TTBR low-order register (0x48134): Trap table base address [9:0] (fixed at "0")

TTBR1 (D[F:A]) / TTBR low-order register (0x48134): Trap table base address [15:10]

TTBR2 (D[B:0]) / TTBR high-order register (0x48136):Trap table base address [27:16]

TTBR3 (D[F:C]) / TTBR high-order register (0x48136):Trap table base address [31:28] (fixed at "0")

After an initial reset, the TTBR register is set to 0x0C00000.

Therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the

above address.

TTBR0 and TTBR3 are read-only bits which are fixed at "0". Therefore, the trap table starting address always begins

with a 1KB boundary address.

The TTBR register is normally write-protected to prevent them from being inadvertently rewritten. To remove this

write protection function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D [byte]), is

provided. A write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write

to the most significant byte of the TTBR register (0x48137). Consequently, a write to the TTBR register needs to

begin with the low-order half-word first. However, since an occurrence of NMI or the like between writes of the

low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in

words.

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-5

Control of Maskable Interrupts

Structure of the Interrupt Controller

The interrupt controller is configured as shown in Figure 5.1.

CPU interrupt

priority judgment

(with interrupt level)

Interrupt vector

generator

Interrupt factor flag

Interrupt enable

IDMA request

IDMA enable

Interrupt request

Interrupt level

Interrupt vector

Key input x

HSDMA x

K5x (#DMAREQx) input Software trigger

16-bit timer x

8-bit timer x

Serial I/F x

A/D

Port input x

CPU

ITC

IDMA request

priority judgment

(without interrupt level)

IDMA channel number

generator

Interrupt factor flag

Interrupt enable

IDMA request

IDMA enable

IDMA request

IDMA channel number

IDMA completion

Reset A

Reset B

Reset C

Ch.x HSDMA request

HSDMA trigger

selection circuit

IDMA

HSDMA

Ch.x

Interrupt

factors

Figure 5.1 Configuration of Interrupt Controller

The following sections explain the funct ions of the registers used to control interrupts.

Processor Status Register (PSR)

The PSR is a special register incorporated in the core CPU and contains control bits to enable or disable an interrupt

request to the CPU.

Interrupt Enable (IE) bit: PSR[4]

This bit is used to enable or disable an interrupt request to the CPU. When this bit is set to "1", the CPU is

enabled to accept a maskable interrupt request. When this bit is reset to "0", no maskable interrupt request is

accepted by the CPU.

When the CPU accepts an interrupt request (or some other trap occurs), it saves the PSR to the stack and resets

the IE bit to "0". Consequently, no maskable interrupt request occurring thereafter will be accepted unless the

IE bit is set to "1" in software program or the interrupt (trap) processing routine is terminated by the reti

instruction.

The IE bit is initialized to "0" (interrupts disabled) by an initial reset.

Interrupt Level (IL): PSR[11:8]

The IL bits disable the interrupts whose priorities are below the set interrupt level. For example, if the interrupt

level set in the IL is 3, the interrupts whose priorities are set below 3 in the interrupt priority register (described

later) are not accepted by the CPU even if the IE bit is set to "1". The IL an d the interrupt priority register

together allow you to control the interrupt priorities in each interrupt system. For details about the interrupt

levels, refer to " Interrupt Priority Register and Interrupt Levels".

When the CPU accepts a maskable interrupt request, it saves the PSR to the stack and sets the IL to the

accepted interrupt's priority level. Therefore, even when the IE bit is set to "1" in the interrupt processing

routine, no interrupts whose priority levels are equal or below that of the interrupt currently being processed are

accepted unless the IL is rewritten.

The IL is restored to its previous status when the interrupt processing routine is terminated by the reti

instruction.

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-6 EPSON S1C33209/221/222 FUNCTION PART

The IL is rewritten for only maskable interrupts and not for any other traps (except a reset).

The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset.

Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15.

However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each

interrupt system can only be set for up to 8.

Interrupt Factor Flag and Interrupt Enable Register

An interrupt factor flag and an interrupt enable register are provided for each maskable interrupt factor.

Interrupt factor flag

The interrupt factor flag is set to "1" when the corresponding interrupt factor occurs. Reading the flag enables

you to determine what caused an i nterrupt, making it unnecessary to resort to the CPU's trap processing. The

interrupt factor flag is reset only by writing data in software. Note that the method by which this flag is reset

can be selected from the software application using either of the two methods described below. This selection is

accomplished using RSTONLY (D0) / Interrupt factor flag reset method select register (0x4029F).

• Reset-only method (default)

This method is selected (RSTONLY = "1") when initially reset.

With this method, the interrupt factor flag is reset by writing "1". Although multiple interrupt factor flags are

located at the same address of the interrupt control register, the interrupt factor flags for which "0" has been

written can be neither set nor reset. Therefore, this method ensures that only a specific factor flag is reset.

However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an interrupt factor flag

that has been set to "1" is reset by writing.

In this method, no interrupt factor flag can be set in the software application.

• Read/write method

This method is selected by writing "0" to RSTONLY.

When this method is used, interrupt factor flags can be read and written as for other registers. Therefore, the flag

is reset by writing "0" and set by writing "1". In this case, all factor flags for which "0" has been written are

reset. Even in a read-modify-write operation, an interrupt factor can occur between the read and the write, so

be careful when using this method.

Since interrupt factor flags are not initialized by an initial reset, be sure to reset them before enabling

interrupts.

Note: Even when a maskable interrupt request is accepted by the CPU and control branches off to the

interrupt processing routine, the interrupt factor flag is not reset. Consequently, if control is

returned from the interrupt processing routine by the reti instruction without resetting the interrupt

factor flag in a program, the same interrupt factor occurs again.

For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this

manual.

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-7

Interrupt enable register

This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this

interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding

interrupt factor occurs.

Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset by

writing "0" and set by writing "1". By reading this register, its setup status can be checked at any time.

Settings of the interrupt enable register do not affect the operation of interrupt factor flags, so when an interrupt

factor occurs the interrupt factor flag is set to "1" even if the corresponding interrupt enable bit is set to "0".

When initially reset, the interrupt enable register is set to "0" (interrupts are disabled).

In cases when IDMA is started up by occurrence of an interrupt factor or when clearing standby mode (HALT

or SLEEP mode) too, the corresponding interrupt enable bit must be set to "1".

The interrupt controller outputs an interrupt request to the CPU when the following conditions are met:

• An interrupt factor has occurred and the interrupt factor flag is set to "1".

• The bit of the interrupt enable register for the interrupt factor that has occurred is set to "1" (interrupt enable).

• The bit of the IDMA request register for the interrupt factor that has occurred is set to "0" (interrupt request).

If two or more interrupt factors occur simultaneously, the interrupt factor that has the highest priority is allowed to

signal an interrupt request to the CPU. (See the following section.)

When these conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with the

setup content (interrupt level) of the interrupt priority reg ister for the generated interrupt system and its vector

number.

These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt

enable register is set to "0" (interrupts are disabled) or until some o ther interrupt factor of higher priority occurs.

They are not cleared if the CPU simply accepts the interrupt request.

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-8 EPSON S1C33209/221/222 FUNCTION PART

Interrupt Priority Register and Interrupt Levels

The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a

given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table 5.1 can be modified

according to system requirements by this setting.

The value set in this register is used by the interrupt controller and the CPU as described below.

Roles of the interrupt priority register in the interrupt controller

If two or more interrupt factors that have been enabled by the interrupt enable register occur simultaneously,

the interrupt factor in the interrupt system whose interrupt priority register contains the greatest value is

allowed by the interrupt controller to signal an interrupt request to the CPU.

If an interrupt factor occurs in two or more interrupt systems having the same value, the interrupt priority is

resolved according to the default priorities in Table 5.1 . Interrupt factors in the same interrupt system also have

their priorities resolved according to the o rder in Table 5.1 .

Other interrupt factors are kept pending until all interrupts of higher priority are accepted by the CPU.

When outputting an interrupt request signal to the CPU, the interrupt controller outputs the content of the

interrupt priority register to the CPU along with it.

If another interrupt factor of higher priority occurs during outputting an interrupt request signal, the interrupt

controller changes the vector number and interrupt level to those of the new interrupt factor before they are

output to the CPU. The first interrupt request is left pending.

Roles of the interrupt priority register in CPU processing

The CPU compares the content of the interrupt priority register received from the inte rrupt controller with the

interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request.

IE bit = "1" & IL < interrupt priority register: the interrupt request is accepted

IE bit = "1" & IL > interrupt pr iority register: the interrupt request is rejected

Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL.

For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the interrupt

priority register are 4 or more will be accepted.

When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL.

As a result, the interrupt requests below that interrupt level can no longer be accepted.

If the interrupt priority register for an interrupt is set to "0", the interrupt is disabled. However, invoking

IDMA by means of an interrupt factor works fine.

Notes: • As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to

15. However, since the interrupt priority register in the C33 Core Block consists of three bits,

interrupt levels in each interrupt system can only be set for up to 8.

• Multiple interrupts can also be handled by rewriting the interrupt level to the IL in the interrupt

processing routine. However, if the interrupt level of the IL is set below the current level and the

IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has

occurred, the same interrupt may occur again.

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-9

IDMA Invocation

The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the

intelligent DMA (IDMA).

IDMA request register

The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA

request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs.

When the IDMA request bit is set to "0", the corresponding interrupt factor does not invoke IDMA and a

normal interrupt processing will be performed. The IDMA request register is set to "0" by an initial reset.

The method by which this register is set can be selected from the software application using either of the two

methods described below. This selection is accomplished using IDMAONLY (D1) / Flag set/reset method

select register (0x4029F).

•Set-only method (default)

This method is selected (IDMAONLY = "1") when initiall y reset.

With this method, an IDMA request bit is set by writing "1". Although multiple IDMA request bits are located

in the IDMA request register, the IDMA request bits for which "0" has been written can be neither set nor reset.

Therefore, this method ensures that only a specific IDMA request bit is set.

However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit

that has been set to "1" is not reset by writing.

•Read/write method

This method is se lected by writing "0" to IDMAONLY.

When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the

IDMA request bit is reset by writing "0" and set by writing "1". In this case, all IDMA request bits for which

"0" has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by the

hardware between the read and the write, so be careful when using this method.

IDMA enable register

To perform IDMA transfer using an interrupt factor, the corresponding bit of the IDMA enable register must be

set to "1". If this bit is set to "0", the interrupt factor cannot invoke the IDMA channel. The IDMA enable

The IDMA enable register allows selection of a set method (set-only method or Read/write method) similar to

the IDMA request register. This selection is accomplished using DENONLY (D2) / Flag set/reset method

select register (0x4029F). See the above explanation for the set method.

Invoking IDMA

Before IDMA can be invoked by the occurrence of an interrupt factor, the corresponding bits of the IDMA

request and IDMA enable registers must be set to "1". Then when an interrupt factor occurs, the interrupt

request to the CPU is made pending and t he corresponding IDMA channel is invoked. The DMA transfer is

performed according to the control information of that IDMA channel. The interrupt level set by the interrupt

priority register of the ITC does not affect the IDMA invocation. The IDMA request can be accepted even if the

interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when

generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled

using the int errupt level set by the interrupt priority register.

An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to

disable interrupts. It is also necessary that the control information for the IDMA channel has been set.

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-10 EPSON S1C33209/221/222 FUNCTION PART

Interrupt after IDMA transfer

To generate an interrupt after completion of IDMA transfer:

The interrupt request that has been kept pending can be generated after completion of the DMA transfer.

In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to the

interrupt controller and the PSR register settings.

However, if the transfer counter set for the selected IDMA channel does not reach the terminal count of 0 after

the number of transfers s et have been performed, the interrupt factor flag is reset and no interrupt request is

generated. The transfer counter is decremented by 1 for each transfer performed.

If the transfer counter is decremented to 0 when DINTEN is set to "1", the interrupt factor flag is not reset and

the IDMA request bit is cleared to "0". An interrupt request is generated if other interrupt conditions are met.

The IDMA request bit must be set up again in order for IDMA to be invoked when an interrupt factor occurs

next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after

resetting the interrupt factor flag.

Figure 5.2 shows the hardware sequence when DINTEN is set to "1".

3 2 1 0

IDMA trigger (interrupt factor flag)

Transfer counter

Data transfer

Reset A signal

(reset interrupt factor flag)

Reset B signal

(reset IDMA request bit)

IDMA request bit

Interrupt request

Figure 5.2 Sequence when DINTEN = "1"

To disable an interrupt after completion of IDMA transfer:

If an interrupt has been disabled in the IDMA control information (DINTEN = "0"), the interrupt is not

generated since the inte rrupt factor flag is reset when the transfer counter becomes 0.

In this case, the IDMA request bit remains set to "1" without being cleared. However, the IDMA enable bit is

cleared, so the following IDMA request by the same interrupt factor will be disabl ed.

Figure 5.3 shows the hardware sequence when DINTEN is set to "0".

3 2 1 0

IDMA trigger (interrupt factor flag)

Transfer counter

Data transfer

Reset A signal

(reset interrupt factor flag)

Reset B signal

(reset IDMA request bit)

Reset C signal

(reset IDMA enable bit)

IDMA request bit

IDMA enable bit

"1"

Figure 5.3 Sequence when DINTEN = "0"

For details on IDMA, refer to "IDMA (Intelligent DMA)".

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-11

HSDMA Invocation

Some interrupt factors can invoke high-speed DMAs (HSDMA).

HSDMA trigger set-up register

The DMA block contains four channel of HSDMA circuit. Each channel allows selection of an interrupt factor

as the trigger. The HSDMA trigger set-up registers are used for this selection.

HSDMA Ch.0: HSD0S[3:0] (D[3:0])/HSDMA Ch.0/1 trigger set-up register (0x40298)

HSDMA Ch.1: HSD1S[3:0] (D[7:4])/HSDMA Ch.0/1 trigger set-up register (0x40298)

HSDMA Ch.2: HSD2S[3:0] (D[3:0])/HSDMA Ch.2/3 trigger set-up register (0x40299)

HSDMA Ch.3: HSD3S[3:0] (D[7:4])/HSDMA Ch.2/3 trigger set-up register (0x40299)

Table 5.2 shows the setting value and the corresponding trigger factor.

Table 5.2 HSDMA Trigger Factor

Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor

0000 Software trigger Software trigger Software trigger Software trigger

0001 K50 port input (falling edge) K51 port input (falling edge) K53 port input (falling edge) K54 port input (falling edge)

0010 K50 port input (rising edge) K51 port input (rising edge) K53 port input (rising edge) K54 port input (rising edge)

0011 Port 0 input Port 1 input Port 2 input Port 3 input

0100 Port 4 input Port 5 input Port 6 input Port 7 input

0101 8-bit timer 0 underflow 8-bit timer 1 underflow 8-bit timer 2 underflow 8-bit timer 3 underflow

0110 16-bit timer 0 compare B 16-bit timer 1 compare B 16-bit timer 2 compare B 16-bit timer 3 compare B

0111 16-bit timer 0 compare A 16-bit timer 1 compare A 16-bit timer 2 compare A 16-bit timer 3 compare A

1000 16-bit timer 4 compare B 16-bit timer 5 compare B 16-bit timer 4 compare B 16-bit timer 5 compare B

1001 16-bit timer 4 compare A 16-bit timer 5 compare A 16-bit timer 4 compare A 16-bit timer 5 compare A

1010 Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full

1011 Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer em pty Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty

1100 A/D conversion completion A/D conversion completion A/D conversion completion A/D conversion completion

Invoking HSDMA

By selecting an interrupt factor with the HSDMA trigger set-up register, the HSDMA channel is invoked when

the selected interrupt factor occurs. The interrupt control bits (interrupt factor flag, interrupt enable register,

IDMA request register, interrupt priority register) do not affect this invocation.

Since HSDMA does not reset the interrupt factor flag, an interrupt will occur when the DMA transfer is

completed if the interrupt is enabled by ITC.

Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on

the H SDMA side by setting the control register for HSDMA transfer.

For details about HSDMA, refer to "HSDMA (High-Speed DMA)".

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-12 EPSON S1C33209/221/222 FUNCTION PART

I/O Memory of Interrupt Controller

Table 5.3 shows the control bits of the interrupt control ler.

Table 5.3 Control Bits of Interrupt Controller

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

0 to 7

–

PP1L2

PP1L1

PP1L0

–

PP0L2

PP0L1

PP0L0

reserved

Port input 1 interrupt level

reserved

Port input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040260

(B)

Port input 0/1

interrupt

priority register

–

0 to 7

–

PP3L2

PP3L1

PP3L0

–

PP2L2

PP2L1

PP2L0

reserved

Port input 3 interrupt level

reserved

Port input 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040261

(B)

Port input 2/3

interrupt

priority register

–

0 to 7

–

PK1L2

PK1L1

PK1L0

–

PK0L2

PK0L1

PK0L0

reserved

Key input 1 interrupt level

reserved

Key input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040262

(B)

Key input

interrupt

priority register

–

0 to 7

–

PHSD1L2

PHSD1L1

PHSD1L0

–

PHSD0L2

PHSD0L1

PHSD0L0

reserved

High-speed DMA Ch.1

interrupt level

reserved

High-speed DMA Ch.0

interrupt level

–

R/W

–

R/W

0 when being read.

0040263

(B)

High-speed

DMA Ch.0/1

interrupt

priority register

–

0 to 7

–

PHSD3L2

PHSD3L1

PHSD3L0

–

PHSD2L2

PHSD2L1

PHSD2L0

reserved

High-speed DMA Ch.3

interrupt level

reserved

High-speed DMA Ch.2

interrupt level

–

R/W

–

R/W

0 when being read.

0040264

(B)

High-speed

DMA Ch.2/3

interrupt

priority register

–

0 to 7

–

PDM2

PDM1

PDM0

D7–3

reserved

IDMA interrupt level –

–

R/W 0 when being read.0040265

(B)

IDMA interrupt

priority register

–

0 to 7

–

P16T12

P16T11

P16T10

–

P16T02

P16T01

P16T00

reserved

16-bit timer 1 interrupt level

reserved

16-bit timer 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040266

(B)

16-bit timer 0/1

interrupt

priority register

–

0 to 7

–

P16T32

P16T31

P16T30

–

P16T22

P16T21

P16T20

reserved

16-bit timer 3 interrupt level

reserved

16-bit timer 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040267

(B)

16-bit timer 2/3

interrupt

priority register

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-13

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

0 to 7

–

P16T52

P16T51

P16T50

–

P16T42

P16T41

P16T40

reserved

16-bit timer 5 interrupt level

reserved

16-bit timer 4 interrupt level

–

R/W

–

R/W

0 when being read.

0040268

(B)

16-bit timer 4/5

interrupt

priority register

–

0 to 7

–

PSI002

PSI001

PSI000

–

P8TM2

P8TM1

P8TM0

reserved

Serial interface Ch.0

interrupt level

reserved

8-bit timer 0–3 interrupt level

–

R/W

–

R/W

0 when being read.

0040269

(B)

8-bit timer,

serial I/F Ch.0

interrupt

priority register

–

0 to 7

–

PAD2

PAD1

PAD0

–

PSI012

PSI011

PSI010

reserved

A/D converter interrupt level

reserved

Serial interface Ch.1

interrupt level

–

R/W

–

R/W

0 when being read.

004026A

(B)

Serial I/F Ch.1,

A/D interrupt

priority register

–

0 to 7

–

PCTM2

PCTM1

PCTM0

D7–3

reserved

Clock timer interrupt level –

–

R/W Writing 1 not allowed.004026B

(B)

Clock timer

interrupt

priority register

–

0 to 7

–

PP5L2

PP5L1

PP5L0

–

PP4L2

PP4L1

PP4L0

reserved

Port input 5 interrupt level

reserved

Port input 4 interrupt level

–

R/W

–

R/W

0 when being read.

004026C

(B)

Port input 4/5

interrupt

priority register

–

0 to 7

–

PP7L2

PP7L1

PP7L0

–

PP6L2

PP6L1

PP6L0

reserved

Port input 7 interrupt level

reserved

Port input 6 interrupt level

–

R/W

–

R/W

0 when being read.

004026D

(B)

Port input 6/7

interrupt

priority register

–

EK1

EK0

EP3

EP2

EP1

EP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

– –

–

R/W

0 when being read.0040270

(B) 1 Enabled 0 Disabled

Key input,

port input 0–3

interrupt

enable register

–

EIDMA

EHDM3

EHDM2

EHDM1

EHDM0

D7–5

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

– –

–

R/W

0 when being read.0040271

(B) 1 Enabled 0 Disabled

DMA interrupt

enable register

E16TC1

E16TU1

–

E16TC0

E16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040272

(B) 1 Enabled 0 Disabled

16-bit timer 0/1

interrupt

enable register –

1 Enabled 0 Disabled

–

E16TC3

E16TU3

–

E16TC2

E16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040273

(B) 1 Enabled 0 Disabled

16-bit timer 2/3

interrupt

enable register –

1 Enabled 0 Disabled

–

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-14 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

E16TC5

E16TU5

–

E16TC4

E16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040274

(B) 1 Enabled 0 Disabled

16-bit timer 4/5

interrupt

enable register –

1 Enabled 0 Disabled

–

E8TU3

E8TU2

E8TU1

E8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040275

(B) 1 Enabled 0 Disabled

8-bit timer

interrupt

enable register

–

ESTX1

ESRX1

ESERR1

ESTX0

ESRX0

ESERR0

D7–6

reserved

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

SIF Ch.1 receive error

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

SIF Ch.0 receive error

– –

–

R/W

0 when being read.0040276

(B) 1 Enabled 0 Disabled

Serial I/F

interrupt

enable register

–

EP7

EP6

EP5

EP4

ECTM

EADE

D7–6

reserved

Port input 7

Port input 6

Port input 5

Port input 4

Clock timer

A/D converter

– –

–

R/W

0 when being read.0040277

(B) 1 Enabled 0 Disabled

Port input 4–7,

clock timer,

A/D interrupt

enable register

–

FK1

FK0

FP3

FP2

FP1

FP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

– –

–

R/W

0 when being read.0040280

(B) 1 Factor is

generated 0 No factor is

generated

Key input,

port input 0–3

interrupt factor

flag register

–

FIDMA

FHDM3

FHDM2

FHDM1

FHDM0

D7–5

reserved

IDMA

High-speed DMA Ch.3

High-speed DMA Ch.2

High-speed DMA Ch.1

High-speed DMA Ch.0

– –

–

R/W

0 when being read.0040281

(B)

DMA interrupt

factor flag

generated 0 No factor is

generated

F16TC1

F16TU1

–

F16TC0

F16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040282

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 0/1

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC3

F16TU3

–

F16TC2

F16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040283

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 2/3

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC5

F16TU5

–

F16TC4

F16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040284

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 4/5

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F8TU3

F8TU2

F8TU1

F8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040285

(B) 1 Factor is

generated 0 No factor is

generated

8-bit timer

interrupt factor

flag register

–

FSTX1

FSRX1

FSERR1

FSTX0

FSRX0

FSERR0

D7–6

reserved

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

SIF Ch.1 receive error

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

SIF Ch.0 receive error

– –

–

R/W

0 when being read.0040286

(B) 1 Factor is

generated 0 No factor is

generated

Serial I/F

interrupt factor

flag register

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-15

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

FP7

FP6

FP5

FP4

FCTM

FADE

D7–6

reserved

Port input 7

Port input 6

Port input 5

Port input 4

Clock timer

A/D converter

– –

–

R/W

0 when being read.0040287

(B) 1 Factor is

generated 0 No factor is

generated

Port input 4–7,

clock timer, A/D

interrupt factor

flag register

R16TC0

R16TU0

RHDM1

RHDM0

RP3

RP2

RP1

RP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040290

(B) 1 IDMA

request 0 Interrupt

request

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA request

R16TC4

R16TU4

R16TC3

R16TU3

R16TC2

R16TU2

R16TC1

R16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040291

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 1–4

IDMA request

RSTX0

RSRX0

R8TU3

R8TU2

R8TU1

R8TU0

R16TC5

R16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040292

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA request

RP7

RP6

RP5

RP4

–

RADE

RSTX1

RSRX1

Port input 7

Port input 6

Port input 5

Port input 4

reserved

A/D converter

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

–

R/W

–

R/W

0 when being read.

0040293

(B) 1 IDMA

request 0 Interrupt

request

1 IDMA

request 0 Interrupt

request

–

Serial I/F Ch.1,

A/D,

port input 4–7

IDMA request

DE16TC0

DE16TU0

DEHDM1

DEHDM0

DEP3

DEP2

DEP1

DEP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040294

(B) 1 IDMA

enabled 0 IDMA

disabled

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA enable

DE16TC4

DE16TU4

DE16TC3

DE16TU3

DE16TC2

DE16TU2

DE16TC1

DE16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040295

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 1–4

IDMA enable

DESTX0

DESRX0

DE8TU3

DE8TU2

DE8TU1

DE8TU0

DE16TC5

DE16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040296

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA enable

DEP7

DEP6

DEP5

DEP4

–

DEADE

DESTX1

DESRX1

Port input 7

Port input 6

Port input 5

Port input 4

reserved

A/D converter

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

–

R/W

–

R/W

0 when being read.

0040297

(B) 1 IDMA

enabled 0 IDMA

disabled

1 IDMA

enabled 0 IDMA

disabled

–

Serial I/F Ch.1,

A/D,

port input 4–7

IDMA enable

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-16 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

HSD1S3

HSD1S2

HSD1S1

HSD1S0

HSD0S3

HSD0S2

HSD0S1

HSD0S0

High-speed DMA Ch.1

trigger set-up

High-speed DMA Ch.0

trigger set-up

R/W

0040298

(B) 0

Software trigger

K51 input (falling edge)

K51 input (rising edge)

Port 1 input

Port 5 input

8-bit timer Ch.1 underflow

16-bit timer Ch.1 compare B

16-bit timer Ch.1 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

Software trigger

K50 input (falling edge)

K50 input (rising edge)

Port 0 input

Port 4 input

8-bit timer Ch.0 underflow

16-bit timer Ch.0 compare B

16-bit timer Ch.0 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.0/1

trigger set-up

HSD3S3

HSD3S2

HSD3S1

HSD3S0

HSD2S3

HSD2S2

HSD2S1

HSD2S0

High-speed DMA Ch.3

trigger set-up

High-speed DMA Ch.2

trigger set-up

R/W

0040299

(B) 0

Software trigger

K54 input (falling edge)

K54 input (rising edge)

Port 3 input

Port 7 input

8-bit timer Ch.3 underflow

16-bit timer Ch.3 compare B

16-bit timer Ch.3 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

Software trigger

K53 input (falling edge)

K53 input (rising edge)

Port 2 input

Port 6 input

8-bit timer Ch.2 underflow

16-bit timer Ch.2 compare B

16-bit timer Ch.2 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.2/3

trigger set-up

–

DENONLY

IDMAONLY

RSTONLY

D7–3

reserved

IDMA enable register set method

selection

IDMA request register set method

selection

Interrupt factor flag reset method

selection

– –

–

R/W

004029F

(B)

Flag set/reset

method select

1 Set only 0 RD/WR

1 Reset only 0 RD/WR

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-17

NameAddressRegister name Bit Function Setting Init. R/W Remarks

T8CH5S0

SIO3TS0

T8CH4S0

SIO3RS0

SIO2TS0

SIO3ES0

SIO2RS0

SIO2ES0

8-bit timer 5 underflow

SIO Ch.3 transmit buffer empty

8-bit timer 4 underflow

SIO Ch.3 receive buffer full

SIO Ch.2 transmit buffer empty

SIO Ch.3 receive error

SIO Ch.2 receive buffer full

SIO Ch.2 receive error

R/W

00402C5Interrupt factor

FP function

switching

1 SIO Ch.3

TXD Emp. 0 FP6

1 SIO Ch.3

RXD Full 0 FP4

1 SIO Ch.2

TXD Emp. 0 FP3

1 SIO Ch.3

RXD Err. 0 FP2

1 SIO Ch.2

RXD Full 0 FP1

1 SIO Ch.2

RXD Err. 0 FP0

1 T8 Ch.5 UF 0 FP7

1 T8 Ch.4 UF 0 FP5

T8CH5S1

T8CH4S1

SIO3ES1

SIO2ES1

SIO3TS1

SIO3RS1

SIO2TS1

SIO2RS1

8-bit timer 5 underflow

8-bit timer 4 underflow

SIO Ch.3 receive error

SIO Ch.2 receive error

SIO Ch.3 transmit buffer empty

SIO Ch.3 receive buffer full

SIO Ch.2 transmit buffer empty

SIO Ch.2 receive buffer full

R/W

00402CBInterrupt factor

TM16 function

switching

RXD Err. 0 TM16 Ch.3

comp.A

1 SIO Ch.2

RXD Err. 0 TM16 Ch.3

comp.B

1 SIO Ch.3

TXD Emp. 0 TM16 Ch.4

comp.A

1 SIO Ch.3

RXD Full 0 TM16 Ch.4

comp.B

1 SIO Ch.2

TXD Emp. 0 TM16 Ch.5

comp.A

1 SIO Ch.2

RXD Full 0 TM16 Ch.5

comp.B

1 T8 Ch.5 UF 0 TM16 Ch.2

comp.A

1 T8 Ch.4 UF 0 TM16 Ch.2

comp.B

TBRP7

TBRP6

TBRP5

TBRP4

TBRP3

TBRP2

TBRP1

TBRP0

TTBR register write protect 0

W Undefined in read.004812D

(B) Writing 01011001(0x59)

removes the TTBR (0x48134)

write protection.

Writing other data sets the

write protection.

TTBR write

protect register

TTBR15

TTBR14

TTBR13

TTBR12

TTBR11

TTBR10

TTBR09

TTBR08

TTBR07

TTBR06

TTBR05

TTBR04

TTBR03

TTBR02

TTBR01

TTBR00

Trap table base address [15:10]

Trap table base address [9:0] Fixed at 0

R/W

R0 when being read.

Writing 1 not allowed.

0048134

(HW)

TTBR low-

order register

TTBR33

TTBR32

TTBR31

TTBR30

TTBR2B

TTBR2A

TTBR29

TTBR28

TTBR27

TTBR26

TTBR25

TTBR24

TTBR23

TTBR22

TTBR21

TTBR20

Trap table base address [31:28]

Trap table base address [27:16]

Fixed at 0

0x0C0

R/W

0 when being read.

Writing 1 not allowed.

0048136

(HW)

TTBR high-

order register

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-18 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

A10IR2

A10IR1

A10IR0

–

A10BW1

A10BW0

A10DRA

A9DRA

A10SZ

A10DF1

A10DF0

–

A10WT2

A10WT1

A10WT0

reserved

Area 10 internal ROM size

selection

reserved

Areas 10–9

burst ROM

burst read cycle wait control

Area 10 burst ROM selection

Area 9 burst ROM selection

Areas 10–9 device size selection

Areas 10–9

output disable delay time

reserved

Areas 10–9 wait control

–

1 Used 0 Not used

1 8 bits 0 16 bits

–

R/W

–

R/W

–

R/W

0 when being read.

0048126

(HW)

A10BW[1:0] Wait cycles

A10DF[1:0] Number of cycles

3.5

2.5

1.5

0.5

A10IR[2:0] ROM size

2MB

1MB

512KB

256KB

128KB

64KB

32KB

16KB

A10WT[2:0] Wait cycles

Areas 10–9

set-up register

The following collectively explains the basic functions of each control register/bit. For details about individual

interrupt systems and the contents classified by an interrupt factor, refer to the descriptions of the peripheral circuits

in this manual.

Pxxx2–Pxxx0: Interrupt priority register

Set the priority levels of each interrupt system in the range of 0 to 7.

If this register is set below the IL value of the PSR, no interrupt is generated. The value of this register when initially

reset is indeterminate.

Exxx: Interrupt enable register

Enable or disable interrupt generation to the CPU.

Write "1": Interrupt enabled

Write "0": Interrupt disabled

Read: Valid

Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are

set to "0".

For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

When initially reset, this register is set to "0" (interrupt disabled).

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-19

Fxxx: Interrupt factor flag

Indicate the status of interrupt factors generated.

When read

Read "1": Interrupt factor generated

Read "0": No interrupt factor generated

When written using the reset-only method (default)

Write "1": Factor flag is reset

Write "0": Invalid

When written using the read/write method

Write "1": Factor flag is set

Write "0": Factor flag is reset

The interrupt factor flag is set to "1" when an interrupt factor occurs in each peripheral circuit.

If the following conditions are met at this time, an interrupt is generated to the CPU:

1. The corresponding bit of the interrupt enable register is set to "1".

2. No other interrupt request of higher priority has occurred.

3. The IE bit of the PSR is set to "1" (interrupt enabled).

4. T he corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).

When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt

request to the CPU is generated for t he interrupt factor that has occurred. If interrupts are enabled at the setting of

IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.

The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and

interrupt priority registers are set.

In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and the

PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the

IE bit to "1" or executing the reti instruction).

The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set

up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same

interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only

method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse

these two conditions.

The interrupt factor flag becomes indeterminate when initially reset, so be sure to reset the flag in the software

application.

Rxxx: IDMA request register

Specify whether or not to invoke IDMA when an interrupt factor occurs.

When using the set-only method (default)

Write "1": IDMA request

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA request

Write "0": Interrupt request

Read: Valid

If a bit of this register is set to "1", IDMA is invoked when the corresponding interrupt factor occurs and the

programmed data transfer is performed. If the register bit is set to "0", regular interrupt processing is performed,

without ever invoking IDMA.

For details about IDMA, refer to "IDMA (Intelligent DMA)".

If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion

of DMA transfer, the IDMA request register is res et to "0" and an interrupt request for the interrupt factor that

enabled IDMA invoking is generated.

After an initial reset, this register is set to "0" (Interrupt is requested).

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-20 EPSON S1C33209/221/222 FUNCTION PART

DExxx: IDMA enable register

Enable or disable the IDMA request.

When using the set-only method (default)

Write "1": IDMA enabled

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA enabled

Write "0": IDMA disabled

Read: Valid

If a bit of this register is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0",

the IDMA request is disabled.

After an initial reset, this register is set to "0" (IDMA is disabled).

RSTONLY: Interrupt factor flag reset method selection

(D0) / Flag set/reset method select register (0x4029F)

Select the method for resetting the interrupt factor flag.

Write "1": Reset-only method

Write "0": Read/write method

Read: Valid

With the reset-only method, the interrupt factor flag is reset by writing "1".

The interrupt factor flags for which "0" has been written can neither be set nor reset. Therefore, this method ensures

that only a specific factor flag is reset. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot),

note that an interrupt factor flag that has been set to "1" is reset by writing. This method cannot be used to set any

interrupt factor flag in the software application.

The read/write method is selected by writing "0" to RSTONLY. When this method is selected, interrupt factor flags

can be read and written as for other registers. Therefore, the flag is reset by writing "0" and set by writing "1". In this

case all factor flags for which "0" has been written are reset. Even in a read-modify-write operation, an interrupt

factor can occur between read and write instructions, so be careful when using this method.

After an initial reset, RSTONLY is set to "1" (reset-only method).

IDMAONLY: IDMA request register set method selection

(D1) / Flag set/reset method select register (0x4029F)

Select the method for setting the IDMA request registers.

Write "1": Set-only method

Write "0": Read/write method

Read: Valid

With the set-only method, IDMA request bits are set by writing "1".

The IDMA request bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures

that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or

bnot), note that an IDMA request bit that has been set to "1" is not reset by writing.

The read/write method is selected by writing "0" to IDMAONLY. When this method is selected, IDMA request bits

can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing "0" and set by

writing "1". In this case all IDMA request bits for which "0" has been written are reset. Even in a read-modify-write

operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful when using

this method.

After an initial reset, IDMAONLY is set to "1" (set-only method).

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-21

DENONLY: IDMA enable register set method selection

(D2) / Flag set/reset method select register (0x4029F)

Select the method for setting the IDMA enable registers.

Write "1": Set-only method

Write "0": Read/write method

Read: Valid

With the set-only method, IDMA enable bits are set by writing "1".

The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures

that only a specific IDMA enable bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or

bnot), note that an IDMA enable bit that has been set to "1" is not reset by writing.

The read/write method is selected by writing "0" to DENONLY. When this method is s elected, IDMA enable bits

can be read and written as for other registers. Therefore, the IDMA enable bit is reset by writing "0" and set by

writing "1". In this case all IDMA enable bits for which "0" has been written are reset. Even in a read-modify-write

operation, an interrupt enable bit can be reset by the hardware between the read and the write, so be careful when

using this method.

After an initial reset, DENONLY is set to "1" (set-only method).

SIO2ES0: SIO Ch.2 receive error/FP0 interrupt factor switching

(D0) /Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.2 receive error

Write "0": FP0 input

Read: Valid

Set to "1" to use the SIO Ch.2 receive error interrupt.

Set to "0" to use the FP0 input interrupt.

At power-on, this bit is set to "0".

SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching

(D1) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.2 receive-buffer full

Write "0": FP1 input

Read: Valid

Set to "1" to use the SIO Ch.2 receive-buffer full interrupt.

Set to "0" to use the FP1 input interrupt.

At power-on, this bit is set to "0".

SIO3ES0: SIO Ch.3 receive error/FP2 interrupt factor switching

(D2) /Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.3 receive error

Write "0": FP2 input

Read: Valid

Set to "1" to use the SIO Ch.3 receive error interrupt.

Set to "0" to use the FP2 input interrupt.

At power-on, this bit is set to "0".

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-22 EPSON S1C33209/221/222 FUNCTION PART

SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching

(D3) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.2 transmit-buffer empty

Write "0": FP3 input

Read: Valid

Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.

Set to "0" to use the FP3 input interrupt.

At power-on, this bit is set to "0".

SIO3RS0: SIO Ch.3 receive-buffer full/FP4 interrupt factor switching

(D4) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.3 receive-buffer full

Write "0": FP4 input

Read: Valid

Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.

Set to "0" to use the FP4 input interrupt.

At power-on, this bit is set to "0".

T8CH4S0: 8-bit timer 4 underflow/FP5 interrupt factor switching

(D5) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": 8-bit timer 4 u nderflow

Write "0": FP5 input

Read: Valid

Set to "1" to use the 8-bit timer 4 underflow interrupt.

Set to "0" to use the FP5 input interrupt.

At power-on, this bit is set to "0".

SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching

(D6) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": SIO Ch.3 transmit-buffer empty

Write "0": FP6 input

Read: Valid

Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.

Set to "0" to use the FP6 input interrupt.

At power-on, this bit is set to "0".

T8CH5S0: 8-bit timer 5 underflow/FP7 interrupt factor switching

(D7) / Interrupt factor FP function switching register (0x402C5)

Switches the interrupt factor.

Write "1": 8-bit timer 5 u nderflow

Write "0": FP7 input

Read: Valid

Set to "1" to use the 8-bit timer 5 underflow interrupt.

Set to "0" to use the FP7 input interrupt.

At power-on, this bit is set to "0".

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-23

SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt facto r switching

(D0) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.2 receive-buffer full

Write "0": TM16 Ch.5 compare B

Read: Valid

Set to "1" to use the SIO Ch.2 receive-buffer full inter rupt.

Set to "0" to use the TM16 Ch.5 compare B interrupt.

At power-on, this bit is set to "0".

SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.5 compare A interrupt factor switching

(D1) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.2 transmit-buffer empty

Write "0": TM16 Ch.5 compare A

Read: Valid

Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.

Set to "0" to use the TM16 Ch.5 compare A interrupt.

At power-on, this bit is set to "0".

SIO3RS1: SIO Ch.3 receive-buffer full/TM16 Ch.4 compare B interrupt factor switching

(D2) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.3 receive-buffer full

Write "0": TM16 Ch.4 compare B

Read: Valid

Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.

Set to "0" to use the TM16 Ch.4 compare B interrupt.

At power-on, this bit is set to "0".

SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching

(D3) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.3 transmit-buffer empty

Write "0": TM16 Ch.4 compare A

Read: Valid

Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.

Set to "0" to use the TM16 Ch.4 compare A interrupt.

At power-on, this bit is set to "0".

SIO2ES1: SIO Ch.2 receive error/TM16 Ch.3 compare B interrupt factor switching

(D4) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.2 receive error

Write "0": TM16 Ch.3 compare B

Read: Valid

Set to "1" to use the SIO Ch.2 receive error interrupt.

Set to "0" to use the TM16 Ch.3 compare B interrupt.

At power-on, this bit is set to "0".

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-24 EPSON S1C33209/221/222 FUNCTION PART

SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching

(D5) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": SIO Ch.3 receive error

Write "0": TM16 Ch.3 compare A

Read: Valid

Set to "1" to use the SIO Ch.3 receive error interrupt.

Set to "0" to use the TM16 Ch.3 compare A interrupt.

At power-on, this bit is set to "0".

T8CH4S1: 8-bit timer 4 underflow/TM16 Ch.2 compare B interrupt factor switching

(D6) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": 8-bit timer 4 underflow

Write "0": TM16 Ch.2 compare B

Read: Valid

Set to "1" to use the 8-bit timer 4 underflow interrupt.

Set to "0" to use the TM16 Ch.2 compare B interrupt.

At power-on, this bit is set to "0".

T8CH5S1: 8-bit timer 5 underflow/TM16 Ch.2 compare A interrupt factor switching

(D7) / Interrupt factor TM16 function switching register (0x402CB)

Switches the interrupt factor.

Write "1": 8-bit timer 5 underflow

Write "0": TM16 Ch.2 compare A

Read: Valid

Set to "1" to use the 8-bit timer 5 underflow interrupt.

Set to "0" to use the TM16 Ch.2 compare A interrupt.

At power-on, this bit is set to "0".

TBRP7–TBRP0: TTBR register write protection ([D[7:0]) / TTBR write-protect register (0x4812D)

Remove write protection for the TTBR register.

Write 0x59: Write protection is removed

Write not the above: No operation (write protected)

Read: Valid

Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written

to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected.

After an initial reset, TBRP is set to "0x0" (write protected).

II CORE BLOCK: ITC ( Interrupt Controller)

S1C33209/221/222 FUNCTION PART EPSON B-II-5-25

TTBR09–TTBR00: Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW])

TTBR15–TTBR10: Trap table base address [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW])

TTBR2B–TTBR20:Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW])

TTBR33–TTBR30: Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW])

Set the starting address of the trap table.

TTBR0 and TTBR3 are read-only registers and are fixed to "0". For this reason, the trap table starting address always

begins with a 1KB boundary address.

The TTBR registers normally are write-protected to prevent them from being inadvertently rewritten. To remove

this write protect function, another register, TBRP (D[F:8]) / TTBR write-protect register (0x4 812D), is provided. A

write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write to the most

significant byte of the TTBR register (0x48137). Consequently, writes to the TTBR register need to begin with the

low-order half-word first. However, since occurrences of NMI and the like between writes of the low-order and

high-order half-words cause malfunctions, it is recommended that the register be written in words.

After an initial reset, the TTBR register is set to 0x0C00000.

Programming Notes

(1) In cases when an interrupt factor that is used for restarting from the standby mode has been set to invoke IDMA,

IDMA is started up by the interrupt at its occurrence. In SLEEP mode, the high-speed (OSC3) oscillation

circuit also starts operating. However, if an interrupt to be generated upon completion of IDMA is disabled at

the setting of IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the

next interrupt request is generated.

(2) As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However,

since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each interrupt

system can only be set for up to 8.

(3) When the reset-only method is used to reset the interrupt factor flag (by writing "1"), if a read-modify-write

instruction (e.g., bset, bclr, or bnot) is executed, the other interrupt factor flags at the same address that have

been set to "1" are reset by a write. This requires caution. In cases when the read/write method is used to reset

the interrupt factor flag (by writing "0"), all factor flags for which "0" has been written are reset. When a

read-modify-write operation is performed, an interrupt factor may occur between reads and writes, so be

careful when using this method.

The same applies to the set-only method and read/write method for the IDMA request and IDMA enable

registers.

(4) After an initial reset, the interrupt factor flags and interrupt priority registers all become indeterminate. To

prevent unwanted interrupts or IDMA requests from being generated inadvertently, be sure to reset these flags

and registers in the software application.

(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be

sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti

instruction.

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-26 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

II CORE BLOCK: CLG (Clock Generator)

S1C33209/221/222 FUNCTION PART EPSON B-II-6-1

II-6 CLG (Clock Generator)

This section describes the method for controlling the system clock.

Configuration of Clock Generator

The C33 Core Block has a built-in clock generator that consists of a high-speed oscillation circuit (OSC3) and a PLL.

The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g.,

DMA, serial interface, programmable timer, and A/D converter).

Furthermore, the clock generator can input a sub clock, such as low-speed (OSC1, 32.768 kHz, Typ.) clock generated

by the Peripheral Block, for the clock timer and for operating the CPU at a low clock speed in order to reduce current

consumption.

Note: When the Peripheral Block including the low-speed (OSC1) oscillation circuit is used, the source

clocks for the CPU and the peripheral circuits (e.g., DMA, serial interface, programmable timer, and

A/D converter) can be selected between the OSC3 clock and the OSC1 clock independently. For

details, refer to "Setting and Switching Over the CPU Operating Clock" in this section and

"Prescaler" and "Low-Speed (OSC1) oscillation circuit" of the Peripheral Block.

Figure 6.1 shows the configuration of the clock generator.

High-speed (OSC3)

oscillation circuit Clock

switch

CLKCHG

To CPU

SLEEP

OSC3

OSC4

HALT, HALT2,

SLEEP

SOSC3

Oscillation ON/OFF CLKDT[1:0]

Divider

1/1 to 1/8

To BCU and DMA

HALT2, SLEEP

To peripheral circuits

and clock timer

SLEEP

PLL

PLLC

PLLS0

PLLS1

Low-speed (OSC1)

oscillation circuit

SOSC1

Oscillation ON/OFF

OSC1

OSC2

CLG

Peripheral Block

Figure 6.1 Configuration of Clock Generator

After an initial reset, the output (OSC3 clock) of the high-speed (OSC3) oscillation circuit is set for the CPU

operating clock.

When the low-speed (OSC1) oscillation circuit is used, the CPU operating clock can be switched to the output

(OSC1 clock) of the low-speed (OSC1) oscillation circuit in a program. Furthermore, each o scillation circuit can be

stopped in a program.

If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation of

the CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition,

when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current

consumption (no internal units except for the clock timer need to be operated).

II CORE BLOCK: CLG (Clock Generator)

B-II-6-2 EPSON S1C33209/221/222 FUNCTION PART

I/O Pins of Clock Generator

Table 6.1 lists the I/O pins of the clock generator.

Table 6.1 I/O Pins of Clock Generator

Pin name I/O Function

OSC3 I High-speed (OSC3) oscillation input pin

Crystal/ceramic oscillation or external clock input

OSC4 O High-speed (OSC3) oscillation output pin

Crystal/ceramic oscillation (open when external clock is used)

PLLC – Capasitor connecting pin for PLL

PLLS[1:0] I PLL set-up pins

PLLS1 PLLS0 fin (f OSC3) fout (f PSCIN)

1 1 10–30MHz 20–60MHz ∗1

10–25MHz 20–50MHz ∗2

0 1 10–15MHz 40–60MHz ∗1

10–12.5MHz 40–50MHz ∗2

0 0 PLL is not used L ∗3

∗1: ROM-less model with 3.3 V ± 0.3 V operating voltage

∗2: ROM built-in model, or 3.0 V ± 0.3 V operating voltage

∗3: When the PLL is not used, the OSC3 clock is used directly.

High-Speed (OSC3) Oscillation Circuit

The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g.,

DMA, serial interface, programmable timer, and A/D converter).

This circuit can be a crystal or a ceramic oscillation circuit. Optionally an external clock source can be used.

Figure 6.2 shows the structure of the high-speed (OSC3) oscillatio n circuit.

OSC4

OSC3

Oscillation circuit

control signal

SLEEP status

Oscillation circuit

control signal

SLEEP status

X'tal2

Ceramic

fOSC3

OSC4

OSC3

External

clock

N.C.

fOSC3

(

)

stal/ceramic oscillation circuit

(

)

External clock input

Figure 6.2 High-Speed (OSC3) Oscillation Circuit

When using a crystal or a ceramic oscillation for this circuit, connect a crystal (X'tal2) or ceramic (Ceramic) resonator

and feedback resistor (Rf) between the OSC3 and OSC4 pins, and two capacitors (CG2, CD2) between the OSC3 pin

and VSS and the OSC4 pin and VSS, respectively.

When an external clock is used, leave the OSC4 pin open and input a square-wave clock to the OSC3 pin.

The range of osci llation frequencies is 10 MHz to 33 MHz. This frequency range also applies when an external clock

is used.

Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See

Table 6.2.

For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical

Characteristics".

II CORE BLOCK: CLG (Clock Generator)

S1C33209/221/222 FUNCTION PART EPSON B-II-6-3

PLL

The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0]

pins acco rding to the OSC3 clock frequency.

Table 6.2 Setting the PLLS[1:0] Pins

PLLS1 PLLS0 Mode fin (OSC3 clock) fout Notes

1 1 x2 10 to 30 MHz

10 to 25 MHz 20 to 60 MHz

20 to 50 MHz No ROM, and 3.3 V ± 0.3 V

ROM inco rporated, or 3.3 V ± 0.3 V

0 1 x4 10 to 15 MHz

10 to 12.5 MHz 40 to 60 MHz

20 to 50 MHz No ROM, and 3.3 V ± 0.3 V

ROM incorporated, or 3.3 V ± 0.3 V

0 0 PLL

Not used – Not used

Figure 6.3 shows a basic external connection diagram for the PLL pins.

VSS

PLLS1

PLLS0

PLLC

PLL

100 pF

10 pF

4.7 kΩ

VDD

Figure 6.3 External Connection Diagram

Note: When the PLL is not used, the OSC3 oscillation output is used as the source clock. In this case, the

oscillation frequency range is 10 MHz to 33 MHz. Furthermore, leave the PLLC pin open.

Controlling Oscillation

The high-speed (OSC3) oscillation circuit can be turned on or off using SOSC3 (D1) / Power control register

(0x40180).

The oscillation circuit is turned off by writing "0" to SOSC3 and turned back on again by writing "1". SOSC3 is set

to "1" at initial reset, so the oscillation circuit is turned on.

Notes: • When the high-speed (OSC3) oscillation circuit is used as the clock source for the CPU

operating clock, it cannot be turned off. In this case, writing "0" to SOSC3 is ignored. Note also

that writing to SOSC3 is allowed only when the power-control register protection flag is set to

"0b10010110".

• Immediately after the oscillation circuit is turned on, a certain period of time is required for

oscillation to stabilize (for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device

from operating erratically, do not use the clock until its oscillation has stabilized.

The high-speed (OSC3) oscillation ci rcuit turns off when the CPU is set in SLEEP mode.

Setting and Switching Over the CPU Operating Clock

Setting the CPU operating clock frequency

When operating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in

four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for this switchover.

Table 6.3 Setting of CPU Operating Clock

CLKDT1 CLKDT0 Division ratio

1 1 fout/8

1 0 fout/4

0 1 fout/2

0 0 fout/1

fout: PLL output

II CORE BLOCK: CLG (Clock Generator)

B-II-6-4 EPSON S1C33209/221/222 FUNCTION PART

The clock thus set becomes the system clock, which is used as the CPU operating clock and the bus clock.

At initial reset, the division ratio is set to fout/1, so the CPU is operated directly by the PLL output clock.

Since the device's current consumption can be decreased by reducing the CPU operating speed, switch over the

operating frequency as necessary.

This setting is effective only for the high-speed (OSC3) clock, and has no effect when the low-speed (OSC1)

clock is used as the system clock.

Note: Writing to CLKDT[1:0] is effective only when the power-control register protection flag is set to

"0b10010110".

Switching over the CPU operating clock

Note: The CPU operating clock can be switched from OSC3 to OSC1 only when the low-speed (OSC1)

oscillation circuit in the Peripheral Block is used.

After an initial reset, the CPU starts operating using the OSC3 clock. All internal peripheral circuits also

operate.

In cases in which some peripheral circuits (e.g., programmabl e timer, serial interface, and A/D converter) that

are clocked by the OSC3 clock do not need to be operate and the CPU can process its jobs at a low clock speed,

the CPU operating clock can be switched to the OSC1 clock, thereby reducing current consumption. Use

CLKCHG (D2) / Power control register (0x40180) to switch over the operating clock.

Procedure for switching over from the OSC3 clock to the OSC1 clock

1. Turn on the low-speed (OSC1) oscillation circuit (by writing "1" to SOSC1).

2. Wait until the OSC1 oscillation stabilizes (three seconds or more).

3. Change the CPU operating clock (by writing "0" to CLKCHG).

4. Turn off the high-speed (OSC3) oscillation circuit (by writing "0" to SOSC3).

∗ Steps 1 and 2 are required only when the low-speed (OSC1) oscillation circuit is inactive.

Notes: • Use separate instructions to switch from OSC3 to OSC1 and turn the OSC3 oscillation off. If

these operations are processed simultaneously using one instruction, the CPU may operate

erratically.

• Make sure the operation of the peripheral circuits, such as the programmable timer, A/D

converter, and serial interface, which are clocked by the OSC3 oscillation circuit, is terminated

before the OSC3 oscillation is turned off in order to prevent them from operating erratically.

Procedure for switching over from the OSC1 clock to the OSC3 clock

1. Turn on the high-speed (OSC3) oscillation circuit (by writing "1" to SOSC3).

2. Wait until the OSC3 oscillation stabilizes (10 ms or more for a 3.3-V crystal resonator).

3. Switch over the CPU operating clock (by writing "1" to CLKCHG).

Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on

and the power-control register protection flag is set to "0b10010110".

Power-Control Register Protection Flag

The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU

operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary

writing.

To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control

protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control register

(0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is written to.

Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is written to.

The flag CLGP[7:0] does n ot affect the readout from the power-control register (0x40180).

II CORE BLOCK: CLG (Clock Generator)

S1C33209/221/222 FUNCTION PART EPSON B-II-6-5

Operation in Standby Mode

In HALT mode, which is entered by executing the halt instruction, the high-speed (OSC3) and low-speed (OSC1)

oscillation circuits both retain their status before HALT mode is entered. Under normal conditions, therefore, there is

no need to control the oscillation circuits before entering or after exiting HALT mode.

The high-speed (OSC3) oscillation circuit stops operating after SLEEP mode is entered, which is done by executing

the slp (sleep) instruction. If the high-speed (OSC3) oscillation circuit was operating before SLEEP mode was

entered, it automatically starts oscillating again after SLEEP mode is exited.

In addition, if the CPU was operating using the OSC3 clock before SLEEP mode was entered, the CPU starts

operating using the OSC3 clock again even after SLEEP mode is exited. The high-speed (OSC3) oscillation circuit

requires 10 ms max. (when using a 3.3-V crystal resonator) for its oscillation to stabilize after oscillation starts. To

prevent the CPU from operating erratically upon restart during this period, the C33 Core Block is designed to allow

the OSC3 clock supply to the CPU to be disabled in the hardware after SLEEP mode is exited. Use 8T1ON (D2) /

Clock option register (0x40190) to select this function. Use 8-bit programmable timer 1 to set the waitting time

before clock supply is started.

The processing procedure and the operations to be performed when this function is used are as follows:

1. Disable the 8-bit programmable timer 1 interrupt.

2. Preset the initial count to 8-bit programmable timer 1.

Set a value that will provide an ample stabilization waiting time. It is also necessary to set the input clock for 8-

bit programmable timer 1 using the prescaler.

3. Enable the interrupt used to exit SLEEP mode.

Before enabling the interrupt, be sure to reset the interrupt factor flag.

4. Write "0" to 8T1ON (turn on the function for waiting until the oscillation stabilizes after exiting SLEEP mode).

5. Activate 8-bit programmable timer 1 to start counting.

6. Enter SLEEP mode using the slp instruction.

SLEEP mode

7. Exit SLEEP mode using an NMI, input port, or timer interrupt.

8. The high-speed (OSC3) oscillation circui t starts oscillating when SLEEP mode is exited. 8-bit programmable

timer 1 also is made to start counting using the OSC3 clock.

9. 8-bit programmable timer 1 underflows.

The operating clock supply to the CPU is begun by the underflow signal, so that the CPU restarts.

For details on how to control the 8-bit programmable timer, prescaler, and interrupts, refer to the description of each

item in this manual.

Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective

only when SLEEP mode is exited.

Writing to 8T1ON is effective only when the power-control register protection flag is set to

"0b10010110".

II CORE BLOCK: CLG (Clock Generator)

B-II-6-6 EPSON S1C33209/221/222 FUNCTION PART

I/O Memory of Clock Generator

Table 6.4 lists the control bits of clock generator.

Table 6.4 Control Bits of Clock Generator

NameAddressRegister name Bit Function Setting Init. R/W Remarks

CLKDT1

CLKDT0

PSCON

–

CLKCHG

SOSC3

SOSC1

D4–3

System clock division ratio

selection

Prescaler On/Off control

reserved

CPU operating clock switch

High-speed (OSC3) oscillation On/Off

Low-speed (OSC1) oscillation On/Off

1 On 0 Off

1 OSC3 0 OSC1

1 On 0 Off

R/W

–

R/W

Writing 1 not allowed.

0040180

(B) 1

CLKDT[1:0] Division ratio

1/8

1/4

1/2

1/1

–

Power control

–

HLT2OP

8T1ON

–

PF1ON

D7–4

–

HALT clock option

OSC3-stabilize waiting function

reserved

OSC1 external output control

–

R/W

–

R/W

0 when being read.

Do not write 1.

0040190

(B) 1 On 0 Off

1 Off 0 On

1 On 0 Off

–

Clock option

Writing 10010110 (0x96)

removes the write protection of

the power control register

(0x40180) and the clock option

Writing another value set the

write protection.

CLGP7

CLGP6

CLGP5

CLGP4

CLGP3

CLGP2

CLGP1

CLGP0

Power control register protect flag 0

R/W004019E

(B)

Power control

protect register

SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180)

Turns the low-speed (OSC1) oscillation on or off.

Write " 1": OSC1 oscillation turned on

Write "0": OSC1 oscillation turned off

Read: Valid

The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by

writing "1".

Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been

restarted, at least this length of time must pass before the OSC1 clock can be used.

Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating

using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off.

At initial reset, SOSC1 is set to "1" (OSC1 oscillation turned on).

Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral

Block is used.

SOSC3: High-speed (OSC3) oscillation control (D1) / Power control register (0x40180)

Turns the high-speed (OSC3) oscillation on or off.

Write "1": OSC3 oscillation turned on

Write "0": OSC3 oscillation turned off

Read: Valid

The oscillation of the high-speed (OSC3) oscillation circuit is stopped by writing "0" to SOSC3, and started again by

writing "1".

Since a duration of maximum 10 ms (for a 3.3-V crystal resonator) is required for oscillation to stabilize after the

oscillation has been restarted, at least this length of time must pass before the OSC3 clock can be used.

Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating

using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off.

At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on).

II CORE BLOCK: CLG (Clock Generator)

S1C33209/221/222 FUNCTION PART EPSON B-II-6-7

CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180)

Selects the CPU operating clock.

Write "1": OSC3 clock

Write "0": OSC1 clock

Read: Valid

The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by

writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and low-

speed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set to

"0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize

before switching over the CPU operating clock.

At initial reset, CLKCHG is set to "1" (OSC3 clock).

Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral

Block is used.

CLKDT1–CLKDT0: CPU operating frequency selection (D[7:6]) / Power control register (0x40180)

Select the CPU operating clock frequency.

Table 6.5 Setting of CPU Operating Clock

CLKDT1 CLKDT0 Division ratio

1 1 fout/8

1 0 fout/4

0 1 fout/2

0 0 fout/1

fout: PLL output

This setting is effective when the CPU is operated using the high-speed (OSC3) clock and has no effect on the low-

speed (OSC1) clock. Writing to CLKDT[1:0] is allowed only when CLGP[7:0] is set to "0b10010110".

At initial res et, CLKDT is set to "0" (fout/1).

8T1ON: High-speed (OSC3) oscillation waiting function (D2) / Clock option register (0x40190)

Sets the function for waiting until the high-speed (OSC3) oscillation stabilizes after SLEEP mode is exited.

Write "1": Off

Write "0": On

Read: Valid

After SLEEP mode is exited, the high-speed (OSC3) oscillation waiting function is effective by writing "1" to

8T1ON. For this function to be used, the waiting time must be set in 8-bit programmable timer 1 to allow it to start

counting before entering SLEEP mode. After SLEEP mode is exited, the OSC3 clock is not supplied to the CPU until

8-bit programmable timer 1 underflows. This function will not work when 8T1ON is set to "0".

The high-speed (OSC3) oscillation waiting funct ion is effective only when SLEEP mode is exited.

Writing to 8T1ON is effective only when CLGP[7:0] is set to "0b10010110".

When writing to 8T1ON, always be sure to write "0" to the reserved bits at address 0x40190.

At initial reset, 8T1ON is set to "0" (Off).

HLT2OP: HALT clock option (D3) / Clock option register (0x40190)

Select a HALT condition (basic mode or HALT2 mode).

Write "1": HALT2 mode

Write "0": Basic mode

Read: Valid

When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When

"0" is written, the CPU will enter basic mode.

Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110".

At initial reset, HLT2OP is set to "0" (basic mode).

II CORE BLOCK: CLG (Clock Generator)

B-II-6-8 EPSON S1C33209/221/222 FUNCTION PART

The following shows the operating status in H ALT mode (basic mode and HALT2 mode) and SLEEP mode.

Table 6.6 Operating Status in Standby Mode

Standby mode Operating status Reactivating factor

HALT mode Basic mode • The CPU clock is stopped. (CPU stop status)

• BCU clock is supplied. (BCU run status)

• DMA clock is not stopped. (DMA run status)

• Clocks for the peripheral circuits maintain the

status before entering HALT mode. (run or

stop)

• The high-speed oscillation circuit maintains

the status before entering HALT mode.

• The low-speed oscillation circuit maintains the

status before entering HALT mode.

• Reset, NMI

• Enabled (not masked) interrupt

factors

HALT2 mode • The CPU clock is stopped. (CPU stop status)

• BCU clock is stopped. (BCU stop status)

• DMA clock is stopped. (DMA stop status)

• Clocks for the peripheral circuits maintain the

status before entering HALT mode. (run or

stop)

• The high-speed oscillation circuit maintains

the status before entering HALT mode.

• The low-speed oscillation circuit maintains the

status before entering HALT mode.

In HALT2 mode, the A/D, SIO, and

timers (8-bit and 16-bit) continue

operating without stopping, but since

the synchronization clock is

stopped, these circuits cannot be

restarted.

A restart is possible only in the case

of:

• Interrupt from input pin

• Interrupt from clock timer

• NMI

• Reset

SLEEP mode • The CPU clock is stopped. (CPU stop status)

• BCU clock is stopped. (BCU stop status)

• Clocks for the peripheral circuits are stopped.

• The high-speed oscillation circuit is stopped.

• The low-speed oscillation circuit maintains the

status before entering SLEEP mode.

• Reset, NMI

• Enabled (not masked) input port

interrupt factors

• Clock timer interrupt when the

low-speed oscillation circuit is

being operated

CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)

These bits remove the protection against writing to addresses 0x40180 and 0x40190.

Write "0b10010110": Write protection removed

Write other than the above: No operation (write-protected)

Read: Valid

Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against

writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to

"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.

At initial reset, CLGP is set to "0b00000000" (write-protected).

II CORE BLOCK: CLG (Clock Generator)

S1C33209/221/222 FUNCTION PART EPSON B-II-6-9

Programming Notes

(1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required for

oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from

operating erratically, do not use the clock until its oscillation has stabilized.

In particular, if the CPU is set in SLEEP mode during operation using the OSC3 clock, the high-speed (OSC3)

oscillation circuit is turned off during in SLEEP mode and starts oscillating again after SLEEP mode is ex ited.

To prevent the CPU from operating erratically at restart due to an unstable OSC3 clock, set a sufficient

stabilization waiting time in 8-bit programmable timer 1 to turn on the oscillation stabilization waiting function

after SLEEP mode is exited bef ore entering SLEEP mode.

(2) The oscillation circuit used for the CPU operating clock cannot be turned off.

(3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are on.

Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU

operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these

two operations are processed simultaneously using one instruction, the CPU may operate erratically.

(4) If the high-speed (OSC3) oscillation circuit is turned off, all peripheral circuits operated using the OSC3 clock

will be inactive.

(5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3)

oscillation circuit off. This helps reduce current consumption.

(6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,

not HALT2 mode, with a setting of 0 in clock option register HLT20 (0x0040190 bit 3), that operation will be an

unpredictable erroneous operation.

If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,

erroneous operation will result. Ensure that DMA is not invoked in HALT mode.

In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.

(7) In the SLEEP state, the oscillation circuit clock stops, and in the HALT2 mode, the clock supply to peripheral

circuits is stopped.

When restarting from this state, interrupt input from a port can be used as a trigger, but functionally, this

interrupt input operates as level input. Therefore, a level input based restart is performed even in the case of set

edge input.

Restart operation is as follows for rising and falling edges.

In case of rising edge interrupt setting: Restarted by high level input.

In case of falling edge interrupt setting:Restarted by low level input.

In normal operation, a restart begins following the elapse of a given time after execution of the SLP instruction,

but when restart by a falling (rising) level (edge) is set, the operation is as follows.

• The restart is effected immediately after execution of the SLP instruction.

• As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge, and

therefore the SLP state is entered only momentarily, and the restart is effected immediately afterwards.

There was a synchronization circuit using a clock signal in the port input circuit, and as the clock is stopped in

the SLEEP state or HALT2 state, the configuration provided for this synchronization circuit to be bypassed

when restarting. Therefore, a restart is effected when the input level from a port is active by level.

Consequently, the system design should assume that a restart by means of port input from the SLEEP state or

HALT2 state is performed by level.

II CORE BLOCK: CLG (Clock Generator)

B-II-6-10 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

II CORE BLOCK: DBG (Debug Unit)

S1C33209/221/222 FUNCTION PART EPSON B-II-7-1

II-7 DBG (Debug Unit)

Debug Circuit

The C33 Core Block has a built-in debug circuit.

This functional block is provided to simply realize an advanced software development environment.

Note: The debug circuit does not work during normal operation. To construct a software development

environment using the debug circuit, the S5U1C33000H (In-Circuit Debugger for S1C33 Family) is

separately required.

I/O Pins of Debug Circuit

Six pins used to exclusively connect the S5U1C33000H (In-Circuit Debugger for S1C33 Family) are reserved for the

debug circuit. The I/O voltage level of these pins is 3.3 V.

Table 7.1 lists the I/O pins of the debug circuit.

Table 7.1 I/O Pins of Debug Circuit

Pin name I/O Pull-up Initial status Voltage level Function

DCLK O – 1 3.3 V Clock output for debugging

DST2 O – 0 3.3 V Status output 2 for debugging

DST1 O – 1 3.3 V Status output 1 for debugging

DST0 O – 1 3.3 V Status output 0 for debugging

DPCO O – 1 3.3 V PC output for debugging

DSIO I/O With pull-up 1 (Input) 3.3 V Serial I/O for debugging

The DCLK, DST[2:0] and DPCO outputs are extended functions of the I/O port pins P14, P1[2:0] and P13,

respectively. At initial reset, these pins are set as debug signal outputs.

If the debug circuit is not used, these pins can be used for I/O ports or the redefined peripheral circuits by writing "0"

to CFEX[1:0] (D[1:0]) / Port function extension register (0x402DF). Refer to "I/O Ports (P Ports)" for the pin

functions.

Note: When these pins are set as debug signal outputs, only the S5U1C33000H (In-Circuit Debugger for

S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not

connected. For connecting the S5U1C33000H, refer to the "S1C33 Family In-Circuit Debugger

Manual".

Furthermore, the pin status is fixed as shown in the above table after a user reset.

II CORE BLOCK: DBG (Debug Unit)

B-II-7-2 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

S1C33209/221/222 FUNCTION PART

III PERIPHERAL BLOCK

III PERIPHERAL BLOCK: INTRODUCTION

S1C33209/221/222 FUNCTION PART EPSON B-III-1-1

III-1 INTRODUCTION

The C33 peripheral block consists of a prescaler, six 8-bit programmable timer channels, six 16-bit programmable

timer channels including watchdog timer and event counter functions, four serial interface channels, input and I/O

ports, a low-speed (OSC1) oscillation circuit, and a clock timer.

CORE_PAD

Pads

C33_SBUS

Internal RAM

(Area 0)

C33 Core Block

C33 Internal Memory BlockC33 DMA Block

PERI_PAD

Pads

C33_PERI

(Prescaler, 8-bit timer, 16-bit timer,

Clock timer, Serial interface, Ports)

C33 Peripheral BlockC33 Analog Block

C33_CORE

(CPU, BCU, ITC, CLG, DBG)

C33_ADC

(A/D converter)

C33_DMA

(IDMA, HSDMA) Internal ROM

(Area 10)

Figure 1.1 Peripheral Block

Note: Internal ROM is not provided in the S1C33209.

III PERIPHERAL BLOCK: INTRODUCTION

B-III-1-2 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

III PERIPHERAL BLOCK: PRESCALER

S1C33209/221/222 FUNCTION PART EPSON B-III-2-1

III-2 PRESCALER

Configuration of Prescaler

The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the internal

peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock

control circuit to control the clock supply to each peripheral circuit is also included.

The following are the p eripheral circuits that use the output clock:

• 16-bit programmable timers 5 to 0 (and watchdog timer)

• 8-bit programmable timers 5 to 0 (and serial interface)

• A/D converter

Figure 2.1 shows the configuration of the prescaler.

For details on control of each peripheral circuit, refer to each corresponding section in this manual.

Division ratio

select register Selector

Selector 1/21/1 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096

Control register

PSCON

OSC3 or

PLL output clock

OSC1 clock

16-bit programmable timer 5–0

Prescaler

output control

8-bit programmable timer 3–0

A/D converter

Figure 2.1 Configuration of Prescaler and Clock Control Circuit

Source Clock

The source clock for the prescaler can be selected using PSCDT0 (D0) / Prescaer clock select register (0x40181).

When PSCDT0 = "0", the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is

selected.

When PSCDT0 = "1", the OSC1 clock (typ. 32 kHz) is selected.

At initial reset, the OSC3/PLL output clock is selected.

Note: For the prescaler clock, the clock source same as the CPU operating clock must be selected.

For details on how to control the oscillation circuit and CPU operating clock, refer to "CLG (Clock Generator)".

At initial reset, the OSC3 clock is selected.

The source clock is supplied to the prescaler by writing "1" to PSCON (D5) / Power control register (0x40180). At

initial reset, PSCON is set to "1", so the prescaler is in an operating state. If all of said peripheral circuits can be

turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current consumption.

III PERIPHERAL BLOCK: PRESCALER

B-III-2-2 EPSON S1C33209/221/222 FUNCTION PART

Selecting Division Ratio and Output Control for Prescaler

The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral

circuit described above, allowing each peripheral circuit to be controlled.

The prescaler's division ratio can be selected from among eight ratios set for each peripheral circuit through the use of

the division ratio selection bits. The divided clock is output to the corresponding peripheral circuit by writing "1" to

the clock control bit.

Table 2.1 Control Bits of the Clock Control Registers

Peripheral circuit Division ratio selection bit Clock control bit

16-bit programmable timer 0 P16TS0[2:0] (D[2:0]/0x40147)∗1 P16TON0 (D3/0x40147)

16-bit programmable timer 1 P16TS1[2:0] (D[2:0]/0x40148)∗1 P16TON1 (D3/0x40148)

16-bit programmable timer 2 P16TS2[2:0] (D[2:0]/0x40149)∗1 P16TON2 (D3/0x40149)

16-bit programmable timer 3 P16TS3[2:0] (D[2:0]/0x4014A)∗1 P16TON3 (D3/0x4014A)

16-bit programmable timer 4 P16TS4[2:0] (D[2:0]/0x4014B)∗1 P16TON4 (D3/0x4014B)

16-bit programmable timer 5 P16TS5[2:0] (D[2:0]/0x4014C)∗1 P16TON5 (D3/0x4014C)

8-bit programmable timer 0 P8TS0[2:0] (D[2:0]/0x4014D)∗2 P8TON0 (D3/0x4014D)

8-bit programmable timer 1 P8TS1[2:0] (D[6:4]/0x4014D)∗3 P8TON1 (D7/0x4014D)

8-bit programmable timer 2 P8TS2[2:0] (D[2:0]/0x4014E) ∗4 P8TON2 (D3/0x4014E)

8-bit programmable timer 3 P8TS3[2:0] (D[6:4]/0x4014E) ∗2 P8TON3 (D7/0x4014E)

8-bit programmable timer 4 P8TS4[2:0] (D[2:0]/0x40145)∗4 P8TON4 (D3/0x40145)

8-bit programmable timer 5 P8TS5[2:0] (D[6:4]/0x40145)∗2 P8TON5 (D7/0x40145)

A/D converter PSAD[2:0] (D[2:0]/0x4014F)∗2 PSONAD (D3/0x4014F)

∗1 to ∗4: See Table 2.2.

Table 2.2 Division Ratio

Bit setting 76543210

∗1θ/4096 θ/1024 θ/256 θ/64 θ/16 θ/4 θ/2 θ/1

∗2θ/256 θ/128 θ/64 θ/32 θ/16 θ/8 θ/4 θ/2

∗3θ/4096 θ/2048 θ/1024 θ/512 θ/256 θ/128 θ/64 θ/32

∗4θ/4096 θ/2048 θ/64 θ/32 θ/16 θ/8 θ/4 θ/2

(θ = Source clock selected by PSCDT0)

Current consumption can be reduced by turning off the clock output to the peripheral circuits that are unused among

those listed above.

Note: In the following cases, the prescaler output clock may contain a hazard:

• If, when a clock is output, its division ratio is changed

• When the clo ck output is switched between on and off

• When the oscillation circuit is turned off or the CPU operating clock is switched over

Before performing these operations, make sure the 16-bit and 8-bit programmable timers and the

A/D converter are turned of f.

Source Clock Output to 8-Bit Programmable Timer

In addition to the divided clock, the prescaler can output the source clock directly to the 8-bit programmable timer.

This function can be selected for each 8-bit timer using P8TPCKx bit.

8-bit timer 0: P8TPCK0 (D0) / 8-bit timer clock select register (0x40146)

8-bit timer 1: P8TPCK1 (D1) / 8-bit timer clock select register (0x40146)

8-bit timer 2: P8TPCK2 (D2) / 8-bit timer clock select register (0x40146)

8-bit timer 3: P8TPCK3 (D3) / 8-bit timer clock s elect register (0x40146)

8-bit timer 4: P8TPCK4 (D0) / 8-bit timer 4/5 clock select register (0x40140)

8-bit timer 5: P8TPCK5 (D1) / 8-bit timer 4/5 clock select register (0x40140)

When P8TPCKx is set to "1", the prescaler input clock (θ/1) is selected fo r the 8-bit timer x operating clock.

The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1".

When P8TPCKx is "0", the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x.

At initial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective.

III PERIPHERAL BLOCK: PRESCALER

S1C33209/221/222 FUNCTION PART EPSON B-III-2-3

I/O Memory of Prescaler

Table 2.3 shows the control bits of the prescaler.

Table 2.3 Control Bits of Prescaler

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

P8TPCK5

P8TPCK4

D7–2

reserved

8-bit timer 5 clock selection

8-bit timer 4 clock selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040140

(B) 1θ/1 0 Divided clk.

1θ/1 0 Divided clk.

8-bit timer 4/5

clock select

–

1 On 0 OffP8TON5

P8TS52

P8TS51

P8TS50

P8TON4

P8TS42

P8TS41

P8TS40

8-bit timer 5 clock control

8-bit timer 5

clock division ratio selection

8-bit timer 4 clock control

8-bit timer 4

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 5 can

generate the clock for

the serial I/F Ch.3.

θ: selected by

Prescaler clock select

8-bit timer 4 can

generate the clock for

the serial I/F Ch.2.

0040145

(B) 1

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

1 On 0 Off

θ/4096

θ/2048

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 4/5

clock control

––

P8TPCK3

P8TPCK2

P8TPCK1

P8TPCK0

D7–4

reserved

8-bit timer 3 clock selection

8-bit timer 2 clock selection

8-bit timer 1 clock selection

8-bit timer 0 clock selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040146

(B) 1θ/1 0 Divided clk.

1θ/1 0 Divided clk.

8-bit timer

clock select

––

P16TON0

P16TS02

P16TS01

P16TS00

D7–4

reserved

16-bit timer 0 clock control

16-bit timer 0

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

16-bit timer 0 can be

used as a watchdog

timer.

0040147

(B) 1 On 0 Off

P16TS0[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 0

clock control

––

P16TON1

P16TS12

P16TS11

P16TS10

D7–4

reserved

16-bit timer 1 clock control

16-bit timer 1

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040148

(B) 1 On 0 Off

P16TS1[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 1

clock control

––

P16TON2

P16TS22

P16TS21

P16TS20

D7–4

reserved

16-bit timer 2 clock control

16-bit timer 2

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

0040149

(B) 1 On 0 Off

P16TS2[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 2

clock control

III PERIPHERAL BLOCK: PRESCALER

B-III-2-4 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

––

P16TON3

P16TS32

P16TS31

P16TS30

D7–4

reserved

16-bit timer 3 clock control

16-bit timer 3

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014A

(B) 1 On 0 Off

P16TS3[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 3

clock control

––

P16TON4

P16TS42

P16TS41

P16TS40

D7–4

reserved

16-bit timer 4 clock control

16-bit timer 4

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014B

(B) 1 On 0 Off

P16TS4[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 4

clock control

––

P16TON5

P16TS52

P16TS51

P16TS50

D7–4

reserved

16-bit timer 5 clock control

16-bit timer 5

clock division ratio selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014C

(B) 1 On 0 Off

P16TS5[2:0] Division ratio

θ/4096

θ/1024

θ/256

θ/64

θ/16

θ/4

θ/2

θ/1

16-bit timer 5

clock control

1 On 0 OffP8TON1

P8TS12

P8TS11

P8TS10

P8TON0

P8TS02

P8TS01

P8TS00

8-bit timer 1 clock control

8-bit timer 1

clock division ratio selection

8-bit timer 0 clock control

8-bit timer 0

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 1 can

generate the OSC3

oscillation-stabilize

waiting period.

θ: selected by

Prescaler clock select

8-bit timer 0 can

generate the DRAM

refresh clock.

004014D

(B) 1

P8TS1[2:0] Division ratio

θ/4096

θ/2048

θ/1024

θ/512

θ/256

θ/128

θ/64

θ/32

1 On 0 Off

P8TS0[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 0/1

clock control

III PERIPHERAL BLOCK: PRESCALER

S1C33209/221/222 FUNCTION PART EPSON B-III-2-5

NameAddressRegister name Bit Function Setting Init. R/W Remarks

1 On 0 OffP8TON3

P8TS32

P8TS31

P8TS30

P8TON2

P8TS22

P8TS21

P8TS20

8-bit timer 3 clock control

8-bit timer 3

clock division ratio selection

8-bit timer 2 clock control

8-bit timer 2

clock division ratio selection

R/W

θ: selected by

Prescaler clock select

8-bit timer 3 can

generate the clock for

the serial I/F Ch.1.

θ: selected by

Prescaler clock select

8-bit timer 2 can

generate the clock for

the serial I/F Ch.0.

004014E

(B) 1

P8TS3[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

1 On 0 Off

P8TS2[2:0] Division ratio

θ/4096

θ/2048

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

8-bit timer 2/3

clock control

–

PSONAD

PSAD2

PSAD1

PSAD0

D7–4

reserved

A/D converter clock control

A/D converter clock division ratio

selection

–

R/W

0 when being read.

θ: selected by

Prescaler clock select

004014F

(B)

A/D clock

control register

1 On 0 Off

P8TS0[2:0] Division ratio

θ/256

θ/128

θ/64

θ/32

θ/16

θ/8

θ/4

θ/2

–

CLKDT1

CLKDT0

PSCON

–

CLKCHG

SOSC3

SOSC1

D4–3

System clock division ratio

selection

Prescaler On/Off control

reserved

CPU operating clock switch

High-speed (OSC3) oscillation On/Off

Low-speed (OSC1) oscillation On/Off

1 On 0 Off

1 OSC3 0 OSC1

1 On 0 Off

R/W

–

R/W

Writing 1 not allowed.

0040180

(B) 1

CLKDT[1:0] Division ratio

1/8

1/4

1/2

1/1

–

Power control

–

PSCDT0

D7–1

D0 reserved

Prescaler clock selection 0

0–

R/W

0040181

(B) –Prescaler clock

select register 1 OSC1 0 OSC3/PLL

Writing 10010110 (0x96)

removes the write protection of

the power control register

(0x40180) and the clock option

Writing another value set the

write protection.

CLGP7

CLGP6

CLGP5

CLGP4

CLGP3

CLGP2

CLGP1

CLGP0

Power control register protect flag 0

R/W004019E

(B)

Power control

protect register

PSCON: Prescaler on/off control (D5) / Power control register (0x40180)

Turns the prescaler on or off.

Write "1": On

Write "0": Off

Read: Valid

The source clock is input to the prescaler by writing "1" to PSCON, thereby starting a dividing operation.

The prescaler is turned off by writing "0". If the peripheral circuits do not need to be operated, write "0" to this bit to

reduce current consumption. Since PSCON is protected against writing the same as SOSC1, SOSC3, CLKCHG and

CLKDT[1:0], CLGP[7:0] must be set to "0b10010110" before PSCON can be changed.

At initial reset, PSCON is set to "1" (On).

III PERIPHERAL BLOCK: PRESCALER

B-III-2-6 EPSON S1C33209/221/222 FUNCTION PART

CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)

These bits remove the prote ction against writing to addresses 0x40180 and 0x40190.

Write "0b10010110": Write protection removed

Write other than the above: No operation (write-protected)

Read: Valid

Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against

writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to

"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is writ ten to.

At initial reset, CLGP is set to "0b00000000" (write-protected).

PSCDT0: Prescaler clock selection (D0) / Prescaler clock select register (0x40181)

Select the source clock for the prescaler.

Write "1": OSC1 clock

Write "0": OSC3 clock/PLL output clock

Read: Valid

When "1" is written to PSCDT0, the OSC1 clock (typ. 32 kHz) is selected.

When "0" is written, the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is

selected.

For the prescaler clock, the clock source same as the CPU operating clock must be selected.

At initial reset, PSCDT0 is set to "0" (OSC3 clock/PLL output clock).

P16TS0[2:0]: 16-bit timer 0 clock division ratio (D[2:0]) / 16-bit timer 0 clock control register (0x40147)

P16TS1[2:0]: 16-bit timer 1 clock division ratio (D[2:0]) / 16-bit timer 1 clock control register (0x40148)

P16TS2[2:0]: 16-bit timer 2 clock division ratio (D[2:0]) / 16-bit timer 2 clock control register (0x40149)

P16TS3[2:0]: 16-bit timer 3 clock division ratio (D[2:0]) / 16-bit timer 3 clock control register (0x4014A)

P16TS4[2:0]: 16-bit timer 4 clock division ratio (D[2:0]) / 16-bit timer 4 clock control register (0x4014B)

P16TS5[2:0]: 16-bit timer 5 clock division ratio (D[2:0]) / 16-bit timer 5 clock control register (0x4014C)

P8TS0[2:0]: 8-bit timer 0 clock division ratio (D[2:0]) / 8-bit timer 0/1 clock control register (0x4014D)

P8TS1[2:0]: 8-bit timer 1 clock division ratio (D[6:4]) / 8-bit timer 0/1 clock control register (0x4014D)

P8TS2[2:0]: 8-bit timer 2 clock division ratio (D[2:0]) / 8-bit timer 2/3 clock control register (0x4014E)

P8TS3[2:0]: 8-bit timer 3 clock division ratio (D[6:4]) / 8-bit timer 2/3 clock control register (0x4014E)

P8TS4[2:0]: 8-bit timer 4 clock division ratio (D[2:0]) / 8-bit timer 4/5 clock control register (0x40145)

P8TS5[2:0]: 8-bit timer 5 clock division ratio (D[6:4]) / 8-bit timer 4/5 clock control register (0x40145)

PSAD[2:0]: A/D converter clock division ratio (D[2:0]) / A/D clock control register (0x4014F)

Select a clock for each peripheral circuit.

The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division

ratio differs for each peripheral circuit.

These bits can also be read out.

At initial reset, all of these bits are set to "0b000" (highest frequency available).

III PERIPHERAL BLOCK: PRESCALER

S1C33209/221/222 FUNCTION PART EPSON B-III-2-7

P16TON0: 16-bit timer 0 clock control (D3) / 16-bit timer 0 clock control register (0x40147)

P16TON1: 16-bit timer 1 clock control (D3) / 16-bit timer 1 clock control register (0x40148)

P16TON2: 16-bit timer 2 clock control (D3) / 16-bit timer 2 clock control register (0x40149)

P16TON3: 16-bit timer 3 clock control (D3) / 16-bit timer 3 clock control register (0x4014A)

P16TON4: 16-bit timer 4 clock control (D3) / 16-bit timer 4 clock control register (0x4014B)

P16TON5: 16-bit timer 5 clock control (D3) / 16-bit timer 5 clock control register (0x4014C)

P8TON0: 8-bit timer 0 clock control (D3) / 8-bit timer 0/1 clock control register (0x4014D)

P8TON1: 8-bit timer 1 clock control (D7) / 8-bit timer 0/1 clock control register (0x4014D)

P8TON2: 8-bit timer 2 clock control (D3) / 8-bit timer 2/3 clock control register (0x4014E)

P8TON3: 8-bit timer 3 clock control (D7) / 8-bit timer 2/3 clock control register (0x4014E)

P8TON4: 8-bit timer 4 clock control (D3) / 8-bit timer 4/5 clock control register (0x40145)

P8TON5: 8-bit timer 5 clock control (D7) / 8-bit timer 4/5 clock control register (0x40145)

PSONAD: A/D converter clock control (D3) / A/D clock control register (0x4014F)

Control the clock supply to each peripheral circuit.

Write "1": On

Write "0": Off

Read: Valid

The clock selected using the division ratio setup bits is output to the corresponding peripheral circuit by writing "1"

to these bits.

The clock is not output by writing "0". If the peripheral circuits do not need to be operated, write "0" to these bits.

This helps to reduce current consumption.

At initial reset, all of these bits are set to "0" (Off).

P8TPCK0: 8-bit timer 0 clock selection (D0) / 8-bit timer clock select register (0x40146)

P8TPCK1: 8-bit timer 1 clock selection (D1) / 8-bit timer clock select register (0x40146)

P8TPCK2: 8-bit timer 2 clock selection (D2) / 8-bit timer clock select register (0x40146)

P8TPCK3: 8-bit timer 3 clock selection (D3) / 8-bit timer clock select register (0x40146)

P8TPCK4: 8-bit timer 4 clock selection (D0) / 8-bit timer 4/5 clock select register (0x40140)

P8TPCK5: 8-bit timer 5 clock selection (D1) / 8-bit timer 4/5 clock select register (0x40140)

Select the operating clock for the 8-bit programmable timer.

Write "1": Prescaler input clock (θ/1)

Write "0": Divided clock

Read: Valid

When "1" is written to P8TPCKx, the prescaler input clock (θ/1) is selected for the 8-bit timer x operating clock.

The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1".

When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x.

At initial reset, P8TPCKx is set to "0" (divided clock).

Programming Notes

(1) For the prescaler clock, the clock source same as the CPU operating clock must be selected.

(2) In the following cases, the prescaler output clock may contain a hazard:

• If, during outputting of a clock, its division ratio is changed

• When the clock output is switched between on and off

• When the oscillation circuit is turned off or the CPU operating clock is switched over

Before performing these operations, make sure the 16-bit and 8-bit programmable timers and the A/D converter

are turned off.

(3) When the 16-bit and 8-bit programmable timers and the A/D converter do not need to be operated, turn off the

clock supply to those peripheral circuits. This helps to reduce current consumption.

III PERIPHERAL BLOCK: PRESCALER

B-III-2-8 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-1

III-3 8-BIT PROGRAMMABLE TIMERS

Configuration of 8-Bit Programmable Timer

The Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5).

Figure 3.1 shows the structure of the 8-bit programmable timer.

Data bus

8-bit reload data register (RLDx)

8-bit down counter

Control registers

Control circuit Data buffer (PTDx)

Underflow

Reload

Clock output

Underflow signal output

Underflow

interrupt

Interrupt

controller

Prescaler

Clock

generator

Figure 3.1 Structure of 8-Bit Programmable Timer

Each timer consists o f an 8-bit presentable counter and can output a clock generated by the counter's underflow

signal to the internal peripheral circuits or external devices. The output clock cycle can be selected from a wide range

of cycles by setting the preset data that can be set in the software and the input clock in the prescaler.

Output Pins of 8-Bit Programmable Timers

The underflow signals of 8-bit programmable timers 0 to 3 can be output to external devices.

Table 3.1 shows the pins that are used to output the underflow signals of the 8-bit programmable timers to external

devices. Table 3.1 Output Pins of 8-Bit Programmable Timers

Pin name I/O Function Function select bit

P10/EXCL0/

T8UF0 I/O I/O port / 16-bit timer 0 event counter

input / 8-bit timer 0 output / DST0 output CFP10(D0)/P1 function select register (0x402D4)

CFEX1(D1)/Port function extension register (0x402DF)

P11/EXCL1/

T8UF1 I/O I/O port / 16-bit timer 1 event counter

input / 8-bit timer 1 output / DST1 output CFP11(D1/P1 function select register (0x402D4)

CFEX1(D1)/Port function extension register (0x402DF)

P12/EXCL2/

T8UF2 I/O I/O port / 16-bit timer 2 event counter

input / 8-bit timer 2 output / DST2 output CFP12(D2/P1 function select register (0x402D4)

CFEX0(D0)/Port function extension register (0x402DF)

P13/EXCL3/

T8UF3 I/O I/O port / 16-bit timer 3 event counter

input / 8-bit timer 3 output / DPCO output CFP13(D3/P1 function select register (0x402D4)

CFEX1(D1)/Port function extension register (0x402DF)

T8UFx (output pin of the 8-bit programmable timer)

This pin outputs a clock divided in each 8-bit programmable timer. The pulse width is equal to that of input

clock of the 8-bit programmable timer (prescaler output). Therefore, the pulse width varies according to the

prescaler setting.

How to set the output pins of the 8-bit programmable timer

All pins used by the 8-bit programmable timers are shared with I/O ports, event counter inputs of the 16-bit

programmable timers and debug signal outputs. At cold start, all these pins are set for the debug signal outputs

(function select bit CFP1[3:0] = "0", port extended function bit CFEX[1:0] = "1"). When using the clock output

function of the 8-bit programmable timer, write "0" to the port extended function bit CFEXx and write "1" to the

function select bit CFP1x for the corresponding pin.

Then, after setting the above, write "1" to the I/O port's I/O control bit IOC1x (D[3:0]) / P1 I/O control register

(0x402D6) t o set to output mode. In input mode, the pin functions as the 16-bit programmable timer's event

counter input and cannot be used to output a clock of the 8-bit programmable timer. At cold start, the register is

set to input mode. At hot start, the register retains its status from prior to the reset.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-2 EPSON S1C33209/221/222 FUNCTION PART

Uses of 8-Bit Programmable Timers

The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset

data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to control

the internal peripheral circuits. In addition, this signal can be output to external devices.

Furthermore, each 8-bit programmable timer generates a clock from the underflow signal by dividing it b y 2, and the

resulting clock is output to a specific internal peripheral circuit.

CPU interrupt request/IDMA invocation request

Each timer's underflow condition can be used as an interrupt factor to output an interrupt request to the CPU.

Therefore, an interrupt can be generated at an interval that is set in the software.

This interrupt factor also can be used to invoke IDMA or HSDMA.

Clock output to external devices

The underflow signal can be output from the chip to the outside. This output can be used to control external

devices. The output pins of each timer are described in the preceding section.

Control of and clock supply to internal peripheral circuits

The following describes the functions controlled by the underflow signal from the 8-bit programmable timer

and the internal peripheral circuits that use the timer's output clock.

8-bit programmable timer 0

• DRAM refresh

When the BCU has a DRAM directly connected to its external bus, the underflow signal from timer 0 can

be used as a DRAM refresh request signal. This enables the intervals of the refresh cycle to be

programmed.

To use this function, write "1" to the BCU's control bit RPC (D9) / Bus control register (0x4812E) to

enable the DRAM refresh.

• A/D conversion start trigger

The A/D converter enables a trigger for starting the A/D conversion to be selected from among four

available types. One of these is the underflow signal of the 8-bit programmable timer 0. This makes it

possible to perform the A/D conversion at programmab le intervals.

To use this function, write "10" to the A/D converter control bit TS[1:0] (D[4:3]) / A/D trigger register

(0x40242) to select the 8-bit programmable timer 0 as the trigger.

8-bit programmable timer 1

• Oscillation stabilization wait time of the high-speed (OSC3) oscillation circuit

When SLEEP mode is cleared by an external interrupt, the high-speed (OSC3) oscillation circuit starts

oscillating. To prevent the CPU from being operated erratically by an unstable clock before the oscillati on

stabilizes, the C33 Core Block enables setting of the waiting time before the CPU starts operating after

SLEEP is cleared. Use the 8-bit programmable timer 1 to generate this waiting time. If the 8-bit

programmable timer 1 is set so that the timer is actuated when the high-speed (OSC3) oscillation circuit

starts oscillating the timer and, after the oscillation stabilization time elapses, an underflow signal is

generated, then the CPU can be started up by that underflow signal.

To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register

(0x40190) to enable the oscillation stabilization waiting function.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-3

8-bit programmable timer 2

• Clock supply to the Ch.0 serial interface

When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based

asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 2

by dividing it by 2 is supplied to the serial interface as its operating clock . This enables the transfer rate of

the serial interface to be programmed.

To use this function, write "0" to the serial interface control bit SSCK0 (D2) / Serial I/F Ch.0 control

8-bit programmable timer 3

• Clock supply to the Ch.1 serial interface

When using the Ch.1 serial interface in the clock-synchronized master mode or the internal clock-based

asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 3

by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of

the serial interface to be programmed.

To use this function, write "0" to the serial interface control bit SSCK1 (D2) / Serial I/F Ch.1 control

8-bit programmable timer 4

• Clock supply to the Ch.2 serial interface

When using the Ch.2 serial interface in the clock-synchronized master mode or the internal clock-based

asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 4

by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of

the serial interface to be programmed.

To use this function, write "0" to the serial interface control bit SSCK2 (D2) / Serial I/F Ch.2 control

8-bit programmable timer 5

• Clock supply to the Ch.3 serial interface

When using the Ch.3 serial interface in the clock-synchronized master mode or the internal clock-based

asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 5

by dividing it by 2 is supplied to the serial interface as its operating clock. This enable s the transfer rate of

the serial interface to be programmed.

To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-4 EPSON S1C33209/221/222 FUNCTION PART

Control and Operation of 8-Bit Programmable Timer

With the 8-bit programmable timer, the following settings must first be made before it starts counting:

1. Setting the output pin (only when necessary)

2. Setting the input clock

3. Setting the preset data (initial counter value)

4. Setting the interrupt/IDMA/HSDMA

Setting of an output pin is necessary only when the output clock of the 8-bit programmable timer is supplied to

external devices. For details on how to set the pin, refer to "Output Pins of 8-Bit Programmable Timers".

For details on how to set interrupts and DMA, refer to "8-Bit Programmable Timer Interrupts and DMA".

Note: The 8-bit programmable timers 0 through 3 all operate in the same way during counting, and the

structure of their control registers is also the same. The control bit names are assigned the

numerals "0" through "3" to denote the timer numbers. Since all these timers have common

functions, timer numbers here are represented it is by "x" unless necessary to specify a timer

number.

Setting the input clock

The 8-bit programmable timer is operated by the prescaler's output clock. The prescaler's division ratio can be

selected for each timer.

Division ratio select bit Clock control bit Register

8-bit timer 0: P8TS0[2:0] (D[2:0]) P8TON0 (D3) 8-bit timer 0/1 clock control register (0x4014D)

8-bit timer 1: P8TS1[2:0] (D[6:4]) P8TON1 (D7) 8-bit timer 0/1 clock control register (0x4014D)

8-bit timer 2: P8TS2[2:0] (D[2:0]) P8TON2 (D3) 8-bit timer 2/3 clock control register (0x4014E)

8-bit timer 3: P8TS3[2: 0] (D[6:4]) P8TON3 (D7) 8-bit timer 2/3 clock control register (0x4014E)

8-bit timer 4: P8TS4[2:0] (D[2:0]) P8TON4 (D3) 8-bit timer 4/5 clock control register (0x40145)

8-bit timer 5: P8TS5[2:0] (D[6:4]) P8TON5 (D7) 8-bit timer 4/5 clock control reg ister (0x40145)

Note that the division ratios differ for each timer (see Table 3.2).

Furthermore, the prescaler input clock can be directly supplied to the 8-bit timer by writing "1" to the P8TCPKx

bit in the 8-bit timer clock select register (0x40146).

Timer 0 clock selection: P8TCPK0 (D0) / 8-bit timer clock select register (0x40146)

Timer 1 clock selection: P8TCPK1 (D1) / 8-bit timer clock select register (0x40146)

Timer 2 clock selection: P8TCPK2 (D2) / 8-bit timer clock select register (0x40146)

Timer 3 clock selection: P8TCPK3 (D3) / 8-bit timer clock select register (0x40146)

Timer 4 clock selection: P8TCPK4 (D0) / 8-bit timer clock select register (0x40140)

Timer 5 clock selection: P8TCPK5 (D1) / 8-bit timer clock select register (0x40140)

When using the divided clock selected by P8TSx, set P8TCPKx to "0".

Table 3.2 Input Clock Selection

Timer P8TSx = 7 P8TSx = 6 P8TSx = 5 P8TSx = 4 P8TSx = 3 P8TSx = 2 P8TSx = 1 P8TSx = 0 P8TCPK = 1

Timer 0 f PSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1

Timer 1 fPSCIN/4096 fPSCIN/2048 fPSCIN/1024 fPSCIN/512 fPSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/1

Timer 2 fPSCIN/4096 fPSCIN/2048 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1

Timer 3 f PSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1

Timer 4 fPSCIN/4096 fPSCIN/2048 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1

Timer 5 f PSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1

fPSCIN: Prescaler input clock frequency

The selected clock is output from the prescaler to the 8-bit programmable timer by writing "1" to P8TONx.

Notes: • The 8-bit programmable timer operates only when the prescaler is operating. (Refer to

"Prescaler".)

• Do not use a clock that is faster than the CPU operating clock as the 8-bit programmable timer.

• When setting an input clock, make sure the 8-bit programmable timer is turned off.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-5

Setting preset data (initial counter value)

Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set

the initial value of the down-counter of each timer.

Timer 0 reload data: RLD0[7:0] (D[7:0]) / 8-bit timer 0 reload data register (0x40161)

Timer 1 reload data: RLD1[7:0] (D[7:0]) / 8-bit timer 1 reload data register (0x40165)

Timer 2 reload data: RLD2[7:0] (D[7:0]) / 8-bit timer 2 reload data register (0x40169)

Timer 3 reload data: RLD3[7:0] (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)

Timer 4 reload data: RLD4[7:0] (D[7:0]) / 8-bit timer 4 reload data register (0x40175)

Timer 5 reload data: RLD5[7:0] (D[7:0]) / 8-bit timer 5 reload data register (0x40176)

The reload data registers can be read and written. At initial reset, the reload data registers are not initialized.

The data written to this register is preset in the down-counter, and the counter starts counting down from the

preset value.

Data is thus preset in the down-counter in the following two cases:

1. When it is preset in the software

Presetting in the software is performed using the preset control bit PSETx. When this bit is set to "1", the

content of the reload d ata register is loaded into the down-counter at that point.

Timer 0 preset: PSET0 (D1) / 8-bit timer 0 control register (0x40160)

Timer 1 preset: PSET1 (D1) / 8-bit timer 1 control register (0x40164)

Timer 2 preset: PSET2 (D1) / 8-bit timer 2 control register (0x40168)

Timer 3 preset: PSET3 (D1) / 8-bit timer 3 control register (0x4016C)

Timer 4 preset: PSET4 (D1) / 8-bit timer 4 control register (0x40174)

Timer 5 preset: PSET5 (D1) / 8-bit timer 5 control register (0x40178)

2. When the down-counter underflown during counting

Since the reload data is preset in the down-counter upon underflow, its underflow cycle is determined by the

value that is set in the reload data register. This underflow signal controls each function described in the

preceding section.

Before starting the 8-bit programmable timer, set the initial value in the reload data register and use the PSETx

bit to preset the data in the down-counter.

The underflow cycle is determined by the prescaler setting and the reload d ata. The relationship between these

two parameters is expressed by the following equation:

Under flow cycle = RLDx + 1 [sec.]

fPSCIN × pdr

fPSCIN: Prescaler input clock frequency [Hz]

pdr: Prescaler division ratio set by P8TSx

RLDx: Set value of the RLDx register (0 to 255)

Timer RUN/STOP control

Each timer has a PTRUNx bit to control RUN/STOP.

Timer 0 RUN/STOP control: PTRUN0 (D0) / 8-bit timer 0 control register (0x40160)

Timer 1 RUN/STOP control: PTRUN1 (D0) / 8-bit timer 1 control register (0x40164)

Timer 2 RUN/STOP control: PTRUN2 (D0) / 8-bit timer 2 control register (0x40168)

Timer 3 RUN/STOP control: PTRUN3 (D0) / 8-bit timer 3 control register (0x4016C)

Timer 4 RUN/STOP control: PTRUN4 (D0) / 8-bit timer 4 control register (0x40174)

Timer 5 RUN/STOP control: PTRUN5 (D0) / 8-bit timer 5 control register (0x40178)

The timer is initiated to start counting down by writing "1" to PTRUNx. Writing "0" to PTRUNx disables the

clock input and causes the timer to stop counting.

This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the

counter retains its count so that it can start counting again from that point.

When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload

data register into the counter.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-6 EPSON S1C33209/221/222 FUNCTION PART

When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the

same time, the timer starts counting after presetting the reload register valu e into the counter.

PTRUNx

PSETx

RLDx

Input clock

PTDx7

PTDx6

PTDx5

PTDx4

PTDx3

PTDx2

PTDx1

PTDx0

Preset

Timer

initial setup Reload and

interrupt

0xA60x10 0xF3

Figure 3.2 Basic Operation Timing of Counter

Reading out counter data

The counter data is read out via a PTDx data buffer. The counter data can be read out at any time.

Timer 0 data: PTD0[7:0] (D[7:0]) / 8-bit timer 0 counter data register (0x40162)

Timer 1 data: PTD1[7:0] (D[7:0]) / 8-bit timer 1 counter data register (0x40166)

Timer 2 data: PTD2[7:0] (D[7:0]) / 8-bit timer 2 counter data register (0x4016A)

Timer 3 data: PTD3[7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E)

Timer 4 data: PTD4[7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176)

Timer 5 data: PTD5[7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A)

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-7

Control of Clock Output

When outputting an underflow signal of the 8-bit programmable timer to external devices, or when supplying a clock

generated by the underflow signal to the serial interface, it is necessary to control the clock output of the timer.

Timer 0 clock output control: PTOUT0 (D2) / 8-bit timer 0 control register (0x40160)

Timer 1 clock output control: PTOUT1 (D2) / 8-bit timer 1 control register (0x40164)

Timer 2 clock output control: PTOUT2 (D2) / 8-bit timer 2 control register (0x40168)

Timer 3 clock output control: PTOUT3 (D2) / 8-bit timer 3 control register (0x4016C)

To output the underflow signal/clock, write "1" to PTOUTx. If an output pin has been set, the underflow signal is

output from that pin.

The same applies when timer 2 or 3 has been set as the clock source of the serial interface. A clock generated from the

underflow signal by dividing it by 2 is output to the serial interface through this control. The clock output is turned

off by writing "0" to PTOUTx, and the external output is fixed at "0" and the internal clock output is fixed at "1".

Figure 3.3 shows the waveforms of the output signals.

Underflow signal

Underflow signal/2

PTOUTx

External output

T8UFx pin

Clock output

Figure 3.3 8-Bit Programmable Timer Output Waveform

The underflow signal's pulse width (duration of the high period) is equal to that of the timer's input clock (prescaler's

output).

8-bit timer external output (P10– P13 ports)

1) After an initial reset (cold start), the ports (P10– P13) are set to debug signal putput ports.

2) The port (P10– P13) outputs "0" when it is set to the 8-bit timer output (timer output is off status).

3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial

value.

4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit

timer input clock pulse (prescaler's output).

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-8 EPSON S1C33209/221/222 FUNCTION PART

8-Bit Programmable Timer Interrupts and DMA

The 8-bit programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to 3.

The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section.

Control registers of the interrupt controller

Table 3.3 shows the interrupt controller's control register provided for each timer.

Table 3.3 Control Registers of Interrupt Controller

Timer Interrupt factor flag Interrupt enable register Interrupt priority r egister

Timer 0 F8TU0(D0/0x40285) E8TU0(D0/0x40275) P8TM[2:0](D[2:0]/0x40269)

Timer 1 F8TU1(D1/0x40285) E8TU1(D1/0x40275)

Timer 2 F8TU2(D2/0x40285) E8TU2(D2/0x40275)

Timer 3 F8TU3(D3/0x40285) E8TU3(D3/0x40275)

When the timer underflows, the corresponding interrupt factor flag is set to "1". If the interrupt enable register

bit corresponding to that interrupt factor flag has been set to "1", an interrupt request is generated.

An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to "0".

The interrupt factor flag is set to "1" whenever the timer underflows, regardless of how the interrupt enable

The interrupt priority register sets an interrupt priority level (0 to 7) for the four timers as one interrupt source.

Within 8-bit programmable timers, timer 0 has the highest priority and timer 3 the lowest. An interrupt request

to the CPU is accepted on the condition that no other interrupt request of a higher priority has been generated.

It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer

interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the

CPU.

For details on these interrupt control registers and device operation when an interrupt has occurred, refer to

"ITC (Interrupt Controller)".

Intelligent DMA

The underflow interrupt factor of the timer 0 to 3 can invoke intelligent DMA (IDMA). This enables memory-

to-memory DMA transfers to be performed cyclically.

The following shows the IDMA channel numbers set to each timer:

IDMA channel

Timer 0: 0x13

Timer 1: 0x14

Timer 2: 0x15

Timer 3: 0x16

For IDMA to be i nvoked, the IDMA request and IDMA enable bits shown in Table 3.4 must be set to "1" in

advance. Transfer conditions, etc. must also be set on the IDMA side in advance.

Table 3.4 Control Bits for IDMA Transfer

Timer IDMA request bit IDMA enable bit

Timer 0 R8TU0(D2/0x40292) DE8TU0(D2/0x40296)

Timer 1 R8TU1(D3/0x40292) DE8TU1(D3/0x40296)

Timer 2 R8TU2(D4/0x40292) DE8TU2(D4/0x40296)

Timer 3 R8TU3(D5/0x40292) DE8TU3(D5/0x40296)

If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.

No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is

completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed.

For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA

(Intelligent DMA)".

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-9

High-speed DMA

The underflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA).

The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3:

Table 3.5 HSDMA Trigger Set-up Bits

Timer HSDMA channel Trigger set-up bits

Timer 0 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298)

Timer 1 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298)

Timer 2 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299)

Timer 3 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299)

For HSDMA to be invoked, the trigger set-up bits should be set to "0101" in advance. Transfer conditions, etc.

must also be set on the HSDMA side.

If the 8-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the

interrupt factor.

For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".

Trap vectors

The trap vector addresses for individual underflow interrupt factors are set by default as shown below:

Timer 0 underflow interrupt: 0x0C000D0

Timer 1 underflow interrupt: 0x0C000D4

Timer 2 underflow interrupt: 0x0C000D8

Timer 3 underflow interrupt: 0x0C000DC

The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-10 EPSON S1C33209/221/222 FUNCTION PART

I/O Memory of 8-Bit Programmable Timers

Table 3.6 shows the control bits of the 8-bit programmable timers.

For details on the I/O memory of the prescaler u sed to set a clock, refer to "Prescaler".

Table 3.6 Control Bits of 8-Bit Programmable Timer

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PTOUT0

PSET0

PTRUN0

D7–3

reserved

8-bit timer 0 clock output control

8-bit timer 0 preset

8-bit timer 0 Run/Stop control

–

R/W

0 when being read.

0040160

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 0

control register

0 to 255RLD07

RLD06

RLD05

RLD04

RLD03

RLD02

RLD01

RLD00

8-bit timer 0 reload data

RLD07 = MSB

RLD00 = LSB

R/W0040161

(B)

8-bit timer 0

reload data

0 to 255PTD07

PTD06

PTD05

PTD04

PTD03

PTD02

PTD01

PTD00

8-bit timer 0 counter data

PTD07 = MSB

PTD00 = LSB

R0040162

(B)

8-bit timer 0

counter data

–

PTOUT1

PSET1

PTRUN1

D7–3

reserved

8-bit timer 1 clock output control

8-bit timer 1 preset

8-bit timer 1 Run/Stop control

–

R/W

0 when being read.

0040164

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 1

control register

0 to 255RLD17

RLD16

RLD15

RLD14

RLD13

RLD12

RLD11

RLD10

8-bit timer 1 reload data

RLD17 = MSB

RLD10 = LSB

R/W0040165

(B)

8-bit timer 1

reload data

0 to 255PTD17

PTD16

PTD15

PTD14

PTD13

PTD12

PTD11

PTD10

8-bit timer 1 counter data

PTD17 = MSB

PTD10 = LSB

R0040166

(B)

8-bit timer 1

counter data

–

PTOUT2

PSET2

PTRUN2

D7–3

reserved

8-bit timer 2 clock output control

8-bit timer 2 preset

8-bit timer 2 Run/Stop control

–

R/W

0 when being read.

0040168

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 2

control register

0 to 255RLD27

RLD26

RLD25

RLD24

RLD23

RLD22

RLD21

RLD20

8-bit timer 2 reload data

RLD27 = MSB

RLD20 = LSB

R/W0040169

(B)

8-bit timer 2

reload data

0 to 255PTD27

PTD26

PTD25

PTD24

PTD23

PTD22

PTD21

PTD20

8-bit timer 2 counter data

PTD27 = MSB

PTD20 = LSB

R004016A

(B)

8-bit timer 2

counter data

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-11

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PTOUT3

PSET3

PTRUN3

D7–3

reserved

8-bit timer 3 clock output control

8-bit timer 3 preset

8-bit timer 3 Run/Stop control

–

R/W

0 when being read.

004016C

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 3

control register

0 to 255RLD37

RLD36

RLD35

RLD34

RLD33

RLD32

RLD31

RLD30

8-bit timer 3 reload data

RLD37 = MSB

RLD30 = LSB

R/W004016D

(B)

8-bit timer 3

reload data

0 to 255PTD37

PTD36

PTD35

PTD34

PTD33

PTD32

PTD31

PTD30

8-bit timer 3 counter data

PTD37 = MSB

PTD30 = LSB

R004016E

(B)

8-bit timer 3

counter data

–

PTOUT4

PSET4

PTRUN4

D7–3

reserved

8-bit timer 4 clock output control

8-bit timer 4 preset

8-bit timer 4 Run/Stop control

–

R/W

0 when being read.

0040174

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 4

control register

0 to 255RLD47

RLD46

RLD45

RLD44

RLD43

RLD42

RLD41

RLD40

8-bit timer 4 reload data

RLD47 = MSB

RLD40 = LSB

R/W0040175

(B)

8-bit timer 4

reload data

0 to 255PTD47

PTD46

PTD45

PTD44

PTD43

PTD42

PTD41

PTD40

8-bit timer 4 counter data

PTD47 = MSB

PTD40 = LSB

R0040176

(B)

8-bit timer 4

counter data

–

PTOUT5

PSET5

PTRUN5

D7–3

reserved

8-bit timer 5 clock output control

8-bit timer 5 preset

8-bit timer 5 Run/Stop control

–

R/W

0 when being read.

0040178

(B) –

1 On 0 Off

1 Preset 0 Invalid

1 Run 0 Stop

8-bit timer 5

control register

0 to 255RLD57

RLD56

RLD55

RLD54

RLD53

RLD52

RLD51

RLD50

8-bit timer 5 reload data

RLD57 = MSB

RLD50 = LSB

R/W0040179

(B)

8-bit timer 5

reload data

0 to 255PTD57

PTD56

PTD55

PTD54

PTD53

PTD52

PTD51

PTD50

8-bit timer 5 counter data

PTD57 = MSB

PTD50 = LSB

R004017A

(B)

8-bit timer 5

counter data

–

0 to 7

–

PSIO02

PSIO01

PSIO00

–

P8TM2

P8TM1

P8TM0

reserved

Serial interface Ch.0

interrupt level

reserved

8-bit timer 0–3 interrupt level

–

R/W

–

R/W

0 when being read.

0040269

(B)

8-bit timer,

serial I/F Ch.0

interrupt

priority register

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-12 EPSON S1C33209/221/222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

E8TU3

E8TU2

E8TU1

E8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040275

(B) 1Enabled 0Disabled

8-bit timer

interrupt

enable register

–

F8TU3

F8TU2

F8TU1

F8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

– –

–

R/W

0 when being read.0040285

(B) 1Factor is

generated 0No factor is

generated

8-bit timer

interrupt factor

flag register

RSTX0

RSRX0

R8TU3

R8TU2

R8TU1

R8TU0

R16TC5

R16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040292

(B) 1IDMA

request 0Interrupt

request

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA request

DESTX0

DESRX0

DE8TU3

DE8TU2

DE8TU1

DE8TU0

DE16TC5

DE16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040296

(B) 1IDMA

enabled 0IDMA

disabled

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA enable

–

CFP16

CFP15

CFP14

CFP13

CFP12

CFP11

CFP10

reserved

P16 function selection

P15 function selection

P14 function selection

P13 function selection

P12 function selection

P11 function selection

P10 function selection

–

R/W

0 when being read.

Extended functions

(0x402DF)

00402D4

(B) 1EXCL5

#DMAEND1

0P16

1EXCL4

#DMAEND0

0P15

1EXCL3

T8UF3 0P13

1EXCL2

T8UF2 0P12

1EXCL1

T8UF1 0P11

1EXCL0

T8UF0 0P10

–P1 function

select register

1FOSC1 0P14

–

IOC16

IOC15

IOC14

IOC13

IOC12

IOC11

IOC10

reserved

P16 I/O control

P15 I/O control

P14 I/O control

P13 I/O control

P12 I/O control

P11 I/O control

P10 I/O control

–

R/W

0 when being read.00402D6

(B) 1Output 0Input

–P1 I/O control

CFEX7

CFEX6

CFEX5

CFEX4

CFEX3

CFEX2

CFEX1

CFEX0

P07 port extended function

P06 port extended function

P05 port extended function

P04 port extended function

P31 port extended function

P21 port extended function

P10, P11, P13 port extended

function

P12, P14 port extended function

R/W

00402DF

(B)

Port function

extension

#DMAEND3

0P07, etc.

#DMAACK3

0P06, etc.

#DMAEND2

0P05, etc.

#DMAACK2

0P04, etc.

1#GARD 0P31, etc.

1#GAAS 0P21, etc.

1DST0

DST1

DPC0

0P10, etc.

P11, etc.

P13, etc.

1DST2

DCLK 0P12, etc.

P14, etc.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-13

CFP13–CFP10: P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4)

Selects the pin that is used to output a timer underflow signal to external devices.

Write "1": Underflow signal output pin

Write "0": I/O port pin

Read: Valid

Select the pin used to output a timer underflow signal to external devices from among P10 through P13 by writing

"1" to the corresponding bit, CFP10 through CFP13. P10 through P13 correspond to timers 0 through 3, respectively.

If "0" is written to CFP1x, the pin is set for an I/O port.

At cold start, CFP1x is set to "0" (I/O port). At hot start, the bit retains its state from prior to the initial reset.

IOC13–IOC10: P1[3:0] port I/O control (D[3:0]) / P1 I/O control register (0x402D6)

Sets input or output mode for P10 through P13.

Write "1": Output mode

Write "0": Input mode

Read: Valid

If a pin chosen from among P10 through P13 is used to output an underflow signal, write "1" to the corresponding

I/O control bit to set it to output mode. If the pin is set to input mode, even if its CFP1x is set to "1", it functions as

the event counter input pin of a 16-bit programmable timer cannot be used to output a timer underflow signal.

At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset.

CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF)

CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF)

Sets whether the function of an I/O-port pin is to be extended.

Write "1": Function-extended pin

Write "0": I/O-port/peripheral-circuit pin

Read: Valid

When CFEX[1:0] is set to "1", the P13–P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the

CFP1[3:0] bit becomes effective, so the settings of these bits determine whether the P13– P10 ports function as I/O

port s or timer underflow signal output ports.

At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to

the initial reset.

RLD07–RLD00: Timer 0 reload data (D[7:0]) / 8-bit timer 0 reload data register (0x40161)

RLD17–RLD10: Timer 1 reload data (D[7:0]) / 8-bit timer 1 reload data register (0x40165)

RLD27–RLD20: Timer 2 reload data (D[7:0]) / 8-bit timer 2 reload data register (0x40169)

RLD37–RLD30: Timer 3 reload data (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)

RLD47–RLD40: Timer 4 reload data (D[7:0]) / 8-bit timer 4 reload data register (0x40175)

RLD57–RLD50: Timer 5 reload data (D[7:0]) / 8-bit timer 5 reload data register (0x40179)

Set the initial counter value of each timer.

The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with

this data, which is used as the initial count.

There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to

PSETx, or when data is automatically reloaded upon counter underflow.

At initial reset, RLD is not initialized.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-14 EPSON S1C33209/221/222 FUNCTION PART

PTD07–PTD00: Timer 0 counter data (D[7:0]) / 8-bit timer 0 counter data (0x40162)

PTD17–PTD10: Timer 1 counter data (D[7:0]) / 8-bit timer 1 counter data (0x40166)

PTD27–PTD20: Timer 2 counter data (D[7:0]) / 8-bit timer 2 counter data (0x4016A)

PTD37–PTD30: Timer 3 counter data (D[7:0]) / 8-bit timer 3 counter data (0x4016E)

PTD47–PTD40: Timer 4 counter data (D[7:0]) / 8-bit timer 4 counter data (0x40176)

PTD57–PTD50: Timer 5 counter data (D[7:0]) / 8-bit timer 5 counter data (0x4017A)

The 8-bit programmable timer data can be read out from these bits.

These bits function as buffers that retain the counter data when read out, enabling the data to be read out at any time.

At initial reset, PTD is not initialized.

PSET0: Timer 0 preset (D1) / 8-bit timer 0 control register (0x40160)

PSET1: Timer 1 preset (D1) / 8-bit timer 1 control register (0x40164)

PSET2: Timer 2 preset (D1) / 8-bit timer 2 control register (0x40168)

PSET3: Timer 3 preset (D1) / 8-bit timer 3 control register (0x4016C)

PSET4: Timer 4 preset (D1) / 8-bit timer 4 control register (0x40174)

PSET5: Timer 5 preset (D1) / 8-bit timer 5 control register (0x40178)

Preset the reload data in the counter.

Write "1": Preset

Write "0": Invalid

Read: Always "0"

The reload data of RLDx is preset in the counter of timer x by writing "1" to PSETx. If the counter is preset when in

a RUN state, the counter starts counting immediately after the reload data is preset.

If the counter is preset when in a STOP state, the reload data that has been preset is retained.

Writing "0" results in No Operation.

Since PSETx is a write-only bit, its content when read is always "0".

PTRUN0: Timer 0 RUN/STOP control (D0) / 8-bit timer 0 control register (0x40160)

PTRUN1: Timer 1 RUN/STOP control (D0) / 8-bit timer 1 control register (0x40164)

PTRUN2: Timer 2 RUN/STOP control (D0) / 8-bit timer 2 control register (0x40168)

PTRUN3: Timer 3 RUN/STOP control (D0) / 8-bit timer 3 control register (0x4016C)

PTRUN4: Timer 4 RUN/STOP control (D0) / 8-bit timer 4 control register (0x40174)

PTRUN5: Timer 5 RUN/STOP control (D0) / 8-bit timer 5 control register (0x40178)

Controls the counter's RUN/STOP states.

Write "1": RUN

Write "0": STOP

Read: Valid

The counter of each timer starts counting down when "1" written to PTRUNx, and stops counting when "0" is written.

While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When

the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count.

At initial reset, PTRUNx is set to "0" (STOP).

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-15

PTOUT0: Timer 0 clock output control register (D2) / 8-bit timer 0 control register (0x40160)

PTOUT1: Timer 1 clock output control register (D2) / 8-bit timer 1 control register (0x40164)

PTOUT2: Timer 2 clock output control register (D2) / 8-bit timer 2 control register (0x40168)

PTOUT3: Timer 3 clock output control register (D2) / 8-bit timer 3 control register (0x4016C)

PTOUT4: Timer 4 clock output control register (D2) / 8-bit timer 4 control register (0x40174)

PTOUT5: Timer 5 clock output control register (D2) / 8-bit timer 5 control register (0x40178)

Controls the clock output of each timer.

Write "1": On

Write "0": Off

Read: Valid

The underflow signal of timer x is output from the external output pin set by CFP1x by writing "1" to PTOUTx.

When using timer 2 or 3 as the clock source of the serial interface, a clock generated from the underflow signal by

dividing it by 2 is output to the corresponding channel of the serial interface.

The clock output is turned off by writing "0" to PTOUT, and the external output is fixed at "0" and the internal clock

output is fixed at "1".

At initial reset, PTOUT is set to "0" (off).

P8TM2–P8TM0: 8-bit timer interrupt level (D[2:0]) / 8-bit timer, serial I/F Ch.0 interrupt priority register (0x40269)

Set the priority level of the 8-bit programmable timer interrupt in the range of 0 to 7.

At initial reset, the content of the P8TM register becomes indeterminate.

E8TU0: Timer 0 interrupt enable (D0) / 8-bit timer interrupt enable register (0x40275)

E8TU1: Timer 1 interrupt enable (D1) / 8-bit timer interrupt enable register (0x40275)

E8TU2: Timer 2 interrupt enable (D2) / 8-bit timer interrupt enable register (0x40275)

E8TU3: Timer 3 interrupt enable (D3) / 8-bit timer interrupt enable register (0x40275)

Enables or disables generation of an interrupt to the CPU.

Write "1": Interrupt enabled

Write "0": Interrupt disabled

Read: Valid

E8TUx is the interrupt enable bit which controls the interrupt generated by each timer. The interrupt set to "1" by

this bit is enabled, and the interrupt set to "0" by this bit is disabled.

At initial reset, E8TUx is set to "0" (interrupt disabled).

F8TU0: Timer 0 interrupt factor flag (D0) / 8-bit timer interrupt factor flag register (0x40285)

F8TU1: Timer 1 interrupt factor flag (D1) / 8-bit timer interrupt factor flag register (0x40285)

F8TU2: Timer 2 interrupt factor flag (D2) / 8-bit timer interrupt factor flag register (0x40285)

F8TU3: Timer 3 interrupt factor flag (D3) / 8-bit timer interrupt factor flag register (0x40285)

Indicates the interrupt generation status of the 8-bit programmable timer.

When read

Read "1": Interrupt factor has occurred

Read "0": No interrupt factor has occurred

When written using the reset-only method (default)

Write "1": Interrupt factor flag is reset

Write "0": Invalid

When written using the read/write method

Write "1": Interrupt flag is set

Write "0": Interrupt flag is reset

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-16 EPSON S1C33209/221/222 FUNCTION PART

F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows.

At this time, if the following conditions are met, an interrupt to the CPU is generated:

1. The corresponding interrupt enable register bit is set to "1".

2. No other interrupt request of a higher priority has been generated.

3. The IE bit of the PSR is set to "1" (interrupts enabled).

4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.

When using the interrupt factor of the 8-bit programmable timer to request IDMA, note that even when the above

conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If

interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after t he data

transfer by IDMA is completed.

The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the

interrupt enable and interrupt priority registers are set.

If the next interrupt is to be accepted aft er an interrupt has occurred, it is necessary that the interrupt factor flag be

reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level

indicated by the interrupt priority register, or by exec uting the reti instruction).

The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept

interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor fla g, the same

interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method

(RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used.

At initial reset, the content of F8TUx becomes indeterminate, so be sure to reset it in the software.

R8TU0: Timer 0 IDMA request (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)

R8TU1: Timer 1 IDMA request (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)

R8TU2: Timer 2 IDMA request (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)

R8TU3: Timer 3 IDMA request (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)

Specifies whether IDMA is to be invoked at the occurrence of an interrupt factor.

When using the set-only method (default)

Write "1": IDMA request

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA request

Write "0": Interrupt request

Read: Valid

R8TUx is the IDMA request bit for each timer. If this bit is set to "1", IDMA can be invoked when an interrupt factor

occurs, and thus programmed data transfers are performed. If the bit is set to "0", normal interrupt processing is

performed and IDMA is not invoked.

For details on IDMA, refer to "IDMA (Intelligent DMA)".

At initial reset, R8TUx is set to "0" (interrupt request).

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-3-17

DE8TU0: Timer 0 IDMA enable (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

DE8TU1: Timer 1 IDMA enable (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

DE8TU2: Timer 2 IDMA enable (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

DE8TU3: Timer 3 IDMA enable (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

Enables IDMA transfer by means of an interrupt factor.

When using the set-only method (default)

Write "1": IDMA enabled

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA enabled

Write "0": IDMA disabled

Read: Valid

If DE8TUx is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the

IDMA request is disabled.

After an initial reset, DE8TUx is set to "0" (IDMA disabled).

Programming Notes

(1) The 8-bit programmable timer operates only when the prescaler is operating.

(2) Do not use a clock that is faster than the CPU operating clock for the 8-bit programmable timer.

(3) When setting an input clock, make sure the 8-bit programmable timer is turned off.

(4) Since the underflow interrupt condition and the timer output status are undefined after an initial reset, the

counter initial value should be set to the 8-bit timer before resetting the interrupt factor flag or turning the

timer output on.

(5) After an initial reset, the interrupt factor flag (F8TUx) becomes indeterminate. To prevent generation of an

unwanted interrupt or IDMA request, be sure to reset this fl ag in the software.

(6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be

sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction.

III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

B-III-3-18 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-1

III-4 16-BIT PROGRAMMABLE TIMERS

Configuration of 16-Bit Programmable Timer

The Peripheral Block contains six systems of 16-bit programmable timers (timers 0 to 5). They also have an event

counter function using an I/O port pin.

Note: On the following pages, each timer is identified as timer x (x = 0 to 5). The functions and control

assigned numerals "0" to "5" denoting timer numbers. Since explanations are common to all timers,

timer numbers are represented by "x" unless it is necessary to specify a timer number.

Figure 4.1 shows the structure of one channel of the 16-bit programmable timer.

Data bus

16-bit up counter (TCx)

16-bit comparison data register B (CRxB)

Comparison register B buffer (CRBxB)

16-bit comparison data register A (CRxA)

Comparison register A buffer (CRBxA)

Timer x control register

Control circuit

Clock select circuitPrescaler

Clock

generator

Comparator

INCLx

Clock output TMx

Comparison A

interrupt

Comparison B

interrupt

Comparison

match B

Comparison

match A

Comparison A

Comparison B

Timer x

Interrupt

controller

External clock EXCLx

Figure 4.1 Structure of 16-Bit Programmable Timer

In each timer, a 16-bit up-counter (TCx), as well as two 16-bit comparison data registers (CRxA, CRxB) and their

buffers (CRBxA, CRBxB), are provided.

The 16-bit counter can be reset to "0" by software and counts up using the prescaler output clock or an external signal

input from the I/O port. The counter value can be read by software.

The comparison data registers A and B are used to store the data to be compared with the content of the up-counter.

This register can be directly read and written. Furthermore, comparison data can be set via the comparison register

buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the

comparison match B signal or software (by writing "1" to PRESETx bit). The software can select whether

comparison data is written to the comparison data register or the buffer.

When the counter value matches to the content of each comparison data register, the comparator outputs a signal that

controls the interrupt and the output signal. Thus the registers allow interrupt generating intervals and the timer's

output clock frequency and duty ratio to be programmed.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-2 EPSON S1C33209/221/ 222 FUNCTION PART

I/O Pins of 16-Bit Programmable Timers

Table 4.1 shows the input/output pins used for the 16-bit programmable timers.

Table 4.1 I/O Pins of 16-Bit Programmable Timer

Pin name I/O Function Function select bit

P10/EXCL0/

T8UF0/DST0 I/O I/O port / 16-bit timer 0 event counter input (I) /

8-bit timer 0 output (O) / DST0 output (Ex) CFP10(D0)/P1 function select register(0x402D4)

CFEX1(D1)/Port function extension register(0x402DF)

P11/EXCL1/

T8UF1/DST1 I/O I/O port / 16-bit timer 1 event counter input (I) /

8-bit timer 1 output (O) / DST1 output (Ex) CFP11(D1)/P1 function select register(0x402D4)

CFEX1(D1)/Port function extension register(0x402DF)

P12/EXCL2/

T8UF2/DST2 I/O I/O port / 16-bit timer 2 event counter input (I) /

8-bit timer 2 output (O) / DST2 output (Ex) CFP12(D2)/P1 function select register(0x402D4)

CFEX0(D0)/Port function extension register(0x402DF)

P13/EXCL3/

T8UF3/DPCO I/O I/O port / 16-bit timer 3 event counter input (I) /

8-bit timer 3 output (O) / DPCO output (Ex) CFP13(D3)/P1 function select register(0x402D4)

CFEX1(D1)/Port function extension register(0x402DF)

P15/EXCL4

/#DMAEND0 I/O I/O port / 16-bit timer 4 event counter input (I) /

High-speed DMA Ch.0 end signal output (O) CFP15(D5)/P1 function select register(0x402D4)

P16/EXCL5

/#DMAEND1 I/O I/O port / 16-bit timer 5 event counter input (I) /

High-speed DMA Ch.1 end signal output (O) CFP16(D6)/P1 function select register(0x402D4)

P22/TM0 I/O I/O port / 16-bit timer 0 output CFP22(D2)/P2 function select register(0x402D8)

P23/TM1 I/O I/O port / 16-bit timer 1 output CFP23(D3)/P2 function select register(0x402D8)

P24/TM2 I/O I/O port / 16-bit timer 2 output CFP24(D4)/P2 function select register(0x402D8)

P25/TM3 I/O I/O port / 16-bit timer 3 output CFP25(D5)/P2 function select register(0x402D8)

P26/TM4 I/O I/O port / 16-bit timer 4 output CFP26(D6)/P2 function select register(0x402D8)

P27/TM5 I/O I/O port / 16-bit timer 5 output CFP27(D7)/P2 function select register(0x402D8)

(I): Input mode, (O): Output mode, (Ex): Extended function

TMx (output pin of the 16-bit programmable timer)

This pin outputs a clock generated by the timer x.

EXCLx (event counter input pin)

When using the timer x as an event counter, input count pulses from an external source to this pin.

How to set the input/output pins of 16-bit programmable timers

All clock output pins used by the 16-bit programma ble timers are shared with I/O ports. At cold start, all these

pins are set for the I/O port pins P2x (function select bit CFP2x = "0"), and go into high-impedance.

When using the clock output function of the 16-bit programmable timer, select the desired timer and write "1" to

the function select bit CFP2x for the corresponding pin. At hot start, these pins retain their status before from

prior to the reset.

All event-counter input pins are also shared with I/O-ports. At cold start, the EXCL[3:0] pins are set for debug

signal output pins (function extension bit CFEX[1:0] = "1") and the EXCL[5:4] pins are set for I/O-port pins

P1[5:4] (function select bit CFP1[5:4] = "0"). When using the event counter function, select the desired timer

and write "1" to the function select bit CFP1x and write "0" to the function select bit CFEXx for the

corresponding pin.

Note that these pins are also shared with output pins for the 8-bit programmer timers, etc. When the input/output

pins are set in input mode, they function as event counter inputs. Therefore, it is necessary to set the I/O port's

I/O control bit IOC1x to "0" in advance. At cold start, these pins are set in input mode. At hot start, they retain

their status from prior to the reset.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-3

Uses of 16-Bit Progr ammable Timers

The up-counters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with

the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or

control the internal peripheral circuits. A clock generated from the signal can also be output to external devices.

CPU interrupt request/IDMA invocation request

Each timer's comparison match (matching of counter and comparison data) can be used as an interrupt factor to

generate an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set in the

software.

Furthermore, this interrupt factor can also be used to invoke IDMA or HSDMA.

Clock output to external devices

A clock generated from the comparison-match signal can be output from the chip to the outside. The clock cycle

is determined by comparison data B, and the duty ratio is determined by comparison data A. This output can be

used to control external devices. The output pins of each timer are described in the preceding section.

A/D converter start trigger

The A/D converter allows a trigger to start the A/D conversion to be selected from among four available types.

One is the comparison-match B of the 16-bit programm able timer 0. This makes it possible to perform the A/D

conversion at programmable intervals.

To use this function, write "01" to the A/D converter control TS[1:0] (D[4:3]) / A/D trigger register

(0x40242) to select the 16-bit programmable timer 0 as the trigger.

Watchdog timer

The 16-bit programmable timer 0 can be used as a watchdog timer to monitor CPU crash. In this case, the

comparison-match B of this timer serves as an NMI request signal to the CPU.

To use this function, write "1" to the watch dog timer control bit EWD (D1) / Watchdog timer enable register

(0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer".

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-4 EPSON S1C33209/221/ 222 FUNCTION PART

Control and Operation of 16-Bit Programmable Timer

The following settings must first be made before the 16-bit programmable timer starts counting:

1. Setting pins for input/output (only when necessary)

2. Setting input clock

3. Selecting comparison data register/buffer

4. Setting clock output conditions (signal active level, fine mode)

5. Setting comparison data

6. Setting interrupt/IDMA

For details on how to set clock output conditions and interrupts and DMA, refer to "Controlling Clock Output" and

"16-Bit Programmable Timer Interrupts and DMA".

Setting pin for input/output

The pin must be set for output for the output clock of the 16-bit programmable timer to be fed to external

devices.

The pin for input must be set for the 16-bit programmable timer to be used as an event counter that counts external

clock pulses.

For details on how to set the pin, refer to "I/O Pins of 16-Bit Programmable Timers".

Setting the input clock

The count clock for each timer can be selected from between an internal clock and an external clock. Use the

following control bits to select the input clock:

Timer 0 input clock selection: CKSL0 (D3) / 16-bit timer 0 control register (0x48186)

Timer 1 input clock selection: CKSL1 (D3) / 16-bit timer 1 control register (0X4818E)

Timer 2 input clock selection: CKSL2 (D3) / 16-bit timer 2 control register (0x48196)

Timer 3 input clock selection: CKSL3 (D3) / 16-bit timer 3 control register (0x4819E)

Timer 4 input clock selection: CKSL4 (D3) / 16-bit timer 4 control register (0x481A6)

Timer 5 input clock selection: CKSL5 (D3) / 16-bit timer 5 control register (0x481AE)

An external clock is selected by writing "1" to CKSLx, and the internal clock is selected by writing "0".

At initial reset, CKSLx is set for the internal clock.

An external clock can be used for the timer for which the pin is set for input.

• Internal clock

When the internal clock is selected as a timer, the timer is operated by the prescaler output clock. The prescaler

division ratio can be selected for each timer.

Table 4.2 Setting the Internal Clock

Timer Control register Division ratio select bit Clock control bit

Timer 0 16-bit timer 0 clock control register (0x40147) P16TS0[2:0] (D2:0]) P16TON0 (D3)

Timer 1 16-bit timer 1 clock control register (0x40148) P16TS1[2:0] (D2:0]) P16TON1 (D3)

Timer 2 16-bit timer 2 clock control register (0x40149) P16TS2[2:0] (D2:0]) P16TON2 (D3)

Timer 3 16-bit timer 3 clock control register (0x4014A) P16TS3[2:0] (D2:0]) P16TON3 (D3)

Timer 4 16-bit timer 4 clock control register (0x4014B) P16TS4[2:0] (D2:0]) P16TON4 (D3)

Timer 5 16-bit timer 5 clock control register (0x4014C) P16TS5[2:0] (D2:0]) P16TON5 (D3)

The division ratio can be selected from among eight types as shown in Table 4.3.

Table 4.3 Input Clock Selection

P16TS = 7 P16TS = 6 P16TS = 5 P16TS = 4 P16TS = 3 P16TS = 2 P16TS = 1 P16TS = 0

fPSCIN/4096 fPSCIN/1024 fPSCIN/256 fPSCIN/64 fPSCIN/16 fPSCIN/4 fPSCIN/2 fPSCIN/1

fPSCIN: Prescaler input clock frequency

The selected clock is output from the prescaler to the 16-bit programmable timer by writing "1" to P16TONx.

Notes: • When the internal clock is used, the 16-bit programmable timer operates only when the

prescaler is operating (refer to "Prescaler").

• When setting an input clock, make sure the 16-bit programmable timer is turned off.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-5

• External clock

When using the timer as an event counter by supplying clock pulses from an external source, make sure the event

cycle is at least the CPU operating clock period.

Selecting comparison data register/buffer

The comparison data registers A and B are used to store the data to be compared with the content of the up-

counter. This register can be directly read and written. Furthermore, comparison data can be set via the

comparison register buffer. In this case, the set value is loaded to the comparison data register when the

counter is reset by the comparison match B signal or software (by writing "1" to PRESETx bit).

Select whether comparison data is written to the comparison data register or the buffer using the following

control bits:

Timer 0 comparison register buffer enable: SELCRB0 (D5) / 16-bit timer 0 control register (0x48186)

Timer 1 comparison register buffer enable: SELCRB1 (D5) / 16-bit timer 1 control register (0x4818E)

Timer 2 comparison register buffer enable: SELCRB2 (D5) / 16-bit timer 2 control register (0x48196)

Timer 3 comparison register buffer enable: SELCRB3 (D5) / 16-bit timer 3 control register (0x4819E)

Timer 4 comparison register buffer enable: SELCRB4 (D5) / 16-bit timer 4 control register (0x481A6)

Timer 5 comparison register buffer enable: SELCRB5 (D5) / 16-bit timer 5 control register (0x481AE)

When "1" is written to SELCRBx, the comparison register buffer is se lected and when "0" is written, the

comparison data register is selected.

At initial reset, the comparison data register is selected.

Setting comparison data

The programmable timer contains two data comparators that allows the count data to be compared with given

values. The following registers are used to set these values.

Timer 0 comparison data A: CR0A[15:0] (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180)

Timer 0 comparison data B: CR0B[15:0] (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182)

Timer 1 comparison data A: CR1A[15:0] (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188)

Timer 1 comparison data B: CR1B[15:0] (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A)

Timer 2 comparison data A: CR2A[15:0] (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190)

Timer 2 comparison data B: CR2B[15:0] (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192)

Timer 3 comparison data A: CR3A[15:0] (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198)

Timer 3 comparison data B: CR3B[15:0] (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A)

Timer 4 comparison data A: CR4A[15:0] (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0)

Timer 4 comparison data B: CR4B[15:0] (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2)

Timer 5 comparison data A: CR5A[15:0] (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8)

Timer 5 comparison data B: CR5B[15:0] (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA)

When SELCRBx is set to "0", these registers allow direct reading/writing from/to the comparison data register.

When SELCRBx is set to "1", these registers are used to read/write from/to the comparison register buffer. The

content of the buffer is loaded to the comparison data register when the counter is reset.

At initial reset, the comparison data registers/buffers are not initialized.

The programma ble timer compares the comparison data register and count data and, when the two values are

equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx

signal) to external devices, in addition to generating an interrupt.

The comparison data B is also used to reset the counter.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-6 EPSON S1C33209/221/ 222 FUNCTION PART

Resetting the counter

Each timer includes the PRESETx bit to reset the counter.

Timer 0 reset: PRESET0 (D1) / 16-bit timer 0 control register (0x48186)

Timer 1 reset: PRESET1 (D1) / 16-bit timer 1 control register (0x4818E)

Timer 2 reset: PRESET2 (D1) / 16-bit timer 2 control register (0x48196)

Timer 3 reset: PRESET3 (D1) / 16-bit timer 3 control register (0x4819E)

Timer 4 reset: PRESET4 (D1) / 16-bit timer 4 control register (0x481A6)

Timer 5 reset: PRESET5 (D1) / 16-bit timer 5 control register (0x481AE)

Normally, reset the counter before starting count-up by writing "1" to this control bit.

After the counter starts counting, it will be reset by comparison match B.

Timer RUN/STOP control

Each timer includes the PRUNx bit to control RUN/STOP.

Timer 0 RUN/STOP control: PRUN0 (D0) / 16-bit timer 0 control register (0x48186)

Timer 1 RUN/STOP control: PRUN1 (D0) / 16-bit timer 1 control register (0x4818E)

Timer 2 RUN/STOP control: PRUN2 (D0) / 16-bit timer 2 control register (0x48196)

Timer 3 RUN/STOP control: PRUN3 (D0) / 16-bit timer 3 control register (0x4819E)

Timer 4 RUN/STOP control: PRUN4 (D0) / 16-bit timer 4 control register (0x481A6)

Timer 5 RUN/STOP control: PRUN5 (D0) / 16-bit timer 5 control register (0x481AE)

The timer starts counting when "1" is written to PRUNx. The clock input is disabled and the timer stops

counting when "0" is written to PRUNx.

This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the

counter retains its count so that the timer can start counting again from that point.

If the count of the counter matches the set value of the comparison data register during count-up, the timer

generates a comparison match interrupt.

When the counter matches comparison data B, an interrupt is generated and the counter is reset. At the same

time, the values set in the compare register buffer are loaded to the compare data register if SELCRBx is set to

"1".

The counter continues counting up regardless of which interrupt has occurred. In the case of a comparison B

interrupt, the counter starts counting beginning with 0.

When both the timer RUN/STOP control bit (PRUNx) and the timer reset bit (PRESETx) are set to "1" at the

same time, the timer starts counting after resetting the counter.

PRUNx

PRESETx

CRxA

CRxB

Input clock

TCx

Reset Comparison A

interrupt Reset and

Comparison B

interrupt

Comparison A

interrupt Reset and

Comparison B

interrupt

0x2

0 1234501234501

0x5

Figure 4.2 Basic Operation Timing of Counter

Reading counter data

The counter data can be read out from the following addresses shown below at any time:

Timer 0 counter data: TC0[15:0] (D[F:0]) / 16-bit timer 0 counter data register (0x48184)

Timer 1 counter data: TC1[15:0] (D[F:0]) / 16-bit timer 1 counter data register (0x4818C)

Timer 2 counter data: TC2[15:0] (D[F:0]) / 16-bit timer 2 counter data register (0x48194)

Timer 3 counter data: TC3[15:0] (D[F:0]) / 16-bit timer 3 counter data register (0x4819C)

Timer 4 counter data: TC4[15:0] (D[F:0]) / 16-bit timer 4 counter data register (0x481A4)

Timer 5 counter data: TC5[15:0] (D[F:0]) / 16-bit timer 5 counter data register (0x481AC)

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-7

Controlling Clock Output

The timers can generate a TMx signal using the comparison match signals from the counter.

Setting the signal active level

By default, an active high signal (normal low ) is generated. This logic can be inverted using the OUTINVx bit.

When "1" is written to the OUTINVx bit, the timer generates an active low (normal high) signal.

Timer 0 clock output inversion: OUTINV0 (D4) / 16-bit timer 0 control register (0x48186)

Timer 1 clock output inversion: OUTINV1 (D4) / 16-bit timer 1 control register (0x4818E)

Timer 2 clock output inversion: OUTINV2 (D4) / 16-bit timer 2 control register (0x48196)

Timer 3 clock output inversion: OUTINV3 (D4) / 16-bit timer 3 control register (0x4819E)

Timer 4 clock output inversion: OUTINV4 (D4) / 16-bit timer 4 control register (0x481A6)

Timer 5 clock output inversion: OUTINV5 (D4) / 16-bit timer 5 control register (0x481AE)

See Figure 4.3 for the waveforms.

Setting the output port

The TMx signal generated here can be output from the clock output pins (see Table 4.1), enabling a

programmable clock to be supplied to external devices.

After a cold start, the outpu t pins are set for the I/O ports and set in input mode. The pins go into high-

impedance status.

When the pin function is switched to the timer output, the pin goes low if OUTINVx is set to "0" or goes high if

OUTINVx is set to "1".

Starting clock output

To output the TMx clock, write "1" to the clock output control bit PTMx. Clock output is stopped by writing

"0" to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high

when OUTINVx = "1").

Timer 0 clock output control: PTM0 (D2) / 16-bit timer 0 control register (0x48186)

Timer 1 clock output control: PTM1 (D2) / 16-bit timer 1 control register (0x4818E)

Timer 2 clock output control: PTM2 (D2) / 16-bit timer 2 control register (0x48196)

Timer 3 clock output control: PTM3 (D2) / 16-bit timer 3 control register (0x4819E)

Timer 4 clock output control: PTM4 (D2) / 16-bit timer 4 control register (0x481A6)

Timer 5 clock output control: PTM5 (D2) / 16-bit timer 5 control register (0x481AE)

Figure 4.3 shows the waveform of the output signal.

Input clock

PRUNx

CRxA

CRxB

Counter value

Comparison match A signal

Comparison match B signal

PTMx

TMx output (when OUTINVx = "0")

TMx output (when OUTINVx = "1")

0 1234501234501234501

Figure 4.3 Waveform of 16-Bit Programmable Timer Output

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-8 EPSON S1C33209/221/ 222 FUNCTION PART

When OUTINVx = "0" (active high):

The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA register.

When the counter is incremented to the next value from the comparison data A, the output pin goes high and a

comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the CRxB

When OUTINVx = "1" (active low):

The timer outputs a high level until the counter becomes equal to the comparison data A set in the CRxA

and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the

CRxB register, the coun ter is reset and the output pin goes high. At the same time a comparison B interrupt

occurs.

Setting clock output fine mode

By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when

CRxA[15:0] becomes equal to TCx[15:0].

In fine mode, the output signal changes according to CRxA[0] when CRxA[15:1] becomes equal to TCx[14:0].

When CRxA[0] is "0", the output signal changes at the rising edge of the input clock.

When CRxA[0] is "1", the output signal changes at the falling edge of the input clock a half cycle from the

default setting.

Example) CRxA = 3, CRxB = 5 Input clock

Counter value

Comparison match A signal

Comparison match B signal

TMx output (when OUTINVx = "0")

TMx output (when OUTINVx = "1")

01234501234501

Figure 4.4 Clock Output in Fine Mode

As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the

input clock. However, when the CRxA value is "0", the timer outputs a pulse with a 1-cycle width as the input

clock, the same as the default setting.

In fine mode, the maximum value of CRxB is 215 - 1 = 32,767 and the range of CRxA that can be set is 0 to (2

× CRxB - 1).

The fine mode is set by the following registers:

Timer 0 fine mode selection: SELFM0 (D6) / 16-bit timer 0 control register (0x48186)

Timer 1 fine mode selection: SELFM1 (D6) / 1 6-bit timer 1 control register (0x4818E)

Timer 2 fine mode selection: SELFM2 (D6) / 16-bit timer 2 control register (0x48196)

Timer 3 fine mode selection: SELFM3 (D6) / 16-bit timer 3 control register (0x4819E)

Timer 4 fine mode selection: SELFM4 (D6) / 16-bit timer 4 control register (0x481A6)

Timer 5 fine mode selection: SELFM5 (D6) / 16-bit timer 5 control register (0x481AE)

When "1" is written to the SELFMx bit, fine mode is set. At initial reset, the fine mode is disabled.

Precautions

1) If a sa me value is set to the comparison data A and B registers, a hazard may be generated in the output

signal. Therefore, do not set the comparison registers as A = B.

There is no problem when the interrupt function only is used.

2) When using the output clock, set the comparison data registers as A ≥ 0 and B ≥ 1. The minimum settings

are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock × 1/2.

3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case, the

output signal is fixed at the off level.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-9

16-Bit Programmable Timer Interrupts and DMA

The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B states.

The timing at which an inter rupt is generated is shown in Figure 4.2 in the preceding section.

Control registers of the interrupt controller

Table 4.4 shows the control registers of the interrupt controller provided for each timer.

Table 4.4 Control Registers of Interrupt Controller

Interrupt factor Interrupt factor flag Interrupt enable register Interrupt priority register

Timer 0 comparison A F16TC0 (D3/0x40282) E16TC0 (D3/0x40272) P16T0[2:0] (D[2:0]/0x40266)

Timer 0 comparison B F16TU0 (D2/0x40282) E16TU0 (D2/0x40272)

Timer 1 comparison A F16TC1 (D7/0x40282) E16TC1 (D7/0x40272) P16T1[2:0] (D[6:4]/0x40266)

Timer 1 comparison B F16TU1 (D6/0x40282) E16TU1 (D6/0x40272)

Timer 2 comparison A F16TC2 (D3/0x40283) E16TC2 (D3/0x40273) P16T2[2:0] (D[2:0]/0x40267)

Timer 2 comparison B F16TU2 (D2/0x40283) E16TU2 (D2/0x40273)

Timer 3 comparison A F16TC3 (D7/0x40283) E16TC3 (D7/0x40273) P16T3[2:0] (D[6:4]/0x40267)

Timer 3 comparison B F16TU3 (D6/0x40283) E16TU3 (D6/0x40273)

Timer 4 comparison A F16TC4 (D3/0x40284) E16TC4 (D3/0x40274) P16T4[2:0] (D[2:0]/0x40268)

Timer 4 comparison B F16TU4 (D2/0x40284) E16TU4 (D2/0x40274)

Timer 5 comparison A F16TC5 (D7/0x40284) E16TC5 (D7/0x40274) P16T5[2:0] (D[6:4]/0x40268)

Timer 5 comparison B F16TU5 (D6/0x40284) E16TU5 (D6/0x40274)

When a comparison match state occurs in the timer, the corresponding interrupt factor flag is set to "1".

If the interrupt enable register bit corresponding to that interrupt factor flag has been set to "1", an interrupt

request is generated.

An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to

"0". The interrupt factor flag is always set to "1" by the timer's comparison match state, regardless of how the

interrupt enable register is set (even when set to "0").

The interrupt priority register sets an interrupt priority level (0 to 7) for each timer. Priorities within a timer

block are such that timers of smaller numbers have a higher priority. Priorities between interrupt types are such

that the comparison B interrupt has priority over the comparison A interrupt. An interrupt request to the CPU

is accepted only when no other interrupt request of a higher priority has been generated.

It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer

interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the

CPU.

For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,

refer to "ITC (Interrupt Controller)".

Intelligent DMA

The interrupt factor of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory

DMA transfers to be performed cyclically.

The following shows the IDMA channel numbers set for each interrupt factor of timer:

IDMA Ch. IDMA Ch.

Timer 0 comparison B: 0x07 Timer 0 comparison A: 0x08

Timer 1 comparison B: 0x09 Timer 1 comparison A: 0x0A

Timer 2 comparison B: 0x0B Timer 2 comparison A: 0x0C

Timer 3 comparison B: 0x0D Timer 3 comparison A: 0x0E

Timer 4 comparison B: 0x0F Timer 4 comparison A: 0x10

Timer 5 comparison B: 0x11 Timer 5 comparison A: 0x12

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-10 EPSON S1C33209/221/ 222 FUNCTION PART

For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in

advance. Transfer conditions, etc. must also be set on the IDMA side in advance.

Table 4.5 Control Bits for IDMA Transfer

Interrupt factor IDMA request bit IDMA enable bit

Timer 0 comparison A R16TC0(D7/0x40290) DE16TC0(D7/0x40294)

Timer 0 comparison B R16TU0(D6/0x40290) DE16TU0(D6/0x40294)

Timer 1 comparison A R16TC1(D1/0x40291) DE16TC1(D1/0x40295)

Timer 1 comparison B R16TU1(D0/0x40291) DE16TU1(D0/0x40295)

Timer 2 comparison A R16TC2(D3/0x40291) DE16TC2(D3/0x40295)

Timer 2 comparison B R16TU2(D2/0x40291) DE16TU2(D2/0x40295)

Timer 3 comparison A R16TC3(D5/0x40291) DE16TC3(D5/0x40295)

Timer 3 comparison B R16TU3(D4/0x40291) DE16TU3(D4/0x40295)

Timer 4 comparison A R16TC4(D7/0x40291) DE16TC4(D7/0x40295)

Timer 4 comparison B R16TU4(D6/0x40291) DE16TU4(D6/0x40295)

Timer 5 comparison A R16TC5(D1/0x40292) DE16TC5(D1/0x40296)

Timer 5 comparison B R16TU5(D0/0x40292) DE16TU5(D0/0x40296)

If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.

No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is

completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed.

For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA

(Intelligent DMA)".

High-speed DMA

The interrupt factor of each timer can also invoke high-speed DMA (HSDMA).

The following shows the HSDMA channel number and trigger set-up bit corresponding to each timer:

Table 4.6 HSDMA Trigger Set-up Bits

Interrupt factor HSDMA

Ch. Trigger set-up bits

Timer 0 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"

Timer 0 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110"

Timer 1 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"

Timer 1 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x4029 8) = "0110"

Timer 2 comparison A 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"

Timer 2 comparison B 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"

Timer 3 comparison A 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"

Timer 3 comparison B 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"

Timer 4 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"

2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"

Timer 4 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"

2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"

Timer 5 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"

3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"

Timer 5 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"

3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"

For HSDMA to be invoked, a 16-bit timer interrupt factor should be selected using the trigger set-up bits in

advance. Tra nsfer conditions, etc. must also be set on the HSDMA side.

If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the

interrupt factor.

For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-11

Trap vectors

The trap vector addresses for each default interrupt factor are set as shown below:

Timer 0 comparison B: 0x0C00078

Timer 0 comparison A: 0x0C0007C

Timer 1 comparison B: 0x0C00088

Timer 1 comparison A: 0x0C0008C

Timer 2 comparison B: 0x0C00098

Timer 2 comparison A: 0x0C0009C

Timer 3 comparison B: 0x0C000A8

Timer 3 comparison A: 0x0C000AC

Timer 4 comparison B: 0x0C000B8

Timer 4 comparison A: 0x0C000BC

Timer 5 comparison B: 0x0C000C8

Timer 5 comparison A: 0x0C000CC

The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).

Precaution

Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined

which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for

details of the settings.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-12 EPSON S1C33209/221/ 222 FUNCTION PART

I/O Memory of 16-Bit Programmable Timers

Table 4.7 shows the control bits of the 16-bit programmable timers.

For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler".

Table 4.7 Control Bits of 16-Bit Programmable Timer

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

0 to 7

–

P16T12

P16T11

P16T10

–

P16T02

P16T01

P16T00

reserved

16-bit timer 1 interrupt level

reserved

16-bit timer 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040266

(B)

16-bit timer 0/1

interrupt

priority register

–

0 to 7

–

P16T32

P16T31

P16T30

–

P16T22

P16T21

P16T20

reserved

16-bit timer 3 interrupt level

reserved

16-bit timer 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040267

(B)

16-bit timer 2/3

interrupt

priority register

–

0 to 7

–

P16T52

P16T51

P16T50

–

P16T42

P16T41

P16T40

reserved

16-bit timer 5 interrupt level

reserved

16-bit timer 4 interrupt level

–

R/W

–

R/W

0 when being read.

0040268

(B)

16-bit timer 4/5

interrupt

priority register

E16TC1

E16TU1

–

E16TC0

E16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040272

(B) 1 Enabled 0 Disabled

16-bit timer 0/1

interrupt

enable register –

1 Enabled 0 Disabled

–

E16TC3

E16TU3

–

E16TC2

E16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040273

(B) 1 Enabled 0 Disabled

16-bit timer 2/3

interrupt

enable register –

1 Enabled 0 Disabled

–

E16TC5

E16TU5

–

E16TC4

E16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040274

(B) 1 Enabled 0 Disabled

16-bit timer 4/5

interrupt

enable register –

1 Enabled 0 Disabled

–

F16TC1

F16TU1

–

F16TC0

F16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040282

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 0/1

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC3

F16TU3

–

F16TC2

F16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040283

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 2/3

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

F16TC5

F16TU5

–

F16TC4

F16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040284

(B) 1 Factor is

generated 0 No factor is

generated

16-bit timer 4/5

interrupt factor

flag register –

1 Factor is

generated 0 No factor is

generated

–

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-13

NameAddressRegister name Bit Function Setting Init. R/W Remarks

R16TC0

R16TU0

RHDM1

RHDM0

RP3

RP2

RP1

RP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040290

(B) 1 IDMA

request 0 Interrupt

request

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA request

R16TC4

R16TU4

R16TC3

R16TU3

R16TC2

R16TU2

R16TC1

R16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040291

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 1–4

IDMA request

RSTX0

RSRX0

R8TU3

R8TU2

R8TU1

R8TU0

R16TC5

R16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040292

(B) 1 IDMA

request 0 Interrupt

request

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA request

DE16TC0

DE16TU0

DEHDM1

DEHDM0

DEP3

DEP2

DEP1

DEP0

16-bit timer 0 comparison A

16-bit timer 0 comparison B

High-speed DMA Ch.1

High-speed DMA Ch.0

Port input 3

Port input 2

Port input 1

Port input 0

R/W

0040294

(B) 1 IDMA

enabled 0 IDMA

disabled

Port input 0–3,

high-speed

DMA Ch. 0/1,

16-bit timer 0

IDMA enable

DE16TC4

DE16TU4

DE16TC3

DE16TU3

DE16TC2

DE16TU2

DE16TC1

DE16TU1

16-bit timer 4 comparison A

16-bit timer 4 comparison B

16-bit timer 3 comparison A

16-bit timer 3 comparison B

16-bit timer 2 comparison A

16-bit timer 2 comparison B

16-bit timer 1 comparison A

16-bit timer 1 comparison B

R/W

0040295

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 1–4

IDMA enable

DESTX0

DESRX0

DE8TU3

DE8TU2

DE8TU1

DE8TU0

DE16TC5

DE16TU5

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

16-bit timer 5 comparison A

16-bit timer 5 comparison B

R/W

0040296

(B) 1 IDMA

enabled 0 IDMA

disabled

16-bit timer 5,

8-bit timer,

serial I/F Ch.0

IDMA enable

–

CFP16

CFP15

CFP14

CFP13

CFP12

CFP11

CFP10

reserved

P16 function selection

P15 function selection

P14 function selection

P13 function selection

P12 function selection

P11 function selection

P10 function selection

–

R/W

0 when being read.

Extended functions

(0x402DF)

00402D4

(B) 1 EXCL5

#DMAEND1

0 P16

1 EXCL4

#DMAEND0

0 P15

1 EXCL3

T8UF3 0 P13

1 EXCL2

T8UF2 0 P12

1 EXCL1

T8UF1 0 P11

1 EXCL0

T8UF0 0 P10

–P1 function

select register

1 FOSC1 0 P14

CFP27

CFP26

CFP25

CFP24

CFP23

CFP22

CFP21

CFP20

P27 function selection

P26 function selection

P25 function selection

P24 function selection

P23 function selection

P22 function selection

P21 function selection

P20 function selection

R/W

R/W Ext. func.(0x402DF)

00402D8

(B) 1 TM5 0 P27

1 TM4 0 P26

1 TM3 0 P25

1 TM2 0 P24

1 TM1 0 P23

1 TM0 0 P22

1 #DWE 0 P21

1 #DRD 0 P20

P2 function

select register

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-14 EPSON S1C33209/221/ 222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

CFEX7

CFEX6

CFEX5

CFEX4

CFEX3

CFEX2

CFEX1

CFEX0

P07 port extended function

P06 port extended function

P05 port extended function

P04 port extended function

P31 port extended function

P21 port extended function

P10, P11, P13 port extended

function

P12, P14 port extended function

R/W

00402DF

(B)

Port function

extension

#DMAEND3

0 P07, etc.

#DMAACK3

0 P06, etc.

#DMAEND2

0 P05, etc.

#DMAACK2

0 P04, etc.

1 #GARD 0 P31, etc.

1 #GAAS 0 P21, etc.

1 DST0

DST1

DPC0

0 P10, etc.

P11, etc.

P13, etc.

1 DST2

DCLK 0 P12, etc.

P14, etc.

0 to 65535CR0A15

CR0A14

CR0A13

CR0A12

CR0A11

CR0A10

CR0A9

CR0A8

CR0A7

CR0A6

CR0A5

CR0A4

CR0A3

CR0A2

CR0A1

CR0A0

16-bit timer 0 comparison data A

CR0A15 = MSB

CR0A0 = LSB

R/W0048180

(HW)

16-bit timer 0

comparison

data A set-up

0 to 65535CR0B15

CR0B14

CR0B13

CR0B12

CR0B11

CR0B10

CR0B9

CR0B8

CR0B7

CR0B6

CR0B5

CR0B4

CR0B3

CR0B2

CR0B1

CR0B0

16-bit timer 0 comparison data B

CR0B15 = MSB

CR0B0 = LSB

R/W0048182

(HW)

16-bit timer 0

comparison

data B set-up

0 to 65535TC015

TC014

TC013

TC012

TC011

TC010

TC09

TC08

TC07

TC06

TC05

TC04

TC03

TC02

TC01

TC00

16-bit timer 0 counter data

TC015 = MSB

TC00 = LSB

R0048184

(HW)

16-bit timer 0

counter data

–

SELFM0

SELCRB0

OUTINV0

CKSL0

PTM0

PRESET0

PRUN0

reserved

16-bit timer 0 fine mode selection

16-bit timer 0 comparison buffer

16-bit timer 0 output inversion

16-bit timer 0 input clock selection

16-bit timer 0 clock output control

16-bit timer 0 reset

16-bit timer 0 Run/Stop control

–

R/W

0 when being read.

0048186

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 0

control register

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-15

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR1A15

CR1A14

CR1A13

CR1A12

CR1A11

CR1A10

CR1A9

CR1A8

CR1A7

CR1A6

CR1A5

CR1A4

CR1A3

CR1A2

CR1A1

CR1A0

16-bit timer 1 comparison data A

CR1A15 = MSB

CR1A0 = LSB

R/W0048188

(HW)

16-bit timer 1

comparison

data A set-up

0 to 65535CR1B15

CR1B14

CR1B13

CR1B12

CR1B11

CR1B10

CR1B9

CR1B8

CR1B7

CR1B6

CR1B5

CR1B4

CR1B3

CR1B2

CR1B1

CR1B0

16-bit timer 1 comparison data B

CR1B15 = MSB

CR1B0 = LSB

R/W004818A

(HW)

16-bit timer 1

comparison

data B set-up

0 to 65535TC115

TC114

TC113

TC112

TC111

TC110

TC19

TC18

TC17

TC16

TC15

TC14

TC13

TC12

TC11

TC10

16-bit timer 1 counter data

TC115 = MSB

TC10 = LSB

R004818C

(HW)

16-bit timer 1

counter data

–

SELFM1

SELCRB1

OUTINV1

CKSL1

PTM1

PRESET1

PRUN1

reserved

16-bit timer 1 fine mode selection

16-bit timer 1 comparison buffer

16-bit timer 1 output inversion

16-bit timer 1 input clock selection

16-bit timer 1 clock output control

16-bit timer 1 reset

16-bit timer 1 Run/Stop control

–

R/W

0 when being read.

004818E

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 1

control register

0 to 65535CR2A15

CR2A14

CR2A13

CR2A12

CR2A11

CR2A10

CR2A9

CR2A8

CR2A7

CR2A6

CR2A5

CR2A4

CR2A3

CR2A2

CR2A1

CR2A0

16-bit timer 2 comparison data A

CR2A15 = MSB

CR2A0 = LSB

R/W0048190

(HW)

16-bit timer 2

comparison

data A set-up

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-16 EPSON S1C33209/221/ 222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535CR2B15

CR2B14

CR2B13

CR2B12

CR2B11

CR2B10

CR2B9

CR2B8

CR2B7

CR2B6

CR2B5

CR2B4

CR2B3

CR2B2

CR2B1

CR2B0

16-bit timer 2 comparison data B

CR2B15 = MSB

CR2B0 = LSB

R/W0048192

(HW)

16-bit timer 2

comparison

data B set-up

0 to 65535TC215

TC214

TC213

TC212

TC211

TC210

TC29

TC28

TC27

TC26

TC25

TC24

TC23

TC22

TC21

TC20

16-bit timer 2 counter data

TC215 = MSB

TC20 = LSB

R0048194

(HW)

16-bit timer 2

counter data

–

SELFM2

SELCRB2

OUTINV2

CKSL2

PTM2

PRESET2

PRUN2

reserved

16-bit timer 2 fine mode selection

16-bit timer 2 comparison buffer

16-bit timer 2 output inversion

16-bit timer 2 input clock selection

16-bit timer 2 clock output control

16-bit timer 2 reset

16-bit timer 2 Run/Stop control

–

R/W

0 when being read.

0048196

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 2

control register

0 to 65535CR3A15

CR3A14

CR3A13

CR3A12

CR3A11

CR3A10

CR3A9

CR3A8

CR3A7

CR3A6

CR3A5

CR3A4

CR3A3

CR3A2

CR3A1

CR3A0

16-bit timer 3 comparison data A

CR3A15 = MSB

CR3A0 = LSB

R/W0048198

(HW)

16-bit timer 3

comparison

data A set-up

0 to 65535CR3B15

CR3B14

CR3B13

CR3B12

CR3B11

CR3B10

CR3B9

CR3B8

CR3B7

CR3B6

CR3B5

CR3B4

CR3B3

CR3B2

CR3B1

CR3B0

16-bit timer 3 comparison data B

CR3B15 = MSB

CR3B0 = LSB

R/W004819A

(HW)

16-bit timer 3

comparison

data B set-up

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-17

NameAddressRegister name Bit Function Setting Init. R/W Remarks

0 to 65535TC315

TC314

TC313

TC312

TC311

TC310

TC39

TC38

TC37

TC36

TC35

TC34

TC33

TC32

TC31

TC30

16-bit timer 3 counter data

TC315 = MSB

TC30 = LSB

R004819C

(HW)

16-bit timer 3

counter data

–

SELFM3

SELCRB3

OUTINV3

CKSL3

PTM3

PRESET3

PRUN3

reserved

16-bit timer 3 fine mode selection

16-bit timer 3 comparison buffer

16-bit timer 3 output inversion

16-bit timer 3 input clock selection

16-bit timer 3 clock output control

16-bit timer 3 reset

16-bit timer 3 Run/Stop control

–

R/W

0 when being read.

004819E

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 3

control register

0 to 65535CR4A15

CR4A14

CR4A13

CR4A12

CR4A11

CR4A10

CR4A9

CR4A8

CR4A7

CR4A6

CR4A5

CR4A4

CR4A3

CR4A2

CR4A1

CR4A0

16-bit timer 4 comparison data A

CR4A15 = MSB

CR4A0 = LSB

R/W00481A0

(HW)

16-bit timer 4

comparison

data A set-up

0 to 65535CR4B15

CR4B14

CR4B13

CR4B12

CR4B11

CR4B10

CR4B9

CR4B8

CR4B7

CR4B6

CR4B5

CR4B4

CR4B3

CR4B2

CR4B1

CR4B0

16-bit timer 4 comparison data B

CR4B15 = MSB

CR4B0 = LSB

R/W00481A2

(HW)

16-bit timer 4

comparison

data B set-up

0 to 65535TC415

TC414

TC413

TC412

TC411

TC410

TC49

TC48

TC47

TC46

TC45

TC44

TC43

TC42

TC41

TC40

16-bit timer 4 counter data

TC415 = MSB

TC40 = LSB

R00481A4

(HW)

16-bit timer 4

counter data

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-18 EPSON S1C33209/221/ 222 FUNCTION PART

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

SELFM4

SELCRB4

OUTINV4

CKSL4

PTM4

PRESET4

PRUN4

reserved

16-bit timer 4 fine mode selection

16-bit timer 4 comparison buffer

16-bit timer 4 output inversion

16-bit timer 4 input clock selection

16-bit timer 4 clock output control

16-bit timer 4 reset

16-bit timer 4 Run/Stop control

–

R/W

0 when being read.

00481A6

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 4

control register

0 to 65535CR5A15

CR5A14

CR5A13

CR5A12

CR5A11

CR5A10

CR5A9

CR5A8

CR5A7

CR5A6

CR5A5

CR5A4

CR5A3

CR5A2

CR5A1

CR5A0

16-bit timer 5 comparison data A

CR5A15 = MSB

CR5A0 = LSB

R/W00481A8

(HW)

16-bit timer 5

comparison

data A set-up

0 to 65535CR5B15

CR5B14

CR5B13

CR5B12

CR5B11

CR5B10

CR5B9

CR5B8

CR5B7

CR5B6

CR5B5

CR5B4

CR5B3

CR5B2

CR5B1

CR5B0

16-bit timer 5 comparison data B

CR5B15 = MSB

CR5B0 = LSB

R/W00481AA

(HW)

16-bit timer 5

comparison

data B set-up

0 to 65535TC515

TC514

TC513

TC512

TC511

TC510

TC59

TC58

TC57

TC56

TC55

TC54

TC53

TC52

TC51

TC50

16-bit timer 5 counter data

TC515 = MSB

TC50 = LSB

R00481AC

(HW)

16-bit timer 5

counter data

–

SELFM5

SELCRB5

OUTINV5

CKSL5

PTM5

PRESET5

PRUN5

reserved

16-bit timer 5 fine mode selection

16-bit timer 5 comparison buffer

16-bit timer 5 output inversion

16-bit timer 5 input clock selection

16-bit timer 5 clock output control

16-bit timer 5 reset

16-bit timer 5 Run/Stop control

–

R/W

0 when being read.

00481AE

(B) –

1 Enabled 0 Disabled

1 Fine mode 0 Normal

1 Invert 0 Normal

External clock

Internal clock

1 On 0 Off

1 Reset 0 Invalid

1 Run 0 Stop

16-bit timer 5

control register

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-19

CFP16–CFP10: P1[6:0] pin function selection (D[6:0]) / P1 function select register (0x402D4)

Selects the pin to be used for input of an external count clock to the timer.

Write "1": Clock input pin

Write "0": I/O port pin

Read: Valid

Select clock input pins for the timers that are used as an event counter from among P10 through P16, by writing "1" to

CFP10–CFP16. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for an I/O port by

writing "0" to CFP1x.

In addition to pin selection here, the pin to be used for clock input to the 16-bit programmable timer must be set to

input mode using the I/O control register.

At cold start, CFP1x is set to "0" (I/O port). A t hot start, CFP1x retains its status from prior to the initial reset.

CFP27–CFP22: P2[7:2] pin function selection (D[7:2]) / P2 function select register (0x402D8)

Selects the pin used for clock output.

Write "1": Clock output pin

Write "0": I/O port pin

Read: Valid

Select the pin to be used to output a timer-generated clock to external devices from among P22 through P27, by

writing "1" to CFP22– CFP27. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for

an I/O port by writing "0" to CFP2x.

At cold start, CFP2x is set to "0" (I/O port). At hot start, CFP2x retains its status from prior to the initial reset.

CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF)

CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF)

Sets whether the function of an I/O-port pin is to be extended.

Write "1": Function-extended pin

Write "0": I/O-port/peripheral-circuit pin

Read: Valid

When CFEX[1:0] is set to "1", the P14–P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the

CFP1[4:0] bit becomes effective, so the settings of these bits determine whether the P14– P10 ports function as I/O

port s or external clock input ports.

At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to

the initial reset.

IOC16–IOC10: P1[6:0] port I/O control (D[6:0]) / P1 I/O control register (0x402D6)

Directs P10 through P16 for input or output.

Write "1": Output mode

Write "0": Input mode

Read: Valid

For the pin selected from among P10 through P16 for use for external clock input, write "0" to the corresponding I/O

control bit to set it to input mode . If the pin is set to output mode, even though its CFP1x may be set to "1", it

functions as the output pin of an 8-bit programmable timer and cannot be used to receive an external clock.

At cold start, all IOC1x is set to "0" (input mode). At hot s tart, IOC1x retains its state from prior to the initial reset.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-20 EPSON S1C33209/221/ 222 FUNCTION PART

SELFM0: Timer 0 fine mode selection (D6) / 16-bit timer 0 control register (0x48186)

SELFM1: Timer 1 fine mode selection (D6) / 16-bit timer 1 control register (0x4818E)

SELFM2: Timer 2 fine mode selection (D6) / 16-bit timer 2 control register (0x48196)

SELFM3: Timer 3 fine mode selection (D6) / 16-bit timer 3 control register (0x4819E)

SELFM4: Timer 4 fine mode selection (D6) / 16-bit timer 4 control register (0x481A6)

SELFM5: Timer 5 fine mode selection (D6) / 16-bit timer 5 control register (0x481AE)

Sets fine mode for clock output.

Write "1": Fine mode

Write "0": Normal output

Read: Valid

When SELFMx is set to "1", clock output is set in fine mode which allows adjustment of the output signal duty ratio

in units of a half cycle for the input clock.

When SELFMx is set to "0", normal clock output will be performed.

At initial reset, SELCFMx is set to "0" (normal output).

SELCRB0: Timer 0 comparison register buffer enable (D5) / 16-bit timer 0 control register (0x48186)

SELCRB1: Timer 1 comparison register buffer enable (D5) / 16-bit timer 1 control register (0x4818E)

SELCRB2: Timer 2 comparison register buffer enable (D5) / 16-bit timer 2 control register (0x48196)

SELCRB3: Timer 3 comparison register buffer enable (D5) / 16-bit timer 3 control register (0x4819E)

SELCRB4: Timer 4 comparison register buffer enable (D5) / 16-bit timer 4 control register (0x481A6)

SELCRB5: Timer 5 comparison register buffer enable (D5) / 16-bit timer 5 control register (0x481AE)

Enables or disables writing to the comparison register buffer.

Write "1": Enabled

Write "0": Disabled

Read: Valid

When SELCRBx is set to "1", comparison data is read and written from/to the comparison register buffer. The

content of the buffer is loaded to the comparison data register when the counter is reset by the software or the

comparison B signal.

When SELCRBx is set to "0", comparison data is read and written from/to the comparison data register.

At initial reset, SELCRBx is set to "0" (disabled).

OUTINV0: Timer 0 output inversion (D4) / 16-bit timer 0 control register (0x48186)

OUTINV1: Timer 1 output inversion (D4) / 16-bit timer 1 control register (0x4818E)

OUTINV2: Timer 2 output inversion (D4) / 16-bit timer 2 control register (0x48196)

OUTINV3: Timer 3 output inversion (D4) / 16-bit timer 3 control register (0x4819E)

OUTINV4: Timer 4 output inversion (D4) / 16-bit timer 4 control register (0x481A6)

OUTINV5: Timer 5 output inversion (D4) / 16-bit timer 5 control register (0x481AE)

Selects a logic of the output signal.

Write "1": Inverted (active low)

Write "0": Normal (active high)

Read: Valid

By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When

OUTINVx is set to "0", an active-high signal (off level = low) is generated.

At initial reset, OUTINVx is set to "0" (active high).

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-21

CKSL0: Timer 0 input clock selection (D3) / 16-bit timer 0 control register (0x48186)

CKSL1: Timer 1 input clock selection (D3) / 16-bit timer 1 control register (0x4818E)

CKSL2: Timer 2 input clock selection (D3) / 16-bit timer 2 control register (0x48196)

CKSL3: Timer 3 input clock selection (D3) / 16-bit timer 3 control register (0x4819E)

CKSL4: Timer 4 input clock selection (D3) / 16-bit timer 4 control register (0x481A6)

CKSL5: Timer 5 input clock selection (D3) / 16-bit timer 5 control register (0x481AE)

Selects the input clock of each timer.

Write "1": External clock

Write "0": Internal clock

Read: Valid

The internal clock (p rescaler output) is selected for the input clock of each timer by writing "0" to CKSLx. An

external clock (one that is fed from the clock input pin) is selected by writing "1", and the timer functions as an event

counter. In this case, the clock input pin must be set using CFP1x before an external clock is selected here.

At initial reset, CKSLx is set to "0" (internal clock).

PTM0: Timer 0 clock output control (D2) / 16-bit timer 0 control register (0x48186)

PTM1: Timer 1 clock output control (D2) / 16-bit timer 1 control register (0x4818E)

PTM2: Timer 2 clock output control (D2) / 16-bit timer 2 control register (0x48196)

PTM3: Timer 3 clock output control (D2) / 16-bit timer 3 control register (0x4819E)

PTM4: Timer 4 clock output control (D2) / 16-bit timer 4 control register (0x481A6)

PTM5: Timer 5 clock output control (D2) / 16-bit timer 5 control register (0x481AE)

Controls the output of the TMx signal (timer output clock).

Write "1": On

Write "0": Off

Read: Valid

The TMx signal is output from the clock output pin by writing "1" to PTMx. Clock output is stopped by writing "0"

to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high when

OUTINVx = "1"). In this case, the clock output pin must be set using CFP2x before outputting the TMx signal here.

At initial reset, PTMx is set to "0" (off).

PRESET0: Timer 0 reset (D1) / 16-bit timer 0 control register (0x48186)

PRESET1: Timer 1 reset (D1) / 16-bit timer 1 control register (0x4818E)

PRESET2: Timer 2 reset (D1) / 16-bit timer 2 control register (0x48196)

PRESET3: Timer 3 reset (D1) / 16-bit timer 3 control register (0x4819E)

PRESET4: Timer 4 reset (D1) / 16-bit timer 4 control register (0x481A6)

PRESET5: Timer 5 reset (D1) / 16-bit timer 5 control register (0x481AE)

Resets the counter.

Write "1": Reset

Write "0": Invalid

Read: Always "0"

The counter of timer x is reset by writing "1" to PRESETx.

Writing "0" results in No Operation.

Since PRESETx is a write-only bit, its content when read is alway s "0".

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-22 EPSON S1C33209/221/ 222 FUNCTION PART

PRUN0: Timer 0 RUN/STOP control (D0) / 16-bit timer 0 control register (0x48186)

PRUN1: Timer 1 RUN/STOP control (D0) / 16-bit timer 1 control register (0x4818E)

PRUN2: Timer 2 RUN/STOP control (D0) / 16-bit timer 2 control register (0x48196)

PRUN3: Timer 3 RUN/STOP control (D0) / 16-bit timer 3 control register (0x4819E)

PRUN4: Timer 4 RUN/STOP control (D0) / 16-bit timer 4 control register (0x481A6)

PRUN5: Timer 5 RUN/STOP control (D0) / 16-bit timer 5 control register (0x481AE)

Controls the timer's RUN/STOP state.

Write "1": RUN

Write "0": STOP

Read: Valid

Each timer is made to start counting up by writing "1" to PRUNx and made to stop counting by writing "0".

In the STOP state, the counter data is retained until the timer is reset or placed in a RUN state. By changing states

from STOP to RUN, the timer can restart counting beginning at the retained count.

At initial reset, PRUNx is set to "0" (STOP).

CR0A15–CR0A0: Timer 0 comparison data A (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180)

CR1A15–CR1A0: Timer 1 comparison data A (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188)

CR2A15–CR2A0: Timer 2 comparison data A (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190)

CR3A15–CR3A0: Timer 3 comparison data A (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198)

CR4A15–CR4A0: Timer 4 comparison data A (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0)

CR5A15–CR5A0: Timer 5 comparison data A (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8)

Sets the comparison data A of each timer.

When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register A.

When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer A. The

content of the buffer is loaded to the comparison data register A when the counter is reset.

The data set in this register is compared with each corresponding counter data. When the contents match, a

comparison A interrupt is generated and the output signal rises (OUTINVx = "0") or falls (OUTINVx = "1"). This

does not affect the counter value and count-up operation.

At initial reset, CRxA is not initialized.

CR0B15–CR0B0: Timer 0 comparison data B (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182)

CR1B15–CR1B0: Timer 1 comparison data B (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A)

CR2B15–CR2B0: Timer 2 comparison data B (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192)

CR3B15–CR3B0: Timer 3 comparison data B (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A)

CR4B15–CR4B0: Timer 4 comparison data B (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2)

CR5B15–CR5B0: Timer 5 comparison data B (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA)

Sets the comparison data B of each timer.

When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register B.

When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer B. The

content of the buffer is loaded to the comparison data register B when the counter is reset.

The data set in this register i s compared with each corresponding counter data. When the contents match, a

comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1").

Furthermore, the counter is reset to "0".

At initial reset, CRxB is not initialized.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-23

TC015–TC00: Timer 0 counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184)

TC115–TC10: Timer 1 counter data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C)

TC215–TC20: Timer 2 counter data (D[F:0]) / 16-bit timer 2 counter data register (0x48194)

TC315–TC30: Timer 3 counter data (D[F:0]) / 16-bit timer 3 counter data register (0x4819C)

TC415–TC40: Timer 4 counter data (D[F:0]) / 16-bit timer 4 counter data register (0x481A4)

TC515–TC50: Timer 5 counter data (D[F:0]) / 16-bit timer 5 counter data register (0x481AC)

The counter data of each timer can be read from this register.

The data can be read out at any time.

Since TCx is a read-only register, writing to this register is ignored.

At initial reset, TCx is not initialized.

P16T02–P16T00: Timer 0 interrupt level (D[2:0]) / 16-bit timer 0/1 interrupt priority register (0x40266)

P16T12–P16T10: Timer 1 interrupt level (D[6:4]) / 16-bit timer 0/1 interrupt priority register (0x40266)

P16T22–P16T20: Timer 2 interrupt level (D[2:0]) / 16-bit timer 2/3 interrupt priority register (0x40267)

P16T32–P16T30: Timer 3 interrupt level (D[6:4]) / 16-bit timer 2/3 interrupt priority register (0x40267)

P16T42–P16T40: Timer 4 interrupt level (D[2:0]) / 16-bit timer 4/5 interrupt priority register (0x40268)

P16T52–P16T50: Timer 5 interrupt level (D[6:4]) / 16-bit timer 4/5 interrupt priority register (0x40268)

Sets the priority levels of 16-bit programmable timer interrupts.

The priority level can be set in the range of 0 to 7.

At initial reset, P16Tx becomes indeterminate.

E16TU0, E16TC0: Timer 0 interrupt enable (D2, D3) / 16-bit timer 0/1 interrupt enable register (0x40272)

E16TU1, E16TC1: Timer 1 interrupt enable (D6, D7) / 16-bit timer 0/1 interrupt enable register (0x40272)

E16TU2, E16TC2: Timer 2 interrupt enable (D2, D3) / 16-bit timer 2/3 interrupt enable register (0x40273)

E16TU3, E16TC3: Timer 3 interrupt enable (D6, D7) / 16-bit timer 2/3 interrupt enable register (0x40273)

E16TU4, E16TC4: Timer 4 interrupt enable (D2, D 3) / 16-bit timer 4/5 interrupt enable register (0x40274)

E16TU5, E16TC5: Timer 5 interrupt enable (D6, D7) / 16-bit timer 4/5 interrupt enable register (0x40274)

Enables or disables the generation of an interrupt to the CPU.

Write "1": Interrupt enabled

Write "0": Interrupt disabled

Read: Valid

The E16TUx and E16TCx are provided for the comparison B and comparison A interrupt factors, respectively. The

interrupt for which the bit is set to "1" is enabled, and the interrupt for which the bit is set to "0" is disabled.

At initial reset, these bits are set to "0" (interrupt disabled).

F16TU0, F16TC0 : Timer 0 interrupt factor flag (D2, D3) / 16-bit timer 0/1 interrupt factor flag register (0x40282)

F16TU1, F16TC1 : Timer 1 interrupt factor flag (D6, D7) / 16-bit timer 0/1 interrupt factor flag register (0x40282)

F16TU2, F16TC2 : Timer 2 interrupt factor flag (D2, D3) / 16-bit timer 2/3 interrupt factor flag register (0x40283)

F16TU3, F16TC3 : Timer 3 interrupt factor flag (D6, D7) / 16-bit timer 2/3 interrupt factor flag register (0x40283)

F16TU4, F16TC4 : Timer 4 interrupt factor flag (D2, D3) / 16-bit timer 4/5 interrupt factor flag register (0x40284)

F16TU5, F16TC5 : Timer 5 interrupt factor flag (D6, D7) / 16-bit timer 4/5 interrupt factor flag register (0x40284)

Indicates the status of 16-bit programmable timer interrupt generation.

When read

Read "1": Interrupt factor has occurred

Read "0": No interrupt factor has occurred

When written using the reset-only method (default)

Write "1": Interrupt factor flag is reset

Write "0": Invalid

When written using the read/write method

Write "1": Interrupt flag is set

Write "0": Interrupt flag is reset

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-24 EPSON S1C33209/221/ 222 FUNCTION PART

F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A int errupts,

respectively. The flag is set to "1" when each interrupt factor occurs.

At this time, if the following conditions are met, an interrupt to the CPU is generated:

1. The corresponding interrupt enable register bit is set to "1".

2. No other interr upt request of a higher priority has been generated.

3. The PSR's IE bit is set to "1" (interrupts enabled).

4. The value set in the corresponding interrupt priority register is higher than the CPU's interrupt level (IL).

When using the interrupt factor of the 16-bit programmable timer to request IDMA, note that even when the above

conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If

interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data

transfer by IDMA is completed.

The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the

interrupt enable and interrupt priority registers are set.

If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be

reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level

indicated by the interrupt priority register, or by executing the reti instruction).

The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept

interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same

interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method

(RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used.

At initial reset, all these flags become indeterminate, so be sure to reset them in the software.

R16TU0, R16TC0 : Timer 0 IDMA request (D6, D7) /

Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290)

R16TU1, R16TC1 : Timer 1 IDMA request (D0, D1) / 16-bit timer 1–4 IDMA request register (0x40291)

R16TU2, R16TC2 : Timer 2 IDMA request (D2, D3) / 16-bit timer 1–4 IDMA request register (0x40291)

R16TU3, R16TC3 : Timer 3 IDMA request (D4, D5) / 16-bit timer 1–4 IDMA request register (0x40291)

R16TU4, R16TC4 : Timer 4 IDMA request (D6, D7) / 16-bit timer 1–4 IDMA request register (0x40291)

R16TU5, R16TC5 : Timer 5 IDMA request (D0, D1) /

16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)

Specifies whether to invoke IDMA when an interrupt factor occurs.

When using the set-only method (default)

Write "1": IDMA request

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA request

Write "0": Interrupt request

Read: Valid

R16TUx and R16TCx are IDMA request bits corresponding to the comparison B and comparison A interrupt factors,

respectively. When the bit is set to "1", IDMA is invoked when the interrupt factor occurs, thereby performing

programmed data transfers. When the register is set to "0", normal interrupt processing is performed and IDMA is

not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)".

At initial reset, these bits are set to "0" (interrupt request).

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

S1C33209/221/222 FUNCTION PART EPSON B-III-4-25

DE16TU0, DE16TC0 : Timer 0 IDMA enable (D6, D7) /

Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294)

DE16TU1, DE16TC1 : Timer 1 IDMA enable (D0, D1) / 16-bit timer 1–4 IDMA enable register (0x40295)

DE16TU2, DE16TC2 : Timer 2 IDMA enable (D2, D3) / 16-bit timer 1–4 IDMA enable register (0x40295)

DE16TU3, DE16TC3 : Timer 3 IDMA enable (D4, D5) / 16-bit timer 1–4 IDMA enable register (0x40295)

DE16TU4, DE16TC4 : Timer 4 IDMA enable (D6, D7) / 16-bit timer 1–4 IDMA enable register (0x40295)

DE16TU5, DE16TC5 : Timer 5 IDMA enable (D0, D1) /

16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

Enables IDMA transfer by means of an interrupt factor.

When using the set-only method (default)

Write "1": IDMA enabled

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA enabled

Write "0": IDMA disabled

Read: Valid

DE16TUx and DE16TCx are IDMA enable bits corresponding to the comparison B and comparison A interrupt

factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0",

the IDMA request is disabled.

After an initial reset, these bits are set to "0" (IDMA disabled).

Programming Notes

(1) The 16-bit programmable timers clocked by the internal clock operate only when the prescaler is operating.

(2) When setting the input clock or operation mode, make sure the 16-bit programmable timer is turned off.

(3) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal.

Therefore, do not set the comparison registers as A = B.

There is no problem when the interrupt function only is used.

(4) When using the output clock, set the comparison data registers as A ≥ 0 and B ≥ 1. The minimum settings are A

= 0 and B = 1. In this case, the timer output clock cycle is the input clock × 1/2.

(5) When the comparison data registers are set as A > B in normal mode, no comparison A interrupt is generated.

In this case, the output signal is fixed at the off level.

In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A > 2 × B +

(6) After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted

interrupt or IDMA request, be sure to reset thi s flag and register in the software.

(7) To prevent another interrupt from being generated by the same factor after an interrupt has occurred, be sure to

reset the interrupt factor flag before setting the PSR again or executing the reti instruction.

(8) Be aware that unnecessary pulse may be generated according to the control of the clock output and port

configuration when a 16-bit programmable timer is used to output the TMx clock.

For example, when TMx is set as inverted output (OUTINVx = "1"), the output waveform falls with the

comparison B signal and it rises with the comparison A signal. Furthermore, the output pin is fixed at high level

when PTMx is set to "0" to stop the clock output. When switching the output pin to the I/O port pin and then

setting the port to low after the TMx signal falls with the comparison A signal, a high level pulse will be

generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx

after setting the port to low.

III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

B-III-4-26 EPSON S1C33209/221/ 222 FUNCTION PART

THIS PAGE IS BLANK.

III PERIPHERAL BLOCK: WATCHDOG TIMER

S1C33209/221/222 FUNCTION PART EPSON B-III-5-1

III-5 WATCHDOG TIMER

Configuration of Watchdog Timer

The Periheral Block incorporates a watchdog timer function to detect the CPU's crash.

This function is implemented through the use of the 16-bit programmable timer 0. When this function is enabled, an

NMI (nonmaskable interrupt) is generated by the comparison B signal from the 16-bit programmable timer 0

(generating intervals can be set through the use of software). The 16-bit programmable timer 0 set in the software so

as not to generate the NMI, making it possible to detect a program crash that may not pass through this processing

routine.

Figure 5.1 shows the block diagram of the watchdog timer.

Clock Generator 16-bit

programmable timer 0

Prescaler NMI

Watchdog timer

EWD

Figure 5.1 Watchdog Timer Block Diagram

Control of Watchdog Timer

Setting the operating clock and NMI generating interval

The watchdog timer is operated by the prescaler's output clock. Therefore, the watchdog timer function

cannot be used when the prescaler is inactive.

The NMI is generated every time the 16-bit programmable timer 0 is reset by the comparison B setting.

Therefore, this interval is determined by the prescaler's P16TS0[2:0] (D[2:0]) / 16-bit timer 0 clock control

B (0x48182).

The NMI generating interval is calculated using the following equation:

NMI generating interval = CR0B + 1 [sec.]

fPSCIN × pdr

fPSCIN: Prescaler input clock frequency [Hz]

pdr: Prescaler's division ratio set by the P16TS0 register (1/4096, 1/1024, 1/256, 1/64, 1/16, 1/4, 1/2, 1/1)

CR0B: Set value of the CR0B register (0 to 65,535)

For details on how to control the prescaler and the 16-bit programmable timer 0, refer to "Prescaler" and "16-

Bit Programmable Timers".

Setting the watchdog timer function

To use the watchdog timer function, enable the NMI that is generated by the comparison B signal from the

16-bit programmable timer 0. For this purpose, use EWD (D1) / Watchdog timer enable register (0x40171).

The NMI is enabled by writing "1" to EWD. At initial reset, EWD is set to "0", so generation of the NMI is

disabled.

To prevent an unwanted NMI from being generated by erroneous writing to EWD, this register is normally

write-protected. To write-enable EWD, write "1" to WRWD (D7) / Watchdog timer write-protect register

(0x40170). Onl y one writing to EWD is enabled in this way by the WRWD bit. When data is written to EWD

after it is write-enabled, the WRWD bit is reset back to "0", thus making EWD write-protected again.

For the 16-bit programmable timer 0, set an appropriate compari son B value to make it start operating.

If the watchdog timer function is not to be used, set EWD to "0" and do not change it.

III PERIPHERAL BLOCK: WATCHDOG TIMER

B-III-5-2 EPSON S1C33209/221/222 FUNCTION PART

Resetting the watchdog timer

When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is

generated in a location where it will be periodically processed. Make sure this routine is processed within the

NMI generation interval described above.

The 16-bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register

(0x48186). At this point, the timer counter is set to 0, and the timer starts counting the NMI generation interval

over again from that point.

If the watchdog timer is not reset within the set interval for any reason, the CPU is made t o enter trap

processing by an NMI and starts executing the processing routine indicated by the NMI vector.

The NMI trap vector address is set to 0x0C0001C

The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).

Operation in Standby Modes

During HALT mode

In HALT mode (basic mode or HALT2 mode), the prescaler and watchdog timer are operating. Consequently,

if HALT mode continues beyond the NMI generation interval, HALT mode is cleared by the NMI.

To disable the wa tchdog timer in HALT mode, set EWD to "0" before executing the halt instruction or turn off

the 16-bit programmable timer 0.

If the NMI is disabled by EWD, the 16-bit programmable timer 0 continues counting even in HALT mode. To

reenable the NMI after cl earing HALT mode, reset the 16-bit programmable timer 0 in advance.

If HALT mode was entered after the 16-bit programmable timer 0 was turned off, reset the timer before

restarting it.

During SLEEP mode

In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent

generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before

executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary.

III PERIPHERAL BLOCK: WATCHDOG TIMER

S1C33209/221/222 FUNCTION PART EPSON B-III-5-3

I/O Memory of Watchdog Timer

Table 5.1 shows the control bits of the watchdog timer.

Table 5.1 Control Bits of Watchdog Timer

NameAddressRegister name Bit Function Setting Init. R/W Remarks

WRWD

–

D6–0 EWD write protection

–0

–R/W

–0 when being read.

0040170

(B) –

Write enabled

Write-protect

Watchdog

timer write-

protect register

–

EWD

–

D7–2

–

Watchdog timer enable

–

R/W

–

0 when being read.

0040171

(B) 1

NMI enabled

NMI disabled

Watchdog

timer enable

WRWD: EWD write protection (D7) / Watchdog timer write-protect register (0x40170)

Enables writing to the EWD register.

Write "1": Writing enabled

Write "0": Write-protected

Read: Valid

The EWD bit is write-protected to prevent unwanted modifications. Writing to this bit is enabled for only one

writing by setting WRWD to "1". WRWD is reset back to "0" by writing to EWD, so EWD is write-protected again.

If WRWD is reset to "0" when EWD is write-enabled (WRWD = "1"), EWD becomes write-protected again.

At initial reset, WRWD is set to "0" (write-protected).

EWD: NMI enable (D1) / Watchdog timer enable register (0x40171)

Controls the generation of a nonmaskable interrupt (NMI) by the watchdog timer.

Write "1": NMI is enabled

Write "0": NMI is disabled

Read: Valid

The watchdog timer's interrupt signal is masked by writing "0" to EWD, so a nonmaskable interrupt (NMI) to the

CPU is not generated. If EWD is set to "1", an NMI is generated by the 16-bit programmable timer 0 comparison B

signal.

Writing to EWD is valid only when WRWD = "1".

Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has

been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting the EWD register back to

"1".

At initial rese t, EWD is set to "0" (NMI disabled).

Programming Notes

(1) If the watchdog timer's NMI is enabled, the watchdog timer must be reset in the software before the 16-bit

programmable timer 0 outputs the comparison B signal.

(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI

has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to

"1".

III PERIPHERAL BLOCK: WATCHDOG TIMER

B-III-5-4 EPSON S1C33209/221/222 FUNCTION PART

THIS PAGE IS BLANK.

III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT

S1C33209/221/222 FUNCTION PART EPSON B-III-6-1

III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT

Configuration of Low-Speed (OSC1) Oscillation Circuit

The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit.

The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock.

The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as the

source clock for t he clock timer. It can also be used as a sub-clock for the low-speed (low-power) operation of the CPU

and peripheral circuits (switchable in a program).

Figure 6.1 shows the configuration of the clock system.

Clock

switch

CLKCHG

To CPU

and BCU

OSC3/PLL

clock

To peripheral

circuits

Low-speed (OSC1)

oscillation circuit

SOSC1

PF1ON

Oscillation

ON/OFF

OSC1

OSC2

I/O port Prescaler

Clock timer

FOSC1

(P14)

CLG

Figure 6.1 Configuration of Clock System

The CPU operating clock can be switched to the output (OSC1 clock) of the low-speed (OSC1) oscillation circuit in

a program. Furthermore, the oscillation circuit can be s topped in a program.

If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation of

the CPU/peripheral circuits and turn off the high-speed (OSC3) oscillation circuit in order to reduce current

consumption.

The low-speed (OSC1) oscillation circuit does not stop in SLEEP mode.

For the control method when using the OSC1 clock for the operating clock of the peripheral circuits, refer to

"Prescaler".

I/O Pins of Low-Speed (OSC1) Oscillation Circuit

Table 6.1 lists the I/O pins of the low-speed (OSC1) oscillation circuit.

Table 6.1 I/O Pins of Low-Speed (OSC1) Oscillation Circuit

Pin name I/O Function

OSC1 I Low-speed (OS C1) oscillation input pin

Crystal oscillation or external clock input

OSC2 O Low-speed (OSC1) oscillation output pin

Crystal oscillation (open when external clock is used)

P14/FOSC1/DCLK I/O I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output

III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT

B-III-6-2 EPSON S1C33209/221/222 FUNCTION PART

Oscillator Types

In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as the

type of oscillation circuit.

Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit.

OSC2

OSC1

Oscillation circuit

control signal Oscillation circuit

control signal

X'tal1

OSC1

OSC2

OSC1

External

clock

N.C.

DD f

OSC1

(1) Crystal oscillation circuit

OSC2

OSC1

Oscillation circuit

control signal

Low level

(

)

When not used

(2) External clock input

Figure 6.2 Low-Speed (OSC1) Oscillation Circuit

When using a crystal oscillation for this circuit, connect a crystal resonator X'tal1 (32.768 kHz, Typ.) and feedback

resistor (Rf) between the OSC1 and OSC2 pins, and two capacitors (CG1, CD1) between the OSC1 pin and V SS and

the OSC2 pin and V SS, respectively.

When an external clock source is used, leave the OSC2 pin open and input a square-wave clock to the OSC1 pin .

If the low-speed (OSC1) oscillation circuit is not used, connect the OSC1 pin to VSS and leave the OSC2 pin open.

The oscillation frequency is 32.768 kHz (Typ.). Use a crystal resonator or external clock that oscillates at this

frequency. No other frequency can be used for clock applications.

For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical

Characteristics".

III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT

S1C33209/221/222 FUNCTION PART EPSON B-III-6-3

Controlling Oscillation

The low-speed (OSC1) oscillation circuit can be turned on or off using SOSC1 (D0) / Power control register

(0x40180).

The oscillation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing "1". SOSC1 is set

to "1" at initial reset, so the oscillation circuit is turned on.

Notes: • When the low-speed (OSC1) oscillation circuit is used as the clock source for the CPU operating

clock, it cannot be turned off. In this case, writing "0" to SOSC1 is ignored. Note also that writing

to SOSC1 is allowed only when the power-control register protection flag is set to "0b10010110".

• Immediately after the oscillation circuit is turned on, a certain period of time is required for

oscillation to stabilize (3 sec max.). To prevent the device from operating erratically, do not use

the clock until its oscillation has stabilized.

The low-speed (OSC1) oscillation circuit does not stop when the CPU is set in SLEEP mode.

Switching Over the CPU Operating Clock

After an initial reset, the CPU starts operating using the OSC3 clock.

In cases in which some peripheral circuits (e.g., programmable timer, serial interface, and A/D converter) that are

clocked by the OSC3 clock do not need to be operate and the CPU can process its jobs at a low clock speed, the CPU

operating clock can be switched to the OSC1 clock, thereby reducing current consumption. Use CLKCHG (D2) /

Power control register (0x40180) to switch over the operating clock.