CD4093BMJ - National Semiconductor

TL/F/5982

CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger

February 1993

CD4093BM/CD4093BC Quad

2-Input NAND Schmitt Trigger

General Description

The CD4093B consists of four Schmitt-trigger circuits. Each

circuit functions as a 2-input NAND gate with Schmitt-trigger

action on both inputs. The gate switches at different points

for positive and negative-going signals. The difference be-

tween the positive (VTa) and the negative voltage (VTb)is

defined as hysteresis voltage (VH).

All outputs have equal source and sink currents and con-

form to standard B-series output drive (see Static Electrical

Characteristics).

Features

YWide supply voltage range 3.0V to 15V

YSchmitt-trigger on each input

with no external components

YNoise immunity greater than 50%

YEqual source and sink currents

YNo limit on input rise and fall time

YStandard B-series output drive

YHysteresis voltage (any input) TAe25§C

Typical VDD e5.0V VHe1.5V

VDD e10V VHe2.2V

VDD e15V VHe2.7V

Guaranteed VHe0.1 VDD

Applications

YWave and pulse shapers

YHigh-noise-environment systems

YMonostable multivibrators

YAstable multivibrators

YNAND logic

Connection Diagram

Dual-In-Line Package

TL/F/5982–1

Top View

Order Number CD4093B

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)b0.5 to a18 VDC

Input Voltage (VIN)b0.5 to VDD a0.5 VDC

Storage Temperature Range (TS)b65§Ctoa

150§C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD) 3 to 15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)

CD4093BM b55§Ctoa

125§C

CD4093BC b40§Ctoa

85§C

DC Electrical Characteristics CD4093BM (Note 2)

Symbol Parameter Conditions b55§Ca25§Ca125§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD e5V 0.25 0.25 7.5 mA

Current VDD e10V 0.5 0.5 15.0 mA

VDD e15V 1.0 1.0 30.0 mA

VOL Low Level VIN eVDD,

k1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level VIN eVSS,

k1mA

Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VTbNegative-Going Threshold

k1mA

Voltage (Any Input) VDD e5V, VOe4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V

VDD e10V, VOe9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V

VDD e15V, VOe13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V

VTaPositive-Going Threshold

k1mA

Voltage (Any Input) VDD e5V, VOe0.5V 2.75 3.65 2.75 3.3 3.5 2.65 3.5 V

VDD e10V, VOe1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V

VDD e15V, VOe1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V

VHHysteresis (VTabVTb)V

DD e5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V

(Any Input) VDD e10V 1.0 4.30 1.0 2.2 4.0 0.70 4.0 V

VDD e15V 1.5 6.30 1.5 2.7 6.0 1.20 6.0 V

IOL Low Level Output VIN eVDD

Current (Note 3) VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA

VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA

VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA

IOH High Level Output VIN eVSS

Current (Note 3) VDD e5V, VOe4.6V b0.64 0.51 b0.88 b0.36 mA

VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA

VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA

VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

DC Electrical Characteristics CD4093BC (Note 2)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD e5V 1.0 1.0 7.5 mA

Current VDD e10V 2.0 2.0 15.0 mA

VDD e15V 4.0 4.0 30.0 mA

VOL Low Level VIN eVDD,

k1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level VIN eVSS,

k1mA

Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VTbNegative-Going Threshold

k1mA

Voltage (Any Input) VDD e5V, VOe4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 V

VDD e10V, VOe9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65 V

VDD e15V, VOe13.5V 4.35 6.75 4.5 6.3 6.75 4.5 6.9 V

VTaPositive-Going Threshold

k1mA

Voltage (Any Input) VDD e5V, VOe0.5V 2.75 3.6 2.75 3.3 3.5 2.65 3.5 V

VDD e10V, VOe1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0 V

VDD e15V, VOe1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5 V

VHHysteresis (VTabVTb)V

DD e5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V

(Any Input) VDD e10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0 V

VDD e15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0 V

IOL Low Level Output VIN eVDD

Current (Note 3) VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA

VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA

VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output VIN eVSS

Current (Note 3) VDD e5V, VOe4.6V b0.52 0.44 b0.88 b0.36 mA

VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA

VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.3 b10b5b0.3 b1.0 mA

VDD e15V, VIN e15V 0.3 10b50.3 1.0 mA

AC Electrical Characteristics*

TAe25§C, CLe50 pF, RLe200k, Input tr,t

fe20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL,t

PLH Propagation Delay Time VDD e5V 300 450 ns

VDD e10V 120 210 ns

VDD e15V 80 160 ns

tTHL,t

TLH Transition Time VDD e5V 90 145 ns

VDD e10V 50 75 ns

VDD e15V 40 60 ns

CIN Input Capacitance (Any Input) 5.0 7.5 pF

CPD Power Dissipation Capacitance (Per Gate) 24 pF

*AC Parameters are guaranteed by DC correlated testing.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

Typical Applications

Gated Oscillator

TL/F/5982–2

Assume t1at2ll tPHL atPLH then:

t0eRC ﬁn[VDD/VTb]

t1eRC ﬁn[(VDD bVTb)/(VDD bVTa)]

t2eRC ﬁn[VTa/VTb]

fe1

t1at2

RC ﬁn(VTa)(V

DD bVTb)

(VTb)(VDD bVTa)

TL/F/5982–3

Gated One-Shot

TL/F/5982–4

TL/F/5982–5

(a) Negative-Edge Triggered

TL/F/5982–6

TL/F/5982–7

(b) Positive-Edge Triggered

Typical Performance Characteristics

Typical Transfer

Characteristics

TL/F/5982–8

Guaranteed Hysteresis vs VDD

TL/F/5982–9

Guaranteed Trigger Threshold

Voltage vs VDD

TL/F/5982–10

Guaranteed Hysteresis vs VDD

TL/F/5982–11

Input and Output Characteristics

TL/F/5982–12

Output Characteristic Input Characteristic

TL/F/5982–13

VNML eVIH(MIN) bVOL jVIH(MIN) eVTa(MIN)

VNMH eVOH bVIL(MAX) jVDD bVIL(MAX) eVDD bVTb(MAX)

AC Test Circuits and Switching Time Waveforms

TL/F/5982–14

TL/F/5982–15

CD4093BM/CD4093BC Quad 2-Input NAND Schmitt Trigger

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4093BMJ or CD4093BCJ

NS Package Number J14A

Molded Dual-In-Line Package (N)

Order Number CD4093BM or CD4093BCN

NS Package Number N14A

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