General Description
The MAX5054–MAX5057 dual, high-speed MOSFET
drivers source and sink up to 4A peak current. These
devices feature a fast 20ns propagation delay and 20ns
rise and fall times while driving a 5000pF capacitive
load. Propagation delay time is minimized and matched
between the inverting and noninverting inputs and
between channels. High sourcing/sinking peak cur-
rents, low propagation delay, and thermally enhanced
packages make the MAX5054–MAX5057 ideal for high-
frequency and high-power circuits.
The MAX5054–MAX5057 operate from a 4V to 15V single
power supply and consume 40µA (typ) of supply current
when not switching. These devices have internal logic
circuitry that prevents shoot-through during output state
changes to minimize the operating current at high
switching frequency. The logic inputs are protected
against voltage spikes up to +18V, regardless of the VDD
voltage. The MAX5054A is the only version that has
CMOS input logic levels while the MAX5054B/MAX5055/
MAX5056/MAX5057 have TTL input logic levels.
The MAX5055–MAX5057 provide the combination of dual
inverting, dual noninverting, and inverting/noninverting
input drivers. The MAX5054 feature both inverting and
noninverting inputs per driver for greater flexibility. They
are available in 8-pin TDFN (3mm x 3mm), standard SO,
and thermally enhanced SO packages. These devices
operate over the automotive temperature range of -40°C
to +125°C.
Applications
Power MOSFET Switching Motor Control
Switch-Mode Power Supplies Power-Supply Modules
DC-DC Converters
Features
o4V to 15V Single Power Supply
o4A Peak Source/Sink Drive Current
o20ns (typ) Propagation Delay
oMatching Delay Between Inverting and
Noninverting Inputs
oMatching Propagation Delay Between Two
Channels
oVDD / 2 CMOS Logic Inputs (MAX5054AATA)
oTTL Logic Inputs
(MAX5054B/MAX5055/MAX5056/MAX5057)
o0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input
Hysteresis
oUp to +18V Logic Inputs (Regardless of VDD
Voltage)
oLow Input Capacitance: 2.5pF (typ)
o40µA (typ) Quiescent Current
o-40°C to +125°C Operating Temperature Range
o8-Pin TDFN and SO Packages
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
MAX5054
INA+
INA-
INB+
INB-
OUTB
OUTA
VDD
GND
PWM IN
VOUT
VIN
Typical Operating Circuit
19-3348; Rev 3; 3/11
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*
EP = Exposed pad.
/V
Denotes an automotive qualified part.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
MAX5054AATA+ -40°C to +125°C 8 TDFN-EP* AGS
MAX5054AATA/V+ -40°C to +125°C 8 TDFN-EP* BMF
MAX5054BATA+ -40°C to +125°C 8 TDFN-EP* AGR
MAX5055AASA+ -40°C to +125°C 8 SO-EP*
MAX5055BASA+ -40°C to +125°C 8 SO
MAX5056AASA+ -40°C to +125°C 8 SO-EP*
MAX5056BASA+ -40°C to +125°C 8 SO
MAX5057AASA+ -40°C to +125°C 8 SO-EP*
MAX5057BASA+ -40°C to +125°C 8 SO
Selector Guide and Pin Configurations appear at end of
data sheet.
4A, 20ns, Dual MOSFET Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 4V to 15V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND.)
VDD...............................................................................-0.3V to +18V
INA+, INA-, INB+, INB- ...............................................-0.3V to +18V
OUTA, OUTB...................................................-0.3V to (VDD + 0.3V)
OUTA, OUTB Short-Circuit Duration ........................................10ms
Continuous Source/Sink Current at OUT_ (PD< PDMAX) .....200mA
Continuous Power Dissipation (TA= +70°C)
8-Pin TDFN-EP (derate 18.2mW/°C above +70°C)........1454mW
8-Pin SO-EP (derate 19.2mW/°C above +70°C)… ........1538mW
8-Pin SO (derate 5.9mW/°C above +70°C)… ..................471mW
Operating Temperature Range..............................-40°C to +125°C
Storage Temperature Range .................................-65°C to +150°C
Junction Temperature ...........................................................+150°C
Lead Temperature (soldering, 10s)......................................+300°C
Soldering Temperature (reflow)............................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
MAX5054–MAX5057
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
VDD Operating Range VDD 415V
VDD Undervoltage Lockout UVLO VDD rising 3.00 3.50 3.85 V
VDD Undervoltage Lockout
Hysteresis 200 mV
VDD Undervoltage Lockout to
Output Delay VDD rising 12 µs
VDD = 4V 28 55
IDD
INA- = INB- = VDD,
INA+ = INB+ = 0V
(not switching) VDD = 15V 40 75
µA
VDD Supply Current
IDD-SW
INA- = 0V, INB+ = VDD = 15V,
INA+ = INB- both channels switching at
250kHz, CL = 0F
1 2.4 4 mA
DRIVER OUTPUT (SINK)
TA = +25°C 1.1 1.8
VDD = 15V,
IOUT_ = -100mA TA = +125°C 1.5 2.4
TA = +25°C 2.2 3.3
Driver Output Resistance Pulling
Down RON-N VDD = 4.5V,
IOUT_ = -100mA TA = +125°C 3.0 4.5
Peak Output Current (Sinking) IPK-N VDD = 15V, CL = 10,000pF 4 A
VDD = 4.5V 0.45
Output-Voltage Low IOUT_ = -100mA VDD = 15V 0.24 V
Latchup Protection ILUP Reverse current IOUT_ (Note 2) 400 mA
8 TDFN-EP
Junction-to-Ambient Thermal Resistance (θJA)...............+41°C/W
Junction-to-Case Thermal Resistance (θJC)......................+8°C/W
8 SO
Junction-to-Ambient Thermal Resistance (θJA)................+132°C/W
Junction-to-Case Thermal Resistance (θJC).......................+40°C/W
8 SO-EP
Junction-to-Ambient Thermal Resistance (θJA)..................+41°C/W
Junction-to-Case Thermal Resistance (θJC)......................+7°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRIVER OUTPUT (SOURCE)
TA = +25°C 1.5 2.1
VDD = 15V,
IOUT_ = 100mA TA = +125°C 1.9 2.75
TA = +25°C 2.75 4
Driver Output Resistance Pulling
Up RON-P VDD = 4.5V,
IOUT_ = 100mA TA = +125°C 3.75 5.5
Peak Output Current (Sourcing) IPK-P VDD = 15V, CL = 10,000pF 4 A
VDD = 4.5V VDD -
0.55
Output-Voltage High IOUT_ = 100mA
VDD = 15V VDD -
0.275
V
LOGIC INPUT (Note 4)
MAX5054A 0.7 x
VDD
Logic 1 Input Voltage VIH MAX5054B/MAX5055/MAX5056/MAX5057
(Note 5) 2.1
V
MAX5054A 0.3 x
VDDLogic 0 Input Voltage VIL
MAX5054B/MAX5055/MAX5056/MAX5057 0.8
V
MAX5054A 0.1 x
VDDLogic-Input Hysteresis VHYS
MAX5054B/MAX5055/MAX5056/MAX5057 0.3
V
Logic-Input-Current Leakage INA+, INB+, INA-, INB- = 0V or VDD -1 +0.1 +1 µA
Input Capacitance CIN 2.5 pF
SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1)
CL = 1000pF 4
CL = 5000pF 18
OUT_ Rise Time tR
CL = 10,000pF 32
ns
CL = 1000pF 4
CL = 5000pF 15OUT_ Fall Time tF
CL = 10,000pF 26
ns
Turn-On Delay Time tD-ON CL = 10,000pF (Note 3) 10 20 34 ns
Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 3) 10 20 34 ns
SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1)
CL = 1000pF 7
CL = 5000pF 37
OUT_ Rise Time tR
CL = 10,000pF 85
ns
CL = 1000pF 7
CL = 5000pF 30OUT_ Fall Time tF
CL = 10,000pF 75
ns
Turn-On Delay Time tD-ON CL = 10,000pF (Note 3) 18 35 70 ns
Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 3) 18 35 70 ns
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MATCHING CHARACTERISTICS
VDD = 15V, CL = 10,000pF 2
Mismatch Propagation Delays from
Inverting and Noninverting Inputs
to Output
tON-OFF
VDD = 4.5V, CL = 10,000pF 4
ns
VDD = 15V, CL = 10,000pF 1
Mismatch Propagation Delays
Between Channel A and Channel B tA-B VDD = 4.5V, CL = 10,000pF 2 ns
Note 2: All devices are 100% tested at TA= +25°C. Specifications over -40°C to +125°C are guaranteed by design.
Note 3: Limits are guaranteed by design, not production tested.
Note 4: The logic-input thresholds are tested at VDD = 4V and VDD = 15V.
Note 5: TTL compatible with reduced noise immunity.
RISE TIME vs. SUPPLY VOLTAGE
(CL = 5000pF)
MAX5054 toc01
SUPPLY VOLTAGE (V)
RISE TIME (ns)
14121086
10
20
30
40
50
60
0
416
TA = +125°C
TA = +25°C
TA = -40°C
FALL TIME vs. SUPPLY VOLTAGE
(CL = 5000pF)
MAX5054 toc02
TA = +125°C
TA = +25°C
TA = -40°C
FALL TIME (ns)
10
20
30
40
50
60
0
SUPPLY VOLTAGE (V)
14121086416
PROPAGATION DELAY TIME,
LOW-TO-HIGH vs. SUPPLY VOLTAGE
(CL = 5000pF)
MAX5054 toc03
TA = +125°C
TA = +25°C
TA = -40°C
PROPAGATION DELAY (ns)
10
20
30
40
50
60
0
SUPPLY VOLTAGE (V)
14121086416
MAX5054 toc04
PROPAGATION DELAY TIME,
HIGH-TO-LOW vs. SUPPLY VOLTAGE
(CL = 5000pF)
TA = +125°C
TA = +25°C
TA = -40°C
PROPAGATION DELAY (ns)
10
20
30
40
50
60
0
SUPPLY VOLTAGE (V)
14121086416
IDD-SW SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5054 toc05
SUPPLY VOLTAGE (V)
IDD-SW SUPPLY CURRENT (mA)
14121086
1
2
3
4
5
6
0
416
DUTY CYCLE = 50%
VDD = 15V, CL = 0
1 CHANNEL SWITCHING
1MHz
50kHz
100kHz
500kHz
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5054 toc06
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
14121086
10
20
30
40
50
60
70
80
90
100
0
416
DUTY CYCLE = 50%
VDD = 15V, CL = 4700pF
1 CHANNEL SWITCHING
1MHz
50kHz
100kHz
500kHz
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
_______________________________________________________________________________________
5
MAX5054 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
1007550250-25
1.5
2.0
2.5
3.0
3.5
4.0
1.0
-50 125
IDD-SW SUPPLY CURRENT
vs. TEMPERATURE
VDD = 15V,
f = 250kHz, CL = 0
DUTY CYCLE = 50%
BOTH CHANNELS SWITCHING
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX5054 toc08
SUPPLY VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
14121086
1
2
3
4
5
6
7
8
9
10
0
416
MAX5054AATA
(CMOS INPUT)
VIN RISING
VIN FALLING
MAX5054 toc09
SUPPLY VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
14121086
0.5
1.0
1.5
2.0
2.5
3.0
0
416
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
VIN RISING
VIN FALLING
TTL INPUT VERSIONS
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)
MAX5054 toc10
LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
1412108642
100
200
300
400
500
0
016
TTL INPUT VERSIONS
VDD = 15V
MAX5054 toc11
LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
1412108642
100
200
300
400
500
0
016
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)
TTL INPUT VERSIONS
VDD = 15V
MAX5054 toc12
LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
1412108642
1
2
3
4
5
0
016
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)
MAX5054AATA (CMOS INPUT)
VDD = 15V
MAX5054 toc13
LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
1412108642
1
2
3
4
5
0
016
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)
MAX5054AATA (CMOS INPUT)
VDD = +15V
DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE
MAX5054 toc14
TEMPERATURE (°C)
DELAY MISMATCH (ns)
1007550250-25
-4
-2
0
2
4
6
-6
-50 125
OUTPUT FALLING
OUTPUT RISING
MAX5054AATA (CMOS INPUT)
VDD = 4.5V, CL = 10,000pF
MAX5054 toc15
TEMPERATURE (°C)
DELAY MISMATCH (ns)
1007550250-25
-4
-2
0
2
4
6
-6
-50 125
DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE
OUTPUT FALLING
OUTPUT RISING
MAX5054AATA (CMOS INPUT)
VDD = 15V, CL = 10,000pF
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5054 toc16
TEMPERATURE (°C)
DELAY MISMATCH (ns)
10075-25 0 25 50
-3
-2
-1
0
1
2
3
4
-4
-50 125
DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE
VDD = 4.5V, CL = 10,000pF
OUTPUT RISING
OUTPUT FALLING
MAX5054 toc17
TEMPERATURE (°C)
DELAY MISMATCH (ns)
10075-25 0 25 50
-3
-2
-1
0
1
2
3
4
-4
-50 125
DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE
VDD = 15V, CL = 10,000pF
OUTPUT RISING
OUTPUT FALLING
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 5000pF)
MAX5054 toc18
IN_-
2V/div
20ns/div
OUT_
2V/div
MAX5055 (TTL INPUT)
MAX5054 toc19
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 10,000pF)
IN_-
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
MAX5054 toc20
20ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 5000pF)
IN_-
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
MAX5054 toc21
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 4V, CL = 10,000pF)
IN_-
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
_______________________________________________________________________________________
7
MAX5054 toc22
20ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 5000pF)
IN_-
2V/div
OUT_
5V/div
MAX5055
MAX5054 toc23
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 10,000pF)
IN_-
2V/div
OUT_
5V/div
MAX5055
MAX5054 toc24
20ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 5000pF)
IN_-
2V/div
OUT_
5V/div
MAX5055
MAX5054 toc25
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(VDD = 15V, CL = 10,000pF)
MAX5055
IN_-
2V/div
OUT_
5V/div
VDD vs. OUTPUT VOLTAGE
MAX5054 toc26
2ms/div
MAX5055
INA- = INB- = GND
CLA = CLB = 10,000pF
VDD
5V/div
OUTB
5V/div
OUTA
5V/div
MAX5054 toc27
2ms/div
VDD vs. OUTPUT VOLTAGE
MAX5055
INA- = INB- = GND
CLA = CLB = 10,000pF
VDD
5V/div
OUTB
5V/div
OUTA
5V/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
8 _______________________________________________________________________________________
Pin Descriptions
PIN NAME FUNCTION
1 INA- Inverting Logic-Input Terminal for Driver A. Connect to GND when not used.
2 INB- Inverting Logic-Input Terminal for Driver B. Connect to GND when not used.
3 GND Ground
4 OUTB Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off.
5V
DD Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors.
6 OUTA Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off.
7 INB+ Noninverting Logic-Input Terminal for Driver B. Connect to VDD when not used.
8 INA+ Noninverting Logic-Input Terminal for Driver A. Connect to VDD when not used.
—EP
Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical
ground connection.
PIN
MAX5055 MAX5056 MAX5057 NAME FUNCTION
1, 8 1, 8 1, 8 N.C. No Connection. Not internally connected.
2 2 INA- Inverting Logic-Input Terminal for Driver A. Connect to GND if not used.
3 3 3 GND Ground
4 INB- Inverting Logic-Input Terminal for Driver B. Connect to GND if not used.
5 5 5 OUTB Driver B Output. Sources or sinks current for channel B to turn the external
MOSFET on or off.
666V
DD Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors.
7 7 7 OUTA Driver A Output. Sources or sinks current for channel A to turn the external
MOSFET on or off.
4 4 INB+ Noninverting Logic-Input Terminal for Driver B. Connect to VDD if not used.
2 INA+ Noninverting Logic-Input Terminal for Driver A. Connect to VDD if not used.
——EP
Exposed Pad. Internally connected to GND. Do not use the exposed pad as
the only electrical ground connection.
MAX5054
MAX5055/MAX5056/MAX5057
Detailed Description
VDD Undervoltage Lockout (UVLO)
The MAX5054–MAX5057 have internal undervoltage
lockout for VDD. When VDD is below the UVLO thresh-
old, OUT_ is low, independent of the state of the inputs.
The undervoltage lockout is typically 3.5V with 200mV
typical hysteresis to avoid chattering. When VDD rises
above the UVLO threshold, the outputs go high or low
depending upon the logic-input levels. Bypass VDD
using low-ESR ceramic capacitors for proper operation
(see the
Applications Information
section).
Logic Inputs
The MAX5054B–MAX5057 have TTL-compatible logic
inputs, while the MAX5054A is a CMOS logic-input dri-
ver. The logic-input signals can be independent of the
VDD voltage. For example, the device can be powered
by a 5V supply while the logic inputs are provided from
CMOS logic. Also, the logic inputs are protected against
the voltage spikes up to 18V, regardless of the VDD volt-
age. The TTL and CMOS logic inputs have 300mV and
0.1 x VDD hysteresis, respectively, to avoid possible dou-
ble pulsing during transition. The low 2.5pF input capaci-
tance reduces loading and increases switching speed.
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
_______________________________________________________________________________________ 9
VIH
VIL
90%
10%
VIH
VIL
tR
tF
tD-OFF1 tD-ON1
tD-OFF2 tD-ON2
IN_+
OUT_
IN_-
RISING MISMATCH = tD-ON2 - tD-ON1
FALLING MISMATCH = tD-OFF2 - tD-OFF1
Figure 1. Timing Diagram
P
N
MAX5054
BREAK-
BEFORE-
MAKE
CONTROL
VDD
OUT_
GND
IN_-
IN_+
Figure 2. MAX5054 Block Diagram (1 Driver)
P
N
MAX5055
MAX5056
MAX5057
BREAK-
BEFORE-
MAKE
CONTROL
VDD
OUT_
GND
IN_+
NONINVERTING INPUT DRIVER
P
N
MAX5055
MAX5056
MAX5057
BREAK-
BEFORE-
MAKE
CONTROL
VDD
OUT_
GND
IN_-
INVERTING INPUT DRIVER
Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams
(1 Driver)
MAX5054–MAX5057
The logic inputs are high impedance and must not be left
floating. If the inputs are left open, OUT_ can go to an
undefined state as soon as VDD rises above the UVLO
threshold. Therefore, the PWM output from the controller
must assume proper state when powering up the device.
The MAX5054 has two logic inputs per driver providing
greater flexibility in controlling the MOSFET. Use IN_+ for
noninverting logic and IN_- for inverting logic operation.
Connect IN_+ to VDD and IN_- to GND if not used.
Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low shutdown logic
and IN_- for active-high shutdown logic (see Figure 4).
See Table 1 for all possible input combinations.
Driver Output
The MAX5054–MAX5057 have low RDS(ON) p-channel
and n-channel devices (totem pole) in the output stage
for the fast turn-on and turn-off high gate-charge switch-
ing MOSFETs. The peak source or sink current is typically
4A. The OUT_ voltage is approximately equal to VDD
when in high state and is ground when in low state. The
driver RDS(ON) is lower at higher VDD, thus higher
source-/sink-current capability and faster switching
speeds. The propagation delays from the noninverting
and inverting logic inputs to outputs are matched to 2ns.
The break-before-make logic avoids any cross-conduc-
tion between the internal p- and n-channel devices, and
eliminates shoot-through currents reducing the quiescent
supply current.
Applications Information
RLC Series Circuit
The driver’s RDS(ON) (RON), internal bond and lead
inductance (LP), trace inductance (LS), gate inductance
(LG), and gate capacitance (CG) form a series RLC
circuit with a second-order characteristic equation. The
series RLC circuit has an undamped natural frequency
(ϖ0) and a damping ratio (ζ) where:
The damping ratio needs to be greater than 0.5 (ideally 1)
to avoid ringing. Add a small resistor (RGATE) in series
with the gate when driving a very low gate-charge
MOSFET, or when the driver is placed away from the
MOSFET. Use the following equation to calculate the
series resistor:
LPcan be approximated as 3nH and 2nH for SO and
TDFN packages, respectively. LSis on the order of
20nH/in. Verify LGwith the MOSFET vendor.
RLLL
CR
GATE PSG
GON
++ ()
ϖ
ξ
0
1
2
=++ ×
=
×++
()
()
LLL C
R
LLL
C
PSG G
ON
PSG
G
4A, 20ns, Dual MOSFET Drivers
10 ______________________________________________________________________________________
MAX5054A
VDD
GND
INA-
INA+ OUTA
PWM
INPUT
ON
OFF
Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A)
Table 1. MAX5054 Truth Table
INA+/INB+ INA-/INB- OUTA/OUTB
Low Low Low
Low High Low
High Low High
High High Low
Table 2. MAX5055/MAX5056/MAX5057
Truth Table
NONINVERTING
IN_+ OUT_
Low Low
High High
INVERTING
IN_- OUT_
Low High
High Low
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5054–MAX5057. Peak supply and output currents
may exceed 8A when both drivers drive large external
capacitive loads in phase. Supply voltage drops and
ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition times.
Ground shifts due to insufficient device grounding may
also disturb other circuits sharing the same AC ground
return path. Any series inductance in the VDD, OUT_,
and/or GND paths can cause oscillations due to the very
high di/dt when switching the MAX5054–MAX5057 with
any capacitive load. Place one or more 0.1µF ceramic
capacitors in parallel as close to the device as possible to
bypass VDD to GND. Use a ground plane to minimize
ground return resistance and series inductance. Place
the external MOSFET as close as possible to the
MAX5054–MAX5057 to further minimize board induc-
tance and AC path impedance.
Power Dissipation
Power dissipation of the MAX5054–MAX5057 consists
of three components: caused by the quiescent current,
capacitive charge/discharge of internal nodes, and the
output current (either capacitive or resistive load).
Maintain the sum of these components below the maxi-
mum power dissipation limit.
The current required to charge and discharge the internal
nodes is frequency dependent (see the Supply Current
vs. Supply Voltage graph in the
Typical Operating
Characteristics
). The power dissipation (PQ) due to the
quiescent switching supply current (IDD-SW) per driver
can be calculated as:
PQ= VDD x IDD-SW
For capacitive loads, use the following equation to esti-
mate the power dissipation per driver:
PCLOAD = CLOAD x (VDD)2x fSW
where CLOAD is the capacitive load, VDD is the supply
voltage, and fSW is the switching frequency.
Calculate the total power dissipation (PT) per driver as
follows:
PT= PQ+ PCLOAD
Use the following equation to estimate the MAX5054–
MAX5057 total power dissipation per driver when driving
a ground-referenced resistive load:
PT= PQ+ PRLOAD
PRLOAD = D x RON(MAX) x ILOAD2
where D (duty cycle) is the fraction of the period the
MAX5054–MAX5057’s output pulls high duty cycle,
RON(MAX) is the maximum on-resistance of the device
with the output high, and ILOAD is the output load current
of the MAX5054–MAX5057.
Layout Information
The MAX5054–MAX5057 MOSFET drivers source and
sink large currents to create very fast rising and falling
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use the
following PC board layout guidelines when designing
with the MAX5054–MAX5057:
Place one or more 0.1µF decoupling ceramic
capacitors from VDD to GND as close to the device
as possible. Connect VDD and GND to large copper
areas. Place one bulk capacitor of 10µF (min) on
the PC board with a low resistance path to the VDD
input and GND of the MAX5054–MAX5057.
Two AC current loops form between the device and
the gate of the driven MOSFET. The MOSFET looks
like a large capacitance from gate to source when the
gate pulls low. The active current loop is from the
MOSFET gate to OUT_ of the MAX5054–MAX5057, to
GND of the MAX5054–MAX5057, and to the source of
the MOSFET. When the gate of the MOSFET pulls
high, the active current is from the VDD terminal of the
decoupling capacitor, to VDD of the MAX5054–
MAX5057, to OUT_ of the MAX5054–MAX5057, to the
MOSFET gate, to the MOSFET source, and to the
negative terminal of the decoupling capacitor. Both
charging current and discharging current loops are
important. Minimize the physical distance and the
impedance in these AC current paths.
Keep the device as close to the MOSFET as possible.
In a multilayer PC board, the inner layers should
consist of a GND plane containing the discharging
and charging current loops.
Pay extra attention to the ground loop and use a
low-impedance source when using a TTL logic-
input device. Fast fall time at OUT_ may corrupt the
input during transition.
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
______________________________________________________________________________________ 11
MAX5054–MAX5057
Exposed Pad
Both the SO-EP and TDFN-EP packages have an
exposed pad on the bottom of their package. These
pads are internally connected to GND. For the best
thermal conductivity, solder the exposed pad to the
ground plane to dissipate 1.5W and 1.9W in SO-EP and
TDFN-EP packages, respectively. Do not use the
ground-connected pads as the only electrical ground
connection or ground return. Use GND (pin 3) as the
primary electrical ground connection.
4A, 20ns, Dual MOSFET Drivers
12 ______________________________________________________________________________________
Additional Application Circuits
MAX5054
INA+
INA-
INB+
INB-
OUTB
OUTA
VDD
GND
VDD
PWM IN
PWM IN
MAX5054
INA+
INA-
INB+
INB-
OUTB
OUTA
VDD
GND
PWM IN
VOUT
VIN
Figure 5. Push-Pull Converter with Synchronous Rectification Drive Using MAX5054
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
______________________________________________________________________________________ 13
REG5 R21
24.9k
1%
C1
100pF
1RCOSC
+VIN TP1
R25
100k
C2
390pF
3RCFF
5CSS
4COM
6COMP
7FB
8REG5
2SYNCOUT
C5
4700pF
D8
21
R15
31.6k
1%
R16
10.5k
1%
C4
4.7µF
REG5
REG5
9REG9
C3
4.7µF
REG9
10 PVIN
C6
0.1µF
PVIN
11 STT
12 LXVDD
13 LXH
C18
1000pF
R27
10
C19
1µF
LXH
TP3 14 LXL
R3
2.2k
R11
360
C17
0.33µF
C24
1000pF
4
3
1
2
U2
R20
0
R19
475
R12
100k
1%
C27
0.15µF
C36
0.22µF
C28
0.047µF
R1
11.5k
1%
R2
2.55k
1%
VOUT
R23
10
TRIM
SENSE (+) SENSE (-)
R24
10
3
52
1
4
OUT IN
PGND
GND
FB
U3
REG9
C26
0.1µF
C22
2200pF
2kV
SYNCIN 28
GND 24
AVIN 23
BST 22
DRVH 21
XFRMRH 20
UVLO 25
FLTINT 27
STARTUP ON/OFF
26
R4
1M
1%
R6
1M
1%
C7
0.22µF
+VIN
+VIN
REG9
+VIN
R5
38.3k
1%
D1
R7
0
R8
8.2
2
C8
4.7µF
XFRMRH
DRVB 19
DRVDD 18
PGND 17
DRVL 16
CS 15
IC_PADDLE
DRVB
REG9
C9
1µF
R14
270
R9
8.2
C20
220pF
D3
12
65
4
123
78
N2
R17
0.027
1%
C21
4.7µF
80V
R18
4.7
PVIN +VIN
R22
15k
1
2
1
6
D5
4T
R13
47
C34
330pF
2
5
8T
D7
1
23
214
56
6
7
8
N3
D4
1
23
214
5
7
8
N4
R10
20
C23
1000pF
8
10
2T
T1
L1
2.4µH
U5
5V
C31
0.1µF
5
4
3
1
2
VCC
OUT
GND
U1: MAX5051
U2: PS2913-1-M
U3: MAX8515
U4: MAX5054
U5: MAX5023M
U6: PS9715
N1, N2: SI4486
N3, N4: SI4864
N5: BSS123
AN
CA
U6
LXH
R26
560
R28
2k
C13
270µF
4V
C14
270µF
4V
C15
270µF
4V
C33
1µF
10V
VOUT
VOUT
SGND
5V
+VIN
C16
3.3µF
21
D6
C35
1µF
C32
1µF
1
2
3
4
8
7
6
5
IN OUT
WDI
N.C.
EN
GND
RESET HOLD
21
D2 N1
32
1
87
6
5
4
XFRMRH
XFRMRH
C10
0.47µF
100V
C11
0.47µF
100V
C12
1µF
100V
C25
0.047µF
100V
-VIN
+VIN
N5
3
2
1
R29
1
XFRMRH
DRVB
MAX5051
U1
REG5
VOUT
VOUT
MAX5054
U4
+5V +5V
C30
0.1µF
6
4
7
1
INA+
INB-
VDD
GND
OUTA
OUTB
INB+
INA-
8
2
5
3
29
Figure 6. Schematic of a 48V Input, 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
14 ______________________________________________________________________________________
Chip Information
PROCESS: CMOS
OUTA
VDD
OUTB
1
2
8
7
INA+
INB+INB-
GND
INA-
TDFN-EP
TOP VIEW
3
4
6
5
MAX5054
VDD
OUTBINB-
1
2
8
7
N.C.
OUTAINA-
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5055
VDD
OUTBINB+
1
2
8
7
N.C.
OUTAINA+
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5056
VDD
OUTBINB+
1
2
8
7
N.C.
OUTAINA-
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5057
Pin Configurations
Selector Guide
PART PIN-
PACKAGE LOGIC INPUT
MAX5054AATA 8 TDFN-EP* VDD / 2 CMOS Dual Inverting
and Dual Noninverting Inputs
MAX5054BATA 8 TDFN-EP* TTL Dual Inverting and Dual
Noninverting Inputs
MAX5055AASA 8 SO-EP* TTL Dual Inverting Inputs
MAX5055BASA 8 SO TTL Dual Inverting Inputs
MAX5056AASA 8 SO-EP* TTL Dual Noninverting Inputs
MAX5056BASA 8 SO TTL Dual Noninverting Inputs
MAX5057AASA 8 SO-EP* TTL Inverting and
Noninverting Inputs
MAX5057BASA 8 SO TTL Inverting and
Noninverting Inputs
*
EP = Exposed pad.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
8 TDFN-EP T833+2 21-0137 90-0059
8 SO-EP S8E+14 21-0111 90-0151
8 SO S8+4 21-0041 90-0096
MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 8/04 Initial release 0
1 9/05 Package-related changes TBD
2 9/10 Added automotive part; updated Package Information table 1, 2, 14,
15, 16
3 3/11 Corrected top mark discrepancy and actual top mark for MAX5054AATA/V+ 1, 2