Supply voltage.

Ground.

Input to the inverting amplifier of the oscillator and the internal clock circuit. This is an alternative pin configuration

The reset pin can also be used as a (weak) I/O pin.

This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the

following drive characteristics:

page 62.

page 65.

This is a 6-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the

following drive characteristics:

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single

register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated

exist. The actual instruction set varies, as some devices only implement a part of the instruction set.

SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

priority.

signed/unsigned multiplication and fractional format. See external document “AVR Instruction Set” and “Instruction

The Status Register contains information about the result of the most recently executed arithmetic instruction. This

pare instructions, resulting in faster and more compact code. See external document “AVR Instruction Set” and

32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory

the internal data memory.

address the first location in the I/O register area as 0x00 and the last as 0x3F.

ters, bits are easily set and cleared using SBI and CBI, while bit-conditional branches are readily constructed using

Registers in this area may also be accessed with instructions LD/LDD/LDS and ST/STD/STS. These instructions

See “Instruction Set Summary” on page 278.

See “Register Summary” on page 276 for a list of I/O registers.

Following the general purpose register file and the I/O register files, the remaining 1024 locations are reserved for

All addressing modes can be used on the entire volatile memory, including the general purpose register file, the I/O

register files and the data memory.

Internal SRAM is accessed in two clkCPU cycles, as illustrated in Figure 5-2, below.

ATtiny1634 contains 256 bytes of non-volatile data memory. This EEPROM is organized as a separate data space,

in which single bytes can be read and written. All access registers are located in the I/O space.

specified. To avoid problems in situations like this, see “Preventing EEPROM Corruption” on page 19.

The EEPROM has a minimum endurance of 100,000 write/erase cycles.

EEPROM Control Register (EECR). See Table 5-4 on page 23. Write and erase times are given in the same table.

Since EEPROM programming takes some time the application must wait for one operation to complete before

starting the next. This can be done by either polling the EEPROM Program Enable bit (EEPE) in EEPROM Control

Ready Interrupt Enable (EERIE) bit in EECR.

tions. To erase an EEPROM memory location follow the procedure below:

bits is undefined and a legitimate value must therefore be written to the register before EEPROM is accessed.

Devices with 256 bytes of EEPROM, or less, do not require a high address registers (EEARH). In such devices the

the low byte of the EEPROM address register (EEARL).

and they always read zero.

programmed, or Erase and Write can be split in two different operations. The programming times for the different

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Ready Interrupt is triggered when non-volatile memory is ready for programming.

When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be pro-

Note that an EEPROM write operation blocks all software programming of Flash, fuse bits, and lock bits.

be written to one to trigger the EEPROM read operation.

Figure 6-1 presents the principal clock systems and their distribution in ATtiny1634. All of the clocks need not be

The clock subsystems are detailed in the sections below.

Halting the CPU clock inhibits the core from performing general operations and calculations.

See “Speed” on page 229.

The application software can write this register to change the oscillator frequency. The oscillator can be calibrated

(Nominal = 8MHz) vs. OSCCAL Value” on page 273.

A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory cal-

ibrated frequency specified in Table 24-2 on page 230.

This register need not be updated if factory defaults in OSCCAL0 are overwritten although optimal accuracy is

achieved when OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.

When this bit is set the contents of registers OSCTCAL0A and OSCTCAL0B are used for calibration. When this bit

• Bits 1:0 – CAL1[1:0]: Oscillator Calibration Value

The oscillator calibration register is used to trim the internal 32kHz oscillator and to remove process variations from

power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU,

thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to

used for wake up.

• Bit 4 – SE: Sleep Enable

after waking up.

nals to be disabled.

• Bit 7 – Res: Reserved Bit

• Bit 4 – PRTIM0: Power Reduction Timer/Counter0

• Bit 3 – PRUSI: Power Reduction USI

again, the USI should be re initialized to ensure proper operation.

tinue like before the shutdown.

The instruction placed at the Reset Vector should be a JMP (two-word, direct jump) instruction to the reset han-

section “System and Reset” on page 231.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not

A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in “Sys-

be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.

A typical and general setup for interrupt vector addresses in ATtiny1634 is shown in the program example below.

The pin change interrupts trigger as follows:

Register” on page 37. When INT0 is enabled and configured as level triggered, the interrupt will trigger as long as