UT22VP10E-15PPA - Aeroflex, Inc.

Standard Products

UT22VP10 Universal RADPALTM

Data Sheet

November 2000

FEATURES

q High speed Universal RADPAL

-tPD: 15.5ns, 20ns, 25ns maximum

- fMAX1: 33MHz maximum external frequency

-Supported by industry-standard programmer

-Amorphous silicon anti-fuse

qAsynchronous and synchronous RADPAL operation

-Synchronous PRESET

-Asynchronous RESET

qUp to 22 input and 10 output drivers may be configured

-CMOS & TTL-compatible input and output levels

-Three-state output drivers

qVariable product terms, 8 to 16 per output

q10 user-programmable output macrocells

-Registered or combinatorial operation

-Output driver polarity control selectable

-Two feedback paths available

qRadiation-hardened process and design; total dose irradia-

tion testing to MIL-STD-883, Method 1019

-Total dose: 1.0E6 rads(Si)

-Upset threshold 50 MeV-cm2/mg (min)

-Latchup immune(LET>109 MeV-cm2/mg)

qQML Q & V compliant

qPackaging options:

-24-pin 100-mil center DIP (0.300 x 1.2)

-24-lead flatpack (.45 x .64)

-28-lead quad-flatpack (.45 x .45)

qStandard Military Drawing 5962-94754 available

Macrocell

11 10 9 8 7 6 5 4 3 2 1

Reset

Preset

Figure 1. Block Diagram

PROGRAMMABLE ARRAY LOGIC

(132 X 44)

VSS

VDD

PRODUCT DESCRIPTION

The UT22VP10 RADPAL is a fuse programmable logic array

device. The familiar sum-of-products (AND-OR) logic struc-

ture is complemented with a programmable macrocell. The

UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and

28-lead quad-flatpack package offerings providing up to 22

inputs and 10 outputs. Amorphous silicon anti-fuse technology

provides the programming of each output. The user specifies

whether each of the potential outputs is registered or combina-

torial. Output polarity is also individually selected, allowing for

greater flexibility for output configuration. A unique output en-

able function allows the user to configure bidirectional I/O on

an individual basis.

The UT22VP10 architecture implements variable sum terms

providing 8 to 16 product terms to outputs. This feature provides

the user with increased logic function flexibility. Other features

include common synchronous preset and asynchronous reset.

These features eliminate the need for performing the initializa-

tion function.

The UT22VP10 provides a device with the flexibility to imple-

ment logic functions in the 500 to 800 gate complexity. The

flexible architecture supports the implementation of logic func-

tions requiring up to 21 inputs and only a single output or down

to 12 inputs and 10 outputs. Development and programming

support for the UT22VP10 is provided by DATA I/O.

DIP & FLATPACK PIN CONFIGURATION

QUAD-FLATPACK PIN CONFIGURATION

PIN NAMES

FUNCTION DESCRIPTION

The UT22VP10 RADPAL implements logic functions as sum-

of-products expressions in a one-time programmable-AND/

fixed-OR logic array. User-defined functions are created by

programming the connections of input signals into the array.

User-configurable output structures in the form of I/O macro-

cells further increase logic flexibility.

CK/I

VSS

VDD

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

CK/I Clock/Data Input

IData Input

I/O Data Input/Output

VDD Power

VSS Ground

12 13 14 15 16 17 18

1234 28 27 26

VSS

I/O2

I/O3

I/O4

VSS

I/O5

I/O7

I/O6

VDD

CK/III VDD I/O0 I/O1

VSS

II I I/O9 I/O8VSS

Table 1. Macrocell Configuration Table1, 2, 3

OVERVIEW

The UT22VP10 RADPAL architecture (see figure 1) has 12 ded-

icated inputs and 10 I/Os to provide up to 22 inputs and 10

outputs for creating logic functions. At the core of the device

is a one-time programmable anti-fuse AND array that drives a

fixed OR array. With this structure, the UT22VP10 can imple-

ment up to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is a macrocell

which is independently programmed to one of six different con-

figurations. The one-time programmable macro cells allow

each I/O to create sequential or combinatorial logic functions

with either Active-High or Active-Low polarity.

LOGIC ARRAY

The one-time programmable AND array of the UT22VP10

RADPAL is formed by input lines intersecting product terms.

The input lines and product terms are used as follows:

44 input lines:

•24 input lines carry the true and complement of the signals

applied to the input pins

•20 lines carry the true and complement values of feedback

or input signals from the 10 I/Os

132 product terms:

•120 product terms (arranged in 2 groups of 8, 10, 12, 14, and

16) used to form logic sums

•10 output enable terms (one for each I/O)

•1 global synchronous preset term

•1 global asynchronous reset term

At each input-line/product-term intersection there is an anti-

fuse cell which determines whether or not there is a logical

connection at that intersection. A product term which is con-

nected to both the true and complement of an input signal will

always be logical zero, and thus will not effect the OR function

that it drives. When there are no connections on a product term

a Don’t Care state exists and that term will always be a logical

one.

PRODUCT TERMS

The UT22VP10 provides 120 product terms that drive the 10

OR functions. The 120 product terms connect to the outputs in

two groups of 8, 10, 12, 14, and 16 to form logical sums.

MACROCELL ARCHITECTURE

The output macrocell provides complete control over the archi-

tecture of each output. Configuring each output independently

permits users to tailor the configuration of the UT22VP10 to

meet design requirements.

Each I/O macrocell (see figure 2) consists of a D flip-flop and

two signal-select multiplexers. Three configuration select bits

controlling the multiplexers determine the configuration of

each UT22VP10 macrocell (see table 1). The configuration se-

lect bits determine output polarity, output type (registered or

combinatorial) and input feedback type (registered or I/O). See

figure 3 for equivalent circuits for the macrocell configurations.

OUTPUT FUNCTIONS

The signal from the OR array may be fed directly to the output

pin (combinatorial function) or latched in the D flip-flop (reg-

istered function). The D flip-flop latches data on the rising edge

of the clock. When the synchronous preset term is satisfied, the

Q output of the D flip-flop output will be set logical one at the

next rising edge of the clock input. Satisfying the asynchronous

clear term sets Q logical zero, regardless of the clock state. If

both terms are satisfied simultaneously, the clear will override

the preset.

C2C1C0Output Type Polarity Feedback

000 Registered Active LOW Registered

001 Registered Active HIGH Registered

X1 0 Combinatorial Active LOW I/O

X1 1 Combinatorial Active HIGH I/O

100 Registered Active LOW I/O

101 Registered Active HIGH I/O

Notes:

1. 0 equals programmed low or programmed.

2. 1 equals programmed high or unprogrammed.

3. X equals don’t care.

OUTPUT POLARITY

Each macrocell can be configured to implement Active-High

or Active-Low logic. Programmable polarity eliminates the

need for external inverters.

OUTPUT ENABLE

The output of each I/O macrocell can be enabled or disabled

under the control a programmable output enable product term.

The output signal is propagated to the I/O pin when the logical

conditions programmed on the output enable term are satisfied.

Otherwise, the output buffer is driven to the high-impedance

state.

The output enable term allows the I/O pin to function as a ded-

icated input, dedicated output, or bidirectional I/O. When every

connection is unprogrammed, the output enable product term

permanently enables the output buffer and yields a dedicated

output. If every connection is programmed, the enable term is

logically low and the I/O functions as a dedicated input.

The feedback signal to the AND array is taken from the Q output

when the I/O macrocell implements a registered function

(C2 = 0, C1 = 0).

BIDIRECTIONAL I/O

The feedback signal is taken from the I/O pin when the macro-

cell implements a combinatorial function (C1 = 1) or a regis-

tered function (C2 = 1, C1 = 0). In this case, the pin can be used

as a dedicated input, a dedicated output, or a bidirectional I/O.

POWER-ON RESET

To ease system initialization, all D flip-flops will power-up to

a reset condition and the Q output will be low. The actual output

of the UT22VP10 will depend on the programmed output po-

larity. The reset delay time is 5µs maximum. See the Power-up

Reset section for a more descriptive list of POR requirements.

ANTI-FUSE SECURITY

The UT22VP10 provides a security bit that prevents unautho-

rized reading or copying of designs programmed into the de-

vice. The security bit is set by the PLD programmer at the con-

clusion of the programming cycle. Once the security bit is set

it is no longer possible to verify (read) or program the

UT22VP10. NOTE: UTMC does not recommend using the

UT22VP10 unless the security fuse has been programmed.

The security bit must be blown to ensure proper function-

ality of the UT22VP10.

CK QC1C0

OUTPUT

SELECT

MUX

INPUT/

FEEDBACK

MUX

Figure 2. Macrocell

Registered Feedback, Registered, Active-Low Output (C2 = 0, C1 = 0, C0 = 0)

CK Q

Registered Feedback, Registered, Active-High Output (C2 = 0, C1 = 0, C0 = 1)

I/O Feedback, Combinatorial, Active-Low Output (C2 = X, C1 = 1, C0 = 0)

Figure 3. Macrocell Configuration (continued on next page)

I/O Feedback, Combinatorial, Active-High Output (C2 = X, C1 = 1, C0 = 1)

CK Q

I/O Feedback, Registered, Active-Low Output (C2 = 1, C1 = 0, C0 = 0)

CK Q

I/O Feedback, Registered, Active-High Output (C2 = 1, C1 = 0, C0 = 1)

Figure 3. Macrocell Configuration

ABSOLUTE MAXIMUM RATINGS1

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the

device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2. Minimum voltage is -0.6VDD which may undershoot to -2.0VDD for pulses of less than 20ns. Maximum output pin voltage is VDD +0.75VDD which may

overshoot to +7.0VDD for pulses of less than 20ns.

3. (ICC max + IOS) 5.5V.

RECOMMENDED OPERATING CONDITIONS

Notes:

1. See page 12 for minimum VDD requirements at power-up.

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage -0.3 to 7.0 V

VI/O2Input voltage any pin -0.3 to +7.0 V

TSTG Storage Temperature range -65 to +150 °C

TJMaximum junction temperature +175 °C

TSLead temperature (soldering 10 seconds) +300 °C

ΘJC Thermal resistance junction to case 20 °C/W

IIDC input current ±10 mA

PD3Maximum power dissipation 1.6 W

IOOutput sink current 12 mA

SYMBOL PARAMETER LIMIT UNITS

VDD1Supply voltage 4.5 to 5.5 V

VIN Input voltage any pin 0 to VDD V

TCTemperature range -55 to + 125 °C

DC ELECTRICAL CHARACTERISTICS 1, 7

(VDD2 = 5.0V ±10%; VSS = 0V3, -55°°C < TC < +125°°C)

Notes:

1. All specifications valid for radiation dose < 1E6 rads(Si).

2. See page 12 for minimum VDD requirements at power-up.

3. Maximum allowable relative shift equals 50mV.

4. Duration not to exceed 1 second, one output at a time.

5. Tested initially and after any design or process changes that affect that parameter and, therefore, shall be guaranteed to the limit specified.

6. All pins not being tested are to be open.

7. CMOS levels only tested on CMOS devices. TTL levels only tested on TTL devices.

SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM UNIT

VIL Low-level input voltage TTL -- .8 V

VIH High-level input voltage TTL 2.2 -- V

VIL Low-level input voltage CMOS -- .3*VDD V

VIH High-level input voltage CMOS .7*VDD -- V

VOL Low-level output voltage IOL = 12.0mA, VDD = 4.5V (TTL) .4 V

VOH High-level output voltage IOH = -12.0mA, VDD = 4.5V (TTL) 2.4 -- V

VOL Low-level output voltage IOL = 200µµA, VDD = 4.5V (CMOS) -- VSS+0.05 V

VOH High-level output voltage IOH = -200µµA, VDD = 4.5V (CMOS) VDD-0.05 -- V

IIN Input leakage current VIN = VDD and VSS -10 10 µA

IOZ Three-state output leakage

current VO = VDD and VSS, VDD = 5.5V -10 10 µA

IOS4,5 Short-circuit output cur-

rent VDD = 5.5V, VO = VDD

VDD = 5.5V, VO = 0V -160 160 mA

CIN5,6 Input capacitance ƒƒ=1MHz @0V -- 15 pF

CI/O5,6 Bidirectional capacitance ƒƒ=1MHz @0V -- 15 pF

IDD5Supply current: Output

three-state, worst-case pat-

tern programmed,

ƒƒ=fMAX1

VDD = 5.5V -- 120 mA

IDDQ Supply current:

Unprogrammed VDD = 5.5V -- 25 mA

AC CHARACTERISTICS READ CYCLE (Post-Radiation) 1,2

(VDD3 = 5.0V ±10%; -55°C < TC < +125°C)

Notes:

1. Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

2. Guaranteed by characterization.

3. See page 12 for minimum VDD requirements for power-up.

4. Tested initially and after any design or process changes that affect.

5. Device 22VP10-15 tested at -55°C, +25°C and +50°C. At 125°C, tested to 20ns limit.

6. Tested on Programmed Test Ring only.

SYMBOL PARAMETER 22VP10-15.5

MIN MAX 22VP10-20

MIN MAX 22VP10-25

MIN MAX UNIT

tPD4,5,6 Input to output propagation delay 15.5 20 25 ns

tEA4Input to output enable delay 23 23 25 ns

tER4Input to output disable delay 23 23 25 ns

tCO4,6 Clock to output delay 15 15 15 ns

tCO24Clock to combinatorial output delay via internal

registered feedback 24 24 28 ns

tS4,6 Input or feedback setup time 15 15 18 ns

tH4,6 Input or feedback hold time 222 ns

tP4External clock period (tCO + tS)30 30 33 ns

tWH, WL4Clock width, clock high time, clock low time 12 12 14 ns

fMAX14,6 External maximum frequency (1/(tCO + tS)) 33 33 30 MHz

fMAX24,6 Data path maximum frequency (1/(tWH + tWL)) 42 42 36 MHz

fMAX34,6 Internal feedback maximum frequency (1/(tCO + tCF)) 32 32 32 MHz

tCF4Register clock to feedback input 13 13 13 ns

tAW4Asynchronous reset width 20 20 25 ns

tAR4Asynchronous reset recovery time 20 20 25 ns

tAP4Input to asynchronous reset 20 20 25 ns

tSPR4,6 Synchronous preset recovery time 20 20 25 ns

tPR4,6 Power up reset time 1.0 1.0 1.0 µs

tPD

tStH

tCO

INPUT OR

BIDIRECTIONAL

INPUT

COMBINATIONAL

OUTPUT

Combinatorial Output

INPUT OR

BIDIRECTIONAL

INPUT

REGISTERED

OUTPUT

CLOCK

Registered Output

tWH

tWL

Clock Width

INPUT OR

BIDIRECTIONAL

INPUT

OUTPUT

Combinatorial Output

(VOH - 0.5V, VOL + 0.5V)

tEA

tER

tAP

tAR

INPUT ASSERTING

ASYNCHRONOUS

RESET

CLOCK

REGISTERED

OUTPUT

tAW

CLOCK

REGISTERED

OUTPUT

INPUT ASSERTING

SYNCHRONOUS

PRESET

tStHtSPR

tCO

Asynchronous Reset Synchronous Preset

Notes:

1. VT = 1.5V.

2. Input pulse amplitude 0V to 3.0V.

3. Input rise and fall times 3ns maximum.

Figure 4. AC Electrical1,2,3

CLK

fMAX3; Internal Feedback

OUTPUT

CLK

Clock to Combinatorial Output (tCO2)

OUTPUT

PRODUCT

TERMS

Figure 5. Signal Paths

PRODUCT

TERMS D

PRODUCT

TERMS

PRODUCT

TERMS

tCF1

Note:

1. tCF defined as the propagation delay from Q to D register input.

tCO + tCF

POWER-UP RESET

The power-up reset feature ensures that all flip-flops will be

reset to LOW after the device has been powered up. The output

state will depend on the programmed pattern. This feature is

valuable in simplifying state machine initialization. See figure

6 for a timing diagram. Due to the synchronous operation of the

power-up reset and the wide range of ways VDD can rise to its

steady state, the following five conditions are required to ensure

a valid power-up reset.

1. The voltage supplied to the VDD pin(s) must be equal to 0V

prior to the intended power-up sequence.

2. The voltage on VDD must rise from 0V to 1V at a rate of

0.1V/s or faster.

3. The VDD rise must be continuously increasing with respect

to time, through 3V, and monotonic thereafter.

4. Following reset, the clock input must not be driven from

LOW to HIGH until all applicable input and feedback setup

times are met.

5. The power-up voltage must meet the minimum VDD require-

ments described by the following device dependent and tem-

perature dependent equations:

RADIATION HARDNESS

The UT22VP10 RADPAL incorporates special design and layout features which allow operation in high-level radiation environments.

UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both

the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup

immunity, UTMC builds radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process.

RADIATION HARDNESS DESIGN SPECIFICATIONS1

Note:

1. The RADPAL will not latchup during radiation exposure under recommended operating conditions.

SMD Device types 01, 02, 03, 04, 08 CMOS and TTL

VDD =4.61V -0.0090*(oC)

SMD Device types 05, 06, 07 CMOS

VDD =4.41 -0.0090* (oC)

Note: The minimum VDD requirement above is not applicable

if the UT22VP10 application is purely combinatorial (i.e. no

registered outputs).

VDD

REGISTERED

ACTIVE-LOW

OUTPUT

CLOCK

VDD

tWL

VDD min

tPR

Figure 6. Power-Up Reset Waveform

PARAMETER CONDITION MINIMUM UNIT

Total Dose +25°C per MIL-STD-883 Method 1019 1.0E6 rads(Si)

LET Threshold -55°C to +125°C 50 MeV-cm2/mg

Neutron Fluence 1MeV equivalent 1.0E14 n/cm2

Figure 7. 24-Pin 100-mil Center DIP (0.300 x 1.2)

0.018 ±0.002

0.010 +0 .002

- 0.001

TOP VIEW

SIDE VIEW

FRONT VIEW

DETAIL A

(NO SCALE)

LEAD

CERAMIC

BODY

0.040 MAX.

BRAZE FILLET

0.025 MAX.

SEE DETAIL A

0.300±0.010

0.166

0.110

0.050 TYP.

0.200

0.125 L1

0.150 MIN.

0.005

MIN. TYP.

0.005 MIN.

-C- 4

0.060

0.015 0.010 CM

1.100

0.100

PIN 1 INDEX

GEOMETRY OPT.

1.200 0.015

0.50 R.

(AT SEATING PLANE)

14 24-LD

6038

0.295 ±0.010

0.310 ±0.010

Notes:

1. Package material: Opaque ceramic.

2. All exposed metalized areas are finished per MIL-PRF-38535.

3. Letter designations are for cross-reference to MIL-STD-1835.

4. For solder coated leads, increase maximum limit by 0.003 inch as measured at the center

of the flat.

5. Numbering and lettering on the ceramic are not subject to visual marking criteria.

Figure 8. 24-Lead Flatpack (0.45 x 0.64)

Notes:

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Dimension letters refer to MIL-STD-1835.

5. Lead position and coplanarity are not measured.

6. ID mark symbol is vendor option.

7. For solder coated leads, increase maximum limit by 0.003 inch as measured at the center of the flat.

-B-

28 PLACES

HA-B D5

0.010 M

PIN NO. 1 ID. 65

-D-

0.015

0.008

0.015

0.008

26 PLACES

0.05

-A-

4 PLACES

0.000 MIN.

0.006

0.004

0.040

-H-

0.030 MIN. TYP.

0.180

MIN.

0.420

0.350

-C-

0.115

0.045

0.022

0.015

0.450 MAX.

0.045

0.026

0.370 TYP.

0.250

0.640 MAX.

HA-B D

0.036 MSS

Figure 9. 28-Lead Quad-Flatpack (.45 x .45)

Notes:

1. All exposed metalized areas are gold plated over

electroplated nickel per MIL-PRF-38535.

2. Lead finishes are in accordance with MIL-PRF-38535.

3. Dimension letters refer to MIL-STD-1835.

4. Lead position and coplanarity are not measured.

5. Mark is not subject to visual marking criteria.

6. Mark is on lid and its symbol is vendor option.

7. For solder coated leads, increase maximum limit by

0.003 inch as measured at the center of the flat.

0.008 ±0.001

TOP VIEW

SIDE VIEW

VIEW A-A

-C-

0.040

PACKAGE PART

NUMBER 5

0.980 SQ. REF.

SEE DETAIL

A. PIN 1 ID 0.250

MIN. TYP.

O.450 ±0.007 SQ.

128

-A- A

0.100 MAX.

0.050 4

0.018±0.002

0.065 ±0.007

CAB

0.030 M

0.009 M4

-B- E

0.450 REF.

7050

DETAIL A

PIN 1 ID

SQUARE CORNERS.

THIS PAD ONLY.

BACK SIDE

PIN 1 ID MARK

ORDERING INFORMATION

UT22VP10 Radiation Hardened PAL: SMD

Lead Finish:

(A) = Solder

(X) =Optional

Case Outline:

(L) =24-lead DIP

(X) =24-lead pin Flatpack

(Y) =28-lead pin Quad Flatpack

Class Designator:

(Q) =Class Q

(V) =Class V

Device Type

(01) = 25ns prop delay, CMOS I/O

(02) = 25ns prop delay, TTL I/O

(03) = 20ns prop delay, CMOS I/O

(04) = 20ns prop delay, TTL I/O

(05) = 25ns prop delay, CMOS I/O

(06) = 20ns prop delay, CMOS I/O

(07) = 15.5ns prop delay, CMOS I/O

(08) = 15.5ns prop delay, TTL I/O

Drawing Number: 94754

Total Dose:

(H) =1E6 rads(Si)

(G) =5E5 rads(Si)

(F) =3E5 rads(Si)

(R) =1E5 rads(Si)

Federal Stock Class Designator: No options

5962 * 94754 * * * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.

4. (01-04, 08) is VDD(min) = -0.009*(oC)+4.61.

5. (05-07) is VDD(min) = -0.009*(oC)+4.41.

6. (07, 08) is tested at -55°C, +25°C, and +50°C to 15.5ns for tPD. At +125°C tested to 20ns limit for tPD.

UT22VP10 Radiation Hardened PAL

Radiation:

- = None

Lead Finish:

(A) =Solder

(X) =Optional

Screening:

(P) =Prototype

Package Type:

(P) =24-pin DIP

(U) =24-pin Flatpack

(W) =28-pin Quad Flatpack

Device Type Modifier:

C-20 = CMOS I/O: 20ns propagation delay

C-25 = CMOS I/O: 25ns propagation delay

E-15 = CMOS I/O: 15.5ns propagation delay

E-20 = CMOS I/O: 20ns propagation delay

E-25 = CMOS I/O: 25ns propagation delay

T-15 = TTL I/O: 15.5ns propagation delay

T-20 = TTL I/O: 20ns propagation delay

T-25 = TTL I/O: 25ns propagation delay

UT22VP10 * * * * *

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Military Temperature range flow per UTMC’s manufacturing flows document. Devices have 48 hours of burn-in and are tested at -55°C,

room temperature, and 125°C. Radiation characteristics are neither tested nor guaranteed and may not be specified.

4. Prototype flow per UTMC Manufacturing Flows Technical Description. Devices have prototype assembly and are tested at 25°C only.

Radiation is neither tested nor guaranteed.

5. (T-15, C-25, T-25, C-20, T-20) is VDD(min) = -0.009*(oC)+4.61.

6. (E-15, E-20 and E-25) is VDD(min) = -0.009*(oC)+4.41.

7. (E-15 and T-15) is tested at at -55°C, +25°C, and +50°C to 15.5ns for tPD. At +125°C tested to 20ns limit for tPD.

Notes