Philips Semiconductors Product specification
OM5232CMOS single-chip 8-bit microcontroller
December 1994 7
DC ELECTRICAL CHARACTERISTICS
VSS = 0V, VDD = 5.0V ±10%. Operating temperature range 0 to 70°C.
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VIL Input low voltage,
except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V
VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V
VIL2 Input low voltage to P1.6, P1.7 –0.5 0.3VDD V
VIH Input high voltage, except XTAL1, RST, P1.6, P1.7 0.2VDD+0.9 VDD+0.5 V
VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V
VIH2 Input high voltage, P1.6, P1.7 0.7VDD 6.0 V
VOL Output low voltage, ports 1, 2, 3, except P1.6, P1.7 IOL = 1.6mA 7), 8) 0.45 V
VOL1 Output low voltage, port 0, ALE, PSEN IOL = 3.2mA 7), 8) 0.45 V
VOL2 Output low voltage, P1.6, P1.7 IOL = 3.0mA 0.4 V
VOH Output high voltage, ports 1, 2, 3, ALE, PSEN 9) IOH = –60µA 2.4 V
IOH = –25µA 0.75VDD V
IOH = –10µA 0.9VDD V
VOH1 Output high voltage; port 0 in external bus mode IOH = –800µA2.4 V
IOH = –300µA0.75VDD V
IOH = –80µA0.9VDD V
IIL Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7 VIN = 0.45V –50 µA
ITL Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6, P1.7 See note 6) –650 µA
IL1 Input leakage current, port 0, EA 0.45V < VI < VDD ±10 µA
IL2 Input leakage current, P1.6, P1.7 0V < VI < 6.0V
0V < VDD < 6.0V ±10 µA
IDD Power supply current: See note 1)
Active mode @ 16MHz 2), 10) VDD=6.0V 26.5 mA
Idle mode @ 16MHz 3), 10) 6 mA
Power down mode 4), 5) 50 µA
RRST Internal reset pull-down resistor 50 150 kΩ
CIO Pin capacitance Freq.=1MHz 10 pF
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 9 through 11 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V;
VIH = VDD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD;
EA = RST = VSS. See Figure 11.
5. 2V ≤ VPD ≤ VDDmax.
6. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt T rigger, or use an address latch with a Schmitt Trigger STROBE input.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum
IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the
test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
9. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
10.IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA.