2011 Microchip Technology Inc. DS41332D-page 1
This document includes the
programming specifications for the
following devi ces:
1.0 OVERVIEW
The PIC16F72X and PIC16LF72X devices are
programmed using In-Circuit Serial Programming™
(ICSP™). This programming specification applies to
the PIC16F72X and PIC16LF72X devices in all
packages.
The PIC16F72X devices operate from 1.8 to 5.5 volts
and the PIC16LF72X devices operate from 1.8 to 3.6
volts. All other aspects of the PIC16F72X with regards
to the PIC16LF72X devices are identica l.
1.1 Hardware Requirements
PIC16F72X and PIC16LF72X devices require one
power supply for VDD and one for VPP. (See
Section 8.0 “Electrical Specifications” for more
details.)
1.2 Pin Utilization
Five pins are needed for ICSP™ programming. The
pins are listed in Table 1-1.
TABLE 1-1: PIN DE SCR IPTI ONS DU RING PROGR AMMIN G
• PIC16F722 • PIC16F722A • PIC16F723
• PIC16F723A • PIC16F724 • PIC16F726
• PIC16F727 • PIC16LF722 • PIC16LF722A
• PIC16LF723 • PIC16LF723A • PIC16LF724
• PIC16LF726 • PIC16LF727
Pin Name During Programming
Function Pin Type Pin Description
RB6 ICSPCLK I Clock Input – Schmitt Trigger Input
RB7 ICSPDAT I/O Data Input/O utp ut – Schmitt Trigger Input
MCLR/VPP Program/Verify mode P(1) Program Mode Select/Programming Power Supply
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: To activate the Program/Verify mode, high voltage needs to be applied to MCLR/VPP input. Since the
MCLR/VPP is used to provide high voltage during programming, the programmer must be able to supply
current on this pin.
PIC16(L)F72X Memory Programming Specification
PIC16(L)F72X
PIC16(L)F72X
DS41332D-page 2 2011 Microchip Technology Inc.
2.0 DEVICE PINOUTS
The pin diagrams for the PIC16(L)F72X family are
shown in Figure 2-1 thro ugh Figure 2-6. The pins that
are required for programming are listed in Table 1-1
and shown in bold lettering in the pin diagrams.
FIGURE 2-1: PDIP/SOIC/SSOP DIAGRAM FOR PIC16F722/722A/723/723A/726 AND
PIC16LF722/722A/723/723A/726
28-Pin SOIC, SSOP, Skinny PDIP
PIC16(L)F/722/722A/723/723A/726
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
SS/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
T0CKI/RA4
VCAP/SS/AN4/RA5
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
RB3/AN9/CCP2
RB2/AN8
RB1/AN10
RB0/AN12/INT
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
CLKI/OSC1/RA7
CLKO/OSC2/RA6
T1CKI/T1OSO/RC0
CCP2/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
RC5/SDO
RC4/SDI/SDA
RC7/RX/DT
RC6/TX/CK
RB7/ICSPDAT
2011 Microchip Technology Inc. DS41332D-page 3
PIC16(L)F72X
FIGURE 2-2: QFN PACKAGE DIAGRAM FOR PIC1 6F72 2/72 2A/7 23/7 23A/ 726 AND
PIC16LF722/722A/723/723A/726
2
3
6
1
18
19
20
21
15
716
17
T1CKI/T1OSO/RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
RB3/AN9/CCP2
RB2/AN8
RB1/AN10
RB0/AN12/INT
VDD
VSS
RC7/RX/DT
CK/TX/RC6
SDO/RC5
SDA/SDI/RC4
RE3/MCLR/VPP
RA0/AN0/SS
RA1/AN1
AN2/RA2
VREF/AN3/RA3
T0CKI/RA4
VCAP/SS/AN4/RA5
VSS
CLKI/OSC1/RA7
CLKO/OSC2/RA6
CCP2/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
9
10
13
8
14
12
11
27
26
23
28
22
24
25
PIC16(L)F/722/722A/
723/723A/726
28-Pin QFN, UQFN
PIC16(L)F72X
DS41332D-page 4 2011 Microchip Technology Inc.
FIGURE 2-3: PDIP PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
FIGURE 2-4: QFN PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
40-Pin PDIP
PIC16(L)F724/727
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
SS/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
T0CKI/RA4
VCAP/SS/AN4/RA5
AN5/RE0
AN6/RE1
AN7/RE2
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
RB3/AN9/CCP2
RB2/AN8
RB1/AN10
RB0/AN12/INT
VDD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
CLKI/OSC1/RA7
CLKO/OSC2/RA6
T1CKI/T1OSO/RC0
CCP2/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
RD0
RD1
RC5/SDO
RC4/SDI/SDA
RD3
RD4
RC7/RX/DT
RC6/TX/CK
RD7
RD6
RD5
RB7/ICSPDAT
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/AN3/RA3
AN2/RA2
AN1/RA1
SS(2)/AN0/RA0
VPP/MCLR/RE3
CCP2(1)/AN9/RB3
ICSPDAT/RB7
ICSPCLK/RB6
T1G/AN13/RB5
AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS(2)/VCAP
RA4/T0CKI
DT/RX/RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
INT/AN12/RB0
AN10/RB1
AN8/RB2
44-Pin QFN
PIC16(L)F724/727
2011 Microchip Technology Inc. DS41332D-page 5
PIC16(L)F72X
FIGURE 2-5: TQFP PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/AN3/RA3
AN2/RA2
AN1/RA1
SS/AN0/RA0
VPP/MCLR/RE3
NC
ICSPDAT/RB7
ICSPCLK/RB6
T1G/AN13/RB5
AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/VCAP
RA4/T0CKI
RC7/RX/DT
RD4
RD5
RD6
VSS
VDD
INT/AN12/RB0
AN10/RB1
AN8/RB2
CCP2/AN9/RB3
RD7 5
4
PIC16(L)F724/727
44-Pin TQFP
PIC16(L)F72X
DS41332D-page 6 2011 Microchip Technology Inc.
FIGURE 2-6: 40-PIN UQFN PACKAGE DIAGRAM FOR PIC16F724/727
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/AN3/RA3
AN2/RA2
AN1/RA1
VCAP/SS(2)/AN0/RA0
VPP/MCLR/RE3
CCP2(1)/CPS3/AN9/RB3
ICSPDAT/RB7
ICSPCLK/RB6
T1G/CPS5/AN13/RB5
CPS4/AN11/RB4 RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T1CKI
RA6/OSC2/CLKO/VCAP
RA7/OSC1/CLKI
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP
RA4/CPS6/T0CKI
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
CPS15/RD7
VSS
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
40-Pin UQFN
PIC16F724/727
2011 Microchip Technology Inc. DS41332D-page 7
PIC16(L)F72X
3.0 MEMORY MAP
The memory for the PIC16(L)F72X devices is broken
into two sections: program memory and configuration
memory. Only the size of the program memory
changes between devices; the configuration memory
remains the sa me.
FIGURE 3-1: PIC16(L)F722/722A PROGRAM MEMORY MAPPING
1FFF
h
2000
h
2200
h
3FFF
h
Implemented
2 KW
Implemented
07FF
h
Maps to
0-7FF
Maps to
Program Memory
Configuration Memory
2000-21FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
2009h
2008h
200Ah
200Bh-20FFh
0000h
PIC16(L)F72X
DS41332D-page 8 2011 Microchip Technology Inc.
FIGURE 3-2: PIC16(L)F723/723A/724 PROGRAM MEMORY MAPPING
1FFF
h
2000
h
2200
h
3FFF
h
Implemented
4 KW
Implemented
0FFF
h
Maps to
0-FFF
Maps to
Program Memory
Configuration Memory
2000-21FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
200Ah
2008h
200Bh-20FFh
2009h
0000
h
2011 Microchip Technology Inc. DS41332D-page 9
PIC16(L)F72X
FIGURE 3-3: PIC16( L)F726 /727 PROGR AM MEMORY MAPP ING
3.1 User ID Location
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 2000h-2003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
3.2 Device ID
The device ID word for the PIC16F72X and the
PIC16LF 72X dev ices is loc ated a t 20 06h. T his l ocatio n
cannot be erased or modified.
1FFF
h
2000
h
2200
h
3FFF
h
8 KW
Implemented
Maps to
Program Memory
Configuration Memory
2000-21FFh
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Reserved
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
2009h
2008h
200Ah
Implemented
200Bh-20FFh
0000
h
Note: MPLAB® IDE only displays the 7 Least
Significant bits (LSb) of each user ID
location, the upper bits are not read. It is
recommended that only the 7 LSbs be
used if MPLAB IDE is the primary tool
used to read these addresses.
PIC16(L)F72X
DS41332D-page 10 2011 Microchip Technology Inc.
3.3 Configuration Words
The PIC16(L)F72X devices have two Configuration
Words, Configuration Word 1 (2007h) and
Configuration Word 2 (2008h). The individual bits
within these Co nfiguratio n Wor ds are used to enable or
disable device functions such as the Brown-out Reset,
code protection and Power-up Timer.
3.4 Calibration Words
For the PIC16(L)F72X devices, the 16 MHz internal
oscillator (INTOSC), and the Brown-out Reset (BOR),
are fact ory calibra ted and stored i n Calibratio n Words 1
and 2 (2009h and 200Ah).
The Calibration Words do not participate in erase
operat ions. The de vice can be erase d wit hout af fec ting
the Calibration Words.
TABLE 3-1: DEVICE ID VALUES
DEVICE DEVICE ID VALUES
DEV REV
PIC16F722 01 1000 100 x xxxx
PIC16F722A 01 1011 001 x xxxx
PIC16F723 01 1000 011 x xxxx
PIC16F723A 01 1011 000 x xxxx
PIC16F724 01 1000 010 x xxxx
PIC16F726 01 1000 001 x xxxx
PIC16F727 01 1000 000 x xxxx
PIC16LF722 01 1001 100 x xxxx
PIC16LF722A 01 1011 011 x xxxx
PIC16LF723 01 1001 011 x xxxx
PIC16LF723A 01 1011 010 x xxxx
PIC16LF724 01 1001 010 x xxxx
PIC16LF726 01 1001 001 x xxxx
PIC16LF727 01 1001 000 x xxxx
2011 Microchip Technology Inc. DS41332D-page 11
PIC16(L)F72X
REGISTER 3-1: CONFIGURATION WORD 1
R/P-1 R/P-1 U-1(2) R/P-1 R/P-1 R/P-1 U-1(2)
DEBUG(1) PLLEN — BORV BOREN1 BOREN0 —
bit 13
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0bit 0
Legend: P = Programmable x = Bit is unknown
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Default value ‘1’ = Bit is written to ‘1’ ‘0’ = Bit is written to ‘0’
bit 13 DEBUG: Debugger mode bit(1)
1 = Background debugger is disabled
0 = Background debugger is enabled
bit 12 PLLEN: INTOSC PLL Enable bit
1 = INTOSC frequency is 16 MHz
0 = INTOSC frequency is 500 kHz
bit 11 Unimplemented: Read as ‘1’
bit 10 BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset Voltage (VBOR) set to 1.9V
0 = Brown-out Reset Voltage (VBOR) set to 2.5V
bit 9-8 BOREN<1:0>: Brown-out Reset Enable bi ts
0x = Brown-out Reset disabled
10 = Brown-out Reset enabled during operation and disabled in Sleep
11 = Brown-out Reset enabled
bit 7 Unimplemented: Re ad as ‘1’
bit 6 CP: Flash Program Memory Code Protection bit
For PIC16F/LF726/727:
0 = 0000h to 1FFFh code protection on
1 = Code protection off
For PIC16F/LF723/723A/724:
0 = 0000h to 0FFFh code protection on
1 = Code protection off
For PIC16F/LF722/722A:
0 = 0000h to 07FFh code protection on
1 = Code protection off
bit 5 MCLRE: RE3/MCLR/VPP Pin Functi on Sele ct bit
1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled.
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
Note 1: DEBUG bit is ignored when code-protect is enabled (CP = 0).
2: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
PIC16(L)F72X
DS41332D-page 12 2011 Microchip Technology Inc.
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC wi th CLKO UT osci llator: CLKO fu nction on RA6/O SC2/ CLKO pi n, RC o n RA7/O SC1/CLKI
110 = RC NO CLKOUT oscillator: I/O function on RA6/OSC2/CLKO pin, RC on RA7/OSC1/CLKI
101 = INTOSC with CLKOUT oscillator: CLKO function on RA6/OSC2/CLKO pin, I/O function on
RA7/OSC1/CLKI
100 = INTOSC NO CLKOUT oscillator: I/O function on RA6/OSC2/CLKO pin, I/O function on
RA7/OSC1/CLKI
011 = EC oscillator: I/O function on RA6/ OSC2/CLKO pin, C LKI on RA7/OSC1/CLKI
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
001 = XT oscillator: Crysta l/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
REGISTER 3-1: CONFIGURATION WORD 1 (CONTINUED)
Note 1: DEBUG bit is ignored when code-protect is enabled (CP = 0).
2: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
REGISTER 3-2: CONFIGURATION WORD 2
U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1)
— — — — — — —
bit 13
U-1(1) R/P-1 R/P-1 U-1(1) U-1(1) U-1(1) U-1(1)
— VCAPEN1 VCAPEN0 — — — — bit 0
Legend: P = Programmable x = Bit is unknown
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Default value ‘1’ = Bit is written to ‘1’ ‘0’ = Bit is written to ‘0’
bit 13-6 Unimplemented: Re ad as ‘1’
bit 5-4 VCAPEN<1:0>: Voltage Regula tor Capacitor Enable bits
For PIC16LF72X:
These bits are ignored. All VCAP pin functions are disabled.
For PIC16F72X:
00 =VCAP functionality is enabled on RA0
01 =V
CAP functionality is enabled on RA5
10 =V
CAP functionality is enabled on RA6
11 = All VCAP pin functions are disabled
bit 3-0 Unimplemented: Read as ‘1’
Note 1: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
2011 Microchip Technology Inc. DS41332D-page 13
PIC16(L)F72X
4.0 PROGRAM/VERIFY MODE
In Program/V erify mode, the program memory and the
configuration memory can be accessed and pro-
grammed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
latched on the falling edge. In Program/Verify mode
both the IS CPDAT an d IC SPCLK are S chmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/O’s are automatically configured as high-impedance
inputs and the Progr am Counter (PC) is cleared.
4.1 Program/Verify Mode Entry and
Exit
There are 2 different methods of entering Program/
Verify mode:
•V
PP – First entry mode
•VDD – First entry mode
4.1.1 VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-fi rst metho d
the following sequence must be followed:
1. Hold ICSPCLK an d ICSPDAT low. All other pins
should be unpowered.
2. R aise the voltage o n MCLR from 0V to VIHH.
3. Raise the volt age on VDD fr om 0V to th e des ired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode (e.g., When
the Configuration Word has MCLR disabled (MCLRE = 0),
the power-up time disabled (PWR TE = 0), and the internal
oscillator is selected (FOSC = 10x), VPP-first entry mode is
strongly recommended for this reason. ICSPCLK or
ICSPDAT is driven high by the user code. See the timing
diagram in Figure 8-4.
4.1.2 VDD–FIRST ENTRY MODE
To enter Program/ Verify mode via the VDD-fir st metho d
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the volta ge on VDD from 0V to the desire d
operating voltage.
3. R aise the v oltage on MCLR from below V DD to
VPP.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-5.
4.1.3 PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower.
4.2 Program/Verify Commands
The PIC16F72X and PIC16LF72X devices implement
10 programming commands, each six bits in length.
The commands are summarized in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. Th e first cloc k is for the S t art bit an d the last cl ock
is for the Stop bit.
TABLE 4-1: COMMAND MAPPING FOR PIC16F72X
Command Mapping Data/Note
Binary (MSb … LSb) Hex
Load Configuration x0000000h 0, data (14), 0
Load Data For Program Memory x0001002h 0, data (14), 0
Read Data From Program Memory x0010004h 0, data (14), 0
Inc rement Address x0011006h
Reset Address x1011016h
Begin Internally Timed Programming x0100008h
Begin Extern all y Timed Programmin g x1100018h
End Externally Timed Programming x010100Ah
Bulk Erase Program Memory x0100109h Internally Timed
Row Era se Prog ram Memory x1000111h Internally Timed
PIC16(L)F72X
DS41332D-page 14 2011 Microchip Technology Inc.
4.2.1 LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (user ID locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the Program Counter
(PC) to address 2000h and loads the data latches with
one word of data.
Aft er issuing the Load Configurat ion command , use the
Increment Address command until the proper address
to be programmed is reached. The address is then
programmed by issuing either the Begin Internally
Timed Programming or Begin Externally Timed
Programming command.
After the configuration memory has been accessed by
the Load Configuration command, the only way to get
back to the program memory is to exit Program/Verify
mode or issue the Reset Address command.
FIGURE 4-1: LOAD CONFIGURATION
4.2.2 LOAD DATA FOR PROGRAM
MEMORY
The Load Da ta for Progra m Memo ry comm and is use d
to load one 14-b it w ord into t he da t a la tc hes . The word
in placed into program memory after the Begin
Internally Timed Programming or Begin Externally
Timed Programming command is issued.
FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY
X
00LSb MSb 0
123 4561215 16
ICSPCLK
ICSPDAT 0000
TDLY
ICSPCLK
ICSPDAT
123 4561215 16
X
00LSb MSb 0
0100
TDLY
2011 Microchip Technology Inc. DS41332D-page 15
PIC16(L)F72X
4.2.3 READ DATA FROM PROGRAM
MEMORY
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Ou tpu t m od e on the first falling clock edge, an d
it will revert to Input mode (high-impedance) after the
16th falli ng edge of the cloc k. If the program memory is
code-protected (CP), the data will be read as zeros.
FIGURE 4-3: READ DATA FROM PROGRAM MEMORY
4.2.4 INCREMENT ADDRESS
The Program Counter (PC) is incremented when this
command is received. It is not possible to decrement
the PC. To reset this counter, the user must exit
Program/Verify mode and re-enter it or use the Reset
Address co mm and.
FIGURE 4-4: INCREMENT ADDRESS
12345612 15
16
X
00 LSb MSb 0
0010
TDLY
ICSPCLK
ICSPDAT
Input Input
Output
X
0
12345612
ICSPCLK
ICSPDAT 011
3
XXX
TDLY
Next Command
0
PC + 1
PC
PIC16(L)F72X
DS41332D-page 16 2011 Microchip Technology Inc.
4.2.5 RESE T ADDRES S
After receiving this command the Program Counter
(PC) is se t to 0 000 h. Th e PC will be res et inde pe nde nt
of ad dressing the prog ram memory o r the configur ation
memory.
FIGURE 4-5: RESET ADDRESS
4.2.6 BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time
for the programming to complete. The addres s that is
being programmed is not erased prior to being
programmed.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
FIGURE 4-6: BEGIN INTERNALLY TIMED PROGRAMMING
X
0
123 45612
ICSPCLK
ICSPDAT 011
3
XXX
TDLY
Next Command
1
0000h
PC
123 4561
2
ICSPCLK
ICSPDAT
3
TPINT
X
1
000XXX
0
Next Command
2011 Microchip Technology Inc. DS41332D-page 17
PIC16(L)F72X
4.2.7 BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration, Load Data for Program Memory
or Load Dat a for Data Memory command must be given
before every Begin Programming command.
Programming of the addressed memory will begin after
this command is received. To complete the
progra mming of the addre ss, the End Exter nally T ime d
Programming command must be sent in the specified
time window defined by TPEXT.
The Begin Externally Timed Programming command
cannot be used for programming the Configuration
Words.
FIGURE 4-7: BEGIN EXTERNALLY TIMED PROGRAMMING
4.2.8 END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
comma nd, an addit ional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands.
FIGURE 4-8: END EXTERNALLY TIMED PROGRAMMING
X
10
123 4561
2
ICSPCLK
ICSPDAT 000110
End Externally Timed Programming
Command
TPEXT 3
123 4561
2
ICSPCLK
ICSPDAT
3
TDIS
X
1
010XXX
1
Next Command
PIC16(L)F72X
DS41332D-page 18 2011 Microchip Technology Inc.
4.2.9 BULK ERASE PROGRAM MEMORY
The Bulk Erase Program Memory command performs
two different functions, dependant on the current state
of the Program Count er (PC).
After receiving the Bulk Erase Program Memory
command, the erase will not complete until the time
interval, TERAB, has expired.
FIGURE 4-9: BULK ERASE PROGRAM MEMORY
4.2.10 ROW ERASE PROGRAM MEMORY
A row of program memory consists of 32 consecutive
14-bit words. A row is addressed by the Program
Coun ter PC< 13:5 >. The R ow Eras e Pro gram Mem ory
comma nd can b e used t o erase a n indivi dual row . If th e
program memory is code-protected the Row Erase
Program Memory comm and will be ignored. When the
PC is 2000h-2008h the Row Erase Program Memory
command will only erase the user ID locations,
independent of the setting of the CP Configuration bit.
After receiving the Row Erase Program Memory
command, the erase will not complete until the time
interval, TERAR, has expired.
FIGURE 4-10: ROW ERASE PROGRAM MEMORY
PC 0000h-1FFFh:
Program Memory is eras ed
Configuration words are erased
PC 2000h-2008h:
Program Memory is eras ed
Configuration Words are erased
User ID Locations are erased
Note 1: The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
Note 2: A Bulk Erase Program Memory com-
mand sh ou l d not be is su ed w hen t he PC
is greater than 2008h .
12345612
ICSPCLK
ICSPDAT
3
TERAB
X
1
100XXX
0
Next Command
12345612
ICSPCLK
ICSPDAT
3
TERAR
X
0
100XXX
1
Next Command
2011 Microchip Technology Inc. DS41332D-page 19
PIC16(L)F72X
5.0 PROGRAMMING ALGORITHMS
The PIC16(L)F72X devices have the capability of
storing ei ght 14-bit words in its data latches. The data
latches are internal to the PIC16(L)F72X devices and
are on ly u se d for p rogra mming. The data latc hes all ow
the user to program up to eight program words with a
single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration Word
command is used to load a single data latch. The data
latch will hold the data until Begin Externally Timed
Programming or Begin Internally Timed Programming
comma nd is given .
The data latches are aligned with the 3 LSb of the PC.
The addre ss of the PC, at t he time the Begin Externa lly
Timed Programming or Begin Internally Timed
Programming command is given, will determine which
location(s) in memory are written. Writes cannot cross
a physical eight-word boundary. For example,
attempting to write from PC 0002h-0009h will result in
data bei ng w ritte n to 0008h -000Fh.
If more than 8 data latches are written without a Begin
Externally Timed Programming or Begin Internally
Timed Programming command the data in the data
latches will be overwritten. The following diagrams
show the recommended flowcharts for programming.
FIGURE 5-1: ONE-WO RD PROGRAMMING FLOWCHART
Start
Program Cycle
All Locations
Done?
Begin
Programming
Wait TDIS
Program Cycle
No
Increment
Address
Command
Bulk Erase
Program
Load Data
for
Program Memory
Command
(Internally timed)
Begin
Programming
Wa it TPEXT
Command
(Externally timed)
End
Programming
Wait TPINT
One-word
Memory(1)
Done
Yes
Note 1: This step is optional if the device has already been erased or has not been previously programmed.
PIC16(L)F72X
DS41332D-page 20 2011 Microchip Technology Inc.
FIGURE 5-2: EIGHT-WORD PROGRAMMING FLOWCHART
Start
All Locations
Done?
Begin
Programming
Wai t TPINT
Program Cycle
No
Increment
Address
Command Load Data
for
Program Memory
Command
(Internally timed)
Wait TPEXT
End
Programming
Wai t TDIS
Load Data
for
Program Memory
Increment
Address
Command
Load Data
for
Program Memory
Eight-word
Program Cycle
Bul k Erase
Program
Memory(1)
Done
Yes
Begin
Programming
Command
(Externally timed)
Data
Data
Data
Increment
Address
Command
Note 1: This step is optional if the device is erased or not previously programmed.
Latch 1
Latch 2
Latch 8
2011 Microchip Technology Inc. DS41332D-page 21
PIC16(L)F72X
FIGURE 5- 3 : PROGRAM FL OWCH ART – PI C1 6F72X CONFIGURATION MEMORY
Start
Load
Configuration
Program Cycle
Read Data
Memory Command
Data Correct? Report
Programming
Failure
Address =
2004h?
Data Correct? Report
Programming
Failure
Yes
No
Yes
Yes
No
Increment
Address
Command
No Increment
Address
Command
Done
One-word
One-word
Program Cycle
(Config Word 1)
Begin
Programming
Wait TDIS
Program Cycle
Load Data
for
Program Memory
Command
(Internally timed)
Wait TPEXT
End
Programming
Wait TPINT
Increment
Address
Command
Increment
Address
Command
(User ID)
From Program
Read Data
Memory Command
From Program
Program
Bulk Erase
Memory(1)
Begin
Programming
Command
(Externally timed)
Data Correct? Report
Programming
Failure
Yes
No
One-word
Program Cycle
(Config Word 2)
Increment
Address
Command
Read Data
Memory Command
From Program
Note 1: This step is optional if the device is erased or not previously programmed.
PIC16(L)F72X
DS41332D-page 22 2011 Microchip Technology Inc.
FIGUR E 5- 4: V E RIFY FLOWCHART
Done
Start
Bulk Erase
Device
Write User IDs
Enter
Programming Mode
Write Program
Memory
Verify Program Memory
Verify User IDs
Write Configuration
Words
Verify Configuration
Words
Exit Programming Mode
2011 Microchip Technology Inc. DS41332D-page 23
PIC16(L)F72X
6.0 CODE PR OTEC TIO N
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled , all p rogram mem ory loca tions (00 00h-1FFFh)
read as all ‘0’. Further programming is disabled for the
program me mory (0000h-1 FFFh ).
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
prote cti on set tin gs.
6.1 Enabling Code Protection
Code prot ec tion is ena bl ed by progra mm in g the CP bit
in Configura tion Word 1 to ‘0’.
6.2 Disabling Code Protection
The only way to disable code protection is to use the
Bulk Er ase Pr ogram Memory co mmand.
PIC16(L)F72X
DS41332D-page 24 2011 Microchip Technology Inc.
7.0 HEX FILE USAGE
In the hex file there are two bytes per program word
stored in the Intel® INH8M hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: The
Configuration Word 1 is stored at 2007h on the
PIC16(L)F72X. In the hex file this will be at location
400Eh-400Fh).
7.1 Configuration Word
To allow port abil ity of c ode, it i s strongly recom mended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Config uration Wo rds information w as not present in th e
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
7.2 Device ID and Revision
If a device ID is prese nt in the hex file at 400C h-400 Dh
(2006h on the part), the programmer should verify the
device ID/rev isio n again st the v alue rea d from th e pa rt.
On a mismatch condition, the programmer should
generate a warning message.
7.3 Checksum Comput ation
The checksum is calculated by two different methods,
dependent on the setting of the CP Configuration bit.
7.3.1 CODE PROTECTION DISABLED
With the code protection disabled, the checksum is
computed by reading the contents of the PIC16(L)F72X
progra m mem ory lo ca tio ns and adding up the program
memory data, st arting at addres s 0000h, up to the max-
imum user addressable location (e.g., 1FFFH for the
PIC16F726). Any Carry bit exceeding 16 bits are
neglected. Additionally, the relevant bits of the Config-
uration Words are added to the checksum. All unused
Configuration bits are masked to ‘0’.
EXAMPLE 7-1: CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED, PIC16F726,
BLANK DEVICE
PIC16F726 Sum of Memory addresses 0000h-1FFFh E000h
Configuration Word 1 2AC3h
Configuration Word 1 mask 377Fh
Configuration Word 2 3FEFh
Configuration Word 2 mask 0030h
Checksum = E000h + (2AC3h and 377Fh) + (3FEFh and 0030h)
= E000h + 2243h + 0020h
= 0263h
2011 Microchip Technology Inc. DS41332D-page 25
PIC16(L)F72X
7.3.2 CODE PRO T E CT ION ENAB LED
With the code protection enabled, the checksum is
computed in the following manner. The Configuration
Words are summed (all unused Configuration bits are
masked to ‘0’) with the Least Significant nibble of the
user ID’s.
EXAMPLE 7-2: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED, PIC16F726,
BLANK DEVICE
PIC16F726 Configuration Word 1 2A83h
Configuration Word 1 mask 377Fh
Configuration Word 2 3FEFh
Configuration Word 2 mask 0030h
User ID (2000h ) 0123h
User ID (2001h ) 4567h
User ID (2002h) 89ABh
User ID (2003h ) CDEFh
Sum of User IDs = (0003h and 000Fh) << 12 + (0007h and 000Fh) << 8 +
(000Bh and 000Fh) << 4 + (000Fh and 000Fh)
= 3000h + 0700h +00B0h + 000Fh
= 37BFh
Checksum = (2A83h and 377Fh) + (3FEFh and 0030h) + Sum of User IDs
= 2203h + 0020h + 37BFh
= 59E2h
PIC16(L)F72X
DS41332D-page 26 2011 Microchip Technology Inc.
8.0 ELECTRICAL SPECIFICATIONS
Refer to the device specific data sheet for absolute
maximum ratings.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating Temperature +10°C TA +40°C
Sym. Characteristics Min. Type. Max. Units Conditions/Comments
Supply Volta ges and curren ts
VDD
VDD PIC16F72X (excluding Bulk Erase) 1.8 — 5.5 V
PIC16LF72X (excluding Bulk Erase) 1.8 — 3.6 V
PIC16(L)F72X Bulk Erase 2.7 — V
IDDI Current on VDD, Idle 1.0 mA
IDDA Current on VDD, program cycle or
Bulk Erase in progress 5.0 mA
VIHH VPP
High voltage on MCLR/VPP for
Program/Verify mode entry 8.0 — 9.0 V
TVHHR MCLR rise time (VDD to VIHH) for
Program/Verify mode entry ——1.0s
IPP Current on MCLR/VPP 5.0 mA
I/O pins
VIH (ICSPCLK, ICSPDAT) input high
level 0.8 VDD ——V
VIL (ICSPCLK, ICSPDAT) input low leve l — — 0.2 VDD V
VOH ICSPDAT output high level VDD-0.7
VDD-0.7
VDD-0.7 VDD VIOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
VOL ICSPDAT output low level VSS VSS+0.6
VSS+0.6
VSS+0.6 VIOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
Programming mo de entry and ex it
TENTS Programing mode entry setup time:
ICSPCLK, ICSPDAT setup time
before VDD or MCLR 100 — — ns
TENTH Programing mode entry hold time:
ICSPCLK, ICSPDAT hold time after
VDD or MCLR 250 s
Serial Program/Verify
TCKL Clock Low Pulse Width 100 — — ns
TCKH Clock High Pulse Width 100 — — ns
TDS Data in setup time before clock100 — — ns
TDH Data in hold time after clock100 — — ns
TCO Clock to data out valid (during a
Read Data command) 0 — 80 ns
TLZD Clock to data low-impedance
(during a Read Data command) 0 — 80 ns
THZD Clock to data high-impedance
(during a Read Data command) 0 — 80 ns
2011 Microchip Technology Inc. DS41332D-page 27
PIC16(L)F72X
TDLY
Data input not driven to next clock
input (delay required between
command/data or command/
command)
1.0 — — s
TERAB Bulk Erase cycle time — — 5 ms
TERAR Row Erase cycle time — — 2.5 ms
TPINT Internally timed programming
operation time —
——
—2.5
5ms
ms Program memory
Configuration fuses
TPEXT Externally timed programming pulse 1.0 — 2.1 ms 10°C TA +40°C
Program memory
TDIS Time delay from program to compare
(HV discharge time) 100 — — s
TEXIT Time delay when exiting
Program/Verify mode 1——s
TABLE 8-1: AC/DC CHARACTERISTICS TI MING REQUIREMENTS FOR PROGRAM/VERIFY
MODE (CONTINUED)
AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating Temperature +10°C TA +40°C
Sym. Characteristics Min. Type. Max. Units Conditions/Comments
PIC16(L)F72X
DS41332D-page 28 2011 Microchip Technology Inc.
8.1 AC Timing Diagrams
FIGURE 8-2: PROGRAMMING MODE
ENTRY – VDD FIRST
FIGURE 8-3: PROGRAMMING MODE
ENTRY – VPP FIRST
FIGURE 8-4: PROGRAMMING MODE
EXIT – VPP LAST
FIGURE 8-5: PROGRAMMING MODE
EXIT – VDD LAST
FIGURE 8-6: CLOCK AND DATA
TIMING
VPP
TENTH
VDD
TENTS
ICSPDAT
ICSPCLK
VIHH
VIL
VDD
TENTH
ICSPDAT
ICSPCLK
VDD
TENTS
VPP
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
VDD
as
ICSPCLK
TCKH TCKL
TDH
TDS
ICSPDAT
Output
TCO
ICSPDAT
ICSPDAT
ICSPDAT
TLZD
THZD
Input
as
from In p u t
from Output
to Input
to Output
2011 Microchip Technology Inc. DS41332D-page 29
PIC16(L)F72X
FIGURE 8-7: COMMAND-PAYLOAD TIMING
123 4561215 16
X0LSb MSb 0
TDLY
Command Next
Command
Payload
ICSPCLK
ICSPDAT XXXXX
PIC16(L)F72X
DS41332D-page 30 2011 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision A (11/2007)
Original release of this document.
Revision B (02/2009)
Updated minimum VDD for Bulk Erase in Table 8-1.
Various minor edits.
Clarified time of transi tion from inp ut to output in Figu re
4-3.
Corrected Reserved area range in Figures 3-1, 3-2,
and 3-3.
Corrected low-voltage range for Programming modes
shown in Figures 8-3 and 8-5.
Revision C (02/2010)
Added PIC16F722A, PIC16F723A, PIC16LF722A and
PIC16LF723A devices to the Programming
Specification; Other minor edits.
Revision D (03/2011)
Updated spec. to new format; Updated Figure 2-2 to
add UQFN; Added Figu re 2-6; Added Note 2 to Regis-
ter 3-1, and Note 1 to Register 3-2; Revised Examples
7-1 and 7-2.
2011 Microchip Technology Inc. DS41332D-page 31
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil i ty to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, M XLA B, SE EVAL and The Em bedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE, In-Circu it Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-083-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopp ing
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41332D-page 32 2011 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792- 7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957- 9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760- 0087
Fax: 774-760-0088
Chicago
Itasc a , IL
Tel: 630-285- 0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447- 0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818- 7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538- 2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773- 8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462- 9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961- 6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673- 0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921- 5869
Fax: 44-118-921-5820
Worldwide Sales and Service
02/18/11
