MT40A512M16LY-062E IT:E TR - MICRON TECHNOLOGY

DDR4 SDRAM

MT40A2G4

MT40A1G8

MT40A512M16

Features

•V

DD = VDDQ = 1.2V ±60mV

•V

PP = 2.5V, –125mV, +250mV

• On-die, internal, adjustable VREFDQ generation

• 1.2V pseudo open-drain I/O

• Refresh time of 8192-cycle at TC temperature range:

– 64ms at -40°C to 85°C

– 32ms at >85°C to 95°C

– 16ms at >95°C to 105°C

• 16 internal banks (x4, x8): 4 groups of 4 banks each

• 8 internal banks (x16): 2 groups of 4 banks each

•8n-bit prefetch architecture

• Programmable data strobe preambles

• Data strobe preamble training

• Command/Address latency (CAL)

• Multipurpose register READ and WRITE capability

• Write leveling

• Self refresh mode

• Low-power auto self refresh (LPASR)

• Temperature controlled refresh (TCR)

• Fine granularity refresh

• Self refresh abort

• Maximum power saving

• Output driver calibration

• Nominal, park, and dynamic on-die termination

(ODT)

• Data bus inversion (DBI) for data bus

• Command/Address (CA) parity

• Databus write cyclic redundancy check (CRC)

• Per-DRAM addressability

• Connectivity test

• JEDEC JESD-79-4 compliant

• sPPR and hPPR capability

• MBIST-PPR support (Die Revision R only)

Options1Marking

• Configuration

– 2 Gig x 4 2G4

– 1 Gig x 8 1G8

– 512 Meg x 16 512M16

• 78-ball FBGA package (Pb-free) – x4,

– 9mm x 13.2mm – Rev. A PM

– 8mm x 12mm – Rev. B, D, G WE

– 7.5mm x 11mm – Rev. E, H, J, R SA

• 96-ball FBGA package (Pb-free) – x16

– 9mm x 14mm – Rev. A HA

– 8mm x 14mm – Rev. B JY

– 7.5mm x 13.5mm – Rev. D, E, H LY

– 7.5mm x 13mm – Rev. J, R TB

• Timing – cycle time

– 0.625ns @ CL = 22 (DDR4-3200) -062E

– 0.682ns @ CL = 21 (DDR4-2933) -068

– 0.750ns @ CL = 19 (DDR4-2666) -075

– 0.750ns @ CL = 18 (DDR4-2666) -075E

– 0.833ns @ CL = 17 (DDR4-2400) -083

– 0.833ns @ CL = 16 (DDR4-2400) -083E

– 0.937ns @ CL = 15 (DDR4-2133) -093E

– 1.071ns @ CL = 13 (DDR4-1866) -107E

• Operating temperature

– Commercial (0° ื TC ื 95°C) None

– Industrial (–40° ื TC ื 95°C) IT

– Automotive (–40° ื TC ื 105°C) AT

• Revision :A, :B, :D, :E,

:G, :H, :J, :R

Note: 1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade1Data Rate (MT/s) Target CL-nRCD-nRP tAA (ns) tRCD (ns) tRP (ns)

-062Y 3200 22-22-22 13.75 (13.32) 13.75 (13.32) 13.75 (13.32)

-062E 3200 22-22-22 13.75 13.75 13.75

-068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75)

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 1: Key Timing Parameters (Continued)

Speed Grade1Data Rate (MT/s) Target CL-nRCD-nRP tAA (ns) tRCD (ns) tRP (ns)

-075E 2666 18-18-18 13.50 13.50 13.50

-075 2666 19-19-19 14.25 (13.75) 14.25 (13.75) 14.25 (13.75)

-083E 2400 16-16-16 13.32 13.32 13.32

-083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75)

-093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50)

-093 2133 16-16-16 15.00 15.00 15.00

-107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50)

Note: 1. Refer to the Speed Bin Tables for additional details.

Table 2: Addressing

Parameter 2048 Meg x 4 1024 Meg x 8 512 Meg x 16

Number of bank groups 4 4 2

Bank group address BG[1:0] BG[1:0] BG0

Bank count per group 4 4 4

Bank address in bank group BA[1:0] BA[1:0] BA[1:0]

Row addressing 128K (A[16:0]) 64K (A[15:0]) 64K (A[15:0])

Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])

Page size1512B 1KB 2KB

Note: 1. Page size is per bank, calculated as follows:

Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of

DQ bits.

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 1: Order Part Number Example

Example Part Number: MT40A1G8SA-062E:R

Configuration

2 Gig x 4 2G8

1 Gig x 8

512 Meg x 16

1G8

512M16

Configuration

MT40A Package Speed

Revision

{

Package

Mark

78-ball 9.0mm x 13.2mm FBGA

78-ball 8.0mm x 12.0mm FBGA

78-ball 7.5mm x 11.0mm FBGA

96-ball 9.0mm x 14.0mm FBGA

96-ball 8.0mm x 14.0mm FBGA

96-ball 7.5mm x 13.5mm FBGA

96-ball 7.5mm x 13.0mm FBGA

:A, :B, :D, :G, :E, :H, :J, :R

Die Revision

Speed

Grade

-107E

-093E

tCK = 1.071ns, CL = 13

tCK = 0.937ns, CL = 15

-083E tCK = 0.833ns, CL = 16

-083 tCK = 0.833ns, CL = 17

-075E tCK = 0.750ns, CL = 18

-075 tCK = 0.750ns, CL = 19

-068 t

CK = 0.682ns, CL = 21

-062E CK = 0.625ns, CL = 22

Cycle Time, CAS Latency

Commercial

Industrial

Extended

None

Case Temperature Mark

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Contents

Important Notes and Warnings ....................................................................................................................... 19

General Notes and Description ....................................................................................................................... 19

Description ................................................................................................................................................ 19

Industrial Temperature ............................................................................................................................... 20

Automotive Temperature ............................................................................................................................ 20

General Notes ............................................................................................................................................ 20

Definitions of the Device-Pin Signal Level ................................................................................................... 21

Definitions of the Bus Signal Level ............................................................................................................... 21

Functional Block Diagrams ............................................................................................................................. 22

Ball Assignments ............................................................................................................................................ 24

Ball Descriptions ............................................................................................................................................ 26

Package Dimensions ....................................................................................................................................... 29

State Diagram ................................................................................................................................................ 36

Functional Description ................................................................................................................................... 38

RESET and Initialization Procedure ................................................................................................................. 39

Power-Up and Initialization Sequence ......................................................................................................... 39

RESET Initialization with Stable Power Sequence ......................................................................................... 42

Uncontrolled Power-Down Sequence .......................................................................................................... 43

Programming Mode Registers ......................................................................................................................... 44

Mode Register 0 .............................................................................................................................................. 47

Burst Length, Type, and Order ..................................................................................................................... 48

CAS Latency ............................................................................................................................................... 49

Test Mode .................................................................................................................................................. 50

Write Recovery (WR)/READ-to-PRECHARGE ............................................................................................... 50

DLL RESET ................................................................................................................................................. 50

Mode Register 1 .............................................................................................................................................. 51

DLL Enable/DLL Disable ............................................................................................................................ 52

Output Driver Impedance Control ............................................................................................................... 53

ODT RTT(NOM) Values .................................................................................................................................. 53

Additive Latency ......................................................................................................................................... 53

Rx CTLE Control ......................................................................................................................................... 53

Write Leveling ............................................................................................................................................ 54

Output Disable ........................................................................................................................................... 54

Termination Data Strobe ............................................................................................................................. 54

Mode Register 2 .............................................................................................................................................. 55

CAS WRITE Latency .................................................................................................................................... 57

Low-Power Auto Self Refresh ....................................................................................................................... 57

Dynamic ODT ............................................................................................................................................ 57

Write Cyclic Redundancy Check Data Bus .................................................................................................... 57

Mode Register 3 .............................................................................................................................................. 58

Multipurpose Register ................................................................................................................................ 59

WRITE Command Latency When CRC/DM is Enabled ................................................................................. 60

Fine Granularity Refresh Mode .................................................................................................................... 60

Temperature Sensor Status ......................................................................................................................... 60

Per-DRAM Addressability ........................................................................................................................... 60

Gear-Down Mode ....................................................................................................................................... 60

Mode Register 4 .............................................................................................................................................. 61

Hard Post Package Repair Mode .................................................................................................................. 62

Soft Post Package Repair Mode .................................................................................................................... 62

WRITE Preamble ........................................................................................................................................ 63

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

READ Preamble .......................................................................................................................................... 63

READ Preamble Training ............................................................................................................................ 63

Temperature-Controlled Refresh ................................................................................................................. 63

Command Address Latency ........................................................................................................................ 63

Internal VREF Monitor ................................................................................................................................. 63

Maximum Power Savings Mode ................................................................................................................... 64

MBIST-PPR ................................................................................................................................................ 64

Mode Register 5 .............................................................................................................................................. 65

Data Bus Inversion ..................................................................................................................................... 66

Data Mask .................................................................................................................................................. 67

CA Parity Persistent Error Mode .................................................................................................................. 67

ODT Input Buffer for Power-Down .............................................................................................................. 67

CA Parity Error Status ................................................................................................................................. 67

CRC Error Status ......................................................................................................................................... 67

CA Parity Latency Mode .............................................................................................................................. 67

Mode Register 6 .............................................................................................................................................. 68

Data Rate Programming .............................................................................................................................. 69

VREFDQ Calibration Enable .......................................................................................................................... 69

VREFDQ Calibration Range ........................................................................................................................... 69

VREFDQ Calibration Value ............................................................................................................................ 69

Truth Tables ................................................................................................................................................... 70

NOP Command .............................................................................................................................................. 73

DESELECT Command .................................................................................................................................... 73

DLL-Off Mode ................................................................................................................................................ 73

DLL-On/Off Switching Procedures .................................................................................................................. 75

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 75

DLL-Off to DLL-On Procedure .................................................................................................................... 77

Input Clock Frequency Change ....................................................................................................................... 78

Write Leveling ................................................................................................................................................ 79

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 80

Procedure Description ................................................................................................................................ 81

Write Leveling Mode Exit ............................................................................................................................ 82

Command Address Latency ............................................................................................................................ 84

Low-Power Auto Self Refresh Mode ................................................................................................................. 89

Manual Self Refresh Mode .......................................................................................................................... 89

Multipurpose Register .................................................................................................................................... 91

MPR Reads ................................................................................................................................................. 92

MPR Readout Format ................................................................................................................................. 94

MPR Readout Serial Format ........................................................................................................................ 94

MPR Readout Parallel Format ..................................................................................................................... 95

MPR Readout Staggered Format .................................................................................................................. 96

MPR READ Waveforms ............................................................................................................................... 97

MPR Writes ................................................................................................................................................ 99

MPR WRITE Waveforms ............................................................................................................................. 100

MPR REFRESH Waveforms ........................................................................................................................ 101

Gear-Down Mode .......................................................................................................................................... 104

Maximum Power-Saving Mode ....................................................................................................................... 107

Maximum Power-Saving Mode Entry .......................................................................................................... 107

Maximum Power-Saving Mode Entry in PDA .............................................................................................. 108

CKE Transition During Maximum Power-Saving Mode ................................................................................ 108

Maximum Power-Saving Mode Exit ............................................................................................................ 108

Command/Address Parity .............................................................................................................................. 110

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

Per-DRAM Addressability .............................................................................................................................. 118

VREFDQ Calibration ........................................................................................................................................ 121

VREFDQ Range and Levels ........................................................................................................................... 122

VREFDQ Step Size ........................................................................................................................................ 122

VREFDQ Increment and Decrement Timing .................................................................................................. 123

VREFDQ Target Settings ............................................................................................................................... 127

Connectivity Test Mode ................................................................................................................................. 129

Pin Mapping ............................................................................................................................................. 129

Minimum Terms Definition for Logic Equations ......................................................................................... 130

Logic Equations for a x4 Device .................................................................................................................. 130

Logic Equations for a x8 Device .................................................................................................................. 131

Logic Equations for a x16 Device ................................................................................................................ 131

CT Input Timing Requirements .................................................................................................................. 131

Excessive Row Activation ............................................................................................................................... 133

Post Package Repair ....................................................................................................................................... 134

Post Package Repair ................................................................................................................................... 134

Hard Post Package Repair .............................................................................................................................. 135

hPPR Row Repair - Entry ............................................................................................................................ 135

hPPR Row Repair – WRA Initiated (REF Commands Allowed) ...................................................................... 136

hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ................................................................. 137

sPPR Row Repair ........................................................................................................................................... 139

MBIST-PPR ................................................................................................................................................... 142

MBIST-PPR Procedure ............................................................................................................................... 142

hPPR/sPPR/MBIST-PPR Support Identifier ..................................................................................................... 144

ACTIVATE Command .................................................................................................................................... 144

PRECHARGE Command ................................................................................................................................ 145

REFRESH Command ..................................................................................................................................... 146

Temperature-Controlled Refresh Mode .......................................................................................................... 148

Normal Temperature Mode ........................................................................................................................ 148

Extended Temperature Mode ..................................................................................................................... 148

Fine Granularity Refresh Mode ....................................................................................................................... 151

Mode Register and Command Truth Table .................................................................................................. 151

tREFI and tRFC Parameters ........................................................................................................................ 151

Changing Refresh Rate ............................................................................................................................... 154

Usage with TCR Mode ................................................................................................................................ 154

Self Refresh Entry and Exit ......................................................................................................................... 154

SELF REFRESH Operation .............................................................................................................................. 156

Self Refresh Abort ...................................................................................................................................... 158

Self Refresh Exit with NOP Command ......................................................................................................... 159

Power-Down Mode ........................................................................................................................................ 161

Power-Down Clarifications – Case 1 ........................................................................................................... 166

Power-Down Entry, Exit Timing with CAL ................................................................................................... 167

ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 169

CRC Write Data Feature ................................................................................................................................. 171

CRC Write Data ......................................................................................................................................... 171

WRITE CRC DATA Operation ...................................................................................................................... 171

DBI_n and CRC Both Enabled .................................................................................................................... 172

DM_n and CRC Both Enabled .................................................................................................................... 172

DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 172

CRC and Write Preamble Restrictions ......................................................................................................... 172

CRC Simultaneous Operation Restrictions .................................................................................................. 172

CRC Polynomial ........................................................................................................................................ 172

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.

CRC Combinatorial Logic Equations .......................................................................................................... 173

Burst Ordering for BL8 ............................................................................................................................... 174

CRC Data Bit Mapping ............................................................................................................................... 174

CRC Enabled With BC4 .............................................................................................................................. 175

CRC with BC4 Data Bit Mapping ................................................................................................................ 175

CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 178

CRC Error Handling ................................................................................................................................... 179

CRC Write Data Flow Diagram ................................................................................................................... 181

Data Bus Inversion ........................................................................................................................................ 182

DBI During a WRITE Operation .................................................................................................................. 182

DBI During a READ Operation ................................................................................................................... 183

Data Mask ..................................................................................................................................................... 184

Programmable Preamble Modes and DQS Postambles .................................................................................... 186

WRITE Preamble Mode .............................................................................................................................. 186

READ Preamble Mode ............................................................................................................................... 189

READ Preamble Training ........................................................................................................................... 189

WRITE Postamble ...................................................................................................................................... 190

READ Postamble ....................................................................................................................................... 190

Bank Access Operation .................................................................................................................................. 192

READ Operation ............................................................................................................................................ 196

Read Timing Definitions ............................................................................................................................ 196

Read Timing – Clock-to-Data Strobe Relationship ....................................................................................... 197

Read Timing – Data Strobe-to-Data Relationship ........................................................................................ 199

tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 200

tRPRE Calculation ..................................................................................................................................... 201

tRPST Calculation ...................................................................................................................................... 202

READ Burst Operation ............................................................................................................................... 203

READ Operation Followed by Another READ Operation .............................................................................. 205

READ Operation Followed by WRITE Operation .......................................................................................... 210

READ Operation Followed by PRECHARGE Operation ................................................................................ 216

READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 219

READ Operation with Command/Address Parity (CA Parity) ........................................................................ 220

READ Followed by WRITE with CRC Enabled .............................................................................................. 222

READ Operation with Command/Address Latency (CAL) Enabled ............................................................... 223

WRITE Operation .......................................................................................................................................... 225

Write Timing Definitions ........................................................................................................................... 225

Write Timing – Clock-to-Data Strobe Relationship ...................................................................................... 225

tWPRE Calculation .................................................................................................................................... 227

tWPST Calculation ..................................................................................................................................... 228

Write Timing – Data Strobe-to-Data Relationship ........................................................................................ 228

WRITE Burst Operation ............................................................................................................................. 232

WRITE Operation Followed by Another WRITE Operation ........................................................................... 234

WRITE Operation Followed by READ Operation .......................................................................................... 240

WRITE Operation Followed by PRECHARGE Operation ............................................................................... 244

WRITE Operation with WRITE DBI Enabled ................................................................................................ 247

WRITE Operation with CA Parity Enabled ................................................................................................... 249

WRITE Operation with Write CRC Enabled ................................................................................................. 250

Write Timing Violations ................................................................................................................................. 255

Motivation ................................................................................................................................................ 255

Data Setup and Hold Violations ................................................................................................................. 255

Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 255

ZQ CALIBRATION Commands ....................................................................................................................... 256

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

On-Die Termination ...................................................................................................................................... 258

ODT Mode Register and ODT State Table ........................................................................................................ 258

ODT Read Disable State Table .................................................................................................................... 259

Synchronous ODT Mode ................................................................................................................................ 260

ODT Latency and Posted ODT .................................................................................................................... 260

Timing Parameters .................................................................................................................................... 260

ODT During Reads .................................................................................................................................... 262

Dynamic ODT ............................................................................................................................................... 263

Functional Description .............................................................................................................................. 263

Asynchronous ODT Mode .............................................................................................................................. 266

Electrical Specifications ................................................................................................................................. 267

Absolute Ratings ........................................................................................................................................ 267

DRAM Component Operating Temperature Range ...................................................................................... 267

Electrical Characteristics – AC and DC Operating Conditions .......................................................................... 268

Supply Operating Conditions ..................................................................................................................... 268

Leakages ................................................................................................................................................... 269

VREFCA Supply ............................................................................................................................................ 269

VREFDQ Supply and Calibration Ranges ....................................................................................................... 270

VREFDQ Ranges ........................................................................................................................................... 271

Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels .............................................. 272

RESET_n Input Levels ................................................................................................................................ 272

Command/Address Input Levels ................................................................................................................ 272

Command, Control, and Address Setup, Hold, and Derating ........................................................................ 274

Data Receiver Input Requirements ............................................................................................................. 276

Connectivity Test (CT) Mode Input Levels .................................................................................................. 280

Electrical Characteristics – AC and DC Differential Input Measurement Levels ................................................. 284

Differential Inputs ..................................................................................................................................... 284

Single-Ended Requirements for CK Differential Signals ............................................................................... 285

Slew Rate Definitions for CK Differential Input Signals ................................................................................ 286

CK Differential Input Cross Point Voltage .................................................................................................... 287

DQS Differential Input Signal Definition and Swing Requirements .............................................................. 288

DQS Differential Input Cross Point Voltage ................................................................................................. 290

Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 291

Electrical Characteristics – Overshoot and Undershoot Specifications ............................................................. 293

Address, Command, and Control Overshoot and Undershoot Specifications ................................................ 293

Clock Overshoot and Undershoot Specifications ......................................................................................... 294

Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 295

Electrical Characteristics – AC and DC Output Measurement Levels ................................................................ 295

Single-Ended Outputs ............................................................................................................................... 295

Differential Outputs .................................................................................................................................. 297

Reference Load for AC Timing and Output Slew Rate ................................................................................... 298

Connectivity Test Mode Output Levels ........................................................................................................ 299

Electrical Characteristics – AC and DC Output Driver Characteristics ............................................................... 300

Connectivity Test Mode Output Driver Electrical Characteristics ................................................................. 300

Output Driver Electrical Characteristics ..................................................................................................... 302

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 305

Alert Driver ............................................................................................................................................... 305

Electrical Characteristics – On-Die Termination Characteristics ...................................................................... 306

ODT Levels and I-V Characteristics ............................................................................................................ 306

ODT Temperature and Voltage Sensitivity ................................................................................................... 308

ODT Timing DefinitionsODT Timing Definitions and Waveforms ................................................................ 308

DRAM Package Electrical Specifications ......................................................................................................... 312

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

Thermal Characteristics ................................................................................................................................. 316

Current Specifications – Measurement Conditions .......................................................................................... 317

IDD, IPP, and IDDQ Measurement Conditions ................................................................................................ 317

IDD Definitions .......................................................................................................................................... 319

Current Specifications – Patterns and Test Conditions ..................................................................................... 323

Current Test Definitions and Patterns ......................................................................................................... 323

IDD Specifications ...................................................................................................................................... 332

Current Specifications – Limits ....................................................................................................................... 333

Speed Bin Tables ........................................................................................................................................... 354

Backward Compatibility ............................................................................................................................ 354

Refresh Parameters By Device Density ............................................................................................................ 373

AC Electrical Characteristics and AC Timing Parameters ................................................................................. 374

Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 ........................................................ 387

Converting Time-Based Specifications to Clock-Based Requirements .............................................................. 398

Options Tables .............................................................................................................................................. 400

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Figures

Figure 1: Order Part Number Example .............................................................................................................. 3

Figure 2: 2 Gig x 4 Functional Block Diagram .................................................................................................. 22

Figure 3: 1 Gig x 8 Functional Block Diagram .................................................................................................. 22

Figure 4: 512 Meg x 16 Functional Block Diagram ........................................................................................... 23

Figure 5: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 24

Figure 6: 96-Ball x16 Ball Assignments ............................................................................................................ 25

Figure 7: 78-Ball FBGA – x4, x8 (PM) ............................................................................................................... 29

Figure 8: 78-Ball FBGA – x4, x8 (WE) ............................................................................................................... 30

Figure 9: 78-Ball FBGA – x4, x8 (SA) ................................................................................................................ 31

Figure 10: 96-Ball FBGA – x16 (HA) ................................................................................................................. 32

Figure 11: 96-Ball FBGA – x16 (JY) .................................................................................................................. 33

Figure 12: 96-Ball FBGA – x16 (LY) .................................................................................................................. 34

Figure 13: 96-Ball FBGA – x16 (TB) ................................................................................................................. 35

Figure 14: Simplified State Diagram ............................................................................................................... 36

Figure 15: RESET and Initialization Sequence at Power-On Ramping ............................................................... 42

Figure 16: RESET Procedure at Power Stable Condition ................................................................................... 43

Figure 17: tMRD Timing ................................................................................................................................ 45

Figure 18: tMOD Timing ................................................................................................................................ 45

Figure 19: DLL-Off Mode Read Timing Operation ........................................................................................... 74

Figure 20: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 76

Figure 21: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 77

Figure 22: Write Leveling Concept, Example 1 ................................................................................................ 79

Figure 23: Write Leveling Concept, Example 2 ................................................................................................ 80

Figure 24: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 82

Figure 25: Write Leveling Exit ......................................................................................................................... 83

Figure 26: CAL Timing Definition ................................................................................................................... 84

Figure 27: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 84

Figure 28: CAL Enable Timing – tMOD_CAL ................................................................................................... 85

Figure 29: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 85

Figure 30: CAL Enabling MRS to Next MRS Command, tMRD_CAL .................................................................. 86

Figure 31: tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 86

Figure 32: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group ............................................... 87

Figure 33: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group ............................................... 87

Figure 34: Auto Self Refresh Ranges ................................................................................................................ 90

Figure 35: MPR Block Diagram ....................................................................................................................... 91

Figure 36: MPR READ Timing ........................................................................................................................ 97

Figure 37: MPR Back-to-Back READ Timing ................................................................................................... 98

Figure 38: MPR READ-to-WRITE Timing ........................................................................................................ 99

Figure 39: MPR WRITE and WRITE-to-READ Timing ..................................................................................... 100

Figure 40: MPR Back-to-Back WRITE Timing ................................................................................................. 101

Figure 41: REFRESH Timing .......................................................................................................................... 101

Figure 42: READ-to-REFRESH Timing ........................................................................................................... 102

Figure 43: WRITE-to-REFRESH Timing ......................................................................................................... 102

Figure 44: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) ......................................................... 105

Figure 45: Clock Mode Change After Exiting Self Refresh ................................................................................ 105

Figure 46: Comparison Between Gear-Down Disable and Gear-Down Enable ................................................. 106

Figure 47: Maximum Power-Saving Mode Entry ............................................................................................. 107

Figure 48: Maximum Power-Saving Mode Entry with PDA .............................................................................. 108

Figure 49: Maintaining Maximum Power-Saving Mode with CKE Transition ................................................... 108

Figure 50: Maximum Power-Saving Mode Exit ............................................................................................... 109

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 51: Command/Address Parity Operation ............................................................................................. 110

Figure 52: Command/Address Parity During Normal Operation ..................................................................... 112

Figure 53: Persistent CA Parity Error Checking Operation ............................................................................... 113

Figure 54: CA Parity Error Checking – SRE Attempt ........................................................................................ 113

Figure 55: CA Parity Error Checking – SRX Attempt ........................................................................................ 114

Figure 56: CA Parity Error Checking – PDE/PDX ............................................................................................ 114

Figure 57: Parity Entry Timing Example – tMRD_PAR ..................................................................................... 115

Figure 58: Parity Entry Timing Example – tMOD_PAR ..................................................................................... 115

Figure 59: Parity Exit Timing Example – tMRD_PAR ....................................................................................... 115

Figure 60: Parity Exit Timing Example – tMOD_PAR ....................................................................................... 116

Figure 61: CA Parity Flow Diagram ................................................................................................................ 117

Figure 62: PDA Operation Enabled, BL8 ........................................................................................................ 119

Figure 63: PDA Operation Enabled, BC4 ........................................................................................................ 119

Figure 64: MRS PDA Exit ............................................................................................................................... 120

Figure 65: VREFDQ Voltage Range ................................................................................................................... 121

Figure 66: Example of VREF Set Tolerance and Step Size .................................................................................. 123

Figure 67: VREFDQ Timing Diagram for VREF,time Parameter .............................................................................. 124

Figure 68: VREFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 125

Figure 69: VREF Step: Single Step Size Increment Case .................................................................................... 126

Figure 70: VREF Step: Single Step Size Decrement Case ................................................................................... 126

Figure 71: VREF Full Step: From VREF,min to VREF,maxCase .................................................................................. 127

Figure 72: VREF Full Step: From VREF,max to VREF,minCase .................................................................................. 127

Figure 73: VREFDQ Equivalent Circuit ............................................................................................................. 128

Figure 74: Connectivity Test Mode Entry ....................................................................................................... 132

Figure 75: hPPR WRA – Entry ........................................................................................................................ 137

Figure 76: hPPR WRA – Repair and Exit ......................................................................................................... 137

Figure 77: hPPR WR – Entry .......................................................................................................................... 138

Figure 78: hPPR WR – Repair and Exit ............................................................................................................ 138

Figure 79: sPPR – Entry ................................................................................................................................. 141

Figure 80: sPPR – Repair, and Exit ................................................................................................................. 141

Figure 81: MBIST-PPR Sequence ................................................................................................................... 143

Figure 82: tRRD Timing ................................................................................................................................ 145

Figure 83: tFAW Timing ................................................................................................................................. 145

Figure 84: REFRESH Command Timing ......................................................................................................... 147

Figure 85: Postponing REFRESH Commands (Example) ................................................................................. 147

Figure 86: Pulling In REFRESH Commands (Example) ................................................................................... 147

Figure 87: TCR Mode Example1 ..................................................................................................................... 150

Figure 88: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 153

Figure 89: OTF REFRESH Command Timing ................................................................................................. 154

Figure 90: Self Refresh Entry/Exit Timing ...................................................................................................... 157

Figure 91: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 158

Figure 92: Self Refresh Abort ......................................................................................................................... 159

Figure 93: Self Refresh Exit with NOP Command ............................................................................................ 160

Figure 94: Active Power-Down Entry and Exit ................................................................................................ 162

Figure 95: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 163

Figure 96: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 163

Figure 97: Power-Down Entry After Write ...................................................................................................... 164

Figure 98: Precharge Power-Down Entry and Exit .......................................................................................... 164

Figure 99: REFRESH Command to Power-Down Entry ................................................................................... 165

Figure 100: Active Command to Power-Down Entry ....................................................................................... 165

Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry ................................................ 166

Figure 102: MRS Command to Power-Down Entry ......................................................................................... 166

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 103: Power-Down Entry/Exit Clarifications – Case 1 ............................................................................ 167

Figure 104: Active Power-Down Entry and Exit Timing with CAL .................................................................... 167

Figure 105: REFRESH Command to Power-Down Entry with CAL ................................................................... 168

Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode .............................................................. 169

Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................. 170

Figure 108: CRC Write Data Operation .......................................................................................................... 171

Figure 109: CRC Error Reporting ................................................................................................................... 180

Figure 110: CA Parity Flow Diagram .............................................................................................................. 181

Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode ........................................................................................... 186

Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 ............................................................................ 187

Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 ............................................................................ 188

Figure 114: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 ........................................................................... 188

Figure 115: 1tCK vs. 2tCK READ Preamble Mode ............................................................................................ 189

Figure 116: READ Preamble Training ............................................................................................................. 190

Figure 117: WRITE Postamble ....................................................................................................................... 190

Figure 118: READ Postamble ........................................................................................................................ 191

Figure 119: Bank Group x4/x8 Block Diagram ................................................................................................ 192

Figure 120: READ Burst tCCD_S and tCCD_L Examples .................................................................................. 193

Figure 121: Write Burst tCCD_S and tCCD_L Examples ................................................................................... 193

Figure 122: tRRD Timing ............................................................................................................................... 194

Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 194

Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) .............................. 195

Figure 125: Read Timing Definition ............................................................................................................... 197

Figure 126: Clock-to-Data Strobe Relationship .............................................................................................. 198

Figure 127: Data Strobe-to-Data Relationship ................................................................................................ 199

Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 200

Figure 129: tRPRE Method for Calculating Transitions and Endpoints ............................................................. 201

Figure 130: tRPST Method for Calculating Transitions and Endpoints ............................................................. 202

Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) ................................................................... 203

Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) ................................................................. 204

Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group .......................................... 205

Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group .......................................... 205

Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group ....................... 206

Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group ....................... 206

Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group ...................................... 207

Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group ...................................... 207

Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ............................... 208

Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group ............................... 208

Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group ............................... 209

Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group ............................... 209

Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ........................ 210

Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ........................ 210

Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ......... 211

Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ......... 212

Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group ..... 212

Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group ..... 213

Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group ................ 214

Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group ................ 214

Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ................ 215

Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ................ 215

Figure 153: READ to PRECHARGE with 1tCK Preamble .................................................................................. 216

Figure 154: READ to PRECHARGE with 2tCK Preamble .................................................................................. 217

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble .................................................. 217

Figure 156: READ with Auto Precharge and 1tCK Preamble ............................................................................ 218

Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble ................................................. 219

Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group ............................ 219

Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group .................... 220

Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group ... 221

Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 222

Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 223

Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group .................. 223

Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group .................. 224

Figure 165: Write Timing Definition .............................................................................................................. 226

Figure 166: tWPRE Method for Calculating Transitions and Endpoints ............................................................ 227

Figure 167: tWPST Method for Calculating Transitions and Endpoints ............................................................ 228

Figure 168: Rx Compliance Mask .................................................................................................................. 229

Figure 169: VCENT_DQ VREFDQ Voltage Variation .............................................................................................. 229

Figure 170: Rx Mask DQ-to-DQS Timings ...................................................................................................... 230

Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings ................................................................................. 231

Figure 172: Example of Data Input Requirements Without Training ................................................................ 232

Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) ................................................................. 233

Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) ............................................................. 234

Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group ........................................ 234

Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group ........................................ 235

Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ..................... 236

Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ..................... 236

Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group .................... 237

Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group .................... 238

Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group ................. 238

Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group ............................ 239

Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group ............................ 240

Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group ..................................... 240

Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group .......................................... 241

Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ...................... 242

Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group ........................... 242

Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 243

Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group ....................... 243

Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble ........................................................ 244

Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble .............................................................. 245

Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble ................................................ 245

Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble ...................................................... 246

Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI ................................................................... 247

Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI ......................................................................... 248

Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group ..................... 249

Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank

Group ....................................................................................................................................................... 250

Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank

Group ....................................................................................................................................................... 251

Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 252

Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 253

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group ... 254

Figure 202: ZQ Calibration Timing ................................................................................................................ 257

Figure 203: Functional Representation of ODT .............................................................................................. 258

Figure 204: Synchronous ODT Timing with BL8 ............................................................................................. 261

Figure 205: Synchronous ODT with BC4 ........................................................................................................ 261

Figure 206: ODT During Reads ...................................................................................................................... 262

Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......................... 264

Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......... 265

Figure 209: Asynchronous ODT Timings with DLL Off ................................................................................... 266

Figure 210: VREFDQ Voltage Range .................................................................................................................. 269

Figure 211: RESET_n Input Slew Rate Definition ............................................................................................ 272

Figure 212: Single-Ended Input Slew Rate Definition ..................................................................................... 274

Figure 213: DQ Slew Rate Definitions ............................................................................................................ 277

Figure 214: Rx Mask Relative to tDS/tDH ....................................................................................................... 279

Figure 215: Rx Mask Without Write Training .................................................................................................. 280

Figure 216: TEN Input Slew Rate Definition ................................................................................................... 281

Figure 217: CT Type-A Input Slew Rate Definition .......................................................................................... 281

Figure 218: CT Type-B Input Slew Rate Definition .......................................................................................... 282

Figure 219: CT Type-C Input Slew Rate Definition .......................................................................................... 283

Figure 220: CT Type-D Input Slew Rate Definition ......................................................................................... 283

Figure 221: Differential AC Swing and “Time Exceeding AC-Level” tDVAC ....................................................... 284

Figure 222: Single-Ended Requirements for CK .............................................................................................. 286

Figure 223: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 287

Figure 224: VIX(CK) Definition ........................................................................................................................ 287

Figure 225: Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 288

Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling ..... 289

Figure 227: VIXDQS Definition ........................................................................................................................ 290

Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 291

Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 293

Figure 230: CK Overshoot and Undershoot Definition .................................................................................... 294

Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 295

Figure 232: Single-ended Output Slew Rate Definition ................................................................................... 296

Figure 233: Differential Output Slew Rate Definition ...................................................................................... 298

Figure 234: Reference Load For AC Timing and Output Slew Rate ................................................................... 299

Figure 235: Connectivity Test Mode Reference Test Load ................................................................................ 299

Figure 236: Connectivity Test Mode Output Slew Rate Definition .................................................................... 300

Figure 237: Output Driver During Connectivity Test Mode ............................................................................. 301

Figure 238: Output Driver: Definition of Voltages and Currents ...................................................................... 302

Figure 239: Alert Driver ................................................................................................................................ 306

Figure 240: ODT Definition of Voltages and Currents ..................................................................................... 307

Figure 241: ODT Timing Reference Load ....................................................................................................... 308

Figure 242: tADC Definition with Direct ODT Control .................................................................................... 310

Figure 243: tADC Definition with Dynamic ODT Control ................................................................................ 310

Figure 244: tAOFAS and tAONAS Definitions .................................................................................................. 311

Figure 245: Thermal Measurement Point ....................................................................................................... 317

Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx ........................................................... 319

Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ....................................... 319

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Addressing ......................................................................................................................................... 2

Table 3: Ball Descriptions .............................................................................................................................. 26

Table 4: State Diagram Command Definitions ................................................................................................ 37

Table 5: Supply Power-up Slew Rate ............................................................................................................... 39

Table 6: Address Pin Mapping ........................................................................................................................ 47

Table 7: MR0 Register Definition .................................................................................................................... 47

Table 8: Burst Type and Burst Order ............................................................................................................... 49

Table 9: Address Pin Mapping ........................................................................................................................ 51

Table 10: MR1 Register Definition .................................................................................................................. 51

Table 11: Additive Latency (AL) Settings ......................................................................................................... 53

Table 12: TDQS Function Matrix .................................................................................................................... 54

Table 13: Address Pin Mapping ...................................................................................................................... 55

Table 14: MR2 Register Definition .................................................................................................................. 55

Table 15: Address Pin Mapping ...................................................................................................................... 58

Table 16: MR3 Register Definition .................................................................................................................. 58

Table 17: Address Pin Mapping ...................................................................................................................... 61

Table 18: MR4 Register Definition .................................................................................................................. 61

Table 19: Address Pin Mapping ...................................................................................................................... 65

Table 20: MR5 Register Definition .................................................................................................................. 65

Table 21: Address Pin Mapping ...................................................................................................................... 68

Table 22: MR6 Register Definition .................................................................................................................. 68

Table 23: Truth Table – Command .................................................................................................................. 70

Table 24: Truth Table – CKE ........................................................................................................................... 72

Table 25: MR Settings for Leveling Procedures ................................................................................................ 80

Table 26: DRAM TERMINATION Function in Leveling Mode ........................................................................... 80

Table 27: Auto Self Refresh Mode ................................................................................................................... 89

Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 91

Table 29: DRAM Address to MPR UI Translation ............................................................................................. 91

Table 30: MPR Page and MPRx Definitions ..................................................................................................... 92

Table 31: MPR Readout Serial Format ............................................................................................................. 94

Table 32: MPR Readout – Parallel Format ....................................................................................................... 95

Table 33: MPR Readout Staggered Format, x4 ................................................................................................. 96

Table 34: MPR Readout Staggered Format, x4 – Consecutive READs ................................................................ 96

Table 35: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 97

Table 36: Mode Register Setting for CA Parity ................................................................................................. 112

Table 37: VREFDQ Range and Levels ................................................................................................................ 122

Table 38: VREFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 128

Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 130

Table 40: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 133

Table 41: PPR MR0 Guard Key Settings .......................................................................................................... 135

Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 139

Table 43: sPPR Associated Rows .................................................................................................................... 139

Table 44: PPR MR0 Guard Key Settings .......................................................................................................... 140

Table 45: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 141

Table 46: MBIST-PPR Timing Parameter ........................................................................................................ 142

Table 47: MPR Page3 Configuration for MBIST-PPR ....................................................................................... 143

Table 48: DDR4 Repair Mode Support Identifier ............................................................................................ 144

Table 49: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 148

Table 50: MRS Definition .............................................................................................................................. 151

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 51: REFRESH Command Truth Table .................................................................................................... 151

Table 52: tREFI and tRFC Parameters ............................................................................................................. 152

Table 53: Power-Down Entry Definitions ....................................................................................................... 161

Table 54: CRC Error Detection Coverage ........................................................................................................ 172

Table 55: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 174

Table 56: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 174

Table 57: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 175

Table 58: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 175

Table 59: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 176

Table 60: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 177

Table 61: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 182

Table 62: DBI Write, DQ Frame Format (x8) ................................................................................................... 182

Table 63: DBI Write, DQ Frame Format (x16) ................................................................................................. 182

Table 64: DBI Read, DQ Frame Format (x8) .................................................................................................... 183

Table 65: DBI Read, DQ Frame Format (x16) .................................................................................................. 183

Table 66: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 184

Table 67: Data Mask, DQ Frame Format (x8) .................................................................................................. 184

Table 68: Data Mask, DQ Frame Format (x16) ................................................................................................ 184

Table 69: CWL Selection ............................................................................................................................... 187

Table 70: DDR4 Bank Group Timing Examples .............................................................................................. 192

Table 71: Read-to-Write and Write-to-Read Command Intervals .................................................................... 197

Table 72: Termination State Table ................................................................................................................. 259

Table 73: Read Termination Disable Window ................................................................................................. 259

Table 74: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 260

Table 75: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) ................................ 263

Table 76: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 264

Table 77: Absolute Maximum Ratings ............................................................................................................ 267

Table 78: Temperature Range ........................................................................................................................ 267

Table 79: Recommended Supply Operating Conditions .................................................................................. 268

Table 80: VDD Slew Rate ................................................................................................................................ 268

Table 81: Leakages ....................................................................................................................................... 269

Table 82: VREFDQ Specification ...................................................................................................................... 270

Table 83: VREFDQ Range and Levels ................................................................................................................ 271

Table 84: RESET_n Input Levels (CMOS) ....................................................................................................... 272

Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 ........................................... 272

Table 86: Command and Address Input Levels: DDR4-2666 ............................................................................ 273

Table 87: Command and Address Input Levels: DDR4-2933 and DDR4-3200 ................................................... 273

Table 88: Single-Ended Input Slew Rates ....................................................................................................... 274

Table 89: Command and Address Setup and Hold Values Referenced – AC/DC-Based ..................................... 275

Table 90: Derating Values for tIS/tIH – AC100DC75-Based .............................................................................. 275

Table 91: Derating Values for tIS/tIH – AC90/DC65-Based .............................................................................. 276

Table 92: DQ Input Receiver Specifications .................................................................................................... 277

Table 93: Rx Mask and tDS/tDH without Write Training .................................................................................. 280

Table 94: TEN Input Levels (CMOS) .............................................................................................................. 280

Table 95: CT Type-A Input Levels .................................................................................................................. 281

Table 96: CT Type-B Input Levels .................................................................................................................. 282

Table 97: CT Type-C Input Levels (CMOS) ..................................................................................................... 282

Table 98: CT Type-D Input Levels .................................................................................................................. 283

Table 99: Differential Input Swing Requirements for CK_t, CK_c ..................................................................... 284

Table 100: Minimum Time AC Time tDVAC for CK .......................................................................................... 285

Table 101: Single-Ended Requirements for CK ............................................................................................... 286

Table 102: CK Differential Input Slew Rate Definition ..................................................................................... 286

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 ................ 288

Table 104: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 ................ 288

Table 105: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c ............. 288

Table 106: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c ............. 289

Table 107: Cross Point Voltage For Differential Input Signals DQS ................................................................... 290

Table 108: DQS Differential Input Slew Rate Definition .................................................................................. 291

Table 109: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 291

Table 110: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 292

Table 111: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 293

Table 112: CK Overshoot and Undershoot/ Specifications .............................................................................. 294

Table 113: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 295

Table 114: Single-Ended Output Levels ......................................................................................................... 295

Table 115: Single-Ended Output Slew Rate Definition .................................................................................... 296

Table 116: Single-Ended Output Slew Rate .................................................................................................... 297

Table 117: Differential Output Levels ............................................................................................................. 297

Table 118: Differential Output Slew Rate Definition ....................................................................................... 297

Table 119: Differential Output Slew Rate ....................................................................................................... 298

Table 120: Connectivity Test Mode Output Levels .......................................................................................... 299

Table 121: Connectivity Test Mode Output Slew Rate ..................................................................................... 300

Table 122: Output Driver Electrical Characteristics During Connectivity Test Mode ......................................... 302

Table 123: Strong Mode (34˖) Output Driver Electrical Characteristics ........................................................... 303

Table 124: Weak Mode (48˖) Output Driver Electrical Characteristics ............................................................. 304

Table 125: Output Driver Sensitivity Definitions ............................................................................................ 305

Table 126: Output Driver Voltage and Temperature Sensitivity ....................................................................... 305

Table 127: Alert Driver Voltage ...................................................................................................................... 306

Table 128: ODT DC Characteristics ............................................................................................................... 307

Table 129: ODT Sensitivity Definitions .......................................................................................................... 308

Table 130: ODT Voltage and Temperature Sensitivity ..................................................................................... 308

Table 131: ODT Timing Definitions ............................................................................................................... 309

Table 132: Reference Settings for ODT Timing Measurements ........................................................................ 309

Table 133: DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 312

Table 134: DRAM Package Electrical Specifications for x16 Devices ................................................................ 313

Table 135: Pad Input/Output Capacitance ..................................................................................................... 315

Table 136: Thermal Characteristics ............................................................................................................... 316

Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions .......................................................................... 319

Table 138: IDD0 and IPP0 Measurement-Loop Pattern1 .................................................................................... 323

Table 139: IDD1 Measurement – Loop Pattern1 ............................................................................................... 324

Table 140: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1 .................................................................... 325

Table 141: IDD2NT Measurement – Loop Pattern1 ............................................................................................ 326

Table 142: IDD4R Measurement – Loop Pattern1 .............................................................................................. 327

Table 143: IDD4W Measurement – Loop Pattern1 ............................................................................................. 328

Table 144: IDD4Wc Measurement – Loop Pattern1 ............................................................................................ 329

Table 145: IDD5R Measurement – Loop Pattern1 .............................................................................................. 330

Table 146: IDD7 Measurement – Loop Pattern1 ............................................................................................... 331

Table 147: Timings used for IDD, IPP, and IDDQ Measurement – Loop Patterns .................................................. 332

Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. A (0° ื TC ื 85°C) ........................................................... 333

Table 149: IDD, IPP, and IDDQ Current Limits; Die Rev. B (0° ื TC ื 85°C) .......................................................... 335

Table 150: IDD, IPP, and IDDQ Current Limits; Die Rev. D (0° ื TC ื 85°C) .......................................................... 337

Table 151: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40° ื TC ื 85°C) ........................................................ 339

Table 152: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40° ื TC ื 105°C) ...................................................... 342

Table 153: IDD, IPP, and IDDQ Current Limits; Die Rev. G (0° ื TC ื 85°C) .......................................................... 344

Table 154: IDD, IPP, and IDDQ Current Limits; Die Rev. H (0° ื TC ื 85°C) .......................................................... 346

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 155: IDD, IPP, and IDDQ Current Limits; Die Rev. J (-40° ื TC ื 85°C) ........................................................ 348

Table 156: IDD, IPP, and IDDQ Current Limits; Die Rev. R (-40° ื TC ื 85°C) ....................................................... 351

Table 157: Backward Compatibility ............................................................................................................... 355

Table 158: DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 357

Table 159: DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 359

Table 160: DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 361

Table 161: DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 363

Table 162: DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 365

Table 163: DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 368

Table 164: DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 371

Table 165: Refresh Parameters by Device Density ........................................................................................... 373

Table 166: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 ................... 374

Table 167: Electrical Characteristics and AC Timing Parameters ..................................................................... 387

Table 168: Options – Speed Based ................................................................................................................. 400

Table 169: Options – Width Based ................................................................................................................. 401

8Gb: x4, x8, x16 DDR4 SDRAM

Features

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

General Notes and Description

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-

ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

8Gb: x4, x8, x16 DDR4 SDRAM

Important Notes and Warnings

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach-

ieve high-speed operation. The 8n-prefetch architecture is combined with an interface

designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit

wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit

wide, one-half-clock-cycle data transfers at the I/O pins.

Industrial Temperature

An industrial temperature (IT) device option requires that the case temperature not ex-

ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double

when TC exceeds 85°C; this also requires use of the high-temperature self refresh option.

Additionally, ODT resistance and the input/output impedance must be derated when

operating outside of the commercial temperature range, when TC is between –40°C and

0°C.

Automotive Temperature

The automotive temperature (AT) device option requires that the case temperature not

exceed below –40°C or above 105°C. The specifications require the refresh rate to 2X

when TC exceeds 85°C; 4X when TC exceeds 95°C. Additionally, ODT resistance and the

input/output impedance must be derated when operating temperature Tc <0°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation), unless specifically stated other-

wise.

• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise.

• The terms "_t" and "_c" are used to represent the true and complement of a differen-

tial signal pair. These terms replace the previously used notation of "#" and/or over-

bar characters. For example, differential data strobe pair DQS, DQS# is now referred

to as DQS_t, DQS_c.

• The term "_n" is used to represent a signal that is active LOW and replaces the previ-

ously used "#" and/or overbar characters. For example: CS# is now referred to as

CS_n.

• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as

DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the entire document; any page

or diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated here within is considered undefined, illegal,

and not supported, and can result in unknown operation.

• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for

row/col address.

• The NOP command is not allowed, except when exiting maximum power savings

mode or when entering gear-down mode, and only a DES command should be used.

8Gb: x4, x8, x16 DDR4 SDRAM

General Notes and Description

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.

• Not all features described within this document may be available on the Rev. A (first)

version.

• Not all specifications listed are finalized industry standards; best conservative esti-

mates have been provided when an industry standard has not been finalized.

• Although it is implied throughout the specification, the DRAM must be used after VDD

has reached the stable power-on level, which is achieved by toggling CKE at least once

every 8192 × tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least

once every 8192 × tREFI is an acceptable alternative. Placing the DRAM into self re-

fresh mode also alleviates the need to toggle CKE.

• Not all features designated in the data sheet may be supported by earlier die revisions

due to late definition by JEDEC.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS_t to VDDQ or VSS/ VSSQ via a resistor in the 200 വ range.

– Connect UDQS_c to the opposite rail via a resistor in the same 200വ range.

– Connect UDM to VDDQ via a large (10,000വ) pull-up resistor.

– Connect UDBI to VDDQ via a large (10,000വ) pull-up resistor.

– Connect DQ [15:8] individually to VDDQ via a large (10,000വ) resistors, or float DQ

[15:8] .

Definitions of the Device-Pin Signal Level

• HIGH: A device pin is driving the logic 1 state.

• LOW: A device pin is driving the logic 0 state.

• High-Z: A device pin is tri-state.

• ODT: A device pin terminates with the ODT setting, which could be terminating or tri-

state depending on the mode register setting.

Definitions of the Bus Signal Level

• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT

or High-Z. The voltage level on the bus is nominally VDDQ.

• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT

or High-Z. The voltage level on the bus is nominally VOL(DC) if ODT was enabled, or

VSSQ if High-Z.

• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as

the bus is floating.

• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-

el on the bus is nominally VDDQ.

• The specification requires 8,192 refresh commands within 64ms between 0 oC and 85

oC. This allows for a tREFI of 7.8125μs (the use of "7.8μs" is truncated from 7.8125μs).

The specification also requires 8,192 refresh commands within 32ms between 85 oC

and 95 oC. This allows for a tREFI of 3.90625μs (the use of "3.9μs" is truncated from

3.90625μs).

8Gb: x4, x8, x16 DDR4 SDRAM

General Notes and Description

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Block Diagrams

DDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 16-bank (4-banks per Bank Group) DRAM.

Figure 2: 2 Gig x 4 Functional Block Diagram

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8Gb: x4, x8, x16 DDR4 SDRAM

Functional Block Diagrams

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 4: 512 Meg x 16 Functional Block Diagram

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8Gb: x4, x8, x16 DDR4 SDRAM

Functional Block Diagrams

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Ball Assignments

Figure 5: 78-Ball x4, x8 Ball Assignments

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2. A comma “,” separates the configuration; a slash “/” defines a mode register selectable

function, command/address function, density, or package dependence.

3. Address bits (including bank groups) are density- and configuration-dependent (see Ad-

dressing).

8Gb: x4, x8, x16 DDR4 SDRAM

Ball Assignments

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 6: 96-Ball x16 Ball Assignments

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Notes: 1. See Ball Descriptions.

2. A slash “/” defines a mode register selectable function, command/address function, den-

sity, or package dependence.

3. Address bits (including bank groups) are density- and configuration-dependent (see Ad-

dressing).

8Gb: x4, x8, x16 DDR4 SDRAM

Ball Assignments

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Ball Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4 de-

vices. All pins listed may not be supported on the device defined in this data sheet. See

the Ball Assignments section to review all pins used on this device.

Table 3: Ball Descriptions

Symbol Type Description

A[17:0] Input Address inputs: Provide the row address for ACTIVATE commands and the column

address for READ/WRITE commands to select one location out of the memory array in

the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have addi-

tional functions, see individual entries in this table.) The address inputs also provide

the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and

16Gb parts. A17 connection is part-number specific; Contact vendor for more infor-

mation.

A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine

whether auto precharge should be performed to the accessed bank after a READ or

WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sam-

pled during a PRECHARGE command to determine whether the PRECHARGE applies

to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,

the bank is selected by the bank group and bank addresses.

A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if

burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chop-

ped). See the Command Truth Table.

ACT_n Input Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with

CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as

row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with

CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as nor-

mal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command

Truth Table.

BA[1:0] Input Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,

READ, WRITE, or PRECHARGE command is being applied. Also determines which

mode register is to be accessed during a MODE REGISTER SET command.

BG[1:0] Input Bank group address inputs: Define the bank group to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determines which mode regis-

ter is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the

x4 and x8 configurations. BG1 is not used in the x16 configuration.

C0/CKE1,

C1/CS1_n,

C2/ODT1

Input Stack address inputs: These inputs are used only when devices are stacked; that is,

they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are

not used in the x16 configuration, and are NC on the x4/x8 SDP). DDR4 will support a

traditional DDP package, which uses these three signals for control of the second die

(CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. For

all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load

(master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects

in conjunction with a single CS_n, CKE, and ODT signal.

CK_t,

CK_c

Input Clock: Differential clock inputs. All address, command, and control input signals are

sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.

8Gb: x4, x8, x16 DDR4 SDRAM

Ball Descriptions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: Ball Descriptions (Continued)

Symbol Type Description

CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock sig-

nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE

POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down

(row active in any bank). CKE is asynchronous for self refresh exit, however, timing

parameters such as tXS are still calculated from the first rising clock edge where CKE

HIGH satisfies tIS. After VREFCA has become stable during the power-on and initializa-

tion sequence, it must be maintained during all operations (including SELF REFRESH).

CKE must be maintained HIGH throughout read and write accesses. Input buffers (ex-

cluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input

buffers (excluding CKE and RESET_n) are disabled during self refresh.

CS_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides

for external rank selection on systems with multiple ranks. CS_n is considered part of

the command code.

DM_n,

UDM_n

LDM_n

Input Input data mask: DM_n is an input mask signal for write data. Input data is masked

when DM is sampled LOW coincident with that input data during a write access. DM

is sampled on both edges of DQS. DM is not supported on x4 configurations. The

UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with

DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are en-

abled by mode register settings. See the Data Mask section.

ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal

to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t,

DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations

(when the TDQS function is enabled via mode register). For the x16 configuration, RTT

is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal.

The ODT pin will be ignored if the mode registers are programmed to disable RTT.

PAR Input Parity for command and address: This function can be enabled or disabled via the

mode register. When enabled, the parity signal covers all command and address in-

puts, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n,

BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT cov-

ered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are densi-

ty- and configuration-specific should be treated internally as 0s by the DRAM parity

logic. Command and address inputs will have parity check performed when com-

mands are latched via the rising edge of CK_t and when CS_n is LOW.

RAS_n/A16,

CAS_n/A15,

WE_n/A14

Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and

ACT_n) define the command and/or address being entered. See the ACT_n descrip-

tion in this table.

RESET_n Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inac-

tive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n

is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV

for DC HIGH and 240 mV for DC LOW).

TEN Input Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN

must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC

HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC

LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN

pin should be considered NF maintained LOW at all times.

8Gb: x4, x8, x16 DDR4 SDRAM

Ball Descriptions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: Ball Descriptions (Continued)

Symbol Type Description

DQ I/O Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and

DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled

via mode register, the write CRC code is added at the end of data burst. Any one or

all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal VREF level during

test via mode register setting MR[4] A[4] = HIGH, training times change when ena-

bled. During this mode, the RTT value should be set to High-Z. This measurement is

for verification purposes and is NOT an external voltage supply pin.

DBI_n,

UDBI_n,

LDBI_n

I/O DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data

bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configu-

ration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The

DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS

devices and should be disabled in MR5. DBI can be configured for both READ (out-

put) and WRITE (input) operations depending on the mode register settings. The DM,

DBI, and TDQS functions are enabled by mode register settings. See the Data Bus In-

version section.

DQS_t,

DQS_c,

UDQS_t,

UDQS_c,

LDQS_t,

LDQS_c

I/O Data strobe: Output with READ data, input with WRITE data. Edge-aligned with

READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the

data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 con-

figurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4

SDRAM supports a differential data strobe only and does not support a single-ended

data strobe.

ALERT_n Output Alert output: This signal allows the DRAM to indicate to the system's memory con-

troller that a specific alert or event has occurred. Alerts will include the command/

address parity error and the CRC data error when either of these functions is enabled

in the mode register.

TDQS_t,

TDQS_c

Output Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When

enabled via the mode register, the DRAM will enable the same RTT termination resist-

ance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS

function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA

MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be dis-

abled in the mode register for both the x4 and x16 configurations. The DM function

is supported only in x8 and x16 configurations.

VDD Supply Power supply: 1.2V ±0.060V.

VDDQ Supply DQ power supply: 1.2V ±0.060V.

VPP Supply DRAM activating power supply: 2.5V –0.125V/+0.250V.

VREFCA Supply Reference voltage for control, command, and address pins.

VSS Supply Ground.

VSSQ Supply DQ ground.

ZQ Reference Reference ball for ZQ calibration: This ball is tied to an external 240˖ resistor

(RZQ), which is tied to VSSQ.

RFU – Reserved for future use.

NC – No connect: No internal electrical connection is present.

NF – No function: Internal connection is present but has no function.

8Gb: x4, x8, x16 DDR4 SDRAM

Ball Descriptions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Package Dimensions

Figure 7: 78-Ball FBGA – x4, x8 (PM)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID

(covered by SR) Ball A1 ID

0.28 MIN

1.1 ±0.1

6.4 CTR

9 ±0.1

0.8 TYP

9.6 CTR

13.2 ±0.1

78X Ø0.47

Dimensions apply

to solder balls

post-reflow on

Ø0.42 SMD ball pads.

0.8 TYP

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 8: 78-Ball FBGA – x4, x8 (WE)

1.8 CTR

nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

9.6 CTR

12 ±0.1

78X Ø0.47

Dimensions apply

to solder balls post-

reflow on Ø0.42 SMD

ball pads.

0.8 TYP

23789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 9: 78-Ball FBGA – x4, x8 (SA)

1.8 CTR

nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

9.6 CTR

11 ±0.1

78X Ø0.47

Dimensions apply

to solder balls post-

reflow on Ø0.42 SMD

ball pads.

0.8 TYP

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 10: 96-Ball FBGA – x16 (HA)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.29 MIN

1.1 ±0.1

6.4 CTR

9 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.47

Dimensions apply

to solder balls post-

reflow on Ø0.42 SMD

ball pads.

0.8 TYP

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 11: 96-Ball FBGA – x16 (JY)

1.8 CTR

Nonconductive

overmold

0.155

Seating plane

0.12 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

12 CTR

14 ±0.1

96X Ø0.47

Dimensions apply

to solder balls post-

reflow on Ø0.42 SMD

ball pads.

0.8 TYP

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 12: 96-Ball FBGA – x16 (LY)

Seating plane

0.12 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

12 CTR

13.5 ±0.1

96X Ø0.47

Dimensions apply

to solder balls post-

reflow on Ø0.42

SMD ball pads.

0.8 TYP

1.8 CTR

Nonconductive

overmold

0.155

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

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Figure 13: 96-Ball FBGA – x16 (TB)

Seating plane

0.1 A

Ball A1 ID

(covered by SR)

Ball A1 ID

0.34 ±0.05

1.1 ±0.1

6.4 CTR

7.5 ±0.1

0.8 TYP

12 CTR

13 ±0.1

96X Ø0.47

Dimensions

apply to solder

balls post-reflow

on Ø0.42 SMD

ball pads.

0.8 TYP

1.8 CTR

Nonconductive

overmold

0.155

123789

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

8Gb: x4, x8, x16 DDR4 SDRAM

Package Dimensions

CCMTD-1725822587-9875

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State Diagram

This simplified state diagram provides an overview of the possible state transitions and

the commands to control them. Situations involving more than one bank, the enabling

or disabling of on-die termination, and some other events are not captured in full de-

tail.

Figure 14: Simplified State Diagram

Bank

active

Reading

Writing

Activating

Refreshing

Self

refresh

Idle

Active

power-

down

calibration

Power

From any state

applied Reset

procedure

Power-On

Initialization

MRS, MPR,

write leveling,

VREFDQ training

Precharge

power-

down

Writing Reading

Automatic

sequence

Command

sequence

Precharging

READ

READ READ

READ A

PRE, PREA

PRE, PREA PRE, PREA

WRITE

WRITE A

PDE

PDX

SRX

SRE

REF

ACT

ZQCL

ZQCL,ZQCS

CKE_L

MPSM

PDA

mode

REFDQ

RTT, and

so on

Connectivity

test

RESET

TEN = 0

MRS

SRX*

SRX* = SRX with NOP

MRS

TEN = 1 TEN = 1

8Gb: x4, x8, x16 DDR4 SDRAM

State Diagram

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Table 4: State Diagram Command Definitions

Command Description

ACT Active

MPR Multipurpose register

MRS Mode register set

PDE Enter power-down

PDX Exit power-down

PRE Precharge

PREA Precharge all

READ RD, RDS4, RDS8

READ A RDA, RDAS4, RDAS8

REF Refresh, fine granularity refresh

RESET Start reset procedure

SRE Self refresh entry

SRX Self refresh exit

TEN Boundary scan mode enable

WRITE WR, WRS4, WRS8 with/without CRC

WRITE A WRA, WRAS4, WRAS8 with/without CRC

ZQCL ZQ calibration long

ZQCS ZQ calibration short

Note: 1. See the Command Truth Table for more details.

8Gb: x4, x8, x16 DDR4 SDRAM

State Diagram

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Functional Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-

ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi-

ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16

devices. The device uses double data rate (DDR) architecture to achieve high-speed op-

eration. DDR4 architecture is essentially an 8n-prefetch architecture with an interface

designed to transfer two data words per clock cycle at the I/O pins. A single read or

write access for a device module effectively consists of a single 8n-bit-wide, four-clock-

cycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the device are burst-oriented. Accesses start at a selected lo-

cation and continue for a burst length of eight or a chopped burst of four in a program-

med sequence. Operation begins with the registration of an ACTIVE command, which is

then followed by a READ or WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]

select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select

the bank, and A[17:0] select the row. See the Addressing section for more details). The

address bits registered coincident with the READ or WRITE command are used to select

the starting column location for the burst operation, determine if the auto PRECHARGE

command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via

A12) if enabled in the mode register.

Prior to normal operation, the device must be powered up and initialized in a prede-

fined manner. The following sections provide detailed information covering device reset

and initialization, register definition, command descriptions, and device operation.

NOTE: The use of the NOP command is allowed only when exiting maximum power

saving mode or when entering gear-down mode.

8Gb: x4, x8, x16 DDR4 SDRAM

Functional Description

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RESET and Initialization Procedure

To ensure proper device function, the power-up and reset initialization default values

for the following mode register (MR) settings are defined as:

• Gear-down mode (MR3 A[3]): 0 = 1/2 rate

• Per-DRAM addressability (MR3 A[4]): 0 = disable

• Maximum power-saving mode (MR4 A[1]): 0 = disable

• CS to command/address latency (MR4 A[8:6]): 000 = disable

• CA parity latency mode (MR5 A[2:0]): 000 = disable

• Hard post package repair mode (MR4 A[13]): 0 = disable

• Soft post package repair mode (MR4 A[5]): 0 = disable

Power-Up and Initialization Sequence

The following sequence is required for power-up and initialization:

1. Apply power (RESET_n and TEN should be maintained below 0.2 × VDD while sup-

plies ramp up; all other inputs may be undefined). When supplies have ramped to

a valid stable level, RESET_n must be maintained below 0.2 × VDD for a minimum

of tPW_RESET_L and TEN must be maintained below 0.2 × VDD for a minimum of

700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time

of 10ns). The power voltage ramp time between 300mV to VDD,min must be no

greater than 200ms, and during the ramp, VDD must be greater than or equal to

VDDQ and (VDD - VDDQ) < 0.3V. VPP must ramp at the same time or up to 10 minutes

prior to VDD, and VPP must be equal to or higher than VDD at all times. The total

time for which VPP is powered and VDD is unpowered should not exceed 360 cu-

mulative hours. After VDD has ramped and reached a stable level, RESET_n must

go high within 10 minutes. After RESET_n goes high, the initialization sequence

must be started within 3 seconds. For debug purposes, the 10 minute and 3 sec-

ond delay limits may be extended to 60 minutes each provided the DRAM is oper-

ated in this debug mode for no more than 360 cumulative hours.

During power-up, the supply slew rate is governed by the limits stated in the table

below and either condition A or condition B listed below must be met.

Table 5: Supply Power-up Slew Rate

Symbol Min Max Unit Comment

VDD_SL, VDDQ_SL,

VPP_SL

0.004 600 V/ms Measured between 300mV and 80% of

supply minimum

VDD_ona N/A 200 ms VDD maximum ramp time from 300mV to

VDD minimum

VDDQ_ona N/A 200 ms VDDQ maximum ramp time from 300mV to

VDDQ minimum

Note: 1. 20 MHz band-limited measurement.

• Condition A:

– Apply VPP without any slope reversal before or at the same time as VDD and

VDDQ.

8Gb: x4, x8, x16 DDR4 SDRAM

RESET and Initialization Procedure

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–V

DD and VDDQ are driven from a single-power converter output and apply

VDD/VDDQ without any slope reversal before or at the same time as VTT and

VREFCA.

– The voltage levels on all balls other than VDD, VDDQ, VSS, and VSSQ must be less

than or equal to VDDQ and VDD on one side and must be greater than or equal

to VSSQ and VSS on the other side.

–V

TT is limited to 0.76V MAX when the power ramp is complete.

–V

REFCA tracks VDD/2.

• Condition B:

– Apply VPP without any slope reversal before or at the same time as VDD.

– Apply VDD without any slope reversal before or at the same time as VDDQ.

– Apply VDDQ without any slope reversal before or at the same time as VTT and

VREFCA.

– The voltage levels on all pins other than VPP, VDD, VDDQ, VSS, and VSSQ must be

less than or equal to VDDQ and VDD on one side and must be larger than or

equal to VSSQ and VSS on the other side.

2. After RESET_n is de-asserted, wait for a minimum of 500μs, but no longer than 3

seconds, before allowing CKE to be registered HIGH at clock edge Td. During this

time, the device will start internal state initialization; this will be done independ-

ently of external clocks. A reasonable attempt was made in the design to power up

with the following default MR settings: gear-down mode (MR3 A[3]): 0 = 1/2 rate;

per-DRAM addressability (MR3 A[4]): 0 = disable; maximum power-down (MR4

A[1]): 0 = disable; CS to command/address latency (MR4 A[8:6]): 000 = disable; CA

parity latency mode (MR5 A[2:0]): 000 = disable. However, it should be assumed

that at power up the MR settings are undefined and should be programmed as

shown below.

3. Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 tCK

(whichever is larger) before CKE is registered HIGH at clock edge Td. Because CKE

is a synchronous signal, the corresponding setup time to clock (tIS) must be met.

Also, a DESELECT command must be registered (with tIS setup time to clock) at

clock edge Td. After the CKE is registered HIGH after RESET, CKE needs to be con-

tinuously registered HIGH until the initialization sequence is finished, including

expiration of tDLLK and tZQinit.

4. The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,

the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is

registered HIGH. The ODT input signal may be in an undefined state until tIS be-

fore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal

may be statically held either LOW or HIGH. If RTT(NOM) is to be enabled in MR1,

the ODT input signal must be statically held LOW. In all cases, the ODT input sig-

nal remains static until the power-up initialization sequence is finished, including

the expiration of tDLLK and tZQinit.

5. After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, tXPR, be-

fore issuing the first MRS command to load mode register (tXPR = MAX (tXS, 5 ×

tCK).

6. Issue MRS command to load MR3 with all application settings, wait tMRD.

7. Issue MRS command to load MR6 with all application settings, wait tMRD.

8. Issue MRS command to load MR5 with all application settings, wait tMRD.

9. Issue MRS command to load MR4 with all application settings, wait tMRD.

10. Issue MRS command to load MR2 with all application settings, wait tMRD.

11. Issue MRS command to load MR1 with all application settings, wait tMRD.

8Gb: x4, x8, x16 DDR4 SDRAM

RESET and Initialization Procedure

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12. Issue MRS command to load MR0 with all application settings, wait tMOD.

13. Issue a ZQCL command to start ZQ calibration.

14. Wait for tDLLK and tZQinit to complete.

15. The device will be ready for normal operation. Once the DRAM has been initial-

ized, if the DRAM is in an idle state longer than 960ms, then either (a) REF com-

mands must be issued within tREFI constraints (specification for posting allowed)

or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For

debug purposes, the 960ms delay limit maybe extended to 60 minutes provided

the DRAM is operated in this debug mode for no more than 360 cumulative hours.

16. Optional MBIST-PPR mode can be entered by setting MR4:A0 to a "1", followed by

subsequent MR0 guard key sequences, then DRAM will drive ALERT_n to LOW.

DRAM will drive ALERT_n to HIGH to indicate that this operation is completed.

MBIST PPR mode can take place anytime after Tk. Note that no exit sequence or

re-initialization is needed after MBIST completes; as soon as ALERT_N goes HIGH

and tIS is satisfied, MR0 must be re-written to the pre guard key state, then and the

DRAM is immediately ready to receive valid commands.

A stable valid VDD level is a set DC level (0Hz to 250 KHz) and must be no less than

VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa-

tion, the DLL reset and calibrations must be performed again after the new set DC level

is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the

noise doesn't alter VDD to less than VDD,min or greater than VDD,max.

A stable valid VDDQ level is a set DC level (0Hz to 250 KHz) and must be no less than

VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial-

ization, the DLL reset and calibrations must be performed again after the new set DC

level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided

the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.

A stable valid VPP level is a set DC level (0Hz to 250 KHz) and must be no less than

VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initializa-

tion, the DLL reset and calibrations must be performed again after the new set DC level

is stable. AC noise of ±120mV (greater than 250KHz) is allowed on VPP provided the

noise doesn't alter VPP to less than VPP,min or greater than VPP,max.

8Gb: x4, x8, x16 DDR4 SDRAM

RESET and Initialization Procedure

CCMTD-1725822587-9875

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Figure 15: RESET and Initialization Sequence at Power-On Ramping

CKE

RTT

BG, BA

tPW_RESET_L

CK_t, CK_c

Command Note 1 Note 1

TdTc

Don’t CareTime Break

tIS

ODT

tMRD tMOD

MRSMRS Valid

Valid

tMRD tMRD

MRS

MRxMRx

MRx

MRS

MRx

Ti Tj Tk

RESET_n

T = 500μs

Valid

TeTa Tb Tf

ZQCL

tIS

Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW

tIS tIS

tXPR

Valid

T (MIN) = 10ns

VDD, VDDQ

VPP

tDLLK

tZQinit

tCKSRX

Notes: 1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL

commands.

2. MRS commands must be issued to all mode registers that have defined settings.

3. In general, there is no specific sequence for setting the MRS locations (except for de-

pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,

for example).

4. TEN is not shown; however, it is assumed to be held LOW.

5. Optional MBIST-PPR may be entered any time after Tk.

RESET Initialization with Stable Power Sequence

The following sequence is required for RESET at no power interruption initialization:

1. Assert RESET_n below 0.2 × VDD any time when reset is needed (all other inputs

may be undefined). RESET_n needs to be maintained for minimum tPW_RESET.

CKE is pulled LOW before RESET_n being de-asserted (minimum time 10ns).

2. Follow Steps 2 through 10 in the Reset and Initialization Sequence at Power-On

Ramping procedure.

When the reset sequence is complete, all counters except the refresh counters have

been reset and the device is ready for normal operation.

8Gb: x4, x8, x16 DDR4 SDRAM

RESET and Initialization Procedure

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Figure 16: RESET Procedure at Power Stable Condition

CKE

RTT

BG, BA

tPW_RESET_S

CK_t, CK_c

Command Note 1 Note 1

TdTc

Don’t CareTime Break

tIS

ODT

tMRD tMOD

MRSMRS Valid

Valid

tMRD tMRD

MRS

MRxMRx

MRx

MRS

MRx

Ti Tj Tk

RESET_n

T = 500μs

Valid

TeTa Tb Tf

ZQCL

tIS

Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW

tIS tIS

tXPR

Valid

T (MIN) = 10ns

VDD, VDDQ

VPP

tDLLK

tZQinit

tCKSRX

Notes: 1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL

commands.

2. MRS commands must be issued to all mode registers that have defined settings.

3. In general, there is no specific sequence for setting the MRS locations (except for de-

pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,

for example).

4. TEN is not shown; however, it is assumed to be held LOW.

Uncontrolled Power-Down Sequence

In the event of an uncontrolled ramping down of VPP supply, VPP is allowed to be less

than VDD provided the following conditions are met:

• Condition A: VPP and VDD/VDDQ are ramping down (as part of turning off) from nor-

mal operating levels.

• Condition B: The amount that VPP may be less than VDD/VDDQ is less than or equal to

500mV.

• Condition C: The time VPP may be less than VDD is ื10ms per occurrence with a total

accumulated time in this state ื100ms.

8Gb: x4, x8, x16 DDR4 SDRAM

RESET and Initialization Procedure

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• Condition D: The time VPP may be less than 2.0V and above VSS while turning off is

ื15ms per occurrence with a total accumulated time in this state ื150ms.

Programming Mode Registers

For application flexibility, various functions, features, and modes are programmable in

seven mode registers (MRn) provided by the device as user defined variables that must

be programmed via a MODE REGISTER SET (MRS) command. Because the default val-

ues of the mode registers are not defined, contents of mode registers must be fully ini-

tialized and/or re-initialized; that is, they must be written after power-up and/or reset

for proper operation. The contents of the mode registers can be altered by re-executing

the MRS command during normal operation. When programming the mode registers,

even if the user chooses to modify only a sub-set of the MRS fields, all address fields

within the accessed mode register must be redefined when the MRS command is is-

sued. MRS and DLL RESET commands do not affect array contents, which means these

commands can be executed any time after power-up without affecting the array con-

tents.

The MRS command cycle time, tMRD, is required to complete the WRITE operation to

the mode register and is the minimum time required between the two MRS commands

shown in the tMRD Timing figure.

Some of the mode register settings affect address/command/control input functionali-

ty. In these cases, the next MRS command can be allowed when the function being up-

dated by the current MRS command is completed. These MRS commands don’t apply

tMRD timing to the next MRS command; however, the input cases have unique MR set-

ting procedures, so refer to individual function descriptions:

• Gear-down mode

• Per-DRAM addressability

• CMD address latency

• CA parity latency mode

•V

REFDQ training value

•V

REFDQ training mode

•V

REFDQ training range

Some mode register settings may not be supported because they are not required by

certain speed bins.

8Gb: x4, x8, x16 DDR4 SDRAM

Programming Mode Registers

CCMTD-1725822587-9875

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Figure 17: tMRD Timing

T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2

Don’t Care

ValidValid Valid MRS

MRS

DES DES DESDES DES Valid

CK_t

CK_c

Command

Settings

CKE

Updating settings

Address Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

MRD

Time Break

Old settings

Notes: 1. This timing diagram depicts CA parity mode “disabled” case.

2. tMRD applies to all MRS commands with the following exceptions:

Gear-down mode

CA parity latency mode

CMD address latency

Per-DRAM addressability mode

VREFDQ training value, VREFDQ training mode, and VREFDQ training range

The MRS command to nonMRS command delay, tMOD, is required for the DRAM to

update features, except for those noted in note 2 in figure below where the individual

function descriptions may specify a different requirement. tMOD is the minimum time

required from an MRS command to a nonMRS command, excluding DES, as shown in

the tMOD Timing figure.

Figure 18: tMOD Timing

T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2

Don’t Care

ValidValid Valid MRS

DES DES DESDES DES ValidValid

CK_t

CK_c

Command

Settings

CKE

Updating settings New settings

Address Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

MOD

Time Break

Old settings

Notes: 1. This timing diagram depicts CA parity mode “disabled” case.

2. tMOD applies to all MRS commands with the following exceptions:

DLL enable, DLL RESET, Gear-down mode

VREFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQ

training range

8Gb: x4, x8, x16 DDR4 SDRAM

Programming Mode Registers

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Maximum power savings mode, Per-DRAM addressability mode, and CA parity latency

mode

The mode register contents can be changed using the same command and timing re-

quirements during normal operation as long as the device is in idle state; that is, all

banks are in the precharged state with tRP satisfied, all data bursts are completed, and

CKE is HIGH prior to writing into the mode register. If the RTT(NOM) feature is enabled in

the mode register prior to and/or after an MRS command, the ODT signal must contin-

uously be registered LOW, ensuring RTT is in an off state prior to the MRS command.

The ODT signal may be registered HIGH after tMOD has expired. If the RTT(NOM) feature

is disabled in the mode register prior to and after an MRS command, the ODT signal

can be registered either LOW or HIGH before, during, and after the MRS command. The

mode registers are divided into various fields depending on functionality and modes.

In some mode register setting cases, function updating takes longer than tMOD. This

type of MRS does not apply tMOD timing to the next valid command, excluding DES.

These MRS command input cases have unique MR setting procedures, so refer to indi-

vidual function descriptions.

8Gb: x4, x8, x16 DDR4 SDRAM

Programming Mode Registers

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Mode Register 0

Mode register 0 (MR0) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR0 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR0 Register

Definition table.

Table 6: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 7: MR0 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

13,11:9 WR (WRITE recovery)/RTP (READ-to-PRECHARGE)

0000 = 10 / 5 clocks1

0001 = 12 / 6 clocks

0010 = 14 / 7 clocks1

0011 = 16 / 8 / clocks

0100 = 18 / 9 clocks1

0101 = 20 /10 clocks

0110 = 24 / 12 clocks

0111 = 22 / 11 clocks1

1000 = 26 / 13 clocks1

1001 = 28 / 14 clocks2

1010 through 1111 = Reserved

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 0

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Table 7: MR0 Register Definition (Continued)

Mode

8DLL reset

0 = No

1 = Yes

7Test mode (TM) – Manufacturer use only

0 = Normal operating mode, must be programmed to 0

12, 6:4, 2 CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out

00000 = 9 clocks1

00001 = 10 clocks

00010 = 11 clocks1

00011 = 12 clocks

00100 = 13 clocks1

00101 = 14 clocks

00110 = 15 clocks1

00111 = 16 clocks

01000 = 18 clocks

01001 = 20 clocks

01010 = 22 clocks

01011 = 24 clocks

01100 = 23 clocks1

01101 = 17 clocks1

01110 = 19 clocks1

01111 = 21 clocks 1

10000 = 25 clocks

10001 = 26 clocks

10011 = 28 clocks

10100 = 29 clocks1

10101 = 30 clocks

10110 = 31 clocks1

10111 = 32 clocks

3Burst type (BT) – Data burst ordering within a READ or WRITE burst access

0 = Nibble sequential

1 = Interleave

1:0 Burst length (BL) – Data burst size associated with each read or write access

00 = BL8 (fixed)

01 = BC4 or BL8 (on-the-fly)

10 = BC4 (fixed)

11 = Reserved

Notes: 1. Not allowed when 1/4 rate gear-down mode is enabled.

2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28

clocks and RTP should be set to 14 clocks.

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order.

The ordering of accesses within a burst is determined by the burst length, burst type,

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 0

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and the starting column address as shown in the following table. Burst length options

include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec-

ted coincidentally with the registration of a READ or WRITE command via A12/BC_n.

Table 8: Burst Type and Burst Order

Note 1 applies to the entire table

Burst

Length

READ/

WRITE

Starting

Column Address

(A[2, 1, 0])

Burst Type = Sequential

(Decimal)

Burst Type = Interleaved

(Decimal) Notes

BC4 READ 0 0 0 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 2, 3

0 0 1 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3

0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T 2, 3

0 1 1 3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T 2, 3

1 0 0 4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T 2, 3

1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T 2, 3

1 1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T 2, 3

1 1 1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T 2, 3

WRITE 0, V, V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 2, 3

1, V, V 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 2, 3

BL8 READ 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

WRITE V, V, V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 3

Notes: 1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a

burst.

2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts

two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and

tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in-

ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during

column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting

point for tWR and tWTR will not be pulled in by two clocks as described in the BC4

(fixed) case.

3. T = Output driver for data and strobes are in High-Z.

V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.

X = “Don’t Care.”

CAS Latency

The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS laten-

cy is the delay, in clock cycles, between the internal READ command and the availability

of the first bit of output data. The device does not support half-clock latencies. The

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 0

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overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL +

CL.

Test Mode

The normal operating mode is selected by MR0[7] and all other bits set to the desired

values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1

places the device into a DRAM manufacturer-defined test mode to be used only by the

manufacturer, not by the end user. No operations or functionality is specified if MR0[7]

= 1.

Write Recovery (WR)/READ-to-PRECHARGE

The programmed write recovery (WR) value is used for the auto precharge feature along

with tRP to determine tDAL. WR for auto precharge (MIN) in clock cycles is calculated

by dividing tWR (in ns) by tCK (in ns) and rounding to the next integer using the round-

ing algorithms found in the Converting Time-Based Specifications to Clock-Based Re-

quirements section. The WR value must be programmed to be equal to or larger than

tWR (MIN). When both DM and write CRC are enabled in the mode register, the device

calculates CRC before sending the write data into the array; tWR values will change

when enabled. If there is a CRC error, the device blocks the WRITE operation and dis-

cards the data.

Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in

clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding to the next

integer using the rounding algorithms found in the Converting Time-Based Specifica-

tions to Clock-Based Requirements section. The RTP value in the mode register must be

programmed to be equal to or larger than RTP (MIN). The programmed RTP value is

used with tRP to determine the ACT timing to the same bank.

DLL RESET

The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL

RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET

should be applied. Any time the DLL RESET function is used, tDLLK must be met before

functions requiring the DLL can be used. Such as READ commands or synchronous

ODT operations, for example.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 0

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Mode Register 1

Mode register 1 (MR1) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR1 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR1 Register

Definition table.

Table 9: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 10: MR1 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

12 Data output disable (Qoff) – Output buffer disable

0 = Enabled (normal operation)

1 = Disabled (both ODI and RTT)

11 Termination data strobe (TDQS) – Additional termination pins (x8 configuration only)

0 = TDQS disabled

1 = TDQS enabled

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 1

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Table 10: MR1 Register Definition (Continued)

Mode

10, 9, 8 Nominal ODT (RTT(NOM) – Data bus termination setting

000 = RTT(NOM) disabled

001 = RZQ/4 (60 ohm)

010 = RZQ/2 (120 ohm)

011 = RZQ/6 (40 ohm)

100 = RZQ/1 (240 ohm)

101 = RZQ/5 (48 ohm)

110 = RZQ/3 (80 ohm)

111 = RZQ/7 (34 ohm)

7Write leveling (WL) – Write leveling mode

0 = Disabled (normal operation)

1 = Enabled (enter WL mode)

13, 6, 5 Rx CTLE Control

000 = Vendor Default

001 = Vendor Defined

010 = Vendor Defined

011 = Vendor Defined

100 = Vendor Defined

101 = Vendor Defined

110 = Vendor Defined

111 = Vendor Defined

4, 3 Additive latency (AL) – Command additive latency setting

00 = 0 (AL disabled)

01 = CL - 11

10 = CL - 2

11 = Reserved

2, 1 Output driver impedance (ODI) – Output driver impedance setting

00 = RZQ/7 (34 ohm)

01 = RZQ/5 (48 ohm)

10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm)

11 = Reserved

0DLL enable – DLL enable feature

0 = DLL disabled

1 = DLL enabled (normal operation)

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

DLL Enable/DLL Disable

The DLL must be enabled for normal operation and is required during power-up initial-

ization and upon returning to normal operation after having the DLL disabled. During

normal operation (DLL enabled with MR1[0]) the DLL is automatically disabled when

entering the SELF REFRESH operation and is automatically re-enabled upon exit of the

SELF REFRESH operation. Any time the DLL is enabled and subsequently reset, tDLLK

clock cycles must occur before a READ or SYNCHRONOUS ODT command can be is-

sued to allow time for the internal clock to be synchronized with the external clock. Fail-

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 1

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ing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON,

or tAOF parameters.

During tDLLK, CKE must continuously be registered HIGH. The device does not require

DLL for any WRITE operation, except when RTT(WR) is enabled and the DLL is required

for proper ODT operation.

The direct ODT feature is not supported during DLL off mode. The ODT resistors must

be disabled by continuously registering the ODT pin LOW and/or by programming the

RTT(NOM) bits MR1[9,6,2] = 000 via an MRS command during DLL off mode.

The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT

externally, use the MRS command to set RTT(WR), MR2[10:9] = 00.

Output Driver Impedance Control

The output driver impedance of the device is selected by MR1[2,1], as shown in the MR1

ODT RTT(NOM) Values

The device is capable of providing three different termination values: RTT(Park), RTT(NOM),

and RTT(WR). The nominal termination value, RTT(NOM), is programmed in MR1. A sepa-

rate value, RTT(WR), may be programmed in MR2 to enable a unique RTT value when

ODT is enabled during WRITE operations. The RTT(WR) value can be applied during

WRITE commands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is pro-

gramed in MR5. RTT(Park) provides a termination value when the ODT signal is LOW.

Additive Latency

The ADDITIVE LATENCY (AL) operation is supported to make command and data

buses efficient for sustainable bandwidths in the device. In this operation, the device al-

lows a READ or WRITE command (either with or without auto precharge) to be issued

immediately after the ACTIVATE command. The command is held for the time of AL be-

fore it is issued inside the device. READ latency (RL) is controlled by the sum of the AL

and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the sum of

the AL and CAS WRITE latency (CWL) register settings.

Table 11: Additive Latency (AL) Settings

A4 A3 AL

0 0 0 (AL disabled)

0 1 CL - 1

1 0 CL - 2

1 1 Reserved

Note: 1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 regis-

ter.

Rx CTLE Control

The Mode Register for Rx CTLE Control MR1[A13,A6,A5] is vendor specific. Since CTLE

circuits can not be typically bypassed a disable option is not provided. Instead, a vendor

optimized setting is given. It should be noted that the settings are not specifically linear

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 1

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in relationship to the vendor optimized setting, so the host may opt to instead walk

through all the provided options and use the setting that works best in their environ-

ment.

Write Leveling

For better signal integrity, the device uses fly-by topology for the commands, addresses,

control signals, and clocks. Fly-by topology benefits from a reduced number of stubs

and their lengths, but it causes flight-time skew between clock and strobe at every

DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS,

and tDSH specifications. Therefore, the device supports a write leveling feature that al-

lows the controller to compensate for skew.

Output Disable

The device outputs may be enabled/disabled by MR1[12] as shown in the MR1 Register

Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ

and DQS) are disconnected from the device, which removes any loading of the output

drivers. For example, this feature may be useful when measuring module power. For

normal operation, set MR1[12] to 0.

Termination Data Strobe

Termination data strobe (TDQS) is a feature of the x8 device and provides additional

termination resistance outputs that may be useful in some system configurations. Be-

cause this function is available only in a x8 configuration, it must be disabled for x4 and

x16 configurations.

While TDQS is not supported in x4 or x16 configurations, the same termination resist-

ance function that is applied to the TDQS pins is applied to the DQS pins when enabled

via the mode register.

The TDQS, DBI, and DATA MASK (DM) functions share the same pin. When the TDQS

function is enabled via the mode register, the DM and DBI functions are not supported.

When the TDQS function is disabled, the DM and DBI functions can be enabled sepa-

rately.

Table 12: TDQS Function Matrix

TDQS Data Mask (DM) WRITE DBI READ DBI

Disabled Enabled Disabled Enabled or disabled

Disabled Enabled Enabled or disabled

Disabled Disabled Enabled or disabled

Enabled Disabled Disabled Disabled

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 1

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Mode Register 2

Mode register 2 (MR2) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR2 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR2 Register

Definition table.

Table 13: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 14: MR2 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

13 RFU

0 = Must be programmed to 0

1 = Reserved

12 WRITE data bus CRC

0 = Disabled

1 = Enabled

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 2

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Table 14: MR2 Register Definition (Continued)

Mode

11:9 Dynamic ODT (RTT(WR)) – Data bus termination setting during WRITEs

000 = RTT(WR) disabled (WRITE does not affect RTT value)

001 = RZQ/2 (120 ohm)

010 = RZQ/1 (240 ohm)

011 = High-Z

100 = RZQ/3 (80 ohm)

101 = Reserved

110 = Reserved

111 = Reserved

7:6 Low-power auto self refresh (LPASR) – Mode summary

00 = Manual mode - Normal operating temperature range (TC: -40°C–85°C)

01 = Manual mode - Reduced operating temperature range (TC: -40°C–45°C)

10 = Manual mode - Extended operating temperature range (TC: -40°C–105°C)

11 = ASR mode - Automatically switching among all modes

5:3 CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in

1tCK WRITE preamble

000 = 9 (DDR4-1600)1

001 = 10 (DDR4-1866)

010 = 11 (DDR4-2133/1600)1

011 = 12 (DDR4-2400/1866)

100 = 14 (DDR4-2666/2133)

101 = 16 (DDR4-2933,3200/2400)

110 = 18 (DDR4-2666)

111 = 20 (DDR4-2933, 3200)

CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in

2tCK WRITE preamble

000 = N/A

001 = N/A

010 = N/A

011 = N/A

100 = 14 (DDR4-2400)

101 = 16 (DDR4-2666/2400)

110 = 18 (DDR4-2933, 3200/2666)

111 = 20 (DDR4-2933, 3200)

8, 2 RFU

0 = Must be programmed to 0

1 = Reserved

1:0 RFU

0 = Must be programmed to 0

1 = Reserved

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 2

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CAS WRITE Latency

CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Defini-

tion table. CWL is the delay, in clock cycles, between the internal WRITE command and

the availability of the first bit of input data. The device does not support any half-clock

latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity la-

tency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.

Low-Power Auto Self Refresh

Low-power auto self refresh (LPASR) is supported in the device. Applications requiring

SELF REFRESH operation over different temperature ranges can use this feature to opti-

mize the IDD6 current for a given temperature range as specified in the MR2 Register

Definition table.

Dynamic ODT

In certain applications and to further enhance signal integrity on the data bus, it is de-

sirable to change the termination strength of the device without issuing an MRS com-

mand. This may be done by configuring the dynamic ODT (RTT(WR)) settings in

MR2[11:9]. In write leveling mode, only RTT(NOM) is available.

Write Cyclic Redundancy Check Data Bus

The write cyclic redundancy check (CRC) data bus feature during writes has been added

to the device. When enabled via the mode register, the data transfer size goes from the

normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for

the CRC information.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 2

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Mode Register 3

Mode register 3 (MR3) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR3 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR3 Register

Definition table.

Table 15: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 16: MR3 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

13 RFU

0 = Must be programmed to 0

1 = Reserved

12:11 Multipurpose register (MPR) – Read format

00 = Serial

01 = Parallel

10 = Staggered

11 = Reserved

10:9 WRITE CMD latency when CRC/DM enabled

00 = 4CK (DDR4-1600)

01 = 5CK (DDR4-1866/2133/2400/2666)

10 = 6CK (DDR4-2933/3200)

11 = Reserved

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 3

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Table 16: MR3 Register Definition (Continued)

Mode

8:6 Fine granularity refresh mode

000 = Normal mode (fixed 1x)

001 = Fixed 2x

010 = Fixed 4x

011 = Reserved

100 = Reserved

101 = On-the-fly 1x/2x

110 = On-the-fly 1x/4x

111 = Reserved

5Temperature sensor status

0 = Disabled

1 = Enabled

4Per-DRAM addressability

0 = Normal operation (disabled)

1 = Enable

3Gear-down mode – Ratio of internal clock to external data rate

0 = [1:1]; (1/2 rate data)

1 = [2:1]; (1/4 rate data)

2Multipurpose register (MPR) access

0 = Normal operation

1 = Data flow from MPR

1:0 MPR page select

00 = Page 0

01 = Page 1

10 = Page 2

11 = Page 3 (restricted for DRAM manufacturer use only)

Multipurpose Register

The multipurpose register (MPR) is used for several features:

• Readout of the contents of the MRn registers

• WRITE and READ system patterns used for data bus calibration

• Readout of the error frame when the command address parity feature is enabled

To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of

read data from the MPR. Prior to issuing the MRS command, all banks must be in the

idle state (all banks precharged and tRP met). After MPR is enabled, any subsequent RD

or RDA commands will be redirected to a specific mode register.

The mode register location is specified with the READ command using address bits. The

MR is split into upper and lower halves to align with a burst length limitation of 8. Pow-

er-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA com-

mands are not allowed during MPR mode. The RESET function is supported during

MPR mode, which requires device re-initialization.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 3

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WRITE Command Latency When CRC/DM is Enabled

The WRITE command latency (WCL) must be set when both write CRC and DM are en-

abled for write CRC persistent mode. This provides the extra time required when com-

pleting a WRITE burst when write CRC and DM are enabled. This means at data rates

less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at

data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is

used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less

than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed.

Fine Granularity Refresh Mode

This mode had been added to DDR4 to help combat the performance penalty due to

refresh lockout at high densities. Shortening tRFC and decreasing cycle time allows

more accesses to the chip and allows for increased scheduling flexibility.

Temperature Sensor Status

This mode directs the DRAM to update the temperature sensor status at MPR Page 2,

MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an

MPR read of the temperature sensor status bits occurs, the temperature sensor status

should be no older than 32ms.

Per-DRAM Addressability

This mode allows commands to be masked on a per device basis providing any device

in a rank (devices sharing the same command and address signals) to be programmed

individually. As an example, this feature can be used to program different ODT or VREF

values on DRAM devices within a given rank.

Gear-Down Mode

The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS com-

mand followed by a sync pulse to align the proper clock edge for operating the control

lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode,

no MRS command or sync pulse is required.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 3

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Mode Register 4

Mode register 4 (MR4) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR4 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR4 Register

Definition table.

Table 17: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.

Table 18: MR4 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

13 Hard Post Package Repair (hPPR mode)

0 = Disabled

1 = Enabled

12 WRITE preamble setting

0 = 1tCK toggle1

1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at

least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)

11 READ preamble setting

0 = 1tCK toggle1

1 = 2tCK toggle

10 READ preamble training

0 = Disabled

1 = Enabled

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 4

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Table 18: MR4 Register Definition (Continued)

Mode

9Self refresh abort mode

0 = Disabled

1 = Enabled

8:6 CMD (CAL) address latency

000 = 0 clocks (disabled)

001 =3 clocks1

010 = 4 clocks

011 = 5 clocks1

100 = 6 clocks

101 = 8 clocks

110 = Reserved

111 = Reserved

5soft Post Package Repair (sPPR mode)

0 = Disabled

1 = Enabled

4Internal VREF monitor

0 = Disabled

1 = Enabled

3Temperature controlled refresh mode

0 = Disabled

1 = Enabled

2Temperature controlled refresh range

0 = Normal temperature mode

1 = Extended temperature mode

1Maximum power savings mode

0 = Normal operation

1 = Enabled

0MBIST-PPR

0 = Disabled

1 = Enabled

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

Hard Post Package Repair Mode

The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4

memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is

available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair

method of the device after placed in the system. One row per bank can be repaired. The

repair process is irrevocable so great care should be exercised when using.

Soft Post Package Repair Mode

The soft post package repair (sPPR) mode feature is JEDEC optional for 4Gb and 8Gb

DDR4 memories. Performing an MPR read to page 2 MPR0 [6] indicates whether sPPR

mode is available (A6 = 1) or not available (A6 = 0). sPPR mode provides a simple and

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 4

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easy repair method of the device after placed in the system. One row per bank can be

repaired. The repair process is revocable by either doing a reset or power-down or by

rewriting a new address in the same bank.

WRITE Preamble

Programmable WRITE preamble, tWPRE, can be set to 1tCK or 2tCK via the MR4 register.

The 1tCK setting is similar to DDR3. However, when operating in 2tCK WRITE preamble

mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL

setting supported in the applicable tCK range.

Some even settings will require addition of 2 clocks. If the alternate longer CWL was

used, the additional clocks will not be required.

READ Preamble

Programmable READ preamble tRPRE can be set to 1tCK or 2tCK via the MR4 register.

Both the 1tCK and 2tCK DDR4 preamble settings are different from that defined for the

DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller

to train (or read level) its data strobe receivers using the READ preamble training.

READ Preamble Training

Programmable READ preamble training can be set to 1tCK or 2tCK. This mode can be

used by the memory controller to train or READ level its data strobe receivers.

Temperature-Controlled Refresh

When temperature-controlled refresh mode is enabled, the device may adjust the inter-

nal refresh period to be longer than tREFI of the normal temperature range by skipping

external REFRESH commands with the proper gear ratio. For example, the DRAM tem-

perature sensor detected less than 45°C. Normal temperature mode covers the range of

-40°C to 85°C, while the extended temperature range covers -40°C to 105°C.

Command Address Latency

COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled

or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) be-

tween a CS_n registered LOW and its corresponding registered command and address.

The value of CAL (in clocks) must be programmed into the mode register according to

the tCAL(ns)/tCK(ns) rounding algorithms found in the Converting Time-Based Specifi-

cations to Clock-Based Requirements section.

Internal VREF Monitor

This mode enables output of internally generated VREFDQ for monitoring on DQ0, DQ1,

DQ2, and DQ3. May be used during VREFDQ training and test. While in this mode, RTT

should be set to High-Z. VREF_time must be increased by 10ns if DQ load is 0pF, plus an

additional 15ns per pF of loading. This measurement is for verification purposes and is

NOT an external voltage supply pin.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 4

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Maximum Power Savings Mode

This mode provides the lowest power mode where data retention is not required. When

the device is in the maximum power saving mode, it does not need to guarantee data

retention or respond to any external command (except the MAXIMUM POWER SAVING

MODE EXIT command and during the assertion of RESET_n signal LOW).

MBIST-PPR

This mode is JEDEC optional and allows for a self-contained DRAM test and repair.

Please refer to the Features list on page 1 for a list of die revisions that support MBIST-

PPR.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 4

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Mode Register 5

Mode register 5 (MR5) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR5 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR5 Register

Definition table.

Table 19: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 20: MR5 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

13 RFU

0 = Must be programmed to 0

1 = Reserved

12 Data bus inversion (DBI) – READ DBI enable

0 = Disabled

1 = Enabled

11 Data bus inversion (DBI) – WRITE DBI enable

0 = Disabled

1 = Enabled

10 Data mask (DM)

0 = Disabled

1 = Enabled

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 5

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Table 20: MR5 Register Definition (Continued)

Mode

9CA parity persistent error mode

0 = Disabled

1 = Enabled

8:6 Parked ODT value (RTT(Park))

000 = RTT(Park) disabled

001 = RZQ/4 (60 ohm)

010 = RZQ/2 (120 ohm)

011 = RZQ/6 (40 ohm)

100 = RZQ/1 (240 ohm)

101 = RZQ/5 (48 ohm)

110 = RZQ/3 (80 ohm)

111 = RZQ/7 (34 ohm)

5ODT input buffer for power-down

0 = Buffer enabled

1 = Buffer disabled

4CA parity error status

0 = Clear

1 = Error

3CRC error status

0 = Clear

1 = Error

2:0 CA parity latency mode

000 = Disable

001 = 4 clocks (DDR4-1600/1866/2133)

010 = 5 clocks (DDR4-2400/2666)1

011 = 6 clocks (DDR4-2933/3200)

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

Data Bus Inversion

The DATA BUS INVERSION (DBI) function has been added to the device and is suppor-

ted only for x8 and x16 configurations (x4 is not supported). The DBI function shares a

common pin with the DM and TDQS functions. The DBI function applies to both READ

and WRITE operations; Write DBI cannot be enabled at the same time the DM function

is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three

functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an

MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12.

DBI is not supported for 3DS devices and should be disabled in MR5.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 5

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Data Mask

The DATA MASK (DM) function, also described as a partial write, has been added to the

device and is supported only for x8 and x16 configurations (x4 is not supported). The

DM function shares a common pin with the DBI and TDQS functions. The DM function

applies only to WRITE operations and cannot be enabled at the same time the write DBI

function is enabled. Refer to the TDQS Function Matrix table for valid configurations for

all three functions (TDQS/DM/DBI).

CA Parity Persistent Error Mode

Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA

parity checking while the parity error status bit remains set at 1. However, with CA pari-

ty persistent mode enabled, CA parity checking continues to be performed when the

parity error status bit is set to a 1.

ODT Input Buffer for Power-Down

This feature determines whether the ODT input buffer is on or off during power-down.

If the input buffer is configured to be on (enabled during power-down), the ODT input

signal must be at a valid logic level. If the input buffer is configured to be off (disabled

during power-down), the ODT input signal may be floating and the device does not pro-

vide RTT(NOM) termination. However, the device may provide RTT(Park) termination de-

pending on the MR settings. This is primarily for additional power savings.

CA Parity Error Status

The device will set the error status bit to 1 upon detecting a parity error. The parity error

status bit remains set at 1 until the device controller clears it explicitly using an MRS

command.

CRC Error Status

The device will set the error status bit to 1 upon detecting a CRC error. The CRC error

status bit remains set at 1 until the device controller clears it explicitly using an MRS

command.

CA Parity Latency Mode

CA parity is enabled when a latency value, dependent on tCK, is programmed; this ac-

counts for parity calculation delay internal to the device. The normal state of CA parity

is to be disabled. If CA parity is enabled, the device must ensure there are no parity er-

rors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16,

CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group

bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 5

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Mode Register 6

Mode register 6 (MR6) controls various device operating modes as shown in the follow-

ing register definition table. Not all settings listed may be available on a die; only set-

tings required for speed bin support are available. MR6 is written by issuing the MRS

command while controlling the states of the BGx, BAx, and Ax address pins. The map-

ping of address pins during the MRS command is shown in the following MR6 Register

Definition table.

Table 21: Address Pin Mapping

Address

bus

BG1 BG0 BA1 BA0 A17 RAS

CAS

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode

2120191817–––131211109876543210

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 22: MR6 Register Definition

Mode

21 RFU

0 = Must be programmed to 0

1 = Reserved

20:18 MR select

000 = MR0

001 = MR1

010 = MR2

011 = MR3

100 = MR4

101 = MR5

110 = MR6

111 = DNU

17 NA on 4Gb and 8Gb, RFU

0 = Must be programmed to 0

1 = Reserved

12:10 Data rate

000 = Data rateื 1333 Mb/s (1333 Mb/s)

001 = 1333 Mb/s < Data rate ื 1866 Mb/s (1600, 1866 Mb/s)

010 = 1866 Mb/s < Data rate ื 2400 Mb/s (2133, 2400 Mb/s)

011 = 2400 Mb/s < Data rate ื 2666 Mb/s (2666 Mb/s)

100 = 2666 Mb/s < Data rate ื 3200 Mb/s (2933, 3200 Mb/s)

101 = Reserved

110 = Reserved

111 = Reserved

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 6

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Table 22: MR6 Register Definition (Continued)

Mode

13, 9, 8 RFU

Default = 000; Must be programmed to 000

001 = Reserved

010 = Reserved

011 = Reserved

100 = Reserved

101 = Reserved

110 = Reserved

111 = Reserved

7VREF Calibration Enable

0 = Disable

1 = Enable

6VREF Calibration Range

0 = Range 1

1 = Range 2

5:0 VREF Calibration Value

See the VREFDQ Range and Levels table in the VREFDQ Calibration section

Data Rate Programming

The device controller must program the correct data rate according to the operating fre-

quency.

VREFDQ Calibration Enable

VREFDQ calibration is where the device internally generates its own VREFDQ to be used by

the DQ input receivers. The VREFDQ value will be output on any DQ of DQ[3:0] for evalu-

ation only. The device controller is responsible for setting and calibrating the internal

VREFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assumed

that the controller will use a series of writes and reads in conjunction with VREFDQ ad-

justments to optimize and verify the data eye. Enabling VREFDQ calibration must be used

whenever values are being written to the MR6[6:0] register.

VREFDQ Calibration Range

The device defines two VREFDQ calibration ranges: Range 1 and Range 2. Range 1 sup-

ports VREFDQ between 60% and 92% of VDDQ while Range 2 supports VREFDQ between

45% and 77% of VDDQ, as seen in VREFDQ Specification table. Although not a restriction,

Range 1 was targeted for module-based designs and Range 2 was added to target point-

to-point designs.

VREFDQ Calibration Value

Fifty settings provide approximately 0.65% of granularity steps sizes for both Range 1

and Range 2 of VREFDQ, as seen in VREFDQ Range and Levels table in the VREFDQ Calibra-

tion section.

8Gb: x4, x8, x16 DDR4 SDRAM

Mode Register 6

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Truth Tables

Table 23: Truth Table – Command

Notes 1–5 apply to the entire table; Note 6 applies to all READ/WRITE commands

Function

Symbol

Prev.

CKE

Pres.

CKE

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

BG[1:0]

BA [1:0]

C[2:0]

A12/BC_n

A[13,11]

A10/AP

A[9:0]

Notes

MODE REGISTER SET MRS H H L H L L L BG BA V OP code 7

REFRESH REF H H L H L L H V V VVVVV

Self refresh entry SRE H L L H L L H V V V V V V V 8, 9, 10

Self refresh exit SRX L H H X X X X X X X X X X X 8, 9, 10,

LHHHHVVVVVVV

Single-bank PRECHARGE PRE H H L H L H L BG BA V V V L V

PRECHARGE all banks PREA H H L H L H L V V V V V H V

Reserved for future use RFU H H LHLHH RFU

Bank ACTIVATE ACT H H L L Row address (RA) BG BA V Row address (RA)

WRITE BL8 fixed, BC4 fixed WR H H L H H L L BG BA V V V L CA

BC4OTF WRS4 H H L H H L L BG BA V L V L CA

BL8OTF WRS8 H H L H H L L BG BA V H V L CA

WRITE

with auto

precharge

BL8 fixed, BC4 fixed WRA H H L H H L L BG BA V V V H CA

BC4OTF WRAS4 H H L H H L L BG BA V L V H CA

BL8OTF WRAS8 H H L H H L L BG BA V H V H CA

READ BL8 fixed, BC4 fixed RD H H L H H L H BG BA V V V L CA

BC4OTF RDS4 H H L H H L H BG BA V L V L CA

BL8OTF RDS8 H H L H H L H BG BA V H V L CA

READ

with auto

precharge

BL8 fixed, BC4 fixed RDA H H L H H L H BG BA V V V H CA

BC4OTF RDAS4 H H L H H L H BG BA V L V H CA

BL8OTF RDAS8 H H L H H L H BG BA V H V H CA

NO OPERATION NOP H H L H H H H V V V V V V V 12

Device DESELECTED DES H H H X X X X X X X XXXX 13

Power-down entry PDE H L H X X X X X X X X X X X 10, 14

Power-down exit PDX L H H X X X X X XXXXXX10, 14

ZQ CALIBRATION LONG ZQCL H H L H H H L X X X X X H X

ZQ CALIBRATION SHORT ZQCS H H L H H H L X X X X X L X

8Gb: x4, x8, x16 DDR4 SDRAM

Truth Tables

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Notes: 1. • BG = Bank group address

• BA = Bank address

• RA = Row address

• CA = Column address

• BC_n = Burst chop

• X = “Don’t Care”

• V = Valid

2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/

A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA

are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16,

CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respec-

tively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address

pins A16, A15, and A14, respectively.

3. RESET_n is enabled LOW and is used only for asynchronous reset and must be main-

tained HIGH during any function.

4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a

bank group is being operated upon. For MRS commands, the BG and BA selects the spe-

cific mode register location.

5. V means HIGH or LOW (but a defined logic level), and X means either defined or unde-

fined (such as floating) logic level.

6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF)

BL will be defined by MRS.

7. During an MRS command, A17 is RFU and is device density- and configuration-depend-

ent.

8. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh.

9. VPP and VREF (VREFCA) must be maintained during SELF REFRESH operation.

10. Refer to the Truth Table – CKE table for more details about CKE transition.

11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has

the choice of either synchronous or asynchronous.

12. The NO OPERATION (NOP) command may be used only when exiting maximum power

saving mode or when entering gear-down mode.

13. The NOP command may not be used in place of the DESELECT command.

14. The power-down mode does not perform any REFRESH operation.

8Gb: x4, x8, x16 DDR4 SDRAM

Truth Tables

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Table 24: Truth Table – CKE

Notes 1–7, 9, and 20 apply to the entire table

Current State

CKE

Command (n) Action (n) Notes

Previous Cycle

(n - 1)

Present Cycle

(n)

Power-down L L X Maintain power-down 8, 10, 11

L H DES Power-down exit 8, 10, 12

Self refresh L L X Maintain self refresh 11, 13

L H DES Self refresh exit 8, 13, 14, 15

Bank(s) active H L DES Active power-down entry 8, 10, 12, 16

Reading H L DES Power-down entry 8, 10, 12, 16, 17

Writing H L DES Power-down entry 8, 10, 12, 16, 17

Precharging H L DES Power-down entry 8, 10, 12, 16, 17

Refreshing H L DES Precharge power-down entry 8, 12

All banks idle H L DES Precharge power-down entry 8, 10, 12, 16, 18

H L REFRESH Self refresh 16, 18, 19

Notes: 1. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock

edge n.

2. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the

previous clock edge.

3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of

COMMAND (n); ODT is not included here.

4. All states and sequences not shown are illegal or reserved unless explicitly described

elsewhere in this document.

5. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh.

6. During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must be

maintained until 1 nCK prior to tCKE (MIN) being satisfied (at which time CKE may tran-

sition again).

7. DESELECT and NOP are defined in the Truth Table – Command table.

8. For power-down entry and exit parameters, see the Power-Down Modes section.

9. CKE LOW is allowed only if tMRD and tMOD are satisfied.

10. The power-down mode does not perform any REFRESH operations.

11. X = "Don’t Care" (including floating around VREF) in self refresh and power-down. X al-

so applies to address pins.

12. The DESELECT command is the only valid command for power-down entry and exit.

13. VPP and VREFCA must be maintained during SELF REFRESH operation.

14. On self refresh exit, the DESELECT command must be issued on every clock edge occur-

ring during the tXS period. READ or ODT commands may be issued only after tXSDLL is

satisfied.

15. The DESELECT command is the only valid command for self refresh exit.

16. Self refresh cannot be entered during READ or WRITE operations. For a detailed list of

restrictions see the SELF REFRESH Operation and Power-Down Modes sections.

17. If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command,

then precharge power-down is entered; otherwise, active power-down is entered.

8Gb: x4, x8, x16 DDR4 SDRAM

Truth Tables

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18. Idle state is defined as all banks are closed (tRP, tDAL, and so on, satisfied), no data

bursts are in progress, CKE is HIGH, and all timings from previous operations are satis-

fied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on), as well as all self refresh ex-

it and power-down exit parameters are satisfied (tXS, tXP, tXSDLL, and so on).

19. Self refresh mode can be entered only from the all banks idle state.

20. For more details about all signals, see the Truth Table – Command table; must be a legal

command as defined in the table.

NOP Command

The NO OPERATION (NOP) command was originally used to instruct the selected

DDR4 SDRAM to perform a NOP (CS_n = LOW and ACT_n, RAS_n/A16, CAS_n/A15, and

WE_n/A14 = HIGH). This prevented unwanted commands from being registered during

idle or wait states. NOP command general support has been removed and the com-

mand should not be used unless specifically allowed, which is when exiting maximum

power-saving mode or when entering gear-down mode.

DESELECT Command

The deselect function (CS_n HIGH) prevents new commands from being executed;

therefore, with this command, the device is effectively deselected. Operations already in

progress are not affected.

DLL-Off Mode

DLL-off mode is entered by setting MR1 bit A0 to 0, which will disable the DLL for sub-

sequent operations until the A0 bit is set back to 1. The MR1 A0 bit for DLL control can

be switched either during initialization or during self refresh mode. Refer to the Input

Clock Frequency Change section for more details.

The maximum clock frequency for DLL-off mode is specified by the parameter

tCKDLL_OFF.

Due to latency counter and timing restrictions, only one CL value and CWL value (in

MR0 and MR2 respectively) are supported. The DLL-off mode is only required to sup-

port setting both CL = 10 and CWL = 9.

DLL-off mode will affect the read data clock-to-data strobe relationship (tDQSCK), but

not the data strobe-to-data relationship (tDQSQ, tQH). Special attention is needed to

line up read data to the controller time domain.

Compared with DLL-on mode, where tDQSCK starts from the rising clock edge (AL +

CL) cycles after the READ command, the DLL-off mode tDQSCK starts (AL + CL - 1) cy-

cles after the READ command. Another difference is that tDQSCK may not be small

compared to tCK (it might even be larger than tCK), and the difference between tDQSCK

(MIN) and tDQSCK (MAX) is significantly larger than in DLL-on mode. The tDQSCK

(DLL-off) values are undefined and the user is responsible for training to the data-eye.

The timing relations on DLL-off mode READ operation are shown in the following dia-

gram, where CL = 10, AL = 0, and BL = 8.

8Gb: x4, x8, x16 DDR4 SDRAM

NOP Command

CCMTD-1725822587-9875

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Figure 19: DLL-Off Mode Read Timing Operation

CK_c

CK_t

Command

T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14

Address

DQS_t, DQS_c

(DLL-on)

DQS_c

(DLL-on)

CL = 10, AL = 0

RL (DLL-on) = AL + CL = 10

RL (DLL-off) = AL + (CL - 1) = 9

tDQSCK (DLL-off) MAX

tDQSCK (DLL-off) MIN

tDQSCK (MAX)

DQS_t, DQS_c

(DLL-off)

DQS_c

(DLL-off)

DQS_c

(DLL-off)

DQS_t, DQS_c

(DLL-off)

RD DES DES DES DES DES DES DES DES DES DES

Don’t CareTransitioning data

DIN

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

DIN

b+1

DIN

b+2

DIN

b+3

DIN

b+4

DIN

b+5

DIN

b+6

DIN

b+7

DIN

b+1

DIN

b+2

DIN

b+3

DIN

b+4

DIN

b+5

DIN

b+6

DIN

b+7

DIN

b+1

DIN

b+2

DIN

b+3

DIN

b+4

DIN

b+5

DIN

b+6

DIN

b+7

(

)(

)

tDQSCK (MIN)

ARD

8Gb: x4, x8, x16 DDR4 SDRAM

DLL-Off Mode

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DLL-On/Off Switching Procedures

The DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for

subsequent operations until the A0 bit is set back to 1.

DLL Switch Sequence from DLL-On to DLL-Off

To switch from DLL-on to DLL-off requires the frequency to be changed during self re-

fresh, as outlined in the following procedure:

1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to dis-

able the DLL, the DRAM on-die termination resistors, RTT(NOM), must be in High-Z

before MRS to MR1.)

2. Set MR1 bit A0 to 1 to disable the DLL.

3. Wait tMOD.

4. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR is satisfied.

5. Change frequency, following the guidelines in the Input Clock Frequency Change

section.

6. Wait until a stable clock is available for at least tCKSRX at device inputs.

7. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-

tered HIGH until all tMOD timings from any MRS command are satisfied. In addi-

tion, if any ODT features were enabled in the mode registers when self refresh

mode was entered, the ODT signal must continuously be registered LOW until all

tMOD timings from any MRS command are satisfied. If RTT(NOM) was disabled in

the mode registers when self refresh mode was entered, the ODT signal is "Don't

Care."

8. Wait tXS_FAST, tXS_ABORT, or tXS, and then set mode registers with appropriate

values (an update of CL, CWL, and WR may be necessary; a ZQCL command can

also be issued after tXS_FAST).

•tXS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and

WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in

MR3 may be accessed provided the device is not in per-DRAM addressability

mode. Access to other device mode registers must satisfy tXS timing.

•tXS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh

and does not increment the refresh counter. The controller can issue a valid

command after a delay of tXS_ABORT. Upon exiting from self refresh, the device

requires a minimum of one extra REFRESH command before it is put back into

self refresh mode. This requirement remains the same regardless of the MRS bit

setting for self refresh abort.

•tXS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8,

RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.

9. Wait tMOD to complete.

The device is ready for the next command.

8Gb: x4, x8, x16 DDR4 SDRAM

DLL-On/Off Switching Procedures

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Figure 20: DLL Switch Sequence from DLL-On to DLL-Off

CK_c

CK_t

Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th

Don’t CareTime Break

CKE

Command

Enter self refresh Exit self refresh

ODT

Valid

SRE3DES SRX6

Valid Valid

MRS2

tXS_FAST

tXS_ABORT

tRP

tXS

Note 4

tCPDED

tIS

tCKSRE/tCKSRE_PAR tCKSRX5

Valid

Address Valid

Valid7Valid8Valid9

tIS tCKESR/tCKESR_PAR

Notes: 1. Starting in the idle state. RTT in stable state.

2. Disable DLL by setting MR1 bit A0 to 0.

3. Enter SR.

4. Change frequency.

5. Clock must be stable tCKSRX.

6. Exit SR.

7. Update mode registers allowed with DLL-off settings met.

8Gb: x4, x8, x16 DDR4 SDRAM

DLL-On/Off Switching Procedures

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DLL-Off to DLL-On Procedure

To switch from DLL-off to DLL-on (with required frequency change) during self refresh:

1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAM

ODT resistors (RTT(NOM)) must be in High-Z before self refresh mode is entered.)

2. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR are satisfied.

3. Change frequency (following the guidelines in the Input Clock Frequency Change

section).

4. Wait until a stable clock is available for at least tCKSRX at device inputs.

5. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-

tered HIGH until tDLLK timing from the subsequent DLL RESET command is sat-

isfied. In addition, if any ODT features were enabled in the mode registers when

self refresh mode was entered, the ODT signal must continuously be registered

LOW or HIGH until tDLLK timing from the subsequent DLL RESET command is

satisfied. If RTT(NOM) disabled in the mode registers when self refresh mode was

entered, the ODT signal is "Don't Care."

6. Wait tXS or tXS_ABORT, depending on bit 9 in MR4, then set MR1 bit A0 to 0 to en-

able the DLL.

7. Wait tMRD, then set MR0 bit A8 to 1 to start DLL reset.

8. Wait tMRD, then set mode registers with appropriate values; an update of CL,

CWL, and WR may be necessary. After tMOD is satisfied from any proceeding MRS

command, a ZQCL command can also be issued during or after tDLLK.

9. Wait for tMOD to complete. Remember to wait tDLLK after DLL RESET before ap-

plying any command requiring a locked DLL. In addition, wait for tZQoper in case

a ZQCL command was issued.

The device is ready for the next command.

Figure 21: DLL Switch Sequence from DLL-Off to DLL-On

CK_c

CK_t

Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th

Don’t CareTime Break

CKE

Command

Enter self refresh Exit self refresh

ODT

Valid

SRE3DES SRX6

Valid Valid

MRS2

tXS_ABORT

tRP tXS tMRD

Note 4Note 1

tCPDED

tIS

tCKSRE/tCKSRE_PAR tCKSRX5

Valid

Address Valid

Valid7

tIS

Valid7Valid7

tCKESR/tCKESR_PAR

Notes: 1. Starting in the idle state.

8Gb: x4, x8, x16 DDR4 SDRAM

DLL-On/Off Switching Procedures

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2. Enter SR.

3. Change frequency.

4. Clock must be stable tCKSRX.

5. Exit SR.

6. Set DLL to on by setting MR1 to A0 = 0.

7. Update mode registers.

8. Issue any valid command.

Input Clock Frequency Change

After the device is initialized, it requires the clock to be stable during almost all states of

normal operation. This means that after the clock frequency has been set and is in the

stable state, the clock period is not allowed to deviate except for what is allowed by the

clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequen-

cy can be changed from one stable clock rate to another stable clock rate only when in

self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequen-

cy.

After the device has been successfully placed in self refresh mode and tCKSRE/

tCKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Follow-

ing a "Don’t Care," changing the clock frequency is permissible, provided the new clock

frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the

sole purpose of changing the clock frequency, the self refresh entry and exit specifica-

tions must still be met as outlined in SELF REFRESH Operation.

For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5,

and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode,

READ and WRITE preamble, Command Address Latency, and data rate values.

When the clock rate is being increased (faster), the MR settings that require additional

clocks should be updated prior to the clock rate being increased. In particular, the PL

latency must be disabled when the clock rate changes, ie. while in self refresh mode. For

example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity

mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6.

The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter

self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self re-

fresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].

If the MR settings that require additional clocks are updated after the clock rate has

been increased, for example. after exiting self refresh mode, the required MR settings

must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is

RESET. If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration,

the updating of the required MR settings may be deferred to the next time the DRAM

enters the IDLE state.

If MR6 is issued prior to self refresh entry for the new data rate value, DLL will relock

automatically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0

must be issued to reset the DLL.

The device input clock frequency can change only within the minimum and maximum

operating frequency specified for the particular speed grade. Any frequency change be-

low the minimum operating frequency would require the use of DLL-on mode to DLL-

off mode transition sequence (see DLL-On/Off Switching Procedures).

8Gb: x4, x8, x16 DDR4 SDRAM

Input Clock Frequency Change

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Write Leveling

For better signal integrity, DDR4 memory modules use fly-by topology for the com-

mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re-

duced number of stubs and their length, but it also causes flight-time skew between

clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller

to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a

write leveling feature to allow the controller to compensate for skew. This feature may

not be required under some system conditions, provided the host can maintain the

tDQSS, tDSS, and tDSH specifications.

The memory controller can use the write leveling feature and feedback from the device

to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con-

troller involved in the leveling must have an adjustable delay setting on DQS to align the

rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously

feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller

repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab-

lished though this exercise would ensure the tDQSS specification. Besides tDQSS, tDSS

and tDSH specifications also need to be fulfilled. One way to achieve this is to combine

the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS

signals. Depending on the actual tDQSS in the application, the actual values for tDQSL

and tDQSH may have to be better than the absolute limits provided in the AC Timing

Parameters section in order to satisfy tDSS and tDSH specifications. A conceptual tim-

ing of this scheme is shown below.

Figure 22: Write Leveling Concept, Example 1

diff_DQS

T0 T1 T2 T3 T4 T5

CK_c

CK_t

T6 T7

Tn T0 T1 T2 T3 T4

CK_c

CK_t

T5 T6

0 or 1 00 0

0 or 1

Push DQS to capture

the 0-1 transition

111

Source

Destination

DQS driven by the controller during leveling mode must be terminated by the DRAM

based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be

terminated at the controller.

All data bits carry the leveling feedback to the controller across the DRAM configura-

tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.

Therefore, a separate feedback mechanism should be available for each byte lane. The

upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-

clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-

to-clock relationship.

8Gb: x4, x8, x16 DDR4 SDRAM

Write Leveling

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The figure below is another representative way to view the write leveling procedure. Al-

though it shows the clock varying to a static strobe, this is for illustrative purpose only;

the clock does not actually change phase, the strobe is what actually varies. By issuing

multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time

at which the clock edge arrives at the DRAM clock input buffer.

Figure 23: Write Leveling Concept, Example 2

XXX

CK_t

CK_c

CK_t

CK_c

CK_t

CK_c

DQS_t/

DQS_c

DQ (CK 0 to 1)

tWLH

tWLO

tWLS

0000000000000

0000000 XXX

111111111111111111

1111111111

DQ (CK 1 to 0)

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode

The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is fin-

ished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling

Procedures table). Note that in write leveling mode, only DQS terminations are activa-

ted and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TER-

MINATION Function in Leveling Mode table).

Table 25: MR Settings for Leveling Procedures

Function MR1 Enable Disable

Write leveling enable A7 1 0

Output buffer mode (Q off) A12 0 1

Table 26: DRAM TERMINATION Function in Leveling Mode

ODT Pin at DRAM DQS_t/DQS_c Termination DQ Termination

RTT(NOM) with ODT HIGH On Off

8Gb: x4, x8, x16 DDR4 SDRAM

Write Leveling

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Table 26: DRAM TERMINATION Function in Leveling Mode (Continued)

ODT Pin at DRAM DQS_t/DQS_c Termination DQ Termination

RTT(Park) with ODT LOW On Off

Notes: 1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1

and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] =

0), all RTT(NOM) and RTT(Park) settings are supported.

2. RTT(WR) is not allowed in write leveling mode and must be set to disable prior to enter-

ing write leveling mode.

Procedure Description

The memory controller initiates the leveling mode of all DRAM by setting bit 7 of MR1

to 1. When entering write leveling mode, the DQ pins are in undefined driving mode.

During write leveling mode, only the DESELECT command is supported, other than

MRS commands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]).

Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7] = 0)

may also change the other MR1 bits. Because the controller levels one rank at a time,

the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller

may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal,

unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is in-

creased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR

command), then ODT assertion should be delayed by DODTLon after tMOD is satisfied,

which means the delay is now tMOD + DODTLon.

The controller may drive DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN, at

which time the DRAM has applied ODT to these signals. After tDQSL and tWLMRD, the

controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sample

CK driven from the controller. tWLMRD (MAX) timing is controller dependent.

The DRAM samples CK status with the rising edge of DQS and provides feedback on all

the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of

tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the

transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.

There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller sam-

ples incoming DQ and either increments or decrements DQS delay setting and launch-

es the next DQS pulse after some time, which is controller dependent. After a 0-to-1

transition is detected, the controller locks the DQS delay setting, and write leveling is

achieved for the device. The following figure shows the timing diagram and parameters

for the overall write leveling procedure.

8Gb: x4, x8, x16 DDR4 SDRAM

Write Leveling

CCMTD-1725822587-9875

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Figure 24: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)

tMOD

tWLDQSEN

tWLMRD

tWLH

tDQSH6

tDQSL6tDQSH6

tDQSL6

tWLS

tWLH

tWLS

NOP

CK_t

CK_c5

Command

T1 T2

Early Prime DQ1

ODT

Late Prime DQ1

diff_DQS4

DES

MRS2DES DES DES DES DES DES DES DES DES

Don’t CareUndefined Driving Mode Time Break

tWLO

tWLO tWLO

tWLO

tWLOE

DES3

Notes: 1. The device drives leveling feedback on all DQs.

2. MRS: Load MR1 to enter write leveling mode.

3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.

DQS_t is shown with a solid line; DQS_c is shown with a dotted line.

4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line.

5. DQS needs to fulfill minimum pulse width requirements, tDQSH (MIN) and tDQSL (MIN),

as defined for regular WRITEs; the maximum pulse width is system dependent.

6. tWLDQSEN must be satisfied following equation when using ODT:

• DLL = Enable, then tWLDQSEN > tMOD (MIN) + DODTLon + tADC

• DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS

Write Leveling Mode Exit

Write leveling mode should be exited as follows:

1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see

~Tc0). Note that from this point on, DQ pins are in undefined driving mode and

will remain undefined, until tMOD after the respective MR command (Te1).

2. Drive ODT pin LOW (tIS must be satisfied) and continue registering LOW (see

Tb0).

3. After RTT is switched off, disable write leveling mode via the MRS command (see

Tc2).

4. After tMOD is satisfied (Te1), any valid command can be registered. (MR com-

mands can be issued after tMRD [Td1]).

8Gb: x4, x8, x16 DDR4 SDRAM

Write Leveling

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Figure 25: Write Leveling Exit

tMOD

tWLO

ODTL (OFF)

MRD

CK_t

T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1

CK_c

Command

ODT

RTT(DQS_t)

RTT(DQS_c)

RTT(DQ)

DQ1

DQS_t,

DQS_c

DESDES DES DES DES DES DES DES DES

Address MR1 Valid

Valid Valid

Valid

Don’t CareTransitioning Time Break

RTT(NON)

Undefined Driving Mode

tADC (MAX)

tADC (MIN)

DES

RTT(Park)

result = 1

Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t

HIGH just after the T0 state.

2. See previous figure for specific tWLO timing.

8Gb: x4, x8, x16 DDR4 SDRAM

Write Leveling

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Command Address Latency

DDR4 supports the command address latency (CAL) function as a power savings fea-

ture. This feature can be enabled or disabled via the MRS setting. CAL timing is defined

as the delay in clock cycles (tCAL) between a CS_n registered LOW and its correspond-

ing registered command and address. The value of CAL in clocks must be programmed

into the mode register (see MR1 Register Definition table) and is based on the tCAL(ns)/

tCK(ns) rounding algorithms found in the Converting Time-Based Specifications to

Clock-Based Requirements section.

Figure 26: CAL Timing Definition

CLK

CMD/ADDR

123456789101112131415

CS_n

tCAL

CAL gives the DRAM time to enable the command and address receivers before a com-

mand is issued. After the command and the address are latched, the receivers can be

disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the

command and address input receivers enabled for the duration of the command se-

quence.

Figure 27: CAL Timing Example (Consecutive CS_n = LOW)

CLK

CMD/ADDR

123456789101112

CS_n

8Gb: x4, x8, x16 DDR4 SDRAM

Command Address Latency

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When the CAL mode is enabled, additional time is required for the MRS command to

complete. The earliest the next valid command can be issued is tMOD_CAL, which

should be equal to tMOD + tCAL. The two following figures are examples.

Figure 28: CAL Enable Timing – tMOD_CAL

T0 T1 Ta0 Ta1 Ta2

CK_c

CK_t

Address

CS_n

Settings

Command

Ta3 Ta4

Old settings

MRS

Valid DES

DESDES DES

Valid Valid

Valid Valid Valid Valid ValidValid

Don’t CareTime Break

Tb0 Tb1 Tb2 Tb3

New settings

Valid Valid

Valid Valid Valid

tMOD_CAL

tCAL

Updating settings

DES DES DES

Note: 1. CAL mode is enabled at T1.

Figure 29: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled

T0 T1 Ta0 Ta1 Ta2

CK_c

CK_t

Address

CS_n

Settings

Command

Tb0 Tb1

Old settings

Valid DES

DESDES DES

Valid Valid

Valid Valid Valid Valid ValidValid

Don’t CareTime Break

Tb2 Tc0 Tc1 Tc2

New settings

Valid Valid Valid

tMOD_CAL

tCAL tCAL

Updating settings

DES DES DES

MRS Valid Valid

Note: 1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL set-

ting if modified.

8Gb: x4, x8, x16 DDR4 SDRAM

Command Address Latency

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When the CAL mode is enabled or being enabled, the earliest the next MRS command

can be issued is tMRD_CAL is equal to tMOD + tCAL. The two following figures are ex-

amples.

Figure 30: CAL Enabling MRS to Next MRS Command, tMRD_CAL

T0 T1 Ta0 Ta1 Ta2

CK_c

CK_t

Address

CS_n

Settings

Command

Ta3 Ta4

Old settings

MRS MRS

Valid DES

DESDES DES DES

Valid Valid

Valid Valid Valid Valid ValidValid

Don’t CareTime Break

Tb0 Tb1 Tb2 Tb3

Valid Valid Valid

tMRD_CAL

tCAL

Updating settings Updating settings

DES DES DES

Note: 1. Command address latency mode is enabled at T1.

Figure 31: tMRD_CAL, Mode Register Cycle Time With CAL Enabled

7 7 7D 7D 7D

CK_c

CK_t

Address

CS_n

Settings

Command

7E 7E

2OGVHWWLQJV

9DOLG '(6

'(6'(6 '(6

9DOLG 9DOLG

9DOLG 9DOLG 9DOLG 9DOLG 9DOLG9DOLG

'RQ¶W&DUH7LPH%UHDN

7E 7F 7F 7F

1HZVHWWLQJV

9DOLG 9DOLG 9DOLG

W05'B&$/

W&$/ W&$/

8SGDWLQJVHWWLQJV

'(6 '(6 '(6

056 '(6056

Note: 1. MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL set-

ting if modified.

CAL Examples: Consecutive READ BL8 with two different CALs and 1tCK preamble in

different bank group shown in the following figures.

8Gb: x4, x8, x16 DDR4 SDRAM

Command Address Latency

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Figure 32: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

RL = 11

T0 T1 T2 T3 T4 T5 T6 T7 T14T13

tCAL = 3

T15 T16

Don’t CareTransitioning Data

T17 T18 T19 T20 T21 T22

Bank,

Col n

tRPST

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

READ

CK_t

CK_c

Command

CS_n

DQS_t, DQS_c

Address

Bank Group

Address

tCAL = 3

tCCD_S = 4

BG a

Bank,

Col b

BG b

tRPRE (1nCK)

DOUT

n + 4

DOUT

n + 5

DOUT

n + 6

DOUT

n + 7

DOUT

b + 7

DOUT

b + 2

DOUT

b + 3

DOUT

b + 4

DOUT

b + 5

DOUT

b + 6

DOUT

b + 7

Notes: 1. BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK.

2. DOUT n = data-out from column n; DOUT b = data-out from column b.

3. DES commands are shown for ease of illustration, other commands may be valid at these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and

T7.

5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.

6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the

same timing relationship relative to the command/address bus as when CAL is disabled.

Figure 33: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group

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Notes: 1. BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1tCK.

2. DOUT n = data-out from column n; DOUT b = data-out from column b.

3. DES commands are shown for ease of illustration, other commands may be valid at these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and

T8.

8Gb: x4, x8, x16 DDR4 SDRAM

Command Address Latency

CCMTD-1725822587-9875

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5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.

6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the

same timing relationship relative to the command/address bus as when CAL is disabled.

8Gb: x4, x8, x16 DDR4 SDRAM

Command Address Latency

CCMTD-1725822587-9875

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Low-Power Auto Self Refresh Mode

An auto self refresh mode is provided for application ease. Auto self refresh mode is en-

abled by setting MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry

over the supported temperature range of the DRAM. In this mode, the device will

change its self refresh rate as the DRAM operating temperature changes, going lower at

low temperatures and higher at high temperatures.

Manual Self Refresh Mode

If auto self refresh mode is not enabled, the low-power auto self refresh mode register

must be manually programmed to one of the three self refresh operating modes. This

mode provides the flexibility to select a fixed self refresh operating mode at the entry of

the self refresh, according to the system memory temperature conditions. The user is

responsible for maintaining the required memory temperature condition for the mode

selected during the SELF REFRESH operation. The user may change the selected mode

after exiting self refresh and before entering the next self refresh. If the temperature

condition is exceeded for the mode selected, there is a risk to data retention resulting in

loss of data.

Table 27: Auto Self Refresh Mode

MR2[7] MR2[6]

Low-Power

Auto Self Refresh

Mode SELF REFRESH Operation

Operating Temperature

Range for Self Refresh Mode

(DRAM TCASE)

0 0 Normal Variable or fixed normal self refresh rate

maintains data retention at the normal oper-

ating temperature. User is required to ensure

that 85°C DRAM TCASE (MAX) is not exceeded

to avoid any risk of data loss.

-40°C to 85°C

1 0 Extended

temperature

Variable or fixed high self refresh rate opti-

mizes data retention to support the exten-

ded temperature range.

-40°C to 105°C

0 1 Reduced

temperature

Variable or fixed self refresh rate or any oth-

er DRAM power consumption reduction con-

trol for the reduced temperature range. User

is required to ensure 45°C DRAM TCASE

(MAX) is not exceeded to avoid any risk of

data loss.

-40°C to 45°C

1 1 Auto self refresh Auto self refresh mode enabled. Self refresh

power consumption and data retention are

optimized for any given operating tempera-

ture condition.

All of the above

8Gb: x4, x8, x16 DDR4 SDRAM

Low-Power Auto Self Refresh Mode

CCMTD-1725822587-9875

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Figure 34: Auto Self Refresh Ranges

45°C-40°C

IDD6

85°C 105°C

Reduced

temperature

range

Normal

temperature

range

2x refresh rate

1x refresh rate

1/2x refresh rate

Extended

temperature

range

8Gb: x4, x8, x16 DDR4 SDRAM

Low-Power Auto Self Refresh Mode

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Multipurpose Register

The MULTIPURPOSE REGISTER (MPR) function, MPR access mode, is used to write/

read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR

Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through

MPR3. Page 0 can be read by any of three readout modes (serial, parallel, or staggered)

while Pages 1, 2, and 3 can be read by only the serial readout mode. Page 3 is for DRAM

vendor use only. MPR mode enable and page selection is done with MRS commands.

Data bus inversion (DBI) is not allowed during MPR READ operation.

Once the MPR access mode is enabled (MR3[2] = 1), only the following commands are

allowed: MRS, RD, RDA WR, WRA, DES, REF, and RESET; RDA/WRA have the same func-

tionality as RD/WR which means the auto precharge part of RDA/WRA is ignored. Pow-

er-down mode and SELF REFRESH command are not allowed during MPR enable

mode. No other command can be issued within tRFC after a REF command has been

issued; 1x refresh (only) is to be used during MPR access mode. While in MPR access

mode, MPR read or write sequences must be completed prior to a REFRESH command.

Figure 35: MPR Block Diagram

Memory core

(all banks precharged)

MR3 [2] = 1

DQ,s DM_n/DBI_n, DQS_t, DQS_c

Four multipurpose registers (pages),

each with four 8-bit registers:

Data patterns (RD/WR)

Error log (RD)

Mode registers (RD)

DRAM manufacture only (RD)

Table 28: MR3 Setting for the MPR Access Mode

Address Operation Mode Description

A[12:11] MPR data read format 00 = Serial ........... 01 = Parallel

10 = Staggered .... 11 = Reserved

A2 MPR access 0 = Standard operation (MPR not enabled)

1 = MPR data flow enabled

A[1:0] MPR page selection 00 = Page 0 .... 01 = Page 1

10 = Page 2 .... 11 = Page 3

Table 29: DRAM Address to MPR UI Translation

MPR Location [7] [6] [5] [4] [3] [2] [1] [0]

DRAM address – AxA7 A6 A5 A4 A3 A2 A1 A0

MPR UI – UIxUI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

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Table 30: MPR Page and MPRx Definitions

Address MPR Location [7] [6] [5] [4] [3] [2] [1] [0] Note

MPR Page 0 – Read or Write (Data Patterns)

BA[1:0] 00 = MPR0 01010 1 01Read/

Write

(default

value lis-

ted)

01 = MPR1 00110 0 11

10 = MPR2 00001 1 11

11 = MPR3 00000 0 00

MPR Page 1 – Read-only (Error Log)

BA[1:0] 00 = MPR0 A7 A6 A5 A4 A3 A2 A1 A0 Read-on-

01 = MPR1 CAS_n/A

WE_n/A1

A13 A12 A11 A10 A9 A8

10 = MPR2 PAR ACT_n BG1 BG0 BA1 BA0 A17 RAS_n/A

11 = MPR3 CRC er-

ror sta-

tus

CA pari-

ty error

status

CA parity latency: [5] =

MR5[2], [4] = MR5[1], [3] =

MR5[0]

C2 C1 C0

MPR Page 2 – Read-only (MRS Readout)

BA[1:0] 00 = MPR0 hPPR

support

sPPR

support

RTT(WR)

MR2[11]

Temperature sen-

sor status2

CRC write

enable

MR2[12]

RTT(WR) MR2[10:9] Read-on-

01 = MPR1 VREFDQ

traing-

ing

range

MR6[6]

VREFDQ training value: [6:1] = MR6[5:0] Gear-

down

enable

MR3[3]

10 = MPR2 CAS latency: [7:3] = MR0[6:4,2,12] CAS write latency [2:0] =

MR2[5:3]

11 = MPR3 RTT(NOM): [7:5] = MR1[10:8] RTT(Park): [4:2] = MR5[8:6] RON: [1:0] =

MR1[2:1]

MPR Page 3 – Read-only (Restricted, except for MPR3 [3:0])

BA[1:0] 00 = MPR0 DC DC DC DC DC DC DC DC Read-on-

01 = MPR1 DC DC DC DC DC DC DC DC

10 = MPR2 DC DC DC DC DC DC DC DC

11 = MPR3 MBIST-

PPR Sup-

port

DC MBIST-PPR Trans-

parency

MAC MAC MAC MAC

Notes: 1. DC = "Don't Care"

2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh;

MPR[4:3] 11 = Reserved

MPR Reads

MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not sup-

ported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ opera-

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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tion; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode.

READ commands for BC4 are supported with a starting column address of A[2:0] = 000

or 100. After power-up, the content of MPR Page 0 has the default values, which are de-

fined in Table 30. MPR page 0 can be rewritten via an MPR WRITE command. The de-

vice maintains the default values unless it is rewritten by the DRAM controller. If the

DRAM controller does overwrite the default values (Page 0 only), the device will main-

tain the new values unless re-initialized or there is power loss.

Timing in MPR mode:

• Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between READ

commands

• Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S timing between READ

commands; tCCD_L must be used for timing between READ commands

The following steps are required to use the MPR to read out the contents of a mode reg-

ister (MPR Page x, MPRy).

1. The DLL must be locked if enabled.

2. Precharge all; wait until tRP is satisfied.

3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read for-

mat, and MR3[1:0] MPR page.

a. MR3[12:11] MPR read format:

1. 00 = Serial read format

2. 01 = Parallel read format

3. 10 = staggered read format

4. 11 = RFU

b. MR3[1:0] MPR page:

1. 00 = MPR Page 0

2. 01 = MPR Page 1

3. 10 = MPR Page 2

4. 11 = MPR Page 3

4. tMRD and tMOD must be satisfied.

5. Redirect all subsequent READ commands to specific MPRx location.

6. Issue RD or RDA command.

a. BA1 and BA0 indicate MPRx location:

1. 00 = MPR0

2. 01 = MPR1

3. 10 = MPR2

4. 11 = MPR3

b. A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported.

1. If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR

READ commands.

c. A2 = burst-type dependant:

1. BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7

2. BL8: A2 = 1 not allowed

3. BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T

4. BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T

d. A[1:0] = 00, data burst is fixed nibble start at 00.

e. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t

Care."

7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format

determined by MR3[A12,11,1,0].

8. Steps 5 through 7 may be repeated to read additional MPRx locations.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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9. After the last MPRx READ burst, tMPRR must be satisfied prior to exiting.

10. Issue MRS command to exit MPR mode; MR3[2] = 0.

11. After the tMOD sequence is completed, the DRAM is ready for normal operation

from the core (such as ACT).

MPR Readout Format

The MPR read data format can be set to three different settings: serial, parallel, and

staggered.

MPR Readout Serial Format

The serial format is required when enabling the MPR function to read out the contents

of an MRx, temperature sensor status, and the command address parity error frame.

However, data bus calibration locations (four 8-bit registers) can be programmed to

read out any of the three formats. The DRAM is required to drive associated strobes

with the read data similar to normal operation (such as using MRS preamble settings).

Serial format implies that the same pattern is returned on all DQ lanes, as shown the

table below, which uses values programmed into the MPR via [7:0] as 0111 1111.

Table 31: MPR Readout Serial Format

Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

x4 Device

DQ0 01111111

DQ1 01111111

DQ2 01111111

DQ3 01111111

x8 Device

DQ0 01111111

DQ1 01111111

DQ2 01111111

DQ3 01111111

DQ4 01111111

DQ5 01111111

DQ6 01111111

DQ7 01111111

x16 Device

DQ0 01111111

DQ1 01111111

DQ2 01111111

DQ3 01111111

DQ4 01111111

DQ5 01111111

DQ6 01111111

DQ7 01111111

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Table 31: MPR Readout Serial Format (Continued)

Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

DQ8 01111111

DQ9 01111111

DQ10 0 1 1 1 1 1 1 1

DQ11 0 1 1 1 1 1 1 1

DQ12 0 1 1 1 1 1 1 1

DQ13 0 1 1 1 1 1 1 1

DQ14 0 1 1 1 1 1 1 1

DQ15 0 1 1 1 1 1 1 1

MPR Readout Parallel Format

Parallel format implies that the MPR data is returned in the first data UI and then repea-

ted in the remaining UIs of the burst, as shown in the table below. Data pattern location

0 is the only location used for the parallel format. RD/RDA from data pattern locations

1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern

programmed in the data pattern location 0 is 0111 1111. The x4 configuration only out-

puts the first four bits (0111 in this example). For the x16 configuration, the same pat-

tern is repeated on both the upper and lower bytes.

Table 32: MPR Readout – Parallel Format

Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

x4 Device

DQ0 00000000

DQ1 11111111

DQ2 11111111

DQ3 11111111

x8 Device

DQ0 00000000

DQ1 11111111

DQ2 11111111

DQ3 11111111

DQ4 11111111

DQ5 11111111

DQ6 11111111

DQ7 11111111

x16 Device

DQ0 00000000

DQ1 11111111

DQ2 11111111

DQ3 11111111

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Table 32: MPR Readout – Parallel Format (Continued)

Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

DQ4 11111111

DQ5 11111111

DQ6 11111111

DQ7 11111111

DQ8 00000000

DQ9 11111111

DQ10 1 1 1 1 1 1 1 1

DQ11 1 1 1 1 1 1 1 1

DQ12 1 1 1 1 1 1 1 1

DQ13 1 1 1 1 1 1 1 1

DQ14 1 1 1 1 1 1 1 1

DQ15 1 1 1 1 1 1 1 1

MPR Readout Staggered Format

Staggered format of data return is defined as the staggering of the MPR data across the

lanes. In this mode, an RD/RDA command is issued to a specific data pattern location

and then the data is returned on the DQ from each of the different data pattern loca-

tions. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data

from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data

from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA

command to data pattern location 1 will result in data from location 1 being driven on

DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on

DQ2, and so on. Examples of different starting locations are also shown.

Table 33: MPR Readout Staggered Format, x4

x4 READ MPR0 Command x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command

Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0]

DQ0 MPR0 DQ0 MPR1 DQ0 MPR2 DQ0 MPR3

DQ1 MPR1 DQ1 MPR2 DQ1 MPR3 DQ1 MPR0

DQ2 MPR2 DQ2 MPR3 DQ2 MPR0 DQ2 MPR1

DQ3 MPR3 DQ3 MPR0 DQ3 MPR1 DQ3 MPR2

It is expected that the DRAM can respond to back-to-back RD/RDA commands to the

MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be

created on the data bus with no bubbles or clocks between read data. In this case, the

system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2),

RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3).

Table 34: MPR Readout Staggered Format, x4 – Consecutive READs

Stagger UI[7:0] UI[15:8] UI[23:16] UI[31:24] UI[39:32] UI[47:40] UI[55:48] UI[63:56]

DQ0 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Table 34: MPR Readout Staggered Format, x4 – Consecutive READs (Continued)

Stagger UI[7:0] UI[15:8] UI[23:16] UI[31:24] UI[39:32] UI[47:40] UI[55:48] UI[63:56]

DQ1 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0

DQ2 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1

DQ3 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2

For the x8 configuration, the same pattern is repeated on the lower nibble as on the up-

per nibble. READs to other MPR data pattern locations follow the same format as the x4

case. A read example to MPR0 for x8 and x16 configurations is shown below.

Table 35: MPR Readout Staggered Format, x8 and x16

x8 READ MPR0 Command x16 READ MPR0 Command x16 READ MPR0 Command

Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0]

DQ0 MPR0 DQ0 MPR0 DQ8 MPR0

DQ1 MPR1 DQ1 MPR1 DQ9 MPR1

DQ2 MPR2 DQ2 MPR2 DQ10 MPR2

DQ3 MPR3 DQ3 MPR3 DQ11 MPR3

DQ4 MPR0 DQ4 MPR0 DQ12 MPR0

DQ5 MPR1 DQ5 MPR1 DQ13 MPR1

DQ6 MPR2 DQ6 MPR2 DQ14 MPR2

DQ7 MPR3 DQ7 MPR3 DQ15 MPR3

MPR READ Waveforms

The following waveforms show MPR read accesses.

Figure 36: MPR READ Timing

T0 Ta0 Ta1

CK_t

CK_c

DQS_t,

DQS_c

tMOD

tMPRR

Tb0 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Te0 Tf0 Tf1

DES DES DES DES MRS3Valid4DESCommand MRS1

PREA DES READ DES DES

Valid Valid Valid Valid Valid Valid ValidValidValid Valid Add2Valid ValidAddress

CKE

PL5 + AL + CL

tRP tMOD

UI0 UI1 UI2 UI5 UI6 UI7

MPE Enable MPE Disable

Don’t CareTime Break

Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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2. Address setting:

A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)

A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t

Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01

3. Multipurpose registers read/write disable (MR3 A2 = 0).

4. Continue with regular DRAM command.

5. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-

bled.

Figure 37: MPR Back-to-Back READ Timing

T0 T1 T2

DQS_t,

DQS_c

T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10

DES DES DES DES DES DES DES DES DES DES DES DESCommand READDES DES DES DES READ

Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid ValidAdd2

Valid Valid Add2Valid ValidAddress

CKE

PL3 + AL + CL

tCCD_S1

DQS_t,

DQS_c

UI0 UI1 UI2 UI3

UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3

UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

CK_t

CK_c

Don’t Care

Time Break

Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK.

2. Address setting:

A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)

A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is

fixed at 0, 1, 2, 3, T, T, T, T)

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t

Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01

3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-

bled.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Figure 38: MPR READ-to-WRITE Timing

T0 T1 T2

DQS_t,

DQS_c

tMPRR

Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2

DES DES DES DES WRITE DES DESCommand DESREAD DES DES DES DES

Valid Valid Valid Valid Add2Valid ValidValidAdd1Valid Valid Valid ValidAddress

CKE

PL3 + AL + CL

UI2 UI3UI0 UI1 UI4 UI5 UI6 UI7

CK_t

CK_c

Don’t Care

Time Break

Notes: 1. Address setting:

A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)

A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t

Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01

2. Address setting:

BA1 and BA0 indicate the MPR location

A[7:0] = data for MPR

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care"

3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-

bled.

MPR Writes

MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0].

Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will

maintain the new written values unless re-initialized or there is power loss.

The following steps are required to use the MPR to write to mode register MPR Page 0.

1. The DLL must be locked if enabled.

2. Precharge all; wait until tRP is satisfied.

3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR

Page 0); writes to 01, 10, and 11 are not allowed.

4. tMRD and tMOD must be satisfied.

5. Redirect all subsequent WRITE commands to specific MPRx location.

6. Issue WR or WRA command:

a. BA1 and BA0 indicate MPRx location

1. 00 = MPR0

2. 01 = MPR1

3. 10 = MPR2

4. 11 = MPR3

b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0].

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

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c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t

Care."

7. tWR_MPR must be satisfied to complete MPR WRITE.

8. Steps 5 through 7 may be repeated to write additional MPRx locations.

9. After the last MPRx WRITE, tMPRR must be satisfied prior to exiting.

10. Issue MRS command to exit MPR mode; MR3[2] = 0.

11. When the tMOD sequence is completed, the DRAM is ready for normal operation

from the core (such as ACT).

MPR WRITE Waveforms

The following waveforms show MPR write accesses.

Figure 39: MPR WRITE and WRITE-to-READ Timing

T0 Ta0 Ta1

DQS_t,

DQS_c

tRP tMOD tWR_MPR

Tb0 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Td5

READ DES DES DES DES DES DESCommand MRS1

PREA DES WRITE DES DES

Add Valid Valid Valid Add2Valid ValidValidValid Valid Add2Valid ValidAddress

CKE

PL3 + AL + CL

UI2 UI3UI0 UI1 UI4 UI5 UI6 UI7

CK_t

CK_c

MPR Enable

Don’t Care

Time Break

Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1).

2. Address setting:

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care"

3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-

bled.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

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Figure 40: MPR Back-to-Back WRITE Timing

T0 T1 Ta0

DQS_t,

DQS_c

tWR_MPR

Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10

DES DES DES DES DES DES DESCommand DESWRITE DES WRITEDES DES

Add Valid Valid Valid Valid Valid ValidValidAdd1Valid Add1Valid ValidAddress

CKE

CK_t

CK_c

Don’t CareTime Break

Note: 1. Address setting:

BA1 and BA0 indicate the MPR location

A[7:0] = data for MPR

A10 and other address pins are "Don’t Care"

MPR REFRESH Waveforms

The following waveforms show MPR accesses interaction with refreshes.

Figure 41: REFRESH Timing

tMOD

tRP

Tc4Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3

DES DES DES DES Valid Valid ValidCommand MRS1

PREA DES REF2DES DES

Valid Valid Valid Valid Valid Valid ValidValidValid Valid Valid Valid ValidAddress

CK_t

CK_c

tRFC

MPR Enable

Don’t Care

Time Break

Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and

writes to MPR locations.

2. 1x refresh is only allowed when MPR mode is enabled.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Figure 42: READ-to-REFRESH Timing

T0 T1 T2

BL = 8

DQS_t, DQS_c

Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9

DES

DES DES DES REF

DES

DESCommand

DES

READ

DES DES

Valid Valid Valid Valid Valid Valid ValidValidAdd

Valid Valid Valid ValidAddress

CKE

tRFC

UI2 UI3UI0 UI1 UI4 UI5 UI6 UI7

BC = 4

DQS_t, DQS_c

UI2 UI3UI0 UI1

(4 + 1) ClocksPL + AL + CL

CK_t

CK_c

Don’t CareTime Break

Notes: 1. Address setting:

A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)

A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)

BA1 and BA0 indicate the MPR location

A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t

Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01

2. 1x refresh is only allowed when MPR mode is enabled.

Figure 43: WRITE-to-REFRESH Timing

T0 T1 Ta0

DQS_t,

DQS_c

tRFC

Don’t Care

Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10

DES DES DES DES DES DES DESCommand DESWRITE DES DES REF2DES

Valid Valid Valid Valid Valid Valid ValidValidAdd1Valid Valid Valid Valid

Time Break

Address

CKE

CK_t

CK_c

tWR_MPR

Notes: 1. Address setting:

BA1 and BA0 indicate the MPR location

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

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A[7:0] = data for MPR

A10 and other address pins are "Don’t Care"

2. 1x refresh is only allowed when MPR mode is enabled.

8Gb: x4, x8, x16 DDR4 SDRAM

Multipurpose Register

CCMTD-1725822587-9875

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Gear-Down Mode

The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS

command (the MRS command has relaxed setup and hold) followed by a sync pulse

(first CS pulse after MRS setting) to align the proper clock edge for operating the control

lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only sup-

ported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS com-

mand or a sync pulse is required. Gear-down mode may only be entered during initiali-

zation or self refresh exit and may only be exited during self refresh exit. CAL mode and

CA parity mode must be disabled prior to gear-down mode entry. The two modes may

be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The gener-

al sequence for operation in 1/4 rate during initialization is as follows:

1. The device defaults to a 1N mode internal clock at power-up/reset.

2. Assertion of reset.

3. Assertion of CKE enables the DRAM.

4. MRS is accessed with a low-frequency N × tCK gear-down MRS command. (NtCK

static MRS command is qualified by 1N CS_n. )

5. The memory controller will send a 1N sync pulse with a low-frequency N × tCK

NOP command. tSYNC_GEAR is an even number of clocks. The sync pulse is on an

even edge clock boundary from the MRS command.

6. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N

mode after tCMD_GEAR from 1N sync pulse.

The device resets to 1N gear-down mode after entering self refresh. The general se-

quence for operation in gear-down after self refresh exit is as follows:

1. MRS is set to 1, via MR3[3], with a low-frequency N × tCK gear-down MRS com-

mand.

a. The NtCK static MRS command is qualified by 1N CS_n, which meets tXS or

tXS_ABORT.

b. Only a REFRESH command may be issued to the DRAM before the NtCK stat-

ic MRS command.

2. The DRAM controller sends a 1N sync pulse with a low-frequency N × tCK NOP

command.

a. tSYNC_GEAR is an even number of clocks.

b. The sync pulse is on even edge clock boundary from the MRS command.

3. A valid command not requiring locked DLL is available in 2N mode after

tCMD_GEAR from the 1N sync pulse.

a. A valid command requiring locked DLL is available in 2N mode after tXSDLL

or tDLLK from the 1N sync pulse.

4. If operation is in 1N mode after self refresh exit, N × tCK MRS command or sync

pulse is not required during self refresh exit. The minimum exit delay to the first

valid command is tXS, or tXS_ABORT.

The DRAM may be changed from 2N to 1N by entering self refresh mode, which will re-

set to 1N mode. Changing from 2N to by any other means can result in loss of data and

make operation of the DRAM uncertain.

When operating in 2N gear-down mode, the following MR settings apply:

• CAS latency (MR0[6:4,2]): Even number of clocks

• Write recovery and read to precharge (MR0[11:9]): Even number of clocks

• Additive latency (MR1[4:3]): CL - 2

• CAS WRITE latency (MR2 A[5:3]): Even number of clocks

8Gb: x4, x8, x16 DDR4 SDRAM

Gear-Down Mode

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• CS to command/address latency mode (MR4[8:6]): Even number of clocks

• CA parity latency mode (MR5[2:0]): Even number of clocks

Figure 44: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)

tXPR_GEAR tCMD_GEAR

tSYNC_GEAR

CK_c

CK_t

Configure DRAM

to 1/4 rate

tCKSRX

1N sync pulse 2N mode

DRAM

internal CLK

RESET_n

CKE

CS_n

Command MRS NOP Valid

tGEAR_setup tGEAR_hold tGEAR_setup tGEAR_hold

Don’t CareTime Break

TdkN12

TdkN + Neven

Notes: 1. After tSYNC_GEAR from GEAR-DOWN command, internal clock rate is changed at TdkN.

2. After tSYNC_GEAR + tCMD_GEAR from GEAR-DOWN command, both internal clock rate

and command cycle are changed at TdkN + Neven.

Figure 45: Clock Mode Change After Exiting Self Refresh

CK_c

CK_t

Don’t CareTime Break

TdkN + Neven

Configure DRAM

to 1/4 rate

1N sync pulse 2N mode

DRAM

internal CLK

CKE

CS_n

Command



MRS NOP Valid

tXPR_GEAR tCMD_GEAR

tSYNC_GEAR

tGEAR_setup tGEAR_hold tGEAR_setup tGEAR_hold

TdkN1

Notes: 1. After tSYNC_GEAR from GEAR-DOWN command, internal clock rate is changed at TdkN.

2. After tSYNC_GEAR + tCMD_GEAR from GEAR-DOWN command, both internal clock rate

and command cycle are changed at TdkN + Neven.

8Gb: x4, x8, x16 DDR4 SDRAM

Gear-Down Mode

CCMTD-1725822587-9875

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Figure 46: Comparison Between Gear-Down Disable and Gear-Down Enable

tRCD = 16

T33T1 T2 T3 T15 T16 T17 T18 T19 T30 T31 T32

DES DES DES DES DES DES DES

Command DESACT DES DES DES READ

CK_t

CK_c

RL =CL= 16 (AL = 0)

T38T34 T35 T36 T37

AL = 0 (geardown = disable)

Don’t Care

Transitioning DataTime Break

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

n + 2

n + 1

DES DES DES DES DES

DES DES DES DES DES DES DESCommand READACT DES DES DES DES

READ

RL = AL + CL = 31 (AL = CL - 1 = 15)

AL = CL - 1 (geardown = disable)

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

n + 2

n + 1

DES DES DES DES DES

DES DES DESCommand ACT READ DES

READ

AL + CL = RL = 30 (AL = CL - 2 = 14)

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

n + 2

n + 1

DES DES DES

8Gb: x4, x8, x16 DDR4 SDRAM

Gear-Down Mode

CCMTD-1725822587-9875

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Maximum Power-Saving Mode

Maximum power-saving mode provides the lowest power mode where data retention is

not required. When the device is in the maximum power-saving mode, it does not

maintain data retention or respond to any external command, except the MAXIMUM

POWER SAVING MODE EXIT command and during the assertion of RESET_n signal

LOW. This mode is more like a “hibernate mode” than a typical power-saving mode.

The intent is to be able to park the DRAM at a very low-power state; the device can be

switched to an active state via the per-DRAM addressability (PDA) mode.

Maximum Power-Saving Mode Entry

Maximum power-saving mode is entered through an MRS command. For devices with

shared control/address signals, a single DRAM device can be entered into the maxi-

mum power-saving mode using the per-DRAM addressability MRS command. Large

CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result,

CA parity, CAL, and gear-down modes must be disabled prior to the maximum power-

saving mode entry MRS command.

The MRS command may use both address and DQ information, as defined in the Per-

DRAM Addressability section. As illustrated in the figure below, after tMPED from the

mode entry MRS command, the DRAM is not responsive to any input signals except

CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may be-

come High-Z). The system will provide a valid clock until tCKMPE expires, at which time

clock inputs (CK) should be disabled (external clock signals may become High-Z).

Figure 47: Maximum Power-Saving Mode Entry

Ta0 Ta1 Ta2 Tb0 Tb1

Command MRSDES DES DESDES

CK_t

CK_c

RESET_n

Tc11Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc7Tc5 Tc6 Tc8 Tc9 Tc10

Don’t Care

Time Break

CS_n

CKE

tMPED

CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode

MR4[A1=1]

MPSM Enable)

Address Valid

tCKMPE

8Gb: x4, x8, x16 DDR4 SDRAM

Maximum Power-Saving Mode

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Maximum Power-Saving Mode Entry in PDA

The sequence and timing required for the maximum power-saving mode with the per-

DRAM addressability enabled is illustrated in the figure below.

Figure 48: Maximum Power-Saving Mode Entry with PDA

Ta0 Ta1 Ta2 Tb0 Tb1

Command MRSDES DES DESDES DES DES DES DES DES DES DES DESDES

CK_t

CK_c

DQS_t

DQS_c

DQ0

Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tc1Tb9 Tc0 Tc2 Td0 Td1 Td2

Don’t Care

Time Break

CS_n

CKE

RESET_n

MR4[A1 = 1]

MPSM Enable)

AL + CWL tMPED

tPDA_H

tPDA_S

tCKMPE

CKE Transition During Maximum Power-Saving Mode

The following figure shows how to maintain maximum power-saving mode even though

the CKE input may toggle. To prevent the device from exiting the mode, CS_n should be

HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold

(tMPX_H) timings.

Figure 49: Maintaining Maximum Power-Saving Mode with CKE Transition

CMD

CS_n

CKE

RESET_n

Don’t Care

CLK

tMPX_HH

tMPX_S

Maximum Power-Saving Mode Exit

To exit the maximum power-saving mode, CS_n should be LOW at the CKE LOW-to-

HIGH transition, with appropriate setup (tMPX_S) and hold (tMPX_LH) timings, as

8Gb: x4, x8, x16 DDR4 SDRAM

Maximum Power-Saving Mode

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shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during

this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n sig-

nal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit

and begins the exit procedure from this mode. The external clock must be restarted and

be stable by tCKMPX before the device can exit the maximum power-saving mode. Dur-

ing the exit time (tXMP), only NOP and DES commands are allowed: NOP during

tMPX_LH and DES the remainder of tXMP. After tXMP expires, valid commands not re-

quiring a locked DLL are allowed; after tXMP_DLL expires, valid commands requiring a

locked DLL are allowed.

Figure 50: Maximum Power-Saving Mode Exit

Ta0

tCKMPX

tMPX_S

tXMP

tXMP_DLL

Ta1 Ta2 Ta3 Tb0

NOP NOP NOP NOP NOP DES DESCommand

CK_t

CK_c

RESET_n

Te1Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Td1Tc4 Td0 Td2 Td3 Te0

Don’t Care

Time Break

DES DES Valid DES DES

CS_n

CKE

tMPX_LH

8Gb: x4, x8, x16 DDR4 SDRAM

Maximum Power-Saving Mode

CCMTD-1725822587-9875

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Command/Address Parity

Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity

bit for the generated address and commands signals and matches it to the internally

generated parity from the captured address and commands signals. CA parity is suppor-

ted in the DLL enabled state only; if the DLL is disabled, CA parity is not supported.

Figure 51: Command/Address Parity Operation

CMD/ADDR

DRAM Controller DRAM

CMD/ADDR

Even parity bit

Even parity

GEN

Even parity

GEN

CMD/ADDR

Compare

parity

bit

CA parity is disabled or enabled via an MRS command. If CA parity is enabled by pro-

gramming a non-zero value to CA parity latency in the MR, the DRAM will ensure that

there is no parity error before executing commands. There is an additional delay re-

quired for executing the commands versus when parity is disabled. The delay is pro-

grammed in the MR when CA parity is enabled (parity latency) and applied to all com-

mands which are registered by CS_n (rising edge of CK_t and falling CS_n). The com-

mand is held for the time of the parity latency (PL) before it is executed inside the de-

vice. The command captured by the input clock has an internal delay before executing

and is determined with PL. ALERT_n will go active when the DRAM detects a CA parity

error.

CA parity covers ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, the address bus including

bank address and bank group bits, and C[2:0] on 3DS devices; the control signals CKE,

ODT, and CS_n are not covered. For example, for a 4Gb x4 monolithic device, parity is

computed across BG[1:0], BA[1:0], A16/RAS_n, A15/CAS_n, A14/ WE_n, A[13:0], and

ACT_n. The DRAM treats any unused address pins internally as zeros; for example, if a

common die has stacked pins but the device is used in a monolithic application, then

the address pins used for stacking and not connected are treated internally as zeros.

The convention for parity is even parity; for example, valid parity is defined as an even

number of ones across the inputs used for parity computation combined with the pari-

ty signal. In other words, the parity bit is chosen so that the total number of ones in the

transmitted signal, including the parity bit, is even.

If a DRAM device detects a CA parity error in any command qualified by CS_n, it will

perform the following steps:

1. Ignore the erroneous command. Commands in the MAX NnCK window

(tPAR_UNKNOWN) prior to the erroneous command are not guaranteed to be exe-

cuted. When a READ command in this NnCK window is not executed, the device

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

CCMTD-1725822587-9875

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does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs

during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at

MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled

and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset.

2. Log the error by storing the erroneous command and address bits in the MPR er-

ror log.

3. Set the parity error status bit in the mode register to 1. The parity error status bit

must be set before the ALERT_n signal is released by the DRAM (that is,

tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)).

4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within

tPAR_ALERT_ON time.

5. Wait for all in-progress commands to complete. These commands were received

tPAR_UNKOWN before the erroneous command.

6. Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing

any commands during the window defined by (tPAR_ALERT_ON +

tPAR_ALERT_PW).

7. After tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert

ALERT_n.

a. When the device is returned to a known precharged state, ALERT_n is al-

lowed to be de-asserted.

8. After (tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for nor-

mal operation. Parity latency will be in effect; however, parity checking will not re-

sume until the memory controller has cleared the parity error status bit by writing

a zero. The DRAM will execute any erroneous commands until the bit is cleared;

unless persistent mode is enabled.

• It is possible that the device might have ignored a REFRESH command during

tPAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is rec-

ommended that extra REFRESH cycles be issued, as needed.

• The parity error status bit may be read anytime after tPAR_ALERT_ON +

tPAR_ALERT_PW to determine which DRAM had the error. The device maintains the

error log for the first erroneous command until the parity error status bit is reset to a

zero or a second CA parity occurs prior to resetting.

The mode register for the CA parity error is defined as follows: CA parity latency bits are

write only, the parity error status bit is read/write, and error logs are read-only bits. The

DRAM controller can only program the parity error status bit to zero. If the DRAM con-

troller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be

certain that parity will be checked; the DRAM may opt to block the DRAM controller

from writing a 1 to the parity error status bit.

The device supports persistent parity error mode. This mode is enabled by setting

MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asser-

ted, even if the parity error status bit remains a 1. If multiple errors occur before the er-

ror status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In

persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the

DRAM as defined with the MIN and MAX value tPAR_ALERT_PW. The DRAM controller

must issue DESELECT commands once it detects the ALERT_n signal, this response

time is defined as tPAR_ALERT_RSP. The following figures capture the flow of events on

the CA bus and the ALERT_n signal.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

CCMTD-1725822587-9875

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Table 36: Mode Register Setting for CA Parity

CA Parity Latency

MR5[2:0]1Applicable Speed Bin Parity Error Status Parity Persistent Mode

Erroneous CA

Frame

000 = Disabled N/A

MR5 [4] 0 = Clear

MR5 [4] 1 = Error

MR5 [9] 0 = DisabledMR5

[9] 1 = Enabled

C[2:0], ACT_n, BG1,

BG0, BA[1:0], PAR,

A17, A16/RAS_n, A15/

CAS_n, A14/WE_n,

A[13:0]

001 = 4 clocks 1600, 1866, 2133

010 = 5 clocks 2400, 2666

011 = 6 clocks 2933, 3200

100 = 8 clocks RFU

101 = Reserved RFU

110 = Reserved RFU

111 = Reserved RFU

Notes: 1. Parity latency is applied to all commands.

2. Parity latency can be changed only from a CA parity disabled state; for example, a direct

change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to

PL = 4.

3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL.

READ latency = AL + CL + PL.

Figure 52: Command/Address Parity During Normal Operation

Don’t Care Time Break

Command execution unknown

Command not executed

Command executed

DES2

Valid3

ValidError

CK_t

CK_c

Command/

Address Valid2Valid2Valid2Valid3Valid3

T0 T1 Ta0 Ta1 Tb0 Tc0

ALERT_n

Tc1

tPAR_ALERT_ON

Td0

Valid Valid Valid

Error

tPAR_UNKNOWN2

Ta2 Te1

tPAR_ALERT_PW1

Te0

DES2DES2

Valid2

tRP

t > 2nCK

Notes: 1. DRAM is emptying queues. Precharge all and parity checking are off until parity error

status bit is cleared.

2. Command execution is unknown; the corresponding DRAM internal state change may

or may not occur. The DRAM controller should consider both cases and make sure that

the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE

CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located

at MR5[3] may or may not get set.

3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity

checking is off until parity error status bit is cleared.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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Figure 53: Persistent CA Parity Error Checking Operation

Don’t Care Time Break

Command execution unknown

Command not executed

Command executed

DES

Valid3

ValidError

CK_t

CK_c

Command/

Address Valid2Valid2Valid2Valid3

T0 T1 Ta0 Ta1 Tb0 Tc0

ALERT_n

Tc1

tPAR_ALERT_ON

Td0

Valid Valid Valid

Error

tPAR_UNKNOWN2

Ta2 Te1

tPAR_ALERT_PW1

tPAR_ALERT_RSP

Te0

DES DES DES

Valid2

tRP

t > 2nCK

Notes: 1. DRAM is emptying queues. Precharge all and parity check re-enable finished by

tPAR_ALERT_PW.

2. Command execution is unknown; the corresponding DRAM internal state change may

or may not occur. The DRAM controller should consider both cases and make sure that

the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE

CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located

at MR5[3] may or may not get set

3. Normal operation with parity latency and parity checking (CA parity persistent error

mode enabled).

Figure 54: CA Parity Error Checking – SRE Attempt

Don’t Care Time Break

Command not executed

Command executed

DES6Command execution unknown

DES5

Valid3

DES1

Error2

CK_t

CK_c

Command/

Address DES1, 5 Valid3

T0 T1 Ta0 Ta1 Tb1 Tc0

ALERT_n

Tc1

tPAR_ALERT_ON

Td0

DES1

Note 4

Error2

Tb0 Td2

tPAR_ALERT_PW1

Td1

DES6DES6DES5

DES1, 5

t > 2nCK

tIH

tIS

tXP + PL

tCPDED + PL

Td3 Te0 Te1

CKE

tIS

tRP

Notes: 1. Only DESELECT command is allowed.

2. SELF REFRESH command error. The DRAM masks the intended SRE command and enters

precharge power-down.

3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity

checking is off until the parity error status bit cleared.

4. The controller cannot disable the clock until it has been capable of detecting a possible

CA parity error.

5. Command execution is unknown; the corresponding DRAM internal state change may

or may not occur. The DRAM controller should consider both cases and make sure that

the command sequence meets the specifications.

6. Only a DESELECT command is allowed; CKE may go HIGH prior to Tc2 as long as DES

commands are issued.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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Figure 55: CA Parity Error Checking – SRX Attempt

Don’t Care

Time Break

Command execution unknown

Command not executed

Command executed

DES Valid3, 5

Valid4,5,6,7

ValidError

CK_t

CK_c

Command/

Address SRX1DES DES Valid2, 4, 5 Valid2, 4, 7

Valid2, 4, 6

T0 Ta0 Tb0Ta1 Tc0 Tc1

ALERT_n

Tc2

tPAR_ALERT_ON

Td0

Valid2Valid2Valid2

Error2

tPAR_UNKNOWN

tXS_FAST8

tXS

tXSDLL

Tb1 Te0

tPAR_ALERT_PW

Td1

DES2, 3 DES2, 3

SRX1

t > 2nCK

Tf0

CKE

tIS

tRP

Notes: 1. Self refresh abort = disable: MR4 [9] = 0.

2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT, and tXS_FAST timing.

3. Command execution is unknown; the corresponding DRAM internal state change may

or may not occur. The DRAM controller should consider both cases and make sure that

the command sequence meets the specifications.

4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity

checking off until parity error status bit cleared.

5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS,

or ZQCL command is allowed.

6. Valid commands not requiring a locked DLL.

7. Valid commands requiring a locked DLL.

8. This figure shows the case from which the error occurred after tXS_FAST. An error may

also occur after tXS_ABORT and tXS.

Figure 56: CA Parity Error Checking – PDE/PDX

Don’t Care Time Break

Command not executed

Command executed

DES5Command execution unknown

Valid3

DES1

Error2

CK_t

CK_c

Command/

Address Valid3

T0 T1 Ta0 Ta1 Tb1 Tc0

ALERT_n

Tc1

tPAR_ALERT_ON

Td0

DES1

Error2

Tb0 Td2

tPAR_ALERT_PW1

Td1

DES5DES5DES4

DES4

t > 2nCK

tIH

tIS

tXP + PL

tCPDED + PL

Td3 Te0 Te1

CKE

tIS

tRP

Notes: 1. Only DESELECT command is allowed.

2. Error could be precharge or activate.

3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity

checking is off until parity error status bit cleared.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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4. Command execution is unknown; the corresponding DRAM internal state change may

or may not occur. The DRAM controller should consider both cases and make sure that

the command sequence meets the specifications.

5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES

commands are issued.

Figure 57: Parity Entry Timing Example – tMRD_PAR

Ta0

tMRD_PAR

Ta1 Ta2 Tb0 Tb1 Tb2

Command MRSDES DES DES MRS DES

PL = 0 Updating setting PL = NParity latency

CK_t

CK_c

Enable

parity

Don’t Care

Time Break

Note: 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.

Figure 58: Parity Entry Timing Example – tMOD_PAR

Ta0

tMOD_PAR

Ta1 Ta2 Tb0 Tb1 Tb2

Command MRSDES DES DES Valid DES

Parity latency

CK_t

CK_c

Enable

parity

Don’t Care

Time Break

PL = 0 Updating setting PL = N

Note: 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.

Figure 59: Parity Exit Timing Example – tMRD_PAR

Ta0

tMRD_PAR

Ta1 Ta2 Tb0 Tb1 Tb2

Command MRSDES DES DES MRS DES

Parity latency

CK_t

CK_c

Disable

parity

Don’t Care

Time Break

PL = N Updating setting

Note: 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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Figure 60: Parity Exit Timing Example – tMOD_PAR

Ta0

tMOD_PAR

Ta1 Ta2 Tb0 Tb1 Tb2

Command MRSDES DES DES Valid DES

Parity latency

CK_t

CK_c

Disable

parity

Don’t Care

Time Break

PL = N Updating setting

Note: 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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Figure 61: CA Parity Flow Diagram

latched in

Yes

process start MR5[2:0] set parity latency (PL)

MR5[4] set parity error status to 0

MR5[9] enable/disable persistent mode

Yes

CA parity

enabled

CA error

Persistent

mode

enabled

Good CA

processed

Good CA

processed

Good CA

processed

Ignore

bad CMD

Ignore

bad CMD

Log error/

set parity status

Internal

precharge all

ALERT_n HIGH

Command

execution

unknown

Command

execution

unknown

Normal operation ready

MR5[4] reset to 0 if desired

Normal operation ready

MR5[4] reset to 0 if desired

Yes

CA parity

error

ALERT_n LOW

44 to 144 CKs

ALERT_n LOW

44 to 144 CKs

Internal

precharge all

ALERT_n HIGH

Command

execution

unknown

Command

execution

unknown

Yes Log error/

set parity status

MR5[4] = 0

@ ADDR/CMD

latched

MR5[4] = 0

@ ADDR/CMD

latched

CA parity

error

Normal

operation ready

Bad CA

processed

Operation ready?

8Gb: x4, x8, x16 DDR4 SDRAM

Command/Address Parity

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Per-DRAM Addressability

DDR4 allows programmability of a single, specific DRAM on a rank. As an example, this

feature can be used to program different ODT or VREF values on each DRAM on a given

rank. Because per-DRAM addressability (PDA) mode may be used to program optimal

VREF for the DRAM, the data set up for first DQ0 transfer or the hold time for the last

DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the first fall-

ing or second rising DQS transfer edge. This supports a common implementation be-

tween BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0

to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8

cases. Note, both fixed and on-the-fly (OTF) modes are supported for BC4 and BL8 dur-

ing PDA mode.

1. Before entering PDA mode, write leveling is required.

• BL8 or BC4 may be used.

2. Before entering PDA mode, the following MR settings are possible:

•R

TT(Park) MR5 A[8:6] = Enable

•R

TT(NOM) MR1 A[10:8] = Enable

3. Enable PDA mode using MR3 [4] = 1. (The default programed value of MR3[4] = 0.)

4. In PDA mode, all MRS commands are qualified with DQ0. The device captures

DQ0 by using DQS signals. If the value on DQ0 is LOW, the DRAM executes the

MRS command. If the value on DQ0 is HIGH, the DRAM ignores the MRS com-

mand. The controller can choose to drive all the DQ bits.

5. Program the desired DRAM and mode registers using the MRS command and

DQ0.

6. In PDA mode, only MRS commands are allowed.

7. The MODE REGISTER SET command cycle time in PDA mode, AL + CWL + BL/2 -

0.5tCK + tMRD_PDA + PL, is required to complete the WRITE operation to the

mode register and is the minimum time required between two MRS commands.

8. Remove the device from PDA mode by setting MR3[4] = 0. (This command re-

quires DQ0 = 0.)

Note: Removing the device from PDA mode will require programming the entire MR3

when the MRS command is issued. This may impact some PDA values programmed

within a rank as the EXIT command is sent to the rank. To avoid such a case, the PDA

enable/disable control bit is located in a mode register that does not have any PDA

mode controls.

In PDA mode, the device captures DQ0 using DQS signals the same as in a normal

WRITE operation; however, dynamic ODT is not supported. Extra care is required for

the ODT setting. If RTT(NOM) MR1 [10:8] = enable, device data termination needs to be

controlled by the ODT pin, and applies the same timing parameters (defined below).

Symbol Parameter

DODTLon Direct ODT turnon latency

DODTLoff Direct ODT turn off latency

tADC RTT change timing skew

tAONAS Asynchronous RTT(NOM) turn-on delay

tAOFAS Asynchronous RTT(NOM) turn-off delay

8Gb: x4, x8, x16 DDR4 SDRAM

Per-DRAM Addressability

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Figure 62: PDA Operation Enabled, BL8

&.BW

&.BF

'4

2'7

W3'$B6

W02' &:/$/3/ W05'B3'$

'46BW

'46BF

05$ 

3'$HQDEOH 056 056 056

'2'7/RII :/

'2'7/RQ :/

W3'$B+

773DUN

77 5

77120

Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

Figure 63: PDA Operation Enabled, BC4

CK_t

CK_c

DQ0

ODT

tPDA_S

tMOD CWL+AL+PL tMRD_PDA

DQS_t

DQS_c

MR3 A4 = 1

(PDA enable) MRS MRS MRS

DODTLoff = WL-3

DODTLon = WL-3

tPDA_H

RTT(Park)

RTT RTT(NOM)

Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

8Gb: x4, x8, x16 DDR4 SDRAM

Per-DRAM Addressability

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Figure 64: MRS PDA Exit

&.BW

&.BF

'4

2'7

W3'$B6

&:/$/3/ W02'B3'$

'46BW

'46BF

05$ 

3'$GLVDEOH 056 9DOLG

'2'7/RII :/

'2'7/RQ :/

W3'$B+

773DUN 5

77120 5

773DUN

Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

8Gb: x4, x8, x16 DDR4 SDRAM

Per-DRAM Addressability

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VREFDQ Calibration

The VREFDQ level, which is used by the DRAM DQ input receivers, is internally gener-

ated. The DRAM VREFDQ does not have a default value upon power-up and must be set

to the desired value, usually via VREFDQ calibration mode. If PDA or PPR modes (hPPR or

sPPR) are used prior to VREFDQ calibration, VREFDQ should initially be set at the midpoint

between the VDD,max, and the LOW as determined by the driver and ODT termination

selected with wide voltage swing on the input levels and setup and hold times of ap-

proximately 0.75UI. The memory controller is responsible for VREFDQ calibration to de-

termine the best internal VREFDQ level. The VREFDQ calibration is enabled/disabled via

MR6[7], MR6[6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of

VDDQ), and an MRS protocol using MR6[5:0] to adjust the VREFDQ level up and down.

MR6[6:0] bits can be altered using the MRS command if MR6[7] is enabled. The DRAM

controller will likely use a series of writes and reads in conjunction with VREFDQ adjust-

ments to obtain the best VREFDQ, which in turn optimizes the data eye.

The internal VREFDQ specification parameters are voltage range, step size, VREF step

time, VREF full step time, and VREF valid level. The voltage operating range specifies the

minimum required VREF setting range for DDR4 SDRAM devices. The minimum range is

defined by VREFDQ,min and VREFDQ,max. As noted, a calibration sequence, determined by

the DRAM controller, should be performed to adjust VREFDQ and optimize the timing

and voltage margin of the DRAM data input receivers. The internal VREFDQ voltage value

may not be exactly within the voltage range setting coupled with the VREF set tolerance;

the device must be calibrated to the correct internal VREFDQ voltage.

Figure 65: VREFDQ Voltage Range

VDDQ

VREF

range

VSWING small

VSWING large

System variance

Total range

VREF,max

VREF,min

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

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VREFDQ Range and Levels

Table 37: VREFDQ Range and Levels

MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1 MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1

00 0000 60.00% 45.00% 01 1010 76.90% 61.90%

00 0001 60.65% 45.65% 01 1011 77.55% 62.55%

00 0010 61.30% 46.30% 01 1100 78.20% 63.20%

00 0011 61.95% 46.95% 01 1101 78.85% 63.85%

00 0100 62.60% 47.60% 01 1110 79.50% 64.50%

00 0101 63.25% 48.25% 01 1111 80.15% 65.15%

00 0110 63.90% 48.90% 10 0000 80.80% 65.80%

00 0111 64.55% 49.55% 10 0001 81.45% 66.45%

00 1000 65.20% 50.20% 10 0010 82.10% 67.10%

00 1001 65.85% 50.85% 10 0011 82.75% 67.75%

00 1010 66.50% 51.50% 10 0100 83.40% 68.40%

00 1011 67.15% 52.15% 10 0101 84.05% 69.05%

00 1100 67.80% 52.80% 10 0110 84.70% 69.70%

00 1101 68.45% 53.45% 10 0111 85.35% 70.35%

00 1110 69.10% 54.10% 10 1000 86.00% 71.00%

00 1111 69.75% 54.75% 10 1001 86.65% 71.65%

01 0000 70.40% 55.40% 10 1010 87.30% 72.30%

01 0001 71.05% 56.05% 10 1011 87.95% 72.95%

01 0010 71.70% 56.70% 10 1100 88.60% 73.60%

01 0011 72.35% 57.35% 10 1101 89.25% 74.25%

01 0100 73.00% 58.00% 10 1110 89.90% 74.90%

01 0101 73.65% 58.65% 10 1111 90.55% 75.55%

01 0110 74.30% 59.30% 11 0000 91.20% 76.20%

01 0111 74.95% 59.95% 11 0001 91.85% 76.85%

01 1000 75.60% 60.60% 11 0010 92.50% 77.50%

01 1001 76.25% 61.25% 11 0011 to 11 1111 = Reserved

VREFDQ Step Size

The VREF step size is defined as the step size between adjacent steps. VREF step size rang-

es from 0.5% VDDQ to 0.8% VDDQ. However, for a given design, the device has one value

for VREF step size that falls within the range.

The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This ac-

counts for accumulated error over multiple steps. There are two ranges for VREF set tol-

erance uncertainty. The range of VREF set tolerance uncertainty is a function of number

of steps n.

The VREF set tolerance is measured with respect to the ideal line, which is based on the

MIN and MAX VREF value endpoints for a specified range. The internal VREFDQ voltage

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

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value may not be exactly within the voltage range setting coupled with the VREF set tol-

erance; the device must be calibrated to the correct internal VREFDQ voltage.

Figure 66: Example of VREF Set Tolerance and Step Size

VREF

step size

VREF set

tolerance

VREF set

tolerance

Straight line

(endpoint fit)

Actual VREF

output

Digital Code

Note: 1. Maximum case shown.

VREFDQ Increment and Decrement Timing

The VREF increment/decrement step times are defined by VREF,time. VREF,time is defined

from t0 to t1, where t1 is referenced to the VREF voltage at the final DC level within the

VREF valid tolerance (VREF,val_tol). The VREF valid level is defined by VREF,val tolerance to

qualify the step time t1. This parameter is used to insure an adequate RC time constant

behavior of the voltage level change after any VREF increment/decrement adjustment.

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

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Figure 67: VREFDQ Timing Diagram for VREF,time Parameter

MRS

VREF setting

adjustment

Command

DQ VREF

VREF_time

t0 t1

Old VREF setting New VREF settingUpdating VREF setting

Don’t Care

CK_t

CK_c

Note: 1. t0 is referenced to the MRS command clock

t1 is referenced to VREF,tol

VREFDQ calibration mode is entered via an MRS command, setting MR6[7] to 1 (0 disa-

bles VREFDQ calibration mode) and setting MR6[6] to either 0 or 1 to select the desired

range (MR6[5:0] are "Don't Care"). After VREFDQ calibration mode has been entered,

VREFDQ calibration mode legal commands may be issued once tVREFDQE has been sat-

isfied. Legal commands for VREFDQ calibration mode are ACT, WR, WRA, RD, RDA, PRE,

DES, and MRS to set VREFDQ values, and MRS to exit VREFDQ calibration mode. Also, after

VREFDQ calibration mode has been entered, “dummy” WRITE commands are allowed

prior to adjusting the VREFDQ value the first time VREFDQ calibration is performed after

initialization.

Setting VREFDQ values requires MR6[7] be set to 1 and MR6[6] be unchanged from the

initial range selection; MR6[5:0] may be set to the desired VREFDQ values. If MR6[7] is set

to 0, MR6[6:0] are not written. VREF,time-short or VREF,time-long must be satisfied after each

MR6 command to set VREFDQ value before the internal VREFDQ value is valid.

If PDA mode is used in conjunction with VREFDQ calibration, the PDA mode require-

ment that only MRS commands are allowed while PDA mode is enabled is not waived.

That is, the only VREFDQ calibration mode legal commands noted above that may be

used are the MRS commands: MRS to set VREFDQ values and MRS to exit VREFDQ calibra-

tion mode.

The last MR6[6:0] setting written to MR6 prior to exiting VREFDQ calibration mode is the

range and value used for the internal VREFDQ setting. VREFDQ calibration mode may be

exited when the DRAM is in idle state. After the MRS command to exit VREFDQ calibra-

tion mode has been issued, DES must be issued until tVREFDQX has been satisfied

where any legal command may then be issued. VREFDQ setting should be updated if the

die temperature changes too much from the calibration temperature.

The following are typical script when applying the above rules for VREFDQ calibration

routine when performing VREFDQ calibration in Range 1:

• MR6[7:6]10 [5:0]XXXXXXX.

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

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– Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD,

RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).

• All subsequent VREFDQ calibration MR setting commands are MR6[7:6]10

[5:0]VVVVVV.

– "VVVVVV" are desired settings for VREFDQ.

• Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed.

• To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are:

– MR6[7:6]10 [5:0]VVVVVV* where VVVVVV* = desired value for VREFDQ.

– MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode.

The following are typical script when applying the above rules for VREFDQ calibration

routine when performing VREFDQ calibration in Range 2:

• MR6[7:6]11 [5:0]XXXXXXX.

– Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD,

RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).

• All subsequent VREFDQ calibration MR setting commands are MR6[7:6]11

[5:0]VVVVVV.

– "VVVVVV" are desired settings for VREFDQ.

• Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed.

• To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are:

– MR6[7:6]11 [5:0]VVVVVV* where VVVVVV* = desired value for VREFDQ.

– MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode.

Note: Range may only be set or changed when entering VREFDQ calibration mode;

changing range while in or exiting VREFDQ calibration mode is illegal.

Figure 68: VREFDQ Training Mode Entry and Exit Timing Diagram

T0 T1 Ta0 Ta1 Tb0

CK_c

CK_t

Command

Tb1 Tc0

MRS WRDESCMDDESDES CMD DES

Tc1 Td0 Td1 Td2

tVREFDQE

VREFDQ training on

tVREFDQX

DES MRS1,2 DES

New VREFDQ

value or write

New VREFDQ

value or write

VREFDQ training off

Don’t Care

Notes: 1. New VREFDQ values are not allowed with an MRS command during calibration mode en-

try.

2. Depending on the step size of the latest programmed VREF value, VREF must be satisfied

before disabling VREFDQ training mode.

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

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Figure 69: VREF Step: Single Step Size Increment Case

VREF

Voltage

Time

VREF,val_tol

VREF

(VDDQ(DC))

Step size

Figure 70: VREF Step: Single Step Size Decrement Case

VREF

Voltage

Time

VREF,val_tol

VREF

(VDDQ(DC))

Step size

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 71: VREF Full Step: From VREF,min to VREF,maxCase

VREF

Voltage

Time

VREF,val_tol

VREF,max

VREF,min

VREF

(VDDQ(DC))

Full range

step

Figure 72: VREF Full Step: From VREF,max to VREF,minCase

VREF

Voltage

Time

VREF,val_tol

VREF,max

VREF,min

VREF

(VDDQ(DC))

Full range

step

VREFDQ Target Settings

The VREFDQ initial settings are largely dependant on the ODT termination settings. The

table below shows all of the possible initial settings available for VREFDQ training; it is

unlikely the lower ODT settings would be used in most cases.

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 38: VREFDQ Settings (VDDQ = 1.2V)

RON ODT Vx – VIN LOW (mV) VREFDQ (mv) VREFDQ (%VDDQ)

34 ohm

34 ohm 600 900 75%

40 ohm 550 875 73%

48 ohm 500 850 71%

60 ohm 435 815 68%

80 ohm 360 780 65%

120 ohm 265 732 61%

240 ohm 150 675 56%

48 ohm

34 ohm 700 950 79%

40 ohm 655 925 77%

48 ohm 600 900 75%

60 ohm 535 865 72%

80 ohm 450 825 69%

120 ohm 345 770 64%

240 ohm 200 700 58%

Figure 73: VREFDQ Equivalent Circuit

RXer

VREFDQ

(internal)

RON

ODT

VDDQ VDDQ

8Gb: x4, x8, x16 DDR4 SDRAM

VREFDQ Calibration

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 128 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Connectivity Test Mode

Connectivity test (CT) mode is similar to boundary scan testing but is designed to sig-

nificantly speed up the testing of electrical continuity of pin interconnections between

the device and the memory controller on the PC boards. Designed to work seamlessly

with any boundary scan device, CT mode is supported in all ×4, ×8, and ×16 non-3DS

devices (JEDEC states CT mode for ×4 and ×8 is not required on 4Gb and is an optional

feature on 8Gb and above). 3DS devices do not support CT mode and the TEN pin

should be considered RFU maintained LOW at all times.

Contrary to other conventional shift-register-based test modes, where test patterns are

shifted in and out of the memory devices serially during each clock, the CT mode allows

test patterns to be entered on the test input pins in parallel and the test results to be

extracted from the test output pins of the device in parallel. These two functions are al-

so performed at the same time, significantly increasing the speed of the connectivity

check. When placed in CT mode, the device appears as an asynchronous device to the

external controlling agent. After the input test pattern is applied, the connectivity test

results are available for extraction in parallel at the test output pins after a fixed propa-

gation delay time.

Note: A reset of the device is required after exiting CT mode (see RESET and Initializa-

tion Procedure).

Pin Mapping

Only digital pins can be tested using the CT mode. For the purposes of a connectivity

check, all the pins used for digital logic in the device are classified as one of the follow-

ing types:

•Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode.

In CT mode, the normal memory function inside the device is bypassed and the I/O

pins appear as a set of test input and output pins to the external controlling agent.

Additionally, the device will set the internal VREFDQ to VDDQ × 0.5 during CT mode

(this is the only time the DRAM takes direct control over setting the internal VREFDQ).

The TEN pin is dedicated to the connectivity check function and will not be used dur-

ing normal device operation.

•Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the

device. When de-asserted, these output pins will be High-Z. The CS_n pin in the de-

vice serves as the CS_n pin in CT mode.

•Test input: A group of pins used during normal device operation designated as test

input pins. These pins are used to enter the test pattern in CT mode.

•Test output: A group of pins used during normal device operation designated as test

output pins. These pins are used for extraction of the connectivity test results in CT

mode.

•RESET_n: This pin must be fixed high level during CT mode, as in normal function.

8Gb: x4, x8, x16 DDR4 SDRAM

Connectivity Test Mode

CCMTD-1725822587-9875

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Table 39: Connectivity Mode Pin Description and Switching Levels

CT Mode

Pins Pin Name During Normal Memory Operation Switching Level Notes

Test enable TEN CMOS (20%/80% VDD) 1, 2

Chip select CS_n VREFCA ±200mV 3

Test

input

ABA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,

CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR

VREFCA ±200mV 3

B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n VREFDQ ±200mV 4

C ALERT_n CMOS (20%/80% VDD) 2, 5

D RESET_n CMOS (20%/80% VDD)2

Test

output

DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c VTT ±100mV 6

Notes: 1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW.

TEN must be LOW during normal operation.

2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV

for DC HIGH and 240mV for DC LOW.)

3. VREFCA should be VDD/2.

4. VREFDQ should be VDDQ/2.

5. ALERT_n switching level is not a final setting.

6. VTT should be set to VDD/2.

Minimum Terms Definition for Logic Equations

The test input and output pins are related by the following equations, where INV de-

notes a logical inversion operation and XOR a logical exclusive OR operation:

MT0 = XOR (A1, A6, PAR)

MT1 = XOR (A8, ALERT_n, A9)

MT2 = XOR (A2, A5, A13) or XOR (A2, A5, A13, A17)

MT3 = XOR (A0, A7, A11)

MT4 = XOR (CK_c, ODT, CAS_n/A15)

MT5 = XOR (CKE, RAS_n/A16, A10/AP)

MT6 = XOR (ACT_n, A4, BA1)

MT7 = ×16: XOR (DMU_n/DBIU_n, DML_n/DBIL_n, CK_t)

= x8: XOR (BG1, DML_n/DBIL_n, CK_t)

= x4: XOR (BG1, CK_t)

MT8 = XOR (WE_n/A14, A12 / BC, BA0)

MT9 = XOR (BG0, A3, RESET_n and TEN)

Logic Equations for a x4 Device

DQ0 = XOR (MT0, MT1)

DQ1 = XOR (MT2, MT3)

DQ2 = XOR (MT4, MT5)

DQ3 = XOR (MT6, MT7)

DQS_t = MT8

DQS_c = MT9

8Gb: x4, x8, x16 DDR4 SDRAM

Connectivity Test Mode

CCMTD-1725822587-9875

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Logic Equations for a x8 Device

DQ0 = MT0 DQ5 = MT5

DQ1 = MT1 DQ6 = MT6

DQ2 = MT2 DQ7 = MT7

DQ3 = MT3 DQS_t = MT8

DQ4 = MT4 DQS_c = MT9

Logic Equations for a x16 Device

DQ0 = MT0 DQ10 = INV DQ2

DQ1 = MT1 DQ11 = INV DQ3

DQ2 = MT2 DQ12 = INV DQ4

DQ3 = MT3 DQ13 = INV DQ5

DQ4 = MT4 DQ14 = INV DQ6

DQ5 = MT5 DQ15 = INV DQ7

DQ6 = MT6 LDQS_t = MT8

DQ7 = MT7 LDQS_c = MT9

DQ8 = INV DQ0 UDQS_t = INV LDQS_t

DQ9 = INV DQ1 UDQS_c = INV LDQS_c

CT Input Timing Requirements

Prior to the assertion of the TEN pin, all voltage supplies, including VREFCA, must be val-

id and stable and RESET_n registered high prior to entering CT mode. Upon the asser-

tion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and

CKE signals become test inputs within tCTECT_Valid. The remaining CT inputs become

valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, pro-

vided inputs were valid for at least tCT_Valid. While in CT mode, refresh activities in the

memory arrays are not allowed; they are initiated either externally (auto refresh) or in-

ternally (self refresh).

The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM

is initialized and VREFDQ is calibrated, CT mode may no longer be used. The TEN pin

may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the

integrity of the original content of the memory array are unknown. A full reset of the

memory device is required.

After CT mode has been entered, the output signals will be stable within tCT_Valid after

the test inputs have been applied as long as TEN is maintained HIGH and CS_n is main-

tained LOW.

8Gb: x4, x8, x16 DDR4 SDRAM

Connectivity Test Mode

CCMTD-1725822587-9875

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Figure 74: Connectivity Test Mode Entry

tCTCKE_Valid

T = 10ns

CS_n

CT Inputs

CT Outputs

tCT_Enable

tCKSRX

tCTCKE_Valid >10ns

tCT_IS >0ns

T = 500μsT = 200μs

tIS

tCT_Valid tCT_Valid

tCT_Valid

TEN

Valid input Valid input

Valid Valid

RESET_n

CKE

CK_c

CK_t

Ta Tb Tc Td

tCT_IS

Don’t Care

8Gb: x4, x8, x16 DDR4 SDRAM

Connectivity Test Mode

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Excessive Row Activation

Rows can be accessed a limited number of times within a certain time period before ad-

jacent rows require refresh. The maximum activate count (MAC) is the maximum num-

ber of activates that a single row can sustain within a time interval of equal to or less

than the maximum activate window (tMAW) before the adjacent rows need to be re-

freshed, regardless of how the activates are distributed over tMAW.

Micron's DDR4 devices automatically perform a type of TRR mode in the background

and provide an MPR Page 3 MPR3[3:0] of 1000, indicating there is no restriction to the

number of ACTIVATE commands to a given row in a refresh period provided DRAM tim-

ing specifications are not violated. However, specific attempts to by-pass TRR may re-

sult in data disturb.

Table 40: MAC Encoding of MPR Page 3 MPR3

[7] [6] [5] [4] [3] [2] [1] [0] MAC Comments

xxxx0000 Untested The device has not been tested for MAC.

xxxx0001tMAC = 700K

xxxx0010tMAC = 600K

xxxx0011tMAC = 500K

xxxx0100tMAC = 400K

xxxx0101tMAC = 300K

xxxx0110 Reserved

xxxx0111tMAC = 200K

x x x x 1 0 0 0 Unlimited There is no restriction to the number of AC-

TIVATE commands to a given row in a re-

fresh period provided DRAM timing specifi-

cations are not violated.

x x x x 1 0 0 1 Reserved

x x x x : : : : Reserved

x x x x 1 1 1 1 Reserved

Note: 1. MAC encoding in MPR Page 3 MPR3.

8Gb: x4, x8, x16 DDR4 SDRAM

Excessive Row Activation

CCMTD-1725822587-9875

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Post Package Repair

JEDEC defines two modes of Post Package Repair (PPR): soft Post Package Repair (sPPR)

and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row maybe

altered; that is, sPPR is NOT a permanent repair and even though it will repair a row, the

repair can be reversed, reassigned via another sPPR, or made permanent via hPPR.

Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR ad-

dress, further PPR commands to a previous hPPR section should not be performed, that

is, hPPR is a permanent repair; once repaired, it cannot be reversed. The controller pro-

vides the failing row address in the hPPR/sPPR sequence to the device to perform the

row repair. hPPR Mode and sPPR Mode may not be enabled at the same time.

JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts how-

ever Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The

hPPR support is identified via an MPR read from MPR Page 2, MPR0[7] and sPPR sup-

port is identified via an MPR read from MPR Page 2, MPR0[6].

The JEDEC minimum support requirement for DDR4 PPR (hPPR or sPPR) is to provide

one row of repair per bank group (BG), x4/x8 have 4 BG and x16 has 2 BG; this is a total

of 4 repair rows available on x4/x8 and 2 repair rows available on x16. Micron PPR sup-

port exceeds the JEDEC minimum requirements; Micron DDR4 DRAMs have at least

one row of repair for each bank which is essentially 4 row repairs per BG for a total of 16

repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows.

JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to

enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing

sPPR row repair addresses are not required to be cleared prior to entering hPPR mode.

Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a

sPPR row repair existing in a different bank.

sPPR followed by sPPR to same bank

When PPR is issued to a bank for the first time and is a sPPR command, the repair row

will be a sPPR. When a subsequent sPPR is issued to the same bank, the previous sPPR

repair row will be cleared and used for the subsequent sPPR address as the sPPR opera-

tion is non-persistent.

sPPR followed by hPPR to same bank

When a PPR is issued to a bank for the first time and is a sPPR command, the repair row

will be a sPPR. When a subsequent hPPR is issued to the same bank, the initial sPPR

repair row will be cleared and used for the hPPR address1. If a further subsequent PPR

(hPPR or sPPR) is issued to the same bank, the further subsequent PPR ( hPPR or sPPR)

repair row will not clear or overwrite the previous hPPR address as the hPPR operation

is persistent.

hPPR followed by hPPR or sPPR to same bank

When a PPR is issued to a bank for the first time and is a hPPR command, the repair row

will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the same bank, the

subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR

address as the initial hPPR is persistent.

8Gb: x4, x8, x16 DDR4 SDRAM

Post Package Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Note 1) Newer Micron DDR4 designs may not guarantee that an sPPR followed by an

hPPR to the same bank will result the same repair row being used. Contact factory for

more information.

Hard Post Package Repair

All banks must be precharged and idle. DBI and CRC modes must be disabled. Both

sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled

with MR4[13] = 0, which is the normal state, and hPPR is enabled with MR4 [13]= 1,

which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of

hPPR have the same entry requirement as defined in the sections below. The first com-

mand sequence uses a WRA command and supports data retention with a REFRESH

operation except for the bank containing the row that is being repaired; JEDEC has re-

laxed this requirement and allows BA[0] to be a don't care regarding the banks which

are not required to maintain data a REFRESH operation during hPPR. The second com-

mand sequence uses a WR command (a REFRESH operation can't be performed in this

command sequence). The second command sequence doesn't support data retention

for the target DRAM.

hPPR Row Repair - Entry

As stated above, all banks must be precharged and idle. DBI and CRC modes must be

disabled, and all timings must be followed as shown in the timing diagram that follows.

All other commands except those listed in the following sequences are illegal.

1. Issue MR4[13] 1 to enter hPPR mode enable.

a. All DQ are driven HIGH.

2. Issue four consecutive guard key commands (shown in the table below) to MR0

with each command separated by tMOD. The PPR guard key settings are the same

whether performing sPPR or hPPR mode.

a. Any interruption of the key sequence by other commands, such as ACT, WR,

RD, PRE, REF, ZQ, and NOP, are not allowed.

b. If the guard key bits are not entered in the required order or interrupted with

other MR commands, hPPR will not be enabled, and the programming cycle

will result in a NOP.

c. When the hPPR entry sequence is interrupted and followed by ACT and WR

commands, these commands will be conducted as normal DRAM com-

mands.

d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a suppli-

er perspective and the user should rely on vendor datasheet.

Table 41: PPR MR0 Guard Key Settings

MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0

First guard key 0 0 xxxxxx 1 1 0 0 1 1111111

Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111

Third Guard key 0 0 xxxxxx 1 0 1 1 1 1111111

Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111

8Gb: x4, x8, x16 DDR4 SDRAM

Hard Post Package Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice.

hPPR Row Repair – WRA Initiated (REF Commands Allowed)

1. Issue an ACT command with failing BG and BA with the row address to be re-

paired.

2. Issue a WRA command with BG and BA of failing row address.

a. The address must be at valid levels, but the address is "Don't Care."

3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)

after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.

a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through

bit 7 are LOW. The bank under repair does not get the REFRESH command

applied to it.

b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through

bit 7 is HIGH.

1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH

is driven to all DQs of a DRAM consecutively for equal to or longer than

2tCK, then DRAM does not conduct hPPR and retains data if REF com-

mand is properly issued; if all DQs are neither LOW for 4tCK nor HIGH

for equal to or longer than 2tCK, then hPPR mode execution is un-

known.

c. DQS should function normally.

4. REF command may be issued anytime after the WRA command followed by WL +

4nCK + tWR + tRP.

a. Multiple REF commands are issued at a rate of tREFI or tREFI/2, however

back-to-back REF commands must be separated by at least tREFI/4 when the

DRAM is in hPPR mode.

b. All banks except the bank under repair will perform refresh.

5. Issue PRE after tPGM time so that the device can repair the target row during tPGM

time.

a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target

row address.

6. Issue MR4[13] 0 command to hPPR mode disable.

a. Wait tPGMPST for hPPR mode exit to complete.

b. After tPGMPST has expired, any valid command may be issued.

The entire sequence from hPPR mode enable through hPPR mode disable may be re-

peated if more than one repair is to be done.

After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if

the device is to be accessed.

After hPPR mode has been exited, the DRAM controller can confirm if the target row

was repaired correctly by writing data into the target row and reading it back.

8Gb: x4, x8, x16 DDR4 SDRAM

Hard Post Package Repair

CCMTD-1725822587-9875

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Figure 75: hPPR WRA – Entry

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ADDR

CMD

CKE

DQS_t

DQS_c

DQs

Valid

BA BAf

Valid

BGf

tRCD

WL = CWL+AL+PL tWR +

tRP + 1nCK

CK_t

CK_c

N/A

All Banks

Precharged

and idle state

Normal

mode

hPPR Recognition hPPR Exit

hPPR Repair hPPR RepairhPPR Repair

MRSx

tPGM

ACT WRA

Valid

(A13 = 0)

Valid

N/A

tPGM_Exit tPGMPST

REF/DES REF/DES REF/DESDES DES DES DES DES

N/A

DESPRE

Valid

BAf

BGf

Te0 Tf0 Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 Tk0 Tk1 Tm0 Tm1 Tn0

4nCK

bit 0 bit 7

bit 6

bit 1

Don’t Care

hPPR Row Repair – WR Initiated (REF Commands NOT Allowed)

1. Issue an ACT command with failing BG and BA with the row address to be re-

paired.

2. Issue a WR command with BG and BA of failing row address.

a. The address must be at valid levels, but the address is "Don't Care."

3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)

after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.

a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through

bit 7 are LOW.

b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through

bit 7 is HIGH.

1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH

is driven to all DQs of a DRAM consecutively for equal to or longer than

2tCK, then DRAM does not conduct hPPR and retains data if REF com-

mand is properly issued; if all DQs are neither LOW for 4tCK nor HIGH

for equal to or longer than 2tCK, then hPPR mode execution is un-

known.

8Gb: x4, x8, x16 DDR4 SDRAM

Hard Post Package Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice.

c. DQS should function normally.

4. REF commands may NOT be issued at anytime while in PPT mode.

5. Issue PRE after tPGM time so that the device can repair the target row during tPGM

time.

a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target

row address.

6. Issue MR4[13] 0 command to hPPR mode disable.

a. Wait tPGMPST for hPPR mode exit to complete.

b. After tPGMPST has expired, any valid command may be issued.

The entire sequence from hPPR mode enable through hPPR mode disable may be re-

peated if more than one repair is to be done.

After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if

the device is to be accessed.

After hPPR mode has been exited, the DRAM controller can confirm if the target row

was repaired correctly by writing data into the target row and reading it back.

Figure 77: hPPR WR – Entry

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Figure 78: hPPR WR – Repair and Exit

ADDR

CMD

CKE

DQS_t

DQS_c

DQs

Valid

BA BAf

Valid

BGf

tRCD

WL = CWL + AL + PL

CK_t

CK_c

N/A

All Banks

Precharged

and idle state

Normal

mode

hPPR Recognition hPPR Exit

hPPR Repair hPPR RepairhPPR Repair

MRSx

tPGM

ACT WR

Valid

(A13 = 0)

Valid

N/A

tPGM_Exit tPGMPST

DES DES DES DES DES DES DESDES

N/A

DESPRE

Valid

BAf

BGf

Te0 Tf0 Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 Tk0 Tk1 Tm0 Tm1 Tn0

4nCK

bit 0 bit 7

bit 6

bit 1

Don’t Care

8Gb: x4, x8, x16 DDR4 SDRAM

Hard Post Package Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200

Parameter Symbol Min Max Unit

hPPR programming time tPGM ×4, ×8 1000 – ms

×16 2000 – ms

hPPR precharge exit time tPGM_Exit 15 – ns

hPPR exit time tPGMPST 50 – μs

sPPR Row Repair

Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row ele-

ment in a bank on a DRAM device, where hPPR takes longer but permanently repairs a

row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5]

while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state,

and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state.

sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. After

sPPR entry, an ACT command will capture the target bank and target row, herein seed

row, where the row repair will be made. After tRCD time, a WR command is used to se-

lect the individual DRAM, through the DQ bits, to transfer the repair address into an in-

ternal register in the DRAM. After a write recovery time and PRE command, the sPPR

mode can be exited and normal operation can resume.

The DRAM will retain the soft repair information as long as VDD remains within the op-

erating region unless rewritten by a subsequent sPPR entry to the same bank. If DRAM

power is removed or the DRAM is reset, the soft repair will revert to the unrepaired

state. hPPR and sPPR should not be enabled at the same time; Micron sPPR does not

have to be disabled and cleared prior to entering hPPR mode, but sPPR must be disa-

bled and cleared prior to entering MBIST-PPR mode.

With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR re-

quest is made to the same bank, the subsequently issued sPPR address will replace the

previous sPPR address. When the hPPR resource for a bank is used up, the bank should

be assumed to not have available resources for sPPR. If a repair sequence is issued to a

bank with no repair resource available, the DRAM will ignore the programming se-

quence.

The bank receiving sPPR change is expected to retain memory array data in all rows ex-

cept for the seed row and its associated row addresses. If the data in the memory array

in the bank under sPPR repair is not required to be retained, then the handling of the

seed row’s associated row addresses is not of interest and can be ignored. If the data in

the memory array is required to be retained in the bank under sPPR mode, then prior to

executing the sPPR mode, the seed row and its associated row addresses should be

backed up and subsequently restored after sPPR has been completed. sPPR associated

seed row addresses are specified in the Table below; BA0 is not required by Micron

DRAMs however it is JEDEC reserved.

Table 43: sPPR Associated Rows

sPPR Associated Row Address

BA0* A17 A16 A15 A14 A13 A1 A0

8Gb: x4, x8, x16 DDR4 SDRAM

sPPR Row Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice.

All banks must be precharged and idle. DBI and CRC modes must be disabled, and all

sPPR timings must be followed as shown in the timing diagram that follows.

All other commands except those listed in the following sequences are illegal.

1. Issue MR4[5] 1 to enter sPPR mode enable.

a. All DQ are driven HIGH.

2. Issue four consecutive guard key commands (shown in the table below) to MR0

with each command separated by tMOD. Please note that JEDEC recently added

the four guard key entry used for hPPR to sPPR entry; early DRAMs may not re-

quire four guard key entry code. A prudent controller design should accommodate

either option in case an earlier DRAM is used.

a. Any interruption of the key sequence by other commands, such as ACT, WR,

RD, PRE, REF, ZQ, and NOP, are not allowed.

b. If the guard key bits are not entered in the required order or interrupted with

other MR commands, sPPR will not be enabled, and the programming cycle

will result in a NOP.

c. When the sPPR entry sequence is interrupted and followed by ACT and WR

commands, these commands will be conducted as normal DRAM com-

mands.

d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a suppli-

er perspective and the user should rely on vendor datasheet.

Table 44: PPR MR0 Guard Key Settings

MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0

First guard key 0 0 xxxxxx 1 1 0 0 1 1111111

Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111

Third guard key 0 0 xxxxxx 1 0 1 1 1 1111111

Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111

3. After tMOD, issue an ACT command with failing BG and BA with the row address

to be repaired.

4. After tRCD, issue a WR command with BG and BA of failing row address.

a. The address must be at valid levels, but the address is a "Don't Care."

5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)

after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.

a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through

bit 7 are LOW.

b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through

bit 7 is HIGH.

1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH

is driven to all DQs of a DRAM consecutively for equal to or longer than

the first 2tCK, then DRAM does not conduct hPPR and retains data if

REF command is properly issued; if all DQs are neither LOW for 4tCK

nor HIGH for equal to or longer than the first 2tCK, then hPPR mode ex-

ecution is unknown.

c. DQS should function normally.

6. REF command may NOT be issued at anytime while in sPPR mode.

7. Issue PRE after tWR time so that the device can repair the target row during tWR

time.

a. Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired tar-

get row address.

8Gb: x4, x8, x16 DDR4 SDRAM

sPPR Row Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice.

8. Issue MR4[5] 0 command to sPPR mode disable.

a. Wait tPGMPST_s for sPPR mode exit to complete.

b. After tPGMPST_s has expired, any valid command may be issued.

The entire sequence from sPPR mode enable through sPPR mode disable may be repea-

ted if more than one repair is to be done.

After sPPR mode has been exited, the DRAM controller can confirm if the target row

was repaired correctly by writing data into the target row and reading it back.

Figure 79: sPPR – Entry

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Figure 80: sPPR – Repair, and Exit

bit 1

ADDR

CMD

CKE

DQS_t

DQS_c

DQs

Valid

BA BAf

Valid

BGf

tRCD

WL = CWL + AL + PL

CK_t

CK_c

N/A

All Banks

Precharged

and idle state

Normal

Mode

sPPR Recognition sPPR Exit

sPPR Repair sPPR RepairsPPR RepairsPPR Repair

MRS4

tPGM_s

ACT WR

Valid

(A5=0)

Valid

N/A

DES DES DES DES DES DES DES DES

N/A

DESPRE

Valid

BAf

BGf

Te0 Tf0 Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 Tk0 Tk1 Tm0 Tm1 Tn0

4nCK

bit 0 bit 7

bit 6

tPGM_Exit_s tPGMPST_s

Don’t Care

Table 45: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200

Parameter Symbol Min Max Unit

sPPR programming time tPGM_s t RCD(MIN)+ WL + 4nCK

+ tWR(MIN)

–ns

sPPR precharge exit time tPGM_Exit_s 20 – ns

sPPR exit time tPGMPST_s tMOD – ns

8Gb: x4, x8, x16 DDR4 SDRAM

sPPR Row Repair

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice.

MBIST-PPR

DDR4 devices can support optional memory built-in self-test post-package repair

(MBIST-PPR) to help with hard failures such as single-bit or multi-bit failures in a single

device so that weak cells can be scanned and repaired during the initialization phase.

The DRAM will use vendor-specific patterns to investigate the status of all cell arrays

and automatically perform PPR for weak bits during this operation. This operation in-

troduces proactive, automated PPR by the DRAM, and it is recommended to be done for

a very first boot-up at least. After that, it is at the controller’s discretion whether to acti-

vate MBIST. MBIST mode can only be entered from the all banks idle state. The DLL is

required to be enabled and locked prior to MBIST-PPR execution.

MBIST-PPR resources are separated from normal hPPR/sPPR resources. MBIST-PPR re-

sources are typically used for initial scan and repair, and hPPR/sPPR resources must still

satisfy the number of repair elements, one per BG, specified in the DDR4 Bank Group

Timing Examples Table 70 (page 192). Once the MBIST-PPR is completed, the DRAM

will update the status flag in MPR3[7] of MPR page 3. Detailed status is described in the

MPR Page and MPRx Definitions Table 30 (page 92).

The test time of MBIST-PPR will not exceed 10 seconds for all mono-die DRAM densi-

ties. For DDP devices, test time will be 20 seconds.

The controller is required to inject an MRS command to enter this operation. The con-

troller sets MR4:A0 to 1, followed by MR0 commands for the guard key. Then the DRAM

enters MBIST-PPR operation. The ALERT_n signal notifies the host of the status of this

operation. When the controller sets MR4:A0 to 1, followed by the MR0 guard key se-

quence, the DRAM drives ALERT_n to 0. Once the MBISTS PPR is completed, the DRAM

drives ALERT_n to 1 to notify the controller that this operation is completed. DRAM da-

ta will not be guaranteed after the MBIST-PPR operation.

Table 46: MBIST-PPR Timing Parameter

Parameter

Value

UnitMin Max

tSELFHEAL Monolithic - 10 s

DDP - 20

MBIST-PPR Procedure

The following sequences are required for MBIST-PPR and are shown in the figure below.

1. The DRAM needs to finalize initialization, MR training, and ZQ calibration prior to

entering MBIST PPR.

2. Four consecutive guard key commands must be issued to MR0, with each com-

mand separated by tMOD. The PPR guard key settings are the same whether per-

forming sPPR, hPPR, or MBIST-PPR mode.

3. Anytime after Tk in the Read Termination Disable Window Figure 15 (page 42), the

host must set MR4:A0 to 1, followed by subsequent MR0 guard key sequences

(which is identical to typical hPPR/sPPR guard key sequences and specified in Ta-

ble 73) to start MBIST PPR operation, and the DRAM drives the ALERT_n signal to

4. During MBIST-PPR mode, only DESELECT commands are allowed.

8Gb: x4, x8, x16 DDR4 SDRAM

MBIST-PPR

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice.

5. The ODT pin must be driven LOW during MBIST PPR to satisfy DODTLoff from

time Tb0 until Tc2. The DRAM may or may not provide RTT_PARK termination

during MBIST-PPR regardless of whether RTT_PARK is enabled in MR5.

Figure 81: MBIST-PPR Sequence

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Table 47: MPR Page3 Configuration for MBIST-PPR

Address MPR Location [7] [6] [5] [4] [3] [2] [1] [0] Note

BA[1:0] 00 = MPR0 DC DC DC DC DC DC DC DC Read-

only

01 = MPR1 DC DC DC DC DC DC DC DC

10 = MPR2 DC DC DC DC DC DC DC DC

11 = MPR3 MBIST-

PPR Sup-

port

DC MBIST-PPR Trans-

parency

MAC MAC MAC MAC

MPR Location Address Bit Function Data Notes

11 = MPR3 7 MBIST-PPR Support 0: Don't Support

1: Support 1

11 = MPR3 5:4 MBIST-PPR

Transparency

00B: MBIST-PPR hasn't run since init OR no fails found

during most recent MBIST-PPR 1,2

01B: Repaired all found fails during most recent run 1

10B: Unrepairable fails found during most recent run 1

11B: MBIST-PPR should be run again 1,3

Notes: 1. MPR bits are cleared either by a power-up sequence or re-initialization by RESET_n sig-

nal

8Gb: x4, x8, x16 DDR4 SDRAM

MBIST-PPR

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice.

2. The host should track whether MBIST-PPR has run since INIT. If MBIST-PPR is performed

and it finds no fails, this transparency state will remain set to 00B

3. This state does not imply that MBIST-PPR is required to run again. This implies that addi-

tional repairable fails were found during the most recent MBIST-PPR beyond what could

be repaired in the tSELFHEAL window.

hPPR/sPPR/MBIST-PPR Support Identifier

Table 48: DDR4 Repair Mode Support Identifier

MPR Page 2 A7 A6 A5 A4 A3 A2 A1 A0

UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

MPR0 hPPR1sPPR2RTT_WR Temp sensor CRC RTT_WR

MPR Page 3 A7 A6 A5 A4 A3 A2 A1 A0

UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

MPR3 MBIST-PPR

Support3Don't Care MBIST-PPR Transparency MAC MAC MAC MAC

Notes: 1. 0 = hPPR mode is not available, 1 = hPPR mode is available.

2. 0 = sPPR mode is not available, 1 = sPPR mode is available.

3. 0 = MBIST-PPR mode is not available, 1 = MBIST-PPR mode is available.

4. Gray shaded areas are for reference only.

ACTIVATE Command

The ACTIVATE command is used to open (activate) a row in a particular bank for subse-

quent access. The values on the BG[1:0] inputs select the bank group, the BA[1:0] inputs

select the bank within the bank group, and the address provided on inputs A[17:0] se-

lects the row within the bank. This row remains active (open) for accesses until a PRE-

CHARGE command is issued to that bank. A PRECHARGE command must be issued be-

fore opening a different row in the same bank. Bank-to-bank command timing for AC-

TIVATE commands uses two different timing parameters, depending on whether the

banks are in the same or different bank group. tRRD_S (short) is used for timing be-

tween banks located in different bank groups. tRRD_L (long) is used for timing between

banks located in the same bank group. Another timing restriction for consecutive ACTI-

VATE commands [issued at tRRD (MIN)] is tFAW (four activate window). Because there

is a maximum of four banks in a bank group, the tFAW parameter applies across differ-

ent bank groups (five ACTIVATE commands issued at tRRD_L (MIN) to the same bank

group would be limited by tRC).

8Gb: x4, x8, x16 DDR4 SDRAM

hPPR/sPPR/MBIST-PPR Support Identifier

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 82: tRRD Timing

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tRRD_S

T10 T11

Don’t Care

BG a

DES

ACT ACT

DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

Bank

Group

(BG)

Bank c

Bank

Row n

BG b

Bank c

Row n

BG b

Bank d

Row n

Address

tRRD_L

ACT

Notes: 1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI-

VATE commands to different bank groups (that is, T0 and T4).

2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI-

VATE commands to the different banks in the same bank group (that is, T4 and T10).

Figure 83: tFAW Timing

T0 Ta0 Tb0 Tc0 Tc1 Tc2

tRRD tRRD

Td0 Td1

Don’t Care Time Break

Valid

ACT ACT

Valid Valid Valid Valid Valid NOP

CK_t

CK_c

Command

Bank

Group

(BG)

Valid

Bank

Valid

ACT ACT

Address

tFAW

ACT

Valid

tRRD

Note: 1. tFAW; four activate windows.

PRECHARGE Command

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row activation

for a specified time (tRP) after the PRECHARGE command is issued. An exception to

this is the case of concurrent auto precharge, where a READ or WRITE command to a

different bank is allowed as long as it does not interrupt the data transfer in the current

bank and does not violate any other timing parameters.

After a bank is precharged, it is in the idle state and must be activated prior to any READ

or WRITE commands being issued to that bank. A PRECHARGE command is allowed if

there is no open row in that bank (idle state) or if the previously open row is already in

the process of precharging. However, the precharge period will be determined by the

last PRECHARGE command issued to the bank.

The auto precharge feature is engaged when a READ or WRITE command is issued with

A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay

the PRECHARGE operation until the ARRAY RESTORE operation has completed. The

8Gb: x4, x8, x16 DDR4 SDRAM

PRECHARGE Command

CCMTD-1725822587-9875

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RAS lockout circuit feature allows the PRECHARGE operation to be partially or com-

pletely hidden during burst READ cycles when the auto precharge feature is engaged.

The PRECHARGE operation will not begin until after the last data of the burst write se-

quence is properly stored in the memory array.

REFRESH Command

The REFRESH command (REF) is used during normal operation of the device. This

command is nonpersistent, so it must be issued each time a refresh is required. The de-

vice requires REFRESH cycles at an average periodic interval of tREFI. When CS_n,

RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of

the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be pre-

charged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH

command can be applied. The refresh addressing is generated by the internal DRAM re-

fresh controller. This makes the address bits “Don’t Care” during a REFRESH command.

An internal address counter supplies the addresses during the REFRESH cycle. No con-

trol of the external address bus is required once this cycle has started. When the RE-

FRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle)

state. A delay between the REFRESH command and the next valid command, except

DES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN),

as shown in Figure 84 (page 147).

Note: The tRFC timing parameter depends on memory density.

In general, a REFRESH command needs to be issued to the device regularly every tREFI

interval. To allow for improved efficiency in scheduling and switching between tasks,

some flexibility in the absolute refresh interval is provided for postponing and pulling-

in the REFRESH command. A limited number REFRESH commands can be postponed

depending on refresh mode: a maximum of 8 REFRESH commands can be postponed

when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be

postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH

commands can be postponed when the device is in 4X refresh mode.

When 8 consecutive REFRESH commands are postponed, the resulting maximum inter-

val between the surrounding REFRESH commands is limited to 9 × tREFI (see Figure 85

(page 147)). For both the 2X and 4X refresh modes, the maximum interval between sur-

rounding REFRESH commands allowed is limited to 17 × tREFI2 and 33 × tREFI4, re-

spectively.

A limited number REFRESH commands can be pulled-in as well. A maximum of 8 addi-

tional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode,

a maximum of 16 additional REFRESH commands can be issued when in advance in 2X

refresh mode, and a maximum of 32 additional REFRESH commands can be issued in

advance when in 4X refresh mode. Each of these REFRESH commands reduces the

number of regular REFRESH commands required later by one. The resulting maximum

interval between two surrounding REFRESH commands is limited to 9 × tREFI (Fig-

ure 86 (page 147)), 17 × tRFEI2, or 33 × tREFI4. At any given time, a maximum of 16 REF

commands can be issued within 2 × tREFI, 32 REF2 commands can be issued within 4 ×

tREFI2, and 64 REF4 commands can be issued within 8 × tREFI4 (larger densities are

limited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met).

8Gb: x4, x8, x16 DDR4 SDRAM

REFRESH Command

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 84: REFRESH Command Timing

DESREF DESREF Valid Valid Valid Valid REF ValidValidValid

CK_t

CK_c

Command

tRFC tRFC (MIN)

tREFI (MAX 9 × tREFI)

Don’t CareTime Break

T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3

Valid

DESDES

DRAM must be idle DRAM must be idle

Notes: 1. Only DES commands are allowed after a REFRESH command is registered until tRFC

(MIN) expires.

2. Time interval between two REFRESH commands may be extended to a maximum of 9 ×

tREFI.

Figure 85: Postponing REFRESH Commands (Example)

8 REF-Commands postponed

tRFC

tREFI

9 × tREFI

Figure 86: Pulling In REFRESH Commands (Example)

8 REF-Commands pulled-in

tRFC

tREFI 9 × tREFI

8Gb: x4, x8, x16 DDR4 SDRAM

REFRESH Command

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Temperature-Controlled Refresh Mode

During normal operation, temperature-controlled refresh (TCR) mode disabled, the de-

vice must have a REFRESH command issued once every tREFI, except for what is al-

lowed by posting (see REFRESH Command section). This means a REFRESH command

must be issued once every 7.8μs if TC is less than or equal to 85°C, once every 3.9μs if TC

is greater than 85°C, once every 1.95μs if TC is greater than 95°C, regardless of which

Temperature Mode is selected (MR4[2]). TCR mode is disabled by setting MR4[3] = 0

while TCR mode is enabled by setting MR4[3] = 1. When TCR mode is enabled (MR4[3]

= 1), the Temperature Mode must be selected where MR4[2] = 0 enables the Normal

Temperature Mode while MR4[2] = 1 enables the Extended Temperature Mode.

When TCR mode is enabled, the device will register the externally supplied REFRESH

command and adjust the internal refresh period to be longer than tREFI of the normal

temperature range, when allowed, by skipping REFRESH commands with the proper

gear ratio. TCR mode has two Temperature Modes to select between the normal tem-

perature range and the extended temperature range; the correct Temperature Mode

must be selected so the internal control operates correctly. The DRAM must have the

correct refresh rate applied externally; the internal refresh rate is determined by the

DRAM based upon the temperature.

Normal Temperature Mode

REFRESH commands should be issued to the device with the refresh period equal to

tREFI of normal temperature range (-40°C to 85°C). The system must guarantee that the

TC does not exceed 85°C when tREFI of the normal temperature range is used. The de-

vice may adjust the internal refresh period to be longer than tREFI of the normal tem-

perature range by skipping external REFRESH commands with the proper gear ratio

when TC is below 85°C. The internal refresh period is automatically adjusted inside the

DRAM, and the DRAM controller does not need to provide any additional control.

Extended Temperature Mode

REFRESH commands should be issued to the device with the refresh period equal to

tREFI of extended temperature range (85°C to 95°C, or 95°C to 105°C) . The system must

guarantee that the TC does not exceed 95°C, or 105°C. Even though the external refresh

supports the extended temperature range, the device may adjust its internal refresh pe-

riod to be equal to or longer than tREFI of the normal temperature range (-40°C to 85°C)

by skipping external REFRESH commands with the proper gear ratio when TC is equal

to or below 85°C. The internal refresh period is automatically adjusted inside the

DRAM, and the DRAM controller does not need to provide any additional control.

Table 49: Normal tREFI Refresh (TCR Enabled)

Normal Temperature Mode Extended Temperature Mode

Temperature

External Refresh

Period

Internal Refresh

Period

External Refresh

Period

Internal Refresh

Period

TC ื 85°C 7.8μs ุ7.8μs 3.9μs1ุ7.8μs

85°C < TC ื 95°C 3.9μs

8Gb: x4, x8, x16 DDR4 SDRAM

Temperature-Controlled Refresh Mode

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Table 49: Normal tREFI Refresh (TCR Enabled) (Continued)

Normal Temperature Mode Extended Temperature Mode

Temperature

External Refresh

Period

Internal Refresh

Period

External Refresh

Period

Internal Refresh

Period

95°C < TC ื 105°C 1.95μs

Note: 1. If the external refresh period is slower than 3.9μs, the device will refresh internally at

too slow of a refresh rate and will violate refresh specifications.

8Gb: x4, x8, x16 DDR4 SDRAM

Temperature-Controlled Refresh Mode

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Figure 87: TCR Mode Example1

External REFRESH

commands are not

ignored

At least every other

external REFRESH

ignored

Controller 85°C  TC  95°C TC  85°C

Controller issues REFRESH

commands at extended

temperature rate

REFRESH

External

tREFI

3.9μs

Internal

tREFI

3.9μs Internal

tREFI

7.8μs

REFRESH

Note: 1. TCR enabled with Extended Temperature Mode selected.

8Gb: x4, x8, x16 DDR4 SDRAM

Temperature-Controlled Refresh Mode

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Fine Granularity Refresh Mode

Mode Register and Command Truth Table

The REFRESH cycle time (tRFC) and the average refresh interval (tREFI) can be pro-

grammed by the MRS command. The appropriate setting in the mode register will set a

single set of REFRESH cycle times and average refresh interval for the device (fixed

mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and

average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be ena-

bled by MRS before any OTF REFRESH command can be issued.

Table 50: MRS Definition

MR3[8] MR3[7] MR3[6] Refresh Rate Mode

0 0 0 Normal mode (fixed 1x)

0 0 1 Fixed 2x

0 1 0 Fixed 4x

0 1 1 Reserved

1 0 0 Reserved

1 0 1 On-the-fly 1x/2x

1 1 0 On-the-fly 1x/4x

1 1 1 Reserved

There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by pro-

gramming the appropriate values into the mode register MR3 [8:6]. When either of the

two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH com-

mand is issued, and depending on the status of BG0, it dynamically switches its internal

refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the

corresponding REFRESH operation.

Table 51: REFRESH Command Truth Table

Refresh CS_n ACT_n

RAS_n/A

CAS_n/A

WE_n/

A13 BG1 BG0

A10/

A[9:0],

A[12:11],

A[20:16]

MR3[8:6

]

Fixed rate L H L L H V V V V 0vv

OTF: 1x L H L L H V L V V 1vv

OTF: 2x L H L L H V H V V 101

OTF: 4x L H L L H V H V V 110

tREFI and tRFC Parameters

The default refresh rate mode is fixed 1x mode where REFRESH commands should be

issued with the normal rate; that is, tREFI1 = tREFI(base) (for TC ื 85°C), and the dura-

tion of each REFRESH command is the normal REFRESH cycle time (tRFC1). In 2x

mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the

device at the double frequency (tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x

mode, the REFRESH command rate should be quadrupled (tREFI4 = tREFI(base)/4). Per

8Gb: x4, x8, x16 DDR4 SDRAM

Fine Granularity Refresh Mode

CCMTD-1725822587-9875

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each mode and command type, the tRFC parameter has different values as defined in

the following table.

For discussion purposes, the REFRESH command that should be issued at the normal

refresh rate and has the normal REFRESH cycle duration may be referred to as an REF1x

command. The REFRESH command that should be issued at the double frequency

(tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH

command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be

referred to as a REF4x command.

In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2x

refresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh rate

mode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh rate

mode is enabled, both REF1x and REF2x commands are permitted. When the OTF

1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted.

Table 52: tREFI and tRFC Parameters

Refresh

Mode Parameter 2Gb 4Gb 8Gb 16Gb Units

tREFI (base) 7.8 7.8 7.8 7.8 μs

1x mode tREFI1 -40°C ื TC ื 85°C tREFI(base) tREFI(base) tREFI(base) tREFI(base) μs

85°C ื TC ื 95°C tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 μs

95°C ื TC ื 105°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs

tRFC1 160 260 350 350 ns

2x mode tREFI2 -40°C ื TC ื 85°C tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 μs

85°C ื TC ื 95°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs

95°C ื TC ื 105°C tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 μs

tRFC2 110 160 260 260 ns

4x mode tREFI4 -40°C ื TC ื 85°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs

85°C ื TC ื 95°C tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 μs

95°C ื TC ื 105°C tREFI(base)/16 tREFI(base)/16 tREFI(base)/16 tREFI(base)/16 μs

tRFC4 90 110 160 160 ns

8Gb: x4, x8, x16 DDR4 SDRAM

Fine Granularity Refresh Mode

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Figure 88: 4Gb with Fine Granularity Refresh Mode Example

tREFI = 0.975μs

1x Mode

(-40°C to 85°C)

2x Mode

(-40°C to 85°C)

4x Mode

(-40°C to 85°C)

Normal Temperature Operation – -40°C to 85°C

REF@260ns REF@160ns REF@110ns

REF@110ns

REF@160ns REF@110ns

REF@110ns

REF@260ns REF@160ns REF@110ns

REF@110ns

REF@160ns REF@110ns

REF@110nsREF@260ns REF@160ns

REF@110ns

tREFI = 7.8μs

tREFI = 3.9μs

tREFI = 1.95μs

1x Mode

(-40°C to 105°C)

2x Mode

(-40°C to 105°C)

4x Mode

(-40°C to 105°C)

REF@260ns REF@160ns REF@110ns

REF@110ns

REF@160ns REF@110ns

REF@110ns

REF@260ns REF@160ns REF@110ns

REF@110ns

REF@160ns REF@110ns

REF@110nsREF@260ns

REF@260ns

REF@160ns

REF@160ns REF@110ns

REF@110ns

tREFI = 3.9μs

tREFI = 1.95μs

Extended Temperature Operation – -40°C to 105°C

8Gb: x4, x8, x16 DDR4 SDRAM

Fine Granularity Refresh Mode

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Changing Refresh Rate

If the refresh rate is changed by either MRS or OTF. New tREFI and tRFC parameters will

be applied from the moment of the rate change. When the REF1x command is issued to

the DRAM, tREF1 and tRFC1 are applied from the time that the command was issued;

when the REF2x command is issued, tREF2 and tRFC2 should be satisfied.

Figure 89: OTF REFRESH Command Timing

REF1 DESDES DES ValidDES REF2 DESValid Valid DESDES DESREF2

tRFC1 (MIN) tRFC2 (MIN)

tREFI1 tREFI2

Don’t Care

Command

CK_t

CK_c

The following conditions must be satisfied before the refresh rate can be changed. Oth-

erwise, data retention cannot be guaranteed.

• In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number of

REF2x commands must be issued because the last change of the refresh rate mode

with an MRS command before the refresh rate can be changed by another MRS com-

mand.

• In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be is-

sued between any two REF1x commands.

• In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-four

number of REF4x commands must be issued because the last change of the refresh

rate with an MRS command before the refresh rate can be changed by another MRS

command.

• In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commands

must be issued between any two REF1x commands.

There are no special restrictions for the fixed 1x refresh rate mode. Switching between

fixed and OTF modes keeping the same rate is not regarded as a refresh rate change.

Usage with TCR Mode

If the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x

mode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode is

selected, the temperature controlled refresh mode must be disabled.

Self Refresh Entry and Exit

The device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any re-

striction on the number of REFRESH commands that have been issued during the

mode before the self refresh entry. However, upon self refresh exit, extra REFRESH com-

mand(s) may be required, depending on the condition of the self refresh entry.

The conditions and requirements for the extra REFRESH command(s) are defined as

follows:

• In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is rec-

ommended there be an even number of REF2x commands before entry into self re-

fresh after the last self refresh exit, REF1x command, or MRS command that set the

8Gb: x4, x8, x16 DDR4 SDRAM

Fine Granularity Refresh Mode

CCMTD-1725822587-9875

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refresh mode. If this condition is met, no additional REFRESH commands are re-

quired upon self refresh exit. In the case that this condition is not met, either one ex-

tra REF1x command or two extra REF2x commands must be issued upon self refresh

exit. These extra REFRESH commands are not counted toward the computation of the

average refresh interval (tREFI).

• In the fixed 4x refresh rate mode or the enable-OTF 1x/4x refresh rate mode, it is rec-

ommended there be a multiple-of-four number of REF4x commands before entry in-

to self refresh after the last self refresh exit, REF1x command, or MRS command that

set the refresh mode. If this condition is met, no additional refresh commands are re-

quired upon self refresh exit. When this condition is not met, either one extra REF1x

command or four extra REF4x commands must be issued upon self refresh exit. These

extra REFRESH commands are not counted toward the computation of the average

refresh interval (tREFI).

There are no special restrictions on the fixed 1x refresh rate mode.

This section does not change the requirement regarding postponed REFRESH com-

mands. The requirement for the additional REFRESH command(s) described above is

independent of the requirement for the postponed REFRESH commands.

8Gb: x4, x8, x16 DDR4 SDRAM

Fine Granularity Refresh Mode

CCMTD-1725822587-9875

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SELF REFRESH Operation

The SELF REFRESH command can be used to retain data in the device, even if the rest

of the system is powered down. When in self refresh mode, the device retains data with-

out external clocking. The device has a built-in timer to accommodate SELF REFRESH

operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n,

and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock.

Before issuing the SELF REFRESH ENTRY command, the device must be idle with all

banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are

closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and

all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper,

tZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must

be held LOW to keep the device in self refresh mode. The DRAM automatically disables

ODT termination, regardless of the ODT pin, when it enters self refresh mode and auto-

matically enables ODT upon exiting self refresh. During normal operation (DLL_on),

the DLL is automatically disabled upon entering self refresh and is automatically ena-

bled (including a DLL reset) upon exiting self refresh.

When the device has entered self refresh mode, all of the external control signals, except

CKE and RESET_n, are “Don’t Care.” For proper SELF REFRESH operation, all power

supply and reference pins (VDD, VDDQ, VSS, VSSQ, VPP, and VREFCA) must be at valid levels.

The DRAM internal VREFDQ generator circuitry may remain on or be turned off depend-

ing on the MR6 bit 7 setting. If the internal VREFDQ circuit is on in self refresh, the first

WRITE operation or first write-leveling activity may occur after tXS time after self re-

fresh exit. If the DRAM internal VREFDQ circuitry is turned off in self refresh, it ensures

that the VREFDQ generator circuitry is powered up and stable within the tXSDLL period

when the DRAM exits the self refresh state. The first WRITE operation or first write-lev-

eling activity may not occur earlier than tXSDLL after exiting self refresh. The device ini-

tiates a minimum of one REFRESH command internally within the tCKE period once it

enters self refresh mode.

The clock is internally disabled during a SELF REFRESH operation to save power. The

minimum time that the device must remain in self refresh mode is tCKESR/

tCKESR_PAR. The user may change the external clock frequency or halt the external

clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock must

be restarted and tCKSRX must be stable before the device can exit SELF REFRESH oper-

ation.

The procedure for exiting self refresh requires a sequence of events. First, the clock must

be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX,

combination of CKE going HIGH and DESELECT on the command bus) is registered,

the following timing delay must be satisfied:

Commands that do not require locked DLL:

•tXS = ACT, PRE, PREA, REF, SRE, and PDE.

•tXS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM

CL, WR/RTP register, and DLL reset in MR0; RTT(NOM) register in MR1; the CWL and

RTT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ pre-

amble registers in MR4; RTT(PARK) register in MR5; Data rate and VREFDQ calibration

value registers in MR6 may be accessed provided the DRAM is not in per-DRAM

mode. Access to other DRAM mode registers must satisfy tXS timing. WRITE com-

mands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT

and dynamic ODT controlled by the WRITE command require a locked DLL.

8Gb: x4, x8, x16 DDR4 SDRAM

SELF REFRESH Operation

CCMTD-1725822587-9875

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Commands that require locked DLL in the normal operating range:

•tXSDLL – RD, RDS4, RDS8, RDA, RDAS4, and RDAS8 (unlike DDR3, WR, WRS4, WRS8,

WRA, WRAS4, and WRAS8 because synchronous ODT is required).

Depending on the system environment and the amount of time spent in self refresh, ZQ

CALIBRATION commands may be required to compensate for the voltage and tempera-

ture drift described in the ZQ CALIBRATION Commands section. To issue ZQ CALIBRA-

TION commands, applicable timing requirements must be satisfied (see the ZQ Calibra-

tion Timing figure).

CKE must remain HIGH for the entire self refresh exit period tXSDLL for proper opera-

tion except for self refresh re-entry. Upon exit from self refresh, the device can be put

back into self refresh mode or power-down mode after waiting at least tXS period and

issuing one REFRESH command (refresh period of tRFC). The DESELECT command

must be registered on each positive clock edge during the self refresh exit interval tXS.

ODT must be turned off during tXSDLL.

The use of self refresh mode introduces the possibility that an internally timed refresh

event can be missed when CKE is raised for exit from self refresh mode. Upon exit from

self refresh, the device requires a minimum of one extra REFRESH command before it is

put back into self refresh mode.

Figure 90: Self Refresh Entry/Exit Timing

CK_t

CK_c

Command DES DESSRE

ADDR

CKE

ODT

SRX Valid1Valid2

Valid Valid

tRP

XSDLL

CKESR/

CKESR_PAR

tCPDED

tIS

tCKSRE/tCKSRE_PAR tCKSRX

Enter Self Refresh Exit Self Refresh

T0 T1 Ta0 Td0 Td1 Te0Tc0

Don’t Care

Tf0

Time Break

Tb0 Tg0

XS_FAST

Valid3

Valid

Valid Valid Valid

Valid

Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or

ZQCL commands are allowed.

2. Valid commands not requiring a locked DLL.

3. Valid commands requiring a locked DLL.

8Gb: x4, x8, x16 DDR4 SDRAM

SELF REFRESH Operation

CCMTD-1725822587-9875

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Figure 91: Self Refresh Entry/Exit Timing with CAL Mode

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Notes: 1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE/tCKSRE_PAR = 8nCK, tCKSRX = 8nCK, tXS_FAST =

tREFC4 (MIN) + 10ns.

2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't

Care," WE_n/A14 = "Don't Care."

3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or

ZQCL commands are allowed.

4. The figure only displays tXS_FAST timing, but tCAL must also be added to any tXS and

tXSDLL associated commands during CAL mode.

Self Refresh Abort

The exit timing from self refresh exit to the first valid command not requiring a locked

DLL is tXS. The value of tXS is (tRFC1 + 10ns). This delay allows any refreshes started by

the device time to complete. tRFC continues to grow with higher density devices, so tXS

will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled,

the controller uses tXS timings (location MR4, bit 9). If the bit is enabled, the device

aborts any ongoing refresh and does not increment the refresh counter. The controller

can issue a valid command not requiring a locked DLL after a delay of tXS_ABORT.

Upon exit from self refresh, the device requires a minimum of one extra REFRESH com-

mand before it is put back into self refresh mode. This requirement remains the same

irrespective of the setting of the MRS bit for self refresh abort.

8Gb: x4, x8, x16 DDR4 SDRAM

SELF REFRESH Operation

CCMTD-1725822587-9875

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Figure 92: Self Refresh Abort

CK_t

CK_c

Command DES DESSRE

ADDR

CKE

ODT

SRX Valid1Valid2

Valid Valid

tRP

XS_ABORT

XSDLL

CKESR/

CKESR_PAR

tCPDED

tIS

tCKSRE/tCKSRE_PAR tCKSRX

Enter Self Refresh Exit Self Refresh

T0 T1 Ta0 Td0 Td1 Te0Tc0

Don’t Care

Tf0

Time Break

Tb0 Tg0

XS_FAST

Valid3

Valid

Valid Valid Valid

Valid

Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or

ZQCL commands are allowed.

2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the

mode register.

3. Valid commands requiring a locked DLL.

Self Refresh Exit with NOP Command

Exiting self refresh mode using the NO OPERATION command (NOP) is allowed under a

specific system application. This special use of NOP allows for a common command/

address bus between active DRAM devices and DRAM(s) in maximum power saving

mode. Self refresh mode may exit with NOP commands provided:

• The device entered self refresh mode with CA parity, CAL, and gear-down disabled.

•tMPX_S and tMPX_LH are satisfied.

• NOP commands are only issued during tMPX_LH window.

No other command is allowed during the tMPX_LH window after an SELF REFRESH EX-

IT (SRX) command is issued.

8Gb: x4, x8, x16 DDR4 SDRAM

SELF REFRESH Operation

CCMTD-1725822587-9875

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Figure 93: Self Refresh Exit with NOP Command

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'(6

9DOLG 9DOLG 9DOLG 9DOLG

8Gb: x4, x8, x16 DDR4 SDRAM

SELF REFRESH Operation

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Power-Down Mode

Power-down is synchronously entered when CKE is registered LOW (along with a DESE-

LECT command). CKE is not allowed to go LOW when the following operations are in

progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/

WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW

ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the

power-down IDD specification will not be applied until those operations are complete.

The timing diagrams that follow illustrate power-down entry and exit.

For the fastest power-down exit timing, the DLL should be in a locked state when pow-

er-down is entered. If the DLL is not locked during power-down entry, the DLL must be

reset after exiting power-down mode for proper READ operation and synchronous ODT

operation. DRAM design provides all AC and DC timing and voltage specification as

well as proper DLL operation with any CKE intensive operations as long as the control-

ler complies with DRAM specifications.

During power-down, if all banks are closed after any in-progress commands are com-

pleted, the device will be in precharge power-down mode; if any bank is open after in-

progress commands are completed, the device will be in active power-down mode.

Entering power-down deactivates the input and output buffers, excluding CK, CKE, and

RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on

Mode Register 5, bit 5 (MR5[5]). If it is configured to 0b, the ODT input buffer remains

on and the ODT input signal must be at valid logic level. If it is configured to 1b, the

ODT input buffer is deactivated and the DRAM ODT input signal may be floating and

the device does not provide RTT(NOM) termination. Note that the device continues to

provide RTT(Park) termination if it is enabled in MR5[8:6]. To protect internal delay on the

CKE line to block the input signals, multiple DES commands are needed during the CKE

switch off and on cycle(s); this timing period is defined as tCPDED. CKE LOW will result

in deactivation of command and address receivers after tCPDED has expired.

Table 53: Power-Down Entry Definitions

DRAM Status DLL

Power-

Down Exit Relevant Parameters

Active

(a bank or more open)

On Fast tXP to any valid command.

Precharged

(all banks precharged)

On Fast tXP to any valid command.

The DLL is kept enabled during precharge power-down or active power-down. In pow-

er-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be main-

tained at the inputs of the device. ODT should be in a valid state, but all other input sig-

nals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out

of power-down mode and in the reset state.) CKE LOW must be maintained until tCKE

has been satisfied. Power-down duration is limited by 9 × tREFI.

The power-down state is synchronously exited when CKE is registered HIGH (along

with DES command). CKE HIGH must be maintained until tCKE has been satisfied. The

ODT input signal must be at a valid level when the device exits from power-down mode,

independent of MR1 bit [10:8] if RTT(NOM) is enabled in the mode register. If RTT(NOM) is

disabled, the ODT input signal may remain floating. A valid, executable command can

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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be applied with power-down exit latency, tXP, after CKE goes HIGH. Power-down exit la-

tency is defined in the AC Specifications table.

Figure 94: Active Power-Down Entry and Exit

CK_t

CK_c

Command DES DES DES DES DES

Address

CKE

Enter

power-down

mode

Exit

power-down

mode

tPD

Valid

tCPDED

Valid

ODT (ODT buffer enabled - MR5[5] = 0)2

tIH

tIS

T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0

DES

tXP

tCKE

Don’t Care

Time Break

ODT (ODT buffer disabled - MR5[5] = 1)3Refer to ODT Power-Down Entry/Exit

with ODT Buffer Disable Mode figures

Notes: 1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-

tion of the PRECHARGE command.

2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting).

3. ODT pin drive/float timing requirements for the ODT input buffer disable option (for ad-

ditional power savings during active power-down) is described in the section for ODT In-

put Buffer Disable Mode for Power-Down (page 169); MR5[5] = 1.

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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Figure 95: Power-Down Entry After Read and Read with Auto Precharge

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7

RL = AL + CL

Ta8 Tb0 Tb1

DES

Valid Valid

RD or

RDA DES DES DES DES DES DES DES DES DES DES Valid

Valid

CK_t

CK_c

Command

DQ BL8

DQ BC4

DQS_t, DQS_c

Address

CKE

tCPDED

tIS

tPD

tRDPDEN

Power-Down

entry

Transitioning Data Don’t Care

Time Break

b+3

b+2

b+1

n+3

n+2

n+1

b+7

b+6

b+5

b+4

Note: 1. DI n (or b) = data-in from column n (or b).

Figure 96: Power-Down Entry After Write and Write with Auto Precharge

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta 7

WL = AL + CWL

Tb0 Tb1 Tb2 Tc 0 Tc 1

Bank,

Col n

b + 3

b + 2

b + 1

bDI

b + 7

b + 6

b + 5

b + 4

DES

WRITE DES DES DES DES DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

DQ BL8

DQ BC4

DQS_t, DQS_c

Address

A10

CKE

tCPDED

tIS

tPD

tWRAPDEN

Power-Down

entry

Start internal

precharge

n + 3

n + 2

n + 1

Transitioning Data 'RQ¶W&DUH

7LPH%UHDN

Valid

Notes: 1. DI n (or b) = data-in from column n (or b).

2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-

tion of the PRECHARGE command.

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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Figure 97: Power-Down Entry After Write

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta 4 Ta5 Ta 6 Ta7

WL = AL + CWL

Tb0 Tb1 Tb2 Tc 0 Tc 1

Bank,

Col n

DES

WRITE DES DES DES DES DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

DQ BL8

DQ BC4

DQS_t, DQS_c

Address

A10

CKE

tWR

tCPDED

tIS

tPD

tWRPDEN

Power-Down

entry

Valid

Transitioning Data Don’t Care

Time Break

b + 3

b + 2

b + 1

bDI

b + 7

b + 6

b + 5

b + 4

n + 3

n + 2

n + 1

Note: 1. DI n (or b) = data-in from column n (or b).

Figure 98: Precharge Power-Down Entry and Exit

CK_t

CK_c

Command DES DES DESDES DES DES

CKE

Enter

power-down

mode

Exit

power-down

mode

tPD tXP

tCPDED

tIS

tIH

tIS

T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0

tCKE

Don’t Care

Time Break

Valid Valid

Valid

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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Figure 99: REFRESH Command to Power-Down Entry

CK_t

CK_c

Command REF DES DESDES

Address Valid

CKE

tREFPDEN

tCPDED

tCKE

T0 T1 T2 Ta0 Tb0 Tb1

tPD

Don’t Care

Time Break

Valid

tIS

DES

Figure 100: Active Command to Power-Down Entry

CK_t

CK_c

Command ACT DES DESDES

Address Valid

CKE

tACTPDEN

tCPDED

tCKE

tIS

T0 T1 T2 Ta0 Tb0 Tb1

tPD

Don’t Care

Time Break

Valid

DES

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

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Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry

CK_t

CK_c

Command PRE or

PREA DES DESDES Valid

Address Valid

CKE

tPREPDEN

tCPDED

T0 T1 T2 Ta0 Tb0 Tb1

tPD tCKE

Don’t Care

Time Break

tIS

Figure 102: MRS Command to Power-Down Entry

CK_t

CK_c

Command MRS DES DESDES

Address Valid

CKE

tMRSPDEN

tCPDED

T0 T1 Tb0 Tb1Ta0 Ta1

tPD tCKE

Don’t Care

Time Break

Valid

tIS

DES

Power-Down Clarifications – Case 1

When CKE is registered LOW for power-down entry, tPD (MIN) must be satisfied before

CKE can be registered HIGH for power-down exit. The minimum value of parameter

tPD (MIN) is equal to the minimum value of parameter tCKE (MIN) as shown in the

Timing Parameters by Speed Bin table. A detailed example of Case 1 follows.

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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Figure 103: Power-Down Entry/Exit Clarifications – Case 1

CK_t

CK_c

Command Valid DES DESDES DES

Address Valid

CKE

tCPDED

Enter

power-down

mode

Exit

power-down

mode

Enter

power-down

mode

tCPDED

T0 T1 T2 Ta0 Ta1

tPD tPD

Don’t Care

Time Break

Tb0 Tb1 Tb2

tIS tIS

tIH tIS tCKE

tIH

DES DES

Power-Down Entry, Exit Timing with CAL

Command/Address latency is used and additional timing restrictions are required when

entering power-down, as noted in the following figures.

Figure 104: Active Power-Down Entry and Exit Timing with CAL

&.BW

&.BF

&RPPDQG '(6 9DOLG '(6'(6 '(6

$GGUHVV

&.(

W3'

'(6

9DOLG

W&3'('

W&$/ W;3 W&$/

9DOLG

W,+

W,6

7 7 7D 7D 7D 7E 7E 7F 7F 7G 7G 7H

'RQ¶W&DUH

7LPH%UHDN

&6BQ

'(6 '(6 9DOLG'(6 '(6

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

CCMTD-1725822587-9875

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Figure 105: REFRESH Command to Power-Down Entry with CAL

&.BW

&.BF

&RPPDQG '(6 5() '(6'(6 '(6

$GGUHVV

&.(

W3'

'(6

9DOLG

W&3'('

W&$/ W5()3'(1 W;3 W&$/

9DOLG

W,+

W,6

7 7 7D 7 E  7 E  7F  7F 7G 7G 7H 7H 7I

'RQ¶W&DUH

7LPH%UHDN

&6BQ

'(6 '(6 9DOLG'(6 '(6

8Gb: x4, x8, x16 DDR4 SDRAM

Power-Down Mode

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ODT Input Buffer Disable Mode for Power-Down

DRAM does not provide RTT_NOM termination during power-down when ODT input

buffer deactivation mode is enabled in MR5 bit A5.

To account for DRAM internal delay on CKE line to disable the ODT buffer and block

the sampled output, the host controller must continuously drive ODT to either low or

high when entering power down (from tDODTLoff+1 prior to CKE low till tCPDED after

CKE low).

The ODT signal is allowed to float after tCPDEDmin has expired. In this mode, RTT_NOM

termination corresponding to sampled ODT at the input when CKE is registered low

(and tANPD before that) may be either RTT_NOM or RTT_PARK. tANPD is equal to (WL-1)

and is counted backwards from PDE.

Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode

diff_CK

tDODTLoff +1 tCPDED (MIN)

CKE

ODT Floating

DRAM_RTT_sync

(DLL enabled)

CA parity disabled

DRAM_RTT_async

(DLL disabled)

RTT(Park)

RTT(NOM)

tCPDED (MIN) + tADC (MAX)

tADC (MIN)

DODTLoff

RTT(Park)

RTT(NOM)

tAONAS (MIN)

tCPDED (MIN) + tAOFAS (MAX)

8Gb: x4, x8, x16 DDR4 SDRAM

ODT Input Buffer Disable Mode for Power-Down

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Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode

diff_CK

CKE

ODT_A

(DLL enabled) tADC (MAX)

tXP

Floating

DRAM_RTT_A RTT(Park) RTT(NOM)

tADC (MIN)

DODTLon

ODT_B

(DLL disabled) Floating

DRAM_RTT_B RTT(Park)

tAONAS (MIN)

tAOFAS (MAX)

RTT(NOM)

8Gb: x4, x8, x16 DDR4 SDRAM

ODT Input Buffer Disable Mode for Power-Down

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CRC Write Data Feature

CRC Write Data

The CRC write data feature takes the CRC generated data from the DRAM controller and

compares it to the internally CRC generated data and determines whether the two

match (no CRC error) or do not match (CRC error).

Figure 108: CRC Write Data Operation

Data

DRAM Controller DRAM

Data

CRC Code

CRC

Code

CRC

engine

Data

CRC Code

CRC

engine

Compare

CRC

WRITE CRC DATA Operation

A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the

write data frames, as shown in the following CRC data mapping tables for the x4, x8, and

x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the re-

maining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data

bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is

used (1s are sent when not used). A x16 device has two identical CRC trees each, one for

the lower byte and one for the upper byte, with 64 input data bits used by each, and the

remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s

are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must

send 1s in transfer 9 location whether or not DM_n/DBI_n is used.

The DRAM checks for an error in a received code word D[71:0] by comparing the re-

ceived checksum against the computed checksum and reports errors using the

ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core

without waiting for the CRC check for full writes when DM is disabled. If bad data is

written to the DRAM core, the DRAM memory controller will try to overwrite the bad

data with good data; this means the DRAM controller is responsible for data coherency

when DM is disabled. However, in the case where both CRC and DM are enabled via

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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MRS (that is, persistent mode), the DRAM will not write bad data to the core when a

CRC error is detected.

DBI_n and CRC Both Enabled

The DRAM computes the CRC for received written data D[71:0]. Data is not inverted

back based on DBI before it is used for computing CRC. The data is inverted back based

on DBI before it is written to the DRAM core.

DM_n and CRC Both Enabled

When both DM and write CRC are enabled in the DRAM mode register, the DRAM cal-

culates CRC before sending the write data into the array. If there is a CRC error, the

DRAM blocks the WRITE operation and discards the data. If a CRC error is encountered

from a WRITE with auto precharge (WRA), the DRAM will not block the precharge. The

Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or

Different Bank Group and the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and

Write CRC in Same or Different BankGroup figures in the WRITE Operation section

show timing differences when DM is enabled.

DM_n and DBI_n Conflict During Writes with CRC Enabled

Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and

DM_n can be enabled at the same time.

CRC and Write Preamble Restrictions

When write CRC is enabled:

• And 1tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 4 clocks is not

allowed.

• And 2tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 6 clocks is not

allowed.

CRC Simultaneous Operation Restrictions

When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed.

CRC Polynomial

The CRC polynomial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1.

A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data in-

cludes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees.

The CRC polynomial and combinatorial logic used by DDR4 is the same as used on

GDDR5.

The error coverage from the DDR4 polynomial used is shown in the following table.

Table 54: CRC Error Detection Coverage

Error Type Detection Capability

Random single-bit errors 100%

Random double-bit errors 100%

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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Table 54: CRC Error Detection Coverage (Continued)

Error Type Detection Capability

Random odd count errors 100%

Random multibit UI vertical column error

detection excluding DBI bits

100%

CRC Combinatorial Logic Equations

module CRC8_D72;

// polynomial: (0 1 2 8)

// data width: 72

// convention: the first serial data bit is D[71]

//initial condition all 0 implied

// "^" = XOR

function [7:0]

nextCRC8_D72;

input [71:0] Data;

input [71:0] D;

reg [7:0] CRC;

begin

D = Data;

CRC[0] =

D[69]^D[68]^D[67]^D[66]^D[64]^D[63]^D[60]^D[56]^D[54]^D[53]^D[52]^D[50]^D[49

]^D[48]^D[45]^D[43]^D[40]^D[39]^D[35]^D[34]^D[31]^D[30]^D[28]^D[23]^D[21]^D[1

9]^D[18]^D[16]^D[14]^D[12]^D[8]^D[7]^D[6]^D[0];

CRC[1] =

D[70]^D[66]^D[65]^D[63]^D[61]^D[60]^D[57]^D[56]^D[55]^D[52]^D[51]^D[48]^D[46

]^D[45]^D[44]^D[43]^D[41]^D[39]^D[36]^D[34]^D[32]^D[30]^D[29]^D[28]^D[24]^D[2

3]^D[22]^D[21]^D[20]^D[18]^D[17]^D[16]^D[15]^D[14]^D[13]^D[12]^D[9]^D[6]^D[1

]^D[0];

CRC[2] =

D[71]^D[69]^D[68]^D[63]^D[62]^D[61]^D[60]^D[58]^D[57]^D[54]^D[50]^D[48]^D[47

]^D[46]^D[44]^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[2

2]^D[17]^D[15]^D[13]^D[12]^D[10]^D[8]^D[6]^D[2]^D[1]^D[0];

CRC[3] =

D[70]^D[69]^D[64]^D[63]^D[62]^D[61]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47

]^D[45]^D[44]^D[43]^D[40]^D[38]^D[35]^D[34]^D[30]^D[29]^D[26]^D[25]^D[23]^D[1

8]^D[16]^D[14]^D[13]^D[11]^D[9]^D[7]^D[3]^D[2]^D[1];

CRC[4] =

D[71]^D[70]^D[65]^D[64]^D[63]^D[62]^D[60]^D[59]^D[56]^D[52]^D[50]^D[49]^D[48

]^D[46]^D[45]^D[44]^D[41]^D[39]^D[36]^D[35]^D[31]^D[30]^D[27]^D[26]^D[24]^D[1

9]^D[17]^D[15]^D[14]^D[12]^D[10]^D[8]^D[4]^D[3]^D[2];

CRC[5] =

D[71]^D[66]^D[65]^D[64]^D[63]^D[61]^D[60]^D[57]^D[53]^D[51]^D[50]^D[49]^D[47

]^D[46]^D[45]^D[42]^D[40]^D[37]^D[36]^D[32]^D[31]^D[28]^D[27]^D[25]^D[20]^D[1

8]^D[16]^D[15]^D[13]^D[11]^D[9]^D[5]^D[4]^D[3];

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

CCMTD-1725822587-9875

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CRC[6] =

D[67]^D[66]^D[65]^D[64]^D[62]^D[61]^D[58]^D[54]^D[52]^D[51]^D[50]^D[48]^D[47

]^D[46]^D[43]^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[26]^D[21]^D[19]^D[1

7]^D[16]^D[14]^D[12]^D[10]^D[6]^D[5]^D[4];

CRC[7] =

D[68]^D[67]^D[66]^D[65]^D[63]^D[62]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48

]^D[47]^D[44]^D[42]^D[39]^D[38]^D[34]^D[33]^D[30]^D[29]^D[27]^D[22]^D[20]^D[1

8]^D[17]^D[15]^D[13]^D[11]^D[7]^D[6]^D[5];

nextCRC8_D72 = CRC;

Burst Ordering for BL8

DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is ena-

bled in BL8 (fixed).

CRC Data Bit Mapping

Table 55: CRC Data Mapping for x4 Devices, BL8

Func-

tion

Transfer

0123456789

DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 CRC4

DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 CRC5

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 CRC6

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 CRC7

Table 56: CRC Data Mapping for x8 Devices, BL8

Func-

tion

Transfer

0123456789

DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1

DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

DM_n/

DBI_n

D64 D65 D66 D67 D68 D69 D70 D71 1 1

A x16 device is treated as two x8 devices; a x16 device will have two identical CRC trees

implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits

D[143:72].

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

CCMTD-1725822587-9875

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Table 57: CRC Data Mapping for x16 Devices, BL8

Func-

tion

Transfer

0 1 2 3 4 5 6 7 8 9

DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1

DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

LDM_n/

LDBI_n

D64 D65 D66 D67 D68 D69 D70 D71 1 1

DQ8 D72 D73 D74 D75 D76 D77 D78 D79 CRC8 1

DQ9 D80 D81 D82 D83 D84 D85 D86 D87 CRC9 1

DQ10 D88 D89 D90 D91 D92 D93 D94 D95 CRC10 1

DQ11 D96 D97 D98 D99 D100 D101 D102 D103 CRC11 1

DQ12 D104 D105 D106 D107 D108 D109 D110 D111 CRC12 1

DQ13 D112 D113 D114 D115 D116 D117 D118 D119 CRC13 1

DQ14 D120 D121 D122 D123 D124 D125 D126 D127 CRC14 1

DQ15 D128 D129 D130 D131 D132 D133 D134 D135 CRC15 1

UDM_n/

UDBI_n

D136 D137 D138 D139 D140 D141 D142 D143 1 1

CRC Enabled With BC4

If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data

first for BC4 writes.

CRC with BC4 Data Bit Mapping

For a x4 device, the CRC tree inputs are 16 data bits, and the inputs for the remaining

bits are 1.

When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to

D[11:8], and so forth, for the CRC tree.

Table 58: CRC Data Mapping for x4 Devices, BC4

Function

Transfer

0123456789

A2 = 0

DQ0 D0D1D2D31111CRC0 CRC4

DQ1 D8D9D10D111111CRC1 CRC5

DQ2 D16D17D18D191111CRC2 CRC6

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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Table 58: CRC Data Mapping for x4 Devices, BC4 (Continued)

Function

Transfer

0 1 2 3 4 5 6 7 8 9

DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 CRC7

A2 = 1

DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 CRC4

DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 CRC5

DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 CRC6

DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 CRC7

For a x8 device, the CRC tree inputs are 36 data bits.

When A2 = 0, the input bits D[67:64]) are used if DBI_n or DM_n functions are enabled;

if DBI_n and DM_n are disabled, then D[67:64]) are 1.

When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to

D[11:8], and so forth, for the CRC tree. The input bits D[71:68]) are used if DBI_n or

DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68]) are 1.

Table 59: CRC Data Mapping for x8 Devices, BC4

Function

Transfer

0 1 2 3 4 5 6 7 8 9

A2 = 0

DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1

DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1

DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1

DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1

DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1

DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1

DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1

DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1

DM_n/DBI_n D64 D65 D66 D67 1 1 1111

A2 = 1

DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1

DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1

DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1

DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1

DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1

DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1

DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1

DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1

DM_n/DBI_n D68 D69 D70 D71 1 1 1111

There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits.

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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When A2 = 0, input bits D[67:64] are used if DBI_n or DM_n functions are enabled; if

DBI_n and DM_n are disabled, then D[67:64] are 1s. The input bits D[139:136] are used

if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then

D[139:136] are 1s.

When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs

for D[11:8], and so forth, for the CRC tree. Input bits D[71:68] are used if DBI_n or DM_n

functions are enabled; if DBI_n and DM_n are disabled, then D[71:68] are 1s. The input

bits D[143:140] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n

are disabled, then D[143:140] are 1s.

Table 60: CRC Data Mapping for x16 Devices, BC4

Function

Transfer

0 1 2 3 4 5 6 7 8 9

A2 = 0

DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1

DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1

DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1

DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1

DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1

DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1

DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1

DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1

LDM_n/LDBI_n D64 D65 D66 D67 1 1 1111

DQ8 D72 D73 D74 D75 1 1 1 1 CRC8 1

DQ9 D80 D81 D82 D83 1 1 1 1 CRC9 1

DQ10 D88 D89 D90 D91 1 1 1 1 CRC10 1

DQ11 D96 D97 D98 D99 1 1 1 1 CRC11 1

DQ12 D104 D105 D106 D107 1 1 1 1 CRC12 1

DQ13 D112 D113 D114 D115 1 1 1 1 CRC13 1

DQ14 D120 D121 D122 D123 1 1 1 1 CRC14 1

DQ15 D128 D129 D130 D131 1 1 1 1 CRC15 1

UDM_n/UDBI_n D136 D137 D138 D139 1 1 1111

A2 = 1

DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1

DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1

DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1

DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1

DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1

DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1

DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1

DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1

LDM_n/LDBI_n D68 D69 D70 D71 1 1 1111

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

CCMTD-1725822587-9875

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Table 60: CRC Data Mapping for x16 Devices, BC4 (Continued)

Function

Transfer

0 1 2 3 4 5 6 7 8 9

DQ8 D76 D77 D78 D79 1 1 1 1 CRC8 1

DQ9 D84 D85 D86 D87 1 1 1 1 CRC9 1

DQ10 D92 D93 D94 D95 1 1 1 1 CRC10 1

DQ11 D100 D101 D102 D103 1 1 1 1 CRC11 1

DQ12 D108 D109 D110 D111 1 1 1 1 CRC12 1

DQ13 D116 D117 D118 D119 1 1 1 1 CRC13 1

DQ14 D124 D125 D126 D127 1 1 1 1 CRC14 1

DQ15 D132 D133 D134 D135 1 1 1 1 CRC15 1

UDM_n/UDBI_n D140 D141 D142 D143 1 1 1111

CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1

The following example is of a CRC tree when x8 is used in BC4 mode (x4 and x16 CRC

trees have similar differences).

CRC[0], A2=0 =

1^1^D[67]^D[66]^D[64]^1^1^D[56]^1^1^1^D[50]^D[49]^D[48]^1^D[43]^D[40]^1^D[3

5]^D[34]^1^1^1^1^1^D[19]^D[18]^D[16]^1^1^D[8] ^1^1^ D[0] ;

CRC[0], A2=1 =

1^1^D[71]^D[70]^D[68]^1^1^D[60]^1^1^1^D[54]^D[53]^D[52]^1^D[47]^D[44]^1^D[3

9]^D[38]^1^1^1^1^1^D[23]^D[22]^D[20]^1^1^D[12]^1^1^D[4] ;

CRC[1], A2=0 =

1^D[66]^D[65]^1^1^1^D[57]^D[56]^1^1^D[51]^D[48]^1^1^1^D[43]^D[41]^1^1^D[34

]^D[32]^1^1^1^D[24]^1^1^1^1^D[18]^D[17]^D[16]^1^1^1^1^D[9] ^1^ D[1]^D[0];

CRC[1], A2=1 =

1^D[70]^D[69]^1^1^1^D[61]^D[60]^1^1^D[55]^D[52]^1^1^1^D[47]^D[45]^1^1^D[38

]^D[36]^1^1^1^D[28]^1^1^1^1^D[22]^D[21]^D[20]^1^1^1^1^D[13]^1^D[5]^D[4];

CRC[2], A2=0 =

1^1^1^1^1^1^1^D[58]^D[57]^1^D[50]^D[48]^1^1^1^D[43]^D[42]^1^1^D[34]^D[33]^1

^1^D[25]^D[24]^1^D[17]^1^1^1^D[10]^D[8] ^1^D[2]^D[1]^D[0];

CRC[2], A2=1 =

1^1^1^1^1^1^1^D[62]^D[61]^1^D[54]^D[52]^1^1^1^D[47]^D[46]^1^1^D[38]^D[37]^1

^1^D[29]^D[28]^1^D[21]^1^1^1^D[14]^D12]^1^D[6]^D[5]^D[4];

CRC[3], A2=0 =

1^1^D[64]^1^1^1^D[59]^D[58]^1^D[51]^D[49]^D[48]^1^1^1^D[43]^D[40]^1^D[35]^

D[34]^1^1^D[26]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^D[3]^D[2]^D[1];

CRC[3], A2=1 =

1^1^D[68]^1^1^1^D[63]^D[62]^1^D[55]^D[53]^D[52]^1^1^1^D[47]^D[44]^1^D[39]^

D[38]^1^1^D[30]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^D[7]^D[6]^D[5];

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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CRC[4], A2=0 =

1^1^D[65]^D[64]^1^1^1^D[59]^D[56]^1^D[50]^D[49]^D[48]^1^1^1^D[41]^1^1^D[35

]^1^1^D[27]^D[26]^D[24]^D[19]^D[17]^1^1^1^D[10]^D[8] ^1^D[3]^D[2];

CRC[4], A2=1 =

1^1^D[69]^D[68]^1^1^1^D[63]^D[60]^1^D[54]^D[53]^D[52]^1^1^1^D[45]^1^1^D[39

]^1^1^D[31]^D[30]^D[28]^D[23]^D[21]^1^1^1^D[14]^D[12]^1^D[7]^D[6];

CRC[5], A2=0 =

1^D[66]^D[65]^D[64]^1^1^1^D[57]^1^D[51]^D[50]^D[49]^1^1^1^D[42]^D[40]^1^1^

D[32]^1^1^D[27]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^1^D[3];

CRC[5], A2=1 =

1^D[70]^D[69]^D[68]^1^1^1^D[61]^1^D[55]^D[54]^D[53]^1^1^1^D[46]^D[44]^1^1^

D[36]^1^1^D[31]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^1^D[7];

CRC[6], A2=0 =

D[67]^D[66]^D[65]^D[64]^1^1^D[58]^1^1^D[51]^D[50]^D[48]^1^1^D[43]^D[41]^1^1

^D[33]^D[32]^1^1^D[26]^1^D[19]^D[17]^D[16]^1^1^D[10]^1^1^1;

CRC[6], A2=1 =

D[71]^D[70]^D[69]^D[68]^1^1^D[62]^1^1^D[55]^D[54]^D[52]^1^1^D[47]^D[45]^1^1

^D[37]^D[36]^1^1^D[30]^1^D[23]^D[21]^D[20]^1^1^D[14]^1^1^1;

CRC[7], A2=0 =

1^D[67]^D[66]^D[65]^1^1^D[59]^1^1^1^D[51]^D[49]^D[48]^1^1^D[42]^1^1^D[34]^

D[33]^1^1^D[27]^1^1^D[18]^D[17]^1^1^D[11]^1^1^1;

CRC[7], A2=1 =

1^D[71]^D[70]^D[69]^1^1^D[63]^1^1^1^D[55]^D[53]^D[52]^1^1^D[46]^1^1^D[38]^

D[37]^1^1^D[31]^1^1^D[22]^D[21]^1^1^D[15]^1^1^1;

CRC Error Handling

The CRC error mechanism shares the same ALERT_n signal as CA parity for reporting

write errors to the DRAM. The controller has two ways to distinguish between CRC er-

rors and CA parity errors: 1) Read DRAM mode/MPR registers, and 2) Measure time

ALERT_n is LOW. To speed up recovery for CRC errors, CRC errors are only sent back as

a "short" pulse; the maximum pulse width is roughly ten clocks (unlike CA parity where

ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the

maximum limit at the controller if there are multiple CRC errors as the ALERT_n signals

are connected by a daisy chain bus. The latency to ALERT_n signal is defined as

tCRC_ALERT in the following figure.

The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC

error, which will subsequently set the CRC error status flag in the MPR error log HIGH

(MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) remains set

at 1 until the DRAM controller clears the CRC error status bit using an MRS command

to set MR5[3] to a 0. The DRAM controller, upon seeing an error as a pulse width, will

retry the write transactions. The controller should consider the worst-case delay for

ALERT_n (during initialization) and backup the transactions accordingly. The DRAM

controller may also be made more intelligent and correlate the write CRC error to a spe-

cific rank or a transaction.

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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Figure 109: CRC Error Reporting

T0 T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Tb0

CK_t

CK_c

DQIN Dx+1 Dx+2 Dx+3 Dx+4 Dx+5 Dx+6 Dx+7 CRCy 1

ALERT_n CRC ALERT_PW (MIN)

Tb1

tCRC_ALERT

CRC ALERT_PW (MAX)

Don’t CareTransition Data

Notes: 1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generat-

ing process at T6.

2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal

LOW to the point where the DRAM driver releases and the controller starts to pull the

signal up.

3. Timing diagram applies to x4, x8, and x16 devices.

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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CRC Write Data Flow Diagram

Figure 110: CA Parity Flow Diagram

Capture data

Transfer Data

Internally

Transfer data

internally

Yes

DRAM write

process start MR2 12 enable CRC

MR5 3 set CRC error clear to 0

MR5 10 enable/disable DM

MR3[10:9] WCL if DM enabled

Yes

ALERT_n LOW

6 to 10 CKs

ALERT_n HIGH Set error status

PAGE1 MPR3[7] 1

Set error flag

MR5[A3] 1

Transfer data

internally

Yes

CRC

enabled

CA error

Persistent

mode

enabled

MR5[A3] and

PAGE1 MPR3[7]

remain set to 1

Yes

DRAM

CRC same as

controller

CRC

DRAM

CRC same as

controller

CRC

MR5[3] = 0

at WRITE

WRITE burst

completed

WRITE burst

completed

WRITE burst

completed

WRITE burst

completed

WRITE burst

completed

Bad data written

MR5 3 reset to 0 if desired

ALERT_n LOW

6 to 10 CKs

ALERT_n HIGH Set error status

PAGE1 MPR3[7] 1

Set error flag

MR5[A3] 1

Yes

MR5[A3] and

PAGE1 MPR3[7]

remain set to 1

MR5[3] = 0

at WRITE

WRITE burst

rejected

Bad data not written

MR5 3 reset to 0 if desired

8Gb: x4, x8, x16 DDR4 SDRAM

CRC Write Data Feature

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Data Bus Inversion

The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configura-

tions (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in

conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given

DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM)

and TDQS functions. The DBI function applies to either or both READ and WRITE oper-

ations: Write DBI cannot be enabled at the same time the DM function is enabled, and

DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM,

and DBI functions are shown below.

Table 61: DBI vs. DM vs. TDQS Function Matrix

Read DBI Write DBI Data Mask (DM) TDQS (x8 only)

Enabled (or Disabled)

MR5[12]=1 (or

MR5[12] = 0)

Disabled

MR5[11] = 0

Disabled

MR5[10] = 0

Disabled

MR1[11] = 0

Enabled

MR5[11] = 1

Disabled

MR5[10] = 0

Disabled

MR1[11] = 0

Disabled

MR5[11] = 0

Enabled

MR5[10] = 1

Disabled

MR1[11] = 0

Disabled

MR5[12] = 0

Disabled

MR5[11] = 0

Disabled

MR5[10] = 0

Enabled

MR1[11] = 1

DBI During a WRITE Operation

If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM in-

verts write data received on the DQ inputs prior to writing the internal memory array. If

DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the

DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 con-

figurations (the x4 configuration does not support the DBI function).

Table 62: DBI Write, DQ Frame Format (x8)

Function

Transfer

0 1 2 3 4 5 6 7

DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

DM_n or

DBI_n

DM0 or

DBI0

DM1 or

DBI1

DM2 or

DBI2

DM3 or

DBI3

DM4 or

DBI4

DM5 or

DBI5

DM6 or

DBI6

DM7 or

DBI7

Table 63: DBI Write, DQ Frame Format (x16)

Function

Transfer, Lower (L) and Upper(U)

0 1 2 3 4 5 6 7

DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7

LDM_n or

LDBI_n

LDM0 or

LDBI0

LDM1 or

LDBI1

LDM2 or

LDBI2

LDM3 or

LDBI3

LDM4 or

LDBI4

LDM5 or

LDBI5

LDM6 or

LDBI6

LDM7 or

LDBI7

DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7

8Gb: x4, x8, x16 DDR4 SDRAM

Data Bus Inversion

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Table 63: DBI Write, DQ Frame Format (x16) (Continued)

Function

Transfer, Lower (L) and Upper(U)

0 1 2 3 4 5 6 7

UDM_n or

UDBI_n

UDM0 or

UDBI0

UDM1 or

UDBI1

UDM2 or

UDBI2

UDM3 or

UDBI3

UDM4 or

UDBI4

UDM5 or

UDBI5

UDM6 or

UDBI6

UDM7 or

UDBI7

DBI During a READ Operation

If the number of 0 data bits within a given byte lane is greater than four during a READ

operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin

LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin

HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4

configuration does not support the DBI function).

Table 64: DBI Read, DQ Frame Format (x8)

Function

Transfer Byte

0 1 2 3 4 5 6 7

DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

DBI_n DBI0 DBI1 DBI2 DBI3 DBI4 DBI5 DBI6 DBI7

Table 65: DBI Read, DQ Frame Format (x16)

Function

Transfer Byte, Lower (L) and Upper(U)

0 1 2 3 4 5 6 7

DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7

LDBI_n LDBI0 LDBI1 LDBI2 LDBI3 LDBI4 LDBI5 LDBI6 LDBI7

DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7

UDBI_n UDBI0 UDBI1 UDBI2 UDBI3 UDBI4 UDBI5 UDBI6 UDBI7

8Gb: x4, x8, x16 DDR4 SDRAM

Data Bus Inversion

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Data Mask

The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only

for x8 and x16 configurations (it is not supported on x4 devices). The DM function

shares a common pin with the DBI_n and TDQS functions. The DM function applies

only to WRITE operations and cannot be enabled at the same time the WRITE DBI

function is enabled. The valid configurations for the TDQS, DM, and DBI functions are

shown here.

Table 66: DM vs. TDQS vs. DBI Function Matrix

Data Mask (DM) TDQS (x8 only) Write DBI Read DBI

Enabled

MR5[10] = 1

Disabled

MR1[11] = 0

Disabled

MR5[11] = 0

Enabled or Disabled

MR5[12] = 1 or

MR5[12] = 0

Disabled

MR5[10] = 0

Enabled

MR1[11] = 1

Disabled

MR5[11] = 0

Disabled

MR5[12] = 0

Disabled

MR1[11] = 0

Enabled

MR5[11] = 1

Enabled or Disabled

MR5[12] = 1 or

MR5[12] = 0

Disabled

MR1[11] = 0

Disabled

MR5[11] = 0

Enabled (or Disabled)

MR5[12] = 1 (or

MR5[12] = 0)

When enabled, the DM function applies during a WRITE operation. If DM_n is sampled

LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. If

DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and

writes this data into the DRAM core. The DQ frame format for x8 and x16 configurations

is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be

checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error

occurs while the DM feature is enabled, CRC write persistent mode will be enabled and

data will not be written into the DRAM core. In the case of CRC write enabled and DM

disabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAM

core even if a CRC error occurs.

Table 67: Data Mask, DQ Frame Format (x8)

Function

Transfer

0 1 2 3 4 5 6 7

DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

DM_n or

DBI_n

DM0 or

DBI0

DM1 or

DBI1

DM2 or

DBI2

DM3 or

DBI3

DM4 or

DBI4

DM5 or

DBI5

DM6 or

DBI6

DM7 or

DBI7

Table 68: Data Mask, DQ Frame Format (x16)

Function

Transfer, Lower (L) and Upper (U)

0 1 2 3 4 5 6 7

DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7

8Gb: x4, x8, x16 DDR4 SDRAM

Data Mask

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Table 68: Data Mask, DQ Frame Format (x16) (Continued)

Function

Transfer, Lower (L) and Upper (U)

0 1 2 3 4 5 6 7

LDM_n or

LDBI_n

LDM0 or

LDBI0

LDM1 or

LDBI1

LDM2 or

LDBI2

LDM3 or

LDBI3

LDM4 or

LDBI4

LDM5 or

LDBI5

LDM6 or

LDBI6

LDM7 or

LDBI7

DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7

UDM_n or

UDBI_n

UDM0 or

UDBI0

UDM1 or

UDBI1

UDM2 or

UDBI2

UDM3 or

UDBI3

UDM4 or

UDBI4

UDM5 or

UDBI5

UDM6 or

UDBI6

UDM7 or

UDBI7

8Gb: x4, x8, x16 DDR4 SDRAM

Data Mask

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Programmable Preamble Modes and DQS Postambles

The device supports programmable WRITE and READ preamble modes, either the nor-

mal 1tCK preamble mode or special 2tCK preamble mode. The 2tCK preamble mode

places special timing constraints on many operational features as well as being suppor-

ted for data rates of DDR4-2400 and faster. The WRITE preamble 1tCK or 2tCK mode

can be selected independently from READ preamble 1tCK or 2tCK mode.

READ preamble training is also supported; this mode can be used by the DRAM con-

troller to train or "read level" the DQS receivers.

There are tCCD restrictions under some circumstances:

• When 2tCK READ preamble mode is enabled, a tCCD_S or tCCD_L of 5 clocks is not

allowed.

• When 2tCK WRITE preamble mode is enabled and write CRC is not enabled, a tCCD_S

or tCCD_L of 5 clocks is not allowed.

• When 2tCK WRITE preamble mode is enabled and write CRC is enabled, a tCCD_S or

tCCD_L of 6 clocks is not allowed.

WRITE Preamble Mode

MR4[12] = 0 selects 1tCK WRITE preamble mode while MR4[12] = 1 selects 2tCK WRITE

preamble mode. Examples are shown in the figures below.

Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode

CK_c

CK_t

Preamble

2tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

DQS_t,

DQS_c

DQS_t,

DQS_c

CK_c

CK_t

Preamble

1tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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CWL has special considerations when in the 2tCK WRITE preamble mode. The CWL val-

ue selected in MR2[5:3], as seen in table below, requires at least one additional clock

when the primary CWL value and 2tCK WRITE preamble mode are used; no additional

clocks are required when the alternate CWL value and 2tCK WRITE preamble mode are

used.

Table 69: CWL Selection

CWL - Primary Choice CWL - Alternate Choice

Speed Bin 1tCK Preamble 2tCK Preamble 1tCK Preamble 2tCK Preamble

DDR4-1600 9 N/A 11 N/A

DDR4-1866 10 N/A 12 N/A

DDR4-2133 11 N/A 14 N/A

DDR4-2400 12 14 16 16

DDR4-2666 14 16 18 18

DDR4-2933 16 18 20 20

DDR4-3200 16 18 20 20

Note: 1. CWL programmable requirement for MR2[5:3].

When operating in 2tCK WRITE preamble mode, tWTR (command based) and tWR

(MR0[11:9]) must be programmed to a value 1 clock greater than the tWTR and tWR set-

ting normally required for the applicable speed bin to be JEDEC compliant; however,

Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The

CAS_n-to-CAS_n command delay to either a different bank group (tCCD_S) or the same

bank group (tCCD_L) have minimum timing requirements that must be satisfied be-

tween WRITE commands and are stated in the Timing Parameters by Speed Bin tables.

Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4

DQS_t,

DQS_c

tCCD = 4 WL

Preamble

1tCK Mode

D0 D1

WRITE WRITE

D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

CK_t

CK_c

CMD

DQS_t,

DQS_c

tCCD = 4 WL

Preamble

2tCK Mode

D0 D1

WRITE WRITE

D2 D3 D4 D5 D6 D7 D0 D1

CK_t

CK_c

CMD

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5

DQS_t,

DQS_c

tCCD = 5 WL

Preamble

1tCK Mode

D0 D1

WRITEWRITE

D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

CK_t

CK_c

CMD

2tCK Mode: tCCD = 5 is not allowed in 2tCK mode.

Note: 1. tCCD_S and tCCD_L = 5 tCKs is not allowed when in 2tCK WRITE preamble mode.

Figure 114: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6

tCCD = 6

DQS_t,

DQS_c

Preamble

1tCK Mode

D0 D1

WRITEWRITE

D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

CK_t

CK_c

CMD

2tCK Mode

tCCD = 6

DQS_t,

DQS_c

Preamble

D0 D1

WRITEWRITE

D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

CK_t

CK_c

CMD

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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READ Preamble Mode

MR4[11] = 0 selects 1tCK READ preamble mode and MR4[11] = 1 selects 2tCK READ pre-

amble mode. Examples are shown in the following figure.

Figure 115: 1tCK vs. 2tCK READ Preamble Mode

DQS_t,

DQS_c

DQS_t,

DQS_c

CK_c

CK_t

Preamble

2tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

CK_c

CK_t

Preamble

1tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

READ Preamble Training

DDR4 supports READ preamble training via MPR reads; that is, READ preamble train-

ing is allowed only when the DRAM is in the MPR access mode. The READ preamble

training mode can be used by the DRAM controller to train or "read level" its DQS re-

ceivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is ena-

bled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ

preamble training, the DRAM DQS signals are driven to a valid level by the time tSDO is

satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH.

The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until

an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pat-

tern is used), and when CAS latency (CL) has expired, the DQS signals will toggle nor-

mally depending on the burst length setting. To exit READ preamble training mode, an

MRS command must be issued, MR4[10] = 0.

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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Figure 116: READ Preamble Training

CMD

DQs

DQS_t

DQS_c,

tSDO

MPR RD

(Quiet/Driven HIGH)

MRS

D0 D1 D2 D3 D4 D5 D6 D7

WRITE Postamble

Whether the 1tCK or 2tCK WRITE preamble mode is selected, the WRITE postamble re-

mains the same at ½tCK.

Figure 117: WRITE Postamble

DQS_t,

DQS_c

DQS_t,

DQS_c

CK_c

CK_t

2tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

CK_c

CK_t

Postamble

1tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

Postamble

READ Postamble

Whether the 1tCK or 2tCK READ preamble mode is selected, the READ postamble re-

mains the same at ½tCK.

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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Figure 118: READ Postamble

CK_c

CK_t

2tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

DQS_t,

DQS_c

DQS_t,

DQS_c

CK_c

CK_t

1tCK Mode

D0 D1 D2 D3 D4 D5 D6 D7

Postamble

8Gb: x4, x8, x16 DDR4 SDRAM

Programmable Preamble Modes and DQS Postambles

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Bank Access Operation

DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and

each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank

groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to

different banks' groups require less time delay between accesses than bank accesses to

within the same bank's group. Bank accesses to different bank groups require tCCD_S

(or short) delay between commands while bank accesses within the same bank group

require tCCD_L (or long) delay between commands.

Figure 119: Bank Group x4/x8 Block Diagram

Local I/O gating

Global I/O gating

Bank 0

Memory Array

Sense amplifiers

Bank 1

Bank 2

Bank 3

Local I/O gating

Bank 0

Memory Array

Sense amplifiers

Bank 1

Bank 2

Bank 3

Local I/O gating

Bank 0

Memory Array

Sense amplifiers

Bank 1

Bank 2

Bank 3

Local I/O gating

Bank 0

Memory Array

Sense amplifiers

Bank 1

Bank 2

Bank 3

CMD/ADDR

Data I/O

Bank Group 0 Bank Group 1 Bank Group 2 Bank Group 3

Notes: 1. Bank accesses to different bank groups require tCCD_S.

2. Bank accesses within the same bank group require tCCD_L.

Table 70: DDR4 Bank Group Timing Examples

Parameter DDR4-1600 DDR4-2133 DDR4-2400

tCCD_S 4nCK 4nCK 4nCK

tCCD_L 4nCK or 6.25ns 4nCK or 5.355ns 4nCK or 5ns

tRRD_S (½K) 4nCK or 5ns 4nCK or 3.7ns 4nCK or 3.3ns

tRRD_L (½K) 4nCK or 6ns 4nCK or 5.3ns 4nCK or 4.9ns

tRRD_S (1K) 4nCK or 5ns 4nCK or 3.7ns 4nCK or 3.3ns

tRRD_L (1K) 4nCK or 6ns 4nCK or 5.3ns 4nCK or 4.9ns

tRRD_S (2K) 4nCK or 6ns 4nCK or 5.3ns 4nCK or 5.3ns

tRRD_L (2K) 4nCK or 7.5ns 4nCK or 6.4ns 4nCK or 6.4ns

8Gb: x4, x8, x16 DDR4 SDRAM

Bank Access Operation

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Table 70: DDR4 Bank Group Timing Examples (Continued)

Parameter DDR4-1600 DDR4-2133 DDR4-2400

tWTR_S 2nCK or 2.5ns 2nCK or 2.5ns 2nCK or 2.5ns

tWTR_L 4nCK or 7.5ns 4nCK or 7.5ns 4nCK or 7.5ns

Notes: 1. Refer to Timing Tables for actual specification values, these values are shown for refer-

ence only and are not verified for accuracy.

2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the

two cases must be satisfied.

Figure 120: READ Burst tCCD_S and tCCD_L Examples

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tCCD_S

T10 T11

Don’t Care

BG a

DES

READ READ

DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

Bank Group

(BG)

Bank c

Bank

Col n

BG b

Bank c

Col n

BG b

Bank c

Col n

Address

tCCD_L

READ

Notes: 1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank

groups (T0 to T4).

2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank

group (T4 to T10).

Figure 121: Write Burst tCCD_S and tCCD_L Examples

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tCCD_S

T10 T11

Don’t Care

BG a

DES

WRITE WRITE

DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

Bank Group

(BG)

Bank c

Bank

Col n

BG b

Bank c

Col n

BG b

Bank c

Col n

Address

tCCD_L

WRITE

Notes: 1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank

groups (T0 to T4).

2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank

group (T4 to T10).

8Gb: x4, x8, x16 DDR4 SDRAM

Bank Access Operation

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Figure 122: tRRD Timing

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tRRD_S

T10 T11

Don’t Care

BG a

DES

ACT ACT

DES DES DES DES DES DES DES DES

CK_t

CK_c

Command

Bank

Group

(BG)

Bank c

Bank

Row n

BG b

Bank c

Row n

BG b

Bank d

Row n

Address

tRRD_L

ACT

Notes: 1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI-

VATE commands to different bank groups (T0 and T4).

2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI-

VATE commands to the different banks in the same bank group (T4 and T10).

Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)

T0 Tb0T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7

Valid Valid Valid Valid Valid READ ValidCommand ValidWRITE Valid Valid Valid Valid

BGb

Bank

Group BGa

Bank c

Bank

Col n

Bank c

Col n

Address

CK_t

CK_c

Tb1

Don’t Care

Transitioning DataTime Break

tWPRE tWPST

tWTR_S

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

n + 2

n + 1

DQS, DQS_c

Note: 1. tWTR_S: delay from start of internal write transaction to internal READ command to a

different bank group.

8Gb: x4, x8, x16 DDR4 SDRAM

Bank Access Operation

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Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)

T0 Tb0T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7

Valid Valid Valid Valid Valid READ ValidCommand ValidWRITE Valid Valid Valid Valid

BGa

Bank

Group BGa

Bank c

Bank

Col n

Bank c

Col n

Address

CK_t

CK_c

Tb1

Don’t Care

Transitioning DataTime Break

tWPRE tWPST

tWTR_L

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

n + 2

n + 1

DQS, DQS_c

Note: 1. tWTR_L: delay from start of internal write transaction to internal READ command to the

same bank group.

8Gb: x4, x8, x16 DDR4 SDRAM

Bank Access Operation

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READ Operation

Read Timing Definitions

The read timings shown below are applicable in normal operation mode, that is, when

the DLL is enabled and locked.

Note: tDQSQ = both rising/falling edges of DQS; no tAC defined.

Rising data strobe edge parameters:

•tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-

tive to CK.

•tDQSCK is the actual position of a rising strobe edge relative to CK.

•tQSH describes the DQS differential output HIGH time.

•tDQSQ describes the latest valid transition of the associated DQ pins.

•tQH describes the earliest invalid transition of the associated DQ pins.

Falling data strobe edge parameters:

•tQSL describes the DQS differential output LOW time.

•tDQSQ describes the latest valid transition of the associated DQ pins.

•tQH describes the earliest invalid transition of the associated DQ pins.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 125: Read Timing Definition

CK_t

CK_c

DQS_c

DQS_t

tDQSCK tDQSCK

tDQSQ

Rising strobe

region

window

Rising strobe

region

window

tQSH/DQS_c tQSH/DQS_t

tQH tQH

tDQSCK (MAX)

tDQSCK (MIN) tDQSCK (MAX)

tDQSCK (MIN)

Associated

DQ Pins

tDQSCKi

tDQSCK MIN

tDQSCKi

Rising strobe

region

window

Rising strobe

region

window

tDQSCKi

tDQSCK center

tDQSCKi

Rising strobe

region

window

Rising strobe

region

window

tDQSCKi

tDQSCK MAX

tDQSCKi

Table 71: Read-to-Write and Write-to-Read Command Intervals

Access Type Bank Group Timing Parameters Note

Read-to-Write, mini-

mum

Same CL - CWL + RBL/2 + 1tCK + tWPRE 1, 2

Different CL - CWL + RBL/2 + 1tCK + tWPRE 1, 2

Write-to-Read, mini-

mum

Same CWL + WBL/2 + tWTR_L 1, 3

Different CWL + WBL/2 + tWTR_S 1, 3

Notes: 1. These timings require extended calibrations times tZQinit and tZQCS.

2. RBL: READ burst length associated with READ command, RBL = 8 for fixed 8 and on-the-

fly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4.

3. WBL: WRITE burst length associated with WRITE command, WBL = 8 for fixed 8 and on-

the-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only.

Read Timing – Clock-to-Data Strobe Relationship

The clock-to-data strobe relationship shown below is applicable in normal operation

mode, that is, when the DLL is enabled and locked.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Rising data strobe edge parameters:

•tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-

tive to CK.

•tDQSCK is the actual position of a rising strobe edge relative to CK.

•tQSH describes the data strobe high pulse width.

•tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section

of the figure below).

Falling data strobe edge parameters:

•tQSL describes the data strobe low pulse width.

•tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section

of the figure below).

Figure 126: Clock-to-Data Strobe Relationship

RL measured

to this point

DQS_t, DQS_c

Early Strobe

CK_t

CK_c

tLZ(DQS) MIN

tLZ(DQS) MAX

DQS_t, DQS_c

Late Strobe

tDQSCK (MIN)

tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX)

tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN)

tHZ(DQS) MIN

tHZ(DQS) MAX

tRPRE

tQSH tQSL

tQSH tQSL tQSH tQSL

Bit 0 Bit 1 Bit 2 Bit 7Bit 6Bit 4Bit 3 Bit 5

tRPST

Notes: 1. Within a burst, the rising strobe edge will vary within tDQSCKi while at the same volt-

age and temperature. However, when the device, voltage, and temperature variations

are incorporated, the rising strobe edge variance window can shift between tDQSCK

(MIN) and tDQSCK (MAX).

A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a devi-

ce's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from ris-

ing CK_t, CK_c is limited by tDQSCK (MIN).

2. Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be im-

mediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other

timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH

(MIN) + tQSL (MIN)) - | tDQSCK(n + 1) |.

3. The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t,

DQS_c differential output LOW time is defined by tQSL.

4. tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and

tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case).

5. The minimum pulse width of READ preamble is defined by tRPRE (MIN).

6. The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left

side and tHZDSQ (MAX) on the right side.

7. The minimum pulse width of READ postamble is defined by tRPST (MIN).

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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8. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK

(MAX) on the right side.

Read Timing – Data Strobe-to-Data Relationship

The data strobe-to-data relationship is shown below and is applied when the DLL is en-

abled and locked.

Note: tDQSQ: both rising/falling edges of DQS; no tAC defined.

Rising data strobe edge parameters:

•tDQSQ describes the latest valid transition of the associated DQ pins.

•tQH describes the earliest invalid transition of the associated DQ pins.

Falling data strobe edge parameters:

•tDQSQ describes the latest valid transition of the associated DQ pins.

•tQH describes the earliest invalid transition of the associated DQ pins.

Data valid window parameters:

•tDVWd is the Data Valid Window per device per UI and is derived from [tQH - tDQSQ]

of each UI on a given DRAM

•tDVWp is the Data Valid Window per pin per UI and is derived [tQH - tDQSQ] of each

UI on a pin of a given DRAM

Figure 127: Data Strobe-to-Data Relationship

CK_t

CK_c

Command

3READ

Bank,

Col n

DES DES DES DES DES DES DES DES DES DES

Address

DQS_t, DQS_c

(Last data )

(First data no longer)

All DQ collectively

RL = AL + CL

tDQSQ (MAX)

tRPRE (1nCK)

tRPST

tQH tQH

tDVWp

tDVWd tDVWd

T0 T1 T2 T9 T10 T11 T12 T13

Don’t Care

T14 T15 T16

DOUT

n + 2

DOUT

n + 1

DOUT

n + 4

DOUT

n + 5

DOUT

n + 6

DOUT

n + 7

DOUT

n + 2

DOUT

n + 1

DOUT

n + 3

DOUT

n + 4

DOUT

n + 5

DOUT

n + 6

DOUT

n + 7

tDQSQ (MAX)

DOUT

n + 2

DOUT

n + 1

DOUT

n + 3

DOUT

n + 4

DOUT

n + 5

DOUT

n + 6

DOUT

n + 7

DOUT

n + 3

DOUT

Notes: 1. BL = 8, RL = 11 (AL = 0, CL = 1), Premable = 1tCK.

2. DOUTn = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during

READ commands at T0.

5. Output timings are referenced to VDDQ, and DLL on for locking.

6. tDQSQ defines the skew between DQS to data and does not define DQS to clock.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ

can vary (either early or late) within a burst.

tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations

tHZ and tLZ transitions occur in the same time window as valid data transitions. These

parameters are referenced to a specific voltage level that specifies when the device out-

put is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and

tLZ(DQ). The figure below shows a method to calculate the point when the device is no

longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by

measuring the signal at two different voltages. The actual voltage measurement points

are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS),

and tHZ(DQ) are defined as singled-ended parameters.

Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints

CK_t

CK_c

tLZ tHZ

0.7 × VDDQ

0.4 × VDDQ

Begin point:

Extrapolated point at VDDQ

VDDQ

VSW2

Begin point: Extrapolated point (low level)

VDDQ

tLZ(DQ): CK_t, CK_c rising crossing at RL tHZ(DQ) with BL8: CK_t, CK_c rising crossing at RL + 4CK

tHZ(DQ) with BC4: CK_t, CK_c rising crossing at RL + 2CK

VSW1

VSW2

VSW1

0.7 × VDDQ

0.4 × VDDQ

Notes: 1. Vsw1 = (0.70 - 0.04) × VDDQ for both tLZ and tHZ.

2. Vsw2 = (0.70 + 0.04) × VDDQ for both tLZ and tHZ.

3. Extrapolated point (low level) = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ

Driver impedance = RZQ/7 = 34˖

VTT test load = 50˖ to VDDQ.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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tRPRE Calculation

Figure 129: tRPRE Method for Calculating Transitions and Endpoints

DQS_t

CK_t

CK_c

Resulting differential signal relevant for

tRPRE specification

Single-ended signal provided as background information

DQS_c

DQS_t, DQS_c

DQS_t

DQS_c

DQS_t

DQS_c

VSW1

VSW2

0.7 × V

DDQ

0.7 × V

DDQ

0.4 × V

DDQ

0.4 × V

DDQ

VDDQ

0.7 × V

DDQ

0.3 × V

DDQ

0.6 × V

DDQ

0.4 × V

DDQ

VDD

tRPRE begins (t1) tRPRE ends (t2)

Notes: 1. Vsw1 = (0.3 - 0.04) × VDDQ.

2. Vsw2 = (0.30 + 0.04) × VDDQ.

3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ

Driver impedance = RZQ/7 = 34˖

VTT test load = 50˖ to VDDQ.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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tRPST Calculation

Figure 130: tRPST Method for Calculating Transitions and Endpoints

DQS_t, DQS_c

VSW1

VSW2

DQS_t

tRPST ends (

t2)

CK_t

CK_c

Resulting differential signal relevant for

tRPST specification

Single-ended signal provided as background information

DQS_c

DQS_t

DQS_c

tRPST begins (

t1)

0.7 × V

DDQ

0.7 × V

DDQ

0.4 × V

DDQ

0.4 × V

DDQ

VDDQ

0.7 × V

DDQ

–0.3 × V

DDQ

–0.6 × V

DDQ

VDD

Notes: 1. Vsw1 = (–0.3 - 0.04) × VDDQ.

2. Vsw2 = (–0.30 + 0.04) × VDDQ.

3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ

Driver impedance = RZQ/7 = 34˖

VTT test load = 50˖ to VDDQ.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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READ Burst Operation

DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-

the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:

• A12 = 0, BC4 (BC4 = burst chop)

• A12 = 1, BL8

READ commands can issue precharge automatically with a READ with auto precharge

command (RDA), and is enabled by A10 HIGH:

• READ command with A10 = 0 (RD) performs standard read, bank remains active after

READ burst.

• READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in

to precharge after READ burst.

Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)

CL = 11

RL = AL + CL

tRPRE

T1 T2 Ta1

Ta0 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9

DES DES DES DES DES DESCommand DESREAD DES DES

DES DES DES

CK_t

CK_c

Don’t CareTransitioning DataTime Break

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

n + 2

n + 1

Bank Group

Address

DQS_t

DQS_c

BGa

Address

Bank

col n

tRPST

Notes: 1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1tCK.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

command at T0.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)

CL = 11AL = 10

RL = AL + CL

tRPRE

T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6

DES DES DES DES DESCommand DESREAD DES DES DES DES

CK_t

CK_c

Don’t CareTransitioning Data

Time Break

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

n + 2

n + 1

Bank Group

Address

DQS_t

DQS_c

BGa

Address

Bank

col n

tRPST

DESDES

Notes: 1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1tCK.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

command at T0.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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READ Operation Followed by Another READ Operation

Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 1tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 2tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group

tCCD_S/L = 5

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES DES READ

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 1tCK, tCCD_S/L = 5.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and T5.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group

tCCD_S/L = 6

tRPRE

RL = 11

tRPST

T16T1 T2 T5 T6 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t CareTransitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGa or

BGb

Address Bank

Col n Bank

Col b

tRPRE

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 2tCK, tCCD_S/L = 6.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during

READ commands at T0 and T6.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

6. 6 tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

bDO

b + 1 DO

b + 2 DO

b + 3

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

tRPRE

tRPST

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 1tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ

commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

bDO

b + 1 DO

b + 2 DO

b + 3

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

tRPRE

Notes: 1. BL8, AL = 0, CL = 11, Preamble = 2tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ

commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

Notes: 1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4

setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

tRPST

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 1 DO

b + 2 DO

b + 3

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

Notes: 1. BL = 8, AL =0, CL = 11, Preamble = 2tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4

setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T20 T21T14T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGb

tRPRE tRPST

tRPST

BGa

Notes: 1. BL = 8, AL =0, CL = 11, Preamble = 1tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8

setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T20 T21T14T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

bDO

b + 1 DO

b + 2 DO

b + 3 DO

b + 4 DO

b + 5 DO

b + 6 DO

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGb

tRPST

BGa

Notes: 1. BL = 8, AL = 0, CL = 11, Preamble = 2tCK.

2. DO n (or b) = data-out from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8

setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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READ Operation Followed by WRITE Operation

Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 4 Clocks

tRPRE

RL = 11

tRPST

T1 T7 T8 T9

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T22T16T10 T11 T12 T13 T14 T15 T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE

preamble = 1tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and WRITE commands at T8.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 3 tCK 4 Clocks

tRPRE

RL = 11

tRPST

T1 T7 T8 T9

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 10

T22T16T10 T11 T12 T13 T14 T15 T21T17 T18 T19 T20

Don’t CareTransitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9+1 [see Note

5], AL = 0), WRITE preamble = 2tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and WRITE commands at T8.

5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank

Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 4 Clocks

tRPRE

RL = 11

tRPST

T1 T5 T6 T7

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),

WRITE preamble = 1tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0

and WRITE commands at T6.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 211 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank

Group

READ to WRITE command delay

= RL +BL/2 - WL + 3 tCK 4 Clocks

tRPRE

RL = 11

tRPST

T1 T5 T6 T7

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 10

T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note

5], AL = 0), WRITE preamble = 2tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0

and WRITE commands at T6.

5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank

Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK

tRPRE

RL = 11

tRPST

T1 T5 T6 T7

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa or

BGb

tWPRE tWPST

tWTR

tWR

BGa

2 Clocks

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),

WRITE preamble = 1tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 212 Micron Technology, Inc. reserves the right to change products or specifications without notice.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 (fixed) setting activated by MR0[1:0] = 01.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank

Group

READ to WRITE command delay

= RL +BL/2 - WL + 3 tCK 2 Clocks

tRPRE

RL = 11

tRPST

T1 T5 T6 T7

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 10

T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 9 (CWL = 9 + 1 [see Note

5], AL = 0), WRITE preamble = 2tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 (fixed) setting activated by MR0[1:0] = 10.

5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 213 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK

tWPRE

RL = 11

tWPST

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T5 T6 T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tRPRE tRPST

tWTR

tWR

4 Clocks

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE

preamble = 1tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.

BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 3 tCK

tWPRE

RL = 11

tWPST

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 10

T5 T6 T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tRPRE tRPST

tWTR

tWR

4 Clocks

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note

5], AL = 0), WRITE preamble = 2tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.

BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 4 Clocks

tRPRE

RL = 11

tRPST

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T22T21T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE

preamble = 1tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.

BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 3 tCK 4 Clocks

tRPRE

RL = 11

tRPST

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 10

T22T21T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note

5], AL = 0), WRITE preamble = 2tCK.

2. DO n = data-out from column n; DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.

BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

READ Operation Followed by PRECHARGE Operation

The minimum external READ command to PRECHARGE command spacing to the same

bank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGE

command delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as

well. The minimum value for the internal READ command to PRECHARGE command

delay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE command

may be issued to the same bank if the following two conditions are satisfied simultane-

ously:

• The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock at

which the precharge begins.

• The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has been

satisfied.

Figure 153: READ to PRECHARGE with 1tCK Preamble

RL = AL + CL

tRTP tRP

T1 T2 T3 T6

DES DES DES DES DES DES DESCommand READDES DES DES DES PRE

BC4 Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T20 T21T14T7 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3

DES ACT DES DES DES

Bank Group

Address BGa BGa

or BGb BGa

Address Bank a

Col n Bank a

(or all) Bank a

Row b

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

Notes: 1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)

and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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Figure 154: READ to PRECHARGE with 2tCK Preamble

RL = AL + CL

tRTP tRP

BC4 Opertaion

DQS_t,

DQS_c

Don’t CareTransitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

T0 T1 T2 T3 T6

DES DES DES DES DES DES DESCommand READDES DES DES DES PRE

CK_t

CK_c

T20 T21T14T7 T10 T11 T12 T13 T19T15 T16 T17 T18

DES ACT DES DES DES

Bank Group

Address BGa BGa

BGa or

BGb

Address Bank a

Col n Bank a

(or all) Bank a

Row b

Notes: 1. RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)

and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble

CL = 11

AL = CL - 2 = 9 tRTP

T1 T2 T3

DES DES PRE DES DES DES DESCommand READDES DES DES DES DES

BC4 Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T26 T27T10 T11 T12 T13 T24 T25T22 T23T21T20T19T16

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3

DES DES DES DES ACT

Bank Group

Address BGa BGa or

BGb

tRP

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

Address Bank a

Col n Bank a

(or all) Bank a

Row b

BGa

Notes: 1. RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.

2. DO n = data-out from column n.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 217 Micron Technology, Inc. reserves the right to change products or specifications without notice.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time

(T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27).

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 156: READ with Auto Precharge and 1tCK Preamble

RL = AL + CL

tRTP tRP

T1 T2 T3 T6

DES DES DES DES DES DES DESCommand RDADES DES DES DES PRE

BC4 Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T20 T21T14T7 T10 T11 T12 T13 T19T15 T16 T17 T18

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3

DES ACT DES DES DES

Bank Group

Address BGa BGa

Address Bank a

Col n Bank a

Col n

BGa or

BGb

Bank a

Row b

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

Notes: 1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. tRTP = 6 setting activated by MR0[A11:9 = 001].

5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time

(T18).

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 218 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble

CL = 11

AL = CL - 2 = 9 tRTP

T1 T2 T3

DES DES DES DES DES DES DESCommand RDADES DES DES DES DES

BC4 Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T26 T27T10 T11 T12 T13 T24 T25T22 T23T21T20T19T16

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3

DES DES DES DES ACT

Bank Group

Address BGa BGa

tRP

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7

Address Bank a

Col n Bank a

Row b

Notes: 1. RL = 20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.

2. DO n = data-out from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. tRTP = 6 setting activated by MR0[11:9] = 001.

5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time

(T27).

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

READ Operation with Read Data Bus Inversion (DBI)

Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group

tCCD_S = 4

tRPRE

RL = 11 + 2 (Read DBI adder)

T16T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11 + 2 (Read DBI adder)

T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

b + 1 DO

b + 2 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGb

Address Bank

Col n Bank

Col b

tRPST

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 5 DO

b + 6

b + 3 DO

b +4 _

DBI_n

DBI

n + 1 DBI

n + 2 DBI

n + 3 DBI

b + 1 DBI

b + 2 DBI

b + 7

DBI

nDBI

n + 4 DBI

n + 5 DBI

n + 6 DBI

n + 7 DBI

bDBI

b + 5 DBI

b + 6

DBI

b + 3 DBI

b + 4

Notes: 1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK, RL = 11 + 2 (Read DBI adder).

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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2. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from col-

umn n (or b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable.

READ Operation with Command/Address Parity (CA Parity)

Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group

tCCD_S = 4

tRPRE

RL = 15

T1 T2 T3 T4 T7 T8

DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 15

T16T13 T14 T15 T21T17 T18 T19 T20 T21T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

b + 1 DO

b + 2 DO

b + 7

DES DES DES DES DES

Bank Group

Address BGa BGb

Address

Parity

Bank

Col n Bank

Col b

tRPST

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DO

bDO

b + 5 DO

b + 6

b + 3 DO

b +4 _

Notes: 1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1tCK.

2. DO n (or b) = data-out from column n (or b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during

READ commands at T0 and T4.

5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

CCMTD-1725822587-9875

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Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank

Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 4 Clocks

tRPRE

RL = 15

tRPST

T1 T7 T8 T9

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = 13

T22T16T14 T15 T21T17 T18 T19 T20 T25 T26T24T23

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Parity

Bank

Col n Bank

Col b

BGa BGa or

BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1tCK, CWL = 9,

AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK.

2. DO n = data-out from column n, DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and WRITE command at T8.

5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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READ Followed by WRITE with CRC Enabled

Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or

Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 4 Clocks

tRPRE

RL = 11

tRPST

T1 T7 T8 T9 T10 T11 T12 T13

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

DQ x4,

BL = 8

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T22T16T14 T15 T21T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

DQ x8/X16,

BL = 8

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC

DQ x4,

READ: BL = 8,

WRITE: BC = 4 (OTF)

DQ x8/X16,

READ: BL = 8,

WRITE: BC = 4 (OTF)

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 CRC CRC

tWPRE tWPST

tWTR

tWR

n + 1 DO

n + 2 DO

n + 3 DO

n + 4 DO

n + 5 DO

n + 6 DO

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC

b + 3

Notes: 1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL =

9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.

2. DO n = data-out from column n, DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T0 and WRITE commands at T8.

5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Enable.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or

Different Bank Group

READ to WRITE command delay

= RL +BL/2 - WL + 2 tCK 2 Clocks

tRPRE

RL = 11

tRPST

T1 T7T6T5 T8 T9 T10 T11 T12 T13

DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES

DQ x4,

BC = 4 (Fixed)

CK_t

CK_c

DQS_t,

DQS_c

WL = 9

T16T14 T15 T17 T18 T19 T20

Don’t Care

Transitioning DataTime Break

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

DQ x8/X16,

BC = 4 (Fixed)

n + 1 DO

n + 2 DO

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC

tWPRE tWPST

tWTR

tWR

Notes: 1. BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL =

0), WRITE preamble = 1tCK.

2. DO n = data-out from column n, DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Enable.

READ Operation with Command/Address Latency (CAL) Enabled

Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group

tCAL = 3 tCAL = 3

tCCD_S = 4

tRPRE

RL = 11

T1 T2 T3 T4

DES DES DES DES DES DESCommand

w/o CS_n

DES DES READ READDES DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T5 T6 T7 T8 T22 T23T13 T17T14 T15 T18 T19 T21

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tRPST

CS_n

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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2. DI n (or b) = data-in from column n (or b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T3 and T7.

5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. Enabling CAL mode does not impact ODT control timings. The same timing relationship

relative to the command/address bus as when CAL is disabled should be maintained.

Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group

tCAL = 4 tCAL = 4

tCCD_S = 4

tRPRE

RL = 11

T1 T2 T3 T4

DES DES DES DES DES DESCommand

w/o CS_n

DES DES READ READDES DES

CK_t

CK_c

DQS_t,

DQS_c

RL = 11

T5 T6 T7 T8 T24T22 T23T16T14 T15 T18 T19 T21

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tRPST

CS_n

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.

2. DI n (or b) = data-in from column n (or b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ

commands at T3 and T8.

5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. Enabling CAL mode does not impact ODT control timings. The same timing relationship

relative to the command/address bus as when CAL is disabled should be maintained.

8Gb: x4, x8, x16 DDR4 SDRAM

READ Operation

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WRITE Operation

Write Timing Definitions

The write timings shown in the following figures are applicable in normal operation

mode, that is, when the DLL is enabled and locked.

Write Timing – Clock-to-Data Strobe Relationship

The clock-to-data strobe relationship is shown below and is applicable in normal oper-

ation mode, that is, when the DLL is enabled and locked.

Rising data strobe edge parameters:

•tDQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge

relative to CK.

•tDQSS is the actual position of a rising strobe edge relative to CK.

•tDQSH describes the data strobe high pulse width.

•tWPST strobe going to HIGH, nondrive level (shown in the postamble section of the

graphic below).

Falling data strobe edge parameters:

•tDQSL describes the data strobe low pulse width.

•tWPRE strobe going to LOW, initial drive level (shown in the preamble section of the

graphic below).

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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Figure 165: Write Timing Definition

WL = AL + CWL

T0 T1 T2 T7 T8 T9 T10 T11 T12 T13 T14

Don’t CareTime Break Transitioning Data

Bank,

Col n

DES

WRITE DES

DES DES DES DES DES DES DES DES

CK_t

CK_c

Command3

DQ2

DQS_t, DQS_c

Address4

tWPSTaa

DM_n

tWPST (MIN)

tDQSL

tDQSS (MIN)

DIN

n + 2

DIN

n + 3

DQ2

tDQSS (MAX)

tDQSS (nominal)

tDQSL

tWPRE(1nCK)

tDQSL

tDQSS

tDSS tDSS tDSS tDSS tDSS

tDSH tDSH tDSH tDSH

tDSS tDSS tDSS tDSS tDSS

tDSH tDSH tDSH tDSH

tDQSL

tDQSH tDQSL

tDQSH tDQSH

tDQSL

tDQSH tDQSL

tDQSH tDQSH

tDQSL

tDQSH tDQSL

tDQSH tDQSH

tWPRE(1nCK)

tDQSH (MIN)

tWPST (MIN)

tDQSL (MIN)

DIN

n + 4

DIN

n + 6

DIN

n + 7

DIN

n + 2

DIN

n + 3

DIN

n + 4

DIN

n + 6

DIN

n + 7

DIN

n + 2

DIN

n + 3

DIN

n + 4

DIN

n + 6

DIN

n + 7

Notes: 1. BL8, WL = 9 (AL = 0, CWL = 9).

2. DINn = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0.

5. tDQSS must be met at each rising clock edge.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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tWPRE Calculation

Figure 166: tWPRE Method for Calculating Transitions and Endpoints

'46BW

W:35(HQGVW

&.BW

&.BF

9''



5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRUW:35(VSHFLILFDWLRQ

6LQJOHHQGHGVLJQDOSURYLGHGDVEDFNJURXQGLQIRUPDWLRQ

9

'46BF

'46BW'46BF

'46BW

'46BF

'46BW

'46BF

W:35(EHJLQV W

96:

96:

95()'4



95()'4



95()'4





9,+',))'46



9,+',))3HDN

Notes: 1. Vsw1 = (0.1) × VIH,diff,DQS.

2. Vsw2 = (0.9) × VIH,diff,DQS.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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tWPST Calculation

Figure 167: tWPST Method for Calculating Transitions and Endpoints

'46BW'46BF

96:

96:

'46BW

W:367HQGV W

&.BW

&.BF

5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRU W:367VSHFLILFDWLRQ

6LQJOHHQGHGVLJQDOSURYLGHGDVEDFNJURXQGLQIRUPDWLRQ

9

'46BF

'46BW

'46BF

W:367EHJLQV W

9''



95()'4



95()'4



95()'4



9,/',))'46



9,/',))3HDN

Notes: 1. Vsw1 =(0.9) × VIL,diff,DQS.

2. Vsw2 = (0.1) × VIL,diff,DQS.

Write Timing – Data Strobe-to-Data Relationship

The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in

the figure below. The receiver mask (Rx mask) defines the area where the input signal

must not encroach in order for the DRAM input receiver to be able to successfully cap-

ture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and V diVW define

the absolute maximum Rx mask.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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Figure 168: Rx Compliance Mask

TdiVW

VDIVW

Rx Mask

VCENTDQ,midpoint

VCENTDQ,midpoint is defined as the midpoint between the largest VREFDQ voltage level and

the smallest VREFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's

VREFDQ is defined by the center (widest opening) of the cumulative data input eye as de-

picted in the following figure. This means a DRAM's level variation is accounted for

within the DRAM Rx mask. The DRAM VREFDQ level will be set by the system to account

for RON and ODT settings.

Figure 169: VCENT_DQ VREFDQ Voltage Variation

VCENTDQx

VCENTDQy

VCENTDQz

VCENTDQ,midpoint

DQx DQy

(smallest VREFDQ Level)

DQz

(largest VREFDQ Level)

VREF variation

(component)

The following figure shows the Rx mask requirements both from a midpoint-to-mid-

point reference (left side) and from an edge-to-edge reference. The intent is not to add

any new requirement or specification between the two but rather how to convert the

relationship between the two methodologies. The minimum data-eye shown in the

composite view is not actually obtainable due to the minimum pulse width require-

ment.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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Figure 170: Rx Mask DQ-to-DQS Timings

DQS, DQs Data-In at DRAM BallDQS, DQs Data-In at DRAM Ball

Rx Mask Rx Mask – Alternative View

Rx Mask

DQS_t

Rx Mask

0.5 × TdiVW

tDQS2DQ +0.5 × TdiVW

DQy

DRAMc Rx Mask

DQz

DRAMc Rx Mask

DQz

DRAMb Rx Mask

DQy

DRAMb Rx Mask

DQS_cDQS_c

DQS_t

DQx–z

DRAMa

DQy

DRAMc

DQz

DRAMc

DQz

DRAMb

DQy

DRAMb

DQx–z

DRAMa

Rx Mask

TdiVW TdiVW

0.5 × TdiVW

tDQS2DQ

tDQ2DQ

tDQS2DQ

tDQ2DQ

VdiVW

TdiVW

Notes: 1. DQx represents an optimally centered mask.

DQy represents earliest valid mask.

DQz represents latest valid mask.

2. DRAMa represents a DRAM without any DQS/DQ skews.

DRAMb represents a DRAM with early skews (negative tDQS2DQ).

DRAMc represents a DRAM with delayed skews (positive tDQS2DQ).

3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ

for a DRAM. Signals assume data is center-aligned at DRAM latch.

TdiPW is not shown; composite data-eyes shown would violate TdiPW.

VCENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW.

The previous figure shows the basic Rx mask requirements. Converting the Rx mask re-

quirements to a classical DQ-to-DQS relationship is shown in the following figure. It

should become apparent that DRAM write training is required to take full advantage of

the Rx mask.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings

DQS_c

DQS_t

Rx Mask

DQS, DQs Data-In at DRAM Ball

VdiVW

DQx , y, z

DQS_c

DQS_t

Rx Mask

DQS, DQs Data-In at DRAM Ball

tDSx tDHx

DQx–z

DRAMa

DRAMb

DRAMc

TdiPW

Rx Mask vs. Composite Data-Eye Rx Mask vs. UI Data-Eye

TdiPW

*Skew

tDSy tDHy

DQy Rx Mask

TdiVW

tDQ2DQ

DQz

TdiPW

TdiVW TdiVW

tDSz tDHz

DQy tDQ2DQ

DQz

TdiPW

Rx Mask

TdiVW tDQ2DQ

Rx Mask

TdiVW

Rx Mask

TdiVW

tDQ2DQ

Notes: 1. DQx represents an optimally centered mask.

DQy represents earliest valid mask.

DQz represents latest valid mask.

2. *Skew = tDQS2DQ + 0.5 × TdiVW

DRAMa represents a DRAM without any DQS/DQ skews.

DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew).

DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew).

3. tDS/tDH are traditional data-eye setup/hold edges at DC levels.

tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width

and Rx mask limits are not violated.

tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ.

The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx

mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller

will have to train the data input buffer to utilize the Rx mask specifications to this maxi-

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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mum benefit. If the DRAM controller does not train the data input buffers, then the

worst case limits have to be used for the Rx mask (TdiVW + 2 × tDQS2DQ), which will

generally be the classical minimum ( tDS and tDH) and is required as well.

Figure 172: Example of Data Input Requirements Without Training

tDS

VdiVW

0.5 × VdiVW

tDH

0.5 × TdiVW + tDQS2DQ

TdiVW + 2 × tDQS2DQ

0.5 × TdiVW + tDQS2DQ

VCENTDQ,midpoint

VIL(DC)

VIH(DC)

DQS_c

DQS_t

Rx Mask

WRITE Burst Operation

The following write timing diagrams are intended to help understand each write pa-

rameter's meaning and are only examples. Each parameter will be defined in detail sep-

arately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and

DQ are shown center-aligned for the purpose of illustration.

DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-

the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:

• A12 = 0, BC4 (BC4 = burst chop)

• A12 = 1, BL8

WRITE commands can issue precharge automatically with a WRITE with auto pre-

charge (WRA) command, which is enabled by A10 HIGH.

• WRITE command with A10 = 0 (WR) performs standard write, bank remains active af-

ter WRITE burst

• WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes

into precharge after WRITE burst

The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the

DM function is not supported on x4 devices). The DM function shares a common pin

with the DBI_n and TDQS functions. The DM function only applies to WRITE opera-

tions and cannot be enabled at the same time the DBI function is enabled.

• If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data re-

ceived on the DQ inputs.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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• If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and

writes this data into the DRAM core.

• If CRC write is enabled, then DM enabled (via MRS) will be selected between write

CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM ena-

bled).

Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)

tWPRE

T1 T7T2 T8 T9 T10 T11 T12 T13

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T16T14 T15

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

Bank Group

Address

Address Bank

Col n

BGa

tWPST

Notes: 1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK.

2. DI n = Data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0.

5. CA parity = Disable, CS to CA Latency = Disable, Read DBI = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

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Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)

tWPRE

AL = 10 CWL = 9

T1 T2 T9 T10 T11

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 19

T21T17 T18 T19 T20 T23T22

Don’t Care

Transitioning DataTime Break

nDI

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

Bank Group

Address

Address Bank

Col n

BGa

tWPST

Notes: 1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

WRITE Operation Followed by Another WRITE Operation

Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPST

tWTR

tWR

Notes: 1. BL8, AL = 0, CWL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T17.

Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = AL + CWL = 10

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 10

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPST

tWTR

tWR

Notes: 1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T4.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T17.

7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting supported in the applicable

tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-

ble mode.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group

tCCD_S/L = 5 4 Clocks

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES WRITE

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T5 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa

or BGb

tWPST

tWTR

tWR

Notes: 1. BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T5.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T18.

Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group

tCCD_S/L = 6 4 Clocks

tWPRE

WL = AL + CWL = 10

T1 T2 T6 T7

DES DES DES DES DES DES DESCommand DESWRITE DES WRITE DES DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 10

T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T20T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa

or BGb

tWPRE tWPST

tWTR

tWR

Notes: 1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T6.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.

7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T20.

8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting supported in the applicable

tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-

ble mode.

Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPRE

tWTR

tWR

tWPST

Notes: 1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and

T4.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T17.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = AL + CWL = 10

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 10

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPRE

tWTR

tWR

tWPST

Notes: 1. BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and

T4.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T18.

7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting supported in the applicable

tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-

ble mode.

Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group

tCCD_S = 4 2 Clocks

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPRE

tWTR

tWR

tWPST

Notes: 1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 (fixed) setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T15.

Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWTR

tWR

tWPST

Notes: 1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.

BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T17.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group

tCCD_S = 4

tWPRE tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T7 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWTR

tWR

tWPST

4 Clocks

Notes: 1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.

BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T17.

WRITE Operation Followed by READ Operation

Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6

tWTR_S = 2

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES READ DES DESCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T16T14 T15 T24 T25 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tRPRE

tWPST

4 Clocks

Notes: 1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0 and READ command at T15.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after

the last write data shown at T13.

Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group

tWTR_L = 4

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES DES DESDESCommand DESWRITE DES DES DES READ

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa

tRPRE

tWPST

bDI

b + 1 DI

b + 2

4 Clocks

Notes: 1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0 and READ command at T17.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after

the last write data shown at T13.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group

tWTR_S = 2

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES READ DES DESCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T16T14 T15 T24 T25 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tRPRE

tWPST tRPST

bDI

b + 1 DI

b + 2 DI

b + 3

4 Clocks

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and

READ command at T15.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after

the last write data shown at T13.

Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group

tWTR_L = 4

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES DES DES READCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa

tRPRE

tWPST

bDI

b + 1 DI

b + 2

4 Clocks

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and

READ command at T17.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 242 Micron Technology, Inc. reserves the right to change products or specifications without notice.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after

the last write data shown at T13.

Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group

tWTR_S = 2

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES DES DES READCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T23T14 T22 T24 T25 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tRPRE

tWPST tRPST

bDI

b + 1 DI

b + 2 DI

b + 3

2 Clocks

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after

the last write data shown at T11.

Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group

tWTR_L = 4

tWPRE

WL = AL + CWL = 9 RL = AL + CL = 11

T1 T7

DES DES DES DES DESDESREADCommand DESWRITE DES DES DES DES

CK_t

CK_c

DQS_t,

DQS_c

T8 T9 T10 T11 T12 T13 T16T14 T15 T24 T25 T26 T27 T28 T29

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa

tRPRE

tWPST tRPST

bDI

b + 1 DI

b + 2 DI

b + 3

2 Clocks

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble =

1tCK.

2. DI b = data-in from column b.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,

Write CRC = Disable.

6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after

the last write data shown at T11.

WRITE Operation Followed by PRECHARGE Operation

The minimum external WRITE command to PRECHARGE command spacing is equal to

WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The min-

imum ACT to PRE timing, tRAS, must be satisfied as well.

Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble

WL = AL + CWL = 9 tWR = 12 tRP

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (OTF) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES PRE DES

Address

BGa, Bank b

Col n BGa, Bank b

(or all)

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

4 Clocks

Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8

setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command

at T0.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.

6. The write recovery time (tWR) is referenced from the first rising clock edge after the last

write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 244 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble

WL = AL + CWL = 9 tWR = 12 tRP

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (Fixed) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES PRE DES DES DES

Address

BGa, Bank b

Col n BGa, Bank b

(or all)

2 Clocks

Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.

6. The write recovery time (tWR) is referenced from the first rising clock edge after the last

write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble

WL = AL + CWL = 9 tWR = 12 tRP

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (OTF) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Address

BGa, Bank b

Col n

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

4 Clocks

Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.

BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-

mand at T0.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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6. The write recovery time (tWR) is referenced from the first rising clock edge after the last

write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble

WL = AL + CWL = 9 tWR = 12 tRP

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (Fixed) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Address

BGa, Bank b

Col n

2 Clocks

Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.

6. The write recovery time (tWR) is referenced from the first rising clock edge after the last

write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE

command can be issued to the same bank.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 246 Micron Technology, Inc. reserves the right to change products or specifications without notice.

WRITE Operation with WRITE DBI Enabled

Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI

WL = AL + CWL = 9 tWR

tWTR

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (OTF) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T5 T6 T14T7 T8 T9 T10 T11 T12 T13 T15 T16 T17

Don’t Care

Transitioning Data

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Address BGa

Address Bank,

Col n

DBI_n

BL8 Opertaion

DQS_t,

DQS_c

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7

DBI_n

n + 1 DI

n + 2 DI

n + 3

4 Clocks

Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.

BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-

mand at T0.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-

bled.

6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the

last write data shown at T13.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI

WL = AL + CWL = 9 tWR

tWTR

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES

BC4 (Fixed) Opertaion

CK_t

CK_c

DQS_t,

DQS_c

T5 T6 T14T7 T8 T9 T10 T11 T12 T13 T15 T16 T17

Don’t Care

Transitioning Data

n + 1 DI

n + 2 DI

n + 3

DES DES DES DES DES

Address BGa

Address Bank,

Col n

DBI_n

n + 1 DI

n + 2 DI

n + 3

2 Clocks

Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10.

5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-

bled.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

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WRITE Operation with CA Parity Enabled

Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group

tCCD_S = 4 4 Clocks

tWPRE

WL = PL + AL + CWL = 13

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES

CK_t

CK_c

DQS_t,

DQS_c

WL = PL + AL + CWL = 13

T20 T21 T22 T23T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGb

tWPST

tWTR

tWR

Parity Valid Valid

Notes: 1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK.

2. DI n = data-in from column n.

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-

mands at T0 and T4.

5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-

ble.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T21.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 249 Micron Technology, Inc. reserves the right to change products or specifications without notice.

WRITE Operation with Write CRC Enabled

Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Differ-

ent Bank Group

tCCD_S/L = 5

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES WRITE

DQ x4,

BL = 8

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T5 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 CRC

n + 7

CRC

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

DQ x8/X16,

BL = 8

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC

CRC

DQ x4,

BC = 4 (OTF)

DQ x8/X16,

BC = 4 (OTF)

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 CRC CRC

tWPST

tWTR

tWR

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC

b + 3

CRC

4 Clocks

Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T5.

5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and

T5.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable.

7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T18.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 250 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different

Bank Group

tCCD_S/L = 5

tWPRE

WL = AL + CWL = 9

T1 T2 T3 T4

DES DES DES DES DES DES DESCommand DESWRITE DES DES DES WRITE

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 9

T5 T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

CRC

DQ x4,

BC = 4 (Fixed)

DQ x8/X16,

BC = 4 (Fixed)

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 CRC CRC

tWPST

tWTR

tWR

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC

b + 3

2 Clocks

Notes: 1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.

5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,

DM = Disable.

6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T16.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 251 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Dif-

ferent Bank Group

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Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 6tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T6.

5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and

T6.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,

DM = Disable.

7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T19.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 252 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Dif-

ferent Bank Group

tCCD_S/L = 7

tWPRE

WL = AL + CWL = 10

DES DES DES DES DES DES DESCommand DESWRITE DES DESDESWRITE

DQ x4,

BL = 8

CK_t

CK_c

DQS_t,

DQS_c

WL = AL + CWL = 10

T22T21T7 T20T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 CRC

n + 7

CRC

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n Bank

Col b

BGa BGa or

BGb

DQ x8/X16,

BL = 8

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

bDI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7 CRC

CRC

DQ x4,

BC = 4 (OTF)

DQ x8/X16,

BC = 4 (OTF)

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 CRC CRC

tWPRE tWPST

tWTR

tWR

n + 1 DI

n + 2 DI

n + 3 DI

bDI

b + 1 DI

b + 2 DI

b + 3 CRC

b + 3

CRC

4 Clocks

Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCCD_S/L = 7tCK

(see Note 7).

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE commands at T0 and T7.

5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and

T7.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,

DM = Disable.

7. tCCD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCCD_S/L allowed in

1tCK preamble mode would have been 6 clocks.

8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from

the first rising clock edge after the last write data shown at T21.

9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a

value at least 1 clock greater than the lowest CWL setting supported in the applicable

tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble

mode.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 253 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank

Group

tWPRE

WL = AL + CWL = 9

T1 T2 T6 T7

DES DES DES DES DES DES DESCommand DESWRITE DES DESDESDESDES

DQ x4,

BL = 8

CK_t

CK_c

DQS_t,

DQS_c

T20T8 T9 T10 T11 T12 T13 T16T14 T15 T17 T18 T19

Don’t Care

Transitioning DataTime Break

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6 DI

n + 7 CRC

n + 7

CRC

DES DES DES DES DES

Bank Group

Address

Address Bank

Col n

BGa

DQ x8/X16,

BL = 8

n + 1 DI

n + 2 DI

n + 3 DI

n + 4 DI

n + 5 DI

n + 6

CRC

DQ x4,

BC = 4 (OTF/Fixed)

DQ x8/X16,

BC = 4 (OTF/Fixed)

n + 1 DI

n + 2 DI

n + 3

tWTR_S_CRC_DM/tWTR_L_CRC_DM

tWR_CRC_DM

tWPST

n + 1 DI

n + 2 DI

n + 3

n + 7

DMx4/x8/x16

BL = 8

n + 1 DM

n + 2 DM

n + 3 DM

n + 4 DM

n + 5 DM

n + 6

CRC

DM x4/x8/x16

BC = 4 (OTF / Fixed)

n + 1 DM

n + 2 DM

n + 3

4 Clocks

Notes: 1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK.

2. DI n (or b) = data-in from column n (or column b).

3. DES commands are shown for ease of illustration; other commands may be valid at

these times.

4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during

WRITE command at T0.

5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during

WRITE command at T0.

6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,

DM = Enable.

7. The write recovery time (tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/

tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write da-

ta shown at T13.

8Gb: x4, x8, x16 DDR4 SDRAM

WRITE Operation

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 254 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Write Timing Violations

Motivation

Generally, if timing parameters are violated, a complete reset/initialization procedure

has to be initiated to make sure that the device works properly. However, for certain mi-

nor violations, it is desirable that the device is guaranteed not to "hang up" and that er-

rors are limited to that specific operation. A minor violation does not include a major

timing violation (for example, when a DQS strobe misses in the tDQSCK window).

For the following, it will be assumed that there are no timing violations with regard to

the WRITE command itself (including ODT, and so on) and that it does satisfy all timing

requirements not mentioned below.

Data Setup and Hold Violations

If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe

edges associated with a WRITE burst, then wrong data might be written to the memory

location addressed with this WRITE command.

In the example, the relevant strobe edges for WRITE Burst A are associated with the

clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5.

Subsequent reads from that location might result in unpredictable read data; however,

the device will work properly otherwise.

Strobe-to-Strobe and Strobe-to-Clock Violations

If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock

timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges asso-

ciated with a WRITE burst, then wrong data might be written to the memory location

addressed with the offending WRITE command. Subsequent reads from that location

might result in unpredictable read data; however, the device will work properly other-

wise with the following constraints:

• Both write CRC and data burst OTF are disabled; timing specifications other than

tDQSH, tDQSL, tWPRE, tWPST, tDSS, tDSH, tDQSS are not violated.

• The offending write strobe (and preamble) arrive no earlier or later than six DQS tran-

sition edges from the WRITE latency position.

• A READ command following an offending WRITE command from any open bank is

allowed.

• One or more subsequent WR or a subsequent WRA (to same bank as offending WR)

may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and

WRA can be either offending or non-offending writes. Reads from these writes may

provide incorrect data.

• One or more subsequent WR or a subsequent WRA (to a different bank group) may be

issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA

can be either offending or non-offending writes. Reads from these writes may provide

incorrect data.

• After one or more precharge commands (PRE or PREA) are issued to the device after

an offending WRITE command and all banks are in precharged state (idle state), a

subsequent, non-offending WR or WRA to any open bank will be able to write correct

data.

8Gb: x4, x8, x16 DDR4 SDRAM

Write Timing Violations

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 255 Micron Technology, Inc. reserves the right to change products or specifications without notice.

ZQ CALIBRATION Commands

A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The de-

vice needs a longer time to calibrate the output driver and on-die termination circuits

at initialization and a relatively smaller time to perform periodic calibrations.

The ZQCL command is used to perform the initial calibration during the power-up ini-

tialization sequence. This command may be issued at any time by the controller de-

pending on the system environment. The ZQCL command triggers the calibration en-

gine inside the DRAM and, after calibration is achieved, the calibrated values are trans-

ferred from the calibration engine to DRAM I/O, which is reflected as an updated out-

put driver and ODT values.

The first ZQCL command issued after reset is allowed a timing period of tZQinit to per-

form the full calibration and the transfer of values. All other ZQCL commands except

the first ZQCL command issued after reset are allowed a timing period of tZQoper.

The ZQCS command is used to perform periodic calibrations to account for voltage and

temperature variations. A shorter timing window is provided to perform the calibration

and transfer of values as defined by timing parameter tZQCS. One ZQCS command can

effectively correct a minimum of 0.5% (ZQ correction) of RON and RTT impedance error

within 64 nCK for all speed bins assuming the maximum sensitivities specified in the

Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate in-

terval between ZQCS commands can be determined from these tables and other appli-

cation-specific parameters. One method for calculating the interval between ZQCS

commands, given the temperature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the

device is subjected to in the application, is illustrated. The interval could be defined by

the following formula:

ZQcorrection

(Tsense

x T

drift_rate) + (Vsense

x T

drift_rate)

Where Tsense = MAX(dRTTdT, dRONdTM) and Vsense = MAX(dRTTdV, dRONdVM) define

the temperature and voltage sensitivities.

For example, if Tsens = 1.5%/°C, Vsens = 0.15%/mV, Tdriftrate = 1 °C/sec and Vdriftrate = 15

mV/sec, then the interval between ZQCS commands is calculated as:

0.5 = 0.133 §128ms

(1.5 × 1) + (0.15 × 15)

No other activities should be performed on the DRAM channel by the controller for the

duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows ac-

curate calibration of output driver and on-die termination values. After DRAM calibra-

tion is achieved, the device should disable the ZQ current consumption path to reduce

power.

All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued

by the controller.

ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when

coming out of self refresh. Upon self refresh exit, the device will not perform an I/O cali-

8Gb: x4, x8, x16 DDR4 SDRAM

ZQ CALIBRATION Commands

CCMTD-1725822587-9875

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bration without an explicit ZQ CALIBRATION command. The earliest possible time for a

ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or

tXS_FAST depending on operation mode.

In systems that share the ZQ resistor between devices, the controller must not allow any

overlap of tZQoper, tZQinit, or tZQCS between the devices.

Figure 202: ZQ Calibration Timing

T0 T1 Ta0

DQ Bus

tZQinit_tZQoper

Don’t Care

Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2

ZQCS DES DES DES Valid

Valid

Command DESZQCL DES DES Valid Valid

Valid Valid

High-Z or RTT(Park) Activities

Note 3

Note 2

Note 1

Activities

High-Z or RTT(Park)

Time Break

Address

Valid Valid

A10

CKE

Valid Valid

ODT

CK_t

CK_c

tZQCS

Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.

2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to pro-

vide RTT_PARK.

3. All devices connected to the DQ bus should be High-Z during the calibration procedure.

8Gb: x4, x8, x16 DDR4 SDRAM

ZQ CALIBRATION Commands

CCMTD-1725822587-9875

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On-Die Termination

The on-die termination (ODT) feature enables the device to change termination resist-

ance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and

TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control

pin, WRITE command, or default parking value with MR setting. For the x16 configura-

tion, ODT is applied to each UDQ, LDQ, UDQS, LDQS, UDM_n/UDBI_n, and LDM_n/

LDBI_n signal. The ODT feature is designed to improve the signal integrity of the mem-

ory channel by allowing the DRAM controller to independently change termination re-

sistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in

standby, either DM mode or DBI write mode must also be enabled if RTT(NOM) or

RTT(Park) is desired. More details about ODT control modes and ODT timing modes can

be found further along in this document.

The ODT feature is turned off and not supported in self refresh mode.

Figure 203: Functional Representation of ODT

ODT VDDQ

RTT

Switch

DQ, DQS, DM, TDQS

To other

circuitry

such as

RCV,

. . .

The switch is enabled by the internal ODT control logic, which uses the external ODT

pin and other control information. The value of RTT is determined by the settings of

mode register bits (see Mode Register). The ODT pin will be ignored if the mode register

MR1 is programmed to disable RTT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode.

ODT Mode Register and ODT State Table

The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM),

RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (RTT(NOM)),

MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of

RTT is determined by the settings of these bits.

RTT control of each RTT condition is possible with a WR or RD command and ODT pin.

•R

TT(WR): The DRAM (rank) that is being written to provide termination regardless of

ODT pin status (either HIGH or LOW).

•R

TT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT

is disabled by MR1).

•R

TT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned

on.

• The Termination State Table that follows shows various interactions.

The RTT values have the following priority:

• Data termination disable

•R

TT(WR)

•R

TT(NOM)

•R

TT(Park)

8Gb: x4, x8, x16 DDR4 SDRAM

On-Die Termination

CCMTD-1725822587-9875

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Table 72: Termination State Table

Case RTT(Park) RTT(NOM)1RTT(WR)2ODT Pin ODT READS3

ODT Stand-

by7ODT WRITES

A4Disabled Disabled Disabled Don't Care Off (High-Z) Off (High-Z) Off (High-Z)

Enabled Don't Care Off (High-Z) Off (High-Z) RTT(WR)

B5Enabled Disabled Disabled Don't Care Off (High-Z) RTT(Park) RTT(Park)

Enabled Don't Care Off (High-Z) RTT(Park) RTT(WR)

C6Disabled Enabled Disabled Low Off (High-Z) Off (High-Z) Off (High-Z)

High Off (High-Z) RTT(NOM) RTT(NOM)

Enabled Low Off (High-Z) Off (High-Z) RTT(WR)

High Off (High-Z) RTT(NOM) RTT(WR)

D6Enabled Enabled Disabled Low Off (High-Z) RTT(Park) RTT(Park)

High Off (High-Z) RTT(NOM) RTT(NOM)

Enabled Low Off (High-Z) RTT(Park) RTT(WR)

High Off (High-Z) RTT(NOM) RTT(WR)

Notes: 1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power.

2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period

time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in

the Dynamic ODT section.

3. When a READ command is executed, the DRAM termination state will be High-Z for a

defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is

described in the ODT During Read section.

4. Case A is generally best for single-rank memories.

5. Case B is generally best for dual-rank, single-slotted memories.

6. Case C and Case D are generally best for multi-slotted memories.

7. The ODT feature is turned off and not supported in self refresh mode.

ODT Read Disable State Table

Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or

3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays

off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble

mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled.

Table 73: Read Termination Disable Window

Preamble CRC

Start ODT Disable After

Read Duration of ODT Disable

1tCK Disabled RL - 2 BL/2 + 2

Enabled RL - 2 BL/2 + 3

2tCK Disabled RL - 3 BL/2 + 3

Enabled RL - 3 BL/2 + 4

8Gb: x4, x8, x16 DDR4 SDRAM

ODT Mode Register and ODT State Table

CCMTD-1725822587-9875

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Synchronous ODT Mode

Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based

on the power-down definition, these modes include the following:

• Any bank active with CKE HIGH

• Refresh with CKE HIGH

• Idle mode with CKE HIGH

• Active power-down mode

• Precharge power-down mode

In synchronous ODT mode, RTT(NOM) will be turned on DODTLon clock cycles after

ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after

ODT is registered LOW by a rising clock edge. The ODT latency is determined by the

programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity la-

tency (PL), as well as the programmed state of the preamble.

ODT Latency and Posted ODT

The ODT latencies for synchronous ODT mode are summarized in the table below. For

details, refer to the latency definitions.

Table 74: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200

Applicable when write CRC is disabled

Symbol Parameter 1tCK Preamble 2tCK Preamble Unit

DODTLon Direct ODT turn-on latency CWL + AL + PL - 2 CWL + AL + PL - 3 tCK

DODTLoff Direct ODT turn-off latency CWL + AL + PL - 2 CWL + AL + PL - 3

RODTLoff READ command to internal ODT turn-off

latency

CL + AL + PL - 2 CL + AL + PL - 3

RODTLon4 READ command to RTT(Park) turn-on la-

tency in BC4-fixed

RODTLoff + 4 RODTLoff + 5

RODTLon8 READ command to RTT(Park) turn-on la-

tency in BL8/BC4-OTF

RODTLoff + 6 RODTLoff + 7

ODTH4 ODT Assertion time, BC4 mode 4 5

ODTH8 ODT Assertion time, BL8 mode 6 7

Timing Parameters

In synchronous ODT mode, the following parameters apply:

• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX).

•tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew

between different termination values. These timing parameters apply to both the syn-

chronous ODT mode and the data termination disable mode.

When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or

ODTH8 (BL = 8) is satisfied. If write CRC mode or 2tCK preamble mode is enabled,

ODTH should be adjusted to account for it. ODTHx is measured from ODT first regis-

tered HIGH to ODT first registered LOW or from the registration of a WRITE command.

8Gb: x4, x8, x16 DDR4 SDRAM

Synchronous ODT Mode

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 260 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 204: Synchronous ODT Timing with BL8

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

diff_CK

DODTLon = WL - 2 DODTLoff = WL - 2

Command

ODT

DRAM_RTT RTT(Park) RTT(NOM) RTT(Park)

tADC (MIN)

tADC (MAX)

tADC (MIN)

tADC (MAX)

Transitioning

Notes: 1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL +

PL + CWL - 2 = 7.

2. ODT must be held HIGH for at least ODTH8 after assertion (T1).

Figure 205: Synchronous ODT with BC4

diff_CK

DODTLon = CWL - 2

ODTH4

ODTLcwn4 = ODTLcnw + 4

DODTLoff = WL - 2

Command

ODT

DRAM_RTT

RTT(Park) RTT(Park)

RTT(WR)

tADC (MIN)

tADC (MAX)

tADC (MIN)

tADC (MAX)

T1T0 T2 T3 T4 T5 T18 T19 T20 T21 T22 T23 T36 T37 T38 T39 T40 T41 42

tADC (MIN)

tADC (MAX)

tADC (MIN)

tADC (MAX)

WRS4

Transitioning

ODTLcnw = WL - 2

RTT(Park)

RTT(NOM)

Notes: 1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw =

AL + PL+ CWL - 2 = 17.

2. ODT must be held HIGH for at least ODTH4 after assertion (T1).

8Gb: x4, x8, x16 DDR4 SDRAM

Synchronous ODT Mode

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 261 Micron Technology, Inc. reserves the right to change products or specifications without notice.

ODT During Reads

Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT

may nominally not be enabled until the end of the postamble as shown in the example

below. At cycle T26 the device turns on the termination when it stops driving, which is

determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC

(MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the

DRAM complies with tADC (MAX) timing.

Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL +

CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK

preamble.

Figure 206: ODT During Reads

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8Gb: x4, x8, x16 DDR4 SDRAM

Synchronous ODT Mode

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 262 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Dynamic ODT

In certain application cases and to further enhance signal integrity on the data bus, it is

desirable that the termination strength of the device can be changed without issuing an

MRS command. This requirement is supported by the dynamic ODT feature.

Functional Description

Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.

• Three RTT values are available: RTT(NOM), RTT(WR), and RTT(Park).

– The value for RTT(NOM) is preselected via bits MR1[10:8].

– The value for RTT(WR) is preselected via bits MR2[11:9].

– The value for RTT(Park) is preselected via bits MR5[8:6].

• During operation without WRITE commands, the termination is controlled as fol-

lows:

– Nominal termination strength RTT(NOM) or RTT(Park) is selected.

–R

TT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and

DODTLoff, and RTT(Park) is on when ODT is LOW.

• When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is regis-

tered, and if dynamic ODT is enabled, the termination is controlled as follows:

– Latency ODTLcnw after the WRITE command, termination strength RTT(WR) is se-

lected.

– Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for

BC4, fixed by MRS or selected OTF) after the WRITE command, termination

strength RTT(WR) is de-selected.

One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4,

depending on write CRC mode and/or 2tCK preamble enablement.

The following table shows latencies and timing parameters relevant to the on-die termi-

nation control in dynamic ODT mode. The dynamic ODT feature is not supported in

DLL-off mode. An MRS command must be used to set RTT(WR) to disable dynamic ODT

externally (MR2[11:9] = 000).

Table 75: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled)

Name and Descrip-

tion Abbr. Defined from Defined to

1600/1866/

2133/2400 2666 2933/3200 Unit

ODT latency for

change from RTT(Park)/

RTT(NOM) to RTT(WR)

ODTLc

Registering ex-

ternal WRITE

command

Change RTT

strength from

RTT(Park)/

RTT(NOM) to

RTT(WR)

ODTLcnw = WL - 2 tCK

ODT latency for

change from RTT(WR) to

RTT(Park)/RTT(NOM) (BC =

ODTLc

wn4

Registering ex-

ternal WRITE

command

Change RTT

strength from

RTT(WR) to

RTT(Park)/

RTT(NOM)

ODTLcwn4 = 4 + ODTLcnw tCK

ODT latency for

change from RTT(WR) to

RTT(Park)/RTT(NOM) (BL =

ODTLc

wn8

Registering ex-

ternal WRITE

command

Change RTT

strength from

RTT(NOM) to

RTT(WR)

ODTLcwn8 = 6 + ODTLcnw tCK

(AVG)

8Gb: x4, x8, x16 DDR4 SDRAM

Dynamic ODT

CCMTD-1725822587-9875

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Table 75: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) (Continued)

Name and Descrip-

tion Abbr. Defined from Defined to

1600/1866/

2133/2400 2666 2933/3200 Unit

RTT change skew tADC ODTLcnw

ODTLcwn

RTT valid tADC (MIN) =

0.30

tADC (MAX) =

0.70

tADC (MIN) =

0.28

tADC (MAX) =

0.72

tADC (MIN) =

0.26

tADC (MAX) =

0.74

tCK

(AVG)

Table 76: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix

Symbol

1tCK Parameter 2tCK Parameter

UnitCRC Off CRC On CRC Off CRC On

ODTLcnw1WL - 2 WL - 2 WL - 3 WL - 3 tCK

ODTLcwn4 ODTLcnw + 4 ODTLcnw + 7 ODTLcnw + 5 ODTLcnw + 8

ODTLcwn8 ODTLcnw + 6 ODTLcnw + 7 ODTLcnw + 7 ODTLcnw + 8

Note: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).

Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

diff_CK

ODTLcwn

ODTLcnw

DODTLon = WL - 2

DODTLoff = WL - 2

Command

ODT

RTT RTT(Park) RTT(NOM) RTT(Park)

RTT(WR)

tADC (MAX) tADC (MAX)

T1T0 T2 T5 T6 T7 T14T8 T9 T10 T11 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24

tADC (MIN)

tADC (MAX)

RTT(Park)

tADC (MAX)

Transitioning

Notes: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).

2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then

ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.

8Gb: x4, x8, x16 DDR4 SDRAM

Dynamic ODT

CCMTD-1725822587-9875

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Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

diff_CK

Command

ODT

T1T0 T2 T5 T6 T7 T25T12T9 T10 T11 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24

ODTLcnw

DODTLoff = CWL -2

ODTLcwn8

RTT RTT_NOM RTT_NOM RTT_PARK

RTT_WR

tADC (MAX) tADC (MAX)

tADC (MIN)

tADC (MAX)

Note: 1. Behavior with WR command issued while ODT is registered HIGH.

8Gb: x4, x8, x16 DDR4 SDRAM

Dynamic ODT

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Asynchronous ODT Mode

Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asyn-

chronous ODT timing mode, the internal ODT command is not delayed by either addi-

tive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)).

In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and

tAOFAS (MIN/MAX).

RTT(NOM) Turn-on Time

• Minimum RTT(NOM) turn-on time (tAONAS [MIN]) is when the device termination cir-

cuit leaves RTT(Park) and ODT resistance begins to turn on.

• Maximum RTT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has

reached RTT(NOM).

•tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH.

RTT(NOM) Turn-off Time

• Minimum RTT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination

circuit starts to leave RTT(NOM).

• Maximum RTT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has

reached RTT(Park).

•tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW.

Figure 209: Asynchronous ODT Timings with DLL Off

diff_CK

tAONAS (MAX)

CKE

ODT

RTT RTT(Park) RTT(NOM)

tAONAS (MIN) tAONAS (MAX)

tAONAS (MIN)

tIH tIS tIH tIS

T1T0 T2 T3 T4 T5 T6 Ti Ti + 1 Ti + 2 Ti + 3 Ti + 4 Ti + 5 Ti + 6 Ta Tb

Transitioning

8Gb: x4, x8, x16 DDR4 SDRAM

Asynchronous ODT Mode

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Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions outside those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may ad-

versely affect reliability. Although "unlimited" row accesses to the same row is allowed

within the refresh period; excessive row accesses to the same row over a long term can

result in degraded operation.

Table 77: Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

VDD Voltage on VDD pin relative to VSS –0.4 1.5 V 1

VDDQ Voltage on VDDQ pin relative to VSS –0.4 1.5 V 1

VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 3

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V

TSTG Storage temperature –55 150 °C 2

Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be

greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ื300mV.

2. Storage temperature is the case surface temperature on the center/top side of the

DRAM. For the measurement conditions, please refer to the JESD51-2 standard.

3. VPP must be equal to or greater than VDD/VDDQ at all times when powered.

DRAM Component Operating Temperature Range

Operating temperature, TOPER, is the case surface temperature on the center/top side of

the DRAM. For measurement conditions, refer to the JEDEC document JESD51-2.

Table 78: Temperature Range

Symbol Parameter Min Max Unit Notes

TOPER Normal operating temperature range -40 85 °C 1

Extended temperature range (optional) >85 105 °C 2

Notes: 1. The normal temperature range specifies the temperatures at which all DRAM specifica-

tions will be supported. During operation, the DRAM case temperature must be main-

tained between 0°C to 85°C under all operating conditions for the commercial offering;

The industrial and automotive temperature offerings allow the case temperature to go

below 0°C to -40°C.

2. Some applications require operation of the commercial, industrial, and automotive tem-

perature DRAMs in the extended temperature range (between 85°C and 105°C case

temperature). Full specifications are supported in this range, but the following addition-

al conditions apply:

• Refer to tREFI and tRFC parameters table for tREFI requirements when operating

above 85°C

• If SELF REFRESH operation is required in the extended temperature range, it is manda-

tory to use either the manual self refresh mode with extended temperature range ca-

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Specifications

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pability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode

(MR2 [6] = 1 and MR2 [7] = 1).

Electrical Characteristics – AC and DC Operating Conditions

Supply Operating Conditions

Table 79: Recommended Supply Operating Conditions

Symbol Parameter

Rating

Unit NotesMin Typ Max

VDD Supply voltage 1.14 1.2 1.26 V 1, 2, 3, 4, 5

VDDQ Supply voltage for output 1.14 1.2 1.26 V 1, 2, 6

VPP Wordline supply voltage 2.375 2.5 2.750 V 7

Notes: 1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600

V/ms, 20 MHz band-limited measurement.

4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms.

5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than

VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa-

tion, the DLL reset and calibrations must be performed again after the new set DC level

is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the noise

doesn't alter VDD to less than VDD,min or greater than VDD,max.

6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than

VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial-

ization, the DLL reset and calibrations must be performed again after the new set DC

level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided the

noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.

7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than

VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initializa-

tion, the DLL reset and calibrations must be performed again after the new set DC level

is final. AC noise of ±120mV (greater than 250 KHz) is allowed on VPP provided the noise

doesn't alter VPP to less than VPP,min or greater than VPP,max.

Table 80: VDD Slew Rate

Symbol Min Max Unit Notes

VDD_sl 0.004 600 V/ms 1, 2

VDD_on – 200 ms 3

Notes: 1. Measurement made between 300mV and 80% VDD (minimum level).

2. The DC bandwidth is limited to 20 MHz.

3. Maximum time to ramp VDD from 300 mV to VDD minimum.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Operating Conditions

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Leakages

Table 81: Leakages

Condition Symbol Min Max Unit Notes

Input leakage (excluding ZQ and TEN) IIN –2 2 μA 1

ZQ leakage IZQ –50 10 μA 1

TEN leakage ITEN –6 10 μA 1, 2

VREFCA leakage IVREFCA –2 2 μA 3

Output leakage: VOUT = VDDQ IOZpd –10μA4

Output leakage: VOUT = VSSQ IOZpu –50 – μA 4, 5

Notes: 1. Input under test 0V < VIN < 1.1V.

2. Additional leakage due to weak pull-down.

3. VREFCA = VDD/2, VDD at valid level after initialization.

4. DQs are disabled.

5. ODT is disabled with the ODT input HIGH.

VREFCA Supply

VREFCA is to be supplied to the DRAM and equal to VDD/2. The VREFCA is a reference sup-

ply input and therefore does not draw biasing current.

The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA are illus-

trated in the figure below. The figure shows a valid reference voltage VREF(t) as a function

of time (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long

period of time (1 second). This average has to meet the MIN/MAX requirements. Fur-

thermore, VREF(t) may temporarily deviate from VREF(DC) by no more than ±1% VDD for

the AC-noise limit.

Figure 210: VREFDQ Voltage Range

VREF AC-noise

VREF(DC)

VREF(DC) MAX

VREF(t)

VREF(DC) MIN

VDD/2

VSS

Time

Voltage

VDD

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Operating Conditions

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The voltage levels for setup and hold time measurements are dependent on VREF. VREF is

understood as VREF(DC), as defined in the above figure. This clarifies that DC-variations

of VREF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW

level, and therefore, the time to which setup and hold is measured. System timing and

voltage budgets need to account for VREF(DC) deviations from the optimum position

within the data-eye of the input signals. This also clarifies that the DRAM setup/hold

specification and derating values need to include time and voltage associated with VREF

AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit

(±1% of VDD) are included in DRAM timings and their associated deratings.

VREFDQ Supply and Calibration Ranges

The device internally generates its own VREFDQ. DRAM internal VREFDQ specification pa-

rameters: voltage range, step size, VREF step time, VREF full step time, and VREF valid level

are used to help provide estimated values for the internal VREFDQ and are not pass/fail

limits. The voltage operating range specifies the minimum required range for DDR4

SDRAM devices. The minimum range is defined by VREFDQ,min and VREFDQ,max. A cali-

bration sequence should be performed by the DRAM controller to adjust VREFDQ and

optimize the timing and voltage margin of the DRAM data input receivers.

Table 82: VREFDQ Specification

Parameter Symbol Min Typ Max Unit Notes

Range 1 VREFDQ operating points VREFDQ R1 60% – 92% VDDQ 1, 2

Range 2 VREFDQ operating points VREFDQ R2 45% – 77% VDDQ 1, 2

VREF step size VREF,step 0.5% 0.65% 0.8% VDDQ 3

VREF set tolerance VREF,set_tol –1.625% 0% 1.625% VDDQ 4, 5, 6

–0.15% 0% 0.15% VDDQ 4, 7, 8

VREF step time VREF,time – – 150 ns 9, 10, 11

VREF valid tolerance VREF_val_tol –0.15% 0% 0.15% VDDQ 12

Notes: 1. VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V.

2. DRAM range 1 or range 2 is set by the MRS6[6]6.

3. VREF step size increment/decrement range. VREF at DC level.

4. VREF,new = VREF,old ±n × VREF,step; n = number of steps. If increment, use “+,” if decrement,

use “-.”

5. For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% × VDDQ. The

maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ.

6. Measured by recording the MIN and MAX values of the VREF output over the range,

drawing a straight line between those points, and comparing all other VREF output set-

tings to that line.

7. For n ื4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The

maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ.

8. Measured by recording the MIN and MAX values of the VREF output across four consecu-

tive steps (n = 4), drawing a straight line between those points, and comparing all VREF

output settings to that line.

9. Time from MRS command to increment or decrement one step size for VREF.

10. Time from MRS command to increment or decrement more than one step size up to the

full range of VREF.

11. If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and

an additional +15 ns/pF of DQ bus loading.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Operating Conditions

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12. Only applicable for DRAM component-level test/characterization purposes. Not applica-

ble for normal mode of operation. VREF valid qualifies the step times, which will be char-

acterized at the component level.

VREFDQ Ranges

MR6[6] selects range 1 (60% to 92.5% of VDDQ) or range 2 (45% to 77.5% of VDDQ), and

MR6[5:0] sets the VREFDQ level, as listed in the following table. The values in MR6[6:0]

will update the VDDQ range and level independent of MR6[7] setting. It is recommended

MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommen-

ded MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a

calibration routine.

Table 83: VREFDQ Range and Levels

MR6[5:0]

MR6[6] 0 =

Range 1

MR6[6] 1 =

Range 2 MR6[5:0]

MR6[6] 0 =

Range 1

MR6[6] 1 =

Range 2

00 0000 60.00% 45.00% 01 1010 76.90% 61.90%

00 0001 60.65% 45.65% 01 1011 77.55% 62.55%

00 0010 61.30% 46.30% 01 1100 78.20% 63.20%

00 0011 61.95% 46.95% 01 1101 78.85% 63.85%

00 0100 62.60% 47.60% 01 1110 79.50% 64.50%

00 0101 63.25% 48.25% 01 1111 80.15% 65.15%

00 0110 63.90% 48.90% 10 0000 80.80% 65.80%

00 0111 64.55% 49.55% 10 0001 81.45% 66.45%

00 1000 65.20% 50.20% 10 0010 82.10% 67.10%

00 1001 65.85% 50.85% 10 0011 82.75% 67.75%

00 1010 66.50% 51.50% 10 0100 83.40% 68.40%

00 1011 67.15% 52.15% 10 0101 84.05% 69.05%

00 1100 67.80% 52.80% 10 0110 84.70% 69.70%

00 1101 68.45% 53.45% 10 0111 85.35% 70.35%

00 1110 69.10% 54.10% 10 1000 86.00% 71.00%

00 1111 69.75% 54.75% 10 1001 86.65% 71.65%

01 0000 70.40% 55.40% 10 1010 87.30% 72.30%

01 0001 71.05% 56.05% 10 1011 87.95% 72.95%

01 0010 71.70% 56.70% 10 1100 88.60% 73.60%

01 0011 72.35% 57.35% 10 1101 89.25% 74.25%

01 0100 73.00% 58.00% 10 1110 89.90% 74.90%

01 0101 73.65% 58.65% 10 1111 90.55% 75.55%

01 0110 74.30% 59.30% 11 0000 91.20% 76.20%

01 0111 74.95% 59.95% 11 0001 91.85% 76.85%

01 1000 75.60% 60.60% 11 0010 92.50% 77.50%

01 1001 76.25% 61.25% 11 0011 to 11 1111 are reserved

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Operating Conditions

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Electrical Characteristics – AC and DC Single-Ended Input Measurement

Levels

RESET_n Input Levels

Table 84: RESET_n Input Levels (CMOS)

Parameter Symbol Min Max Unit Note

AC input high voltage VIH(AC)_RESET 0.8 × VDD VDD V1

DC input high voltage VIH(DC)_RESET 0.7 × VDD VDD V2

DC input low voltage VIL(DC)_RESET VSS 0.3 × VDD V3

AC input low voltage VIL(AC)_RESET VSS 0.2 × VDD V4

Rising time tR_RESET – 1 μs 5

RESET pulse width after power-up tPW_RESET_S 1 – μs 6, 7

RESET pulse width during power-up tPW_RESET_L 200 – μs 6

Notes: 1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table.

2. After RESET_n is registered HIGH, the RESET_n level must be maintained above

VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n

signal LOW.

3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RE-

SET during tPW_RESET, otherwise the DRAM may not be reset.

4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table.

5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-

gated as much as possible.

6. RESET is destructive to data contents.

7. See RESET Procedure at Power Stable Condition figure.

Figure 211: RESET_n Input Slew Rate Definition

R_RESET

PW_RESET

IH(AC)_RESET,min

IL(AC)_RESET,max

IH(DC)_RESET,min

IL(DC)_RESET,max

Command/Address Input Levels

Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400

Parameter Symbol Min Max Unit Note

AC input high voltage VIH(AC) VREF + 100 VDD5 mV 1, 2, 3

DC input high voltage VIH(DC) VREF + 75 VDD mV 1, 2

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)

Parameter Symbol Min Max Unit Note

DC input low voltage VIL(DC) VSS VREF - 75 mV 1, 2

AC input low voltage VIL(AC) VSS5V

REF - 100 mV 1, 2, 3

Reference voltage for CMD/ADDR inputs VREFFCA(DC) 0.49 × VDD 0.51 × VDD V4

Notes: 1. For input except RESET_n. VREF = VREFCA(DC).

2. VREF = VREFCA(DC).

3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.

4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than

±1% VDD (for reference: approximately ±12mV).

5. Refer to “Overshoot and Undershoot Specifications.”

Table 86: Command and Address Input Levels: DDR4-2666

Parameter Symbol Min Max Unit Note

AC input high voltage VIH(AC) VREF + 90 VDD5 mV 1, 2, 3

DC input high voltage VIH(DC) VREF + 65 VDD mV 1, 2

DC input low voltage VIL(DC) VSS VREF - 65 mV 1, 2

AC input low voltage VIL(AC) VSS5V

REF - 90 mV 1, 2, 3

Reference voltage for CMD/ADDR inputs VREFFCA(DC) 0.49 × VDD 0.51 × VDD V4

Notes: 1. For input except RESET_n. VREF = VREFCA(DC).

2. VREF = VREFCA(DC).

3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.

4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than

±1% VDD (for reference: approximately ±12mV).

5. Refer to “Overshoot and Undershoot Specifications.”

Table 87: Command and Address Input Levels: DDR4-2933 and DDR4-3200

Parameter Symbol Min Max Unit Note

AC input high voltage VIH(AC) VREF + 90 VDD5 mV 1, 2, 3

DC input high voltage VIH(DC) VREF + 65 VDD mV 1, 2

DC input low voltage VIL(DC) VSS VREF - 65 mV 1, 2

AC input low voltage VIL(AC) VSS5V

REF - 90 mV 1, 2, 3

Reference voltage for CMD/ADDR inputs VREFFCA(DC) 0.49 × VDD 0.51 × VDD V4

Notes: 1. For input except RESET_n. VREF = VREFCA(DC).

2. VREF = VREFCA(DC).

3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.

4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than

±1% VDD (for reference: approximately ±12mV).

5. Refer to “Overshoot and Undershoot Specifications.”

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 88: Single-Ended Input Slew Rates

Parameter Symbol Min Max Unit Note

Single-ended input slew rate – CA SRCA 1.0 7.0 V/ns 1, 2, 3, 4

Notes: 1. For input except RESET_n.

2. VREF = VREFCA(DC).

3. tIS/tIH timings assume SRCA = 1V/ns.

4. Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC)

for rising edges

Figure 212: Single-Ended Input Slew Rate Definition

TFse

VIH(DC)

VIH(AC)

VIL(AC)

VIL(DC)

VREFCA

Command, Control, and Address Setup, Hold, and Derating

The total tIS (setup time) and tIH (hold time) required is calculated to account for slew

rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and

tIH (base) values, the VIL(DC)/VIH(DC) points; to the ˂tIS and ˂tIH derating values, re-

spectively. The base values are derived with single-end signals at 1V/ns and differential

clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + ˂tIS. For a valid transition,

the input signal has to remain above/below VIH(AC)/VIL(AC) for the time defined by tVAC.

Although the total setup time for slow slew rates might be negative (for example, a valid

input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi-

tion), a valid input signal is still required to complete the transition and to reach

VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the

derating values may be obtained by linear interpolation.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back be-

low VIH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)max that does

not ring back above VIL(DC)max.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the

last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back be-

low VIH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of VIH(DC)min and the first crossing of VIL(AC)minthat does not

ring back above VIL(DC)max.

Table 89: Command and Address Setup and Hold Values Referenced – AC/DC-Based

Symbol 1600 1866 2133 2400 2666 2933 3200 Unit Reference

tIS(base, AC100) 115 100 80 62 – – – ps VIH(AC)/VIL(AC)

tIH(base, DC75) 140 125 105 87 – – – ps VIH(DC)/VIL(DC)

tIS(base, AC90) ––––554840psV

IH(AC)/VIL(AC)

tIH(base, DC65) ––––807365psV

IH(DC)/VIL(DC)

tIS/tIH(Vref) 215 200 180 162 145 138 130 ps VIH(DC)/VIL(DC)

Table 90: Derating Values for tIS/tIH – AC100DC75-Based

tIS with AC100 Threshold,

tIH with DC75 Threshold Derating (ps) – AC/DC-Based

CMD/

ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

10.0 V/ns 8.0 V/ns 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.5 V/ns 1.0 V/ns

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

7.0 76 54 76 55 77 56 79 58 82 60 86 64 94 73 111 89

6.0 73 53 74 53 75 54 77 56 79 58 83 63 92 71 108 88

5.0 70 50 71 51 72 52 74 54 76 56 80 60 88 68 105 85

4.0 65 46 66 47 67 48 69 50 71 52 75 56 83 65 100 81

3.0 57 40 57 41 58 42 60 44 63 46 67 50 75 58 92 75

2.0 40 28 41 28 42 29 44 31 46 33 50 38 58 46 75 63

1.5 23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50

1.0 –10 –10 –9 –9 –8 –8 –6 –6 –4 –4 008 8 25 25

0.9 –17 –14 –16 –14 –15 –13 –13 –10 –11 –8 –7 –4 1 4 18 21

0.8 –26 –19 –25 –19 –24 –18 –22 –16 –20 –14 –16 –9 –7 –1 9 16

0.7 –37 –26 –36 –25 –35 –24 –33 –22 –31 –20 –27 –16 –18 –8 –2 9

0.6 –52 –35 –51 –34 –50 –33 –48 –31 –46 –29 –42 –25 –33 –17 –17 0

0.5 –73 –48 –72 –47 –71 –46 –69 –44 –67 –42 –63 –38 –54 –29 –38 –13

0.4 –104 –66 –103 –66 –102 –65 –100 –63 –98 –60 –94 –56 –85 –48 –69 –31

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 91: Derating Values for tIS/tIH – AC90/DC65-Based

tIS with AC90 Threshold,

tIH with DC65 Threshold Derating (ps) – AC/DC-Based

CMD/

ADDR

Slew Rate

V/ns

CK, CK# Differential Slew Rate

10.0 V/ns 8.0 V/ns 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.5 V/ns 1.0 V/ns

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

tIS

tIH

7.0 68 47 69 47 70 48 72 50 73 52 77 56 85 63 100 78

6.0 66 45 67 46 68 47 69 49 71 50 75 54 83 62 98 77

5.0 63 43 64 44 65 45 66 46 68 48 72 52 80 60 95 75

4.0 59 40 59 40 60 41 62 43 64 45 68 49 75 56 90 71

3.0 51 34 52 35 53 36 54 38 56 40 60 43 68 51 83 66

2.0 36 24 37 24 38 25 39 27 41 29 45 33 53 40 68 55

1.5 21 13 22 13 23 14 24 16 26 18 30 22 38 29 53 44

1.0 –9 –9 –8 –8 –8 –8 –6 –6 –4 –4 008 8 23 23

0.9 –15 –13 –15 –12 –14 –11 –12 –9 –10 –7 –6 –4 1 4 16 19

0.8 –23 –17 –23 –17 –22 –16 –20 –14 –18 –12 –14 –8 –7 –1 8 14

0.7 –34 –23 –33 –22 –32 –21 –30 –20 –28 –18 –25 –14 –17 –6 –2 9

0.6 –47 –31 –47 –30 –46 –29 –44 –27 –42 –25 –38 –22 –31 –14 –16 1

0.5 –67 –42 –66 –41 –65 –40 –63 –38 –61 –36 –58 –33 –50 –25 –35 –10

0.4 –95 –58 –95 –57 –94 –56 –92 –54 –90 –53 –86 –49 –79 –41 –64 –26

Data Receiver Input Requirements

The following parameters apply to the data receiver Rx MASK operation detailed in the

Write Timing section, Data Strobe-to-Data Relationship.

The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement

points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time,

tr1, is measured from 0.5 × VdiVW,max below VCENTDQ,midpoint to the last transition

through 0.5 × VdiVW,max above VCENTDQ,midpoint; tr2 is measured from the last transition

through 0.5 × VdiVW,max above VCENTDQ,midpoint to the first transition through the 0.5 ×

VIHL(AC)min above VCENTDQ,midpoint.

The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement

points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time,

tf1, is measured from 0.5 × VdiVW,max above VCENTDQ,midpoint to the last transition

through 0.5 × VdiVW,max below VCENTDQ,midpoint; tf2 is measured from the last transition

through 0.5 × VdiVW,max below VCENTDQ,midpoint to the first transition through the 0.5 ×

VIHL(AC)min below VCENTDQ,midpoint.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Figure 213: DQ Slew Rate Definitions

VIHL(AC)min

0.5 ×

VIHL(AC)min

0.5 ×

VIHL(AC)min

0.5 ×

VIHL(AC)min

0.5 ×

VIHL(AC)min

0.5 × VdiVW,max

VCENTDQ,midpoint

VdiVW,max

0.5 × VdiVW,max

VdiVW,max

tr1

tr2

VCENTDQ,midpoint

tf1

tf2

Rx Mask

Notes: 1. Rising edge slew rate equation srr1 = VdiVW,max/(tr1).

2. Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 × tr2).

3. Falling edge slew rate equation srf1 = VdiVW,max/(tf1).

4. Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 × tf2).

Table 92: DQ Input Receiver Specifications

Note 1 applies to the entire table

Parameter Symbol

DDR4-1600,

1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Unit

Not

Min Max Min Max Min Max Min Max Min Max

VIN Rx mask input

peak-to-peak

VdiVW – 136 – 130 – 120 – 115 – 110 mV 2, 3

DQ Rx input tim-

ing window

TdiVW – 0.2 – 0.2 – 0.22 – 0.23 – 0.23 UI 2, 3

DQ AC input

swing peak-to-

peak

VIHL(AC) 186 – 160 – 150 – 145 – 140 – mV 4, 5

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 92: DQ Input Receiver Specifications (Continued)

Note 1 applies to the entire table

Parameter Symbol

DDR4-1600,

1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Unit

Not

Min Max Min Max Min Max Min Max Min Max

DQ input pulse

width

TdiPW 0.58 – 0.58 – 0.58 – 0.58 – 0.58 – UI 6

DQS-to-DQ Rx

mask offset

tDQS2D

–0.17 0.17 –0.17 0.17 –0.19 0.19 –0.22 0.22 –0.22 0.22 UI 7

DQ-to-DQ Rx mask

offset

tDQ2DQ – 0.1 – 0.1 – 0.105 – 0.115 – 0.125 UI 8

Input slew rate

over VdiVW if tCK ุ

0.937ns

srr1, srf1 1 9 1 9 1 9 1 9 1 9 V/ns 9

Input slew rate

over VdiVW if

0.937ns > tCK ุ

0.625ns

srr1, srf1 – – 1.25 9 1.25 9 1.25 9 1.25 9 V/ns 9

Rising input slew

rate over 1/2

VIHL(AC)

srr2 0.2 ×

srr1

9 0.2 ×

srr1

9 0.2 ×

srr1

9 0.2 ×

srr1

9 0.2 ×

srr1

9 V/ns 10

Falling input slew

rate over 1/2

VIHL(AC)

srf2 0.2 ×

srf1

9 0.2 ×

srf1

9 0.2 ×

srf1

9 0.2 ×

srf1

9 0.2 ×

srf1

9 V/ns 10

Notes: 1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum in-

put pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew

rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased

to the point where the minimum input pulse width would no longer be violated.

2. Data Rx mask voltage and timing total input valid window where VdiVW is centered

around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied

per bit and should include voltage and temperature drift terms. The input buffer design

specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.

3. Defined over the DQ internal VREF range 1.

4. Overshoot and undershoot specifications apply.

5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min

is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a

valid TdiPW).

6. DQ minimum input pulse width defined at the VCENTDQ,midpoint.

7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word

(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM

balls over process, voltage, and temperature.

8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at

the SDRAM balls for a given component over process, voltage, and temperature.

9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to

fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.

10. Input slew rate between VdiVW mask edge and VIHL(AC)min points.

The following figure shows the Rx mask relationship to the input timing specifications

relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; how-

ever, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the

input pulse width specification is satisfied and the Rx mask is not violated.

Figure 214: Rx Mask Relative to tDS/tDH

tDH = Greater of 0.5 × TdiVW

0.5 × (TdiPW + VdiVW/tr1)

tDS = Greater of 0.5 × TdiVW

0.5 × (TdiPW + VdiVW/tf1)

VdiVW

0.5 × VdiVW

tf1 tr1

0.5 × VdiVW

TdiPW

TdiVW

VCENTDQ,pin mean

VIL(DC)

VIH(DC)

DQS_c

DQS_t

Mask

The following figure and table show an example of the worst case Rx mask required if

the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The

figure and table show that without DRAM write DQ training, the Rx mask would in-

crease from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH

required as well.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Figure 215: Rx Mask Without Write Training

tDS

VdiVW

0.5 × VdiVW

tDH

0.5 × TdiVW + tDQS2DQ

TdiVW + 2 × tDQS2DQ

0.5 × TdiVW + tDQS2DQ

VCENTDQ,midpoint

VIL(DC)

VIH(DC)

DQS_c

DQS_t

Rx Mask

Table 93: Rx Mask and tDS/tDH without Write Training

DDR4 VIHL(AC)

(mV)

TdiPW

(UI)

VdiVW

(mV)

TdiVW

(UI)

tDQS2DQ

(UI)

tDQ2DQ

(UI)

Rx Mask

with Write

Train

(ps)

tDS + tDH

(ps)

1600 186 0.58 136 0.2 ±0.17 0.1 125 338

1866 186 0.58 136 0.2 ±0.17 0.1 107.1 289

2133 186 0.58 136 0.2 ±0.17 0.1 94 253

2400 160 0.58 130 0.2 ±0.17 0.1 83.3 225

2666 150 0.58 120 0.22 ±0.19 0.105 82.5 225

2933 145 0.58 115 0.23 ±0.22 0.115 78.4 228

3200 140 0.58 110 0.23 ±0.22 0.125 71.8 209

Note: 1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint.

Connectivity Test (CT) Mode Input Levels

Table 94: TEN Input Levels (CMOS)

Parameter Symbol Min Max Unit Note

TEN AC input high voltage VIH(AC)_TEN 0.8 × VDD VDD V1

TEN DC input high voltage VIH(DC)_TEN 0.7 × VDD VDD V

TEN DC input low voltage VIL(DC)_TEN VSS 0.3 × VDD V

TEN AC input low voltage VIL(AC)_TEN VSS 0.2 × VDD V2

TEN falling time tF_TEN – 1 0 ns

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 94: TEN Input Levels (CMOS) (Continued)

Parameter Symbol Min Max Unit Note

TEN rising time tR_TEN – 1 0 ns

Notes: 1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.

2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.

Figure 216: TEN Input Slew Rate Definition

tR_TEN

tF_TEN

VIH(AC)_TENmin

VIL(AC)_TENmin

VIH(DC)_TENmin

VIL(DC)_TENmin

Table 95: CT Type-A Input Levels

Parameter Symbol Min Max Unit Note

CTipA AC input high voltage VIH(AC) VREF + 200 VDD11V 2, 3

CTipA DC input high voltage VIH(DC) VREF + 150 VDD V 2, 3

CTipA DC input low voltage VIL(DC) VSS VREF - 150 V 2, 3

CTipA AC input low voltage VIL(AC) VSS11VREF - 200 V 2, 3

CTipA falling time tF_CTipA – 5 ns 2

CTipA rising time tR_CTipA – 5 ns 2

Notes: 1. Refer to Overshoot and Undershoot Specifications.

2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,

CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR.

3. VREFCA = 0.5 × VDD.

Figure 217: CT Type-A Input Slew Rate Definition

VIH(AC)_CTipAmin

VIL(AC)_CTipAmax

VIH(DC)_CTipAmin

VIL(DC)_CTipAmax

tR_CTipA

tF_CTipA

VREFCA

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Table 96: CT Type-B Input Levels

Parameter Symbol Min Max Unit Note

CTipB AC input high voltage VIH(AC) VREF + 300 VDD11V 2, 3

CTipB DC input high voltage VIH(DC) VREF + 200 VDD V 2, 3

CTipB DC input low voltage VIL(DC) VSS VREF - 200 V 2, 3

CTipB AC input low voltage VIL(AC) VSS11VREF - 300 V 2, 3

CTipB falling time tF_CTipB – 5 ns 2

CTipB rising time tR_CTipB – 5 ns 2

Notes: 1. Refer to Overshoot and Undershoot Specifications.

2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n.

3. VREFDQ should be 0.5 × VDD

Figure 218: CT Type-B Input Slew Rate Definition

IH(AC)_CTipBmin

IL(AC)_CTipBmax

IH(DC)_CTipBmin

IL(DC)_CTipBmax

R_CTipB

F_CTipB

REFDQ

Table 97: CT Type-C Input Levels (CMOS)

Parameter Symbol Min Max Unit Note

CTipC AC input high voltage VIH(AC)_CTipC 0.8 × VDD VDD1V2

CTipC DC input high voltage VIH(DC)_CTipC 0.7 × VDD VDD V2

CTipC DC input low voltage VIL(DC)_CTipC VSS 0.3 × VDD V2

CTipC AC input low voltage VIL(AC)_CTipC VSS10.2 × VDD V2

CTipC falling time tF_CTipC – 1 0 ns 2

CTipC rising time tR_CTipC – 1 0 ns 2

Notes: 1. Refer to Overshoot and Undershoot Specifications.

2. CT Type-C inputs: Alert_n.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Figure 219: CT Type-C Input Slew Rate Definition

tR_TEN

tF_TEN

VIH(AC)_TENmin

VIL(AC)_TENmin

VIH(DC)_TENmin

VIL(DC)_TENmin

Table 98: CT Type-D Input Levels

Parameter Symbol Min Max Unit Note

CTipD AC input high voltage VIH(AC)_CTipD 0.8 × VDD VDD V4

CTipD DC input high voltage VIH(DC)_CTipD 0.7 × VDD VDD V2

CTipD DC input low voltage VIL(DC)_CTipD VSS 0.3 × VDD V1

CTipD AC input low voltage VIL(AC)_CTipD VSS 0.2 × VDD V5

Rising time tR_RESET – 1 μs 3

RESET pulse width - after power-up tPW_RESET_S 1 – μs

RESET pulse width - during power-up tPW_RESET_L 200 – μs

Notes: 1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RE-

SET during tPW_RESET, otherwise, the DRAM may not be reset.

2. After RESET_n is registered HIGH, the RESET_n level must be maintained above

VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n

signal LOW.

3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-

gated as much as possible.

4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.

5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.

6. CT Type-D inputs: RESET_n; same requirements as in normal mode.

Figure 220: CT Type-D Input Slew Rate Definition

tR_RESET

tPW_RESET

VIH(AC)_RESETmin

VIL(AC)_RESETmax

VIH(DC)_RESETmin

VIL(DC)_RESETmax

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

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Electrical Characteristics – AC and DC Differential Input Measurement

Levels

Differential Inputs

Figure 221: Differential AC Swing and “Time Exceeding AC-Level” tDVAC

VIH,diff(AC)min

0.0

VIL,diff,max

tDVAC

VIH,diff,min

VIL,diff(AC)max

Half cycle tDVAC

CK_t, CK_c

Notes: 1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope.

2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.

Table 99: Differential Input Swing Requirements for CK_t, CK_c

Parameter

Sym-

bol

DDR4-1600 /

1866 / 2133

DDR4-2400 /

2666 DDR4-2933 DDR4-3200

Unit

Note

Min Max Min Max Min Max Min Max

Differential input high VIHdiff 150 Note 3 135 Note 3 125 Note 3 110 Note 3 mV 1

Differential input low VILdiff Note 3 –150 Note 3 -135 Note 3 -125 Note 3 -110 mV 1

Differential input high

(AC)

VIH-

diff(AC)

2 ×

(VIH(AC)

- VREF)

Note 3 2 ×

(VIH(AC)

- VREF)

Note 3 2 ×

(VIH(AC)

- VREF)

Note 3 2 ×

(VIH(AC)

- VREF)

Note 3 V 2

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

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Table 99: Differential Input Swing Requirements for CK_t, CK_c (Continued)

Parameter

Sym-

bol

DDR4-1600 /

1866 / 2133

DDR4-2400 /

2666 DDR4-2933 DDR4-3200

Unit

Note

Min Max Min Max Min Max Min Max

Differential input low

(AC)

VIL-

diff(AC)

Note 3 2 ×

(VIL(AC) -

VREF)

Note 3 2 ×

(VIL(AC) -

VREF)

Note 3 2 ×

(VIL(AC) -

VREF)

Note 3 2 ×

(VIL(AC) -

VREF)

Notes: 1. Used to define a differential signal slew-rate.

2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.

3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be

within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as

the limitations for overshoot and undershoot.

Table 100: Minimum Time AC Time tDVAC for CK

Slew Rate (V/ns)

tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|

200mV TBDmV

>4.0 120 TBD

4.0 115 TBD

3.0 110 TBD

2.0 105 TBD

1.9 100 TBD

1.6 95 TBD

1.4 90 TBD

1.2 85 TBD

1.0 80 TBD

<1.0 80 TBD

Note: 1. Below VIL(AC).

Single-Ended Requirements for CK Differential Signals

Each individual component of a differential signal (CK_t, CK_c) has to comply with cer-

tain requirements for single-ended signals. CK_t and CK_c have to reach approximately

VSEHmin/VSEL,max, which are approximately equal to the AC levels VIH(AC) and VIL(AC) for

ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might

differ per speed-bin, and so on. For example, if a value other than 100mV is used for

ADD/CMD VIH(AC) and VIL(AC) signals, then these AC levels also apply for the single-

ended signals CK_t and CK_c.

While ADD/CMD signal requirements are with respect to VREFCA, the single-ended com-

ponents of differential signals have a requirement with respect to VDD/2; this is nomi-

nally the same. The transition of single-ended signals through the AC levels is used to

measure setup time. For single-ended components of differential signals the require-

ment to reach VSEL,max/VSEH,min has no bearing on timing, but adds a restriction on the

common mode characteristics of these signals.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

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Figure 222: Single-Ended Requirements for CK

VSS or VSSQ

VDD or VDDQ

VSEL,max

VSEH,min

VSEH

VSEL

VDD/2 or VDDQ/2

Table 101: Single-Ended Requirements for CK

Parameter Symbol

DDR4-1600 /

1866 / 2133 DDR4-2400 / 2666 DDR4-2933 / 3200

Unit NotesMin Max Min Max

Single-ended high level for

CK_t, CK_c

VSEH VDD/2 +

0.100

Note 3 VDD/2 +

0.095

Note 3 VDD/2 +

0.085

Note 3 V 1, 2

Single-ended low level for

CK_t, CK_c

VSEL Note 3 VDD/2 -

0.100

Note 3 VDD/2 -

0.095

Note 3 VDD/2 -

0.085

V 1, 2

Notes: 1. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.

2. ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA.

3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be

within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as

the limitations for overshoot and undershoot.

Slew Rate Definitions for CK Differential Input Signals

Table 102: CK Differential Input Slew Rate Definition

Description

Measured

Defined byFrom To

Differential input slew rate for rising edge VIL,diff,max VIH,diff,min |VIH,diff,min - VIL,diff,max_˂TRdiff

Differential input slew rate for falling edge VIH,diff,min VIL,diff,max |VIH,diff,min - VIL,diff,max_˂TFdiff

Note: 1. The differential signal CK_t, CK_c must be monotonic between these thresholds.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

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Figure 223: Differential Input Slew Rate Definition for CK_t, CK_c

TFdiff

VIH,diff,min

VIL,diff,max

CK Differential Input Voltage

TRdiff

CK Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect

to clock and strobe, each cross point voltage of differential input signal CK_t, CK_c must

meet the requirements shown below. The differential input cross point voltage VIX(CK) is

measured from the actual cross point of true and complement signals to the midlevel

between VDD and VSS.

Figure 224: VIX(CK) Definition

VIX(CK)

VSEH VSEL

VIX(CK)

CK_t

VSS

VDD/2

CK_c

VDD

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

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Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400

Parameter Sym Input Level

DDR4-1600, 1866, 2133, 2400

Min Max

Differential input

cross point volt-

age relative to

VDD/2 for CK_t,

CK_c

VIX(CK) VSEH > VDD/2 + 145mV N/A 120mV

VDD/2 + 100mV ื VSEH ื VDD/2 + 145mV N/A (VSEH - VDD/2) - 25mV

VDD/2 - 145mV ื VSEL ื VDD/2 - 100mV –(VDD/2 - VSEL) + 25mV N/A

VSEL < VDD/2 - 145mV –120mV N/A

Table 104: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200

Parameter Sym Input Level

DDR4-2666, 2933, 3200

Min Max

Differential input

cross point volt-

age relative to

VDD/2 for CK_t,

CK_c

VIX(CK) VSEH > VDD/2 + 145mV N/A 110mV

VDD/2 + 90mV ื VSEH ื VDD/2 + 145mV N/A (VSEH - VDD/2) - 30mV

VDD/2 - 145mV ื VSEL ื VDD/2 - 90mV –(VDD/2 - VSEL) + 30mV N/A

VSEL < VDD/2 - 145mV –110mV N/A

DQS Differential Input Signal Definition and Swing Requirements

Figure 225: Differential Input Signal Definition for DQS_t, DQS_c

Half cycle

VIL,diff,peak

0.0V

DQS_t, DQS_c: Differential Input Voltage

VIH,diff,peak

Half cycle

Table 105: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c

Parameter Symbol

DDR4-1600, 1866,

2133 DDR4-2400

Unit NotesMin Max Min Max

Peak differential input high voltage VIH,diff,peak 186 VDDQ 160 VDDQ mV 1, 2

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

CCMTD-1725822587-9875

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Table 105: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c

(Continued)

Parameter Symbol

DDR4-1600, 1866,

2133 DDR4-2400

Unit NotesMin Max Min Max

Peak differential input low voltage VIL,diff,peak VSSQ –186 VSSQ –160 mV 1, 2

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded

within allowed overshoot and undershoot limits.

2. Minimum value point is used to determine differential signal slew-rate.

Table 106: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c

Parameter Symbol

DDR4-2666 DDR4-2933 DDR4-3200

Unit NotesMin Max Min Max Min Max

Peak differential input high volt-

age

VIH,diff,peak 150 VDDQ 145 VDDQ 140 VDDQ mV 1, 2

Peak differential input low volt-

age

VIL,diff,peak VSSQ –150 VSSQ –145 VSSQ –140 mV 1, 2

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded

within allowed overshoot and undershoot limits.

2. Minimum value point is used to determine differential signal slew-rate.

The peak voltage of the DQS signals are calculated using the following equations:

VIH,dif,Peak voltage = MAX(ft)

VIL,dif,Peak voltage = MIN(ft)

(ft) = DQS_t, DQS_c.

The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the

±35% window of the exempt non-monotonic signaling shall be the smallest peak volt-

age observed in all UIs.

Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Sig-

naling

DQS_t

MIN(ft)MAX(ft)

DQS_c

DQS_t, DQS_c: Single-Ended Input Voltages

+50%

–50%

+35%

–35%

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

CCMTD-1725822587-9875

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DQS Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with re-

spect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must

meet VIX_DQS,ratio in the table below. The differential input cross point voltage VIX_DQS

(VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c

relative to the VDQS,mid of the DQS_t and DQS_c signals.

VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t

and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the low-

est horizontal tangent above VDQS,mid of the transitioning DQS signals and the highest

horizontal tangent below VDQS,mid of the transitioning DQS signals. A non-monotonic

transitioning signal’s ledge is exempt or not used in determination of a horizontal tan-

gent provided the said ledge occurs within ±35% of the midpoint of either VIH.DIFF.Peak

voltage (DQS_t rising) or VIL.DIFF.Peak voltage (DQS_c rising), as shown in the figure be-

low.

A secondary horizontal tangent resulting from a ring-back transition is also exempt in

determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is

derived from its negative slope to zero slope transition (point A in the figure below), and

a ring-back’s horizontal tangent is derived from its positive slope to zero slope transi-

tion (point B in the figure below) and is not a valid horizontal tangent; a rising transi-

tion’s horizontal tangent is derived from its positive slope to zero slope transition (point

C in the figure below), and a ring-back’s horizontal tangent derived from its negative

slope to zero slope transition (point D in the figure below) and is not a valid horizontal

tangent.

Figure 227: VIXDQS Definition

DQS_t, DQS_c: Single-Ended Input Voltages

DQS_t

VIX_DQS,FR

VIX_DQS,RF

VDQS_trans

VDQS_trans/2

Lowest horizontal tanget above VDQS,mid

of the transitioning signals

Highest horizontal tanget below VDQS,mid

of the transitioning signals

VSSQ

VDQS,mid

DQS_c

Table 107: Cross Point Voltage For Differential Input Signals DQS

Parameter Symbol

DDR4-1600, 1866, 2133, 2400,

2666, 2933, 3200

Unit Notes

Min Max

DQS_t and DQS_c crossing relative to the

midpoint of the DQS_t and DQS_c signal

swings

VIX_DQS,ratio – 25 % 1, 2

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

CCMTD-1725822587-9875

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Table 107: Cross Point Voltage For Differential Input Signals DQS (Continued)

Parameter Symbol

DDR4-1600, 1866, 2133, 2400,

2666, 2933, 3200

Unit NotesMin Max

VDQS,mid to Vcent(midpoint) offset VDQS,mid_to_Vcent – Note 3 mV 2

Notes: 1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is

the difference between the lowest horizontal tangent above VDQS,midd of the transition-

ing DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning

DQS signals.

2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) ob-

tained during VREF Training if the DQS and DQs drivers and paths are matched.

3. The maximum limit shall not exceed the smaller of VIH,diff,DQS minimum limit or 50mV.

Slew Rate Definitions for DQS Differential Input Signals

Table 108: DQS Differential Input Slew Rate Definition

Description

Measured

Defined byFrom To

Differential input slew rate for rising edge V IL,diff,DQS V IH,diff,DQS |VIH,diff,DQS - VIL,diff,DQS_˂TRdiff

Differential input slew rate for falling edge V IH,diff,DQS V IL,diff,DQS |VIHdiffDQS - VIL,diff,DQS_˂TFdiff

Note: 1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds.

Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c

TFdiff TR

diff VIL,diff,peak

0.0V

DQS_t, DQS_c: Differential Input Voltage

VIH,diff,peak

VIH,diff,DQS

VIL,diff,DQS

Table 109: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,

DQS_c

Parameter Symbol

DDR4-1600, 1866, 2133 DDR4-2400

Unit NotesMin Max Min Max

Peak differential input high voltage VIH,diff,peak 186 VDDQ 160 VDDQ mV 1

Differential input high voltage VIH,diff,DQS 136 – 130 – mV 2, 3

Differential input low voltage VIL,diff,DQS – –136 – –130 mV 2, 3

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

CCMTD-1725822587-9875

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Table 109: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,

DQS_c (Continued)

Parameter Symbol

DDR4-1600, 1866, 2133 DDR4-2400

Unit NotesMin Max Min Max

Peak differential input low voltage VIL,diff,peak -VDDQ –186 -VDDQ –160 mV 1

DQS differential input slew rate SRIdiff 3.0 18 3.0 18 V/ns 4, 5

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded

within allowed overshoot and undershoot limits.

2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.

3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.

4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |

VIL,diff,min - VIH,diff,max_˂TRdiff.

5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |

VIL,diff,min - VIH,diff,max_˂TFdiff.

Table 110: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t,

DQS_c

Parameter Symbol

DDR4-2666 DDR4-2933 DDR4-3200

Unit NotesMin Max Min Max Min Max

Peak differential input

high voltage

VIH,diff,peak 150 VDDQ 145 VDDQ 140 VDDQ mV 1

Differential input high

voltage

VIH,diff,DQS 130 – 115 – 110 – mV 2, 3

Differential input low

voltage

VIL,diff,DQS – –130 – –115 – –110 mV 2, 3

Peak differential input

low voltage

VIL,diff,peak VSSQ –150 VSSQ –145 VSSQ –140 mV 1

DQS differential input

slew rate

SRIdiff 2.5 18 2.5 18 2.5 18 V/ns 4, 5

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded

within allowed overshoot and undershoot limits.

2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.

3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.

4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |

VIL,diff,min - VIH,diff,max_˂TRdiff.

5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |

VIL,diff,min - VIH,diff,max_˂TFdiff.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-

urement Levels

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Electrical Characteristics – Overshoot and Undershoot Specifications

Address, Command, and Control Overshoot and Undershoot Specifications

Table 111: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications

Description

DDR4-

1600

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200 Unit

Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0)

Area A: Maximum peak amplitude above VDD

absolute MAX

0.06 0.06 0.06 0.06 0.06 0.06 0.06 V

Area B: Amplitude allowed between VDD and

VDD absolute MAX

0.24 0.24 0.24 0.24 0.24 0.24 0.24 V

Area C: Maximum peak amplitude allowed for

undershoot below VSS

0.30 0.30 0.30 0.30 0.30 0.30 0.30 V

Area A maximum overshoot area per 1tCK 0.0083 0.0071 0.0062 0.0055 0.0055 0.0055 0.0055 V/ns

Area B maximum overshoot area per 1tCK 0.2550 0.2185 0.1914 0.1699 0.1699 0.1699 0.1699 V/ns

Area C maximum undershoot area per 1tCK 0.2644 0.2265 0.1984 0.1762 0.1762 0.1762 0.1762 V/ns

Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition

VDD absolute MAX

Absolute MAX overshoot

Overshoot area above VDD absolute MAX

Overshoot area below VDD absolute MAX

and above VDD MAX

Undershoot area below VSS

1tCK

Volts (V)

VDD

VSS

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – Overshoot and Undershoot Specifi-

cations

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Clock Overshoot and Undershoot Specifications

Table 112: CK Overshoot and Undershoot/ Specifications

Description

DDR4-

1600

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200 Unit

CLK_t, CLK_n

Area A: Maximum peak amplitude above VDD

absolute MAX

0.06 0.06 0.06 0.06 0.06 0.06 0.06 V

Area B: Amplitude allowed between VDD and

VDD absolute MAX

0.24 0.24 0.24 0.24 0.24 0.24 0.24 V

Area C: Maximum peak amplitude allowed for

undershoot below VSS

0.30 0.30 0.30 0.30 0.30 0.30 0.30 V

Area A maximum overshoot area per 1UI 0.0038 0.0032 0.0028 0.0025 0.0025 0.0025 0.0025 V/ns

Area B maximum overshoot area per 1UI 0.1125 0.0964 0.0844 0.0750 0.0750 0.0750 0.0750 V/ns

Area C maximum undershoot area per 1UI 0.1144 0.0980 0.0858 0.0762 0.0762 0.0762 0.0762 V/ns

Figure 230: CK Overshoot and Undershoot Definition

VDD absolute MAX

Absolute MAX overshoot

Overshoot area above VDD absolute MAX

Overshoot area below VDD absolute MAX

and above VDD MAX

Undershoot area below VSS

1UI

Volts (V)

VDD

VSS

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – Overshoot and Undershoot Specifi-

cations

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Data, Strobe, and Mask Overshoot and Undershoot Specifications

Table 113: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications

Description

DDR4-

1600

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200 Unit

DQS_t, DQS_n, LDQS_t, LDQS_n, UDQS_t, UDQS_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI,

Area A: Maximum peak amplitude above VDDQ

absolute MAX

0.16 0.16 0.16 0.16 0.16 0.16 0.16 V

Area B: Amplitude allowed between VDDQ and

VDDQ absolute MAX

0.24 0.24 0.24 0.24 0.24 0.24 0.24 V

Area C: Maximum peak amplitude allowed for

undershoot below VSSQ

0.30 0.30 0.30 0.30 0.30 0.30 0.30 V

Area D: Maximum peak amplitude below VSSQ

absolute MIN

0.10 0.10 0.10 0.10 0.10 0.10 0.10 V

Area A maximum overshoot area per 1UI 0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100 V/ns

Area B maximum overshoot area per 1UI 0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700 V/ns

Area C maximum undershoot area per 1UI 0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700 V/ns

Area D maximum undershoot area per 1UI 0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100 V/ns

Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition

VDDQ absolute MAX

VSSQ absolute MIN

Absolute MAX overshoot

Absolute MAX undershoot

Overshoot area above VDDQ absolute MAX

Undershoot area below VSSQ absolute MIN

Overshoot area below VDDQ absolute MAX

and above VDDQ MAX

Undershoot area below VSSQ MIN and

above VSSQ absolute MIN

1UI

Volts (V)

VDDQ

VSSQ

Electrical Characteristics – AC and DC Output Measurement Levels

Single-Ended Outputs

Table 114: Single-Ended Output Levels

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

DC output high measurement level (for IV curve linearity) VOH(DC) 1.1 × VDDQ V

DC output mid measurement level (for IV curve linearity) VOM(DC) 0.8 × VDDQ V

DC output low measurement level (for IV curve linearity) VOL(DC) 0.5 × VDDQ V

AC output high measurement level (for output slew rate) VOH(AC) (0.7 + 0.15) × VDDQ V

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Measurement

Levels

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Table 114: Single-Ended Output Levels (Continued)

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

AC output low measurement level (for output slew rate) VOL(AC) (0.7 - 0.15) × VDDQ V

Note: 1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended

output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load

of 50˖ to VTT = VDDQ.

Using the same reference load used for timing measurements, output slew rate for fall-

ing and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-

ended signals.

Table 115: Single-Ended Output Slew Rate Definition

Description

Measured

Defined byFrom To

Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)@˂TRse

Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)@˂TFse

Figure 232: Single-ended Output Slew Rate Definition

TRse

TFse

VOH(AC)

VOL(AC)

Single-Ended Output Voltage (DQ)

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Measurement

Levels

CCMTD-1725822587-9875

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Table 116: Single-Ended Output Slew Rate

For RON = RZQ/7

Parameter Symbol

DDR4-1600/ 1866 / 2133 /

2400 DDR4-2666 DDR4-2933 / 3200

UnitMin Max Min Max Min Max

Single-ended output

slew rate

SRQse 4 9 4949V/ns

Notes: 1. SR = slew rate; Q = query output; se = single-ended signals.

2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte

lane:

• Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer-

tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-

nals in the same byte lane are static (they stay at either HIGH or LOW).

• Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer-

tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-

nals in the same byte lane are switching into the opposite direction (from LOW-to-

HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the

opposite direction, the standard maximum limit of 9 V/ns applies.

Differential Outputs

Table 117: Differential Output Levels

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

AC differential output high measurement level (for output slew

rate)

VOH,diff(AC) 0.3 × VDDQ V

AC differential output low measurement level (for output slew

rate)

VOL,diff(AC) –0.3 × VDDQ V

Note: 1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended out-

put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of

50˖ to VTT = VDDQ at each differential output.

Using the same reference load used for timing measurements, output slew rate for fall-

ing and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for dif-

ferential signals.

Table 118: Differential Output Slew Rate Definition

Description

Measured

Defined byFrom To

Differential output slew rate for rising edge VOL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)@˂TRdiff

Differential output slew rate for falling edge VOH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)@˂TFdiff

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Measurement

Levels

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Figure 233: Differential Output Slew Rate Definition

TRdiff

TFdiff

VOH,diff(AC)

VOL,diff(AC)

Differential Input Voltage (DQS_t, DQS_c)

Table 119: Differential Output Slew Rate

For RON = RZQ/7

Parameter Symbol

DDR4-1600 / 1866 /

2133 / 2400 DDR4-2666 DDR4-2933 / 3200

UnitMin Max Min Max Min Max

Differential output slew

rate

SRQdiff 8 18 8 18 8 18 V/ns

Note: 1. SR = slew rate; Q = query output; diff = differential signals.

Reference Load for AC Timing and Output Slew Rate

The effective reference load of 50˖ to VTT = VDDQ and driver impedance of RZQ/7 for

each output was used in defining the relevant AC timing parameters of the device as

well as output slew rate measurements.

RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC

timing parameter values of the device. The maximum DC high level of output signal =

1.0 × VDDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × VDDQ = 0.4 ×

VDDQ.

The nominal reference level of an output signal can be approximated by the following:

The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × VDDQ = 0.7 ×

VDDQ. The actual reference level of output signal might vary with driver RON and refer-

ence load tolerances. Thus, the actual reference level or midpoint of an output signal is

at the widest part of the output signal’s eye.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Measurement

Levels

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Figure 234: Reference Load For AC Timing and Output Slew Rate

Timing reference point

DQ, DQS_t, DQS_c,

DM, TDQS_t, TDQS_c

CK_t, CK_c DUT

VTT = VDDQ

VDDQ

VSSQ

RTT = 50ȍ

Connectivity Test Mode Output Levels

Table 120: Connectivity Test Mode Output Levels

Parameter Symbol DDR4-1600 to DDR4-3200 Unit

DC output high measurement level (for IV curve linearity) VOH(DC) 1.1 × VDDQ V

DC output mid measurement level (for IV curve linearity) VOM(DC) 0.8 × VDDQ V

DC output low measurement level (for IV curve linearity) VOL(DC) 0.5 × VDDQ V

DC output below measurement level (for IV curve linearity) VOB(DC) 0.2 × VDDQ V

AC output high measurement level (for output slew rate) VOH(AC) VTT + (0.1 × VDDQ)V

AC output low measurement level (for output slew rate) VOL(AC) VTT - (0.1 × VDDQ)V

Note: 1. Driver impedance of RZQ/7 and an effective test load of 50˖ to VTT = VDDQ.

Figure 235: Connectivity Test Mode Reference Test Load

Timing reference point

LDQS_t, LDQS_c, UDQS_t, UDQS_c,

DQ, DQS_t, DQS_c,

DM, LDM, HDM, TDQS_t, TDQS_c

CT_Inputs DUT 0.5 × VDDQ

VDDQ

VSSQ

RTT = 50 ȍ

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Measurement

Levels

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Figure 236: Connectivity Test Mode Output Slew Rate Definition

TFoutput_CT

VOH(AC)

VOL(AC)

VTT

0.5 x VDD

output_CT

Table 121: Connectivity Test Mode Output Slew Rate

Parameter Symbol

DDR4-1600 / 1866 /

2133 / 2400 DDR4-2666

DDR4-2933 /

3200

UnitMin Max Min Max Min Max

Output signal falling time TF_output_CT – 10 – 10 – 10 ns/V

Output signal rising time TR_output_CT – 10 – 10 – 10 ns/V

Electrical Characteristics – AC and DC Output Driver Characteristics

Connectivity Test Mode Output Driver Electrical Characteristics

The DDR4 driver supports special values during connectivity test mode. These RON val-

ues are referenced in this section. A functional representation of the output buffer is

shown in the figure below.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

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Figure 237: Output Driver During Connectivity Test Mode

VDDQ

VSSQ

Chip in drive mode

VOUT

IOUT

RONPU_CT

RONPD_CT

Output driver

other

circuitry

RCV,

...

IPU_CT

IPD_CT

The output driver impedance, RON, is determined by the value of the external reference

resistor RZQ as follows: RON = RZQ/7. This targets 34˖ with nominal RZQ ˖; however,

connectivity test mode uses uncalibrated drivers and only a maximum target is defined.

Mismatch between pull up and pull down is undefined.

The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as

follows:

RONPu_CT when RONPd_CT is off:

52138B&7 

9''49287

,287

RONPD_CT when RONPU_CT is off:

5213'B&7 

9287

,287

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 301 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 122: Output Driver Electrical Characteristics During Connectivity Test Mode

Assumes RZQ ˖; ZQ calibration not required

RON,nom_CT Resistor VOUT Min Nom Max Unit

˖

RONPD_CT

VOB(DC) = 0.2 × VDDQ N/A N/A 1.9 RZQ/7

VOL(DC) = 0.5 × VDDQ N/A N/A 2.0 RZQ/7

VOM(DC) = 0.8 × VDDQ N/A N/A 2.2 RZQ/7

VOH(DC) = 1.1 × VDDQ N/A N/A 2.5 RZQ/7

RONPU_CT

VOB(DC) = 0.2 × VDDQ N/A N/A 1.9 RZQ/7

VOL(DC) = 0.5 × VDDQ N/A N/A 2.0 RZQ/7

VOM(DC) = 0.8 × VDDQ N/A N/A 2.2 RZQ/7

VOH(DC) = 1.1 × VDDQ N/A N/A 2.5 RZQ/7

Output Driver Electrical Characteristics

The DDR4 driver supports two RON values. These RON values are referred to as strong

mode (low RON˖) and weak mode (high RON˖). A functional representation of

the output buffer is shown in the figure below.

Figure 238: Output Driver: Definition of Voltages and Currents

VDDQ

VSSQ

Chip in drive mode

VOUT

IOUT

RONPU

RONPD

Output driver

other

circuitry

RCV,

...

IPU

IPD

The output driver impedance, RON, is determined by the value of the external reference

resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nomi-

nal 34.3˖±10% or 48˖±10% with nominal RZQ ˖

The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as fol-

lows:

RONPu when RONPd is off:

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

CCMTD-1725822587-9875

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RONPU =

VDDQ - VOUT

IOUT

RONPD when RONPU is off:

RONPD =

VOUT

IOUT

Table 123: Strong Mode (34˖

) Output Driver Electrical Characteristics

Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration

RON,nom Resistor VOUT Min Nom Max Unit Notes

˖

RON34PD

VOL(DC) = 0.5 × VDDQ 0.73 1.00 1.10 RZQ/7 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.83 1.00 1.10 RZQ/7 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.83 1.00 1.25 RZQ/7 1, 2, 3

RON34PU

VOL(DC) = 0.5 × VDDQ 0.90 1.00 1.25 RZQ/7 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.90 1.00 1.10 RZQ/7 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.80 1.00 1.10 RZQ/7 1, 2, 3

Mismatch between pull-up and pull-

down, MMPUPD

VOM(DC) = 0.8 × VDDQ 10 – 23 % 1, 2, 3, 4,

6, 7

Mismatch between DQ to DQ within

byte variation pull-up, MMPUdd

VOM(DC) = 0.8 × VDDQ – – 10 % 1, 2, 3, 4,

Mismatch between DQ to DQ within

byte variation pull-down, MMPDdd

VOM(DC) = 0.8 × VDDQ - – 10 % 1, 2, 3, 4,

6, 7

Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature.

For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity.

2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =

VSS.

3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8

× VDDQ. Other calibration schemes may be used to achieve the linearity specification

shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.

4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and

DQS_c (characterized).

5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:

Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val-

ue:

MMPUPD =× 100

RONPU - RONPD

RON,nom

6. RON variance range ratio to RON nominal value in a given component, including DQS_t

and DQS_c:

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

CCMTD-1725822587-9875

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MMPUDD = × 100

RONPU,max - RONPU,min

RON,nom

MMPDDD = × 100

RONPD,max - RONPD,min

RON,nom

7. The lower and upper bytes of a x16 are each treated on a per byte basis.

8. The minimum values are derated by 9% when the device operates between –40°C and

0°C (TC).

Table 124: Weak Mode (48˖

) Output Driver Electrical Characteristics

Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration

RON,nom Resistor VOUT Min Nom Max Unit Notes

˖RON48PD VOL(DC) = 0.5 × VDDQ 0.73 1.00 1.10 RZQ/5 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.83 1.00 1.10 RZQ/5 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.83 1.00 1.25 RZQ/5 1, 2, 3

RON48PU VOL(DC) = 0.5 × VDDQ 0.90 1.00 1.25 RZQ/5 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.90 1.00 1.10 RZQ/5 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.80 1.00 1.10 RZQ/5 1, 2, 3

Mismatch between pull-up and

pull-down, MMPUPD

VOM(DC) = 0.8 × VDDQ 10 – 23 % 1, 2, 3, 4,

6, 7

Mismatch between DQ to DQ

within byte variation pull-up,

MMPUdd

VOM(DC) = 0.8 × VDDQ – – 10 % 1, 2, 3, 4, 5

Mismatch between DQ to DQ

within byte variation pull-down,

MMPDdd

VOM(DC) = 0.8 × VDDQ – – 10 % 1, 2, 3, 4,

6, 7

Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature.

For the behavior of the tolerance limits if temperature or voltage changes after calibra-

tion, see following section on voltage and temperature sensitivity.

2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =

VSS.

3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8

× VDDQ. Other calibration schemes may be used to achieve the linearity specification

shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.

4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and

DQS_c (characterized).

5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:

Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val-

ue:

MMPUPD =× 100

RONPU - RONPD

RON,nom

6. RON variance range ratio to RON nominal value in a given component, including DQS_t

and DQS_c:

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

CCMTD-1725822587-9875

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MMPUDD = × 100

RONPU,max - RONPU,min

RON,nom

MMPDDD = × 100

RONPD,max - RONPD,min

RON,nom

7. The lower and upper bytes of a x16 are each treated on a per byte basis.

8. The minimum values are derated by 9% when the device operates between –40°C and

0°C (TC).

Output Driver Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen ac-

cording to the equations and tables below.

˂T = T - T(@calibration); ˂V = VDDQ - VDDQ(@ calibration); VDD = VDDQ

Table 125: Output Driver Sensitivity Definitions

Symbol Min Max Unit

RONPU@ VOH(DC) 0.6 - dRONdTH × |˂T| - dRONdVH × |˂V| 1.1 _ dRONdTH × |˂T| + dRONdVH × |˂V| RZQ/6

RON@ VOM(DC) 0.9 - dRONdTM × |˂T| - dRONdVM × |˂V| 1.1 + dRONdTM × |˂T| + dRONdVM × |˂V| RZQ/6

RONPD@ VOL(DC) 0.6 - dRONdTL × |˂T| - dRONdVL × |˂V| 1.1 + dRONdTL × |˂T| + dRONdVL × |˂V| RZQ/6

Table 126: Output Driver Voltage and Temperature Sensitivity

Symbol

Voltage and Temperature Range

UnitMin Max

dRONdTM 0 1.5 %/°C

dRONdVM 0 0.15 %/mV

dRONdTL 0 1.5 %/°C

dRONdVL 0 0.15 %/mV

dRONdTH 0 1.5 %/°C

dRONdVM 0 0.15 %/mV

Alert Driver

A functional representation of the alert output buffer is shown in the figure below. Out-

put driver impedance, RON, is defined as follows.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Output Driver Charac-

teristics

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 305 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 239: Alert Driver

Alert

VOUT

RONPD

'5$0

Alert driver

IPD

IOUT

VSSQ

RONPD when RONPU is off:

RONPD =

VOUT

IOUT

Table 127: Alert Driver Voltage

RON,nom Register VOUT Min Nom Max Unit

N/A RONPD VOL(DC) = 0.1 × VDDQ 0.3 N/A 1.2 RZQ/7

VOM(DC) = 0.8 × VDDQ 0.4 N/A 1.2 RZQ/7

VOH(DC) = 1.1 × VDDQ 0.4 N/A 1.4 RZQ/7

Note: 1. VDDQ voltage is at VDDQ(DC).

Electrical Characteristics – On-Die Termination Characteristics

ODT Levels and I-V Characteristics

On-die termination (ODT) effective resistance settings are defined and can be selected

by any or all of the following options:

• MR1[10:8] (RTT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40

ohms, and 34 ohms.

• MR2[11:9] (RTT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms.

• MR5[8:6] (RTT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40

ohms, and 34 ohms.

ODT is applied to the following inputs:

• x4: DQ, DM_n, DQS_t, and DQS_c inputs.

• x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs.

• x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs.

A functional representation of ODT is shown in the figure below.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

CCMTD-1725822587-9875

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Figure 240: ODT Definition of Voltages and Currents

VDDQ

VSSQ

Chip in termination mode

VOUT

IOUT

RTT

To other

circuitry

like RCV,

...

ODT

Table 128: ODT DC Characteristics

RTT VOUT Min Nom Max Unit Notes

240 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ 1, 2, 3

120 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/2 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/2 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/2 1, 2, 3

80 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/3 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/3 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/3 1, 2, 3

60 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/4 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/4 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/4 1, 2, 3

48 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/5 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/5 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/5 1, 2, 3

40 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/6 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/6 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/6 1, 2, 3

34 ohm VOL(DC) = 0.5 × VDDQ 0.9 1 1.25 RZQ/7 1, 2, 3

VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 RZQ/7 1, 2, 3

VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 RZQ/7 1, 2, 3

DQ-to-DQ mismatch

within byte

VOM(DC) = 0.8 × VDDQ 0 – 10 % 1, 2, 4, 5, 6

Notes: 1. The tolerance limits are specified after calibration to 240 ohm ±1% resistor with stable

voltage and temperature. For the behavior of the tolerance limits if temperature or

voltage changes after calibration, see ODT Temperature and Voltage Sensitivity.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 307 Micron Technology, Inc. reserves the right to change products or specifications without notice.

2. Micron recommends calibrating pull-up ODT resistors at 0.8 × VDDQ. Other calibration

schemes may be used to achieve the linearity specification shown here.

3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS.

4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t

and DQS_c.

5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t

and DQS_c.

DQ-to-DQ mismatch = RTT(MAX) - RTT(MIN)

RTT(NOM)

× 100

6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes.

7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op-

erates between –40°C and 0°C (TC).

ODT Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen ac-

cording to the following equations and tables.

˂T = T - T(@ calibration); ˂V = VDDQ - VDDQ(@ calibration); VDD = VDDQ

Table 129: ODT Sensitivity Definitions

Parameter Min Max Unit

RTT@ 0.9 - dRTTdT × |˂T| - dRTTdV × |˂V| 1.6 + dRTTdTH × |˂T| + dRTTdVH × |˂V| RZQ/n

Table 130: ODT Voltage and Temperature Sensitivity

Parameter Min Max Unit

dRTTdT 0 1.5 %/°C

dRTTdV 0 0.15 %/mV

ODT Timing Definitions

The reference load for ODT timings is different than the reference load used for timing

measurements.

Figure 241: ODT Timing Reference Load

Timing reference point

DQ, DQS_t, DQS_c,

DM, TDQS_t, TDQS_c

CK_t, CK_c

DUT

DDQ

SSQ

= 50ȍ

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 308 Micron Technology, Inc. reserves the right to change products or specifications without notice.

ODT Timing Definitions

Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 131 (page 309) and

shown in Figure 242 (page 310) and Figure 244 (page 311). Measurement reference set-

tings are provided in the subsequent Table 132 (page 309).

The tADC for the dynamic ODT case and read disable ODT cases are represented by

tADC of Direct ODT Control case.

Table 131: ODT Timing Definitions

Parameter Begin Point Definition End Point Definition Figure

tADC Rising edge of CK_t, CK_c defined by the end point of

DODTLoff

Extrapolated point at VRTT,nom Figure 242

(page 310)

Rising edge of CK_t, CK_c defined by the end point of

DODTLon

Extrapolated point at VSSQ Figure 242

(page 310)

Rising edge of CK_t, CK_c defined by the end point of

ODTLcnw

Extrapolated point at VRTT,nom Figure 243

(page 310)

Rising edge of CK_t, CK_c defined by the end point of

ODTLcwn4 or ODTLcwn8

Extrapolated point at VSSQ Figure 243

(page 310)

tAONAS Rising edge of CK_t, CK_c with ODT being first registered

HIGH

Extrapolated point at VSSQ Figure 244

(page 311)

tAOFAS Rising edge of CK_t, CK_c with ODT being first registered

LOW

Extrapolated point at VRTT,nom Figure 244

(page 311)

Table 132: Reference Settings for ODT Timing Measurements

Measure

Parameter RTT(Park) RTT(NOM) RTT(WR) VSW1 VSW2 Note

tADC Disable RZQ˖– 0.20V 0.40V 1, 2, 4

–R

ZQ˖High-Z 0.20V 0.40V 1, 3, 5

tAONAS Disable RZQ˖– 0.20V 0.40V 1, 2, 6

tAOFAS Disable RZQ˖– 0.20V 0.40V 1, 2, 6

Notes: 1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has

A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for

RTT(WR) setting.

2. ODT state change is controlled by ODT pin.

3. ODT state change is controlled by a WRITE command.

4. Refer to Figure 242 (page 310).

5. Refer to Figure 243 (page 310).

6. Refer to Figure 244 (page 311).

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

CCMTD-1725822587-9875

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Figure 242: tADC Definition with Direct ODT Control

tADC tADC

Begin point: Rising edge

of CK_t, CK_c defined

by the end point of

DODTLoff

DODTLoff Begin point: Rising edge

of CK_t, CK_c defined

by the end point of

DODTLon

End point: Extrapolated

point at VRTT,nom

End point: Extrapolated

point at VSSQ

VRTT,nom

VSSQ VSSQ

DQ, DM

DQS_t, DQS_c

TDQS_t, TDQS_c

CK_c

CK_t

Vsw2

Vsw1

Figure 243: tADC Definition with Dynamic ODT Control

tADC tADC

Begin point: Rising edge

of CK_t, CK_c defined

by the end point of

ODTLcnw

ODTLcnw Begin point: Rising edge

of CK_t, CK_c defined

by the end point of

ODTLcnw4 or ODTLcnw8

ODTLcnw4/8

End point: Extrapolated

point at VRTT,nom

End point: Extrapolated

point at VSSQ

VRTT,nom

VSSQ VSSQ

DQ, DM

DQS_t, DQS_c

TDQS_t, TDQS_c

CK_c

CK_t

Vsw2

Vsw1

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

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Figure 244: tAOFAS and tAONAS Definitions

tAOFAS tAONAS

Rising edge of CK_t, CK_c

with ODT being first

registered LOW

Rising edge of CK_t, CK_c

with ODT being first

registered HIGH

End point: Extrapolated

point at VRTT_NOM

End point: Extrapolated

point at VSSQ

VRTT,nom

VSSQ VSSQ

DQ, DM

DQS_t, DQS_c

TDQS_t, TDQS_c

CK_c

CK_t

Vsw2

Vsw1

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – On-Die Termination Characteristics

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DRAM Package Electrical Specifications

Table 133: DRAM Package Electrical Specifications for x4 and x8 Devices

Parameter Symbol

1600/1866/2133/

2400/2666 2933 3200

Unit NotesMin Max Min Max Min Max

Input/

output

Zpkg ZIO 45 85 48 85 48 85 ohm 1, 2, 4

Package delay TdIO 14 42 14 40 14 40 ps 1, 3, 4

Lpkg LIO – 3.3 – 3.3 – 3.3 nH 10

Cpkg CIO – 0.78 – 0.78 – 0.78 pF 11

DQS_t,

DQS_c

Zpkg ZIO DQS 45 85 48 85 48 85 ohm 1, 2

Package delay TdIO DQS 14 42 14 40 14 40 ps 1, 3

Delta Zpkg DZIO DQS – 10 – 10 – 10 ohm 1, 2, 6

Delta delay DTdIO DQS –5–5–5ps1, 3, 6

Lpkg LIO DQS – 3.3 – 3.3 – 3.3 nH 10

Cpkg CIO DQS – 0.78 – 0.78 – 0.78 pF 11

Input CTRL

pins

Zpkg ZI CTRL 50 90 50 90 50 90 ohm 1, 2, 8

Package delay TdI CTRL 14 42 14 40 14 40 ps 1, 3, 8

Lpkg LI CTRL – 3.4 – 3.4 – 3.4 nH 10

Cpkg CI CTRL – 0.7 – 0.7 – 0.7 pF 11

Input CMD

ADD pins

Zpkg ZI ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7

Package delay TdI ADD CMD 14 45 14 40 14 40 ps 1, 3, 7

Lpkg LI ADD CMD – 3.6 – 3.6 – 3.6 nH 10

Cpkg CI ADD CMD – 0.74 – 0.74 – 0.74 pF 11

CK_t, CK_c Zpkg ZCK 50 90 50 90 50 90 ohm 1, 2

Package delay TdCK 14 42 14 42 14 42 ps 1, 3

Delta Zpkg DZDCK – 10 – 10 – 10 ohm 1, 2, 5

Delta delay DTdDCK – 5 – 5 – 5 ps 1, 3, 5

Lpkg LI CLK – 3.4 – 3.4 – 3.4 nH 10

Cpkg CI CLK – 0.7 – 0.7 – 0.7 pF 11

ZQ Zpkg ZO ZQ – 100 – 100 – 100 ohm 1, 2

ZQ delay TdO ZQ 20 90 20 90 20 90 ps 1, 3

ALERT Zpkg ZO ALERT 40 100 40 100 40 100 ohm 1, 2

ALERT delay TdO ALERT 20 55 20 55 20 55 ps 1, 3

Notes: 1. This parameter is not subject to a production test; it is verified by design and characteri-

zation and are provided for reference; system signal simulations should not use these

values but use the Micron package model. The package parasitic (L and C) are validated

using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ

shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ,

VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.

2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a

given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).

8Gb: x4, x8, x16 DDR4 SDRAM

DRAM Package Electrical Specifications

CCMTD-1725822587-9875

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3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin

where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).

4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c.

5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c

for delay (Td).

6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO

(DQS_t), TdIO (DQS_c) for delay (Td).

7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n,

ACT_n, and PAR.

8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.

9. Package implementations will meet specification if the Zpkg and package delay fall

within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi-

mum values shown.

10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.

11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.

Table 134: DRAM Package Electrical Specifications for x16 Devices

Parameter Symbol

1600/1866/2133/

2400/2666 2933 3200

Unit NotesMin Max Min Max Min Max

Input/

output

Zpkg ZIO 45 85 45 85 45 85 ohm 1, 2, 4

Package delay TdIO 14 45 14 45 14 45 ps 1, 3, 4

Lpkg LIO – 3.4 – 3.4 – 3.4 nH 11

Cpkg CIO – 0.82 – 0.82 – 0.82 pF 11

LDQS_t/

LDQS_c/

UDQS_t/

UDQS_c

Zpkg ZIO DQS 45 85 45 85 45 85 ohm 1, 2

Package delay TdIO DQS 14 45 14 45 14 45 ps 1, 3

Lpkg LIO DQS – 3.4 – 3.4 – 3.4 nH 11

Cpkg CIO DQS – 0.82 – 0.82 – 0.82 pF 11

LDQS_t/

LDQS_c,

UDQS_t/

UDQS_c,

Delta Zpkg DZIO DQS – 10.5 – 10.5 – 10.5 ohm 1, 2, 6

Delta delay DTdIO DQS –5–5–5ps1, 3, 6

Input CTRL

pins

Zpkg ZI CTRL 50 90 50 90 50 90 ohm 1, 2, 8

Package delay TdI CTRL 14 42 14 42 14 42 ps 1, 3, 8

Lpkg LI CTRL – 3.4 – 3.4 – 3.4 nH 11

Cpkg CI CTRL – 0.7 – 0.7 – 0.7 pF 11

Input CMD

ADD pins

Zpkg ZI ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7

Package delay TdI ADD CMD 14 52 14 52 14 52 ps 1, 3, 7

Lpkg LI ADD CMD – 3.9 – 3.9 – 3.9 nH 11

Cpkg CI ADD CMD – 0.86 – 0.86 – 0.86 pF 11

CK_t, CK_c Zpkg ZCK 50 90 50 90 50 90 ohm 1, 2

Package delay TdCK 14 42 14 42 14 42 ps 1, 3

Delta Zpkg DZDCK – 10.5 – 10.5 – 10.5 ohm 1, 2, 5

Delta delay DTdDCK – 5 – 5 – 5 ps 1, 3, 5

8Gb: x4, x8, x16 DDR4 SDRAM

DRAM Package Electrical Specifications

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Table 134: DRAM Package Electrical Specifications for x16 Devices (Continued)

Parameter Symbol

1600/1866/2133/

2400/2666 2933 3200

Unit NotesMin Max Min Max Min Max

Input CLK Lpkg LI CLK – 3.4 – 3.4 – 3.4 nH 11

Cpkg CI CLK – 0.7 – 0.7 – 0.7 pF 11

ZQ Zpkg ZO ZQ – 100 – 100 – 100 ohm 1, 2

ZQ delay TdO ZQ 20 90 20 90 20 90 ps 1, 3

ALERT Zpkg ZO ALERT 40 100 40 100 40 100 ohm 1, 2

ALERT delay TdO ALERT 20 55 20 55 20 55 ps 1, 3

Notes: 1. This parameter is not subject to a production test; it is verified by design and characteri-

zation and are provided for reference; system signal simulations should not use these

values but use the Micron package model. The package parasitic (L and C) are validated

using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ

shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ,

VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.

2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a

given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).

3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin

where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).

4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c.

5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c

for delay (Td).

6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO

(DQS_t), TdIO (DQS_c) for delay (Td).

7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n,

ACT_n, and PAR.

8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.

9. Package implementations will meet specification if the Zpkg and package delay fall

within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi-

mum values shown.

10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.

11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.

8Gb: x4, x8, x16 DDR4 SDRAM

DRAM Package Electrical Specifications

CCMTD-1725822587-9875

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Table 135: Pad Input/Output Capacitance

Parameter Symbol

DDR4-1600,

1866, 2133

DDR4-2400,

2666 DDR4-2933 DDR4-3200

Unit NotesMin Max Min Max Min Max Min Max

Input/output capacitance:

DQ, DM, DQS_t, DQS_c,

TDQS_t, TDQS_c

CIO 0.55 1.4 0.55 1.15 0.55 1.00 0.55 1.00 pF 1, 2, 3

Input capacitance: CK_t and

CK_c

CCK 0.2 0.8 0.2 0.7 0.2 0.7 0.15 0.7 pF 2, 3

Input capacitance delta: CK_t

and CK_c

CDCK - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 6

Input/output capacitance del-

ta: DQS_t and DQS_c

CDDQS - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 5

Input capacitance: CTRL,

ADD, CMD input-only pins

CI0.2 0.8 0.2 0.7 0.2 0.6 0.15 0.55 pF 2, 3, 4

Input capacitance delta: All

CTRL input-only pins

CDI_CTRL –0.1 0.1 –0.1 0.1 –0.1 0.1 –0.1 0.1 pF 2, 3, 8,

Input capacitance delta: All

ADD/CMD input-only pins

CDI_ADD_CM

–0.1 0.1 –0.1 0.1 –0.1 0.1 –0.1 0.1 pF 1, 2, 10,

Input/output capacitance del-

ta: DQ, DM, DQS_t, DQS_c,

TDQS_t, TDQS_c

CDIO –0.1 0.1 –0.1 0.1 –0.1 0.1 –0.1 0.1 pF 1, 2, 3,

Input/output capacitance:

ALERT pin

CALERT 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 pF 2, 3

Input/output capacitance: ZQ

CZQ – 2.3 – 2.3 – 2.3 – 2.3 pF 2, 3, 12

Input/output capacitance:

TEN pin

CTEN 0.2 2.3 0.2 2.3 0.2 2.3 0.15 2.3 pF 2, 3, 13

Notes: 1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading

matches DQ and DQS.

2. This parameter is not subject to a production test; it is verified by design and characteri-

zation and are provided for reference; system signal simulations should not use these

values but use the Micron package model. The capacitance, if and when, is measured ac-

cording to the JEP147 specification, “Procedure for Measuring Input Capacitance Using

a Vector Network Analyzer (VNA),” with VDD, VDDQ, VSS, and VSSQ applied and all other

pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD =

VDDQ = 1.2V, VBIAS = VDD/2 and on-die termination off. Measured data is rounded using

industry standard half-rounded up methodology to the nearest hundredth of the MSB.

3. This parameter applies to monolithic die, obtained by de-embedding the package L and

C parasitics.

4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)).

5. Absolute value of CIO (DQS_t), CIO (DQS_c)

6. Absolute value of CCK_t, CCK_c

7. CI applies to ODT, CS_n, CKE, A[17:0], BA[1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and

WE_n.

8. CDI_CTRL applies to ODT, CS_n, and CKE.

8Gb: x4, x8, x16 DDR4 SDRAM

DRAM Package Electrical Specifications

CCMTD-1725822587-9875

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9. CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)).

10. CDI_ADD_CMD applies to A[17:0], BA1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n.

11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)).

12. Maximum external load capacitance on ZQ pin: 5pF.

13. Only applicable if TEN pin does not have an internal pull-up.

Thermal Characteristics

Table 136: Thermal Characteristics

Parameter/Condition Value Units Symbol Notes

Operating case temperature:

Commercial

0 to +85 °C TC1, 2, 3

0 to +95 °C TC1, 2, 3, 4

Operating case temperature:

Industrial

–40 to +85 °C TC1, 2, 3

–40 to +95 °C TC1, 2, 3, 4

Operating case temperature:

Automotive

–40 to +85 °C TC1, 2, 3

–40 to +105 °C TC1, 2, 3, 4

REV A

78-ball

“PM”

Junction-to-case (TOP) 3.1 °C/W ˆJC 5

Junction-to-board 10.6 °C/W ˆJB

96-ball

“HA”

Junction-to-case (TOP) 3.0 °C/W ˆJC 5

Junction-to-board 9.9 °C/W ˆJB

REV B

78-ball

“WE”

Junction-to-case (TOP) 3.5 °C/W ˆJC 5

Junction-to-board 21 °C/W ˆJB

96-ball “JY” Junction-to-case (TOP) 4.1 °C/W ˆJC 5

Junction-to-board 16.2 °C/W ˆJB

REV D

78-ball

“WE”

Junction-to-case (TOP) 3.2 °C/W ˆJC 5

Junction-to-board 20.2 °C/W ˆJB

96-ball “LY” Junction-to-case (TOP) TBD °C/W ˆJC 5

Junction-to-board TBD °C/W ˆJB

REV E

78-ball “SA” Junction-to-case (TOP) 4.9 °C/W ˆJC 5

Junction-to-board 14.2 °C/W ˆJB

96-ball “LY” Junction-to-case (TOP) 4.8 °C/W ˆJC 5

Junction-to-board 15.2 °C/W ˆJB

REV G

78-ball

“WE”

Junction-to-case (TOP) 2.8 °C/W ˆJC 5

Junction-to-board 13.1 °C/W ˆJB

N/A Junction-to-case (TOP) N/A °C/W ˆJC 5

Junction-to-board N/A °C/W ˆJB

REV H

78-ball “SA” Junction-to-case (TOP) 4.4 °C/W ˆJC 5

Junction-to-board 13.2 °C/W ˆJB

96-ball “LY” Junction-to-case (TOP) 3.4 °C/W ˆJC 5

Junction-to-board 14.7 °C/W ˆJB

8Gb: x4, x8, x16 DDR4 SDRAM

Thermal Characteristics

CCMTD-1725822587-9875

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Table 136: Thermal Characteristics (Continued)

Parameter/Condition Value Units Symbol Notes

REV J

78-ball “SA” Junction-to-case (TOP) 6.0 °C/W ˆJC 5

Junction-to-board 17.9 °C/W ˆJB

96-ball “TB” Junction-to-case (TOP) 5.9 °C/W ˆJC 5

Junction-to-board 17.4 °C/W ˆJB

REV R 78-ball "SA" Junction-to-case (TOP) TBD °C/W ˆJC 5

96-ball "TB" Junction-to-board TBD °C/W ˆJB

Notes: 1. MAX operating case temperature. TC is measured in the center of the package.

2. A thermal solution must be designed to ensure the DRAM device does not exceed the

maximum TC during operation.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-

ing operation.

4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs

interval refresh rate.

5. The thermal resistance data is based off of a typical number.

Figure 245: Thermal Measurement Point

(L/2)

(W/2)

TC test point

Current Specifications – Measurement Conditions

IDD, IPP, and IDDQ Measurement Conditions

IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined

in this section.

•I

DD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R,

IDD6N, IDD6E, IDD6R, IDD6A, IDD7, DD8 and IDD9) are measured as time-averaged currents

with all VDD balls of the device under test grouped together.

•I

PP currents are IPP3N for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8),

IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W), IPP5R for the distributed refresh case

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

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(IDD5R), IPP6x for self refresh cases (IDD6N, IDD6E, IDD6R, IDD6A), IPP7 for the operating

bank interleave read case (IDD7) and IPP9 for the MBIST-PPR operation case. These

have the same definitions as the IDD currents referenced but are measured on the VPP

supply.

•I

DDQ currents are measured as time-averaged currents with VDDQ balls of the device

under test grouped together. Micron does not specify IDDQ currents.

•I

PP and IDDQ currents are not included in IDD currents, IDD and IDDQ currents are not

included in IPP currents, and IDD and IPP currents are not included in IDDQ currents.

Note: IDDQ values cannot be directly used to calculate the I/O power of the device. They

can be used to support correlation of simulated I/O power to actual I/O power. In

DRAM module application, IDDQ cannot be measured separately because VDD and VDDQ

are using a merged-power layer in the module PCB.

The following definitions apply for IDD, IPP and IDDQ measurements.

• “0” and “LOW” are defined as VIN ืVIL(AC)max

• “1” and “HIGH” are defined as VIN ุVIH(AC)min

• “Midlevel” is defined as inputs VREF = VDD/2

• Timings used for IDD, IPP and IDDQ measurement-loop patterns are provided in the

Current Test Definition and Patterns section.

• Basic IDD, IPP, and IDDQ measurement conditions are described in the Current Test

Definition and Patterns section.

• Detailed IDD, IPP, and IDDQ measurement-loop patterns are described in the Current

Test Definition and Patterns section.

• Current measurements are done after properly initializing the device. This includes,

but is not limited to, setting:

RON = RZQ/7 (34 ohm in MR1);

Qoff = 0B (output buffer enabled in MR1);

RTT(NOM) = RZQ/6 (40 ohm in MR1);

RTT(WR) = RZQ/2 (120 ohm in MR2);

RTT(Park) = disabled;

TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in

MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disa-

bled in MR5

• Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA

changes when directed.

• Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply in-

vert of BG/BA changes when directed above.

Note: The measurement-loop patterns must be executed at least once before actual cur-

rent measurements can be taken, with the exception of IDD9 which may be measured

any time after MBIST-PPR entry.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

CCMTD-1725822587-9875

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Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx

IDD

CK_t/CK_c

CS_n

CKE

ODT

VDD VDDQ

VSS VSSQ

RESET_n

ACT_n, RAS_n, CAS_n, WE_n

DQS_t, DQS_c

DM_n

A, BG, BA

IDDQ

IPP

VPP

DDR4

SDRAM

Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power

Application-specific

memory cha nnel

environmen t

Channe l I/O

power simulation

IDD Q

test load

IDD Q

simulation

IDD Q

measurement

Correlation

Correction

Channe l I/O

power number

Note: 1. Supported by IDDQ measurement.

IDD Definitions

Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions

Symbol Description

IDD0 Operating One Bank Active-Precharge Current (AL = 0)

CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between

ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the

next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2,

2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT

signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

CCMTD-1725822587-9875

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Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol Description

IPP0 Operating One Bank Active-Precharge IPP Current (AL = 0)

Same conditions as IDD0 above

IDD1 Operating One Bank Active-Read-Precharge Current (AL = 0)

CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH

between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially

toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with

one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode

registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table

IDD2N Precharge Standby Current (AL = 0)

CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measure-

ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and

RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-

Loop Pattern table

IDD2NT Precharge Standby ODT Current

CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop

Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled

in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern de-

tails: see the IDD2NT Measurement-Loop Pattern table

IDD2P Precharge Power-Down Current

CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all

banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0

IDD2Q Precharge Quiet Standby Current

CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all

banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0

IDD3N Active Standby Current (AL = 0)

CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measure-

ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and

RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-

Loop Pattern table

IPP3N Active Standby IPP3N Current (AL = 0)

Same conditions as IDD3N above

IDD3P Active Power-Down Current (AL = 0)

CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-

dress, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all

banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

CCMTD-1725822587-9875

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Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol Description

IDD4R Operating Burst Read Current (AL = 0)

CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;15 AL: 0; CS_n: HIGH between RD; Com-

mand, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measure-

ment-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the

next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks

open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table);

Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Meas-

urement-Loop Pattern table

IDD4W Operating Burst Write Current (AL = 0)

CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Com-

mand, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measure-

ment-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the

next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks

open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table);

Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see

the IDD4W Measurement-Loop Pattern table

IDD5R Distributed Refresh Current (1X REF)

CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF;

Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Meas-

urement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see

the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal:

stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table

IPP5R Distributed Refresh Current (1X REF)

Same conditions as IDD5R above

IDD6N Self Refresh Current: Normal Temperature Range

TC: 0–85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; Exter-

nal clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group

address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer

and RTT: enabled in mode registers;2 ODT signal: midlevel

IDD6E Self Refresh Current: Extended Temperature Range 4

TC: 0–95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; Ex-

ternal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group

bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF

REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel

IPP6x Self Refresh IPP Current

Same conditions as IDD6E above

IDD6R Self Refresh Current: Reduced Temperature Range

TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; Exter-

nal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank

group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF

REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 321 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol Description

IDD7 Operating Bank Interleave Read Current

CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL -

1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially

toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data

between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;

Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7

Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0;

Pattern details: see the IDD7 Measurement-Loop Pattern table

IPP7 Operating Bank Interleave Read IPP Current

Same conditions as IDD7 above

IDD8 Maximum Power Down Current

Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n:

stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n:

stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: sta-

ble at 0

IDD9 MBIST-PPR Current 7

Device in MBIST-PPR mode; External clock: on; CS_n: stable at 1 after MBIST-PPR entry; Command, address,

bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all

banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0

IPP9 MBIST-PPR IPP Current

Same condition with IDD9 above

Notes: 1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.

2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON =

RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001

(RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).

3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.

4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended

temperature range.

5. READ burst type: Nibble sequential, set MR0[3] 0.

6. In the dual-rank DDP case, note the following IDD measurement considerations:

• For all IDD measurements except IDD6, the unselected rank should be in an IDD2P condi-

tion.

• For all IPP measurements except IPP6, the unselected rank should be in an IDD3N condi-

tion.

• For all IDD6/IPP6 measurements, both ranks should be in the same IDD6 condition.

7. When measuring IDD9/IPP9 after entering MBIST-PPR mode and ALERT_N driving LOW,

there is a chance that the DRAM may perform an internal hPPR if fails are found after

internal self-test is completed and before ALERT_N fires HIGH.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Measurement Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 322 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Current Specifications – Patterns and Test Conditions

Current Test Definitions and Patterns

Table 138: IDD0 and IPP0 Measurement-Loop Pattern1

CK_t, CK_c

CKE

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,11]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 ACT00000000000000 –

1, 2 D, D10000000000000 –

3, 4 D_n,

D_n

111110330007F0 –

... Repeat pattern 1...4 until nRAS - 1; truncate if necessary

nRAS PRE01010000000000 –

... Repeat pattern 1...4 until nRC - 1; truncate if necessary

1 1 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead

2 2 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 3 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 4 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 5 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 6 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 7 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 8 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 9 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 10 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 11 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 12 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 13 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 14 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 15 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VDDQ.

2. BG1 is a "Don't Care" for x16 devices.

3. DQ signals are VDDQ.

4. For x4 and x8 only.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Patterns and Test Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 323 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 139: IDD1 Measurement – Loop Pattern1

CK_c, CK_t,

CKE

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,11]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 ACT 00000000000000 –

1, 2 D, D 10000000000000 –

3, 4 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 –

... Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary

nRCD - AL RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 =

FF,

D2 = FF, D3 =

00,

D4 = FF, D5 =

00,

D5 = 00, D7 = FF

... Repeat pattern 1...4 until nRAS - 1; truncate if necessary

nRAS PRE 01010000000000

... Repeat pattern 1...4 until nRC - 1; truncate if necessary

1 1 × nRC + 0 ACT 00011011000000 –

1 × nRC + 1,

D, D 10000000000000 –

1 × nRC + 3,

D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 –

... Repeat pattern nRC + 1...4 until 1 × nRC + nRAS - 1; truncate if necessary

1 × nRC

+nRCD - AL

RD 0 1 1 0 1 0 1 1 0 0 0 0 0 0 D0 = FF, D1 =

00,

D2 = 00, D3 =

FF,

D4 = 00, D5 =

FF,

D5 = FF, D7 = 00

... Repeat pattern 1...4 until nRAS - 1; truncate if necessary

1 × nRC +

nRAS

PRE 01010011000000

... Repeat pattern nRC + 1...4 until 2 × nRC - 1; truncate if necessary

2 2 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 3 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 4 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 5 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 6 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 7 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 9 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 10 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 11 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 12 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 13 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 14 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 15 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 16 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VDDQ when not toggling.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Patterns and Test Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 324 Micron Technology, Inc. reserves the right to change products or specifications without notice.

2. BG1 is a "Don't Care" for x16 devices.

3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ com-

mand.

4. For x4 and x8 only.

Table 140: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1

CK_c, CK_t,

CKE

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,11]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 D 10000000000000 –

1 D 10000000000000 –

2 D_n111110330007F0 –

3 D_n111110330007F0 –

1 4–7 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead

2 8–11 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 12–15 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 16–19 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 20–23 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 24–27 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 28–31 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 32–35 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 36–39 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 40–43 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 44–47 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 48–51 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 52–55 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 56–59 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 60–63 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VDDQ.

2. BG1 is a "Don't Care" for x16 devices.

3. DQ signals are VDDQ.

4. For x4 and x8 only.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Patterns and Test Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 325 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 141: IDD2NT Measurement – Loop Pattern1

CK_c, CK_t,

CKE

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,11]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 D 10000000000000 –

1 D 10000000000000 –

2 D_n111110330007F0 –

3 D_n111110330007F0 –

1 4–7 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead

2 8–11 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 12–15 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 16–19 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 20–23 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 24–27 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 28–31 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 32–35 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 36–39 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 40–43 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 44–47 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 48–51 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 52–55 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 56–59 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 60–63 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VSSQ.

2. BG1 is a "Don't Care" for x16 devices.

3. DQ signals are VSSQ.

4. For x4 and x8 only.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Patterns and Test Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 326 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 142: IDD4R Measurement – Loop Pattern1

CK_c, CK_t,

CKE

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,11]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 =

FF,

D2 = FF, D3 =

00,

D4 = FF, D5 =

00,

D5 = 00, D7 =

1 D 10000000000000

2, 3 D_n,

D_n

111110330007F0

1 4 RD 0 1 1 0 1 0 1 1 0 0 0 7 F 0 D0 = FF, D1 = 00

D2 = 00, D3 =

D4 = 00, D5 =

D5 = FF, D7 = 00

5 D 10000000000000

6, 7 D_n,

D_n

111110330007F0

2 8–11 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 12–15 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 16–19 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 20–23 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 24–27 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 28–31 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 32–35 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 36–39 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 40–43 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 44–47 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 48–51 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 52–55 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 56–59 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 60–63 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VDDQ when not toggling.

2. BG1 is a "Don't Care" for x16 devices.

3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation,

DQ signals are VDDQ.

4. For x4 and x8 only.

8Gb: x4, x8, x16 DDR4 SDRAM

Current Specifications – Patterns and Test Conditions

CCMTD-1725822587-9875

8gb_ddr4_dram.pdf - Rev. S 12/2020 EN 327 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 143: IDD4W Measurement – Loop Pattern1

CK_c,

CK_t,

CKE

Sub-Loop

Cycle

Number

Com-

mand

CS_n

ACT_n

RAS_n/A1

CAS_n/A1

WE_n/A14

ODT

BG[1:0]2

BA[1:0]

A12/BC_n

A[17,13,1

1]]

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data3

Toggling

Static High

0 0 WR01100100000000D0 = 00, D1 = FF,

D2 = FF, D3 = 00,

D4 = FF, D5 = 00,

D5 = 00, D7 = FF

1 D 10000100000000

2, 3 D_n,

D_n

111101330007F0

1 4 WR011001110007F0D0 = FF, D1 = 00

D2 = 00, D3 = FF

D4 = 00, D5 = FF

D5 = FF, D7 = 00

5 D 10000100000000