SC16IS750IPW-T - NXP Semiconductors

1. General description

The SC16IS740/750/760 is a slave I2C-bus/SPI interface to a single-channel high

performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and

sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8

additional programmable I/O pins. The device comes in very small HVQFN24, TSSOP24

(SC16IS750/760) and TSSOP16 (SC16IS740) packages, which makes it ideally suitable

for handheld, battery operated applications. This family of products enables seamless

protocol conversion from I2C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.

The SC16IS760 differs from the SC16IS750 in that it supports SPI clock speeds up to

15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS750, and in that it supports

IrDA SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS760 is functionally and

electrically the same as the SC16IS750. The SC16IS740 is functionally and electrically

identical to the SC16IS750, with the exception of the programmable I/O pins which are

only present on the SC16IS7 50 .

The SC16IS740/750/760’s internal register set is backward-compatible with the widely

used and widely popular 16C450. This allows the software to be easily written or ported

from another platform.

The SC16IS740/750/760 also provides additional advanced features such as auto

hardware and software flow control, automatic RS-485 support, and software reset. This

allows the softwar e to rese t the UAR T at any momen t, independe nt of the hardware r eset

signal.

2. Features and benefits

2.1 General features

Single full-duplex UART

Selectable I2C-bus or SPI interface

3.3 V or 2.5 V operation

Industrial temperature range: 40 C to +95 C

64 bytes FIFO (transmitter and receiver)

Fully compatible with industrial standard 16 C4 50 an d eq uiv ale nt

Baud rates up to 5 Mbit/s in 16 clock mode

Auto hardware flow control using RTS/CTS

Auto software flow control with programmable Xon/Xoff characters

Single or double Xon/Xoff characters

Automatic RS-485 support (automatic slave address detection)

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support

Rev. 7 — 9 June 2011 Product data sheet

Product data sheet Rev. 7 — 9 June 2011 2 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Up to eight programmable I/O pins (SC16IS750 and SC16IS760 only)

RS-485 driver direction control via RTS signal

RS-485 driver direction control inversion

Built-in IrDA encoder and decoder interface

SC16IS750 supports IrDA SIR with speeds up to 115.2 kbit/s

SC16IS760 supports IrDA SIR with speeds up to 1.152 Mbit/s1

Software reset

Transmitter and receiver can be enabled/disabled independent of each other

Receive and Transmit FIFO levels

Programmable special character detection

Fully programmable character formatting

5-bit, 6-bit, 7-bit or 8-bit character

Even, odd, or no parity

1, 112, or 2 stop bits

Line break generation and detection

Internal Loopback mode

Sleep current less than 30 A at 3.3 V

Industrial and commercial temperature ranges

Available in HVQFN24, TSSOP24 (SC16IS750/760) and TSSOP16 (SC16IS740)

packages

2.2 I2C-bus features

Noise filter on SCL/SDA inputs

400 kbit/s maximum speed

Compliant with I2C-bus fast speed

Slave mode only

2.3 SPI features

SC16IS750 supports 4 Mbit/s maximum SPI clock speed

SC16IS760 supports 15 Mbit/s maximum SPI clock speed

Slave mode only

SPI Mode 0

3. Applications

Factory automation and process control

Portable and battery operated devices

Cellular data devices

1. Please note that IrDA SIR at 1.152 Mbit/s is not compatible with IrDA MIR at that speed. Please refer to application notes for usage

of IrDA SIR at 1.152 Mbit/s.

Product data sheet Rev. 7 — 9 June 2011 3 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

4. Ordering information

[1] SC16IS740IPW/Q900 is AEC-Q100 compliant. Contact interface.support@nxp.com for PPAP.

Ta ble 1. Ordering information

Type number Package

Name Description Version

SC16IS740IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

SC16IS740IPW/Q900[1] TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

SC16IS750IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 40.85 mm SOT616-3

SC16IS750IPW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

SC16IS760IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 40.85 mm SOT616-3

SC16IS760IPW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

Product data sheet Rev. 7 — 9 June 2011 4 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

5. Block diagram

Fig 1. Block diagram of SC16IS750/760 I2C-bus interface

Fig 2. Block diagram of SC16IS740 I2C-bus interface

SC16IS750/760

16C450

COMPATIBLE

SETS

002aab014

VDD

I2C-BUS

RTS

GPIO

CTS

GPIO[3:0]

XTAL1 XTAL2

SCL

SDA

IRQ

I2C/SPI

RESET

GPIO4/DSR

GPIO5/DTR

GPIO6/CD

GPIO7/RI

VDD

VSS

VDD

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

SC16IS740

16C450

COMPATIBLE

SETS

002aab971

VDD

I2C-BUS

RTS

CTS

XTAL1 XTAL2

SCL

SDA

IRQ

I2C/SPI

RESET

VDD

VSS

VDD

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

Product data sheet Rev. 7 — 9 June 2011 5 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 3. Block diagram of SC16IS750/760 SPI interface

Fig 4. Block diagram of SC16IS740 SPI interface

SC16IS750/760

16C450

COMPATIBLE

SETS

002aab396

SPI

RTS

GPIO

CTS

GPIO[3:0]

XTAL1 XTAL2

SCLK

IRQ

I2C/SPI

RESET

GPIO4/DSR

GPIO5/DTR

GPIO6/CD

GPIO7/RI

VDD

VSS

VDD

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

SC16IS740

16C450

COMPATIBLE

SETS

002aab972

SPI

RTS

CTS

XTAL1 XTAL2

SCLK

IRQ

I2C/SPI

RESET

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

Product data sheet Rev. 7 — 9 June 2011 6 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

6. Pinning information

6.1 Pinning

a. I2C-bus interface b. SPI interface

Fig 5. Pin configuration for TSSOP16

SC16IS740IPW

SC16IS740IPW/Q900

XTAL2

A0 XTAL1

A1 RESET

n.c. RX

SCL TX

SDA CTS

IRQ RTS

I2C V

002aab973

SC16IS740IPW

SC16IS740IPW/Q900

XTAL2

CS XTAL1

SI RESET

SO RX

SCLK TX

CTS

IRQ RTS

SPI V

002aab974

a. I2C-bus interface b. SPI interface

Fig 6. Pin configuration for TSSOP24

XTAL2

XTAL1

RESET

CTS RTS

GPIO7/RI

GPIO6/CD

GPIO5/DTR

GPIO4/DSR

VSS

VDD

n.c.

SDA

IRQ

GPIO0

GPIO1

GPIO2

SCL

I2C

SC16IS750IPW

SC16IS760IPW GPIO3

002aab016

XTAL2

XTAL1

RESET

CTS RTS

GPIO7/RI

GPIO6/CD

GPIO5/DTR

GPIO4/DSR

VSS

VDD

VSS

IRQ

GPIO0

GPIO1

GPIO2

GPIO3

SCLK

SPI

SC16IS750IPW

SC16IS760IPW

002aab399

Product data sheet Rev. 7 — 9 June 2011 7 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

6.2 Pin description

a. I2C-bus interface b. SPI interface

Fig 7. Pin configuration for HVQFN24

RTS

GPIO7/RI

GPIO6/CD

CTS

I2C

XTAL1

RESET

XTAL2

n.c.

IRQ

SDA

SCL

GPIO0

002aab015

GPIO5/DTR

GPIO4/DSR

GPIO3

GPIO2

GPIO1

SC16IS750IBS

SC16IS760IBS

Transparent top view

terminal 1

index area

613

514

4 15

3 16

2 17

118

RTS

GPIO7/RI

GPIO6/CD

CTS

SPI

XTAL1

RESET

XTAL2

IRQ

SCLK

GPIO0

002aab401

GPIO5/DTR

GPIO4/DSR

GPIO3

GPIO2

GPIO1

SC16IS750IBS

SC16IS760IBS

Transparent top view

terminal 1

index area

613

514

4 15

3 16

2 17

118

Table 2. Pin de scription

Symbol Pin Type Description

TSSOP16 TSSOP24 HVQFN24

CTS 11 1 22 I UART clear to send (active LOW). A logic 0 (LOW) on the CTS pin

indicates the modem or data set is ready to accept transmit data

from the SC16IS740/750/760. Status can be tested by reading

MSR[4]. This pin only affects the transmit and receive operations

when auto CTS function is enabled via the Enhanced Feature

TX 12 2 23 O UART transmitter output. During the local Loopback mode, the TX

output pin is disabled and TX data is internally connected to the

UART RX input.

RX 13 3 24 I UART receiver input. During the local Loopback mode, the RX

input pin is disabled and TX data is connected to the UART RX

input internally.

RESET 14 4 1 I dev ice hardware reset (active LOW)[1]

XTAL1 15 5 2 I Crystal input or external clock input. Functions as a crystal input or

as an external clock input. A crystal can be connected between

XTAL1 and XTAL2 to form an internal oscillator circuit (see

Figure 16). Alternatively , an external clock can be connected to this

pin.

XTAL2 16 6 3 O Cryst al output or clock output. (See also XT AL1.) XTAL2 is used as

a crystal oscillator output.

VDD 1 7 4 - power supply

I2C/SPI 885II

2C-bus or SPI interface select. I2C-bus interface is selected if this

pin is at logic HI GH . SPI in terface is selected if this pin is at logic

LOW.

Product data sheet Rev. 7 — 9 June 2011 8 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] See Section 7.4.1 “Hardware reset, Power-On Reset (POR) and software reset”

[2] These pins have an active pull-up resistor at their inputs. See Table 36.

[3] Selectable with IOControl register bit 1.

CS/A0 2 9 6 I SPI chip select or I2C-bus device address select A0. If SPI

configuration is selected by I2C/SPI pin, this pin is the SPI chip

select pin (Schmitt-trigger, active LOW). If I2C-bus configuration is

selected by I2C/SPI pin, this pin along with A1 pin allows user to

change the device’s base address.

SI/A1 3 10 7 I SPI data input pin or I2C-bus device address select A1. If SPI

configuration is selected by I2C/SPI pin, this is the SPI data input

pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin

along with A0 pin allows user to change the device’s base address.

To select th e device address, please refer to Table 32.

SO 4 1 1 8 O SPI data output pin. If SPI configuration is selected by I2C/SPI pin,

this is a 3-stateable output pin. If I2C-bus configuration is selected

by I2C/SPI pin, this pin function is undefined and must be left as

n.c. (not connected).

SCL/SCLK 5 12 9 I I2C-bus or SPI input clock.

SDA 6 13 10 I/O I2C-bus data input/output, open-drain if I2C-bus configuration is

selected by I2C/SPI pin. If SPI configuration is selected then this

pin is an undefined pin and must be connected to VSS.

IRQ 7 14 11 O Interrupt (open-drain, active LOW). Interrupt is enabled when

interrupt sources are enabled in the Interrupt Enable Register

(IER). Interrupt conditions include: change of state of the input

pins, receiver errors, available receiver buffer data, available

transmit buffer space, or when a modem status flag is detected. An

external resistor (1 k for 3.3 V, 1.5 kfor 2.5 V) must be

connected between this pin and VDD.

GPIO0 - 15 12 I/O programmable I/O pin[2]

GPIO1 - 16 13 I/O programmable I/O pin[2]

GPIO2 - 17 14 I/O programmable I/O pin[2]

GPIO3 - 18 15 I/O programmable I/O pin[2]

GPIO4/DSR - 20 17 I/O programmable I/O pin or modem’s DSR pin[2][3]

GPIO5/DTR - 21 18 I/O programmable I/O pin or modem’s DTR pin[2][3]

GPIO6/CD - 22 19 I/O programmable I/O pin or modem’s CD pin[2][3]

GPIO7/RI - 23 20 I/O programmable I/O pin or modem’s RI pin[2][3]

RTS 10 24 21 O UART request to send (active LOW). A logic 0 on the RTS pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register MCR[1] will set this

pin to a logic 0, in dicating data is available. After a reset this pin is

set to a logic 1. This pin only affects the transmit and receive

operations when auto RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware flow con trol operatio n.

VSS 91916

[4] -ground

VSS - - center

pad[4] - The center pad on the back side of the HVQFN24 package is

metallic and should be connected to ground on the printed-circuit

board.

Table 2. Pin de scription …continued

Symbol Pin Type Description

TSSOP16 TSSOP24 HVQFN24

Product data sheet Rev. 7 — 9 June 2011 9 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[4] HVQFN24 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

7. Functional description

The UART will perform serial-to-I2C conversion on data characters received from

peripheral de vices or modems , an d I 2C-to-serial conversion on data characters

transmitted by the host. The complete status the SC16IS740/750/760 UART can be read

at any time during functional operation by the host.

The SC16IS740/750/760 can be placed in an alternate mode (FIFO mode) relieving the

host of excessive software overhead by buffering received/transmitted characters. Both

the receiver and transmitter FIFOs can store up to 64 characters (including three

additional bits of error status per character for the receiver FIFO) and have selectable or

programmable trigger levels.

The SC16IS740/750/760 has selectable hardware flow control and software flow control.

Hardware flow control significantly reduces software overhead and increases system

efficiency by automatically controlling serial data flow using the R TS output and CTS input

signals. Software flow control automatically controls data flow by using programmable

Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216 –1).

7.1 Trigger levels

The SC16IS740/750/760 provides independently selectable and programmable trigger

levels for both receiver and transmitter interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default valu e of

one character. The selectable trigger levels are availab le via the FCR. The programm able

trigger levels are available via the TLR. If TLR bits are cleared the n selectable trigg er level

in FCR is used. If TLR bit s are not cleared then prog rammable trigger level in TL R is used.

7.2 Hardware flow control

Hardware flow control is comprised of auto CTS and auto RTS (see Figure 8). Auto CTS

and auto RTS can be enabled/disabled independently by programming EFR[7:6].

With auto CTS, CTS must be active before the UART can tr ansmit data.

Auto RTS only activates the R TS output when there is enough ro om in the FIFO to receive

data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and

resume trigger levels in the TCR determine the levels at which RTS is

activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are

used in place of TCR.

If both auto CTS and auto RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware flow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

Product data sheet Rev. 7 — 9 June 2011 10 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.1 Auto RTS

Figure 9 shows RTS functional timi ng. The receiver FIFO trigger levels used in auto RTS

are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger

level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.

The sending device (for example, another UART) may send an additional character after

the trigger level is reached (assuming the sending UART has another character to send)

because it may not recognize the deassertion of RTS until it has begun sending the

additional character. RTS is automatically reasserted on ce th e re ce iver F IFO re ache s the

resume trigger level programmed via TCR[7:4]. This reassertion allows the sending

device to resume transmission.

Fig 8. Autoflow c ontrol (auto RTS and auto CTS) example

FIFO

FLOW

CONTROL

FIFO

PARALLEL

TO SERIAL

FIFO

UART 1 UART 2

RX TX

RTS CTS

TX RX

CTS RTS

002aab656

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1

Fig 9. RTS funct ional timing

start character

Nstart character

N + 1 startstop stopRX

RTS

receive

FIFO

read

N N + 112

002aab040

Product data sheet Rev. 7 — 9 June 2011 11 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.2 Auto CTS

Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before

sending the next data byte. When CTS is active, the transmitter sends the next byte. To

stop the transmitter from sending the following byte, CTS must be deasserted before the

middle of the last stop bit that is currently being sent. The auto CTS function reduces

interrupts to the host system. When flow control is enabled, CTS level changes do not

trigger host interr up ts becaus e th e de vice au tom a tica lly contr o ls its own transm itte r.

Without auto CTS, the transmitter send s any data present in the tr ansmit FIFO and a

receiver overru n er ro r ma y re sult .

7.3 Software flow control

Software flow control is enabled through the enhanced feature register and the Modem

Control Register . Different combinations of software flow control can be enabled by setting

different combinations of EFR[3:0]. Table 3 shows software flow control options.

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS goes HIGH before the middle of the last stop bit of the current character , the transmitter finishes sending the current

character, but it does not send the next character.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 10. CTS functional timing

start bit 0 to bit 7 stopTX

CTS

002aab041

start stop

bit 0 to bit 7

Table 3. Software flow control options (EFR[3:0])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow control

0 0 X X no transmit flow control

1 0 X X transmit Xon1, Xoff1

0 1 X X transmit Xon2, Xoff2

1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 no receive flow control

X X 1 0 receiver compares Xon1, Xoff1

X X 0 1 receiver compares Xon2, Xoff2

1011transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1111transmit Xon1 and Xon2, Xoff1 and Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0011no transmit flow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 7 — 9 June 2011 12 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software flow control:

•Xon Any function (MCR[5]): Receiving any character will resume operation after

recognizing the Xoff character. It is possible that an Xon1 character is recognized as

an Xon Any character, which could cause an Xon2 character to be written to the RX

FIFO.

•Special character (E FR [5 ]) : Incoming data is compared to Xoff2. Detection of the

special charact er sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the IIR. The special ch aracter is transferred to the

RX FIFO.

7.3.1 RX

When software flow control operation is enabled, the SC16IS740/750/760 will compare

incoming dat a with Xoff1/Xoff2 programm ed character s (i n certain cases, Xoff1 and Xoff2

must be received sequentially). When the correct Xoff characters are received,

transmission is halted after completing transmission of the current charac te r. Xoff

detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 TX

Xoff 1/Xof f 2 character is tran smitted when the RX FIFO has p assed the HALT trigger level

programmed in TCR[3:0] or the selectable trigger level in FCR[7:6]

Xon1/Xof f2 character is transmitted when the RX FIFO rea ches the RESUME trigger level

programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in

FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the F IFO. This means that even if the word length is set to be 5, 6,

or 7 bits, then the 5, 6, or 7 least significant bits of XOFF1/XOFF2 or XON1/XON2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but

this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled

simultaneously. Figure 11 shows an example of software flow control.

Product data sheet Rev. 7 — 9 June 2011 13 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Reset and power-on sequence

7.4.1 Hardware reset, Power-On Reset (POR) and software reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 4.

Table 4 summarizes the state of register.

Fig 11. Example of software flow control

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

RECEIVE FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

UART2UART1

002aaa229

data

Xoff–Xon–Xoff

compare

programmed

Xon-Xoff

characters

Table 4. Regis t er reset[1]

Interrupt Enable Register all bits cleared

Interrupt Identification Register bit 0 is set; all other bits cleared

FIFO Control Register all bits cleared

Line Control Register reset to 0001 1101 (0x1D)

Modem Control Register all bits cleared

Line Status Register bit 5 and bit 6 set; all other bits cleared

Modem Status Register bits 0:3 cleared; bits 4:7 input signals

Enhanced Feature Register all bits cleared

Receiver Holding Register pointer logic cleared

Transmitter Holding Register pointer logic cleared

Transmission Control Register all bits cleared.

Trigger Level Register all bits cleared.

Product data sheet Rev. 7 — 9 June 2011 14 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal

RESET, POR or Software Reset, that is, they hold their initialization values during reset.

[2] This register is not supported in SC16IS740.

[3] Only UART Software Reset bit is supported in this register.

Table 5 summarizes the state of registers after reset.

7.4.2 Power-on sequence

After power is applied , the device is reset by th e internal POR. The host must wait at least

3s before initializing a communication with the device.

An external reset pulse (see Figure 26) ca n also be used to reset the device after power is

applied.

Once the device is reset properly, the host processor can start to communicate with the

device. Internal registers can be accessed (read and write), however, at this time the

UART transmitter and receiver cannot be used until there is a stable clock at XTAL1 pin.

Normally, if an external clock such as a system clock or an external oscillator is used to

supply a clock to XT AL1 pin, the clock should be stable at this time. But if a crystal is used,

the host processor must wait until the cryst al is generating a st able clock before accessing

the UART transmitter or receiver.

The crystal’s start-up time depends on the crystal being used, VCC ramp-up time and the

loading capacitor values. The start-up time can be as long as a few milliseconds.

Transmit FIFO level reset to 0100 0000 (0x40)

Receive FIFO level all bits cleared

I/O direction[2] all bits cleared

I/O interrupt enable[2] all bits cleared

I/O control[3] all bits cleared

Extra Feature Register all bits cleared

Table 5. Output signals after reset

Signal Reset state

TX HIGH

RTS HIGH

I/Os inputs

IRQ HIGH by external pull-up

Table 4. Regis t er reset[1]

Product data sheet Rev. 7 — 9 June 2011 15 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.5 Interrupts

The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized

levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable

each of the seven types of interrupts and the IRQ signal in response to an interrupt

generation. When an interrupt is generated, the IIR indicates that an interrupt is pending

and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt

control functions.

[1] Available only on SC16IS750/SC16IS760.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]

generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,

and is cleared only when the re are no more errors r emaining in the FIFO. LSR[4:2] always

represent the error status for the received character at the top of the RX FIFO. Reading

the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of

the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xof f flo w character dete ctio n cause d th e interr upt, the inte rrup t

is cleared by an Xon flow character detection. If a special character detection caused the

interrupt, the interrupt is cleared by a read of the IIR.

Fig 12. St a rt-up time

oscillator starts stable clocks

002aaf521

startup

voltage

(V)

time (ms)

XTAL1 V

0 V

Table 6. Summ ary of interrupt control functions

IIR[5:0] Priority

level Interrupt type Interrupt source

00 0001 none none none

00 0110 1 receiver line status OE, FE, PE, or BI errors occur in characters in the

RX FIFO

00 1100 2 RX time-out Stale data in RX FIFO

00 0100 2 RHR interrupt Receive data ready (FIFO disable) or

RX FIF O above trigger level (FIFO enabl e)

00 0010 3 THR interrupt Transmit FIFO empty (FIFO disable) or

TX FI FO passes above trigger level (FIFO enable)

00 0000 4 modem status[1] Change of state of modem input pins

11 0000 5 I/O pins[1] Input pins change of state

01 0000 6 Xoff interrupt Receive Xoff character(s)/ special c haracter

10 0000 7 CTS, RTS RTS pin or CTS pin change state from active (LOW)

to inactive (HIGH)

Product data sheet Rev. 7 — 9 June 2011 16 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.5.1 Interrupt mode operation

In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the

receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to

continuously poll the Line Status Register (LSR) to see if any interrupt nee ds to be

serviced. Figure 13 shows Interrupt mod e op er a tion .

7.5.2 Polled mode operation

In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be

checked by polling the Line Status Register (LSR). This mode is an alte rnative to the FIFO

Interrupt mode of operation where the status of the receiver and transmitter is

automatically known by means of interrupts sent to the CPU. Figure 14 shows FIFO

Polled mode operation.

Fig 13. Interrupt mode ope ra tion

1111

IIR

IER

THR RHR

HOST IRQ

002aab042

read IIR

Fig 14. FIFO Polled mode operation

0000

LSR

IER

THR RHR

HOST

read LSR

002aab043

Product data sheet Rev. 7 — 9 June 2011 17 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.6 Sleep mode

Sleep mode is an enhanced fe atur e of th e SC 16IS74 0/750/760 UART. It is enabled when

EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered

when:

•The serial data input line, RX, is idle (see Section 7.7 “Break and time-out

conditions”).

•The TX FIFO and TX shift register are empty.

•There are no interrupts pending except THR.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using

these clocks, the power consumption is greatly reduced. The UART will wake up when

any change is detected on the RX line, when there is any change in the state of the

modem input pins, or if data is written to the TX FIFO.

Wake-up by serial data on RX input pin is supported in UART mode but not in IrDA mode

in Rev. C and Rev. D of the device. Refer to application note AN10964, “How to wake up

SC16IS/740/750/760 in IrDA mode” for a software procedure to wake up the device by

receiving data in the IrDA mode.

Wake-up by serial data on RX input pin is supported in both UART mode and IrDA mode

in Rev. E of the device.

The device will not wake up by GPIO pin transition, but GPIO pin input state can be read,

and GPIO interrupt is working normally during Sleep mode.

Remark: Writin g to the divisor latches, DLL and DLH, to set the baud clock, must not be

done during Sleep mode. Therefore, it is advisable to disable Slee p mode using IER[4]

before writing to DLL or DLH.

7.7 Break and time-out conditions

When the UAR T receive s a number of character s and these dat a are not en ough to set of f

the receive interrupt (because they do not reach the receive trigger level), the UART will

generate a time-out interrupt instead, 4 character times after the last character is

received. The time-out counter will be reset at the center of each stop bit received or each

time the receive FIFO is read.

A break condition is detected when the RX pin is pulled LOW for a duration longer than

the time it takes to send a complete character plus Start, Stop and Parity bits. A break

condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW

until LSR[6] is cleared by the software.

Product data sheet Rev. 7 — 9 June 2011 18 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.8 Programmable baud rate generator

The SC16IS740/750/760 UART contains a programmable baud rate generator that takes

any clock input and divides it by a divisor in the range between 1 and (216 –1). An

additional divide-by-4 prescaler is also available and can be selected by MCR[7], as

shown in Figure 15. The output frequency of the baud rate generator is 16  the ba ud

rate. The formula for the divisor is given in Equation 1:

(1)

where:

prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)

prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

Figure 15 shows the internal prescaler and baud rate generator circuitry.

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the

least significant and most significant byte of the baud rate divisor . If DLL and DLH are both

zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit

and receive clock rates.

Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively. The crystal’s frequency tolerance should be

selected as such to keep the baud rate error to be below 1 % for reliable operation with

other UARTs. Crystals with 100 ppm is generally recommended.

Figure 16 shows the crystal clock circuit reference.

Fig 15. Prescaler and baud rate generator block di agram

divisor

XTAL1 crystal input frequency

prescaler

-----------------------------------------------------------------------------------





desired baud rate 16

-----------------------------------------------------------------------------------------

BAUD RATE

GENERATOR

LOGIC

MCR[7] = 1

MCR[7] = 0

PRESCALER

LOGIC

(DIVIDE-BY-1)

INTERNAL

OSCILLATOR

LOGIC

002aaa233

XTAL1

XTAL2 input clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

reference

clock

internal

baud rate

clock for

transmitter

and receiver

Product data sheet Rev. 7 — 9 June 2011 19 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 7. Baud rates using a 1.8432 MHz crystal

Desired baud rate Divisor used to generate

16clock Percent error difference

between desired and actual

50 2304 0

75 1536 0

110 1047 0.026

134.5 857 0.058

150 768 0

300 384 0

600 192 0

1200 96 0

1800 64 0

2000 58 0.69

2400 48 0

3600 32 0

4800 24 0

7200 16 0

9600 12 0

19200 6 0

38400 3 0

56000 2 2.86

Table 8. Baud rates using a 3.072 MHz crystal

Desired baud rate Divisor used to generate

16clock Percent error difference

between desired and actual

50 2304 0

75 2560 0

110 1745 0.026

134.5 1428 0.034

150 1280 0

300 640 0

600 320 0

1200 160 0

1800 107 0.312

2000 96 0

2400 80 0

3600 53 0.628

4800 40 0

7200 27 1.23

9600 20 0

19200 10 0

38400 5 0

Product data sheet Rev. 7 — 9 June 2011 20 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8. Register descriptions

The programming combinations for register selection are shown in Table 9.

[1] MCR[7] can only be modified when EFR[4] is set.

[2] Accessible only when ERF[4] = 1 and MCR[2] = 1, t hat is, EFR[4] and MCR[2] are read/write enables.

[3] Available only on SC16IS750/SC16IS760.

[4] Accessible only when LCR[7] is logic 1.

[5] Accessible only when LCR is set to 1011 1111b (0xBF).

Fig 16. Crystal oscillator circuit reference

002aab402

1.8432 MHz

22 pF C2

33 pF

XTAL1 XTAL2

Table 9. Regis t er map - read/write properties

RHR/THR Receive Holding Register (RHR) Transmit Holding Register (THR)

IER Interrupt Enable Register (IER) Interrupt Enable Register

IIR/FCR Interrupt Identification Register (IIR) FIFO Control Register (FCR)

LCR Line Control Register (LCR) Li ne Control Register

MCR Modem Control Register (MCR)[1] Modem Control Register[1]

LSR Line Status Register (LSR) n/a

MSR Modem Status Register (MSR) n/a

SPR Scratchpad Register (SPR) Scratchpad Register

TCR Transmission Control Register (TCR)[2] Tr ansmission Control Register[2]

TLR Trig ger Level Register (TLR)[2] Trigger Level Register[2]

TXLV L Transmit FIFO Level Register n/a

RXLVL Receive FIFO Level Register n/a

IODir[3] I/O pin Direction Register I/O pin Direction Register

IOState[3] I/O pin States Register n/a

IOIntEna[3] I/O Interrupt Enable Register I/O Interrupt Enable Register

IOControl[3] I/O pins Control Register I/O pins Control Register

EFCR Extra Features Register Extra Features Register

DLL divisor latch LSB (DLL)[4] divisor latch LSB[4]

DLH divisor latch MSB (DLH)[4] divisor latch MSB[4]

EFR Enhanced Feature Register (EFR)[5] Enhanced Feature Register[5]

XON1 Xon1 word[5] Xon1 word[5]

XON2 Xon2 word[5] Xon2 word[5]

XOFF1 Xoff1 word[5] Xoff 1 word[5]

XOFF2 Xoff2 word[5] Xoff 2 word[5]

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Product data sheet Rev. 7 — 9 June 2011 21 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 10 . SC16IS740/750/760 internal registers

address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

General register set[1]

0x00 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

0x00 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W

0x01 IER CTS

interrupt

enable[2]

RTS interrupt

enable[2] Xoff[2] Sleep mode[2] modem status

interrupt receive line

status interrupt THR empty

interrupt RX d ata

available

interrupt

R/W

0x02 FCR RX trigger

level (MSB) RX trigger

level (LSB) TX trigger

level (MSB)[2] TX trigger

level (LSB)[2] reserved[3] TX FIFO

reset[4] RX FIFO

reset[4] FIFO enable W

0x02 IIR[5] FIFO enable FIFO enable interrupt

priority bit 4[2] interrupt

priority bit 3[2] interrupt

priority bit 2 interrupt

priority bit 1 interrupt

priority bit 0 interrupt status R

0x03 LCR Divisor Latch

Enable set break set parity even parity parity enable stop bit word length

bit 1 word length

bit 0 R/W

0x04 MCR clock

divisor[2] IrDA mode

enable[2] Xon Any[2] loopback

enable reserved[3] TCR and TLR

enable[2] RTS DTR/(IO5)[6] R/W

0x05 LSR FIFO dat a

error THR and

TSR empty THR empty break interrupt framing error parity error overrun error data in receiver R

0x06 MSR CD/(IO6)[6] RI/(IO7)[6] DSR/ (IO4)[6] CTS CD/ (IO6)[6] RI/(IO7)[6] DSR/ (IO4)[6] CTS R

0x07 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x06 TCR[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x07 TLR[7] bit 7 b it 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x08 TXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

0x09 RXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

0x0A IODir[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x0B IOState[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x0C IOIntEna[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x0D reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3] reserved[3]

0x0E IOControl[6] reserved[3] reserved[3] reserved[3] reserved[3] UART

software

reset[8]

reserved[3] I/O[7:4] or RI,

CD, DTR, DSR latch R/W

0x0F EFCR IrDA mode

(slow/ fast)[9] reserved[3] auto RS-485

RTS output

inversion

auto RS-485

RTS direction

control

reserved[3] transmitter

disable receiver

disable 9-bit mode

enable R/W

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Product data sheet Rev. 7 — 9 June 2011 22 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] These registers are accessible only when LCR[7] = 0.

[2] These bits in can only be modified if register bit EFR[4] is enabled.

[3] These bits are reserved and should be set to 0.

[4] After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2 Tclk of XTAL1 before reading or writing data to RHR and THR, respectively.

[5] Burst reads on the serial interface (that is, reading multiple elements on the I2C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus

without de-asserting the CS pin), should not be performed on the IIR register.

[6] Only available on the SC16IS750/SC16IS760.

[7] These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.

[8] Device returns NACK on I2C-bus when this bit is written.

[9] IrDA mode slow/fast for SC16IS760, slow only for SC16IS750.

[10] The special register set is accessible only when LCR[7] = 1 and not 0xBF.

[11] Enhanced Feature Registers are only accessible when LCR = 0xBF.

Special register set[10]

0x00 DLL bit 7 bit 6 b it 5 bit 4 bi t 3 bit 2 bit 1 bit 0 R/W

0x01 DLH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

Enhanced register se t[11]

0x02 EFR Auto CT S Auto RTS special

character

detect

enable

enhanced

functions

software flow

control bit 3 software flow

control bit 2 software flow

control bit 1 software flow

control bit 0 R/W

0x04 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x05 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x06 XOFF1 bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0x07 XOFF2 bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

Table 10 . SC16IS740/750/760 internal registers …continued

address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

Product data sheet Rev. 7 — 9 June 2011 23 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.1 Receive Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver

Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data

from the RX pin. The data is converted to parallel data and moved to the RHR. The

receiver section is co ntrolled by the L ine Contro l Register. If the FIFO is disabled, locatio n

zero of the FIFO is used to store the characters.

8.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit

Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and

shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If

the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow

occurs.

8.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting

transmitter and receiv er trigger levels. Table 11 shows FIFO Control Register bit settings.

Table 11. FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7] (MSB),

FCR[6] (LSB) RX trigger. Sets the trigger level for the RX FIFO.

00 = 8 characters

01 = 16 characters

10 = 56 characters

11 = 60 characters

5:4 FCR[5] (MSB),

FCR[4] (LSB) TX trigger. Sets the trigger level for the TX FIFO.

00 = 8 spaces

01 = 16 spaces

10 = 32 spaces

11 = 56 spaces

FCR[5:4] can only be modified and enabled when EFR[4] is set. This is

because the transmit trigger level is regarded as an enhanced function.

3 FCR[3] reserved

2FCR[2]

[1] reset TX FIFO

logic 0 = no FIFO transmit reset (normal defa ult condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

level logic (the Tr ansmit Shift Register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

1FCR[1]

[1] reset RX FIFO

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

level logic (the Receive Shift Register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Product data sheet Rev. 7 — 9 June 2011 24 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the

XTAL1 clock.

8.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop

bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12

shows the Line Control Register bit settings.

Table 12. Line Control Register bits description

Bit Symbol Description

7 LCR[7] divisor latch enable

logic 0 = divisor latch disable d (normal default condition)

logic 1 = divisor latch enabled

6 LCR[6] Break control bit. When enabled, the break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default cond ition).

logic 1 = forces the transmitter output (TX) to a logic 0 to alert the

communication terminal to a line break condition

5 LCR[5] Set parity. LCR[5] selects the fo rced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1

for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0

for the transmit and receive data.

4 LCR[4] parity type select

logic 0 = odd parity is generated (if LCR[3] = 1)

logic 1 = even parity is generated (if LCR[3] = 1)

3 LCR[3] parity enable

logic 0 = no parity (normal default condition).

logic 1 = a parity bit is generated during transmission and the receiver

checks for received parity

2 LCR[2] Number of stop bits. Specifies the number of stop bits.

0 to 1 stop bit (word length = 5, 6, 7, 8)

1 to 1.5 stop bits (word length = 5)

1 = 2 stop bits (word length = 6, 7, 8)

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received; see Table 15.

Product data sheet Rev. 7 — 9 June 2011 25 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 13. LCR[5] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X X 0 no parity

0 0 1 odd parity

011even parity

101forced parity ‘1’

111forced parity ‘0’

Table 14. LCR[2] stop bit length

LCR[2] Word length (bits) Stop bit length (bit times)

0 5, 6, 7, 8 1

15 1

12

1 6, 7, 8 2

Table 15. LCR[1:0] word length

LCR[1] LCR[0] Word length (bits)

005

016

107

118

Product data sheet Rev. 7 — 9 June 2011 26 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.5 Line Status Register (LSR)

Table 16 shows the Line Status Register bit settings.

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the

top of the RX FIFO (next character to be read). Therefore, errors in a character are

identified by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when

there are no more errors remaining in the FIFO.

Table 16. Line Status Register bits description

Bit Symbol Description

7 LSR[7] FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error , framing error , or break indication is in the

receiver FIFO. This bit is cleared when no more errors are present in the

FIFO.

6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

5 LSR[5] THR empty. This bit is th e Transmit Holding Register Empty indicator.

logic 0 = transmit hold register is not empty

logic 1 = transmit hold register is empty. The host can now load up to

64 chara c ters of data into the THR if the TX FIFO is enabled.

4 LSR[4] break interrupt

logic 0 = no break condition (normal default condition)

logic 1 = a break condition occurred and associated character is 0x00, that

is, RX was LOW for one character time frame

3 LSR[3] framing error

logic 0 = no framing error in data being read from RX FIFO (normal default

condition).

logic 1 = framing error occurred in data being read from RX FIFO, that is,

received data did not have a valid stop bit

2 LSR[2] parity error.

logic 0 = no parity error (normal default condition)

logic 1 = pari ty error in data being read from R X FIFO

1 LSR[1] overrun error

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error has occurred

0 LSR[0] data in receiver

logic 0 = no data in receive FIFO (normal default condition)

logic 1 = at least one character in the RX FIFO

Product data sheet Rev. 7 — 9 June 2011 27 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 17 shows the Modem Control Register bit settings.

[1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.

[2] Only available on SC16IS750/SC16IS760.

Table 17. Modem Control Register bits description

Bit Symbol Description

7 MCR[7][1] clock divisor

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

6 MCR[6][1] IrDA mode enable

logic 0 = normal UART mode

logic 1 = IrDA mode

5 MCR[5][1] Xon Any

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

4 MCR[4] enable loopback

logic 0 = normal operating mode

logic 1 = enable local Loopback mode (internal). In this mode the

MCR[1:0] signals are looped back into MSR[4:5] and the TX output is

looped back to the RX input internally.

3 MCR[3] reserved

2 MCR[2] TCR and TLR enable

logic 0 = disable the TCR and TLR register.

logic 1 = enable the TCR and TLR register.

1 MCR[1] RTS

logic 0 = force RTS output to inactive (HIGH)

logic 1 = force RTS output to active (LOW). In Loopback mode,

controls MSR[4]. If Auto RTS is enabled, the RTS output is controlled

by hardware flow control.

0 MCR[0] DTR[2]. If GPIO5 is selected as DTR modem pin through IOControl

IOState bit 5 will not have any effect on this pin.

logic 0 = Force DTR output to inactive (HIGH)

logic 1 = Force DTR output to active (LOW)

Product data sheet Rev. 7 — 9 June 2011 28 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.7 Modem Status Register (MSR)

This 8-bit register provides information about th e current st ate of the control lines from the

modem, data set, or peripheral device to the host. It also indicates when a control input

from the modem changes state. Table 18 shows Modem Status Register bit settings.

[1] Only available on SC16IS750/SC16IS760.

Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.

8.8 Scratch Pad Register (SPR)

This 8-bit register is used as a temporary data storage register. User’s program can

write to or read from this register without any effect on the operation of the device.

Table 18. Modem Status Register bits description

Bit Symbol Description

7MSR[7]CD

[1] (active HIGH, logical 1). If GPIO6 is selected as CD modem pin

through IOControl register bit 1, the state of CD pin can be read from this

bit. This bit is the complement of the CD input. Reading IOState bit 6 does

not reflect the true state of CD pin.

6MSR[6]RI

[1] (active HIGH, logical 1). If GPIO7 is selected as RI modem pin through

IOControl register bit 1, the state of RI pin can be read from this bit. This bit

is the complement of the RI input. Reading IOS tate bit 6 does not reflect the

true state of RI pin.

5 MSR[5] DSR[1] (active HIGH, logical 1). If GPIO4 is selected as DSR modem pin

through IOControl register bit 1, the state of DSR pin can be read from this

bit. This bit is the complement of the DSR input. Reading IOSt ate bit 4 does

not reflect the true state of DSR pin.

4 MSR[4] CTS (active HIGH, logical 1). This bit is the compleme nt of the CTS input.

3MSR[3]CD[1]. Indicates th at CD input has changed state. Cleared on a read.

2MSR[2]RI[1]. Indicates that RI input has changed state from LOW to HIGH.

Cleared on a read.

1MSR[1]DSR[1]. Indicates that DSR input has changed state. Cleared on a read.

0MSR[0]CTS. Indicates that CTS input has changed state. Cleared on a read.

Product data sheet Rev. 7 — 9 June 2011 29 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.9 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver

error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of

state from LOW to HIGH. The IRQ output signal is activated in response to interrupt

generation. Table 19 shows the Interrupt Enable Register bit settings.

[1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not

cause a new interrupt if the THR is below the threshold.

[2] Only available on the SC16IS750/SC16IS760.

Table 19. Interrupt Enable Register bits description

Bit Symbol Description

7IER[7]

[1] CTS interrupt enable

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt

6IER[6]

[1] RTS interrupt enable

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt

5IER[5]

[1] Xoff interrupt

logic 0 = disable the Xoff interrupt (normal default condition)

logic 1 = enable the Xoff interrupt

4IER[4]

[1] Sleep mode

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 7.6 “Sleep mode ” for details.

3 IER[3] Modem Status Interrupt[2].

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

Remark: See IOControl register bit 1 in Table 30 for the description of how to

program the pins as modem pins.

2 IER[2] Receive Line Status interrupt

logic 0 = disable the receiver line status interru pt (normal default condition)

logic 1 = enable the receiver line status interrupt

1 IER[1] Transmit Holding Register interrupt.

logic 0 = disable the THR interrupt (normal default condition)

logic 1 = enable the THR interrupt

0 IER[0] Receive Holding Register interrupt.

logic 0 = disable the RHR interrupt (normal default condition)

logic 1 = enable the RHR interru pt

Product data sheet Rev. 7 — 9 June 2011 30 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.10 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a

prioritized manner. Table 20 shows Interrupt Identification Register bit settings.

[1] Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState

[2] Only available on SC16IS750/SC16IS760.

Table 20. Interrupt Identification Register bits description

Bit Symbol Description

7:6 IIR[7:6] mirror the contents of FCR[0]

5:1 IIR[5:1] 5-bit encoded interru pt. See Table 21.

0 IIR[0] interrupt status

logic 0 = an interrupt is pending

logic 1 = no interrupt is pending

Table 21. Interrupt source

Priority

level IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt

1 0 0 0 1 1 0 Receiver Line Status error

2 0 0 1 1 0 0 Receiver time-out interrupt

2 0 0 0 1 0 0 RHR interrupt

3 000010THR interrupt

4 000000modem interrupt

[1][2]

5 1 1 0 0 0 0 input pin change of state[1][2]

6 0 1 0 0 0 0 received Xoff signal/

special character

7 100000CTS

, RTS change of state from

active (LOW) to inactive

(HIGH)

Product data sheet Rev. 7 — 9 June 2011 31 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.11 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 22

shows the enhanced feature register bit settings.

8.12 Division registers (DLL, DLH)

These are two 8-bit registers wh ich store the 16-bit divisor for generation of the baud clo ck

in the baud rate gen er at or. DLH stores the most signif ic an t part of the div iso r. D LL s tor es

the least significant part of the divisor.

Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is,

before IER[4] is set.

Table 22. Enhanced Features Register bits description

Bit Symbol Description

7 EFR[7] CTS flow control enable

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH

signal is detected on the CTS pin.

6 EFR[6] RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when

the receiver FIFO resume transmission trigger level TCR[7:4] is reached.

5 EFR[5] Special character detect

logic 0 = Special character detect disabled (normal default con dition)

logic 1 = S pecial character detect enabled. Received data is compared

with Xoff2 dat a. If a match occurs, the received dat a is tran sferred to FIFO

and IIR[4] is set to a logical 1 to indicate a special character has been

detected.

4 EFR[4] Enhanced functions enable bit

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]

so that they can be modified.

3:0 EFR[3:0] Combinations of software flow control can be selected by programming

these bits. See Table 3 “Software flow control options (EFR[3:0])”.

Product data sheet Rev. 7 — 9 June 2011 32 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.13 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission

during hardware/software flow control. Table 23 shows Transmission Control Register bit

settings.

TCR trigger levels are available from 0 to 60 characters with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer

must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware

check to make sure this condition is met. Also, the TCR must be programmed with this

condition before auto RTS or software flow control is enabled to avoid spurious oper ation

of the device.

8.14 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for

interrupt generation. Trigger levels from 4 to 60 can be programmed with a granu larity

of 4. Table 24 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or

TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)

are used for the tran smit and re ceive FIFO trig ger levels. Trigger levels from 4 characters

to 60 char ac ter s ar e ava ila ble with a gr an u lar ity of fo ur. The TLR should be pro g ramm e d

for N4, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger

level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level

defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger

level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

that is, ‘00’.

8.15 Transmitter FIFO Level register (TXLVL)

This register is a read-only register, it reports the number of spaces available in the

transmit FIFO .

Table 23. Transmission Control Register bits description

Bit Symbol Description

7:4 TCR[7:4] RX FIFO trigger level to resume

3:0 TCR[3:0] RX FIFO trigger level to halt transmission

Table 24. Trigger Level Register bits description

Bit Symbol Description

7:4 TLR[7:4] RX FIFO trigger levels (4 to 60), number of characters available.

3:0 TLR[3:0] TX FIFO trigger levels (4 to 60), number of spaces available.

Table 25. Transmitter FIFO Level reg ister bits description

Bit Symbol Description

7 - not used; set to zeros

6:0 TXLVL[6:0] number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)

Product data sheet Rev. 7 — 9 June 2011 33 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.16 Receiver FIFO Level register (RXLVL)

This register is a read-only register, it reports the fill level of the receive FIFO. That is, the

number of characters in the RX FIFO.

8.17 Programmable I/O pins Direction register (IODir)

This register is only available on the SC16IS750 and SC16IS760. This register is used to

program the I/O pin s dir ec tion . Bit 0 to bit 7 cont ro ls GP IO 0 to GPIO 7.

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending

interrupt will be cleared, that is, the interrupt signal will be negated.

8.18 Programmable I/O pins State Register (IOState)

This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this

transferred to the corresponding IO pin programmed as output.

8.19 I/O Interrupt Enable Register (IOIntEna)

This register is only available on the SC16IS750 and SC16IS760. This register enables

the interrupt due to a ch ange in the I/O configured as input s. If GPIO[7:4] are programmed

as modem pins, their interrupt generation must be enabled via IER register bit 3. In this

case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].

Table 26. Receiver FIFO Level register bits description

Bit Symbol Description

7 - not used; set to zeros

6:0 RXLVL[6:0] number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)

Table 27. IODir register bits description

Bit Symbol Description

7:0 IODir set GPIO pins [7:0] to input or output

0 = input

1 = output

Table 28. IOState register bits description

Bit Symbol Description

7:0 IOState Write this register:

set the logic level on the output pins

0 = set output pin to zero

1 = set output pin to one

Read this register:

return states of all pins

Table 29. IOIntEna register bits description

Bit Symbol Description

7:0 IOIntEna input interrupt enable

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

Product data sheet Rev. 7 — 9 June 2011 34 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.20 I/O Control register (IOControl)

This register is only available on the SC16IS750 and SC16IS760.

Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled

by the following registers: IODir, IOState, IOIntEna, and IOControl. The st ate of CD, RI,

DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these

three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the

state of the DTR pin cannot be controlled by MCR[0].

As modem CD, RI, DSR pins, the status at the input of these three pins can be read from

MSR[7:5] and MS R[3 :1 ], an d th e state of DTR pin can be controlled by MCR[0]. Also, if

modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will

trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not

have any effect on these three pins.

Table 30. IOControl register bits description

Bit Symbol Description

7:4 - reserved for future use

3 SRESET software reset

A write to bit will reset the device. Once the device is reset this bit is

automatically set to ‘0’

2 - reserved for future use

1 GPIO[7:4] or

modem pins This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR

pins.

0 = GPIO[7:4] behave as I/O pins

1 = GPIO[7:4] behave as RI, CD, DTR, DSR

0 IOLATCH enable/disable inputs latching

0 = input values are not latched. A change in any input generates an

interrupt. A read of the input register clears the interrupt. If the input

goes back to its initial logic state before the input register is read,

then the interrupt is cleared.

1 = input values are latched. A change in the input generates an

interrupt and the input logic value is loaded in the bit of the

corresponding input state register (IOState). A read of the IOState

logic state before the interrupt register is read, then the interrup t is

not cleared and the corresponding bit of the IOState regi ster keeps

the logic value that initiates the interrupt.

Product data sheet Rev. 7 — 9 June 2011 35 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.21 Extra Features Control Register (EFCR)

[1] For SC16IS760 only.

9. RS-485 features

9.1 Auto RS-485 RTS control

Normally the RTS pin is contro lled by MCR bit 1, or if hardware flow control is enabled, the

logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR

transmitter will control the state of the RTS pin. The transmitter automatically asserts the

RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin

(logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware flow

control function.

Table 31. Extra Features Control Register bits description

Bit Symbol Description

7 IRDA MODE IrDA mode

0 = IrDA SIR, 316 pulse ratio, data rate up to 115.2 kbit/s

1 = IrDA SIR, 14 pulse ratio, data rate up to 1.152 Mbit/s[1]

6- reserved

5 RTSINVER invert RTS signal in RS-485 mode

0: RTS = 0 during transmission and RTS = 1 during reception

1: RTS = 1 during transmission and RTS = 0 during reception

4 RTSCON enable the transmitter to control the RTS pin

0 = transmitter does not control RTS pin

1 = transmitter controls RTS pin

3- reserved

2 TXDISABLE Disable transmitter. UART does not send serial data out on the

transmit pin, but the transmit FIF O wil l continue to receive data from

host until full. Any data in the TSR will be sent out before the

transmitter goes into disable state.

0: transmitter is enabled

1: transmitter is disabled

1 RXDISABLE Disable receiver. UART will stop receiving data im mediately once this

bit set to a 1, and any data in the TSR will be sent to the receive FIFO.

User is advised not to set this bit during receiving.

0: receiver is enabled

1: receiver is disabled

0 9-BIT MODE Enable 9-bit or Multidrop mode (RS-485).

0: normal RS-232 mode

1: enables RS-485 mode

Product data sheet Rev. 7 — 9 June 2011 36 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9.2 RS-485 RTS output inversion

EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 R TS m ode.

When the transmitter has data to be sent it will deasserts the RTS pin (lo gic 1), and when

the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 mode the software would have to disable the hardware and

software flow control functions.

9.3.1 Normal multidrop mode

The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).

The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time put s this addr ess byte in the RX FIFO. Af ter the controlle r

examines the byte it must make a decision whether or not to enable th e receiver; it should

enable the receiver if the a ddress byte addresse s it s ID addr ess, and mu st not enab le th e

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message

from the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The contro ller then determ ines if the address byte addresses it s ID

address, if it is not, the controller then can disable th e receiver. If the address byte

addresses the ‘slave’ ID address, the controller take no further action, the receiver will

receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register cont ains the

address byte) the receiver will try to detect an address byte that matches the programmed

character in the XOFF2 register . If the received byte is a data byte or an addres s byte that

does not match the programmed character in the XOFF2 register, the receiver will discard

these data. Upon receiving an address byte that matches the Xoff2 character , the receiver

will be automatically enabled if not already enabled, and the address character is pushed

into the RX FIFO along with the p arity bit (in plac e of the parity error bit). T he receiver also

generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match Xoff2 character,

the receiver will be automatically disabled and the address byte is ignored. If the address

byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the

parity bit in the parity error bit (LSR bit 2).

Product data sheet Rev. 7 — 9 June 2011 37 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10. I2C-bus operation

The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both

lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the

bus is not busy. Each device is recognized by a unique address whether it is a

microcomputer, LCD driver, memory or keyboard interface and can operate as either a

transmitter or receiver, depending on the function of the device. A device generating a

message or data is a transmitter, and a device receiving the message or data is a

receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a

microcontroller or a memory can both transmit and receive data.

10.1 Data tran sfers

One data bit is transferred during each clock pulse (see Figure 17). The data on the SDA

line must remain stable during the HIGH period of the clock pulse in order to be valid.

Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW

transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START

condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP

condition (see Figure 18). The bus is considered to be busy after the START condition

and free again at a certain time interval after the STOP condition. The START and STOP

conditions are always generated by the master.

The number of data bytes tran sf er re d be tween the START and STOP condition from

transmitter to receiver is not limited. Each byte, which must be eight bits long, is

transferred serially with the most significant bit first, and is followed by an acknowledge bit

(see Figure 19). The clock pulse related to the acknowledge bit is generated by the

master. The device that acknowledges has to pull down the SDA line during the

acknowledge clock pulse, while the transmitting device releases this pulse (see

Figure 20).

Fig 17. Bit transfer on the I2C-bus

Fig 18. START and STOP conditions

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 7 — 9 June 2011 38 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter.

There are two exceptions to the ‘acknowledge af ter every byte’ rule. The first occurs when

a master is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock, generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative ackn owle d ge ’.

The second exception is that a slave will send a negative acknowledge when it can no

longer accept additional data bytes. This occurs after an attempted transfer that cannot be

accepted.

10.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the

bus, the master transmits on the bus the address of the slave to be accessed for this

transaction. A well-behaved slave with a matching address, if it exists on the networ k,

should of course acknowledge the master's addressing. The addressing is done by the

first byte transmitted by the master after the START condition.

Fig 19. Data transfer on the I2C-bus

S P

SDA

SCL

MSB

0 1 6 7 8 0 1 2 to 7 8

ACK ACK

002aab012

START

condition STOP

condition

acknowledgement signal

from receiver

byte complete,

interrupt within receiver clock line held LOW

while interrupt is serviced

Fig 20. Acknowle dge on the I2C-bus

S01 678

002aab013

data output

by transmitter

data output

by receiver

SCL from master

START

condition

transmitter stays off of the bus

during the acknowledge clock

acknowledgement signal

from receiver

Product data sheet Rev. 7 — 9 June 2011 39 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

An address on the netwo rk is seven bit s long, ap pearing a s the m ost significant b its of the

address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is

transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete

data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is

shown in Figure 21.

When an address is sent, each device in the system compares the first seven bits after

the START with its own address. If there is a match, the device will consider itself

addressed by the master, and will send an acknowledge. The device could also determine

if in this transaction it is assigned the role of a slave receiver or slave transmitter,

depending on the R/W bit.

Each node of the I2C-bus network has a unique seven-bit address. The address of a

microcontroller is of course fully programmable, while peripheral devices usually have

fixed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format

of Figure 21, where the R/W bit could indicate either direction. After completing the

transfer and issuin g a STOP condition, if a master would like to address some other

device on the network, it could start another transaction by issuing a new START.

Another wa y for a master to communicate with several differe nt devices would be by using

a ‘repeated START’. After the last byte of the transaction was transferred, including its

acknowledge (or negative acknowledge), the master issues another START, followed by

address byte and data — without effecting a STOP. The master may communicate with a

number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes

place, the master issues a STOP and releases the bus. Possible data formats are

demonstrated in Figure 22. Note that the repeated START allows for both change of a

slave and a change of direction, without releasin g the bus. We shall see later on that the

change of direction feature can come in handy even when dealing with a single device.

In a single master system, the repeated START mechanism may be more efficient than

terminating each transfer with a STOP and starting again. In a multimaster environment,

the determination of which form at is more efficient could be more comp licated, a s wh en a

master is using repeated STARTs it occupies the bus for a long time and thus preventing

other devices from initiating transfers.

Fig 21. A complete data transfer

S P

SDA

SCL 0 to 6 78

ACK

002aab046

START

condition STOP

condition

address R/W

0 to 6 78

data ACK

0 to 6 78

data ACK

Product data sheet Rev. 7 — 9 June 2011 40 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 22. I2C-bus data formats

002aab458

DATASLAVE ADDRESSmaster write: S W A DATAA A P

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge acknowledge acknowledgewrite

DATASLAVE ADDRESSmaster read: S R A DATAA NA P

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge acknowledge not

acknowledge

read

DATASLAVE ADDRESS

combined

formats: S R/W A DATAA A P

data transferred

(n bytes + acknowledge)

START condition

STOP condition

acknowledge acknowledge acknowledgeread or

write

SLAVE ADDRESSSr R/W A

repeated

START condition acknowledgeread or

write

direction of transfer

may change at this point

data transferred

(n bytes + acknowledge)

Product data sheet Rev. 7 — 9 June 2011 41 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10.3 Addressing

Before any data is transmitted or received, the master must send the address of the

receiver via the SDA line. The first byte after the START condition carries the address of

the slave device an d th e re ad/wr i te bit. Table 32 shows how the SC16IS740/750/760’s

address can be selected by using A1 and A0 pins. For example, if these 2 pins are

connected to VDD, then the SC16IS740/750/760’s ad dress is set to 0x90, and the master

communicates with it through this address.

[1] X = logic 0 for write cycle; X = logic 1 for read cycle.

10.4 Use of subaddresses

When a master commun icates with the SC16IS740/7 50/760 it must send a su baddress in

the byte following the slave address byte. This subaddress is the internal address of the

word the master want s to access for a single byte transfer, or the beginning of a sequence

of locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device

address, it does not cont ain a d irection (R/W) bit, and like any byte transferred on the bus

it must be followed by an acknowledge.

Table 33 shows the breakdown of the subaddress (register address) byte. Bit 0 is not

used, bits [2:1] are both set to zeroes, bits [6:3] are used to select one of the device’s

internal registers, and bit 7 is not used.

A register write cycle is shown in Figure 23. The START is followed by a slave address

byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a

STOP signal. The subaddress indicates which register the master wants to access, and

the data bytes which follow will be written one after the other to the subaddress location.

Table 32. SC16IS740/750/760 address map

A1 A0 SC16IS750/760 I2C addresses (hex)[1]

VDD VDD 0x90 (1001 000X)

VDD VSS 0x92 (1001 001X)

VDD SCL 0x94 (1001 010X)

VDD SDA 0x96 (1001 011X)

VSS VDD 0x98 (1001 100X)

VSS VSS 0x9A (1001 101X)

VSS SCL 0x9C (1001 110X)

VSS SDA 0x9E (1001 111X)

SCL VDD 0xA0 (1010 000X)

SCL VSS 0xA2 (1010 001X)

SCL S CL 0xA4 (1010 010X)

SCL S DA 0xA6 (1010 011X)

SDA VDD 0xA8 (1010 100X)

SDA VSS 0xAA (1010 101X)

SDA SCL 0xAC (1010 110X)

SDA SDA 0xAE (1010 111X)

Product data sheet Rev. 7 — 9 June 2011 42 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 33 and Table 34 show the bits’ presentation at the subaddress byte for I2C-bus and

SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the

UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the

SPI interface to indicate a read or a write operation.

The register read cycle (see Figure 24) commences in a similar manner, with the master

sending a slave ad dr e ss with the dir ec tio n bit se t to ‘writ e’ with a follow ing sub ad d re ss.

Then, in order to reverse the direction of the transfer, the master issues a repeated

START followed again by the device address, but this time with the direction bit set to

‘read’. The data bytes starting at the internal subaddress will be clocked out of the device,

each followed by a master-generated acknowledge. The last byte of the read cycle will be

followed by a negative acknowledge, signalling the end of transfer. The cycle is

terminated by a STOP signal.

White block: host to SC16IS740/750/760

Grey block: SC16IS740/750/760 to host

(1) See Table 33 for additional information.

Fig 23. Master writes to slave

S SLAVE ADDRESS

002aab047

W A REGISTER ADDRESS(1) AnDATA A P

White block: host to SC16IS740/750/760

Grey block: SC16IS740/750/760 to host

(1) See Table 33 for additional information.

Fig 24. M aster read from slav e

S SLAVE ADDRESS

002aab048

W A REGISTER ADDRESS(1) A

NA P

S SLAVE ADDRESS R A

nDATA A LAST DATA

Table 33. Register address byte (I2C)

Bit Name Function

7 - not used

6:3 A[3:0] UART’s internal register select

2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0

Other values are reserved and should not be used.

0 - not used

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Product data sheet Rev. 7 — 9 June 2011 43 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

11. SPI operation

R/W = 0; A[3:0] = register address; CH1 = 0, CH0 = 0

a. Register write

R/W = 1; A[3:0] = register address; CH1 = 0, CH0 = 0

b. Register read

R/W = 0; A[3:0] = 0000; CH1 = 0, CH0 = 0

c. FIFO write cycle

R/W = 1; A[3:0] = 0000; CH1 = 0, CH0 = 0

d. FIFO read cycle

(1) Last bit (D0) of the last byte to be written to the transmit FIFO.

(2) Last bit (D0) of the last byte to be read from the receive FIFO.

Fig 25. SPI operation

SI A1A2A3

R/W

SCLK

CH1A0 XCH0 D6D7 D4D5 D2D3 D0D1 002aab433

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab434

SO D6D7 D4D5 D2D3 D0D1

SI A1A2A3

R/W

SCLK

CH1A0 XCH0 D6D7 D4D5 D2D3 D0D1

002aab435

D6D7 D4D5 D2D3 D0D1

last bit(1)

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab436

SO D6D7 D4D5 D2D3 D0D1 D0D1

last bit

(2)

D6D7 D4D5 D2D3

Product data sheet Rev. 7 — 9 June 2011 44 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

12. Limiting values

[1] 5.5 V steady state volt age tolerance on inputs and outputs is valid only when the supply voltage is present.

4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

Table 34. Register address byte (SPI)

Bit Name Function

7R/W

1: read from UART

0: write to UART

6:3 A[3:0] UART’s internal register select

2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0

Other values are reserved and should not be used.

0 - not used

Table 35. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.3 +4.6 V

VIinput voltage any input 0.3 +5.5[1] V

IIinput current any in put 10 +10 mA

IOoutput current any output 10 +10 mA

Ptot total power dissipation - 300 mW

P/out power dissipation per

output -50mW

Tamb ambient temperature operating

VDD =2.5V0.2 V 40 +85 C

VDD =3.3V0.3 V 40 +95 C

Tjjunction temperature - +125 C

Tstg storage temperature 65 +150 C

Product data sheet Rev. 7 — 9 June 2011 45 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

13. Static characteristics

Table 36 . Static characteristics

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



C; unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

Supplies

VDD supply voltage 2.3 2.7 3.0 3.6 V

IDD supply current operating; no load - 6.0 - 6.0 mA

Inputs I2C/SPI, RX, CTS

VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V

VIL LOW-level input voltage - 0.6 - 0.8 V

ILleakage current input; VI= 0 V or 5.5 V[1] -1-1A

Ciinput capacitance - 3 - 3 pF

Outputs TX, RTS, SO

VOH HIGH-level output voltage IOH =400 A 1.85---V

IOH =4mA - - 2.4 - V

VOL LOW-level output voltage IOL =1.6mA - 0.4 - - V

IOL =4mA - - - 0.4 V

Cooutput capacitance - 4 - 4 pF

Inputs/outputs GPIO0 to GPIO7 (SC16IS750 and SC16IS760 only)

VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V

VIL LOW-level input voltage - 0.6 - 0.8 V

VOH HIGH-level output voltage IOH =400 A 1.85---V

IOH =4mA - - 2.4 - V

VOL LOW-level output voltage IOL =1.6mA - 0.4 - - V

IOL =4mA - - - 0.4 V

ILleakage current input; VI= 0 V or 5.5 V[1] -1-1A

Cooutput capacitance - 4 - 4 pF

RPU pull-up resistance active pull-up resistor 3.94 4.91 3.02 3.63 M

Output IRQ

VOL LOW-level output voltage IOL =1.6mA - 0.4 - - V

IOL =4mA - - - 0.4 V

Cooutput capacitance - 4 - 4 pF

I2C-bus input/output SDA

VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V

VIL LOW-level input voltage - 0.6 - 0.8 V

VOL LOW-level output voltage IOL =1.6mA - 0.4 - - V

IOL =4mA - - - 0.4 V

ILleakage current input; VI= 0 V or 5.5 V[1] -10-10A

Cooutput capacitance - 7 - 7 pF

Product data sheet Rev. 7 — 9 June 2011 46 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

[2] XTAL2 should be left open when XTAL1 is driven by an external clock.

I2C-bus inputs SCL, CS/A0, SI/A1

VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V

VIL LOW-level input voltage - 0.6 - 0.8 V

ILleakage current input; VI= 0 V or 5.5 V[1] -10-10A

Ciinput capacitance - 7 - 7 pF

Clock input XTAL 1[2]

VIH HIGH-level input voltage 1.8 5.5[1] 2.4 5.5[1] V

VIL LOW-level input voltage - 0.45 - 0.6 V

ILleakage current input; VI= 0 V or 5.5 V[1] 30 +30 30 +30 A

Ciinput capacitance - 3 - 3 pF

Sleep current

IDD(sleep) sleep mode supply current inputs are at VDD or ground - 30 - 30 A

Table 36 . Static characteristics …continued

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



C; unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

Product data sheet Rev. 7 — 9 June 2011 47 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

14. Dynamic characteristics

[1] A detailed description of the I2C-bus specification, with applications, is given in user manual UM10204: “I2C-bus specification and user

manual”. This may be found at www.nxp.com/documents/user_manual/UM10204.pdf.

[2] Minimum SCL clock frequency is limited by the bus time-out feature, wh ich resets the serial bus interface if SDA is held LOW for a

minimum of 25 ms.

[3] Only applicable to the SC16IS750 and SC16IS760.

[4] 2 XTAL1 clocks or 3 s, whichever is less.

Table 37 . I2C-bus timing specifications[1]

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



C; and refer to VIL and VIH with

an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.

Symbol Parameter Conditions Standard mode

I2C-bus Fast mode

I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency [2] 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - s

tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - s

tSU;STO set-up time for STOP condition 4.7 - 0.6 - s

tHD;DAT data hold time 0 - 0 - ns

tVD;ACK data valid acknowledge time - 0.6 - 0.6 s

tVD;DAT data valid time SCL LOW to

data out valid -0.6-0.6ns

tSU;DAT data set-up time 250 - 150 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - s

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s

tffall time of both SDA and SCL signals - 300 - 300 ns

trrise time of both SDA and SCL signals - 1000 - 300 ns

tSP pulse width of spikes that must be

suppressed by the input filter -50-50ns

td1 I2C-bus GPIO output valid time [3] 0.5 - 0.5 - s

td2 I2C-bus modem input interrupt valid time 0.2 - 0.2 - s

td3 I2C-bus modem input interrupt clear time 0.2 - 0.2 - s

td4 I2C input pin interrupt valid time 0.2 - 0.2 - s

td5 I2C input pin interrupt clear time 0.2 - 0.2 - s

td6 I2C-bus receive interrupt valid time 0.2 - 0.2 - s

td7 I2C-bus receive interrupt clear time 0.2 - 0.2 - s

td8 I2C-bus transmit interrupt clear time 1.0 - 0.5 - s

td15 SCL delay time after reset [4] 3-3-s

tw(rst) reset pulse width 3 - 3 - s

Product data sheet Rev. 7 — 9 June 2011 48 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 26. SCL delay after reset

002aab437

RESET

SCL

td15

tw(rst)

Rise and fall times refer to VIL and VIH.

Fig 27. I2C-bus timing diagra m

SCL

SDA

HD;STA

SU;DAT

HD;DAT

BUF

SU;STA

LOW

HIGH

VD;ACK

002aab489

SU;STO

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

LSB

(R/W)

acknowledge

(A)

STOP

condition

(P)

SCL

VD;DAT

Fig 28. Write to output (SC16IS750 and SC16IS760 only)

002aab255

SDA A

GPIOn

DATA A

IOSTATE REG.

SLAVE ADDRESS A

td1

Fig 29. Modem input pin inte rrup t (SC1 6IS750 and SC16IS760 only)

002aab256

SDA A R

IRQ

td2

S A DATA A

ACK to master

SLAVE ADDRESSMSR REGISTER

SLAVE ADDRESS A

td3

MODEM pin

Product data sheet Rev. 7 — 9 June 2011 49 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 30. GPIO pin interrupt (SC16IS750 and SC16IS760 only)

002aab257

SDA A R

IRQ

td4

S A DATA A

ACK from master

SLAVE ADDRESSIOSTATE REG.

SLAVE ADDRESS A

td5

GPIOn

ACK from slaveACK from slave

Fig 31. Receive interrupt

D0 D1 D2 D3 D4 D5 D6 D7

002aab258

start

bit

stop

bit

start

bit

td6

IRQ

Fig 32. Receive inte rr upt clear

002aab259

SDA A R

IRQ

S A DATA A

SLAVE ADDRESSRHR

SLAVE ADDRESS A

td7

Fig 33. Transmit interrupt clear

002aab260

SDA

IRQ

ADATA A

THR REGISTER

SLAVE ADDRESS A

Product data sheet Rev. 7 — 9 June 2011 50 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1] Applies to external clock, crystal oscillator max. 24 MHz.

[2]

[3] 100 ppm is recommended.

Table 38 . fXTAL dynamic characteristics

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

tw1 clock pulse duration 10 - 6 - ns

tw2 clock pulse duration 10 - 6 - ns

fXTAL frequency on pin XTAL [1][2] -48

[3] -80MHz

fXTAL 1

tw3

-------

Fig 34. External clock timing

EXTERNAL

CLOCK

002aaa112

tw3

tw2 tw1

Table 39 . SC16IS740/750 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



C; and refer to VIL and VIH with

an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

tTR CS HIGH to SO 3-state delay time CL= 100 pF - - 100 ns

tCSS CS to SCLK setup time 100 - - ns

tCSH CS to SCLK hold time 20 - - ns

tDO SCLK fall to SO valid delay time CL= 100 pF - - 100 ns

tDS SI to SCLK setup time 100 - - ns

tDH SI to SCLK hold time 20 - - ns

tCP SCLK period tCL + tCH 250 - - ns

tCH SCLK HIGH time 100 - - ns

tCL SCLK LOW time 100 - - ns

tCSW CS HIGH pulse width 200 - - ns

td9 SPI output data valid time 200 - - ns

td10 SPI modem output data valid time 200 - - ns

td11 SPI transmit interrupt clear time 200 - - ns

td12 SPI modem input interrupt clear time 200 - - ns

td13 SPI interrupt clear time 200 - - n s

td14 SPI receive interrupt clear time 200 - - ns

tw(rst) reset pulse width 3 - - s

Product data sheet Rev. 7 — 9 June 2011 51 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 40 . SC16IS760 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD =2.5V



0.2 V, Tamb =





Cto+85



C; or VDD =3.3V



0.3 V, Tamb =





Cto+95



C and refer to VIL and VIH with

an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.

Symbol Parameter Conditions VDD =2.5V VDD =3.3V Unit

Min Max Min Max

tTR CS HIGH to SO 3-state delay time CL= 100 pF - 100 - 100 ns

tCSS CS to SCLK setup time 100 - 100 - ns

tCSH CS to SCLK hold time 5 - 5 - ns

tDO SCLK fall to SO valid delay time CL= 100 pF - 25 - 20 ns

tDS SI to SCLK setup time 10 - 10 - ns

tDH SI to SCLK hold time 10 - 10 - ns

tCP SCLK period tCL + tCH 83 - 67 - ns

tCH SCLK HIGH time 30 - 25 - ns

tCL SCLK LOW time 30 - 25 - ns

tCSW CS HIGH pulse width 200 - 200 - ns

td9 SPI output data valid time 200 - 200 - ns

td10 SPI modem output data valid time 200 - 200 - ns

td11 SPI transmit interrupt clear time 200 - 200 - ns

td12 SPI modem input interrupt clear time 200 - 200 - ns

td13 SPI interrupt clear time 200 - 200 - ns

td14 SPI receive interrupt clear time 200 - 200 - ns

tw(rst) reset pulse width 3 - 3 - s

Fig 35. Detailed SPI-bus timing

tCSH tCSS tCL tCH tCSH

tDO tTR

tDS

tDH

SCLK

002aab066

tCSW

Product data sheet Rev. 7 — 9 June 2011 52 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

R/W = 0; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0

Fig 36. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only)

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab438

GPIOx

D6D7 D4D5 D2D3 D0D1

R/W = 0; A[3:0] = MCR (0x04); CH1 = 0; CH0 = 0

Fig 37. SPI write MCR to DTR output switch (SC16IS750 and SC16IS760 only)

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab439

DTR (GPIO5)

D6D7 D4D5 D2D3 D0D1

d10

R/W = 0; A[3:0] = THR (0x00); CH1 = 0; CH0 = 0

Fig 38. SPI write THR to clear TX INT

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab440

D6D7 D4D5 D2D3 D0D1

d11

IRQ

Product data sheet Rev. 7 — 9 June 2011 53 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

R/W = 1; A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0

Fig 39. Read MSR to clear modem INT (SC16IS750 and SC16IS76 0 only)

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab441

td12

IRQ

D6D7 D4D5 D2D3 D0D1

R/W = 1; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0

Fig 40. Read IOState to clear GPIO INT (SC16IS750 and SC16IS760 only)

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab442

td13

IRQ

D6D7 D4D5 D2D3 D0D1

R/W = 1; A[3:0] = RHR (0x00); CH1 = 0; CH0 = 0

Fig 41. Read RHR to clear RX INT

SI A1A2A3

R/W

SCLK

CH1A0 XCH0

002aab443

td14

IRQ

D6D7 D4D5 D2D3 D0D1

Product data sheet Rev. 7 — 9 June 2011 54 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

15. Package outline

Fig 42. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 7 — 9 June 2011 55 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 43. Package outline SOT616-3 (HVQFN24)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.75

2.45

4.1

3.9 2.75

2.45

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-3 MO-220 04-11-19

05-03-10

- - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616-3

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

712

24 19

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 7 — 9 June 2011 56 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Fig 44. Package outline SOT355-1 (TSSOP24)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 7 — 9 June 2011 57 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate pre ca u tio ns ar e taken as

described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 7 — 9 June 2011 58 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 45) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low en ough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 41 and 42

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 45.

Table 41. SnPb eutectic process (from J-STD-0 20C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 42. Lead-free pr ocess (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 7 — 9 June 2011 59 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 45. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 43. Abbreviations

Acronym Description

CPU Central Processing Unit

FIFO First In, First Out

GPIO General Purpose Input/Output

I2C-bus Inter IC bus

IrDA Infrared Data Association

LCD Liquid Crystal Disp lay

MIR Medium InfraRed

POR Power-On Rese t

SIR Serial InfraRed

SPI Serial Peripheral Interface

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 7 — 9 June 2011 60 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

19. Revision history

Table 44. Revision history

Document ID Release date Data sheet status Change notice Supersedes

SC16IS740_750_760 v.7 20110609 Product data sheet - SC16IS740_750 _760 v.6

Modifications: •Table 1 “Ordering information”:

–Added type number SC16IS740IPW/Q900.

–Added new Table note 1.

•Figure 5 “Pin configuration for TSSOP16”: added type number SC16IS740IPW/Q900

•Table 2 “Pin description”: added (new) Table note [2] and references to it at GPIO0 to

GPIO7.

•Added (new) Section 7.4.2 “Power-on sequence”.

•Section 7.6 “Sleep mode”: added second, third, and fourth paragraphs following first

“Remark”.

•Section 7.8 “Programmable baud rate generator”: added second sentence to paragraph

following second “Remark”.

•Table 10 “SC16IS740/750/760 internal registers”: added (new) Table note [8] and its

reference at IOC o ntrol bit 3.

•Added (new) Section 8.8 “Scratch Pad Register (SPR)”.

•Table 36 “Static characteristics”, sub-section “Inputs/outputs GPIO0 to GPIO7”: added

specification for “RPU, pull-up resistance”

•Table 38 “fXTAL dynamic characteristics”: added (new) Table note [3 ] and its reference at

fXTAL maximum value (at VDD =2.5V).

SC16IS740_750_760 v.6 20080513 Product data sheet - SC16IS740_750_760 v.5

SC16IS740_750_760 v.5 20061116 Product data sheet - SC16IS740_750_760 v.4

SC16IS740_750_760 v.4 20061030 Product data sheet - SC16IS740_750_760 v.3

SC16IS740_750_760 v.3 20060522 Product data sheet - SC16IS740_750_760 v.2

SC16IS740_750_760 v.2 20060330 Product data sheet - SC16IS740_750_760 v.1

SC16IS740_750_760 v.1

(9397 750 14832) 20060104 Product data sheet - -

Product data sheet Rev. 7 — 9 June 2011 61 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environment al

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 7 — 9 June 2011 62 of 63

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 June 2011

Document identifier: SC16IS740_750_760

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 General features. . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 I2C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . . 9

7.1 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2 Hardware flow control. . . . . . . . . . . . . . . . . . . . 9

7.2.1 Auto RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.2.2 Auto CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.3 Software flow control . . . . . . . . . . . . . . . . . . . 11

7.3.1 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.3.2 TX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.4 Reset and power-on seque nce. . . . . . . . . . . . 13

7.4.1 Hardware reset, Power-On Reset (POR)

and software reset . . . . . . . . . . . . . . . . . . . . . 13

7.4.2 Power-on sequence . . . . . . . . . . . . . . . . . . . . 14

7.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.5.1 Interrupt mode operation . . . . . . . . . . . . . . . . 16

7.5.2 Polled mode operation . . . . . . . . . . . . . . . . . . 16

7.6 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.7 Break and time-out conditions . . . . . . . . . . . . 17

7.8 Programmable baud rate generator . . . . . . . . 18

8 Register descriptions . . . . . . . . . . . . . . . . . . . 20

8.1 Receive Holding Register (RHR) . . . . . . . . . . 23

8.2 Transmit Holding Register (THR) . . . . . . . . . . 23

8.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 23

8.4 Line Control Register (LCR). . . . . . . . . . . . . . 24

8.5 Line Status Register (LSR). . . . . . . . . . . . . . . 26

8.6 Modem Control Register (MCR). . . . . . . . . . . 27

8.7 Modem Status Register (MSR). . . . . . . . . . . . 28

8.8 Scratch Pad Register (SPR). . . . . . . . . . . . . . 28

8.9 Interrupt Enable Register (IER) . . . . . . . . . . . 29

8.10 Interrupt Identification Register (IIR). . . . . . . . 30

8.11 Enhanced Features Register (EFR) . . . . . . . . 31

8.12 Division registers (DLL, DLH). . . . . . . . . . . . . 31

8.13 Transmission Control Register (TCR). . . . . . . 32

8.14 Trigger Level Register (TLR) . . . . . . . . . . . . . 32

8.15 Transmitter FIFO Level register (TXLVL) . . . . 32

8.16 Receiver FIFO Level register (RXLVL). . . . . . 33

8.17 Programmable I/O pins Direction

8.18 Programmable I/O pins State Register

(IOState). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.19 I/O Interrupt Enable Register (IOIntEna) . . . . 33

8.20 I/O Control register (IOCon trol) . . . . . . . . . . . 34

8.21 Extra Features Control Register (EFCR) . . . . 35

9 RS-485 features. . . . . . . . . . . . . . . . . . . . . . . . 35

9.1 Auto RS-485 RTS control . . . . . . . . . . . . . . . 35

9.2 RS-485 RTS output inversion . . . . . . . . . . . . 36

9.3 Auto RS-485 . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.3.1 Normal multidrop mode . . . . . . . . . . . . . . . . . 36

9.3.2 Auto address detection . . . . . . . . . . . . . . . . . 36

10 I2C-bus operation . . . . . . . . . . . . . . . . . . . . . . 37

10.1 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . 37

10.2 Addressing and transfer formats . . . . . . . . . . 38

10.3 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.4 Use of subaddresses. . . . . . . . . . . . . . . . . . . 41

11 SPI operation. . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 44

13 Static characteristics . . . . . . . . . . . . . . . . . . . 45

14 Dynamic chara cteristics. . . . . . . . . . . . . . . . . 47

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 54

16 Handling information . . . . . . . . . . . . . . . . . . . 57

17 Soldering of SMD packages. . . . . . . . . . . . . . 57

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 57

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 57

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 57

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 58

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 59

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 60

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 61

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 61

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 61

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62

21 Contact information . . . . . . . . . . . . . . . . . . . . 62

22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63