Fast-Pattern-Processor - Agere Systems, Inc.

Product Brief

November 2001

PayloadPlus Fast Pattern Processor

Introduction

The Agere Systems PayloadPlus architecture

provides a unique hardware and software

com bination that delivers high-speed processing

for multiple communication protocols with full

programmability. This combination gives you the

programmability of traditional RISC processors

with the speed that, until now, only ASICs could

deliver.

The Agere Systems PayloadPlus product family

represents a technology revolution for the

constr uc tion of intell ig ent co mmu nic ati on

equipment with Layer 3 or above processing

capabilities. Agere Systems products focus on the

wire-speed datapath functions and work in

conjunction with physical interface devices, low-

speed microprocessor, and backplane fabric

offerings to provide a complete solution for

networking and communication applications. The

PayloadPlus processor family includes the Fast

Pattern Processor (FPP), Routing Switch

Processor (RSP), and the Agere System Interface

(ASI).

The Agere Systems PayloadPlus Processors are

designed to handle wire-speed data streams at up

to OC-48c rates. Each chip provides a

complementary function: the FPP for high-speed

classification, the RSP for processing and routing

traffic, and the ASI to provide policing, manage

state information, and provide a PCI connection to

a host processor.

The FPP accepts a data stream of protocol data

units (PDUs) from an industry-standard POS-

PHY/UTOPIA Level 3 interface. The PDUs are

analyzed and classified, and the FPP outputs the

packets and conclusions to the RSP on a POS-

PHY Level 3 interface.

Fast Pattern Processor

At the heart of the PayloadP l us pr odu ct family is

the Functional Programming Language (FPL) and

patented Fast Pattern Processor (FPP)

technology. Using the powerful, high-level FPL

code, the FPP implements complex pattern or

signature recogn ition and ope ra tes on the

packets/cells containing those signatures. The

FPP has the ability to perform pattern analysis on

every byte of the payload plus headers of a data

stream. The pattern analysis conclusions are

made available to the customer’s system logic or

to the Agere Systems Routing Switch Processor

(RSP), allowing packet /cell manipulation and

queuing functions. The FPP and RSP provide a

complete solution for switching and routing.

The FPP can be used with Agere Systems other

PayloadPlus components or on its own. The FPP

provides glueless interfaces to the RSP and the

ASI ICs to provide a complete solution for wire-

speed processing in next-generation terabit

switches and routers.

System Overview

The FPP accepts a data stream of frames or cells

from an industry-standard UTOPIA Level 3/

UTOPIA Level 2/POS-PHY Level 3 interface. The

FPP analyzes and classifies these frames and

cells, reasse mbles them into PDUs, then

transmits the PDU s and its classification

conclusions to the Routing Switch Processor over

a POS-PHY Level 3 interface. The FPP is

configured and updated through the Configuration

Bus, which connects the FPP and other devices

to the ASI.

Product Brief NPFPP

March 2002 Fast Pattern Processor

Features and Benefits of the FPP

The key benefits of the Fast Pattern Processor are:

■Programmability—The FPP’s programmability gives you

great flexibility to optimize performance for a wide variety

of applications and protocols.

■Fast, Deterministic Searches—The FPP’s p atented search

algorithm lets you create large lists and search them

quickly, within deterministic time limits. You can search for

data patterns of any size. Search time is independent of

the number of entries in the search table; it depends only

on the size of the data pattern.

■Use of Standard Memory—The FPP stores pattern

matching data in standard memory instead of expensive

content-addressable memory (CAM) devices.

■High Performance at Lower Clock Speeds—The FPP’s

efficient design lets it support OC-48c speeds with an

internal clock speed much lower than that of the

competition. This translates into lower hardware costs and

scalability for the future.

■Segmentation and Reassembly (SAR)—The FPP and

RSP combination provides ATM SARing capabilities,

eliminating the need for separate SARing ICs.

FPP Applications

The Agere Systems FPP handles complex multi-protocol

information at wire speeds up to 2.5 Gbps or OC-48c. The

FPP processes the protocols and applications required by

carrier and enterprise edge systems. Supported protocols

include IP, ATM, Frame Relay , MPLS, and AAL5. Applications

include:

■Routing

■Switching

■Network management and firewalls

■Monitoring

■ATM segmentation and reassembly

■Frame Relay segmentation and reassembly

■Access Control List proc essing

Since the FPP is a programmable processor, not a fixed-

function ASIC, it can handle new protocols or applications as

they are developed or as new network functions are required.

Note that the FPP is devoted to the wire-speed data path.

Non-real-time functions, such as routing table updates, are

handled by a separate external microprocessor. The RSP is

designed to process FPP outputs, although other application

logic can be used.

FPP Interfaces

The FPP has the following interfaces:

■Data path interfaces—The FPP uses an industry-standard

UTOPIA Level 3/UTOPIA Level 2/POS-PHY Level 3

interface for the data path input, and a POS-PHY Level 3

interface for data path output.

■Memory interfaces—64-bit interfaces to standard PC-133

SDRAM and 133-MHz pipelined ZBT-style SSRAM.

■Management interface—The Management Path Interface

(MPI) enables the FPP to receive management frames

from the local microprocessor (through the ASI).

ASI

RSPFPP

Physical

Interface

8-bit POS-PHY 8-b it POS-PHY

PCI to Host CP U

FBI

Configuration Bus

POS-PHY POS-PHY

UTOPIA UTOPIA

Fabric

Interface

Controller

System Overview

Fabric

Product Brief NPFPP

March 2002 Fast Pattern Processor

■Function pr ocessing interface—The Functio nal Bus

Interface (FBI) connects the FPP to an ASI and/or custom

logic for external processing of function calls.

■Configuration interface—The Configuration Bus Interface

(CBI) enables an ASI or custom logic to configure the FPP,

RSP, and other system devices.

FPP Classification and Analysis Capabilities

Through the use of the FPP’s built-in functions and custom

functions that you create, the FPP can be programmed to:

■Assemble packets embedded in another protocol, such as

IP over ATM.

■Identify pr otocol s and perform processing bas ed on the

PDU information.

■Perform PDU checksums and cyclic redundancy checks

(CRCs).

■Perform fast table look-ups and execute functions based

on the values found .

Fast-Path and Slow-Path Functions

In Agere Systems network processors, processing tasks

occur in one of two domains, called the fast (wire-speed) path

and the slow path. The fast path includes all tasks necessary

for normal data stream processing. The slow path includes

tasks such as exception handling, management,

configuration, and updates. The figure that follows shows

how PayloadPlus devices and buses are divided between the

fast path and the slow path.

The following table lists the tasks that the PayloadPlus products

performs, and how each is divided between the fast path and the

slow path.

data stream

FPP

external

processor

ASI

PCI

MPI MPI

RSP

CBI

FBI FAST

PATH

SLOW

PATH

Fast-Path and S low -Path Components

Task Fast Path Slow Path

Normal data stream processing FPP classifies, modifies, and reassembles PDUs; external func-

tion calls hand led by A SI and passed via FBI. RSP mo dif ie s

PDUs an d performs tr affic m an agement and sha p i ng.

—

Maintain state information across PDU

boundaries ASI stores; FPP reads and writes via FBI.

Management PDUs FPP and RSP generate or forwa rd. RSP forwards via MPI; ASI forwa rds to exter nal proc e ssor

via PCI; external processor sends commands to ASI via PCI;

ASI sends new PDUs to FPP via MPI.

Exception ha ndl ing FPP and RSP generate exc epti on PDUs.

Protocol proc essing (e.g., setting up

PVCs & SVCs) FPP and RSP update internal tables as req uired .

Policing FPP performs policing; reads and writes control information via

FBI. External processor transmits policing parameters and service

level agreements to ASI via PCI; ASI sends updates to exter-

nal processor via PCI.

Statistics ASI stores; FPP reads and writes via FBI. External processor requests curr ent statistics from ASI, or

sends reset commands to ASI, via MPI.

Configura t ion — External processor sends information to ASI via PCI; ASI

sends to FPP, RSP, and other devi ces via CBI.

Load ing contro l programs

Dynamic updates (ro uting tables, ACLs,

connec ti on ta bles)

Product Brief NPFPP

March 2002 Fast Pattern Processor

FPP Performance With the RSP

The FPP is complemented by the Routing Switch Processor

(RSP). The RSP is also programmable, and works in concert

with the FPP to process the PDUs classified by the FPP. The

RSP uses the classification information received from the

FPP to determine:

■The starting offset and the length of the PDU payload.

■The classification conclusion for the PDU. This information

determines the port and the associated RSP processing

selected for the PDU.

■Additional PDU information passed in the form of flags.

The R SP provides programmable traffic management,

including policies such as:

■Random Early Discard (RED)

■Weighted Random Early Discard (WRED)

■Early Packet Discard (EPD)

■Partial Packet Discard (PPD)

The RSP also provides:

■Program mable Traffic Shaping, inclu di ng pro gramm abl e

per queue QoS and CoS.

—QoS policies include constant bit rate (CBR), unspecified

bit rate (UBR), and variable bit rate (VBR).

—CoS policies include fixed priority, round robin, weighted

round robin (WRR), weighted fair queuing (WFQ), and

guaranteed frame rate (GFR).

■Programmable Packet Modifications, including adding/

stripping headers and trailers, rewriting or modifying

contents, adding tags, updating checksums and CRCs.

You program the RSP using a scripting language with

semantics similar to the C language. Agere Systems provides

many common scripts which you can use or modify, or you

can write your own scri pts.

How the FPP Works

The FPP is a pipelined, multithreaded processor that

simultaneously analyzes and classifies up to 64 PDUs. Each

PDU has its own processing thread, called a context. A

context is a processing path that keeps track of all of the

blocks of a PDU, the number of the port on which the PDU

arrived, the data offset for the PDU, last-block information,

any program variables for the PDU, and the PDU’s

classification information.

The FPP does not use speculative execution and does not

suffer the pipeline stalls or context switching overhead that

are usually associated with sequential processing

arch itectures. The FPP processes data in two passes:

■The first pass processes PDUs as sepa rate 64-byte

blocks. The first pass typically stores the block data offsets

and links the blocks that compose the PDU.

■The replay pass processes the PDU as a whole. In the

replay pass, the FPP simultaneously performs pattern

matching and transmits the PDU to the output interface,

which performs reassembly, if necessary, by stripping data

from the blocks of the PDU using the data offsets defined

in the first pass.

The exact processing that occurs in both the first and replay

passes is specified by programs written in Agere Systems’

Functional Programming Language.

FPP Components

■Input Framer—frames the input stream into 64-byte blocks,

writes the blocks into the data buffer, and writes the blocks

and their configuration information into the block buffers

and cont ext memo ry.

■Output Inte rface —sends PDUs (stripped according to

block offsets) and their classification conclusions to the

downstream logic.

■Block Buffers and Context Memory—stores the blocks

being processed for each context, along with additional

context information.

■Pattern Processing Engine (PPE)—performs pattern

matchi ng to determi ne how PDUs are clas si fied and

processed.

■Checksum /CRC Eng ine—performs checksum and CRC

calculations.

■Queue En gine—manages FPP replay contexts, provides

addresses for block buffers, and maintains information on

blocks, PDUs, and connection queues.

■Arithmetic Logic Unit—performs computational functions.

■Management Path Interface—provides an input path from

the ASI for management PDUs.

■Configuration Bus Interface—provides access to the FPP,

RSP, and physical input interface for configuring registers

and memor y.

■Functional Bus Interface (FBI)—passes external FPL

function calls to external logic.

The figure below shows the major components of the FPP.

Product Brief NPFPP

March 2002 Fast Pattern Processor

Input

Framer Output

Interface

Block Buffers and

Context Memory

Queue

Engine

Pattern

Processing

Engine

Functional Bus

Interface

Configuration

Bus Interface

Data

Buffer

Control

Memory

Program

Memory

FPP

32-bit UTOPIA/POS-PHY

from PHY

8-bit POS-PHY

Management Path

Interface from ASI

32-b i t POS-PHY

to RSP

8-bit CBI

32-bit FBI to ASI

Checksum/

CRC Engine

ALU

Data

Buffer

Controller

FPP Block Diagram

Agere Systems, In c. reserves the right to make changes to the pr oduct(s) or inform ation contained he rein without notice . No liability is assumed as a re sult of their use or application. P ayloadPlus

is a Trademark of Agere Systems, Inc.

Printed in U.S.A.

3/13/02

PB01-132NP

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