K6F4008U1C Family CMOS SRAM Document Title 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft August 30, 1999 Preliminary 1.0 Finalize - Adopt new code. - Improve VIN, VOUT max. on ABSOLUTE MAXIMUM RATINGS from 3.6V to VCC+0.5V. March 22, 2000 Final 2.0 Change for AC parameter - Change for tWHZ: 25 to 20ns for 70ns product - Change for tDW: 20 to 25ns for 55ns product 25 to 30ns for 70ns product April 24, 2000 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM 512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION * * * * * * The K6F4008U1C families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support small package type for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. Process Technology: Full CMOS Organization: 512K x8 bit Power Supply Voltage: 2.7~3.3V Low Data Retention Voltage: 1.5V(Min) Three state output status and TTL Compatible Package Type: 32-TSOP1-0813.4F PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) Operating (ICC1, Max) PKG Type K6F4008U1C-F Industrial(-40~85C) 2.7~3.3V 551)/70ns 0.5A 3mA 32-TSOP1-0813.4F 1. The parameter is measured with 30pF test load. PIN DESCRIPTION A11 A9 A8 A13 WE A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name 32-STSOP1 (Forward) Function FUNCTIONAL BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Name OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Clk gen. Row Address Function CS Chip Select Input Vcc Power WE Write Enable Input Vss Ground OE Output Enable Input I/O1~I/O8 Data Inputs/Outputs Row select Data cont I/O1 I/O8 Precharge circuit. Memory array 2048 rows 256x8 columns I/O Circuit Column select Data cont A0~A18 Address Inputs Column Address CS WE Control logic OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name Function K6F4008U1C-YF55 K6F4008U1C-YF70 32-sTSOP1-F, 55ns, 3.0V 32-sTSOP1-F, 70ns, 3.0V FUNCTIONAL DESCRIPTION CS OE WE I/O H X1) X1) L H H L L L 1) X Mode Power High-Z Deselected Standby High-Z Output Disabled Active H Dout Read Active L Din Write Active 1. X means dont care.(Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.5V V VCC -0.2 to 4.0V V PD 1.0 W TSTG -65 to 150 C TA -40 to 85 C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -3- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 2.7 3.0 3.3 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.32) V Input low voltage VIL - 0.6 V -0.2 3) Note: 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol ILI Test Conditions Min Typ Max Unit VIN=Vss to Vcc -1 - 1 A Output leakage current ILO CS=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, WE=VIH, VIN=VIL or VIH - - 2 mA ICC1 Cycle time=1s, 100%duty, IIO=0mA, CS0.2V, VIN 0.2V or VINVCC-0.2V - - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH - - 30 mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA Standby Current (CMOS) ISB1 CSVcc-0.2V, Other input =0~Vcc - 0.5 121) A Average operating current 1. Super low power product=5A with special handling. -4- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM VTM3) AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) R12) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.1V Output load (See right): C L=100pF+1TTL CL=30pF+1TTL CL1) R22) 1. Including scope and jig capacitance 2. R1=3070, R2 =3150 3. VTM =2.8V AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product: TA=-40 to 85C) Speed Bins Parameter List Read Symbol Units 70ns Min Max Min Max Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Select to Output tCO - 55 - 70 ns Output Enable to Valid Output tOE - 25 - 35 ns Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Write 55ns tLZ 10 - 10 - ns tOLZ 5 - 5 - ns tHZ 0 20 0 25 ns tOHZ 0 20 0 25 ns Output Hold from Address Change tOH 10 - 10 - ns Write Cycle Time tWC 55 - 70 - ns Chip Select to End of Write tCW 45 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - ns Write Pulse Width tWP 40 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 20 0 20 ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CSVcc-0.2V Data retention current IDR Vcc=1.5V, CSVcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 1.5 - 3.3 V A - 0.5 31) 0 - - tRC - - ns 1. Super low power product=2A with special handling. -5- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. -6- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tCW(2) tAS(3) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low: A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 2.7V 2.2V VDR CSVCC - 0.2V CS GND -7- Revision 2.0 April 2000 K6F4008U1C Family CMOS SRAM 32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 0.008+0.004 -0.002 0.20 Unit: millimeters(inches) 13.400.10 0.5280.008 #1 #32 8.40 0.331 MAX #17 #16 0.25 0.010 TYP 1.000.10 0.0390.004 1.20 0.047 MAX 11.800.10 0.4650.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.15 0~8 0.45 ~0.75 0.018 ~0.030 ( -8- 1.10 MAX 0.004 MAX 0.50 0.0197 0.25 ) 0.010 8.00 0.315 ( 0.50 ) 0.020 Revision 2.0 April 2000