Revision 2.0
April 2000
K6F4008U1C Family
- 1 -
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
1.0
2.0
Remark
Preliminary
Final
Final
History
Initial draft
Finalize
- Adopt new code.
- Improve VIN, VOUT max. on ′ABSOLUTE MAXIMUM RATINGS′ from
3.6V to VCC+0.5V.
Change for AC parameter
- Change for tWHZ: 25 to 20ns for 70ns product
- Change for tDW: 20 to 25ns for 55ns product
25 to 30ns for 70ns product
Draft Date
August 30, 1999
March 22, 2000
April 24, 2000
Revision 2.0
April 2000
K6F4008U1C Family
- 2 -
CMOS SRAM
PRODUCT FAMILY
1. The parameter is measured with 30pF test load.
Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type
Standby
(ISB1, Typ.) Operating
(ICC1, Max)
K6F4008U1C-F Industrial(-40~85°C) 2.7~3.3V 551)/70ns 0.5µA3mA 32-TSOP1-0813.4F
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
GENERAL DESCRIPTION
The K6F4008U1C families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
small package type for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
FEATURES
• Process Technology: Full CMOS
• Organization: 512K x8 bit
• Power Supply Voltage: 2.7~3.3V
• Low Data Retention Voltage: 1.5V(Min)
• Three state output status and TTL Compatible
• Package Type: 32-TSOP1-0813.4F
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
FUNCTIONAL BLOCK DIAGRAM
Precharge circuit.
Memory array
2048 rows
256×8 columns
I/O Circuit
Column select
Clk gen.
Row
select
CS
WE
I/O1Data
cont
Data
cont
OE
I/O8
Control
logic
Name Function Name Function
CS Chip Select Input Vcc Power
WE Write Enable Input Vss Ground
OE Output Enable Input I/O1~I/O8Data Inputs/Outputs
A0~A18 Address Inputs
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
(Forward)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-STSOP1
PIN DESCRIPTION
Row
Address
Column Address
Revision 2.0
April 2000
K6F4008U1C Family
- 3 -
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit
Voltage on any pin relative to Vss VIN, VOUT -0.2 to VCC+0.5V V
Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0V V
Power Dissipation PD1.0 W
Storage temperature TSTG -65 to 150 °C
Operating Temperature TA-40 to 85 °C
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name Function
K6F4008U1C-YF55
K6F4008U1C-YF70 32-sTSOP1-F, 55ns, 3.0V
32-sTSOP1-F, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
1. X means don′t care.(Must be in low or high state)
CS OE WE I/O Mode Power
HX1) X1) High-Z Deselected Standby
LH H High-Z Output Disabled Active
L L HDout Read Active
LX1) LDin Write Active
Revision 2.0
April 2000
K6F4008U1C Family
- 4 -
CMOS SRAM
DC AND OPERATING CHARACTERISTICS
1. Super low power product=5µA with special handling.
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 -1µA
Output leakage current ILO CS=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS=VIL, WE=VIH, VIN=VIL or VIH - - 2mA
Average operating current ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 3mA
ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH - - 30 mA
Output low voltage VOL IOL = 2.1mA - - 0.4 V
Output high voltage VOH IOH = -1.0mA 2.4 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA
Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other input =0~Vcc -0.5 121) µA
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Min Typ Max Unit
Supply voltage Vcc 2.7 3.0 3.3 V
Ground Vss 000V
Input high voltage VIH 2.2 -Vcc+0.32) V
Input low voltage VIL -0.23) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested.
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
Revision 2.0
April 2000
K6F4008U1C Family
- 5 -
CMOS SRAM
DATA RETENTION CHARACTERISTICS
1. Super low power product=2µA with special handling.
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS≥Vcc-0.2V 1.5 -3.3 V
Data retention current IDR Vcc=1.5V, CS≥Vcc-0.2V -0.5 31) µA
Data retention set-up time tSDR See data retention waveform 0- - ns
Recovery time tRDR tRC - -
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.1V
Output load (See right): CL=100pF+1TTL
CL=30pF+1TTL CL1)
1. Including scope and jig capacitance
R22)
R12)
VTM3)
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)
Parameter List Symbol
Speed Bins
Units
55ns 70ns
Min Max Min Max
Read
Read Cycle Time tRC 55 -70 -ns
Address Access Time tAA -55 -70 ns
Chip Select to Output tCO -55 -70 ns
Output Enable to Valid Output tOE -25 -35 ns
Chip Select to Low-Z Output tLZ 10 -10 -ns
Output Enable to Low-Z Output tOLZ 5-5-ns
Chip Disable to High-Z Output tHZ 020 025 ns
Output Disable to High-Z Output tOHZ 020 025 ns
Output Hold from Address Change tOH 10 -10 -ns
Write
Write Cycle Time tWC 55 -70 -ns
Chip Select to End of Write tCW 45 -60 -ns
Address Set-up Time tAS 0-0-ns
Address Valid to End of Write tAW 45 -60 -ns
Write Pulse Width tWP 40 -50 -ns
Write Recovery Time tWR 0-0-ns
Write to Output High-Z tWHZ 020 020 ns
Data to Write Time Overlap tDW 25 -30 -ns
Data Hold from Write Time tDH 0-0-ns
End Write to Output Low-Z tOW 5-5-ns
Revision 2.0
April 2000
K6F4008U1C Family
- 6 -
CMOS SRAM
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
CS
Address
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
tOH
tAA
tOLZ
tLZ tOHZ
tHZ
tRC
tOE
tCO
Revision 2.0
April 2000
K6F4008U1C Family
- 7 -
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS
tCW(2) tWR(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
CS
tWC
tWR(4)
tAS(3)
tWP(1)
tDW tDH
tOW
tWHZ
Data Undefined
Data Valid
WE
Data in
Data out
tDW tDH
Data Valid
WE
Data in
Data out High-Z High-Z
tWC
tAW
tAS(3)
tCW(2)
tWP(1)
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low: A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
2.7V
2.2V
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
Revision 2.0
April 2000
K6F4008U1C Family
- 8 -
CMOS SRAM
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00±0.10
0.039±0.004
MAX
8.40
0.331
1.10 MAX
0.004 MAX
#1
0.50
( )
0.020
11.80±0.10
0.465±0.004
0.45 ~0.75
0.018 ~0.030
13.40±0.10
0.528±0.008
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
#32
#17
Unit: millimeters(inches)
