LM5025CMTCE/NOPB - NATIONAL SEMICONDUCTOR

LM5025C

LM5025C Active Clamp Voltage Mode PWM Controller

Literature Number: SNVS568B

LM5025C

April 23, 2009

Active Clamp Voltage Mode PWM Controller

General Description

The LM5025C is a functional variant of the LM5025 active

clamp PWM controller. The functional differences of the

LM5025C are: The maximum duty cycle of the LM5025C is

increased from 80% to 91%. The soft-start capacitor charging

current is increased from 20 µA to 90 µA. The VCC regulator

current limit threshold is increased from 25 mA to 55 mA. The

CS1 and CS2 current limit thresholds have been increased to

0.5V. The internal CS2 filter discharge device has been dis-

abled and no longer operates each clock cycle. The internal

VCC and VREF regulators continue to operate when the line

UVLO pin is below threshold.

The LM5025C PWM controller contains all of the features

necessary to implement power converters utilizing the Active

Clamp / Reset technique. With the active clamp technique,

higher efficiencies and greater power densities can be real-

ized compared to conventional catch winding or RDC clamp /

reset techniques. Two control outputs are provided, the main

power switch control (OUT_A) and the active clamp switch

control (OUT_B). The two internal compound gate drivers

parallel both MOS and Bipolar devices, providing superior

gate drive characteristics. This controller is designed for high-

speed operation including an oscillator frequency range up to

1MHz and total PWM and current sense propagation delays

less than 100 ns. The LM5025C includes a high-voltage start-

up regulator that operates over a wide input range of 13V to

90V. Additional features include: Line Under Voltage Lockout

(UVLO), softstart, oscillator UP/DOWN sync capability, pre-

cision reference and thermal shutdown.

Features

■Internal Start-up Bias Regulator

■3A Compound Main Gate Driver

■Programmable Line Under-Voltage Lockout (UVLO) with

Adjustable Hysteresis

■Voltage Mode Control with Feed-Forward

■Adjustable Dual Mode Over-Current Protection

■Programmable Overlap or Deadtime between the Main

and Active Clamp Outputs

■Volt x Second Clamp

■Programmable Soft-start

■Leading Edge Blanking

■Single Resistor Programmable Oscillator

■Oscillator UP / DOWN Sync Capability

■Precision 5V Reference

■Thermal Shutdown

Packages

■TSSOP-16

Typical Application Circuit

30058901

Simplified Active Clamp Forward Power Converter

LM5025C Active Clamp Voltage Mode PWM Controller

Connection Diagram

30058916

16-Lead TSSOP

Ordering Information

Order Number Package Type NSC Package Drawing Supplied As

LM5025CMTC TSSOP-16 MTC-16 92 Units per anti-static tube

LM5025CMTCX TSSOP-16 MTC-16 2500 Units on Tape and Reel

LM5025CCMTE TSSOP-16 MTC-16 250 Units on Tape and Reel

Pin Descriptions

Pin Name Description Application Information

1 VIN Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with

transient capability to 105V.

2 RAMP Modulator ramp signal An external RC circuit from Vin sets the ramp slope.

This pin is discharged at the conclusion of every cycle

by an internal FET, initiated by either the internal clock

or the V*Sec Clamp comparator.

3 CS1 Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5V the outputs will go into Cycle-by-

Cycle current limit. CS1 is held low for 50ns after

OUT_A switches high providing leading edge blanking.

4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a

softstart commenced. The soft-start capacitor will be

fully discharged and then released with a pull-up

current of 1µA. After the first output pulse (when SS

=1V), the SS charge current will revert back to 90 µA.

5 TIME Output overlap/Deadtime control An external resistor (RSET) sets either the overlap time

or dead time for the active clamp output. An RSET

resistor connected between TIME and GND produces

in-phase OUT_A and OUT_B pulses with overlap. An

RSET resistor connected between TIME and REF

produces out-of-phase OUT_A and OUT_B pulses with

deadtime.

6 REF Precision 5 volt reference output Maximum output current: 10 mA Locally decouple with

a 0.1 µF capacitor. Reference stays low until the VCC

UV comparator is satisfied.

7 VCC Output from the internal high voltage start-up

regulator. The VCC voltage is regulated to 7.6V.

If an auxiliary winding raises the voltage on this pin

above the regulation setpoint, the internal start-up

regulator will shutdown, reducing the IC power

dissipation.

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LM5025C

Pin Name Description Application Information

8 OUT_A Main output driver Output of the main switch PWM output gate driver.

Output capability of 3A peak sink current.

9 OUT_B Active Clamp output driver Output of the Active Clamp switch gate driver. Capable

of 1.25A peak sink current..

10 PGND Power ground Connect directly to analog ground.

11 AGND Analog ground Connect directly to power ground.

12 SS Soft-start control An external capacitor and an internal 90 µA current

source set the softstart ramp. The SS current source is

reduced to 1 µA initially following a CS2 over-current

event or an over temperature event.

13 COMP Input to the Pulse Width Modulator An internal 5 kΩ resistor pull-up is provided on this pin.

The external opto-coupler sinks current from COMP to

control the PWM duty cycle.

14 RT Oscillator timing resistor pin An external resistor connected from RT to ground sets

the internal oscillator frequency.

15 SYNC Oscillator UP/DOWN synchronization input The internal oscillator can be synchronized to an

external clock with a frequency 20% lower than the

internal oscillator’s free running frequency. There is no

constraint on the maximum sync frequency.

16 UVLO Line Under-Voltage shutdown An external voltage divider from the power source sets

the shutdown comparator levels. The comparator

threshold is 2.5V. Hysteresis is set by an internal

current source (20 µA) that is switched on or off as the

UVLO pin potential crosses the 2.5V threshold.

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LM5025C

Block Diagram

Simplified Block Diagram

30058902

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LM5025C

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VIN to GND -0.3V to 105V

VCC to GND -0.3V to 16V

CS1, CS2 to GND -0.3 to 1.00V

All other inputs to GND -0.3 to 7V

ESD Rating (Note 2)

Human Body Model 2kV

Storage Temperature Range -55°C to 150°C

Junction Temperature 150°C

Operating Ratings (Note 1)

VIN Voltage 13 to 90V

External Voltage Applied to VCC 8 to 15V

Operating Junction Temperature -40°C to +125°C

Electrical Characteristics

Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Tem-

perature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.4 kΩ) unless otherwise stated (Note 3)

Symbol Parameter Conditions Min Typ Max Units

Startup Regulator

VCC Reg VCC Regulation No Load 7.3 7.6 7.9 V

VCC Current Limit (Note 4) 40 55 mA

I-VIN Startup Regulator

Leakage (external Vcc

Supply)

VIN = 100V 165 500 µA

VCC Supply

VCC Under-voltage

Lockout Voltage (positive

going Vcc)

VCC Reg -

220mV

VCC Reg -

120mV

VCC Under-voltage

Hysteresis

1.0 1.5 2.0 V

VCC Supply Current (ICC) Cgate = 0 4.2 mA

Reference Supply

VREF Ref Voltage IREF = 0 mA 4.85 55.15 V

Ref Voltage Regulation IREF = 0 to 10 mA 25 50 mV

Ref Current Limit 10 20 mA

Current Limit

CS1 Prop CS1 Delay to Output CS1 Step from 0 to 0.6V

Time to onset of OUT

Transition (90%)

Cgate = 0

40 ns

CS2 Prop CS2 Delay to Output CS2 Step from 0 to 0.6V

Time to onset of OUT

Transition (90%)

Cgate = 0

50 ns

Cycle by Cycle Threshold

Voltage (CS1)

0.45 0.5 0.55 V

Cycle Skip Threshold

Voltage (CS2)

Resets SS capacitor; auto

restart

0.45 0.5 0.55 V

Leading Edge Blanking

Time (CS1)

50 ns

CS1 Sink Impedance

(clocked)

CS1 = 0.4V 30 50 Ω

CS1 Sink Impedance

(Post Fault Discharge)

CS1 = 0.6V 15 30 Ω

CS2 Sink Impedance

(Post Fault Discharge)

CS2 = 0.6V 55 85 Ω

CS1 and CS2 Leakage

Current

CS = CS Threshold - 100mV 1µA

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LM5025C

Symbol Parameter Conditions Min Typ Max Units

Soft-Start

Soft-start Current Source

Normal

65 90 115 µA

Soft-start Current Source

following a CS2 event

0.5 11.5 µA

Oscillator

Frequency1 TA = 25°C

TJ = Tlow to Thigh

180

175

200 220

225

kHz

Frequency2 RT = 10.8 kΩ510 580 650 kHz

Sync threshold 2 V

Min Sync Pulse Width 100 ns

Sync Frequency Range 160 kHz

PWM Comparator

Delay to Output COMP step 5V to 0V

Time to onset of OUT_A

transition low

Duty Cycle Range 0 91 %

COMP to PWM Offset 0.7 11.3 V

COMP Open Circuit

Voltage

4.3 5.9 V

COMP Short Circuit

Current

COMP = 0V 0.6 11.4 mA

Volt x Second Clamp

Ramp Clamp Level Delta RAMP measured from

onset of OUT_A to Ramp peak.

COMP = 5V

2.4 2.5 2.6 V

UVLO Shutdown

Undervoltage Shutdown

Threshold

2.44 2.5 2.56 V

Undervoltage Shutdown

Hysteresis

16 20 24 µA

Output Section

OUT_A High Saturation MOS Device @ Iout = -10mA, 5 10 Ω

OUTPUT_A Peak Current

Sink

Bipolar Device @ Vcc/2 3 A

OUT_A Low Saturation MOS Device @ Iout = 10mA, 6 9Ω

OUTPUT_A Rise Time Cgate = 2.2nF 20 ns

OUTPUT_A Fall Time Cgate = 2.2nF 15 ns

OUT_B High Saturation MOS Device @ Iout = -10mA, 10 20 Ω

OUTPUT_B Peak Current

Sink

Bipolar Device @ Vcc/2 1

OUT_B Low Saturation MOS Device @ Iout = 10mA, 12 18 Ω

OUTPUT_B Rise Time Cgate = 1nF 20 ns

OUTPUT_B Fall Time Cgate = 1nF 15 ns

Output Timing Control

Overlap Time RSET = 38 kΩ connected to

GND, 50% to 50% transitions

75 105 135 ns

Deadtime RSET = 29.5 kΩ connected to

REF, 50% to 50% transitions

75 105 135 ns

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LM5025C

Symbol Parameter Conditions Min Typ Max Units

Thermal Shutdown

TSD Thermal Shutdown

Threshold

165

°C

Thermal Shutdown

Hysteresis

°C

Thermal Resistance

θJA Junction to Ambient MTC Package 125 °C/W

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: For detailed information on soldering plastic TSSOP package, refer to the Packaging Data Book available from National Semiconductor Corporation.

Note 3: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold

limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Note 4: Device thermal limitations may limit usable range.

Typical Performance Characteristics

VCC Regulator Start-up Characteristics, VCC vs Vin

30058903

VCC vs ICC

30058904

VREF vs IREF

30058905

Oscillator Frequency vs RT

30058906

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LM5025C

Overlap Time vs RSET

30058907

Overlap Time vs Temperature

RSET = 38K

30058908

Dead Time vs RSET

30058909

Dead Time vs Temperature

RSET = 29.5K

30058910

SS Pin Current vs Temperature

30058911

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LM5025C

Detailed Operating Description

The LM5025C is a functional variant of the LM5025 active

clamp PWM controller. The functional differences of the

LM5025C are:

The maximum duty cycle of the LM5025C is increased from

80% to 91%. The soft-start capacitor charging current is in-

creased from 20 µA to 90 µA. The VCC regulator current limit

threshold is increased from 25 mA to 55 mA.

The CS1 and CS2 current limit thresholds have been in-

creased to 0.5V (same as LM5025A).

The internal CS2 filter discharge device has been disabled

and no longer operates each clock cycle (same as LM5025A).

The internal VCC and VREF regulators continue to operate

when the line UVLO pin is below threshold (same as

LM5025A).

The LM5025C PWM controller contains all of the features

necessary to implement power converters utilizing the Active

Clamp Reset technique. The device can be configured to

control either a P-Channel clamp switch or an N-Channel

clamp switch. With the active clamp technique higher effi-

ciencies and greater power densities can be realized com-

pared to conventional catch winding or RDC clamp / reset

techniques. Two control outputs are provided, the main power

switch control (OUT_A) and the active clamp switch control

(OUT_B). The active clamp output can be configured for ei-

ther a guaranteed overlap time (for P-Channel switch appli-

cations) or a guaranteed dead time (for N_Channel applica-

tions). The two internal compound gate drivers parallel both

MOS and Bipolar devices, providing superior gate drive char-

acteristics. This controller is designed for high-speed opera-

tion including an oscillator frequency range up to 1MHz and

total PWM and current sense propagation delays less than

100ns. The LM5025C includes a high-voltage start-up regu-

lator that operates over a wide input range of 13V to 90V.

Additional features include: Line Under Voltage Lockout (UV-

LO), softstart, oscillator UP/DOWN sync capability, precision

reference and thermal shutdown.

High Voltage Start-Up Regulator

The LM5025C contains an internal high voltage start-up reg-

ulator that allows the input pin (VIN) to be connected directly

to the line voltage. The regulator output is internally current

limited to 55 mA. When power is applied, the regulator is en-

abled and sources current into an external capacitor connect-

ed to the VCC pin. The recommended capacitance range for

the VCC regulator is 0.1 µF to 100 µF. When the voltage on

the VCC pin reaches the regulation point of 7.6V and the in-

ternal voltage reference (REF) reaches its regulation point of

5V, the controller outputs are enabled. The outputs will remain

enabled until VCC falls below 6.2V or the line Under Voltage

Lock Out detector indicates that VIN is out of range. In typical

applications, an auxiliary transformer winding is connected

through a diode to the VCC pin. This winding must raise the

VCC voltage above 8V to shut off the internal start-up regula-

tor. Powering VCC from an auxiliary winding improves effi-

ciency while reducing the controller power dissipation.

When the converter auxiliary winding is inactive, external cur-

rent draw on the VCC line should be limited so the power

dissipated in the start-up regulator does not exceed the max-

imum power dissipation of the controller.

An external start-up regulator or other bias rail can be used

instead of the internal start-up regulator by connecting the

VCC and the VIN pins together and feeding the external bias

voltage into the two pins.

Line Under-Voltage Detector

The LM5025C contains a line Under Voltage Lock Out (UV-

LO) circuit. An external set-point voltage divider from Vin to

GND, sets the operational range of the converter. The divider

must be designed such that the voltage at the UVLO pin will

be greater than 2.5V when Vin is in the desired operating

range. If the undervoltage threshold is not met, both outputs

are disabled,all other functions of the controller remain active.

UVLO hysteresis is accomplished with an internal 20 uA cur-

rent source that is switched on or off into the impedance of

the set-point divider. When the UVLO threshold is exceeded,

the current source is activated to instantly raise the voltage at

the UVLO pin. When the UVLO pin voltage falls below the

2.5V threshold, the current source is turned off causing the

voltage at the UVLO pin to fall. The UVLO pin can also be

used to implement a remote enable / disable function. Pulling

the UVLO pin below the 2.5V threshold disables the PWM

outputs.

PWM Outputs

The relative phase of the main (OUT_A) and active clamp

outputs (OUT_B) can be configured for the specific applica-

tion. For active clamp configurations utilizing a ground refer-

enced P-Channel clamp switch, the two outputs should be in

phase with the active clamp output overlapping the main out-

put. For active clamp configurations utilizing a high side N-

Channel switch, the active clamp output should be out of

phase with main output and there should be a dead time be-

tween the two gate drive pulses. A distinguishing feature of

the LM5025C is the ability to accurately configure either dead

time (both off) or overlap time (both on) of the gate driver out-

puts. The overlap / deadtime magnitude is controlled by the

resistor value connected to the TIME pin of the controller. The

opposite end of the resistor can be connected to either REF

for deadtime control or GND for overlap control. The internal

configuration detector senses the connection and configures

the phase relationship of the main and active clamp outputs.

The magnitude of the overlap/dead time can be calculated as

follows:

Overlap Time (ns) = 2.8 x RSET - 1.2

Dead Time (ns) = 2.9 x RSET +20

RSET in kΩ, Time in ns

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LM5025C

30058912

FIGURE 1.

Compound Gate Drivers

The LM5025C contains two unique compound gate drivers,

which parallel both MOS and Bipolar devices to provide high

drive current throughout the entire switching event. The Bipo-

lar device provides most of the drive current capability and

provides a relatively constant sink current which is ideal for

driving large power MOSFETs. As the switching event nears

conclusion and the Bipolar device saturates, the internal MOS

device continues to provide a low impedance to compete the

switching event.

During turn-off at the Miller plateau region, typically around

2V - 3V, is where gate driver current capability is needed

most. The resistive characteristics of all MOS gate drivers are

adequate for turn-on since the supply to output voltage dif-

ferential is fairly large at the Miller region. During turn-off

however, the voltage differential is small and the current

source characteristic of the Bipolar gate driver is beneficial to

provide fast drive capability.

30058913

PWM Comparator

The PWM comparator compares the ramp signal (RAMP) to

the loop error signal (COMP). This comparator is optimized

for speed in order to achieve minimum controllable duty cy-

cles. The internal 5kΩ pull-up resistor, connected between

the internal 5V reference and COMP, can be used as the pull-

up for an optocoupler. The comparator polarity is such that

0V on the COMP pin will produce a zero duty cycle on both

gate driver outputs.

Volt Second Clamp

The Volt x Second Clamp comparator compares the ramp

signal (RAMP) to a fixed 2.5V reference. By proper selection

of RFF and CFF, the maximum ON time of the main switch

can be set to the desired duration. The ON time set by Volt x

Second Clamp varies inversely with the line voltage because

the RAMP capacitor is charged by a resistor connected to Vin

while the threshold of the clamp is a fixed voltage (2.5V). An

example will illustrate the use of the Volt x Second Clamp

comparator to achieve a 50% duty cycle limit, at 200 kHz, at

a 48V line input: A 50% duty cycle at a 200 kHz requires a 2.5

µs of ON time. At 48V input the Volt x Second product is 120V

x µs (48V x 2.5µs). To achieve this clamp level:

RFF x CFF = VIN x TON / 2.5V

48 x 2.5µ / 2.5 = 48µ

Select CFF = 470 pF

RFF = 102kΩ

The recommended capacitor value range for CFF is 100 pF

to 1000 pF.

The CFF ramp capacitor is discharged at the conclusion of

every cycle by an internal discharge switch controlled by ei-

ther the internal clock or by the V x S Clamp comparator,

whichever event occurs first.

Current Limit

The LM5025C contains two modes of over-current protection.

If the sense voltage at the CS1 input exceeds 0.5V the present

power cycle is terminated (cycle-by-cycle current limit). If the

sense voltage at the CS2 input exceeds 0.5V, the controller

will terminate the present cycle, discharge the softstart ca-

pacitor and reduce the softstart current source to 1 µA. The

softstart (SS) capacitor is released after being fully dis-

charged and slowly charges with a 1 µA current source. When

the voltage at the SS pin reaches approximately 1V, the PWM

comparator will produce the first output pulse at OUT_A. After

the first pulse occurs, the softstart current source will revert

to the normal 90 µA level. Fully discharging and then slowly

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LM5025C

charging the SS capacitor protects a continuously over-load-

ed converter with a low duty cycle hiccup mode.

These two modes of over-current protection allow the user

great flexibility to configure the system behavior in over-load

conditions. If it is desired for the system to act as a current

source during an over-load, then the CS1 cycle-by-cycle cur-

rent limiting should be used. In this case the current sense

signal should be applied to the CS1 input and the CS2 input

should be grounded. If during an overload condition it is de-

sired for the system to briefly shutdown, followed by softstart

retry, then the CS2 hiccup current limiting mode should be

used. In this case the current sense signal should be applied

to the CS2 input and the CS1 input should be grounded. This

shutdown / soft-start retry will repeat indefinitely while the

over-load condition remains. The hiccup mode will greatly re-

duce the thermal stresses to the system during heavy over-

loads. The cycle-by-cycle mode will have higher system

thermal dissipations during heavy overloads, but provides the

advantage of continuous operation for short duration overload

conditions.

It is possible to utilize both over-current modes concurrently,

whereby slight overload conditions activate the CS1 cycle-by-

cycle mode while more severe overloading activates the CS2

hiccup mode. Generally the CS1 input will always be config-

ured to monitor the main switch FET current each cycle. The

CS2 input can be configured in several different ways de-

pending upon the system requirements.

a) The CS2 input can also be set to monitor the main switch

FET current except scaled to a higher threshold than CS1.

b) An external over-current timer can be configured which

trips after a pre-determined over-current time, driving the CS2

input high, initiating a hiccup event.

c) In a closed loop voltage regulaton system, the COMP input

will rise to saturation when the cycle-by-cycle current limit is

active. An external filter/delay timer and voltage divider can

be configured between the COMP pin and the CS2 pin to

scale and delay the COMP voltage. If the CS2 pin voltage

reaches 0.5V a hiccup event will initiate.

A small RC filter, located near the controller, is recommended

for each of the CS pins. The CS1 input has an internal FET

which discharges the current sense filter capacitor at the con-

clusion of every cycle, to improve dynamic performance. This

same FET remains on an additional 50ns at the start of each

main switch cycle to attenuate the leading edge spike in the

current sense signal. The CS2 discharge FET only operates

following a CS2 event, UVLO and thermal shutdown.

The LM5025C CS comparators are very fast and may re-

spond to short duration noise pulses. Layout considerations

are critical for the current sense filter and sense resistor. The

capacitor associated with the CS filter must be placed very

close to the device and connected directly to the pins of the

IC (CS and GND). If a current sense transformer is used, both

leads of the transformer secondary should be routed to the

filter network , which should be located close to the IC. If a

sense resistor in the source of the main switch MOSFET is

used for current sensing, a low inductance type of resistor is

required. When designing with a current sense resistor, all of

the noise sensitive low power ground connections should be

connected together near the IC GND and a single connection

should be made to the power ground (sense resistor ground

point).

Oscillator and Sync Capability

The LM5025C oscillator is set by a single external resistor

connected between the RT pin and GND. To set a desired

oscillator frequency (F), the necessary RT resistor can be

calculated from:

RT = (6002/F)1.0192

where F is in kHz and RT in kΩ.

The RT resistor should be located very close to the device

and connected directly to the pins of the IC (RT and GND).

A unique feature of LM5025C is the ability to synchronize the

oscillator to an external clock with a frequency that is either

higher or lower than the frequency of the internal oscillator.

The lower frequency sync frequency range is 91% of the free

running internal oscillator frequency. There is no constraint

on the maximum SYNC frequency. A minimum pulse width of

100 ns is required for the synchronization clock . If the syn-

chronization feature is not required, the SYNC pin should be

connected to GND to prevent any abnormal interference . The

internal oscillator can be completely disabled by connecting

the RT pin to REF. Once disabled, the sync signal will act

directly as the master clock for the controller. Both the fre-

quency and the maximum duty cycle of the PWM controller

can be controlled by the SYNC signal (within the limitations

of the Volt x Second Clamp). The maximum duty cycle (D) will

be (1-D) of the SYNC signal.

30058914

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LM5025C

Feed-Forward Ramp

An external resistor (RFF) and capacitor (CFF) connected to

VIN and GND are required to create the PWM ramp signal.

The slope of the signal at the RAMP pin will vary in proportion

to the input line voltage. This varying slope provides line feed-

forward information necessary to improve line transient re-

sponse with voltage mode control. The RAMP signal is

compared to the error signal at the COMP pin by the pulse

width modulator comparator to control the duty cycle of the

main switch output. The Volt Second Clamp comparator also

monitors the RAMP pin and if the ramp amplitude exceeds

2.5V the present cycle is terminated. The ramp signal is reset

to GND at the end of each cycle by either the internal clock

or the Volt Second comparator, which ever occurs first.

Soft-Start

The softstart feature allows the power converter to gradually

reach the initial steady state operating point, thus reducing

start-up stresses and surges. At power on, a 90 µA current is

sourced out of the softstart pin (SS) into an external capacitor.

The capacitor voltage will ramp up slowly and will limit the

COMP pin voltage and therefore the PWM duty cycle. In the

event of a fault as determined by VCC undervoltage, line un-

dervoltage (UVLO) or second level current limit, the output

gate drivers are disabled and the softstart capacitor is fully

discharged. When the fault condition is no longer present a

softstart sequence will be initiated. Following a second level

current limit detection (CS2), the softstart current source is

reduced to 1 µA until the first output pulse is generated by the

PWM comparator. The current source returns to the nominal

90 µA level after the first output pulse (~1V at the SS pin).

Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the

integrated circuit in the event the maximum junction temper-

ature is exceeded. When activated, typically at 165°C, the

controller is forced into a low power standby state with the

output drivers and the bias regulator disabled. The device will

restart after the thermal hysteresis (typically 25°C). During a

restart after thermal shutdown, the softstart capacitor will be

fully discharged and then charged in the low current mode (1

µA) similar to a second level current limit event. The thermal

protection feature is provided to prevent catastrophic failures

from accidental device overheating.

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LM5025C

Application Circuit: Input 36-78V, Output 3.3V, 30A

30058917

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LM5025C

Physical Dimensions inches (millimeters) unless otherwise noted

Molded TSSOP-16

NS Package Number MTC16

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LM5025C

Notes

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LM5025C

Notes

LM5025C Active Clamp Voltage Mode PWM Controller

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