Vishay Siliconix
Si4920DY
Document Number: 70667
S09-0767-Rev. E, 04-May-09
www.vishay.com
1
Dual N-Channel 30-V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFETs
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A)
30 0.025 at VGS = 10 V ± 6.9
0.035 at VGS = 4.5 V ± 5.8
S1D1
G1D1
S2D2
G2D2
SO-8
5
6
7
8
Top View
2
3
4
1
Ordering Information: Si4920DY-T1-E3 (Lead (Pb)-free)
Si4920DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
D
1
G
1
S
1
N-Channel MOSFET
D
2
G
2
S
2
N-Channel MOSFET
Notes:
a. Surface Mounted on FR4 board, t ≤ 10 s.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)aTA = 25 °C ID
± 6.9
A
TA = 70 °C ± 5.5
Pulsed Drain Current (10 µs Pulse Width) IDM ± 40
Continuous Source Current (Diode Conduction)aIS1.7
Maximum Power DissipationaTA = 25 °C PD
2W
TA = 70 °C 1.3
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Limit Unit
Maximum Junction-to-AmbientaRthJA 62.5 °C/W
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Document Number: 70667
S09-0767-Rev. E, 04-May-09
Vishay Siliconix
Si4920DY
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functiona l operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V 1µA
VDS = 30 V, VGS = 0 V, TJ = 55 °C 25
On-State Drain CurrentaID(on) VDS ≥ 5 V, VGS = 10 V 20 A
Drain-Source On-State ResistanceaRDS(on)
VGS = 10 V, ID = 6.9 A 0.020 0.025 Ω
VGS = 4.5 V, ID = 5.8 A 0.026 0.035
Forward Transconductanceagfs VDS = 15 V, ID = 6.9 A 25 S
Diode Forward VoltageaVSD IS = 1.7 A, VGS = 0 V 1.2 V
Dynamicb
Gate Charge Qg V
DS = 15 V, VGS = 5 V, ID = 6.9 A 15 23
nC
Total Gate Charge Qgt
VDS = 15 V, VGS = 10 V, ID = 6.9 A
30 50
Gate-Source Charge Qgs 7.5
Gate-Drain Charge Qgd 3.5
Gate Resistance Rg f = 1 MHz 2 3 Ω
Tur n - O n D e l ay Time td(on)
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
12 20
ns
Rise Time tr10 20
Turn-Off Delay Time td(off) 60 90
Fall Time tf15 30
Source-Drain Reverse Recovery Time trr IF = 1.7 A, dI/dt = 100 A/µs 50 90
Document Number: 70667
S09-0767-Rev. E, 04-May-09
www.vishay.com
3
Vishay Siliconix
Si4920DY
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current
Gate Charge
0
8
16
24
32
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)ID
VGS = 10 V thru 5 V
3 V
4 V
0
0.01
0.02
0.03
0.04
0.05
0 10203040
RDS(on)
ID - Drain Current (A)
VGS = 10 V
VGS = 4.5 V
- On-Resistance (Ω)
0
2
4
6
8
10
0 5 10 15 20 25 30
- Gate-to-Source Voltage (V)
Qg
- Total Gate Charge (nC)
VGS
VDS = 15 V
ID = 6.9 A
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
10
20
30
40
012345
VGS - Gate-to-Source Voltage (V)
- Drain Current (A)ID
TC = 125 °C
- 55 °C
25 °C
0
500
1000
1500
2000
2500
3000
0 5 10 15 20 25 30
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
Crss
Coss
Ciss
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 6.9 A
TJ - Junction T emperature (°C)
(Normalized)
- On-ResistanceRDS(on)
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Document Number: 70667
S09-0767-Rev. E, 04-May-09
Vishay Siliconix
Si4920DY
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see ww w.vishay.com/ppg?70667.
Source-Drain Diode Forward Voltage
Threshold Voltage
1
10
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD - Source-to-Drain Voltage (V)
- Source Current (A)IS
30
20
40
TJ = 150 °C
TJ = 25 °C
- 1.0
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
Variance (V)VGS(th)
ID = 250 µA
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power
0
0.02
0.04
0.06
0.08
0.10
0246810
RDS(on)
VGS - Gate-to-Source Voltage (V)
ID = 6.9 A
- On-Resistance (Ω)
0
5
10
15
20
25
30
0.01 0.10 1.00 10.00
Power (W)
Time (s)
TC = 25 °C
Single Pulse
Normalized Thermal Transient Impedance, Junction-to-Ambient
Square Wave Pulse Duration (s)
2
1
0.1
0.01
10-4 10-3 10-2 10-1 1
Normalized Effective Transient
Thermal Impedance
30
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
10
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 62.5 °C/W
3. T JM - T A = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
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Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
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