MCP622T-E/MF - Microchip Technology, Inc.

MCP621/1S/2/3/4/5/9

Features

• Gain Bandwidth Product: 20 MHz (typical)

• Short Circuit Current: 70 mA (typical)

• Noise: 13 nV/√Hz (typical, at 1 MHz)

• Calibrated Input Offset: ±200 µV (maximum)

• Rail-to-Rail Output

• Slew Rate: 10 V/µs (typical)

• Supply Current: 2.5 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids

• SPICE Macro Models

•FilterLab

® Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description

The Microchip Technology, Inc. MCP621/1S/2/3/4/5/9

family of operational amplifiers features low offset. At

power-up, these op amps are self-calibrated using

mCal. Some package options also provide a Calibra-

tion/Chip Select pin (CAL/CS) that supports a Low-

Power mode of operation, with offset calibration at the

time normal operation is re-started. These amplifiers

are optimized for high speed, low noise and distortion,

single-supply operation with rail-to-rail output and an

input that includes the negative rail.

This family is offered in single (MCP621 and

MCP621S), single with CAL/CS pin (MCP623), dual

(MCP622), dual with CAL/CS pins (MCP625), quad

(MCP624) and quad with CAL/CS pins (MCP629). All

devices are fully specified from -40°C to +125°C.

Typical Application Circuit

PowerDriverwithHighGain

R1R2

VIN

VDD/2 VOUT

R3RL

MCP62X

20 MHz, 2.5 mA Op Amps with mCal

MCP621/1S/2/3/4/5/9

Package Types

MCP621

SOIC

MCP622

SOIC

VIN+

VIN–

VSS

VDD

VOUT

5VCAL

CAL/CSNC

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

MCP625

MSOP

VINA+

VINA–

VSS

VOUTA VDD

VOUTB

VINB–

VINB+

CALA/CSA5 6 CALB/CSB

MCP622

3x3 DFN *

MCP625

3x3 DFN *

* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1 .

VINA+

VINA–

VSS

VOUTB

VINB–

5VINB+

VDD

VOUTA

VSS

VINA+

CALA/CSA

VINB–

VINB+

6CALB/CSB

VOUTB

VINA–

110 VDD

VOUTA

MCP629

4x4 QFN*

VDD

VINB+

VINA-V

IND+

VSS

VINB-

VINC+

VOUTB

CALBC/CSBC

VOUTC

VINC-

VOUTA

CALAD/CSAD

VOUTD

VIND-

VINA+EP

15 14 13

5678

MCP624

SOIC, TSSOP

VINA+

VINA-

VDD

VOUTA VOUTD

VIND-

VIND+

VSS

VINB+510 VINC+

VINB-69

VOUTB 7 8 VOUTC

VINC-

MCP621

2x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

5VCAL

CAL/CSNC

CAL/CS

VIN+

VOUT

VSS

VIN-

MCP623

SOT-23-6

VDD

VIN+

VOUT

VSS

VIN-

MCP621S

SOT-23-5

VDD

MCP621/1S/2/3/4/5/9

1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD –V

SS .......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD +1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V

Output Short Circuit Current ................................ Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................+150°C

ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V

†Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at those or any other

conditions above those indicated in the operational

listings of this specification is not implied. Exposure to

maximum rating conditions for extended periods may

affect device reliability.

†† See Section 4.2.2, Input Voltage and Current

Limits.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/3, VOUT ≈VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CAL/CS =V

SS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage VOS -200 — +200 µV After calibration (Note 1)

Input Offset Voltage Trim Step

Size

VOSTRM —37200µV(Note 2)

Input Offset Voltage Drift ΔVOS/ΔTA—±2.0—µV/°CT

A= -40°C to +125°C

Power Supply Rejection Ratio PSRR 61 76 — dB

Input Current and Impedance

Input Bias Current IB—5—pA

Across Temperature IB—100—pAT

A= +85°C

Across Temperature IB— 1700 5,000 pA TA= +125°C

Input Offset Current IOS —±10—pA

Common Mode Input

Impedance

ZCM —10

13||9 — Ω||pF

Differential Input Impedance ZDIFF —10

13||2 — Ω||pF

Common Mode

Common Mode Input Voltage

Range

VCMR VSS −0.3 — VDD −1.3 V (Note 3)

Common Mode Rejection Ratio CMRR 65 81 — dB VDD = 2.5V, VCM = -0.3 to

1.2V

CMRR 68 84 — dB VDD = 5.5V, VCM = -0.3 to

4.2V

Open-Loop Gain

DC Open-Loop Gain

(large signal)

AOL 88 117 — dB VDD = 2.5V,

VOUT = 0.3V to 2.2V

AOL 94 126 — dB VDD = 5.5V,

VOUT = 0.3V to 5.2V

Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is

toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.

3: See Figure 2-6 and Figure 2-7 for temperature effects.

4: The ISC specifications are for design guidance only; they are not tested.

MCP621/1S/2/3/4/5/9

Output

Maximum Output Voltage Swing VOL, VOH VSS +20 — V

DD −20 mV VDD = 2.5V, G = +2,

0.5V Input Overdrive

VOL, VOH VSS +40 — V

DD −40 mV VDD = 5.5V, G = +2,

0.5V Input Overdrive

Output Short Circuit Current ISC ±40 ±85 ±130 mA VDD = 2.5V (Note 4)

ISC ±35 ±70 ±110 mA VDD = 5.5V (Note 4)

Calibration Input

Calibration Input Voltage Range VCALRNG VSS +0.1 — V

DD –1.4 mV V

CAL pin externally driven

Internal Calibration Voltage VCAL 0.323VDD 0.333VDD 0.343VDD VCAL pin open

Input Impedance ZCAL —100||5—kΩ||pF

Power Supply

Supply Voltage VDD 2.5 — 5.5 V

Quiescent Current per Amplifier IQ1.2 2.5 3.6 mA IO = 0

POR Input Threshold, Low VPRL 1.15 1.40 — V

POR Input Threshold, High VPRH — 1.40 1.65 V

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/2, VOUT ≈VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL= 50 pF and CAL/CS =V

SS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 20 — MHz

Phase Margin PM — 60 — ° G = +1

Open-Loop Output Impedance ROUT —15— Ω

AC Distortion

Total Harmonic Distortion plus

Noise

THD+N — 0.0018 — % G = +1, VOUT = 2VP-P

, f = 1 kHz,

VDD = 5.5V, BW = 80 kHz

Step Response

Rise Time, 10% to 90% tr— 13 — ns G = +1, VOUT = 100 mVP-P

Slew Rate SR — 10 — V/µs G = +1

Noise

Input Noise Voltage Eni —20—µV

P-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —13—nV/√Hz f = 1 MHz

Input Noise Current Density ini 4—fA/√Hz f = 1 kHz

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/3, VOUT ≈VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CAL/CS =V

SS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is

toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.

3: See Figure 2-6 and Figure 2-7 for temperature effects.

4: The ISC specifications are for design guidance only; they are not tested.

MCP621/1S/2/3/4/5/9

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL= 50 pF and CAL/CS =V

SS (refer to Figure 1-1 and Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

CAL/CS Low Specifications

CAL/CS Logic Threshold, Low VIL VSS —0.2V

DD V

CAL/CS Input Current, Low ICSL —0—nACAL/CS = 0V

CAL/CS High Specifications

CAL/CS Logic Threshold, High VIH 0.8VDD VDD V

CAL/CS Input Current, High ICSH — 0.7 — µA CAL/CS = VDD

GND Current ISS -3.5 -1.8 — µA Single, CAL/CS = VDD = 2.5V

ISS -8 -4 — µA Single, CAL/CS = VDD = 5.5V

ISS -5 -2.5 — µA Dual, CAL/CS = VDD = 2.5V

ISS -10 -5 — µA Dual, CAL/CS = VDD = 5.5V

CAL/CS Internal Pull-Down

Resistor

RPD —5—MΩ

Amplifier Output Leakage IO(LEAK) — 50 — nA CAL/CS = VDD, TA = 125°C

POR Dynamic Specifications

VDD Low to Amplifier Off Time

(output goes High-Z)

tPOFF — 200 — ns G = +1 V/V, VL = VSS,

VDD = 2.5V to 0V step to VOUT =0.1

(2.5V)

VDD High to Amplifier On Time

(including calibration)

tPON 100 200 300 ms G = +1 V/V, VL = VSS,

VDD = 0V to 2.5V step to VOUT =0.9

(2.5V)

CAL/CS Dynamic Specifications

CAL/CS Input Hysteresis VHYST —0.25 —V

CAL/CS Setup Time

(between CAL/CS edges)

tCSU 1——µsG = +1V/V, V

L = VSS (Notes 2,3,4)

CAL/CS = 0.8VDD to VOUT = 0.1

(VDD/2)

CAL/CS High to Amplifier Off Time

(output goes High-Z)

tCOFF — 200 — ns G = +1 V/V, VL = VSS,

CAL/CS = 0.8VDD to VOUT = 0.1

(VDD/2)

CAL/CS Low to Amplifier On Time

(including calibration)

tCON —3 4ms

G = +1 V/V, VL = VSS, MCP621 and

MCP625, CAL/CS = 0.2VDD to

VOUT =0.9(V

DD/2)

tCON —6 8ms

G = +1 V/V, VL = VSS, MCP629,

CAL/CS = 0.2VDD to

VOUT =0.9(V

DD/2)

Note 1: The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V).

2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised

before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.

3: For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously

(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are

toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in

Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.

4: For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously

(within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the

maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD

(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow

more than the maximum tCON time (8 ms) before the other side is toggled.

MCP621/1S/2/3/4/5/9

1.3 Timing Diagram

FIGURE 1-1: Timing Diagram.

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V,VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C (Note 1)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W

Thermal Resistance, 8L-2x3 TDFN θJA —52.5—°C/W

Thermal Resistance, 8L-3x3 DFN θJA —56.7—°C/W(Note 2)

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 10L-3x3 DFN θJA —53.3—°C/W(Note 2)

Thermal Resistance, 10L-MSOP θJA —202—°C/W

Thermal Resistance, 14L-SOIC θJA —95.3—°C/W

Thermal Resistance, 14L-TSSOP θJA —100—°C/W

Thermal Resistance, 16L-4x4-QFN θJA —45.7—°C/W(Note 2)

Note 1: Operation must not cause TJ to exceed the Maximum Junction Temperature specification (150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

High-Z

VDD

VOUT

-3 µA (typical)

High-Z

ISS

ICS

-3 µA (typical)

-2.5 mA (typical)

VPRH VPRL

tPON tPOFF

0nA(typical)

High-Z

-3 µA (typical) -2.5 mA (typical)

tCOFF tCON

0.7 µA (typical) 0nA(typical)

CAL/CS VIH VIL

tCSU

Note: For the MCP625 dual and the MCP629 quad, there is an additional constraint on toggling the two

CAL/CS pins close together; see the TCON specification in Tabl e 1 - 3.

MCP621/1S/2/3/4/5/9

1.4 Test Circuits

The circuit used for most DC and AC tests is shown in

Figure 1-2. This circuit can independently set VCM and

VOUT

; see Equation 1-1. Note that VCM is not the

circuit’s Common mode voltage ((VP+V

M)/2), and that

VOST includes VOS plus the effects (on the input offset

error, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

FIGURE 1-2: AC and DC Test Circuit for

Most Spe cific ations.

GDM RFRG

⁄

VCM VPVDD 2

⁄

+()2

⁄

VOUT VDD 2

⁄

()VPVM

–()VOST 1G

+()++=

Where:

GDM = Differential Mode Gain (V/V)

VCM = Op Amp’s Common Mode

Input Voltage

(V)

VOST = Op Amp’s Total Input Offset

Voltage

(mV)

VOST VIN– VIN+

–=

VDD

RGRF

VOUT

CB2

CB1

10 kΩ

RGRF

VDD/2

10 kΩ

50 pF

2kΩ

2.2 µF100 nF

VIN–

VIN+

6.8 pF

MCP62X

MCP621/1S/2/3/4/5/9

NOTES:

MCP621/1S/2/3/4/5/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.1 DC Signal Inputs

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage

Repeatability (repeated calibration).

FIGURE 2-4: Input Offset Voltage vs.

Power Supply Voltage.

FIGURE 2-5: Input Offset Voltage vs.

Output Voltage.

FIGURE 2-6: Low Input Common Mode

Voltage Headroom vs. Ambient Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

16%

18%

20%

22%

-80-60-40-20 0 20406080

Input Offset Voltage (µV)

Percentage of Occurrences

80 Samples

TA = +25°C

VDD = 2.5V and 5.5V

Calibrated at +25°C

10%

12%

14%

16%

18%

20%

22%

24%

-10-8-6-4-20246810

Input Offset Voltage Drift (µV/°C)

Percentage of Occurrences

80 Samples

VDD = 2.5V and 5.5V

TA = -40°C to +125°C

Calibrated at +25°C

10%

15%

20%

25%

30%

35%

40%

45%

50%

-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60

Input Offset Voltage Calibration Repeatability

(µV)

Percentage of Occurrences

200 Samples

TA = +25°C

VDD = 2.5V and 5.5V

Calibration

Changed

(-1 step)

No Change

(includes noise)

Calibration

Changed

(+1 step)

-700

-600

-500

-400

-300

-200

-100

100

200

300

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Input Offset Voltage (µV)

+125°C

+85°C

+25°C

-40°C

Representative Part

Calibrated at VDD = 6.5V

-50

-40

-30

-20

-10

0.00.51.01.52.02.53.03.54.04.55.05.5

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 2.5V

VDD = 5.5V

Representative Part

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Low Input Common

Mode Headroom (V)

VDD = 2.5V

1 Lot

Low (VCMR_L – VSS)

VDD = 5.5V

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-7: Hig h Input Comm on Mod e

Voltage Headroom vs. Ambient Temperature.

FIGURE 2-8: Input Offset Voltage vs.

Common Mode Voltage with VDD =2.5V.

FIGURE 2-9: Input Offset Voltage vs.

Common Mode Voltage with VDD =5.5V.

FIGURE 2-10: CMRR and PSRR vs.

Ambient Temp eratu re .

FIGURE 2-11: DC Open-Loop Gain vs.

Ambient Temp eratu re .

FIGURE 2-12: Input Bias and Offset

Currents vs. Ambient Temperature with

VDD =+5.5V.

1.0

1.1

1.2

1.3

1.4

-50-25 0 255075100125

Ambient Temperature (°C)

High Input Common

Mode Headroom (V)

VDD = 2.5V

VDD = 5.5V

1 Lot

High (VDD – VCMR_H)

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 2.5V

Representative Part

+125°C

+85°C

+25°C

-40°C

-1000

-800

-600

-400

-200

200

400

600

800

1000

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Input Common Mode Voltage (V)

Input Offset Voltage (µV)

VDD = 5.5V

Representative Part

+125°C

+85°C

+25°C

-40°C

100

105

110

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CMRR, PSRR (dB)

PSRR

CMRR, VDD = 5.5V

CMRR, VDD = 2.5V

100

105

110

115

120

125

130

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 2.5V

100

1,000

10,000

25 45 65 85 105 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

VDD = 5.5V

VCM = VCMR_H

| IOS |

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-13: Input Bias and Offset

Currents vs. Common Mode Input Voltage with

TA= +85°C.

FIGURE 2-14: Input Bias and Offset

Currents vs. Common Mode Input Voltage with

TA= +125°C.

FIGURE 2-15: Input Bias Current vs. Input

Voltage (below VSS).

-60

-40

-20

100

120

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

Representative Part

TA = +85°C

VDD = 5.5V

IOS

-1000

-500

500

1000

1500

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

Representative Part

TA = +125°C

VDD = 5.5V

IOS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C

+25°C

-40°C

100µ

10µ

1µ

100n

10n

100p

10p

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.2 Other DC Voltages and Currents

FIGURE 2-16: Ratio of Output Voltage

Headroom to Output Current.

FIGURE 2-17: Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-18: Output Short Circuit Current

vs. Power Supply Voltage.

FIGURE 2-19: Supply Current vs. Power

Supply Voltage.

FIGURE 2-20: Supply Current vs. Common

Mode Input Voltage.

FIGURE 2-21: Power-On Reset Voltages

vs. Ambient Temperature.

110100

Output Current Magnitude (mA)

Ratio of Output Headroom to

Output Current (mV/mA)

VDD = 2.5V

VDD = 5.5V

VDD – VOH

IOUT

VOL – VSS

-IOUT

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Output Headroom (mV)

VDD = 5.5V

VOL – VSS

VDD = 2.5V VDD – VOH

RL = 2 kΩ

-100

-80

-60

-40

-20

100

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Output Short Circuit Current

(mA)

+125°C

+85°C

+25°C

-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Supply Current

(mA/amplifier)

+125°C

+85°C

+25°C

-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

Supply Current

(mA/amplifier)

VDD = 2.5V

VDD = 5.5V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

POR Trip Voltages (V)

VPRL

VPRH

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-22: Normalized Internal

Calibration Voltage. FIGURE 2-23: VCAL Input Resis tance vs.

Temperature.

10%

15%

20%

25%

30%

33.20%

33.24%

33.28%

33.32%

33.36%

33.40%

33.44%

33.48%

33.52%

Normalized Internal Calibration Voltage;

VCAL/VDD

Percentage of Occurrences

144 Samples

VDD = 2.5V and 5.5V

100

120

140

-50-25 0 255075100125

Ambient Temperature (°C)

Internal V CAL Resistance (kΩ)

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.3 Frequency Response

FIGURE 2-24: CMRR and PSRR vs.

Frequency.

FIGURE 2-25: Open-Loop Gain vs.

Frequency.

FIGURE 2-26: Gain Bandwidth Product

and Phase Margin vs. Ambient Temperature.

FIGURE 2-27: Gain Bandwidth Product

and Phase Margin vs. Common Mode Input

Voltage.

FIGURE 2-28: Gain Bandwidth Product

and Phase Margin vs. Output Voltage.

FIGURE 2-29: Closed-Loop Output

Impedance vs. Frequency.

100

1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

CMRR, PSRR (dB)

CMRR

100 1M10k 10M100k1k

PSRR+

PSRR-

-20

100

120

140

1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8

Frequency (Hz)

Open-Loop Gain (dB)

-240

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

| AOL |

∠AOL

10 1k 100k 10M1 100 10k 1M 100M

-50-250 255075100125

Ambient Temperature (°C)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

0.1

100

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

1k 1M 10M 100M

Open-Loop Output Impedance (Ω)

10k 100k

G = 101 V/V

G = 11 V/V

G = 1 V/V

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-30: Gain Peaking vs.

Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel

Separation vs . Frequ enc y.

1.0E-11 1.0E-10 1.0E-09

Normalized Capacitive Load; CL/GN (F)

Gain Peaking (dB)

10p 100p 1n

GN = 1 V/

GN = 2 V/

GN ≥ 4 V/

100

110

120

130

140

150

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Channel-to-Channel

Separation (dB)

1k 10k 100k

RTI

VCM = VDD/2

G = +1 V/V

RS = 0Ω

RS = 1 kΩ

RS = 10 kΩ

RS = 100 kΩ

1M 10M

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.4 Input Noise and Distortion

FIGURE 2-32: Input Noise Volt age Density

vs. Frequency.

FIGURE 2-33: Input Noise Volt age Density

vs. Input Common Mode Voltage with f = 100 Hz.

FIGURE 2-34: Input Noise Volt age Density

vs. Input Common Mode Voltage with f = 1 MHz.

FIGURE 2-35: Input Noise plus Offset vs.

Time with 0.1 Hz Filter.

FIGURE 2-36: THD+N vs. Frequency.

1.E+1

1.E+2

1.E+3

1.E+4

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

0.1 100 10k 1M

Input Noise Voltage Density (nV/√Hz)

11k100k10M10

10n

100n

1µ

10µ

100

150

200

250

300

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

VDD = 5.5V

VDD = 2.5V

Input Noise Voltage Density

(nV/√Hz)

f = 100 Hz

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

VDD = 5.5V

VDD = 2.5V

Input Noise Voltage Density

(nV/√Hz)

f = 1 MHz

-20

-15

-10

-5

0 5 10 15 20 25 30 35 40 45

Time (min)

Input Offset + Noise;

VOS + eni(t) (µV)

Representative Part

Analog NPBW = 0.1 Hz

Sample Rate = 2 SPS

0.0001

0.001

0.01

0.1

1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

THD + Noise (%)

VDD = 5.0V

VOUT = 2 VP-P

100 1k 10k 100k

BW = 22 Hz to 80 kHz

BW = 22 Hz to > 500 kHz G = 1 V/V

G = 11 V/V

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.5 Time Response

FIGURE 2-37: Non-inverting Small Signal

Step Respon se .

FIGURE 2-38: Non-inverting Large Signal

Step Respon se .

FIGURE 2-39: Inverting Small Signal Step

Response.

FIGURE 2-40: Inverting Large Signal Step

Response.

FIGURE 2-41: The MCP621 /1S /2/3 /4/5/ 9

Family Shows No Input Phase Reversal with

Overdrive.

FIGURE 2-42: Slew Rate vs. Ambient

Temperature.

0 20 40 60 80 100 120 140 160 180 200

Time (ns)

Output Voltage (10 mV/div)

VDD = 5.5V

G = 1

VIN VOUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Time (µs)

Output Voltage (V)

VDD = 5.5V

G = 1

VIN VOUT

0 100 200 300 400 500 600 700 800

Time (ns)

Output Voltage (10 mV/div)

VDD = 5.5V

G = -1

RF = 1 kΩ

VIN

VOUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.00.20.40.60.81.01.21.41.61.82.0

Time (µs)

Output Voltage (V)

VDD = 5.5V

G = -1

RF = 1 kΩ

VIN

VOUT

-1

012345678910

Time (ms)

Input, Output Voltages (V)

VDD = 5.5V

G = 2

VOUT

VIN

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Slew Rate (V/µs)

Falling Edge

Rising

VDD = 2.5V

VDD = 5.5V

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-43: Maximum Output Voltage

Swing vs. Frequency.

0.1

1.E+05 1.E+06 1.E+07 1.E+08

Frequency (Hz)

Maximum Output Voltage

Swing (VP-P)

VDD = 5.5

VDD = 2.5

100k 1M 10M 100M

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

2.6 Calibration and Chip Select Response

FIGURE 2-44: CAL/CS Current vs. Power

Supply Voltage.

FIGURE 2-45: CAL/CS Voltage, Output

V oltage and Supply Current (for Side A) vs. Time

with VDD =2.5V.

FIGURE 2-46: CAL/CS Voltage, Output

V oltage and Supply Current (for Side A) vs. Time

with VDD =5.5V.

FIGURE 2-47: CAL/CS Hysteresis vs.

Ambient Temp eratu re .

FIGURE 2-48: CAL/CS Turn-On T ime vs.

Ambient Temp eratu re .

FIGURE 2-49: CAL/CS’s P u ll -down

Resistor (RPD) vs. Ambient Temperature.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

CAL/CS Current (µA)

CAL/CS = VDD

-1

0246810121416

Time (ms)

CAL/CS, V OUT (V)

-12

-10

-8

-6

-4

-2

Power Supply Current;

IDD (mA)

VDD = 2.5V

G = 1

VL = 0V

Op Amp

turns on

CAL/CS

Op Amp

turns off

Calibration

starts

IDD

VOUT

-2

0 2 4 6 8 10 12 14 16

Time (ms)

CAL/CS, V OUT (V)

-12

-10

-8

-6

-4

-2

Power Supply Current;

IDD (mA)

VDD = 5.5V

G = 1

VL = 0V

Op Amp

turns on

CAL/CS

Op Amp

turns off

Calibration

starts

IDD

VOUT

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CAL/CS Hysteresis (V)

VDD = 2.5V

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CAL/CS Turn On Time (ms)

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CAL/CS Pull-down Resistor

(MΩ)

Representative Part

MCP621/1S/2/3/4/5/9

Note: Unless otherwise indicated, TA=+25°C, V

DD = +2.5V to 5.5V, VSS = GND, VCM =V

DD/3, VOUT =V

DD/2,

VL=V

DD/2, RL=2kΩ to VL, CL= 50 pF, and CAL/CS =V

SS.

FIGURE 2-50: Quiescent Current in

Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs.

Output Voltage.

-7

-6

-5

-4

-3

-2

-1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Negative Power Supply

Current; I SS (µA)

CAL/CS = VDD

+125°C

+85°C

+25°C

-40°C

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

Output Leakage Current (A)

+25°C

+125°C

+85°C

CAL/CS = VDD = 5.5V

MCP621/1S/2/3/4/5/9

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP621 MCP621S MCP622 MCP623 MCP624 MCP625 MCP629 Symbol Description

SOIC TDFN SOT-23 SOIC DFN SOT-23 SOIC TSSOP MSOP DFN QFN

22 4 22 4 2 2 22 1V

IN–, VINA– Inverting Input (op amp A)

33 3 33 3 3 3 33 2V

IN+, VINA+ Non-inverting Input (op amp A)

7 7 5 8 8 6 4 4 10 10 3 VDD Positive Power Supply

—— — 55 — 5 5 7 7 4 V

INB+ Non-inverting Input (op amp B)

—— — 66 —66 885 VINB– Inverting Input (op amp B)

—— — 77 —77 996 VOUTB Output (op amp B)

—— — —— — — — —— 7CALBC/CSBC Calibrate/Chip Select Digital Input

(op amps B and C)

—— — —— — 88—— 8VOUTC Output (op amp C)

—— — —— — 99—— 9VINC– Inverting Input (op amp C)

—— — —— — 10 10 —— 10 VINC+ Non-inverting input (op amp C)

44 2 44 21111

44 11 VSS Negative Power Supply

—— — —— — 12 12 —— 12 VIND+ Non-inverting input (op amp D)

—— — —— — 13 13 —— 13 VINDD– Inverting Input (op amp D)

—— — —— — 14 14 —— 14 VOUTD Output (op amp D)

—— — —— — — — —— 15 CALAD/CSAD Calibrate/Chip Select Digital Input

(op amps A and D)

66 1 11 1 1 1 1116 VOUT

, VOUTA Output (op amp A)

— 9 — — 9 — — — 11 17 EP Exposed Thermal Pad (EP);

must be connected to VSS

88 — ——5 —— 55— CAL/CS,

CALA/CSA

Calibrate/Chip Select Digital Input (op amp A)

—— — —— — — — 6 6 — CALB/CSBCalibrate/Chip Select Digital Input (op amp B)

55 — ——— ————— V

CAL Calibration Common Mode Voltage Input

1 1 — — — — — — — — — NC No Internal Connection

MCP621/1S/2/3/4/5/9

3.1 Analog Outputs

The analog output pins (VOUT) are low-impedance

voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs (VIN+, VIN–, …)

are high-impedance CMOS inputs with low bias

currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 2.5V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

3.4 Calibration Common Mode

Voltage Input

A low-impedance voltage placed at this input (VCAL)

will set the op amps’ Common mode input voltage

during calibration. If this pin is left open, the Common

mode input voltage during calibration is approximately

VDD/3. The internal resistor divider is disconnected

from the supplies whenever the part is not in

calibration.

3.5 Calibrate/Chip Select Digital Input

This input (CAL/CS, …) is a CMOS, Schmitt-triggered

input that affects the calibration and Low-Power modes

of operation. When this pin goes high, the part is placed

into a Low-Power mode and the output is high-Z. When

this pin goes low, a calibration sequence is started

(which corrects VOS). At the end of the calibration

sequence, the output becomes low-impedance and the

part resumes normal operation.

An internal POR triggers a calibration event when the

part is powered on, or when the supply voltage drops

too low. Thus, the MCP622 parts are calibrated, even

though they do not have a CAL/CS pin.

3.6 Exposed Thermal Pad (EP)

There is an internal connection between the Exposed

Thermal Pad (EP) and the VSS pin; they must be

connected to the same potential on the Printed Circuit

Board (PCB).

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θJA).

MCP621/1S/2/3/4/5/9

4.0 APPLICATIONS

The MCP621/1S/2/3/4/5/9 family of self-zeroed op

amps is manufactured using Microchip’s state-of-the-

art CMOS process. It is designed for low-cost, low-

power and high-precision applications. Its low supply

voltage, low quiescent current and wide bandwidth

makes the MCP621/1S/2/3/4/5/9 ideal for battery-

powered applications.

4.1 Calibration and Chip Select

These op amps include circuitry for dynamic calibration

of the offset voltage (VOS).

4.1.1 mCal CALIBRATION CIRCUITRY

The internal mCal circuitry, when activated, starts a

delay timer (to wait for the op amp to settle to its new

bias point), then calibrates the input offset voltage

(VOS). The mCal circuitry is triggered at power-up (and

after some power brown-out events) by the internal

POR, and by the memory’s Parity Detector. The

power-up time, when the mCal circuitry triggers the

calibration sequence, is 200 ms (typical).

4.1.2 CAL/CS PIN

The CAL/CS pin gives the user a means to externally

demand a Low-Power mode of operation, then to

calibrate VOS. Using the CAL/CS pin makes it possible

to correct VOS as it drifts over time (1/f noise and aging;

see Figure 2-35) and across temperature.

The CAL/CS pin performs two functions: it places the

op amp(s) in a Low-Power mode when it is held high,

and starts a calibration event (correction of VOS) after a

rising edge.

While in the Low-Power mode, the quiescent current is

quite small (ISS = -3 µA, typical). The output is also in a

High-Z state.

During the calibration event, the quiescent current is

near, but smaller than the specified quiescent current

(2.5 mA, typical). The output continues in the High-Z

state, and the inputs are disconnected from the

external circuit, to prevent internal signals from

affecting circuit operation. The op amp inputs are

internally connected to a Common mode voltage buffer

and feedback resistors. The offset is corrected (using a

digital state machine, logic and memory), and the

calibration constants are stored in memory.

Once the calibration event is completed, the amplifier is

reconnected to the external circuitry. The turn-on time,

when calibration is started with the CAL/CS pin, is 5 ms

(typical).

There is an internal 5 MΩ pull-down resistor tied to the

CAL/CS pin. If the CAL/CS pin is left floating, the

amplifier operates normally.

For the MCP625 dual and the MCP629 quad, there is

an additional constraint on toggling the two CAL/CS

pins close together; see the tCON specification in

Table 1-3. If the two pins are toggled simultaneously, or

if they are toggled separately with an adequate delay

between them (greater than tCON), then the CAL/CS

inputs are accepted as valid. If one of the two pins

toggles, while the other pin’s calibration routine is in

progress, then an invalid input occurs and the result is

unpredictable.

4.1.3 INTERNAL POR

This part includes an internal Power-on Reset (POR) to

protect the internal calibration memory cells. The POR

monitors the power supply voltage (VDD). When the

POR detects a low VDD event, it places the part into the

Low-Power mode of operation. When the POR detects

a normal VDD event, it starts a delay counter, then

triggers a calibration event. The additional delay gives

a total POR turn-on time of 200 ms (typical); this is also

the power-up time (since the POR is triggered at power

up).

4.1.4 PARITY DETECTOR

A parity error detector monitors the memory contents

for any corruption. In the rare event that a parity error is

detected (e.g., corruption from an alpha particle), a

POR event is automatically triggered. This will cause

the input offset voltage to be recorrected, and the op

amp will not return to normal operation for a period of

time (the POR turn-on time, tPON).

4.1.5 CALIBRATION INPUT PIN

A VCAL pin is available in some options (e.g., the single

MCP621) for those applications that need the

calibration to occur at an internally driven Common

mode voltage other than VDD/3.

Figure 4-1 shows the reference circuit that internally

sets the op amp’s Common mode reference voltage

(VCM_INT) during calibration (the resistors are

disconnected from the supplies at other times). The

5kΩ resistor provides overcurrent protection for the

buffer.

FIGURE 4-1: Common-Mode Reference’s

Input Circuitry.

To op amp during

VCAL BUFFER

5kΩ

300 kΩ

150 kΩ

VSS

VDD calibration

VCM_INT

MCP621/1S/2/3/4/5/9

When the VCAL pin is left open, the internal resistor

divider generates a VCM_INT of approximately VDD/3,

which is near the center of the input Common mode

voltage range. It is recommended that an external

capacitor from VCAL to ground be added to improve

noise immunity.

When the VCAL pin is driven by an external voltage

source, which is within its specified range, the op amp

will have its input offset voltage calibrated at that

Common mode input voltage. Make sure that VCAL is

within its specified range.

It is possible to use an external resistor voltage divider

to modify VCM_INT

; see Figure 4-2. The internal circuitry

at the VCAL pin looks like 100 kΩ tied to VDD/3. The

parallel equivalent of R1 and R2 should be much

smaller than 100 kΩ to minimize differences in match-

ing and temperature drift between the internal and

external resistors. Again, make sure that VCAL is within

its specified range.

FIGURE 4-2: Setting VCM with External

Resistors.

For instance, a design goal to set VCM_INT =0.1V when

VDD = 2.5V could be met with: R1=24.3kΩ,

R2=1.00kΩ and C1= 100 nF. This will keep VCAL

within its range for any VDD, and should be close

enough to 0V for ground-based applications.

4.2 Input

4.2.1 PHASE REVERSAL

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-41 shows an input voltage

exceeding both supplies with no phase inversion.

4.2.2 INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-3. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

FIGURE 4-3: Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-4 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (VIN+

and VIN–) from going too far below ground, and the

resistors R1 and R2 limit the possible current drawn out

of the input pins. Diodes D1 and D2 prevent the input

pins (VIN+ and VIN–) from going too far above VDD, and

dump any currents onto VDD. When implemented as

shown, resistors R1 and R2 also limit the current

through D1 and D2.

FIGURE 4-4: Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of the

resistor R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN–) should be very small.

VSS

VDD

VCAL

MCP62X

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad VIN–

VDD

R1>VSS – (minimum expected V1)

2mA

VOUT

R2>VSS – (minimum expected V2)

2mA

MCP62X

MCP621/1S/2/3/4/5/9

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common

mode voltage (VCM) is below ground (VSS); see

Figure 2-15. Applications that are high-impedance may

need to limit the usable voltage range.

4.2.3 NORMAL OPERATION

The input stage of the MCP621/1S/2/3/4/5/9 op amps

use a differential PMOS input stage. It operates at low

Common mode input voltage (VCM), with VCM up to

VDD – 1.3V and down to VSS – 0.3V. The input offset

voltage (VOS) is measured at VCM =V

SS –0.3V and

VDD – 1.3V to ensure proper operation. See Figure 2-6

and Figure 2-7 for temperature effects.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the VCM range

(< VDD –1.3V); see Figure 4-5.

FIGURE 4-5: Unity Gain Voltage

Limitations for Linear Operation.

4.3 Rail-to-Rail Output

4.3.1 MAXIMUM OUTPUT VOLTAGE

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For instance, the output voltage swings to within

40 mV of the negative rail with a 2 kΩ load tied to

VDD/2.

4.3.2 OUTPUT CURRENT

Figure 4-6 shows the possible combinations of output

voltage (VOUT) and output current (IOUT). IOUT is

positive when it flows out of the op amp into the

external circuit.

FIGURE 4-6: Output Current.

4.3.2.1 Power Dissipation

Since the output short circuit current (ISC) is specified

at ±70 mA (typical), these op amps are capable of both

delivering and dissipating significant power.

Two common loads, and their impact on the op amp’s

power dissipation, will be discussed.

Figure 4-7 shows a resistive load (RL) with a DC output

voltage (VOUT). VL is RL’s ground point, VSS is usually

ground (0V) and IOUT is the output current. The input

currents are assumed to be negligible.

FIGURE 4-7: Diagram for Resistive Load

Power Calculations.

The DC currents are:

EQUATION 4-1:

The DC op amp power is:

EQUATION 4-2:

The maximum op amp power, for resistive loads at DC,

occurs when VOUT is halfway between VDD and VL, or

halfway between VSS and VL:

EQUATION 4-3:

VIN

VDD

VOUT

VSS V

IN V

OUT VDD 1.3V–

≤

MCP62X

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-80

-60

-40

-20

IOUT (mA)

VOUT (V)

RL = 10Ω

RL = 100Ω

RL = 2 kΩ

VOH Limited

VOL Limited

-ISC Limited

+ISC Limited

(VDD = 5.5V)

VDD

VOUT

IDD

ISS

IOUT

VSS

MCP62X

IOUT VOUT VL

–

--------------------------=

IDD IQmax 0 IOUT

,()+

≈

ISS I–Qmin 0 IOUT

,()+

≈

Where:

IQ= Quiescent supply current for one op

amp (mA/amplifier)

VOUT = A DC value (V)

POA IDD VDD VOUT

–()ISS VSS VOUT

–()+=

max POA

()IDD VDD VSS

–()=

max2VDD VL

–VLVSS

–

()

4RL

------------------------------------------------------------------+

MCP621/1S/2/3/4/5/9

Figure 4-7 shows a capacitive load (CL), which is

driven by a sine wave with DC offset. The capacitive

load causes the op amp to output higher currents at

higher frequencies. Because the output rectifies IOUT

the op amp’s dissipated power increases (even though

the capacitor does not dissipate power).

FIGURE 4-8: Diagram for Capacitive Load

Power Calculations.

The output voltage is assumed to be:

EQUATION 4-4:

The op amp’s currents are:

EQUATION 4-5:

The op amp’s instantaneous power, average power

and peak power are:

EQUATION 4-6:

The power dissipated in a package depends on the

powers dissipated by each op amp in that package:

EQUATION 4-7:

The maximum ambient-to-junction temperature rise

(ΔTJA) and junction temperature (TJ) can be calculated

using the maximum expected package power (PPKG),

ambient temperature (TA) and the package thermal

resistance (θJA) found in Table 1-4:

EQUATION 4-8:

The worst-case power derating for the op amps in a

particular package can be easily calculated:

EQUATION 4-9:

Several techniques are available to reduce ΔTJA for a

given package:

• Reduce θJA

- Use another package

- Improve the PCB layout (ground plane, etc.)

- Add heat sinks and air flow

• Reduce max (PPKG)

- Increase RL

- Decrease CL

- Limit IOUT using RISO (see Figure 4-9)

- Decrease VDD

VDD

VOUT

IDD

ISS

IOUT

VSS

MCP62X

VOUT VDC VAC

t()sin+=

Where:

VDC = DC offset (V)

VAC = Peak output swing (VPK)

= Radian frequency (2πf) (rad/s)

IOUT CLdVOUT

-----------------

⋅

VAC

t()cos==

IDD IQmax 0 IOUT

,()+

≈

ISS I–Qmin 0 IOUT

,()+

≈

Where:

IQ= Quiescent supply current for one op

amp (mA/amplifier)

POA IDD VDD VOUT

–()ISS VSS VOUT

–()+=

ave POA

() VDD VSS

–()IQ4VAC fCL

------------------------+

⎝⎠

⎛⎞

max POA

() VDD VSS

–()IQ2VAC fCL

+()=

PPKG POA

k1=

∑

Where:

n = Number of op amps in package (1 or 2)

TJA PPKG

TJTA

TJA

PPKG TJmax TA

–

--------------------------

≤

Where:

TJmax = Absolute maximum junction

temperature (°C)

TA= Ambient temperature (°C)

MCP621/1S/2/3/4/5/9

4.4 Improving Stability

4.4.1 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. See Figure 2-30. A unity gain buffer (G = +1)

is the most sensitive to capacitive loads, though all

gains show the same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 10 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-9) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-9: Output Resistor, RISO

Stabi li ze s Lar ge Capaci tiv e Load s.

Figure 4-10 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN=+2V/V).

FIGURE 4-10: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP621/1S/2/3/4/5/9 SPICE

macro model are helpful.

4.4.2 GAIN PEAKING

Figure 4-11 shows an op amp circuit that represents

non-inverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG

represent the total capacitance at the input pins; they

include the op amp’s Common mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

FIGURE 4-11: Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

CG also reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing CG or RF

CN and RN form a low-pass filter that affects the signal

at VP

. This filter has a single real pole at 1/(2πRNCN).

The largest value of RF that should be used depends

on noise gain (see GN in Section 4.4.1 “Capacitive

Loads”) and CG

. Figure 4-12 shows the maximum

recommended RF for several CG values.

FIGURE 4-12: Maximum Recommended

RF vs. Gain.

Figures 2-37 and 2-38 show the small signal and large

signal step responses at G = +1 V/V. The unity gain

buffer usually has RF=0Ω and RG open.

Figures 2-39 and 2-40 show the small signal and large

signal step responses at G = -1 V/V. Since the noise

gain is 2 V/V and CG≈10 pF, the resistors were

chosen to be RF=R

G=1kΩ and RN=500Ω.

RISO

VOUT

RGRF

RNMCP62X

100

1,000

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08

Normalized Capacitance; CL/GN (F)

Recommended RISO (Ω)

GN = +1

GN ≥ +2

1p 100p 1n 10n10p

VOUT

RGCG

MCP62X

1.E+02

1.E+03

1.E+04

1.E+05

110100

Noise Gain; GN (V/V)

Maximum Recommended RF

(Ω)

GN > +1 V/V

100

10k

100k

CG= 10 pF

CG= 32 pF

CG= 100 pF

CG= 320 pF

CG= 1 nF

MCP621/1S/2/3/4/5/9

It is also possible to add a capacitor (CF) in parallel with

RF to compensate for the destabilizing effect of CG

This makes it possible to use larger values of RF

The conditions for stability are summarized in

Equation 4-10.

EQUATION 4-10:

4.5 Power Supply

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high-frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

supplies does not prove to be a problem.

4.6 High Speed PCB Layout

These op amps are fast enough that a little extra care

in the PCB (Printed Circuit Board) layout can make a

significant difference in performance. Good PC board

layout techniques will help you achieve the

performance shown in the specifications and Typical

Performance Curves; it will also help you minimize

EMC (Electro-Magnetic Compatibility) issues.

Use a solid ground plane. Connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

Separate digital from analog, low speed from high

speed, and low power from high power. This will reduce

interference.

Keep sensitive traces short and straight. Separate

them from interfering components and traces. This is

especially important for high-frequency (low rise time)

signals.

Sometimes, it helps to place guard traces next to victim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect guard traces

to ground plane at both ends, and in the middle for long

traces.

Use coax cables, or low inductance wiring, to route the

signal and power to and from the PCB. Mutual and self

inductance of power wires is often a cause of crosstalk

and unusual behavior.

4.7 Typical Applications

4.7.1 POWER DRIVER WITH HIGH GAIN

Figure 4-13 shows a power driver with high gain

(1 + R2/R1). The MCP621/1S/2/3/4/5/9 op amp’s short

circuit current makes it possible to drive significant

loads. The calibrated input offset voltage supports

accurate response at high gains. R3 should be small,

and equal to R1||R2, in order to minimize the bias

current induced offset.

FIGURE 4-13: Power Driver.

4.7.2 OPTICAL DETECTOR AMPLIFIER

Figure 4-14 shows a transimpedance amplifier, using

the MCP621 op amp, in a photo detector circuit. The

photo detector is a capacitive current source. The op

amp’s input Common mode capacitance (9 pF, typical)

and Differential capacitance (2 pF, typical) act in paral-

lel with CD. RF provides enough gain to produce 10 mV

at VOUT. CF stabilizes the gain and limits

the transimpedance bandwidth to about 0.51 MHz.

RF’s parasitic capacitance (e.g., 0.15 pF for a

0603 SMD) acts in parallel with CF

FIGURE 4-14: Transimpedance Amplifier

for an Optical Detector.

fFfGBWP 2GN2

()

⁄

, GN1 GN2

≤

We need:

GN1 1R

FRG

⁄

GN2 1C

GCF

⁄

fF12

RFCF

()

⁄

fZfFGN1 GN2

⁄

()=

Given:

fFfGBWP 4GN1

()

⁄

, GN1 GN2

≤

R1R2

VIN

VDD/2 VOUT

R3RL

MCP62X

Photo

Detector

VDD/2

30pF

100 kΩ

3pF

100 nA

VOUT

MCP621

MCP621/1S/2/3/4/5/9

4.7.3 H-BRIDGE DRIVER

Figure 4-15 shows the MCP622 dual op amp used as

a H-bridge driver. The load could be a speaker or a DC

motor.

FIGURE 4-15: H-Bridge Driv er.

This circuit automatically makes the noise gains (GN)

equal, when the gains are set properly, so that the

frequency responses match well (in magnitude and in

phase). Equation 4-11 shows how to calculate RGT and

RGB so that both op amps have the same DC gains;

GDM needs to be selected first.

EQUATION 4-11:

Equation 4-12 gives the resulting Common mode and

Differential mode output voltages.

EQUATION 4-12:

VIN

VOT

RGB

VOB

VDD/2

RGT RL

½ MCP622

GDM VOT VOB

–

VIN VDD 2

⁄

–

-------------------------------- 2 V /V

≥≡

RGT RF

GDM 2

⁄

()1–

---------------------------------=

RGB RF

GDM 2

⁄

-------------------=

VOT V+ OB

--------------------------- VDD

-----------=

VOT V–OB GDM VIN VDD

-----------–

⎝⎠

⎛⎞

MCP621/1S/2/3/4/5/9

NOTES:

MCP621/1S/2/3/4/5/9

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP621/1S/2/3/4/5/9 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the

MCP621/1S/2/3/4/5/9 op amps is available on the

Microchip web site at www.microchip.com. This model

is intended to be an initial design tool that works well in

the op amp’s linear region of operation over the

temperature range. See the model file for information

on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

Filter-Lab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

5.3 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design

requirement. Available at no cost from the Microchip

web site at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a customer can define a filter to sort features

for a parametric search of devices and export

side-by-side technical comparison reports. Helpful links

are also provided for data sheets, purchase and

sampling of Microchip parts.

5.4 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time to

market. For a complete listing of these boards and their

corresponding user’s guides and technical information,

visit the Microchip web site at

www.microchip.com/analog tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

5.5 Application Notes

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

•ADN003: “Select the Right Operational Amplifier

for your Filtering Circui ts” (DS21821)

•AN722: “Operationa l Amplifier Topologies and DC

Specifications” (DS00722)

•AN723: “Operational Amplifier AC Specifications

and Applications” (DS00723)

•AN884: “Driving C apacitive L oads With Op Amps”

(DS00884)

•AN990: “Analog Sensor Conditioning Circuits –

An Overview” (DS00990)

•AN1177: “Op Amp Precision Design: DC Errors”

(DS01177)

•AN1228: “Op Amp Precision Design: Random

Noise” (DS01228)

•AN1332: “Current Sensing Circuit Concepts and

Fundamentals” (DS01332)

Some of these application notes, and others, are listed

in the design guide:

•“Signal Chain Design Guide” (DS21825)

MCP621/1S/2/3/4/5/9

NOTES:

MCP621/1S/2/3/4/5/9

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Device Code

MCP622T-E/MF DABL

Note: Applies to 8-Lead 3x3 DFN

Example:

5-Lead SOT-23 (MCP621S)

8-Lead TDFN (2 x 3) (MCP621) Example:

8-Lead DFN (3x3) (MCP622) Example

6-Lead SOT-23 ( MCP623)Example

XXNN

YU25

XXNN

JB25

AAY

129

DABL

1129

256

MCP621/1S/2/3/4/5/9

Package Marking Information (Continued)

14-Lead SOIC (.150”) (MCP624) Example

14-Lead TSSOP (MCP624)

10-Lead DFN (3x3) (MCP625)

10-Lead MSOP (MCP625) Example:

Device Code

MCP625T-E/MF BAFA

Note: Applies to 10-Lead 3x3 DFN

8-Lead SOIC (150 mil) (MCP621, MCP622) Example:

Example

NNN

MCP621E

SN ^^1129

256

BAFA

1129

256

625EUN

129256

MCP624

E/SL ^^

1129256

YYWW

NNN

XXXXXXXX

624E/ST

1129

256

16-Lead QFN (4x4) (MCP629) Example

PIN 1 PIN 1

629

E/ML ^^

129256

MCP621/1S/2/3/4/5/9

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 

 



 

   

  

  

  

    

    

    

    

    

    

    

    

   

    

    

123

A2 c

   

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 6

Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle 0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

PIN 1 ID BY

LASER MARK

123

A2 c

Microchip Technology Drawing C04-028B

MCP621/1S/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

!"#$%&'**+,./0!"



MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

'1#,4+/057



MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

8+&$%9&



 

 

 

 



 

   

  

  

    

    

    

  

  

  

    

  

   

    

    

NOTE 1

A2 c

   

MCP621/1S/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9



MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

8;<"#$%&'=*=*+,4/0<"





 



 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

EXPOSED

PAD

NOTE 1

TOP VIEW BOTTOM VIEW

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MCP621/1S/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP621/1S/2/3/4/5/9

APPENDIX A: REVISION HISTORY

Revision C (August 2011)

The following is the list of modifications:

1. Added the MCP621S and MCP623 amplifiers to

the product family and the related information

throughout the document.

2. Added the 2x3 TDFN (8L) package option for

MCP621, SOT-23 (5L) package for MCP621S

and SOT-23 (6L) package option for MCP623

and the related information throughout the

document.

3. Updated Section 6.0 “Packaging Informa-

tion” with markings for the new additions.

Added the corresponding SOT-23 (5L), SOT-23

(6L) and 2x3 TDFN (8L) package options and

related information.

4. Updated table description and examples in

Product Identification System.

Revision B (June 2011)

The following is the list of modifications:

1. Added the MCP624 and MCP629 amplifiers to

the product family and the related information

throughout the document.

2. Added the corresponding SOIC (14L), TSSOP

(14L) and QFN (16L) package options and

related information.

Revision A (June 2009)

• Original Release of this Document.

MCP621/1S/2/3/4/5/9

NOTES:

MCP621/1S/2/3/4/5/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP621: Single Op Amp

MCP621T: Single Op Amp (Tape and Reel)

(SOIC)

MCP621S: Single Op Amp (SOT-23)

MCP622: Dual Op Amp

MCP622T: Dual Op Amp (Tape and Reel)

(DFN and SOIC)

MCP623T: Single Op Amp (Tape and Reel) (SOT-23)

MCP624: Quad Op Amp

MCP624T: Quad Op Amp (Tape and Reel)

(TSSOP and SOIC)

MCP625: Dual Op Amp

MCP625T: Dual Op Amp (Tape and Reel)

(DFN and MSOP)

MCP629: Quad Op Amp

MCP629T: Quad Op Amp (Tape and Reel)

(QFN)

Temperature

Range:

E = -40°C to +125°C

Package: CHY = Plastic Small Outline (SOT-23), 6-lead

MF = Plastic Dual Flat, No Lead (3x3 DFN),

8-lead, 10-lead

ML = Plastic Quad Flat, No Lead Package (4x4 QFN),

(4x4x0.9 mm), 16-lead

MNY = Plastic Dual Flat, No Lead (2x3 TDFN),

8-lead

OT = Plastic Small Outline (SOT-23), 5-lead

SN = Plastic Small Outline, (3.90 mm), 8-lead

ST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),

14-lead

SL = Plastic Small Outline, Narrow, (3.90 mm SOIC),

14-lead

UN = Plastic Micro Small Outline, (MSOP), 10-lead

* Y = Nickel palladium gold manufacturing designator.

Only available on the TDFN package.

Examples:

a) MCP621T-E/SN: Tape and Reel,

Extended Temperature,

8LD SOIC package

b) MCP621T-E/MNY: Tape and Reel,

Extended Temperature,

8LD TDFN package

c) MCP621ST-E/OT: Tape and Reel,

Extended Temperature,

5LD SOT-23 package

d) MCP622T-E/MF: Tape and Reel,

Extended Temperature,

8LD DFN package

e) MCP622T-E/SN: Tape and Reel,

Extended Temperature,

8LD SOIC package

f) MCP623T-E/CHY: Tape and Reel,

Extended Temperature,

6LD SOT-23 package

g) MCP624T-E/SL: Tape and Reel,

Extended Temperature,

14LD SOIC package

h) MCP624T-E/ST: Tape and Reel,

Extended Temperature,

14LD TSSOP package

i) MCP625T-E/MF: Tape and Reel,

Extended Temperature,

10LD DFN package

j) MCP625T-E/UN: Tape and Reel,

Extended Temperature,

10LD MSOP package

k) MCP629T-E/ML: Tape and Reel,

Extended Temperature,

16LD QFN package

PART NO. -X /XX

PackageTemperature

Range

Device

MCP621/1S/2/3/4/5/9

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-545-0

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopp ing

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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