LINEAR TECHNOLOGY NOVEMBER 1998 IN THIS ISSUE... COVER ARTICLE World's Smallest 24-Bit ADC Packs High Accuracy, Ease of Use, into SO-8 ..................................................... 1 Michael K. Mayes Issue Highlights ............................ 2 VOLUME VIII NUMBER 4 World's Smallest 24-Bit ADC Packs High Accuracy, Ease of Use, into SO-8 LTC(R) in the News ........................... 2 DESIGN FEATURES Wide Input Range, High Efficiency Step-Down Switching Regulators .................... 5 Jeff Schenkel A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for 3V/5V Operation .......................... 10 Joseph G. Petrofsky 250MHz RGB Video Multiplexer in Space-Saving Package Drives Cables, Switches Pixels at 100MHz ......... 16 John Wright and Frank Cox LT (R)1468: An Operational Amplifier for Fast, 16-Bit Systems .............. 18 George Feliz LTC1622: Low Input Voltage, Current Mode PWM Buck Converter .......... 21 San-Hwa Chee LTC1531 Isolated Comparator .... 24 Wayne Shumaker DESIGN IDEAS PolyPhaseTM Switching Regulators Offer High Efficiency in Low Voltage, High Current Applications .......... 27 Craig Varga Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply ...................... 30 Frank Cox DESIGN INFORMATION Component and Measurement Advances Ensure 16-Bit DAC Settling Time (Part Two) ........................... 31 Jim Williams Net1 and Net2 Serial Interface Chip Set Supports Test Mode ............... 34 David Soo New Device Cameos ..................... 37 Design Tools ................................ 39 Sales Offices ............................... 40 by Michael K. Mayes Introduction Overview Linear Technology enters the deltasigma1, 2 analog-to-digital converter market with a tiny, high performance, 24-bit ADC, the LTC2400. The device's superiority to existing deltasigma ADC's results from the combination of an accurate analog modulator with an innovative new digital architecture. Typically, fineline, digitally optimized processes are required for a delta-sigma ADC's on-chip digital filter. The resulting ICs have high pin counts, large packages and complex interfaces. The LTC2400's breakthrough in digital filtering allows the use of an analogoptimized process. The result is the smallest (SO-8 package), lowest pin count (8) simplest to use delta-sigma converter on the market. A highly accurate on-chip oscillator, using Linear's high performance CMOS process, sets the digital filter's notch frequency, eliminating the need for an external crystal. Additionally, the part offers exceptional INL, DNL, noise and 50Hz/60Hz rejection. The innovation does not end here; this article will show how performance, ease of use and functionality make this part the new state of the art in high resolution delta-sigma ADCs. The analog modulator is critical to the performance of a delta-sigma ADC. For high DC accuracy, 1st or 2nd order modulators provide insufficient differential nonlinearity (DNL). The LTC2400 achieves optimum DC performance from a 3rd order delta-sigma modulator (see Figure 1). Feedforward compensation and analog processing within the modulator eliminate instability issues associated with high order modulators. The 1-bit ADC and DAC within the modulator guarantee monotonicity and exceptional INL performance of 4ppm. The output of the delta-sigma modulator is applied to a decimating filter. The sinc4 filter removes the quantization noise from the modulator output. Additionally, this filter rejects the fundamental frequency and its harmonics. This notch frequency is set by an on-chip oscillator, typically at line frequency for DC applications. The combination of a 4th order sinc filter with a precision thin-film, factory-trimmed oscillator guarantees at least 120dB rejection of line frequency 2%. Several converters on the market use sinc3 or sinc1 filters. Since line frequencies can vary up to 2% over a 24-hour period, converters using these lower order filters cannot achieve 120dB Authors can be contacted at (408) 432-1900 continued on page 3 , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load, FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, No R SENSE, PolyPhase, SwitcherCAD and UltraFast are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the products. EDITOR'S PAGE Issue Highlights Our cover article for this issue in- The comparators feature internal hystroduces Linear Technology's entry teresis, making them easy to use, into the delta-sigma analog-to-digital even with slowly moving input signals. converter market: the tiny, high per- The LT1720 is fabricated in Linear formance, 24-bit L TC2400. The Technology's 6GHz complementary LTC2400's superiority to existing bipolar process, resulting in unprecdelta-sigma ADC's results from the edented speed for its low power combination of an accurate analog consumption. modulator with an innovative new The LTC1531 is an isolated, selfdigital architecture. The LTC2400's powered comparator that receives breakthrough in digital filtering allows power and communicates through the use of an analog-optimized pro- internal isolation capacitors. The isocess. The result is the smallest (SO-8 lation capacitors provide 3000VRMS of package), lowest pin count (8) sim- isolation between the comparator and plest to use delta-sigma converter on its output. This allows the part to be used in applications that require high the market. Our Design Features section debuts voltage isolated sensing without the three new power products. The need for an isolated power source. In the amplifier arena, we premier LT1676 and LT1776 are Linear Technology's latest offerings for high the LT1468, a single op amp optimized voltage (to 60V) step-down switching for accuracy and speed in 16-bit sysregulator applications. The LT1676/ tems. Operating from 15V supplies, LT1776 operate in a fixed frequency the LT1468 in a gain of -1 configuramode (100kHz for the LT1676 vs tion will settle in 900ns to 150V for 200kHz for the LT1776) and can be a 10V step. It also features the excelexternally synchronized to a higher lent DC specifications required for switching frequency. The internal out- 16-bit designs. Two key applications put switch is rated at a nominal peak are current-to-voltage (I/V) convercurrent of 700mA, which typically sion following a fast, 16-bit current accommodates DC output currents output digital-to-analog converter (DAC) and buffering the input of up to 500mA. of an analog-to-digital The LTC1622 a converter (ADC). step-down DC/DC Be a One of the first controller is Linear Insider! products from LTC's designed to Visit our web site new proprietary high harness all the (www.linear-tech.com/insider) speed bipolar energy from or use the response card in this issue to pr ocess is a lithium-ion register. We will notify you via email 2 50MHz RGB batteries. Its about new information on the (r ed, green, blue) wide input-voltage web site that matches multiplexer that is range and your interests optimized for switching 100% duty cycle speed. This new MUX, the allow low dropout for LT1675, is designed for pixel switchmaximum energy extraction from the battery. Its low quiescent current ing in video graphics and for RGB extends battery life. High frequency routing. It is configured with three operation allows the use of small SPDT RGB video switches and three inductors, making it ideal for com- current feedback amplifiers for direct driving of cables. munications products. Our two Design Ideas for this issue In addition, this issue introduces two new comparators. The LT1720 is are a PolyPhase supply based on two an UltraFastTM, low power, single- LTC1430As operating 180 out of supply, dual comparator designed to phase, and a current feedback video operate on a single 3V or 5V supply. 2 LTC in the News... Linear Technology Corporation announced its first quarter financial results on October 13, 1998, r eporting net sales of $116,032,000--an increase of 6% compared to the same period last year. The Company's net income for the quarter, $44,382,000 or $0.56 diluted earnings per share, was up 9% compared to the first quarter of last year. Linear Technology also reported that during the quarter it purchased back 1,800,000 shares of its common stock at a cost of approximately $100,000,000. In discussing the results, President and CEO Robert H. Swanson noted that the Company continued to have outstanding profitability and Linear Technology's return on sales for the quarter "was both a record for the Company and the strongest in the industry." Linear Technology's new deltasigma analog-to-digital converter, the LTC2400 (see page 1), was the cover story of the September issue of Electronic Design. The article detailed the LTC2400's exceptional speed, precision and ease-of-use, and included a range of illustrations highlighting the LTC2400's 24-bit differential nonlinearity with no missing codes. The article also underscor ed this new part's groundbreaking design, allowing it to be housed in a tiny SO-8 package yet deliver superior performance compared to competing parts more than twice its size. amplifier with a level shifter for ground-referenced signals. Our Design Information section features the conclusion of Jim Williams's exposition on measuring 16-bit DAC settling time, and also introduces the LTC1545, a Net1 and Net2 compliant serial interface chip that supports the optional Test Mode, Remote Loopback and Local Loopback functions. We conclude with a septet of New Device Cameos. Linear Technology Magazine * November 1998 DESIGN FEATURES VCC GND VIN INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL fO (INT/EXT) DOUT SERIAL INTERFACE ADC SCLK CS VREF DECIMATING FIR FILTER DAC Figure 1. LTC2400 block diagram rejection, even with exact external oscillators (refer to Figure 6a). A simple, SPI-compatible 3-wire interface outputs data with singlecycle settling. This simplifies the user interface by eliminating latency and redundant data normally associated with delta-sigma ADCs. As a black box, the converter resembles traditional, easy-to-use converters. Performance 5 5 4 4 3 2 VCC = 5V VREF = 2.5V TA = 25C fO = GND 1 0 -1 -2 3 OFFSET ERROR (ppm) INTEGRAL NONLINEARITY (ppm) Designed on a 2 , single-metal, analog CMOS process, the LTC2400 is implemented with a die size under 10kmil2. The key to Linear attaining the nearly impossible is the highly efficient sinc4 filter. Once the tiny digital circuitry was completed, the analog circuitry was optimized for ultrahigh performance. The result is 24-bit DNL with no missing codes guaranteed. As shown in Figure 2, the integral nonlinearity is a mere 2ppm or 0.0002%. This compares favorably with other 24-bit devices' INL performance of 15ppm- 30ppm. Transparent to the user, the converter continuously executes selfcalibration algorithms automatically adjusting the offset and full-scale. With an initial accuracy of 1ppm, the offset drifts less than 0.01ppm/C and the full scale drifts less than 0.02ppm/C (see Figures 3 and 4). Combining these DC parameters with RMS noise performance of 0.3ppm (see Figure 5), the LTC2400 resembles a 6-digit digital voltmeter on a chip. The modulator consists of operational amplifiers and switched capacitor circuits. Previous deltasigma converters place limitations on these circuits. Since the LTC2400 was designed on an analog process, these limitations are removed. This 2 -2 -4 Linear Technology Magazine * November 1998 3 -1 -4 Figure 2. LTC2400 integral nonlinearity error 4 VCC = 5V VREF = 5V fO = GND 0 -3 -5 0.00E+00 4.19E+06 8.39E+06 1.26E+07 1.68E+07 OUTPUT CODE (DECIMAL) 5 1 -3 -5 -40 allows a power supply range of 2.7V to 5.5V and a reference range of from below 10mV to 90% of VCC. At V CC = 3V, the power consumption is 750 W; it falls to 45 W in power-down mode. In many applications, the input signal may exceed VREF or fall below ground. Conventional delta-sigma converters are unable to provide the user with any indication of these overrange conditions. The LTC2400 has on-chip overrange circuitry. It continues to output 24-bit valid data over an effective input range of -12.5% x VREF to 112.5% x VREF. One of the main advantages of delta-sigma converters over SAR or flash-type architectures is the inherent rejection of line frequency. In order to achieve good rejection, past deltasigma converters required an accurate external oscillator or crystal with a precise, uncommon value. The LTC2400 incorporates an on-chip oscillator eliminating the need for FULL-SCALE ERROR (ppm) LTC2400, continued from page 1 2 1 0 -1 -2 VCC = 5V VREF = 5V fO = GND -3 -4 -15 10 35 60 TEMPERATURE (C) Figure 3. Offset drift 85 -5 -40 -15 10 35 60 TEMPERATURE (C) 85 Figure 4. Full-scale drift 3 DESIGN FEATURES 0 1200 RMS NOISE = 0.3ppm =1.5V PEAK-TO-PEAK NOISE = 1.8ppm = 9V OFFSET ERROR = 0.28ppm -20 800 600 VDD = 5V VREF = 5V TA = 25C fO = GND SINC2 -60 -80 400 -100 200 -120 0 -1.2 SINC -40 1000 REJECTION (dB) NUMBER OF OCCURRENCES AT VIN = OV 1400 SINC3 SINC4 (LTC2400) -140 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 OUTPUT CODE (ppm OF VREF) 0.6 0.8 1.0 0 1.2 50 100 150 200 FREQUENCY (Hz) 250 300 Figure 6a. Filter response vs filter order Figure 5. Noise histogram 0 Ease of Use At a glance, the LTC2400 looks more like an op amp than a delta-sigma converter. With only eight pins, it's about as easy to use as a common op amp (see Figure 8). Superior noise rejection and internal analog circuitry enable the use of one supply pin, one ground pin and a single-ended input. The internal oscillator eliminates external crystals/capacitors and added device pins. The remaining pins form a standard 3-wire interface, consisting of a three-statable serial data output (DOUT) under the control of a chip select pin (CS) and a serial data output clock (SCLK). Applications currently using traditional ADCs can easily migrate to the LTC2400. Single-cycle settling yields a one-to-one correspondence between the start of a conversion and the output word. This allows the user to place a multiplexer in front of the ADC without worrying about latency or data statistically dependent on previous conversion results. -20 -40 REJECTION (dB) external components. The internal oscillator is so precise that the ADC rejects line frequency over a 2% range, independent of supply or operating temperature (see Figure 6a, where sinc1, sinc2 and sinc3 filters are shown for comparison). Line frequencies of 50Hz or 60Hz are selectable by simply tying the fO pin to VCC or ground. Other rejection frequencies can be obtained by driving the fO pin with an external clock. The converter is so robust that the noise performance and line rejection are insensitive to layout. As shown in Figure 7, large noise errors applied to VCC, VREF or VIN (1.25VP-P, 60Hz, 2%) have no effect on the ADC's noise and linearity performance. -60 -80 -100 -120 -140 -5.8% -3.3% 60 +3.3% +5.8% FREQUENCY (Hz) Figure 6b. Filter response at line frequency Functionality Despite its small size and low pin count, the LTC2400 provides many flexible modes of operation. For example, tying CS low forces a continuous conversion mode. With CS tied high, the device enters a 45 W power-down mode. For applications requiring ultralow power, a capacitor can be tied to CS. Under this continued on page 36 CODE OUT (ppm) 20 ONE-SHOT OUTPUT CODE (NO AVERAGING) 10 0 -10 -20 INJECTED NOISE VIN 1VRMS VCC VREF 60Hz TIME Figure 7. Noise injection 4 Linear Technology Magazine * November 1998 DESIGN FEATURES Wide Input Range, High Efficiency Step-Down Switching Regulators by Jeff Schenkel Introduction The LT1676 and LT1776 are Linear Technology's latest offerings for high efficiency step-down switching regulator applications. These two parts are pin-for-pin compatible and virtually identical in operation, the only difference being their internal oscillator frequencies--100kHz for the LT1676 vs 200kHz for the LT1776. They operate in a fixed frequency mode (as opposed to constant offtime or on-time, for instance) and can be externally synchronized to a higher switching frequency. The internal output switch is rated at a nominal peak current of 700mA, which typically accommodates DC output currents of up to 500mA. The input voltage range is 7.4V to 60V. Maintaining acceptable efficiency in the upper half of this input voltage range requires very fast output-switch edge rates. The LT1676/LT1776 contain specialized output circuitry to deliver this performance. Additionally, they contain circuitry to monitor output load level and reduce leadingedge switch rate (turn-on) when the output load is light. This arrangement helps avoid pulse skipping at light load, with its consequent subharmonic behavior. True current mode operation is supported, with all its well known advantages for switching regulator operation. The shutdown pin implements a pair of functions. Pulling it down to near ground turns off the part almost completely and reduces the quiescent current to a few tens of microamperes. The second shutdown pin function acts at a threshold of roughly 1.25V. Below this level, the part operates normally, except that output switching action is inhibited. This allows the implementation of an undervoltage lockout function set by, for instance, an external resistor divider. The LT1676/LT1776 are available in both 8-pin SO and PDIP packages. Theory of Operation The LT1676/LT1776 are current mode switching regulator ICs optimized for high efficiency operation in high input voltage, low output voltage buck topologies. The block diagram in Figure 1 shows an overall view of the system. Several of the blocks are straightforward and similar to those found in traditional designs, including the internal bias regulator, oscillator and feedback amplifier. The novel portion includes an elaborate output switch section and a logic section to provide the control signals required by the switch section. The LT1676/LT1776 operate much the same as traditional current mode switchers, the major difference being their specialized output switch section. Due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and the step-down topology. A good source of information on these topics is Linear Technology Application Note 19. VCC 2 R1 5 VIN 3 VSW RSENSE VBG SHDN 1 BIAS VB OSC SYNC 6 LOGIC Q3 I COMP SWDR Q4 SWDR SWON BOOST SWOFF Q2 Q1 D1 GND 4 SWON I BOOST COMP I I VC 8 FB AMP FB 7 gm VTH BOOST I SWOFF Q5 VBG 1776 BD Figure 1. LT1776 block diagram Linear Technology Magazine * November 1998 5 DESIGN FEATURES VIN VIN VSW VSW 0 0 SWDR SWDR SWON SWON BOOST BOOST SWOFF SWOFF 1776 TD01 1776 TD02 Figure 2a. Timing diagram: high dV/dt mode One of the classic problems in delivering low output voltage from a high input voltage at good efficiency is that minimizing AC switching losses requires very fast voltage (dV/dt) and current (dI/dt) transitions at the output device. This is in spite of the fact that in a cost-effective bipolar IC process implementation, slow lateral PNPs must be included in the switching signal path. Fast, positive-going slew rate action is provided by lateral PNP Q3 driving the Darlington arrangement of Q1 and Q2. The extra available from Q2 greatly reduces the drive requirements of Q3. Although desirable for dynamic reasons, this topology alone will yield a large DC forward voltage drop. A second lateral PNP, Q4, acts directly on the base of Q1 to reduce the voltage drop after the slewing phase has taken place. To achieve the desired high slew rate, PNPs Q3 and Q4 are "force-fed" packets of charge via the current sources controlled by the BOOST signal. Please refer to the timing diagram of Figure 2a. A typical oscillator cycle is as follows: The logic section first generates a SWDR signal, which pow+ C1 39F 63V ers up the current comparator and allows it time to settle. About 1s later, the SWON signal is asserted and the BOOST signal is pulsed for a few hundred nanoseconds. After a short delay, the VSW pin slews rapidly to VIN . Later, after the peak switch current, indicated by the control voltage VC, has been reached (current mode control), the SWON and SWDR signals are turned off and SWOFF is pulsed for a few hundred nanoseconds. The use of an explicit turn-off device (Q5) improves turn-off response time and thus aids both controllability and efficiency. The system described previously handles heavy loads (continuous mode) at good efficiency, but is actually counterproductive for light loads. The method of jamming charge into the PNP bases makes it difficult to turn them off rapidly and achieve the very short switch ON times required by light loads in discontinuous mode. Furthermore, the high leading edge dV/dt rate has a similar adverse effect on light load controllability. The solution is to employ a "boost comparator" whose inputs are the VC control voltage and a fixed internal 5 1 C5 100pF 6 VIN SHDN VCC VSW LT1676 FB SYNC VC GND 4 C1: PANASONIC HFQ (201) 348-7522 C2: AVX D CASE TPSD107M010R0080 (803) 946-0362 C4, C5: X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY (800) 441-2447 L1: COILCRAFT DO3316P-224 (847) 936-6400 90 L1 220H 2 3 D1 MBRS1100 7 8 C3 2200pF X7R R3 22k 5% + C2 100F 10V R1 36.5k 1% FOR 3.3V VOUT VERSION: R1: 24.3k, R2: 14.7k L1: 150H, DO3316P-154 IOUT: 0mA TO 500mA 80 VOUT 5V 0mA to 500mA R2 12.1k 1% C4 100pF Figure 3a. Minimum component-count application 6 threshold reference, VTH. (Remember that in a current mode switching topology, the VC voltage determines the peak switch current.) When the VC signal is above VTH, the previously described "high dV/dt" action is performed. When the VC signal is below VTH, the BOOST pulses are absent, as can be seen in Figure 2b. Now the DC current activated by the SWON signal alone drives Q4 and this transistor drives Q1 by itself. The absence of a BOOST pulse plus the lack of a second NPN driver results in a much lower slew rate, which aids light load controllability. A further aid to overall efficiency is provided by the specialized bias regulator circuit, which has a pair of inputs, VIN and VCC. The VCC pin is normally connected to the switching supply output. During start-up conditions, the LT1676/LT1776 power themselves directly from VIN. However, after the switching supply output voltage reaches about 2.9V, the bias regulator uses this supply as its input. Previous generation step-down controller ICs without this provision typically required hundreds of milliwatts of quiescent power when 1676 F04a 70 EFFICIENCY (%) VIN 12V TO 48V Figure 2b. Timing diagram: low dV/dt mode 60 50 40 VIN = 12V VIN = 24V 30 VIN = 36V VIN = 48V 20 1 10 100 LOAD CURRENT (mA) 1000 1676 F04b Figure 3b. Efficiency of Figure 3a's circuit Linear Technology Magazine * November 1998 DESIGN FEATURES 90 + C1 15F 35V 1 5 80 VIN SHDN C5 100pF VCC 3 VSW LT1776 6 SYNC GND C2 100F 10V L1 68H 2 + R1 36.5k 1% D1 MBRS1100 7 FB 8 VC C3 2200pF R2 12.1k 1% C4 100pF 4 VOUT 5V 0mA to 400mA 70 EFFICIENCY (%) VIN 10V-30V 60 50 40 VIN = 10V R3 22k 5% VIN = 30V 20 C4, C5: 100pF, X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY MBRS1100 (800) 441-2447 L1: COILCRAFT DO1608C-683 (847) 936-6400 10 100 LOAD CURRENT (mA) 1 1776 F07a C1: AVX D CASE 15F 35V TPSD156M035R0300 (803) 946-0362 C2: AVX D CASE 100F 10V TPSD107M010R0080 C3: 2200pF, X7R VIN = 20V 30 FOR 3.3V VOUT VERSION: IOUT: 0mA TO 500mA L1: 47H, DO1608C-473 R1: 24.3k, R2: 14.7k 1000 1776 F07b Figure 4b. Efficiency of Figure 4a's circuit Applications Figure 4a. Minimum PC board area application Minimum Componentoperating at high input voltages. This quency allows for a lower valued and Count Application both degraded efficiency and limited available output current due to internal heating. Choosing Between the LT1676 and LT1776 As previously mentioned, the LT1676 and LT1776 devices are pin-for-pin compatible and, in fact, nearly identical. The only real difference is in their internal oscillator frequencies, nominally 100kHz for the LT1676 and 200kHz for the LT1776. A user must decide which version is best suited for his or her particular application. Generally, the LT1776 is favored, as its higher switching fre- possibly physically smaller and less costly inductor. However, the higher switching frequency of the LT1776 increases AC switching losses, adversely affecting efficiency and internal power dissipation. In fact, certain combinations of high input voltage and output current may yield unacceptable internal power dissipation and consequent thermal rise. In these cases, the slower switching frequency of the LT1676 may yield acceptable operation. (A more thorough treatment of input voltage vs operating frequency considerations can be found in the LT1776 data sheet.) VIN 12V-48V C1 39F 63V 6 Q1 PN2484 Q2 2N2369 1 5 VIN SYNC VCC VSW U1 LT1676 FB SHDN VC GND NC L1 220H 2 3 D1 MBRS1100 7 8 4 + C2 100F 10V C3 100pF VOUT 5V R1 39k 5% R2 10k 5% V+ OUT 90 80 VIN = 12V 70 4 IN - + 3 IN U2 LTC1440 6 REF 5 HYST V- GND 2 The previous application example used the LT1676 to demonstrate simultaneously the maximum input voltage and output current capability. As such, the input bypass capacitor choice was a high frequency aluminum electrolytic type, rated to R3 323k 1% 7 C1: PANASONIC HFQ 8 (201) 348-2552 C2: AVX D CASE TPSD107M010R0080 (803) 946-0362) C4, C5: X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY (800) 441-2447 L1: COILCRAFT DO3316-224 (847) 639-6400 Minimum PC Board Area Application 1 R6 22k R7 2.4M R4 100k 1% EFFICIENCY (%) + R7 10M Figure 3a shows a basic "minimum component count" application using the LT1676. The circuit produces 5.0V at up to 500mA IOUT with input voltages in the range of 12V to 48V. The typical POUT/PIN efficiency is shown in Figure 3b. No pulse skipping is observed down to zero external load. (The several milliamperes drawn by the VCC pin acts as a sufficient preload.) As shown, the SHDN and SYNC pins are unused, however either (or both) can be optionally driven by external signals as desired. VIN = 48V VIN = 36V VIN = 24V 60 50 40 30 1676 F06 20 1 Figure 5a. Burst Mode operation configuration Linear Technology Magazine * November 1998 10 100 LOAD CURRENT (mA) 1000 1676 F07b Figure 5b. Efficiency of Figure 5a's circuit 7 DESIGN FEATURES VIN 11V TO 30V (SEE TEXT) + C1 39F 63V 5 VIN 1 7 FB 2 VCC SHDN C5 100pF U1 LT1776 3 VSW 8 SYNC VC GND 6 L1 100H C4 2200pF C3 100pF 4 U3 LT1121-5 C6 0.33F C7 0.1F R4 0.5 7.2V + D1 MBRS1100 R3 22k C8 1F R5 3k R6 12k + C2 100F 10V R1 57.6k 1% 3-CELL LEAD-ACID BATTERY R2 12.1k 1% 6 8 VCC 2 IOUT U2 LT1620 7 5 PROG IN + 1 - 4 NC SENSE IN AVG 1776 TA02 GND 3 C1: PANASONIC HFQ (201) 348-7522 C2: AVX TPSD107M010R0080 (803) 946-0362 L1: COILCRAFT DO3316P-104 (847) 639-6400 Figure 6a. Wide VIN range, high efficiency battery charger 63V. Also, the 100kHz switching rate of the LT1676 requires an inductor of about 220 H. The DO3316 device size was chosen to support the output current requirements. However, both of these components are physically large. The application example in Figure 4a shows a circuit that is much smaller physically than the previous minimum component count application. The nominal 200kHz switching frequency of the LT1776 allows the use of a physically smaller 68 H inductor--a Coilcraft DO1608C-683. This inductor will support output current to 400mA at 5V. However, the part is incapable of withstanding an indefinite short circuit to ground. (Momentary shorts of a few seconds or less can still be tolerated.) Additionally, the bulky aluminum 8 OUTPUT VOLTAGE (V) 7 6 5 4 3 2 1 0 0 50 100 150 200 OUTPUT CURRENT (mA) 250 1776 TA05 Figure 6b. Battery charger output voltage vs output current for Figure 6a's circuit 8 electrolytic capacitor previously on VIN has been replaced by a compact 35V-rated tantalum type. The result is a postage-stamp-sized circuit with efficiency as shown in Figure 4b. Burst Mode Application The minimum component count application demonstrates that power supply efficiency degrades with lower output load current. This is not surprising, as the LT1676 itself represents a fixed power overhead. A possible way to improve light load efficiency is to use Burst ModeTM operation. Figure 5a shows the LT1676 configured for Burst Mode operation. Output voltage regulation is now provided in a "bang-bang" digital manner, via comparator U2, an LTC1440. Resistor divider R4/R5 provides a scaled version of the output voltage, which is compared against U2's internal reference. Intentional hysteresis is set by the R6/R7 divider. As the output voltage falls below the regulation range, the LT1676 is turned on. The output voltage rises and, as it climbs above the regulation range, the LT1676 is turned off. Efficiency is maximized as the LT1676 is only powered up while it is providing heavy output current. Figure 5b shows that efficiency is typically maintained at 75% or better down to a load current of 10mA. Even at a load current of 2mA, efficiency is still a respectable 65% to 75% (depending on VIN ). Resistor divider R1/R2 is still present, but does not directly influence output voltage. It is chosen to ensure that the LT1676 delivers high output current throughout the voltage regulation range. Its presence is also required to maintain proper short-circuit protection. Transistors Q1 and Q2 and resistor R7 form a high VIN, low quiescent current voltage regulator to power U2. Battery Charger Application Figure 6a shows the LT1776 configured as a constant-current/ constant-voltage battery charger. An LT1620 rail-to-rail current sense amplifier (U2) monitors the differential voltage across current sense resistor R4. As this equals and exceeds the voltage across resistor R5 in the R5/R6 divider, the LT1620 responds by sinking current at its IOUT pin. This is connected to the VC control node of the LT1776 and therefore acts to reduce the amount of power delivered to the load. The overall constantcurrent/constant-voltage behavior can be seen in Figure 6b. Target voltage and current limits are independently programmable. The output voltage of 7.2V, which corresponds to the charging voltage of a 3-cell lead-acid battery, is set by the R1/R2 divider and the internal referLinear Technology Magazine * November 1998 DESIGN FEATURES VIN 10V-28V + C1 15F 35V exact calculation includes the input voltage. For this and further details of this topology, see Linear Technology Design Note 100. 5 VIN 1 C7 100pF VCC SHDN LT1776 VSW FB 6 VC SYNC 2 L1* 100H 3 7 8 D1 MBR1100 C6 100pF C2 100F 10V VOUT 5V + Positive-to-Negative Converter R1 36.5k 1% GND 4 C1: AVX D CASE TPSD156M035R0300 (803) 946-0362 C2, C3, C4: AVX D CASE TPSD107M010R0080 C6, C7: X7R OR COG/NPO D1, D2: MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY (800) 441-2447 *L1: COILTRONICS CTX100-3 SINGLE CORE WITH 2 WINDINGS (561) 241-7876 R2 12.1k 1% C3 100F 10V VOUT -5V D2 MBR1100 L1* 100H + R3 22k 5% + C5 2200pF X7R C4 100F 10V TOTAL AVAILABLE CURRENT IS LIMITED TO 500mA (SEE TEXT) Figure 7. Dual-output SEPIC converter ence of the LT1776. Output current, presently 200mA, is set by current sense resistor R4 and the R5/R6 divider. (A 16-pin version of the LT1620 that implements end-of-cycle detection is also available. This is useful for implementing lead-acid battery "topoff" charger behavior or the like. See the LT1620 data sheet for further information.) The circuit as shown accommodates an input voltage range of 11V to 30V. The upper input voltage limit of 30V is determined not by the LT1776, but by the LT1121-5 regulator (U3). (A regulated 5V is required by the LT1620.) This regulator was chosen for its micropower behavior, which helps maintain good overall efficiency. However, the basic catalog part is only rated to 30V. Substitution of the industry standard LM317, for example, extends the allowable input voltage to 40V (or more with the HV version), but its greater quiescent current drain degrades efficiency from that shown. Dual Output SEPIC Converter All of the previous applications provide a single positive output voltage. Real world situations often require dual supply voltages. The SEPIC topology (single-ended primary inductance converter) offers a cost-effective way to simultaneously generate a negative voltage with a single piece of Linear Technology Magazine * November 1998 magnetics. The circuit in Figure 7 uses an LT1776 to generate both positive and negative 5V. The two inductors shown are actually just two windings on a standard Coiltronics inductor. Capacitor C3 creates the SEPIC topology, which improves regulation and reduces ripple current in L1. For the best negative supply voltage regulation, this output should have a preload of at least 1% of the maximum positive load. Total available current from both outputs is limited to 500mA. Maximum negative supply current is limited by the positive 5V load. A typical limit is one-half of the positive current, but a more VIN 10V-28V + The previous example used a dual inductor to create a pair of output voltages, one positive and the other negative. The positive-to-negative converter topology illustrated in Figure 8 generates a single negative output voltage from a positive input voltage, using just an ordinary inductor. The topology is somewhat similar to the original step-down arrangement, but the inductor is grounded and the LT1776 ground is now referred to the negative output voltage. Note that the integrated circuit must now be rated for the worst case sum of the input voltage plus the absolute value of the output voltage. The relatively high input voltage rating of the LT1676/ LT1776 parts along with their good efficiency under such conditions make them an excellent choice for implementing this topology. The circuit as shown converts an input voltage in the range of 10V to 28V to a -5V output. Available output current is 300mA at the worst case VIN of 10V. The user should exercise caution in modifying this circuit for other applications. The positive-to-negative topology is not as straightforward as the step-down topology. It is actually more like a flyback topology, in that current is delivered to the output in continued on page 20 C1 15F 35V 5 VIN 1 C5 100pF VCC SHDN LT1776 6 VSW FB VC SYNC 2 3 L1 100H 7 8 R1 36.5k 1% GND 4 R3 22k 5% C3 2200pF X7R C4 100pF D1 MBRS1100 C1: AVX D CASE TPSD156M035R0300 (803) 946-0362 C2: AVX D CASE TPSD107M010R0080 C4, C5: X7R OR COG/NPO D1: MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY (800) 441-2447 L1: COILCRAFT D03316-104 (847) 639-6400 R2 12.1k 1% + C2 100F 10V VOUT -5V 0mA-300mA Figure 8. Positive-to-negative converter 9 DESIGN FEATURES A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for by Joseph G. Petrofsky 3V/5V Operation Introduction NONLINEAR STAGE The LT1720 is an UltraFastTM (4.5ns), low power (4mA/comparator), singlesupply, dual comparator designed to operate on a single 3V or 5V supply. These comparators feature internal hysteresis, making them easy to use, even with slowly moving input signals. The LT1720 is fabricated in Linear Technology's 6GHz complementary bipolar process, resulting in unprecedented speed for its low power consumption. Table 1 summarizes the LT1720's perfor mance specifications. The LT1720 is offered in SO-8, with just three pins per comparator plus power and ground. For a full-featured, 7ns, single-supply comparator with dual complementary outputs and internal latch, the LT1394 is available from this same high speed process. These fast, small, low power comparators are versatile building blocks for a variety of high speed, singlesupply applications, such as clock generators, window comparators, timing skew generators, coincidence detectors and pulse stretchers. - + +IN + + -IN + + AV1 + - AV2 OUT - + - GND Figure 1. LT1720 block diagram Circuit Description The block diagram of one comparator in the LT1720 is shown in Figure 1. There are differential inputs (+IN/ -IN), an output (OUT), a single positive supply (VCC) and ground (GND). The two comparators are completely independent, sharing only the power and ground pins. The circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary common-emitter out- Table 1. Typical LT1720 specifications, TA = 25C Parameter Conditions Value Propagation Delay Overdrive = 20mV 4.5ns Propagation Delay Overdrive = 5mV 7ns Supply Current VCC = 5V 4mA per Comparator Supply Voltage Full Temperature Range Limits 2.7V to 6V Input Voltage Range Full Temperature Range Limits -0.1V to (VCC - 1.2V) Input Offset Voltage VCC = 5V, VCM = 1V 1mV Input-Referred Hysteresis VCC = 5V, VCM = 1V 3.5mV Output Voltage (Low) ISINK = 10mA 0.4V Max Output Voltage (High) ISOURCE = 4mA (VCC - 0.4V) Min 10 VCC + put stage. All of the internal signal paths utilize low voltage swings for high speed at low power. The input stage topology maximizes the input dynamic range available without requiring the power, complexity and die area of two complete input stages such as are found in railto-rail input comparators. With a 2.7V supply, the LT1720 still has a respectable 1.6V of input common mode range. The differential input voltage range is rail-to-rail, without the large input currents found in competing devices. The input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the -100mV common mode voltage limit. The internal hysteresis is implemented by positive, nonlinear feedback around a second gain stage. Until this point, the signal path has been entirely differential. The signal path is then split into two drive signals for the upper and lower output transistors. The output transistors are connected common emitter for rail-to-rail output operation. The Linear Technology Magazine * November 1998 VOH VHYST (= VTRIP+ - VTRIP-) VHYST/2 VOL VIN = VIN+ - VIN- 0 VTRIP- VOS = VTRIP+ ++V VTRIP - TRIP 2 Figure 2. Hysteresis I/O characteristics Schottky clamps limit the output voltages at about 300mV from the rail, not quite the 50mV or 15mV of Linear Technology's rail-to-rail amplifiers and other products. But the output of a comparator is digital, and this output stage can drive TTL or CMOS directly. It can also drive a host of other loads, as will be demonstrated in the applications below. The bias conditions and signal swings in the output stages are designed to turn their respective output transistors off faster than on. This nearly eliminates the surge of current from VCC to ground that occurs at transitions, keeping the power consumption low even with high output-toggle frequencies. In fact, the internal-frequency-dependent current drain is the equivalent of putting just 15pF on the output. The low surge current also helps keep the LT1720 well behaved in high speed applications. Internal Hysteresis The LT1720 includes internal hysteresis, eliminating the linear region where high speed comparators are most temperamental. The inputoutput transfer characteristic is illustrated in Figure 2, which shows the definitions of VOS and VHYST based upon the two measurable trip points. The 3.5mV (typical) hysteresis band makes the LT1720 well behaved, even with slowly moving inputs. The exact amount of hysteresis will vary from unit-to-unit; the LT1720 specifications include both upper and lower limits that are guaranteed over Linear Technology Magazine * November 1998 temperature. The hysteresis will also vary slightly with changes in supply voltage and common mode voltage. If a comparator is used to detect a threshold crossing in one direction only, only that trip point is significant. Therefore, a stable offset voltage with an unpredictable level of hysteresis, as seen in many competing comparators, is useless. The LT1720 is many times better than prior comparators in this regard. Figure 3 shows a typical LT1720's input voltages vs supply voltages. The VOS shift is only 320 V, corresponding to a typical PSRR of 80dB. Speed Limits The LT1720 comparators are intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits and internal speed limits. There are no significant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1720 will respond. The output speed is constrained by the slew currents available from the output transistors. To maintain low power quiescent operation, the LT1720 output transistors are sized to deliver 25mA-45mA typical slew currents. This is sufficient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically VCC 2.7V-6V 1MHz-10MHz CRYSTAL (AT-CUT) 2k 220 620 GROUND CASE + OUTPUT 1/2 LT1720 - 2k 0.1F 1.8k Figure 4. Simple 1MHz-10MHz crystal oscillator 3 VTRIP+ VOS AND TRIP VOLTAGE (mV) VOUT DESIGN FEATURES 2 1 VOS 0 -1 -2 -3 2.5 VTRIP- TJ = 25C VCM = 1V 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 1720 G01 Figure 3. The LT1720's hysteresis is insensitive to supply-voltage variations. with heavy capacitive loads. Because the propagation delay (tPD) definition ends at the time the output voltage is halfway between the supplies, the fixed slew current actually makes the LT1720 faster at 3V than 5V with 20mV of input overdrive. The internal speed limits manifest themselves as dispersion. All comparators have some degree of dispersion, defined as a change in propagation delay vs input overdrive. The propagation delay of the LT1720 will vary with overdrive, from a typical of 4.5ns at 20mV overdrive to 7ns at 5mV overdrive (typical). The LT1720's primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. With 5mV of overdrive, the LT1720 is faster with a 5V supply than with a 3V supply, the opposite of what is true with 20mV overdrive. This is due to the internal speed limit, because the gain stage is faster at 5V than 3V due primarily to the reduced junction capacitances with higher reverse voltage bias. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applica11 DESIGN FEATURES VCC 2.7V-6V tions providing low levels of overdrive, the LT1720 is fast enough that the absolute dispersion of 2.5ns (= 7 - 4.5) is small enough to ignore. The gain and hysteresis stage of the LT1720 is simple, short and high speed to minimize dispersion. This internal "self-latch" can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, either in the same comparator, on the supply lines or from the other comparator in the same package. Once a high speed signal trips the hysteresis, the output will respond, after a fixed propagation delay, without regard to these external influences that can cause trouble in nonhysteretic comparators. 1MHz-10MHz CRYSTAL (AT-CUT) 2k 220 620 GROUND CASE + C1 1/2 LT1720 OUTPUT - 100k 2k 0.1F + A1 LT1636 1.8k 0.1F - 1k 0.1F 100k + C2 1/2 LT1720 OUTPUT - Figure 5. Crystal oscillator with complementary outputs and 50% duty cycle Applications Crystal Oscillators Figure 4 shows a simple crystal oscillator using one half of an LT1720. The 2k-620 resistor pair set a bias point at the comparator's noninverting input. The 2k-1.8k-0.1 F path sets the inverting input node at an appropriate DC average level based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the LT1720 will give the correct logic output when one input is outside the common mode range, additional delays may occur when it is so operated, opening the possibility of spurious operating modes. Therefore, the DC bias voltages at the inputs are set near the center of the LT1720's VCC 2.7V-6V 1MHz-10MHz CRYSTAL (AT-CUT) 2k 220 620 + GROUND CASE C1 1/2 LT1720 OUTPUT 0 - OPTIONAL-- SEE TEXT 100k 2k + A1 LT1636 1.3k 0.1F - 0.1F 1k 2.2k 0.1F 100k + C2 1/2 LT1720 OUTPUT 1 - common mode range and the 220 resistor attenuates the feedback to the noninverting input. The circuit will operate with any AT -cut crystal from 1MHz to 10MHz over a 2.7V to 6V supply range. The output duty cycle for the circuit of Figure 4 is roughly 50% but it is affected by resistor tolerances and, to a lesser extent, by comparator offsets and timings. The circuit of Figure 5 creates a pair of complementary outputs with a forced 50% duty cycle. Crystals are narrow-band elements, so the feedback to the noninverting input is a filtered analog version of the square wave output. Changing the noninverting reference level can therefore vary the duty cycle. C1 operates as in the previous example, whereas C2 creates a complementary output by comparing the same two nodes with the opposite input polarity. A1 compares band-limited versions of the outputs and biases C1's negative input. C1's only degree of freedom to respond is variation of pulse width; hence the outputs are forced to 50% duty cycle. This circuit works well because of the two matched delays and rail-to-rail style outputs. Figure 6. Crystal-based nonoverlapping 10MHz clock generator 12 Linear Technology Magazine * November 1998 DESIGN FEATURES switching circuits requiring identical settling times. It cannot adjust the relative phases between the two outputs to be exactly 180 apart because the signal at the input node driven by the crystal is not an exact sinusoid. Q0 2V/DIV Q1 2V/DIV For a number of reasons, the LT1720 is an excellent choice for applications requiring differential timing skew. The two comparators in a single package are inherently well matched, with just 300ps t PD typical. Monolithic construction keeps the delays well matched vs supply voltage and temperature. Crosstalk between the comparators, usually a disadvantage in monolithic duals, has minimal effect on the LT1720 timing due to the internal hysteresis, as discussed earlier. The circuits of Figure 8 show basic building blocks for differential timing skews. The 2.5k resistance interacts with the 2pF typical input capacitance to create at least 4ns delay, controlled by the potentiometer setting. A differential and a single-ended version are shown. In the differential configuration, the output edges can be smoothly scrolled through t = 0 with negligible interaction. AC errors than other semiconductorbased switching technologies. This circuit features 20dB of gain, 10MHz full power bandwidth and 100 V/C baseline uncertainty. Switching delay is less than 15ns and the minimum sampling window width for full power response is 30ns. The input waveform is presented to the diode bridge switch, the output of which feeds the LT1227 wideband amplifier. The LT1720 comparators, triggered by the sample command, generate phase-opposed outputs. These signals are level shifted by the transistors, providing complementary bipolar drive to switch the bridge. A skew compensation trim ensures bridge-drive signal simultaneity within 1ns. The AC balance corrects for parasitic capacitive bridge imbalances. A DC balance adjustment trims bridge offset. The trim sequence involves grounding the input via 50 and applying a 100kHz sample command. The DC balance is adjusted for minimal bridge ON vs OFF variation at the output. The skew compensation and AC balance adjustments are then optimized for minimum AC disturbance in the output. Finally, unground the input and the circuit is ready for use. Fast Waveform Sampler Coincidence Detector Figure 9 uses a diode-bridge-type switch for clean, fast waveform sampling. The diode bridge, because of its inherent symmetry, provides lower High speed comparators are especially suited for interfacing pulse-output transducers, such as particle detectors, to logic circuitry. The matched Timing Skews 10ns/DIV Figure 7, Nonoverlapping outputs of Figure 6's circuit The circuit in Figure 6 shows a crystal oscillator circuit that generates two nonoverlapping clocks by making full use of the two independent comparators of the LT1720. C1 oscillates as before, but with a lower reference level, C2's output will toggle at different times. The resistors set the degree of separation between the output's high pulses. With the values shown, each output has a 44% high and 56% low duty cycle, sufficient to allow 2ns between the high pulses where both are at logic low. Figure 7 shows the two outputs. The optional A1 feedback network shown can be used to force identical output duty. Because the reference level set for C2 is lower than that set for C1, the steady state duty cycles will be 44% rather than 50%. Note, though, that the addition of this network only adjusts the percentage of time each output is high to be the same, which can be important in LT1720 CIN LT1720 + CIN INPUT - CIN DIFFERENTIAL 4ns RELATIVE SKEW 2.5k INPUT - 2.5k CIN + CIN 0ns-4ns SINGLE-ENDED DELAY - CIN + - + CIN CIN VREF VREF Figure 8. Timing-skew generation is easy with the LT1720. Linear Technology Magazine * November 1998 13 DESIGN FEATURES 5V 2.2k 2.2k INPUT 100mV FULL SCALE + OUTPUT 1V FULL SCALE LT1227 1k - 909 100 = 1N5711 = CA3039 DIODE ARRAY (SUBSTRATE TO -5V) AC BALANCE 3pF 5V 1.5k 3.6k 1.1k 1.1k 0.1F + 1/2 LT1720 CIN - SAMPLE COMMAND 2k SKEW COMP 10pF 2.5k 1.1k 1.1k + 1/2 LT1720 - 2k MRF501 MRF501 CIN DC BALANCE 500 11 820 8 680 LM3045 6 9 10 13 820 7 51 51 -5V Figure 9. Fast waveform sampler using the LT1720 for timing-skew compensation delays of a monolithic dual are well suited for those cases where the coincidence of two pulses needs to be detected. The circuit of Figure 10 is a coincidence detector that uses an LT1720 and discrete components as a fast AND gate. The reference level is set to 1V, an arbitrary threshold. Only when both input signals exceed this will a coincidence be detected. The Schottky diodes from the comparator outputs to the base of the MRF-501 form the AND gate, while the other two 14 Schottkys provide for fast turn-off. A logic AND gate could instead be used, but would add considerably more delay than the 300psec contributed by this discrete stage. This circuit can detect coincident pulses as narrow as 2.5ns. For narrower pulses, the output will degrade gracefully, responding, but with narrow pulses that don't rise all the way to high before starting to fall. The decision delay is 4.5ns with input signals 50mV or more above the reference level. This circuit creates a TTL compatible output but it can typically drive CMOS as well. Pulse Stretcher For detecting short pulses from a single sensor, a pulse stretcher is often required. The circuit of Figure 11 acts as a one-shot, stretching the width of an incoming pulse to a consistent 100ns. Unlike a logic one-shot, this LT1720-based circuit requires only 100pV-s of stimulus to trigger. The circuit works as follows: Comparator C1 functions as a threshold Linear Technology Magazine * November 1998 DESIGN FEATURES The new LT1720 dual 4.5ns singlesupply comparators feature high speeds and low power consumption. They are versatile and easy-to-use building blocks for a wide variety of system design challenges. 1 See Linear Technology Application Note 47, Appendix B. This circuit can detect the output of the pulse generator described after 40dB of attenuation. Authors can be contacted at (408) 432-1900 Linear Technology Magazine * November 1998 5V 300 + MRF501 (GROUND CASE LEAD) 1/2 LT1720 51 - 3.9k 5V OUTPUT 1k - 0.1F 1/2 LT1720 + 4x 1N5711 300 51 300ps AND GATE COINCIDENCE COMPARATORS Figure 10. A 2.5ns coincidence detector 5V 0.01F 15k - OUTPUT C1 1/2 LT1720 PULSE SOURCE + 50 51 100ns 24 6.8k R 1k C 100pF 1N5711 C2 1/2 LT1720 + Conclusion 5V - detector, whereas comparator C2 is configured as a one-shot. The first comparator is prebiased with a threshold of 8mV to overcome comparator and system offsets and establish a low output in the absence of an input signal. An input pulse sends the output of C1 high, which in turn latches C2's output high. The output of C2 is fed back to the input of the first comparator, causing regeneration and latching both outputs high. Timing capacitor C now begins charging through R and, at the end of 100ns, C2 resets low. The output of C1 also goes low, latching both outputs low. A new pulse at the input of C1 can now restart the process. Timing capacitor C can be increased without limit for longer output pulses. This circuit has an ultimate sensitivity of better than 14mV with 5ns-10ns input pulses. It can even detect an avalanche generated test pulse of just 1ns duration with sensitivity better than 100mV. 1 It can detect short events better than the coincidence detector above because the one-shot is configured to catch just 100mV of upward movement from C1's VOL, whereas the coincidence detector's 2.5ns specification is based on a full, legitimate logic high. 2k 2k 2k Figure 11. A 1ns pulse stretcher for the latest information on LTC products, visit www.linear-tech.com 15 DESIGN FEATURES 250MHz RGB Video Multiplexer in Space-Saving Package Drives Cables, Switches Pixels at 100MHz by John Wright and Frank Cox Dense Process Yields One of the first products from LTC's Big Performance from new proprietary high speed bipolar Tiny PC Board Space Introduction process is a 250MHz RGB (red, green, blue) multiplexer that is optimized for switching speed and makes excellent use of the new complementary 6GHz transistors. This new MUX, the LT1675, is designed for pixel switching in video graphics and for RGB routing. It is configured with three SPDT (single pole, double throw) RGB video switches and three current feedback amplifiers for direct driving of cables. The new RGB MUX is similar to the LT1203/LT1205 video switches combined with the LT1260 triple CFA, but with greatly enhanced performance in far less space. The boost over the older configuration is a factor of five in switching speed and a factor of 2.5 in bandwidth, while the PCB footprint is reduced by more than five. This "juiced" performance is accomplished with one-third less supply current than required by the equivalent multichip design. RED 1 One advantage of the dense, high speed bipolar process is that it results in a reduced die size for the LT1675, even though it has well over 300 active devices. The benefit to the user is that the LT1675 comes in a small 16-pin SSOP package, which is the same size as an SO-8. To enhance the small PC board theme, the LT1675 is configured for a fixed gain of two, eliminating six external gain setting resistors. The fixed gain of two in the CFA is ideal for driving double terminated 50 or 75 cables. Additionally, stray PCB capacitance on the sensitive feedback node is no longer a problem. Figure 1 shows a typical application switching between two RGB sources and driving 75 cables. In contrast, some competitive solutions are housed in bulky 24-pin, wide-SO packages and draw significantly more supply current. 0V 1V RED OUT PIN 15 0V 2ns/DIV Figure 2. Select pin switches inputs at 100MHz. RED 1 = 0V, RED 2 = 1V, RL = 100, 10pF scope probe; measured between 50 back termination and 50 load 3V SELECT LOGIC PIN 10 0V RED OUT PIN 15 50mV 0V 5ns/DIV Figure 3. Input-referred switching transient. RL = 150, 10pF scope probe V+ +1 75 75 CABLE +2 VOUT RED +1 GREEN 1 75 +1 BLUE 1 n .. . 75 75 750 CABLE +2 75 OFF 750 VOUT GREEN 75 75 +1 RED 2 75 CABLE VOUT BLUE +2 75 750 R1 75 750 SELECT RGB1/RGB2 +1 OFF V- 75 BLUE 2 Figure 1. LT1675 typical application: switching between two RGB sources and driving three cables R1 75 1575 n-1 R2 75 CABLE ON 750 ENABLE 75 75 750 75 +1 GREEN 2 16 3V SELECT LOGIC PIN 10 R2 75 n = NUMBER OF LT1675s IN PARALLEL 1675 F05 1675 TA01 Figure 4. Each off channel loads the cable termination with the 1575. Linear Technology Magazine * November 1998 DESIGN FEATURES Expanding Inputs Does Not Increase Power Dissipation R1 AV = 2 75 R2 ENABLE LT1675 #1 R3 AV = 2 75 RED OUT 75 R4 ENABLE LT1675 #2 1675 F06 CHIP SELECT 74HC04 Figure 5. Two LT1675s build a 4-input RGB router. The LT1675's internal switches change state in less than 1ns but the output of the MUX switches in 2.5ns. This increased time is due to the finite bandwidth of the current feedback amplifier that drives the cable. To toggle at 100MHz, as shown in Figure 2, implies a pixel width of 5ns; accomplishing this requires a slew rate in excess of 1000V/ s. In Figure 2, the Select pin (pin 10) is driven from a sine wave generator, since only crossings of the logic threshold are required. The fast current steering breakbefore-make SPDT tee switches minimize switching glitches. The switching transients of Figure 3, measured between the 75 back termination and the 75 load, show what the monitor receives. The glitch is only 50mVp-p, the duration is only 5ns and nature of this transient is small and fast enough to not be visible even on quality graphics terminals. Additionally, the break-before-make SPDT switch is open before the alternate channel is connected, which means there is no input feedthrough or crosstalk during switching. In video routing applications, where the ultimate in speed is not mandatory, as it is in pixel switching, it is possible to expand the number of MUX inputs by shorting the LT1675 outputs together and switching with the ENABLE pins. This technique does not increase the power dissipation because LT1675s draw virtually zero current when disabled. The internal gain-set resistors have a nominal value of 750 and cause a 1500 shunt across the 75 cable termination. Figure 4 shows schematically the effect of expanding the number of inputs. The effect of this loading is to cause a gain error that can be calculated by the following formula: 0V 1V RED OUTPUT 0V Figure 6. Square wave response: chip select = 0V, IC 2 disabled 5V CHIP SELECT 0V RED OUTPUT 0V GAIN ERROR (dB) = ( || ( 1575 75 n-1 dB 6dB + 20log 1575 75 + 75 n-1 || where n is the total number of LT1675s. For example, using ten LT1675s (20 red, 20 green, 20 blue) the gain error is only -1.7dB per channel. Figure 5 shows a 4-input RGB router. The response from red 1 input to red output is shown in Figure 6, for Figure 7. Toggling the 4-input router: Red 1 input = 0V; Red 3 input = uncorrelated sine wave a 25MHz square wave with Chip Select = 0V. In this example, the gain error is just -0.23dB. The response to toggling between IC1 and IC2 with Chip Select is shown in Figure 7. In this case red 1 input is connected to 0V, and red 3 is connected to an uncorrelated sine wave. continued on page 20 Table 1. LT1675 performance, VS = 5V Parameter Conditions Typical Values -3dB Bandwidth RL = 150 250MHz 0.1dB Gain Flatness RL = 150 70MHz Crosstalk Between Active Channels at 10MHz -60dB Slew Rate RL = 150 1100V/s Differential Gain RL = 150 0.07% Differential Phase RL = 150 0.05 Channel Select Time RL = 150 ,VIN = 1V 2.5ns Enable Time RL = 150 10ns Output Voltage Swing RL = 150 3V Gain Error RL = 150 ,VIN = 1V 4% Output Offset Voltage Supply Current Supply Current Disabled Linear Technology Magazine * November 1998 1V RED 1 INPUT 20mV All Three Channels Active 30mA 1A 17 DESIGN FEATURES LT1468: An Operational Amplifier for Fast, 16-Bit Systems by George Feliz Introduction The LT1468 is a single operational amplifier that has been optimized for accuracy and speed in 16-bit systems. Operating from 15V supplies, the LT1468 in a gain of -1 configuration will settle in 900ns to 150 V for a 10V step. The LT1468 also features the excellent DC specifications required for 16-bit designs. Input offset voltage is 75 V max, input bias current is 10nA maximum for the inverting input and 40nA maximum for the noninverting input and DC gain is 1V/V minimum. The LT1468 specifications are summarized in Table 1. Two key applications that illustrate its use are current-to-voltage (I/V) conversion following a fast, 16-bit current output digital-to-analog converter (DAC), such as LTC1597 (Figure 1), and buffering the input of an analog-to-digital converter (ADC), such as the 333ksps LTC1604 (Figure 2). Both applications will be discussed in detail to highlight the LT1468 design requirements and trade-offs. and concluding in this issue of Linear Technology magazine and, in greater detail, in Linear Technology Application Note 74. Minimizing settling time is limited by the need to null the DAC output capacitance, which varies from 70pF to 115pF, depending on code. This capacitance at the amplifier input combines with the feedback resistor to form a zero in the closed-loop frequency response in the vicinity of 200kHz-400kHz. Without a feedback capacitor, the circuit will oscillate. The choice of 20pF stabilizes the circuit by adding a pole at 1.3MHz to limit the frequency peaking and is chosen to optimize settling time. The settling time to 16-bit accuracy is theoretically bounded by 11.1 time constants set by the 6k and 20pF. Figure 1's circuit settles in 1.7 s to 150 V for a 10V step. This compares favorably with the 1.33 s theoretical limit and is the best result obtainable with a wide variety of LTC and competitive amplifiers. This excellent settling requires the amplifier to be free of thermal tails in its settling behavior. The LTC1597 current output DAC is specified with a 10V reference input. The LSB is 25.4nA, which becomes 153 V after conversion by the LT1468, and the full-scale output is 1.67mA, which corresponds to 10V at the amplifier output. The zeroscale offset contribution of the LT1468 is the input offset voltage and the 16-Bit DAC Current-to-Voltage Converter with 1.7s Settling Time The key AC specification of the circuit of Figure 1 is settling time as it limits the DAC update rate. The settling time measurement is an exceptionally difficult problem that has been ably addressed by Jim Williams, beginning in the August 1998 issue 10V 16 15V 20pF VREF 6k DAC INPUTS - OPTIONAL NOISE FILTER 2k LTC1597 DAC COUT 70pF-115pF + 50pF -15V 1LSB = 25.4nA FULL SCALE = 1.67mA 153V 10V Figure 1. 16-bit DAC I/V converter with 1.7s settling time 18 VOUT LT1468 Table 1. LT1486 key specifications Input Offset Voltage 75V Max Inverting Input Bias Current 10nA Max Noninverting Input Bias 40nA Max Current DC Gain 1V/V Min CMRR 96dB Min Input Noise Voltage 5nV/ Hz Input Noise Current 0.6pA/ Hz Gain Bandwidth 90MHz Slew Rate 22V/s -96.5 dB THD for 10VP-P, 100kHz DAC Settling Time to 150V, 1.7s 10V Step (Figure 1's Circuit) AV = -1 Settling Time to 900ns 150V, 10V Step Supply Current, VS = 15V 5.2mA Max inverting input current flowing through the 6k feedback resistor. This worst-case total of 135V is less than one LSB. At full-scale there is an insignificant additional 10V of error due to the 1V/V minimum gain of the amplifier. The low input offset of the amplifier ensures negligible degradation of the DAC's outstanding linearity specifications. With its low 5nV/Hz input voltage noise and 0.6pA/Hz input current noise, the LT1468 contributes only an additional 23% to the DAC output noise voltage. As with any precision application, and particularly with wide bandwidth amplifiers, the noise bandwidth should be minimized with an external filter to maximize resolution. ADC Buffer The important amplifier specifications for an analog-to-digital converter buffer application (Figure 2) are low noise and low distortion. The LTC1604 16-bit ADC signal-to-noise ratio (SNR) Linear Technology Magazine * November 1998 DESIGN FEATURES VIN 80 60 PHASE + LT1468 LTC1604 - ADC OUTPUTS 3000pF -15V -5V 530kHz NOISE FILTER 50 60 40 40 20 30 GAIN 20 0 10 -20 0 -40 Figure 2. ADC buffer -10 10k of 90dB implies 56 VRMS noise at the input. The noise for the amplifier, 100/3000pF filter and a high value 10k source is 15 V RMS , which degrades the SNR by only 0.3dB. The LTC1604 total harmonic distortion (THD) is a low -94dB at 100kHz. The buffer/filter combination alone has 2nd and 3rd harmonic distortion better than -100dB for a 5VP-P, 100kHz input, so it does not degrade the AC performance of the ADC. The buffer also drives the ADC from a low source impedance. Without a buffer, the LTC1604 acquisition time increases with increasing source resistance above 1k and therefore the maximum sampling rate must be reduced. With the low noise, low distortion LT1468 buffer, the ADC can be driven at maximum speed from higher source resistances without sacrificing AC performance. The DC requirements for the ADC buffer are relatively modest. The input offset voltage, CMRR (96dB minimum) and noninverting input bias current through the source resistance, RS, affect the DC accuracy, but these errors are an insignificant fraction of the ADC offset and fullscale errors. Circuit Description A simplified schematic of LT1468 is shown in Figure 3. The circuit is a single, folded-cascode gain stage for fast settling and high bandwidth. The inputs are PNP transistors Q1 and Q2 with bias current cancellation from current source I7-Q12 to match Q1 and Q2, and the current mirror composed of Q13, Q14 and Q15. I7 is trimmed to minimize the inverting input current (critical for errors in DAC I/V circuits). The input devices are protected by 100 resistors and back-to-back diodes D1 and D2. The collectors of Q1 and Q2 are loaded by current sources I3 and I4 and the emitters of cascode transistors Q3 and Q4. I3 and I4 are trimmed to null the input offset voltage. The mirror formed by Q5 and Q6 performs differential-to-single ended conversion into the high gain node at the collectors of Q4 and Q6. To increase the gain of this single stage, V+ I5 350A I2 400A I7 50A 2mA I1 100A C2 10pF Q10 2k 1k 2k Q8 D1 100 Q7 Q1 +IN Q2 -IN C1 4pF D2 Q4 BIAS Q12 Q13 Q15 Q14 Q11 100 Q3 I6 350A I3 150A I4 150A V- Figure 3. LT1468 simplified schematic Linear Technology Magazine * November 1998 OUT Q9 Q6 Q5 PHASE (DEGREES) 16 100 GAIN (dB) RS 100 70 5V 15V 100k 1M 10M FREQUENCY (Hz) -60 100M 1418_02a.EPS Figure 4. LT1468 gain and phase vs frequency the Q5-Q6 mirror is bootstrapped by follower Q7 and current source I2 so that the mirror floats with the output level. With this scheme, Q6 never sees a change in base-collector voltage and does not degrade the gain with its output impedance, which is a factor of 5-10 lower than that of NPNs Q3 and Q4. By choosing I2 so that Q7 runs at twice the collector current of Q5-Q6, the base current of Q7 balances the combined base currents of Q5 and Q6. A benefit of this balanced design is low offset voltage drift (2 V/C maximum). The output stage is formed by Q8, Q9, Q10 and Q11 and current sources I5 and I6. This stage further buffers the gain node from the output. The path from the emitter of Q7 to the output has symmetrical current gain, as it contains both an NPN and PNP, whether sourcing or sinking current. This balance reduces 2nd harmonic distortion. Frequency compensation is set by capacitor C1 on the gain node for a 90MHz gain bandwidth at 100kHz. Capacitor C2 rolls off the mirror gain, which produces a pole-zero pair so that the open-loop response reaches unity gain at 25MHz with 42 of phase margin. C2 is bootstrapped to the output so that it does not degrade slew rate. The gain and phase versus frequency are shown in Figure 4. Slew rate is set by I1 and C1 and is typically 22V/ s. Design Trade-Offs Previous precision designs had multiple gain stages and highly balanced configurations. The price paid by these classic designs is lack of 19 DESIGN FEATURES 100 TOTAL NOISE VOLTAGE (nV/Hz) bandwidth, slew rate and settling time. The LT1468 uses a single stage topology to obtain excellent AC specifications with high bandwidth and state-of-the-art 16-bit settling. The demands of precision dictate a fully balanced design and painstaking care in the die layout. The AC performance is ultimately limited, however, by the need for high gain and low input bias current. High gain requires bootstrapping the current mirror in the signal path, which degrades phase margin at high frequency. For this reason the mirror is compensated to lower the unity-gain frequency of the amplifier, which reduces bandwidth at low closed-loop gains. To obtain low input bias current, the choice of operating currents is limited by the accuracy of the input bias current cancellation circuitry. With trimming, up to a 50x reduction VS = 15V TA = 25C f = 10kHz TOTAL NOISE 10 RESISTOR NOISE ONLY 1 RS + - 0.1 100 1k 10k SOURCE RESISTANCE, RS () 100k 1468_05.eps Figure 5. Total noise vs unmatched source resistance increase in noise is due to the resistor (Figure 5). It should be noted that the input bias current cancellation current is not bootstrapped to the input stage to provide constant IB vs input common mode voltage. The reason is simple: this circuitry runs at submicroamp current levels and has no chance of settling if it is allowed to move with the inputs. The IB is optimized for inverting configurations with a constant input voltage and provides excellent settling. Conclusion in IB can be achieved. This constraint sets the maximum value of current source I1, which also places limits on bandwidth, slew rate, noise voltage and noise current. The LT1468 total noise is best with source resistance in the 1k to 20k region, where any The LT1468 has an unequaled blend of speed and precision that is ideal for 16-bit applications. Its unique virtues also provide outstanding performance in low distortion active filters and precision instrumentation. Authors can be contacted at (408) 432-1900 LT1676/LT1776, continued from page 9 discrete pulses. The output capacitor must supply the entire load current for at least a portion of the switching cycle, so output capacitor ripple current rating and ESR may be an issue. Maximum available output current will usually be a strong function of input voltage. Supporting low VIN-toVOUT ratios may require additional components for maintaining control- loop stability. A detailed theoretical analysis of this topology and its behavior can be found in Linear Technology Application Note 44. Conclusion The LT1676 and LT1776 provide excellent efficiency in high input voltage/ low output voltage switching regulator applications. This LT1776's 8-pin SO package and 200kHz switching rate are especially useful in implementing compact power supply solutions. These devices' innate ability to avoid pulse skipping under light loads, plus the optional sync function, aid in controlling the frequency spectrum of switching-generated noise. LT1675, continued from page 17 Performance Conclusion By taking full advantage of LTC's new complementary high speed bipolar process, the LT1675 RGB multiplexer dramatically raises the level of per- 10 CROSSTALK REJECTION (dB) Table 1 summarizes the major perfor mance specifications of the LT1675; Figure 8 shows a graph of crosstalk. 20 0 -10 RS = 75 RL = 150 GREEN 1 DRIVEN RED 1 SELECTED -20 -30 -40 -50 -60 -70 -80 100k 1M 10M 100M FREQUENCY (Hz) 1G formance while saving PC board space. A channel-to-channel toggle rate of 100MHz makes the LT1675 perfect for pixel switching and the simple expansion feature using the ENABLE pin is ideal for RGB routing. A fixed gain of two for driving double terminated cables simplifies PC board layout and boosts performance. These high per formance multiplexers complement the large number of video products offered by LTC. 1418_02a.EPS Figure 8. LT1675 crosstalk rejection vs frequency 20 Linear Technology Magazine * November 1998 DESIGN FEATURES LTC1622: Low Input Voltage, Current Mode PWM Buck Converter by San-Hwa Chee Introduction 750kHz. High frequency operation allows the use of small inductors, making this part ideal for communications products. The LTC1622 comes in a tiny 8-lead MSOP package, providing a complete power solution while occupying only a small area. The LTC1622 uses a pulse-width, current mode architecture, which provides excellent AC and DC load and line regulation. Peak inductor current is set by an external sense resistor. This allows the design to be optimized for each application. A softstart pin allows the LTC1622 to power up gently. A Detailed Look at the LTC1622 The LTC1622 is a constant-frequency, pulse-width-modulated, current mode switching regulator. In normal operation, the external P-channel power MOSFET is turned on during each cycle when the oscillator sets a latch and turned off when the current comparator resets the latch. The peak inductor current at which the current comparator resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, gm. An external resistive divider connected between VOUT and ground allows gm to receive an output feedback voltage, VFB. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which, in turn, causes the ITH voltage to increase until the average inductor current matches the new load current. (For a more detailed description, please refer to the LTC1622 data sheet.) The value of the RSENSE is chosen based on the required output current. The LTC1622 current comparator has a maximum threshold of 100mV/ R SENSE . The current-comparator threshold sets the peak of the inductor current, yielding a maximum average output current equal to the peak value minus one-half the peakto-peak inductor ripple current. For applications where the duty cycle is 100 90 EFFICIENCY (%) The push for 2.5V system supplies continues unabated as manufacturers introduce more parts that operate at this low voltage. The rewards are great, especially for battery-powered equipment, since the lower voltage reduces power consumption and thereby extends the time between battery replacements or recharges. With a 2.5V system supply, operation from a single lithium-ion battery becomes highly attractive, because its end-of-charge voltage is 2.7V and it has the most energy per volume compared to NiCd and NiMH. The 8-pin LTC1622 step-down DC/ DC controller is designed to help system designers harness all of the available energy from lithium-ion batteries in several ways. Its wide operating input-voltage range (2.0V to an absolute maximum of 10V) and 100% duty cycle allows low dropout for maximum energy extraction from the battery. The part's low quiescent current, 400 A, with a shutdown current of 15 A, extends battery life. Its user-selectable Burst Mode operation enhances efficiency at low load current. For portable applications where board space is a premium, the LTC1622 operates at a constant frequency of 550kHz and can be synchronized to frequencies of up to VIN = 4.2V VIN = 3.3V 80 VIN = 8.4V 70 VIN = 6V 60 VOUT = 2.5V RSENSE = 0.03 50 40 0.001 0.100 0.010 LOAD CURRENT (A) 1.000 Figure 2. Efficiency vs load current for Figure 1's circuit (Burst Mode enabled) 100 VIN = 4.2V R2 0.03 VIN = 3.3V VIN 2.5V-8.5V LTC1622 1 SENSE- 7 2 ITH PDRV 6 5 SYNC/MODE GND 3 4 RUN/SS VFB 8 C1 + 10F 16V R1 10k C3 220pF VIN Si3443DV L1 4.7H D1 470pF C1: MURATA CERAMIC GRM235Y5V106Z (814) 236-1431 C2: SANYO POSCAP 6TPA47M (619) 661-6835 L1: MURATA LQN6C-4R7M04 R3 159k + R4 75k D1: IR10BQ015 (310) 322-3331 R2: DALE, 0.25W (605) 665-9301 Figure 1. LTC1622 typical application: 2.5V/1.5A converter Linear Technology Magazine * November 1998 VOUT C2 2.5V/1.5A 47F 6V EFFICIENCY (%) 90 80 70 60 VIN = 8.4V VIN = 6V VOUT = 2.5V RSENSE = 0.03 50 40 0.001 0.010 0.100 1.000 LOAD CURRENT (A) Figure 3. Efficiency vs load current for Figure 1's circuit (Burst Mode disabled) 21 DESIGN FEATURES high (> 80%), the value of the sense resistor is set to approximately 50mV/ IOUTMAX to account for the effect of slope compensation. Under short-circuit conditions, the frequency of the oscillator will be reduced to about 120kHz. This low frequency allows the inductor current to safely discharge, thereby preventing current runaway. The LTC1622 includes protection against output overvoltage conditions or transients. An overvoltage comparator monitors the output voltage and forces the external MOSFET off when the feedback voltage has risen to 8% above the reference voltage (0.8V). necting the SYNC/MODE pin to ground. In this case, constant-frequency operation will be maintained at a lower load current together with lower output ripple. If the load current is low enough, cycle skipping will occur to maintain regulation. Frequency Synchronization The LTC1622 can be externally driven by a clock signal of up to 750kHz. Synchronization is inhibited when the feedback voltage is below 0.3V. This is done to prevent inductor current build-up under short-circuit conditions. Burst Mode operation is inhibited when the LTC1622 is driven by an external clock. Undervoltage Lockout and The LTC1622's Burst Mode operation Dropout Operation Burst Mode Operation is enabled at low load currents simply by connecting the SYNC/MODE pin to VIN or letting it float. In this mode, the minimum peak current of the inductor is set to 0.36V/RSENSE even though the voltage at the ITH pin would indicate a lower value. If the inductor's average current is greater than the load requirement, the voltage at the ITH pin will drop as VOUT rises slightly. When the ITH voltage goes below 0.12V, a sleep signal is generated, turning off the external MOSFET. The load current is now supported by the output capacitor. The LTC1622 will resume normal operation when the ITH voltage goes above 0.22V. For frequency-sensitive applications, Burst Mode operation is inhibited by con- An undervoltage lockout circuit is incorporated into the LTC1622. When the input voltage drops below 2.0V, most of the LTC1622 circuitry will be turned off, reducing the quiescent current from 400 A to several microamperes and forcing the external MOSFET off. The LTC1622 is capable of turning the external P-channel MOSFET on continuously (100% duty cycle) when the input voltage falls to near the output voltage. In dropout, the output voltage is determined by the input voltage minus the voltage drop across the MOSFET, the sense resistor and the inductor resistance. The RUN/SS pin is a dual-function pin that provides the soft-start function and a means to shut down the LTC1622. An internal current source charges an external capacitor. When the voltage on the Run/SS pin reaches 0.65V, the LTC1622 begins operating. As the voltage on the RUN/SS continues to increase linearly from 0.65V to 1.8V, the internal current limit also increases proportionally. The current limit begins at 0A (at VRUN/SS = 0.65V) and ends at 0.10V/ RSENSE (VRUN/SS > 1.8V); therefore, this pin can be used for power supply sequencing. 2.5V/1.5A Step-Down Regulator A typical application circuit using the LTC1622 is shown in Figure 1. This circuit supplies a 1.5A load at 2.5V with an input supply between 2.7V up to 8.5V. The 0.03 sense resistor is selected to ensure that the circuit is capable of supplying 1.5A at a low input voltage. In addition, a sublogic threshold MOSFET is used, since the circuit operates at input voltages as low as 2.7V. The circuit operates at the internally set frequency of 550kHz. A 4.7 H inductor is chosen so that the inductor's current remains continuous during burst periods at low load current. For low output voltage ripple, a low ESR capacitor (100m) is used. OUTPUT VOLTAGE (AC COUPLED) 0.1V/DIV OUTPUT VOLTAGE (AC COUPLED) 0.1V/DIV 0.1ms/DIV Figure 4. Transient response with Burst Mode enabled; load step = 50mA to 1.2A 22 RUN/Soft-Start Pin 0.1ms/DIV Figure 5. Transient response with Burst Mode inhibited; load step = 50mA to 1.2A Linear Technology Magazine * November 1998 DESIGN FEATURES 100 R2 0.03 LTC1622 1 SENSE- 7 2 ITH PDRV 6 5 SYNC/MODE GND 3 4 RUN/SS VFB 8 C1 + 47F 16V R1 22k C3 100pF VIN Si3443DV L1 1.3H D1 470pF R3 159k + EFFICIENCY (%) VIN 2.5V-8.5V VOUT C2 2.5V/1.5A 100F 6V R4 75k C1: AVX TPSD476M016R0150 (803) 946-0362 C2: AVX TPSD476M016R0065 L1: MURATA LQN6C-1R5M04 (814) 237-1431 VIN = 8.4V 70 VIN = 6V 60 40 0.001 Figure 6. 2.5V/1.5A converter with improved transient response for Burst Mode operation than with Burst Mode disabled at 50mA load current. Applications that require better transient response can use the circuit in Figure 6, whose components are selected specifically for this requirement. Figures 7 and 8 show the response with and without Burst Mode operation, respectively. Note that the transient response has been enhanced significantly. However, this comes at the expense of slightly reduced efficiency at low load currents, as indicated by the efficiency curves of Figures 9 and 10. VOUT = 2.5V RSENSE = 0.03 0.010 0.100 LOAD CURRENT (A) 1.000 Figure 9. Efficiency vs load current for Figure 6's circuit (Burst Mode enabled) 100 VIN = 3.3V 90 EFFICIENCY (%) The efficiency curves for Figure 1's circuit are shown in Figures 2 and 3. Figure 2 shows the efficiency with Burst Mode enabled, whereas Figure 3 has Burst Mode defeated. Note that, at low load currents, the efficiency is higher with Burst Mode operation. However, constant frequency operation is still achievable at a lower load currents with Burst Mode operation defeated. The kinks in the efficiency curves indicate the transition out of Burst Mode operation. The components of Figure 1 have been carefully chosen to provide the amount of output power using a minimum of board space. Efficiency is also a prime consideration in selecting the components, as illustrated in Figures 2 and 3. Figures 4 and 5 show the transient response of VOUT with a load step from 50mA to 1.2A. Figure 4 has Burst Mode enabled, while Figure 5 has it defeated. Note that the output voltage ripple (in the middle portion of the photographs) is higher VIN = 3.3V 80 50 D1: IR10BQ015 (310) 322-3331 R2: DALE, 0.25W (605) 665-9301 Efficiency Considerations VIN = 4.2V 90 VIN = 4.2V 80 VIN = 8.4V 70 VIN = 6V 60 VOUT = 2.5V RSENSE = 0.03 50 40 0.001 0.010 0.100 LOAD CURRENT (A) 1.000 Figure 10. Efficiency vs load current for Figure 6's circuit (Burst Mode disabled) Conclusion Although the LTC1622 comes in a tiny 8-pin MSOP, it is packed with features that are not normally found in other DC/DC converters. Its ability to operate from input voltages as low as 2.0V makes it attractive for single lithium-ion battery-powered applications. Features like Burst Mode and 100% duty cycle ensure that energy from the battery is used efficiently and charge is extracted down to the last coulomb. For telecommunications products, where noise generated by a switching regulator may spell trouble, the synchronizable LTC1622 can operate at a constant frequency, making noise a nonissue for system designers. OUTPUT VOLTAGE (AC COUPLED) 0.1V/DIV OUTPUT VOLTAGE (AC COUPLED) 0.1V/DIV 0.1ms/DIV Figure 7. Transient response with Burst Mode enabled; load step = 50mA to 1.2A Linear Technology Magazine * November 1998 0.1ms/DIV Figure 8. Transient response with Burst Mode inhibited; load step = 50mA to 1.2A 23 DESIGN FEATURES LTC1531 Isolated Comparator by Wayne Shumaker Basic Operation The LTC1531 is an isolated, self-powered comparator that receives power and communicates through internal isolation capacitors. The internal isolation capacitors provide 3000VRMS of isolation between the comparator and its output. This allows the part to be used in applications that require high voltage isolated sensing without the need to provide an isolated power source. The isolated side provides a 2.5V pulsed reference output that can deliver 5mA for 100 s using the power stored on the isolated external capacitor. A 4-input, dual-differential comparator samples at the end of the reference pulse and transmits the result back to the nonisolated side. The nonisolated, powered side latches the result of the comparator and provides a zero-cross comparator output for triggering a triac. Typical applications include isolated temperature sensing and control, isolated voltage monitoring and other sensing applications riding on top of high common mode voltages, such as the AC power line. The block diagram in Figure 1 shows the basic components of the LTC1531. The nonisolated powered side toggles between pumping AC voltage through the capacitive barrier to the isolated side, where it is rectified and stored on an external capacitor tied to VPW, and listening for a comparison result. When the isolated-side VPW voltage reaches 3.3V, the comparison circuitry is enabled. On the next listen cycle, the 2.5V VREG output pulses on for 100 s, at the end of which a comparison is done, with the result transmitted back to the nonisolated side. If a valid result is received, the DATA output is updated and the VALID output pulses on for 1ms. When the latched DATA output is high, the zero-cross comparator output is enabled for firing a triac whenever the zero-cross comparator inputs pass through 0V. Figure 2 represents a typical VPW start-up sequence, showing VREG output pulses after VPW reaches 3.3V. Thereafter, whenever V PW reaches 3.3V the comparator samples during the next listen period in the power/ listen cycle. Figure 2 shows typical sampling with light loading on VREG. Sampling is not uniform but depends on the combination of VPW = 3.3V and the 800Hz power/listen cycle. The comparator samples at a typical rate of 200Hz-300Hz. The actual sampling rate depends on the internal and external loading on the 2.5V VREG output and the charging rate to the VRIPPLE VCC = 5V CVPW = 1F IVREG = 5mA 3.3 tSAMPLE 2.5 VPW VPW (V) Introduction VREF 100 0 200 300 TIME (ms) NOTES: VRIPPLE DEPENDS ON CVPW AND IVPW + IVREG tSAMPLE DEPENDS ON IVPW + IVREG 1531 F01 Figure 2. Typical V PW power-up and VREG samples ISOLATION BARRIER POWERED SIDE ISOLATED SIDE VPW 11 VCC V1 18 3.3V DET VCC 1 VOLTAGE PUMP TRANSMIT AND DRIVER VCC VALID 25 + LATCH + DATA 26 Q D VCC V2 17 V3 16 COMPARE - TIMING V4 15 TIMING DECODE 2.5V REG - R POWER-ON RESET VREG 13 ZCDATA 27 CMPOUT 12 GND 28 ZERO-CROSS COMPARATOR 4 3 ZCPOS ZCNEG 2 14 SHDN ISOGND 1531 BD Figure 1. LTC1531 block diagram 24 Linear Technology Magazine * November 1998 DESIGN FEATURES 3.3 VREG (V) 2.5 0 0 10 20 30 TIME (ms) 40 NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE ON VPW > 3.3V AND THE POWER-LISTEN CYCLE SAMPLING 1531 F02 Figure 3. Typical V REG and VPW with IVREG = 100A external capacitor on VPW. This charging rate, through the internal isolation capacitors to VPW, can be modeled as a 100k source resistance and a 5.5V source with V CC = 5V. Figure 4 shows typical sampling periods for different load currents and supply voltages. The sample rate does not depend on the external storage capacitor, whose value should be chosen to minimize ripple on VPW for different VREG loads. VPW can also be used to power continuous, low current circuits, such as the LT1495 op amp or the LTC1540 comparator, provided that such circuits do not prevent VPW from reaching 3.3V. Isolated Comparator The LTC1531 isolated switched capacitor comparator has four inputs that sum the voltages together to perform the following comparison: AC 120V HEATER 25 TECCOR Q4008L4 OR EQUIVALENT NEUTRAL VCC = 4.5V 20 15 VCC = 5.5V 10 VCC = 5V 5 0 0 1 2.5k 5W 3 4 1531 F03 thermistor and a resistor that is driven by the 2.5V VREG output. As the thermistor resistance rises with temperature, the voltage across the thermistor increases. When it exceeds the voltage across R4, the comparator output becomes zero and the triac control to the heater is turned off. Hysteresis can be added in the temperature control by using CMPOUT and R5. A 10 phase-shifted AC line signal is supplied through R1, R2 and C1 to the zero-cross comparator for firing the triac. In the overtemperature detect application in Figure 6, an isolated thermocouple is cold junction compensated with the micropower LT1389 reference and the Yellow Springs thermistor. The micropower LT1495 op amp provides gain to give an overall 0C-200C temperature range, adjustable by changing the 10M feedback resistor. The isolated comparator is connected to compare at 1.25V or ISOLATION BARRIER C1 0.01F 2 IVREG (mA) Figure 4. Typical average tSAMPLE vs IVREG The LTC1531 can be used to isolate sensors such as in the isolated thermistor temperature controller in Figure 5. In this circuit, a comparison is made between the voltages across a R2 47k R1/(R1 + R2) = ATTENUATION R2 * C1 = Tan()/(260Hz) = DESIRED PHASE LAG COMPARISON V1 - V3 > V4 - V2 R = RO * exp (B/T - B/TO) B = 3807 TO = 298K + 390 150 2N2222 OR 2N3904 25 Applications R1 680k IN4004 30 (V1 + V2)/2 > (V3 + V4)/2 By rearranging the equation, for example, a dual differential comparison can be performed: (V1 - V4) > (V3 - V2) or (V1 - V3) > (V4 - V2) The comparator inputs have a railto-rail input range. They sample once at the end of the 100 s VREG pulse. Their summing nature allows midVREG referencing, for example, by connecting V3 to VREG and V4 to ISOGND, which sums together to provide 1.25V for the negative comparator input. In the isolated temperature control application (Figure 5), the comparator is used to compare the voltage across the thermistor to the voltage across R4, with (V1 - V3) > (V4 - V2). The isolated comparator has an isolated output, CMPOUT, which can be used for hysteresis. This output is Hi-Z except when VREG is on; then the output is either 2.5V or 0V, depending on the result of the previous comparison. This output, in combination with the comparator, can be used to create a delta-sigma modulator for transmitting isolated voltage signals across the isolation barrier, as in the isolated voltage sense application (Figure 6). tSAMPLE (ms) VCC = 5V, CVPW = 1F IVREG = 100A VCC SHDN ZC + ZC - LED 1k 1F VPW 2.5V ZCDATA VREG V1 THERM 30k YSI 44008 V2 DATA 5.6V + Q D - + 100F VALID GND V3 V4 CMPOUT LTC1531 ISOGND R5 HYSTERESIS 1M R4 50k 1531 TA01 Figure 5. Isolated thermistor temperature controller Linear Technology Magazine * November 1998 25 DESIGN FEATURES the center of the temperature range. In this case, VTRIP goes high when the temperature exceeds 100C. The LTC1531 can use the high impedance nature of CMPOUT as a duty-cycle modulator, as in the isolated voltage sense application in Figure 7. The duty-cycle output of the comparator is smoothed with the + ISOLATION BARRIER VCC Conclusion LT1490 rail-to-rail op amp to reproduce the voltage at VIN . The output time constant, R2 * C2, should approximately equal the input time constant, 35 * R1 * C1. The factor of 35 results from CMPOUT being on for only 100 s at an average sample rate of 300Hz. The LTC1531 is a versatile part for sensing signals that require large isolation voltages. The ability of the LTC1531 to supply power through the isolation barrier simplifies applications; it can be combined with other micropower circuits in a variety of isolated signal conditioning and sensing applications. 1M LT1389 2.2F 1.74M 10M 2.5V ZCDATA VREG V1 Q D 1.13k 10.7k + VTRIP + 33k LT1495 V2 DATA THERM 30k YSI 44008 10.2k VPW - ZC + ZC - SHDN - VCC V3 - K + V4 VALID GAIN SET FOR 0C TO 200C CMPOUT LTC1531 ISOGND - GND 1531 TA08 UNUSED OP AMP LT1495 COLD JUNCTION COMPENSATES 0C TO 60C OUTPUT, VTRIP = 1 AT 100C RESPONSE TIME = 10 sec RESOLUTION = 4mV 0.5C + Figure 6. Overtemperature detect ISOLATION BARRIER VCC R2 10M RESOLUTION = 4mV SETTLING TIME CONSTANT = 10 sec + VCC C2, 1F SHDN ZC + ZC - 2.5V ZCDATA VCC - VREG VIN 0V TO 2.5V FULL-SCALE INPUT V1 V2 DATA + Q D - V3 V4 VCC LT1490 + VOUT 0V - VCC FULL-SCALE OUTPUT R3 10M 2.2F VPW VALID CMPOUT 10k GND LTC1531 10k ISOGND R1 1M C1 0.22F 1531 TA05 Figure 7. Isolated voltage detect for the latest information on LTC products, visit www.linear-tech.com 26 Linear Technology Magazine * November 1998 DESIGN IDEAS PolyPhase Switching Regulators Offer High Efficiency in Low Voltage, High Current Applications by Craig Varga Introduction What is PolyPhase, Anyway? In recent years, there has been a tendency in the digital world toward smaller device geometries and higher gate counts. This has led to requirements for lower voltages and higher currents for logic supplies. As this trend continues, to levels under 2V and over 30A, the conventional buck regulator approach ceases to be viable. Switch currents are too high for a single device to handle, inductor energy storage exceeds what is avail- Since it is apparent that multiple FETs need to be paralleled to handle the current requirements, the question is whether there is a way to drive them intelligently, rather than by brute force. The solution is to stagger the turn-on times so that the dead bands in the input current waveform are "filled up," so to speak. In the simplest implementation, there are essentially two independent synchronous buck regulators operating 180 able in surface mount technology and ripple current requirements on input capacitors dictate the use of many capacitors in parallel. Although all this may seem like enough of a challenge, the transient response requirements also become much more severe. The question that arises is: "is there a topology that can solve all of these problems simultaneously? " The answer is "PolyPhaseTM." 12V 5V D1 BAW56LT1 R10 10 5V + C22 1F 10V C21 47F 10V CLOCK 5V C28 0.1F 5 4 6 8 12 3 1 C6, 100pF, NPO, 5% 2 9 R6 3.09k 1% AST AST -T +T RET RCC Q Q OSC C3 22F 25V R3 1k U4 10 + Q2 R20 Si4410DY 1 C1 1F 16V U2 7 PVCC2 8 G2 5 SHDN 6 COMP 2 PVCC1 1 G1 4 FB 3 GND C13 180pF R4 1k CX 12V CD4047 C24 1F 16V 12V R32 10 SYNC2 C26 + 22F 25V C29 1F 16V R8 4.3k R30 1k ISENSE2 R31 1k ISENSE1 C38 3300pF C37 3300pF R9 4.3k C30 0.022F 2 3 - 7 + 4 C31 0.022F 8 x 6 1 C16 180pF C7 470F 6.3V R12 10k R24 39k + ETQP1F0R8LB R28 1 C19 6800pF C10 + 470F 6.3V CHARGE PUMP D3 OPTIONAL BAT54 C27, 0.47F ISENSE2 R25 1 Q6 R19 Si4410DY 1 U3 7 PVCC2 8 G2 5 SHDN 6 COMP + C11 470F 6.3V Q1 MMBT3906LT1 C32 470F 6.3V R5 9.76k 1% C18 1000pF 2 PVCC1 1 G1 4 FB 3 GND LTC1430ACS8 C15 1500pF R15 10k C34 1F 10V C35 1F 10V +VOUT 2.5V/30A OUTPUT RTN 5V R16 10 C2 1F 16V + C5 1F 10V +VIN R17 10k, 1% RX RST (POWER FROM 5V) SYNC2 ISENSE1 L2 0.8H Q5 Si4410DY R23 1 LTC1430ACS8 x Q3 Si4410DY Q4 R22 Si4410DY 1 C14 1500pF R14 10k SYNC1 R13 0.002 TRACE R21 1 R1 51 11 13 D4 BAT54 C25 1F 16V SYNC1 CHARGE PUMP OPTIONAL C23 D2 BAT54 0.47F Q7 Si4410DY C12 470F 6.3V + + C33 470F 6.3V C36 1F 10V C8 470F 6.3V L1 0.8H Q8 R26 Si4410DY 1 R27 1 + C4 1F 10V R11 0.002 TRACE ETQP1F0R8LB Q9 Si4410DY R29 1 C20 6800pF C9 + 470F 6.3V R2 9.76k 1% +VIN INPUT RTN C17 1000pF R18 10k 1% R7 51k (4) x U1 LT1006 SHARE AMPLIFIER NOTES: 1. ALL RESISTORS = 5% UNLESS NOTED OTHERWISE. 2. INPUT/OUTPUT CAPACITORS = KEMET T510 SERIES 3. TRACE RESISTORS R11, R13 = 0.1" WIDE x 0.675" LONG (408) 986-0424 Authors can be contacted at (408) 432-1900 Figure 1. 2-phase synchronous buck regulator Linear Technology Magazine * November 1998 27 DESIGN IDEAS 100 80 lel, the actual slew rate is four times that of a single channel design with equal steady-state output ripple current. Both input and output ripple frequencies are double those of a single-channel design, further simplifying filtering requirements. 75 Why Stop at Two? VIN = 5V 95 EFFICIENCY (%) VOUT = 3.3V 90 VOUT = 2V 85 70 VOUT = 2.5V 0 5 10 15 20 CURRENT (A) 25 30 Efficiency of Figure 1's circuit, VINDC201 = F01b 5V out of phase. The net effect of this is that the input and output ripple currents of the two channels tend to cancel during steady-state operation. This results in significant reductions in both input and output capacitor requirements. There is also a fourfold reduction in the total inductor energy storage requirement, which means much smaller inductors and vastly improved transient dynamics. During a large load step, the two channels operate at maximum duty factor in an attempt to maintain the desired output voltage. Both inductor currents slew rapidly and are now additive, since they are going in the same direction. Hence, the slew rate is double what a single channel could do for equal inductor values. However, due to the ripple current cancellation during steady-state conditions, the two inductors can be reduced to approximately one-half the value that a single channel design would require for equal ripple currents. Since during slew they appear to be operating in paral- If two channels are good, aren't more channels better? In a word, yes. In principle, there is no limit to the number of parallel channels that can be added. As the number of channels, n, increases, the ripple frequency increases to n times the single-channel frequency. Input and output RMS ripple currents continue to decrease. Diminishing returns are reached as n rises above three. At three stages, the ripple reductions are very substantial and dynamic performance is excellent. Adding more channels produces slight improvements but the dramatic gains will have been realized by n = 3. The only real penalty is added complexity. Another aspect worth considering is expandability. It is reasonable with today's technology to build a single stage, all surface mount, synchronous buck regulator capable of approximately 15 amps continuous output current. At higher current levels, power dissipation in individual devices becomes difficult to manage. Gate drive capability of driver ICs is somewhat limited and is incapable of driving enough paralleled MOSFETs to handle larger currents at high frequencies. Inductors capable of greater 20mV/DIV energy storage cannot be obtained in surface mount technology. Therefore, if currents substantially greater than 15 amps are required, it is a simple matter of paralleling additional stages to obtain the higher currents. For 30 amps, use two stages. At 45 amps, use three stages and so on. As more stages are added, the ripple currents are further reduced, so there is no need to add large quantities of input or output capacitors to handle the higher current capability. The bottom line is that PolyPhase designs offer a considerable reduction in the cost and volume of the power devices at the expense of a little added complexity in the control circuitry. 2-Phase Design Example The circuit shown in Figure 1 is a 2phase, voltage mode-control, synchronous buck regulator designed for a 5V input and output voltages below 3.3V. It is intended to power large memory arrays, ASICs, FPGAs and the like in server and workstation applications. The output is capable of more than 30 amps continuous at outputs of 2.5V and below, with peak current capability of greater than 40 amps. The design is entirely surface mount and the maximum height above the board is 5.5mm. Overall board area is only 4.24 in2. Efficiency is excellent, as can be seen in the curve in Figure 2. Output ripple voltage is shown in Figure 3. The circuit's dynamic response to a 10 amp load step is shown in Figure 4. The 100mV/DIV V = 160mV VO = 2.5V VIN = 5V 2s/DIV Figure 3. Output ripple with 30A load 28 10s/DIV Figure 4. Transient response with 10A load step (100ns rise time) Linear Technology Magazine * November 1998 DESIGN IDEAS CHANNEL A 5A/DIV 5A/DIV A+B CHANNEL A + B = TOTAL INPUT RIPPLE CURRENT, UNFILTERED CHANNEL A CHANNEL B CHANNEL B 5A/DIV IO = 15A f = 306kHz I O = 25A 2s/DIV Figure 5. Ripple cancellation--input response is dominated by the output capacitor's ESR and shows the output voltage recovered to the original level in under 10s. Figures 5 and 6 show how the input and output ripple currents cancel. Circuit Operation The basic design consists of two LTC1430CS8-based synchronous buck regulators connected in parallel and operated 180 out of phase. U4, the CD4047 oscillator, is used to generate the required clock signals and synchronize the two LTC1430s. Unfortunately, simply connecting two regulators in parallel is a recipe for instant disaster. The output voltages of the two regulators will be slightly different due to normal component tolerances. Therefore, the higher output voltage channel will attempt to supply the full load current, while the lower voltage output will sink current from the output in a desperate attempt to reduce the output voltage to where it thinks it should be. The result is like a dog chasing its tail, with large currents running around in a circle and going nowhere. 2s/DIV Figure 6. Ripple cancellation--output Op amp U1 solves this problem. Because the two channels are identical, if the output currents are the same, the input currents will be also. Low value sense resistors are included in the input power path to allow the circuit to measure input current. U1 then forces the input current of channel two to match the input current of channel one by making small adjustments in channel two's output voltage. It does this by adding or subtracting a small amount of current from channel two's feedback divider. The two sense resistors are short lengths of PCB trace and only need to be ratiometrically accurate. Absolute value of these resistors is not important (see Linear Technology Application Note 69, Appendix A, for a discussion on how to design trace resistors). The only remaining trick in the circuit is the role of Q1 and its associated circuitry. At start-up, the LTC1430's clock frequency is slowed down to approximately 10kHz until the output voltage rises to approximately 50% of the desired level. If, during this start-up phase, an attempt is made to synchronize the controller to a very high frequency, the oscillator ramp amplitude never rises to a level sufficiently high to trip the PWM comparator and enable the FET drivers. Therefore, the output gets stuck on ground. Q1 fixes this by forcing the sync signals high during the turnon transient. Once the output voltage nears its final level, the clock signals are allowed to synchronize the two PWM controllers. Conclusion The design shown combines the performance characteristics that will be required to power the digital systems that will emerge over the next several years. Circuits based on these concepts will be able to efficiently deliver very high current at low voltage while relying on surface mount technology to maintain low profile and minimum use of real estate. They will also provide substantially better dynamic performance than has been available using more conventional design methodologies and do all of this at a reasonable cost. for the latest information on LTC products, visit www.linear-tech.com Linear Technology Magazine * November 1998 29 DESIGN IDEAS Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply by Frank Cox A current feedback (CFA) video amplifier can be made to run off a single supply and still amplify groundreferenced video with the addition of a simple and inexpensive level shifter. The circuit in Figure 1 is an amplifier and cable driver for a current output video DAC. The video can be composite or component but it must have sync. The single positive supply is 12V but could be as low as 6V for the LT1227. The output of the LT1227 CFA used here can swing to within 2.5V of the negative supply with a 150 load over the commercial temperature range of 0C to 70C. Five diodes in the feedback loop are used, in conjunction with C5, to level shift the output to ground. The video from the output of the LT1227 charges C5 and the voltage across it allows the output to swing to ground or even slightly negative. However, the level of this negative swing will depend on the video signal and so will be unpredictable. When the scene is black, there must be sync on the video for C5 to remain charged. A zero-level component video signal with no sync will not work with this circuit. The CFA output will try to go to zero, or as low as it can, and the diodes will turn off. The load will be disconnected from the CFA output and connected through the feedback resistor to the network of R6 and R7. This causes about 150mVDC to appear at the output, instead of the 0V that should be there. The ground-referenced video signal at the input needs to be level shifted into the input common mode range of the LT1227 (3V above negative supply). R4 and R5 shift the input signal to 3V. In the process, the input video is attenuated by a factor of 2.5. For correct gain, no offset and with a zero source impedance, R4 would be 1.5k. To compensate for the presence of R3, R4 is made 1.5k minus R3, or 1.46k. The trade off is a gain error of about 1.5%. If R4 is left 1.5k, the gain is correct, but there is an offset error of 75mV. R6, R7 and R8 set the gain and the output offset of the amplifier. A noninverting gain of five is taken to compensate for the attenuation in the input level shifter and the cable termination. The voltage offset on the output of this circuit is a rather sensitive function of the value of the input resistors. For instance, an error of 1% in the value of R6 will cause an offset of 30mV (1% of 3V) on the output. This is in addition to the offset error introduced by the op amp. Precision resistor networks are available (BI technologies, 714-447-2345) with matching specifications of 0.1% or better. These could be used for the level shifting resistors, although this would make adjustments like the one made to R4 difficult. continued on page 36 12V 5V + 75 VIDEO SOURCE USED FOR TESTING SOURCE C1 10F R1 75 R5 *R2 1k 77.37 FILM + C3 47F C2 4.7F R6 499 C4 0.1F C5 4.7F + B R9 75 - 5x 1N4148 R10 75 A R8 1.5k *R3 38.1 LOAD LT1227 *R4 1.46k R7 1.5k *RESISTORS ARE A COMBINATION OF TWO 1% VALUES, R2 IS A SERIES COMBINATION OF 75 AND 2.37 R3 IS A PARALLEL COMBINATION OF 75 AND 77.3 R4 IS A SERIES COMBINATION OF 1.3k + 160 = 1.46k ALL RESISTORS ARE 1% METAL FILM Figure 1. Amplifier and cable driver for current-output video DAC 30 Linear Technology Magazine * November 1998 DESIGN INFORMATION Component and Measurement Advances Ensure 16-Bit DAC Settling Time (Part Two) by Jim Williams Introduction Reliable measurement of 16-bit DAC settling time is extremely challenging. Part one of this article (in the August 1998 issue of Linear Technology magazine) described a method for making this measurement. This second part discusses detailed circuitry and presents results. Detailed Settling-Time Circuitry Figure 1 is a detailed schematic of the 16-bit DAC settling-time-measurement circuitry. The input pulse DUT LTC1597 BRIDGE DRIVER/RESIDUE AMPLIFIER DELAY COMPENSATION 12ns 5V 15V 0V TO 10V TRANSITION - + LT1236-10 - 15V 50 IN-LINE TERMINATION (SEE TEXT AND NOTES) NC IN - 15V D8 D9 SAMPLING BRIDGE DRIVER GND - 10VREF 47F TANT 510 + - 15V - 5V 1.5k* (SELECT-- SEE TEXT) SAMPLING BRIDGE TEMPERATURE CONTROL SAMPLING BRIDGE + 2.2k 2.2k 10F 0.1F 15V - A3 LT1012 5V 1.1k 15V 10k* A1 LT1220 + 3k** OUT 15pF 0.1F 10k* - SETTLE NODE 3k** AUT LT1468 REF 1k TIME CORRECTED INPUT STEP TO OSCILLOSCOPE CCOMP (SELECT-- SEE TEXT) 5V 15V PULSE GENERATOR INPUT The LT1236 also furnishes the DAC reference, making the measurement ratiometric. The clamped settle node is unloaded by A1, which drives the sampling bridge. Note the additional clamp diodes at A1's output. These diodes prevent any possibility of abnormal A1 outputs (due to lost supply or supply sequencing anomalies) from damaging the diode array. A3 and associated components tem- switches all DAC bits simultaneously and is also routed to the oscilloscope via a delay-compensation network. The delay network, composed of CMOS inverters and an adjustable RC network, compensates the oscilloscope's input step signal for the 12ns delay through the circuit's measur ement path. The DAC amplifier's output is compared against the LT1236-10V reference via the precision 3k summing resistor ratio set. 1k Q5 2N2219 + AC BALANCE 2.5k 7 62 0.01F D5 11 8 - 15V 2 5 14 HEAT + 3 510 1.1k 1 12 13 CA3039 ARRAY 33* D6 470 D7 5pF 8 9 6 560 500 BASELINE ZERO Q4 10 7 51 13 51 0.1F 10F - 5V SAMPLING BRIDGE SWITCHING CONTROL 0.1F 10F SAMPLE DELAY/ WINDOW GENERATOR 5V 1000pF 5V 5.1k 4.7k VCC RC1 C1 Q1 Q2 CLR2 B2 A2 74HC123 680 - 5V + 11 Q3 820 WIDTH 5k Q2 Q1 + : 1N4148 SAMPLING BRIDGE AND TEMPERATURE CONTROL DIODES: HARRIS CA3039M (800) 442-7747 *1% FILM RESISTOR **VISHAY VHD-200, RATIO SET: 10ppm MATCHING D7 TO D9: 1N5711 Q1, Q2: MRF-501 Q3, Q4: LM3045 ARRAY USE IN-LINE COAXIAL 50 TERMINATOR FOR PULSE GENERATOR INPUT. DO NOT MOUNT 50 RESISTOR ON BOARD DERIVE 5V AND - 5V SUPPLIES FROM 15V. USE LT317A FOR 5V, LT1175-5 FOR - 5V CONSTRUCTION IS CRITICAL-- SEE TEXT OUTPUT TO OSCILLOSCOPE 0.01V/DIV = 500V/DIV AT DAC AMPLIFIER OUTPUT 1.3k* SKEW COMP 2.5k - 5V : 74HC04 A2 LT1222 - 4 SENSE RESIDUE AMPLIFIER 3pF 10 A1 B1 CLR1 Q1 Q2 C2 4.7k RC2 GND 470pF 5V 20k DELAY 5.1k 5V AN74 F06 Figure 1. Detailed schematic of DAC-settling-time measurement circuit; optimum performance requires attention to layout. Linear Technology Magazine * November 1998 31 DESIGN INFORMATION A = 10V/DIV A = 10V/DIV B = 10V/DIV B = 10V/DIV C = 10V/DIV C = 500V/DIV D = 500V/DIV 1s/DIV 1s/DIV Figure 2. Settling time circuit waveforms include time-corrected input pulse (Trace A), DAC amplifier output (Trace B), sample gate (Trace C) and settling-time output (Trace D). The sample gate window's delay and width are variable. perature control the sampling diode bridge by comparing a diodes's forward drop to a stable potential derived from the -5V regulator. Another diode, operated in the reverse direction (VZ 7V) serves as a chip heater. The pin connections shown on the schematic have been selected to provide the best temperature-control performance. The input pulse triggers the 74HC123 one shot. The one shot is arranged to produce a delayed (controllable by the 20k potentiometer) pulse whose width (controllable by the 5k potentiometer) sets diode bridge on-time. If the delay is set appropriately, the oscilloscope will not see any input until settling is nearly complete, eliminating overdrive. The sample window width is adjusted so that all remaining settling activity is observable. In this way, the oscilloscope's output is reliable and meaningful data may be taken. The one shot's output Figure 3. Settling time circuit's output (Trace C) with unadjusted sampling bridge AC and DC trims. The DAC is disabled and the settle node grounded for this test. Excessive switch-drive feedthrough and baseline offset are present. Traces A and B are the input pulse and sample window, respectively. is level shifted by the Q1-Q4 transistors, providing complementary switching drive to the bridge. The actual switching transistors, Q1-Q2, are UHF types, permitting true differential bridge switching with less than 1ns of time skew. A2 monitors the bridge output, provides gain and drives the oscilloscope. Figure 2 shows circuit waveforms. Trace A is the input pulse, trace B the DAC amplifier output, trace C the sample gate and trace D the residue amplifier output. When the sample gate goes low, the bridge switches cleanly and the last 1.5mV of slew are easily observed. Ring time is also clearly visible and the amplifier settles nicely to final value. When the sample gate goes high, the bridge switches off, with only 600 V of feedthrough. The 100 V peak before bridge switching (at 3.5 vertical divi- A = 10V/DIV B = 10V/DIV sions) is feedthrough from A1's output, but it is similarly well controlled. Note that there is no off-screen activity at any time--the oscilloscope is never subjected to overdrive. The circuit requires trimming to achieve this level of performance. The bridge temperature control point is set by grounding Q5's base prior to applying power. Next, apply power and measure A3's positive input with respect to the -5V rail. Select the indicated resistor (1.5k nominal) for a voltage at A3's negative input (again, with respect to -5V) that is 57mV below the positive input's value. Unground Q5's base and the circuit will control the sampling bridge to about 55C: 25C ROOM + 57mV 1.9mV/C DIODE DROP = 30C RISE = 55C A = 10V/DIV C = 500V/DIV B = 500V/DIV 1s/DIV Figure 4. The settling time circuit's output (Trace C) with the sampling bridge trimmed. As in Figure 3, the DAC is disabled and the settle node grounded for this test. Switch drive feedthrough and baseline offset are minimized. Traces A and B are the input pulse and sampling gate, respectively. 32 1s/DIV Figure 5. Oscilloscope display with inadequate sample gate delay: the sample window (Trace A) occurs too early, resulting in off-screen activity in the settle output (Trace B). The oscilloscope is overdriven, making displayed information questionable. Linear Technology Magazine * November 1998 DESIGN INFORMATION A = 10V/DIV A = 10V/DIV B = 500V/DIV B = 500V/DIV 1s/DIV 1s/DIV Figure 6. Increasing the sample-gate delay positions the sample window (Trace A) so settle output (Trace B) activity is on-screen. The DC and AC bridge trims are made once the temperature control is functional. Making these adjustments requires disabling the DAC and amplifier (disconnect the input pulse from the DAC and set all DAC inputs low) and shorting the settle node directly to the ground plane. Figure 3 shows typical results before trimming. Trace A is the input pulse, trace B the sample gate and trace C the residue amplifier output. With the DACamplifier disabled and the settle node grounded, the residue amplifier output should (theoretically) always be zero. The photo shows this is not the case for an untrimmed bridge. AC and DC errors are present. The sample gate's transitions cause large, offscreen residue amplifier swings (note residue amplifier's response to the sample gate's turn-off at the 8.5 vertical division). Additionally, the residue amplifier output shows significant DC offset error during the sampling interval. Adjusting the AC balance and Figure 7. Optimal sample-gate delay positions the sampling window (Trace A) so that all settle output (Trace B) information is well inside screen boundaries. skew compensation minimizes the switching induced transients. The DC offset is adjusted out with the baseline zero trim. Figure 4 shows the results after making these adjustments. All switching-related activity is now well on-screen and offset error is reduced to unreadable levels. Once this level of performance has been achieved, the circuit is ready for use. Unground the settle node and restore the input pulse connection to the DAC. Using the Sampling-Based Settling Time Circuit Figures 5 through 7 underscore the importance of positioning the sampling window properly in time. In Figure 5 the sample gate delay initiates the sample window (trace A) too early and the residue amplifier's output (trace B) overdrives the oscilloscope when sampling commences. Figure 6 is better, with only slight offscreen activity. Figure 7 is optimal. A = 5V/DIV All amplifier residue is well inside the screen boundaries. In general, it is good practice to "walk" the sampling window up to the last millivolt or so of amplifier slewing so that the onset of ring time is observable. The sampling based approach provides this capability and it is a very powerful measurement tool. Additionally, remember that slower amplifiers may require extended delay and/or sampling window times. This may necessitate larger capacitor values in the 74HC123 oneshot timing networks. Compensation Capacitor Effects The DAC amplifier requires frequency compensation to get the best possible settling time. The DAC has appreciable output capacitance, complicating amplifier response and making careful compensation capacitor selection even more important. Figure 8 shows effects of very light compensation. A = 5V/DIV B = 500V/DIV B = 500V/DIV 500ns/DIV Figure 8. This settling profile with inadequate feedback capacitance shows underdamped response. Excessive ringing feeds through during the sample gate off-period (third through sixth vertical divisions) but is tolerable (tSETTLE = 2.8s). Linear Technology Magazine * November 1998 500ns/DIV Figure 9. Excessive feedback capacitance overdamps response (tSETTLE = 3.3s). 33 DESIGN INFORMATION Trace A is the time-corrected input pulse and trace B the residue amplifier output. The light compensation permits very fast slewing but excessive ringing amplitude over a protracted time results. The ringing is so severe that it feeds through during a portion of the sample gate off-period, although no overdrive results. When sampling is initiated (just prior to the sixth vertical division) the ringing is seen to be in its final stages, although still offensive. Total settling time is about 2.8 s. Figure 9 presents the opposite extreme. Here, a large value compensation capacitor eliminates all ringing but slows down the amplifier so much that settling stretches out to 3.3s. The best case appears in Figure 10. This photo was taken with the compensation capacitor carefully chosen for the best possible settling time. Damping is tightly controlled and settling time goes down to 1.7 s. A = 5V/DIV Settling Times of Various Amplifiers The previous results, using the LT1468 amplifier, provide extremely fast settling times with high accuracy over temperature. Many applications can tolerate reduced speed, reduced temperature stability or both. Settling times for a number of amplifiers, along with commentary, can be found in LTC Application Note 74, Figure 34. "Optimized" settling times were recorded after individually trimming the feedback capacitors. The "conservative" times represent the worst-case settling times using standard-value compensation capacitors with no trimming. Conclusion B = 500V/DIV 500ns/DIV Figure 10. Optimal feedback capacitance yields a tightly damped signature and the best settling time (tSETTLE = 1.7s). The sampling-based settling-time circuit appears to be a very useful measurement solution. Expanded discussion and tutorial appear in this article's "root" publication: L TC Application Note 74, Component and Measurement Advances Ensure 16Bit DAC Settling Time. Net1 and Net2 Serial Interface Chip Set Supports Test Mode by David Soo Some serial networks use a test mode to exercise all of the circuits in the interface. The network is divided into local and remote data terminal equipment (DTE) and data-circuitterminating equipment (DCE), as shown in Figure 1. Once the network is placed in a test mode, the local DTE will transmit on the driver circuits and expect to receive the same signals back from either a local or remote DCE. These tests are called local or remote loopback. As introduced in the February 1998 issue of Linear Technology, the LTC1543/LTC1544/LTC1344A chip set has taken the integrated approach LOCAL DTE LOCAL DCE LL to multiple protocol. By using this chip set, the Net1 and Net2 design work is done. The LTC1545 extends the family by offering test mode capability. By replacing the 6-circuit LTC1544 with the 9-circuit LTC1545, the optional circuits TM (Test Mode), RL (Remote Loopback) and LL (Local Loopback) can now be implemented. Figure 2 shows a typical application using the LTC1543, LTC1545 and LTC1344A. By just mapping the chip pins to the connector, the design of the interface port is complete. The chip set supports the V.28, V.35, V.36, RS449, EIA-530, EIA-530A or X.21 protocols in either DTE or DCE mode. REMOTE RL DCE REMOTE DTE Shown here is a DCE mode connection to a DB-25 connector. The mode-select pins, M0, M1 and M2, are used to select the interface protocol, as summarized in Table 1. Table 1. Mode pin functions LTC1543/LTC1545 Mode Name M2 M1 M0 Not Used 0 0 0 EIA-530A 0 0 1 EIA-530 0 1 0 X.21 0 1 1 V.35 1 0 0 RS449/V.36 1 0 1 RS232/V.28 1 1 0 No Cable 1 1 1 Figure 1. Serial network 34 Linear Technology Magazine * November 1998 DESIGN INFORMATION C6 C7 C8 100pF 100pF 100pF 3 8 11 12 13 LTC1344A VCC 5V C1 1F C5 1F LTC1543 5 RXD RXC D2 7 R1 9 SCTE R2 10 TXD 11 12 13 NC 14 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 VCC 3 23 16 22 17 21 9 RXD A (104) RXD B RXC A (115) RXC B D3 8 TXC VEE C12 1F 24 D1 6 2 C4 3.3F M0 C2- 27 VEE 26 CHARGE 2 C1+ PUMP 4 VCC 25 1 C1 M1 C2 1F - 21 LATCH VCC DCE/DTE C2 VDD + C3 1F C13 1F + 28 M2 14 3 R3 20 15 19 12 18 24 17 11 16 2 15 14 M0 7 M1 M2 1 VEE DCE/DTE TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101) VCC C10 1F C9 1F 1,19 VCC 2,20 VDD 3 CTS D1 4 DSR VEE GND D2 5 LTC1545 R1 7 DTR R2 R3 9 RI RL R5 18 11 12 13 NC 14 33 32 6 31 22 30 8 29 10 28 20 27 23 CTS A (106) CTS B DSR A (107) DSR B D5 M0 D4ENB M1 M2 R4EN DCD A (109) DCD B DTR A (108) DTR B 4 RTS A (105) 19 RTS B 24 R4 17 TM 5 13 25 D4 10 LL 34 26 8 RTS C11 1F 35 D3 6 DCD DB-25 FEMALE CONNECTOR 36 RI (125)* 23 18 22 21 21 25 LL (141) RL (140) TM (142) 15 16 NC *OPTIONAL: FOR USE WITH DB-26 CONNECTOR DCE/DTE M0 M1 M2 1544 F24 Figure 2. Typical application: Controller-selectable DCE port with DB-25 connector Linear Technology Magazine * November 1998 35 CONTINUATIONS Level Shift, continued from page 30 Fortunately, there is always synchronization information associated with video. A simple circuit can be used to DC restore voltage offsets produced by resistor mismatch, op amp offset or DC errors in the input video. Figure 2 shows the additional circuitry needed to perform this function. The LTC201A analog switch and C1 store the offset error during blanking. The clamp pulse should be 3 s or wider and should occur during blanking. It can conveniently be made by delaying the sync pulse with one shots. If the sync tip is clamped, the clamp pulse must start after and end before the sync pulse or offset errors will be introduced. The integrator made with the LT1632 adjusts the voltage at point B (see Figure 1) to correct the offset. 12V 5V 13 R1 10k C2 6800pF FILM 1/2 LTC201A 3, 14 R3 10k 2, 15 C1 10F FILM R2 10k 12V TO FIGURE 1, POINT A C3 0.1F + 1, 16 4, 5 - R4 1.40k VIDEO R7 10k 1/2 LT1632 5V TO FIGURE 1, POINT B R5 50k HOLD 5V C4 0.1F DC RESTORE LEVEL (ADJUST FOR DESIRED BLANKING LEVEL) 0V SAMPLE R6 20k CLAMP PULSE Figure 2. DC restore subcircuit LTC2400, continued from page 4 configuration, the part performs one conversion, then automatically enters the power-down mode. The duration of the power-down mode is proportional to the capacitor value. While CS is held high, the serial data out pin is high impedance. Once CS is pulled low, the part begins outputting data under the control of the SCLK pin. This device can operate with either an internal or external serial clock. If the SCLK pin is left floating, the LTC2400 automatically detects this state and switches to internal clock mode. If the user drives the SCLK pin with his own clock, the part is automatically switched to external clock mode. Many delta-sigma ADC's on the market include a PGA. These PGAs require that the designer deal with more device pins, status registers and timing sequences. Additionally, they limit the circuit's input range. For example, if the PGA's gain is 256 and the reference is 2.5V the resulting input range is 0mV to 10mV. 36 2.7V-5.5V 60Hz REJECTION 1F LTC2400 VCC 2.5V -300mV TO 2.8V SCLK VIN DOUT GND Conclusion fO VREF CS reduce the board area required by existing designs. } 3-WIRE SPI INTERFACE Figure 8. LTC2400 typical application The LTC2400 provides better noise and TUE (total unadjusted error) performance than previous delta-sigma ADCs; moreover, the user is no longer confined to a 10mV input range. The input can still range between -12.5% x VREF and 112.5% x VREF. The eight MSBs determine the coarse input range. For example, if the eight MSBs = 00h, the input (VIN ) is in the range: 0 < VIN < 10mV, whereas 01h corresponds to 10mV < VIN < 20mV, and so on. This enables the LTC2400 to directly digitize a variety of low level sensors with large offsets. The LTC2400 package is the smallest on the market (SO-8). This tiny chip combined with no external components enables the user to greatly The LTC2400 is the first of a family of delta-sigma converters from LTC. It offers a combination of the best characteristics of delta-sigma converters and conventional converters. Its attributes include latency-free operation and high precision INL, DNL and offset. It frees the user from adding external components and is easy to use. The on-chip sinc4 filter reduces line frequency noise and its harmonics by 120dB, making it ideal for use in noisy environments. With only eight pins, an on-chip oscillator, 24-bit DNL, 4ppm INL and 10ppm TUE, the LTC2400 is the new state of the art in analog-to-digital conversion. Notes: 1.Candy, J.C and G.C. Temes. "Oversampling Methods for A/D and D/A Conversion," in Oversampling Delta-Sigma Data Converters. IEEE Press, 1992. 2. Hauser, Max W. "Principles of Oversampling and A/D Conversion." Journal of the Audio Engineering Society, Vol. 39, No. 1/2 (January/February 1991) pp. 3-26. Linear Technology Magazine * November 1998 NEW DEVICE CAMEOS New Device Cameos LTC1436A/LTC1436A-PLL/ LTC1437A: High Efficiency, PLL-Lockable Switching Regulators The LTC1436A/LTC1436A-PLL/ LTC1437A are high efficiency, low noise, synchronous switching regulators that drive external N-channel power MOSFETs in a phase-lockable, fixed frequency architecture and are ideal for notebook computers and battery-powered equipment requiring high frequency, low duty cycle operation. The LTC1436A/LTC1436A-PLL/ LTC1437A have all of the outstanding features of the LTC1436/LTC1436PLL/LTC1437 with a reduced minimum on-time of 300ns or less and improved noise immunity at low output voltages. With these improvements, high performance can be achieved at output voltages down to 1.3V with operating frequencies in excess of 250kHz and input supply voltages above 22V. As with the originals, the improved parts feature the optional Adaptive PowerTM output stage to provide good low current efficiency while maintaining constant frequency operation by selectively driving two topside N-channel MOSFETs sized for the appropriate load range. An auxiliary low dropout linear regulator is available to generate an additional supply that can be used as a CPU I/O supply or low noise audio supply. A secondary-winding-feedback/burst-disable input guarantees regulation regardless of the primary supply load by forcing continuous operation when needed. Other features include a power-on reset timer that generates a logic-low output signal persisting for 65,536 clock cycles after the output is within 7.5% of the regulated output voltage, low dropout operation (99% duty cycle), a low-battery comparator with open-drain output and a wide supply range for operation from 3.5V to 36V. Linear Technology Magazine * November 1998 The parts are available in 24-lead narrow SSOP for the LTC1436A and LTC1436A-PLL and 28-lead SSOP for the LTC1437A. LTC1625 No RSENSE Controller Now Available in Industrial Temperature Grade An industrial temperature grade version of the LTC1625 No RSENSETM controller is now available for applications that require the enhanced temperature range (-40C to 85C). The LTC1625 provides true current mode control in step-down DC/DC converters without using a sense resistor. A current sense signal is obtained by monitoring the voltage drop across the MOSFET switches, making them perform double duty as current sense elements. Eliminating the sense resistor reduces board area, lowers costs and increases efficiency. Popular features fr om Linear Technology's other controllers have been incorporated, such as fixed frequency operation, N-channel MOSFET drive, Burst ModeTM operation, soft-start and output voltage programming. These features make the LTC1625 an excellent choice for DC/ DC converter designs in a variety of applications that require the highest performance. LTC1694: SMBus Accelerator The LTC1694 is a dual active SMBus pull-up designed to enhance datatransmission speed and reliability under all specified SMBus loading conditions. It consists of two bilevel, hysteretic current source pull-ups that replace the pull-up resistors in a typical SMBus implementation. With the LTC1694, the user can connect multiple SMBus devices or use longer, more capacitive interconnects without compromising slew rates or penalizing bus performance. Resistive pull-ups are used in many communications protocols that employ open-collector or open-drain drivers. Their simplicity is offset by the relatively slow rise times they afford when bus capacitance is high. Rise times can be improved by using lower pull-up resistance values, but the additional current through the low value resistors increases the low state bus voltage, decreasing noise margins. Slow rise times can seriously affect data reliability, enforcing a maximum practical bus speed well below the theoretical SMBus maximum transmission rate. The LTC1694 overcomes these limitations by using bilevel, hysteretic current sources as pull-ups. During positive bus transitions, the current sources provide 2.2mA to quickly slew any parasitic bus capacitance. During negative transitions or steady DC levels, the current sources switch to 275 A to improve negative slew rate and improve low state noise margins. The fast rise times coupled with improved low state logic swings allow maximum transmission speed for any given bus loading conditions. The LTC1694 is available in the 5-lead SOT -23 plastic surface mount package, requiring virtually the same board area as two surface mount resistors. The LTC1694 is specified for operation over the 0C to 70C temperature range. LTC1530: High Power Synchronous Switching Regulator Controller with Current Limit in SO-8 The LTC1530 is a high power, high efficiency switching r egulator controller optimized for 5V buck converter applications. A typical LTC1530 circuit can provide output currents of up to 20A. Packaged in an SO-8, the LTC1530 operates on a single supply of up to 14V. It includes a precision internal reference and an internal feedback system that can provide output voltage regulation of 2% over temperature, load-current and linevoltage shifts. The LTC1530 employs a synchronous switching architecture that drives two external N-channel output devices. It also senses current through the drain-source resistance (or on37 NEW DEVICE CAMEOS resistance) of the upper N-channel MOSFET, eliminating the need for an external, low value sense resistor. The current-limit trip point is set with a single external resistor; a temperature compensation circuit keeps the current-limit level constant as the external MOSFET RDS(ON) increases with temperature. The part also includes an on-chip soft-start capacitor; the soft-start slew rate is 0.4V/ ms. It also has a thermal protection circuit that disables both internal gate drivers and reduces the supply current to 1mA when excessive die temperatures occur. In shutdown mode, the LTC1530 supply current drops to 45 A. LTC1753: Programmable Synchronous Switching Regulator Controller The LTC1753 is a high power, high efficiency, synchronous switching regulator controller that generates a digitally programmable output voltage between 1.3V and 3.5V. Step-down conversion is optimized for a 5V input. The internal 5-bit DAC accepts a parallel word and programs the output voltage from 1.3V to 2.05V in 50mV increments and from 2.1V to 3.5V in 100mV increments. The precision internal reference and feedback system provide an output voltage accuracy of 1.5% at room temperature and 2% (typical) over temperature, load current and line voltage shifts. The LTC1753 uses a synchronous switching architecture with two external N-channel MOSFETs. It provides more than 14A of load current at efficiencies exceeding 90%. The LTC1753 senses output current through the on-resistance of the upper for the latest information on LTC products, visit www.linear-tech.com 38 N-channel FET and provides adjustable current limit without the use of an external sense resistor. External MOSFET power dissipation is considerably reduced under output short-circuit conditions by an over current protection scheme built into the LTC1753. The free-running 300kHz oscillator frequency can be synchronized to a faster clock if desired. Soft-start eases inrush current and recovery from overload conditions. Protection features include overvoltage fault detection, overtemperature detection and a power-good signal when the output voltage is within 5% regulation. The LTC1753 is ideal for high power, tight tolerance microprocessors applications. It is available in 20-pin SO and SSOP packages. The LTC1597/LTC1591: Ultra-accurate, Low Power 16- and 14-Bit Multiplying Current Output DACs Include On-Chip Resistors Expanding LTC's family of current output, multiplying DACs are the pincompatible 16-bit LTC1597 and 14-bit LTC1591. The LTC1597 features true 16-bit performance (DNL and INL, 1LSB maximum), low glitch impulse (2nV-s typical) and low supply power dissipation (10 W typical). The LTC1591 offers the same level of performance at 14-bit resolution. The LTC1597/LTC1591 can be configured for unipolar, 2-quadrant multiplying or for bipolar, 4-quadrant multiplying applications with no external resistors. For a fixed 10V reference input, the DAC unipolar output range is 0V to -10V and the DAC bipolar output range is 10V. The LTC1597, coupled with LT1468 op amp, settles to within 0.0015% of full scale in 2s. The LTC1597/LTC1591 have an asynchronous clear input that resets the output to zero scale. A second pair of parts, the LTC1597-1/LTC1591-1, resets to a midscale output. These devices also have a power-on reset. The LTC1597 and LTC1591 feature 16- and 14-bit parallel input data busses, respectively. The LTC1597 and LTC1591 are designed for applications such as process control and industrial automation, direct digital waveform generation, software-controlled gain adjustment and automatic test equipment. Available in 28-pin SSOP or DIP packages, the LTC1597/LTC1591 operate on single 5V supplies. LTC1258-2.5 Micropower Low Dropout Reference The LTC1258-2.5 is a micropower bandgap reference that combines high accuracy and low drift with very low supply current and small package size. The combination of only 4A quiescent current and low, 200mV Max dropout makes it ideal for battery-powered equipment. This reference uses curvature compensation to obtain a low temperature coefficient and trimmed thin-film resistors to achieve high output accuracy. The reference can supply up to 10mA and sink up to 2mA, making it ideal for precision regulator applications. The LTC12582.5 is stable without an output bypass capacitor, but is also stable with capacitance up to 1 F. This feature is important in critical applications where PC board space is at a premium and fast settling is demanded. This series reference provides supply current and power dissipation advantages over shunt references that must idle the entire load current to operate. The LTC1258-2.5 is available in 8pin SO and MSOP packages. For further information on any of the devices mentioned in this issue of Linear Technology, use the reader service card or call the LTC literature service number: 1-800-4-LINEAR Ask for the pertinent data sheets and Application Notes. Linear Technology Magazine * November 1998 DESIGN TOOLS DESIGN TOOLS Applications on Disk Technical Books FilterCADTM 2.0 CD-ROM -- This CD is a powerful filter design tool that supports all of Linear Technology's high performance switched capacitor filters. Included is FilterViewTM, a document navigator that allows you to quickly find Linear Technology monolithic filter data sheets, the FilterCAD manual, application notes, design notes and Linear Technology magazine articles. It does not have to be installed to run FilterCAD. It is not necessary to use FilterView to view the documents, as they are standard .PDF files, readable with any version of Adobe AcrobatTM. FilterCAD runs on Windows(R) 3.1 or Windows 95. FilterView requires Windows 95. The FilterCAD program itself is also available on the web and will be included on the new LinearViewTM CD. Available at no charge. 1990 Linear Databook, Vol I --This 1440 page collection of data sheets covers op amps, voltage regulators, references, comparators, filters, PWMs, data conversion and interface products (bipolar and CMOS), in both commercial and military grades. The catalog features well over 300 devices. $10.00 Noise Disk -- This IBM-PC (or compatible) program allows the user to calculate circuit noise using LTC op amps, determine the best LTC op amp for a low noise application, display the noise data for LTC op amps, calculate resistor noise and calculate noise using specs for any op amp. Available at no charge SPICE Macromodel Disk -- This IBM-PC (or compatible) high density diskette contains the library of LTC op amp SPICE macromodels. The models can be used with any version of SPICE for general analog circuit simulations. The diskette also contains working circuit examples using the models and a demonstration copy of PSPICETM by MicroSim. Available at no charge SwitcherCADTM -- The SwitcherCAD program is a powerful PC software tool that aids in the design and optimization of switching regulators. The program can cut days off the design cycle by selecting topologies, calculating operating points and specifying component values and manufacturer's part numbers. 144 page manual included. $20.00 SwitcherCAD supports the following parts: LT1070 series: LT1070, LT1071, LT1072, LT1074 and LT1076. LT1082. LT1170 series: LT1170, LT1171, LT1172 and LT1176. It also supports: LT1268, LT1269 and LT1507. LT1270 series: LT1270 and LT1271. LT1371 series: LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377. Micropower SwitcherCADTM -- The MicropowerSCAD program is a powerful tool for designing DC/DC converters based on Linear Technology's micropower switching regulator ICs. Given basic design parameters, MicropowerSCAD selects a circuit topology and offers you a selection of appropriate Linear Technology switching regulator ICs. MicropowerSCAD also performs circuit simulations to select the other components which surround the DC/DC converter. In the case of a battery supply, MicropowerSCAD can perform a battery life simulation. 44 page manual included. $20.00 MicropowerSCAD supports the following LTC micropower DC/DC converters: LT1073, LT1107, LT1108, LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174, LT1300, LT1301 and LT1303. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, Linear Technology makes no representation that the circuits described herein will not infringe on existing patent rights. Linear Technology Magazine * November 1998 1992 Linear Databook, Vol II -- This 1248 page supplement to the 1990 Linear Databook is a collection of all products introduced in 1991 and 1992. The catalog contains full data sheets for over 140 devices. The 1992 Linear Databook, Vol II is a companion to the 1990 Linear Databook, which should not be discarded. $10.00 1994 Linear Databook, Vol III --This 1826 page supplement to the 1990 and 1992 Linear Databooks is a collection of all products introduced since 1992. A total of 152 product data sheets are included with updated selection guides. The 1994 Linear Databook Vol III is a companion to the 1990 and 1992 Linear Databooks, which should not be discarded. $10.00 1995 Linear Databook, Vol IV --This 1152 page supplement to the 1990, 1992 and 1994 Linear Databooks is a collection of all products introduced since 1994. A total of 80 product data sheets are included with updated selection guides. The 1995 Linear Databook Vol IV is a companion to the 1990, 1992 and 1994 Linear Databooks, which should not be discarded. $10.00 1996 Linear Databook, Vol V --This 1152 page supplement to the 1990, 1992, 1994 and 1995 Linear Databooks is a collection of all products introduced since 1995. A total of 65 product data sheets are included with updated selection guides. The 1996 Linear Databook Vol V is a companion to the 1990, 1992, 1994 and 1995 Linear Databooks, which should not be discarded. $10.00 1997 Linear Databook, Vol VI --This 1360 page supplement to the 1990, 1992, 1994, 1995 and 1996 Linear Databooks is a collection of all products introduced since 1996. A total of 79 product data sheets are included with updated selection guides. The 1997 Linear Databook Vol VI is a companion to the 1990, 1992, 1994, 1995 and 1996 Linear Databooks, which should not be discarded. $10.00 1990 Linear Applications Handbook, Volume I -- 928 pages full of application ideas covered in depth by 40 Application Notes and 33 Design Notes. This catalog covers a broad range of "real world" linear circuitry. In addition to detailed, systems-oriented circuits, this handbook contains broad tutorial content together with liberal use of schematics and scope photography. A special feature in this edition includes a 22-page section on SPICE macromodels. $20.00 1993 Linear Applications Handbook, Volume II -- Continues the stream of "real world" linear circuitry initiated by the 1990 Handbook. Similar in scope to the 1990 edition, the new book covers Application Notes 40 through 54 and Design Notes 33 through 69. References and articles from non-LTC publications that we have found useful are also included. $20.00 1997 Linear Applications Handbook, Volume III -- This 976 page handbook maintains the practical outlook and tutorial nature of previous efforts, while broadening topic selection. This new book includes Application Notes 55 through 69 and Design Notes 70 through 144. Subjects include switching regulators, measurement and control circuits, filters, video designs, interface, data converters, power products, battery chargers and CCFL inverters. An extensive subject index references circuits in LTC data sheets, design notes, application $20.00 notes and Linear Technology magazines. 1998 Data Converter Handbook -- This impressive 1360 page handbook includes all of the data sheets, application notes and design notes for Linear Technology's family of high performance data converter products. Products include A/D converters (ADCs), D/A converters (DACs) and multiplexers--including the fastest monolithic 16-bit ADC, the 3Msps, 12-bit ADC with the best dynamic performance and the first dual 12-bit DAC in an SO-8 package. Also included are selection guides for references, op amps and filters and a glossary of data converter terms. $10.00 Interface Product Handbook -- This 424 page handbook features LTC's complete line of line driver and receiver products for RS232, RS485, RS423, RS422, V.35 and AppleTalk(R) applications. Linear's particular expertise in this area involves low power consumption, high numbers of drivers and receivers in one package, mixed RS232 and RS485 devices, 10kV ESD protection of RS232 devices and surface mount packages. Available at no charge Power Solutions Brochure -- This collection of circuits contains real-life solutions for common power supply design problems. There are over 88 circuits, including descriptions, graphs and performance specifications. Topics covered include battery chargers, PCMCIA power management, microprocessor power supplies, portable equipment power supplies, micropower DC/DC, step-up and step-down switching regulators, off-line switching regulators, linear regulators and switched capacitor conversion. Available at no charge Data Conversion Solutions Brochure -- This 64 page collection of data conversion circuits, products and selection guides serves as excellent reference for the data acquisition system designer. Over 60 products are showcased, solving problems in low power, small size and high performance data conversion applications-- with performance graphs and specifications. Topics covered include ADCs, DACs, voltage references and analog multiplexers. A complete glossary defines data conversion specifications; a list of selected application and design notes is also included. Available at no charge Telecommunications Solutions Brochure -- This collection of circuits, new products and selection guides covers a wide variety of products targeted for the telecommunications industry. Circuits solving real life problems are shown for central office switching, cellular phone, base station and other telecom applications. New products introduced include high speed amplifiers, A/D converters, power products, interface transceivers and filters. Reference material includes a telecommunications glossary, serial interface standards, protocol information and a complete list of key application notes and design notes. Available at no charge continued on page 40 39 DESIGN TOOLS, continued from page 39 CD-ROM Catalog LinearView -- LinearViewTM CD-ROM version 3.0 is Linear Technology's latest interactive CD-ROM. It allows you to instantly access thousands of pages of product and applications information, covering Linear Technology's complete line of high performance analog products, with easy-to-use search tools. The LinearView CD-ROM includes the complete product specifications from Linear Technology's Databook library (Volumes I-VI) and the complete Applications Handbook collection (Volumes I-III). Our extensive collection of Design Notes and the complete collection of Linear Technology magazine are also included. A powerful search engine built into the LinearView CDROM enables you to select parts by various criteria, such as device parameters, keywords or part numbers. All product categories are represented: data conversion, references, amplifiers, power products, filters and interface circuits. Up-to-date versions of Linear Technology's software design tools, SwitcherCAD, Micropower SwitcherCAD, FilterCAD, Noise Disk and Spice Macromodel library, are also included. Everything you need to know about Linear Technology's products and applications is readily accessible via LinearView. LinearView runs under Windows 3.1, Windows 95 and Macintosh(R) System 8.0 or later. Available at no charge. World Wide Web Site Linear Technology Corporation's customers can now quickly and conveniently find and retrieve the latest technical information covering the Company's products on LTC's internet web site. Located at www.lineartech.com, this site allows anyone with internet access and a web browser to search through all of LTC's technical publications, including data sheets, application notes, design notes, Linear Technology magazine issues and other LTC publications, to find information on LTC parts and applications circuits. Other areas within the site include help, news and information about Linear Technology and its sales offices. Linear Technology Corporation 1630 McCarthy Boulevard Milpitas, CA 95035-7417 Phone: (408) 432-1900 FAX: (408) 434-0507 Linear Technology Corporation 1080 W. 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The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-1276-677676 FAX: 44-1276-64851 LINEAR TECHNOLOGY CORPORATION 1630 McCarthy Boulevard Milpitas, CA 95035-7417 (408) 432-1900 FAX (408) 434-0507 www.linear-tech.com For Literature Only: 1-800-4-LINEAR Linear Technology Magazine * November 1998