PROFET® BTS 711 L1
Semiconductor Group 1 06.96
Smart Four Channel Highside Power Switch
Features
• Overload protection
• Current limitation
• Short-circuit protection
• Thermal shutdown
• Overvoltage protection
(including load dump)
• Fast demagnetization of inductive loads
• Reverse battery protection1)
• Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
• Open drain diagnostic output
• Open load detection in ON-state
• CMOS compatible input
• Loss of ground and loss of Vbb protection
• Electrostatic discharge (ESD) protection
Application
• µC compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
• All types of resistive, inductive and capacitive loads
• Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin Symbol Function
1,10,
11,12,
15,16,
19,20
Vbb Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
3 IN1 Input 1 .. 4, activates channel 1 .. 4 in case of
5 IN2 logic high signal
7 IN3
9 IN4
18 OUT1 Output 1 .. 4, protected high-side power output
17 OUT2 of channel 1 .. 4. Design the wiring for the
14 OUT3 max. short circuit current
13 OUT4
4 ST1/2 Diagnostic feedback 1/2 of channel 1 and
channel 2, open drain, low on failure
8 ST3/4 Diagnostic feedback 3/4 of channel 3 and
channel 4, open drain, low on failure
2 GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2)
6 GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4)
1)With external current limit (e.g. resistor RGND=150 Ω) in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Product Summary
Overvoltage Protection
V
bb(AZ) 43 V
Operating voltage
V
bb(on) 5.0 ... 34 V
active channels: one
two parallel four parallel
On-state resistance
R
ON 200 100 50 m
Ω
Nominal load current
I
L
(
NOM
)
1.9 2.8 4.4
A
Current limitation
I
L(SCr) 444
A
Pin configuration (top view)
Vbb 1 •20 Vbb
GND1/2 2 19 Vbb
IN1 3 18 OUT1
ST1/2 4 17 OUT2
IN2 5 16 Vbb
GND3/4 6 15 Vbb
IN3 7 14 OUT3
ST3/4 8 13 OUT4
IN4 9 12 Vbb
Vbb 10 11 Vbb
BTS 711 L1
Semiconductor Group 2
Block diagram
Four Channels; Open Load detection in on state;
+ Vbb
IN1
ST1/2 ESD
OUT1
Logic
Voltage
sensor
Voltage
source
Open load
detection 1
Short to Vbb
Level shifter
Temperature
sensor 1
Rectifier 1
Limit for
unclamped
ind. loads 1
Gate 1
protection
Current
limit 1
3
4
V
Logic
Overvoltage
protection
OUT2
Open load
detection 2
Short to Vbb
Level shifter
Temperature
sensor 2
Rectifier 2 Limit for
unclamped
ind. loads 2
Gate 2
protection
Current
limit 2
IN2
5
GND1/2
RR
O1 O2
Charge
pump 1
Charge
pump 2 Channel 2
Channel 1
Signal GND
GND1/2
2
Chip 1
Chip 1
+ Vbb
IN3
ST3/4
PROFET
OUT3
7
8
OUT4
IN4
9
GND3/4
RR
O3 O4
Channel 4
Channel 3
Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
Leadframe
18
17
Load GND
Load
Leadframe
14
13
Load GND
Load
Signal GND
GND3/4
6
Chip 2
Chip 2
Logic and protection circuit of chip 2
(equivalent to chip 1)
Maximum Ratings at
T
j = 25°C unless otherwise specified
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4)
V
bb 43 V
Suppl
y
volta
g
e for full short circuit protection
T
j,start = -40 ...+150°C
V
bb 34 V
BTS 711 L1
Maximum Ratings at
T
j = 25°C unless otherwise specified
Parameter Symbol Values Unit
Semiconductor Group 3
Load current (Short-circuit current, see page 5)
I
Lself-limited A
Load dump protection2)
V
LoadDump =
U
A +
V
s,
U
A = 13.5 V
R
I3) = 2 Ω,
t
d = 200 ms; IN = low or hi
g
h,
each channel loaded with
R
L = 7.1 Ω,
V
Load dump4)60 V
Operating temperature range
Storage temperature range
T
j
T
stg
-40 ...+150
-55 ...+150 °C
Power dissipation (DC)5
T
a = 25°C:
(all channels active)
T
a = 85°C:
P
tot 3.6
1.9 W
Inductive load switch-off ener
gy
dissipation, sin
g
le pulse
Vbb = 12V,
T
j,start = 150°C5),
I
L = 1.9 A, ZL = 66 mH, 0 Ωone channel:
I
L = 2.8 A, ZL = 66 mH, 0 Ω two parallel channels:
I
L = 4.4 A, ZL = 66 mH, 0 Ω four parallel channels:
see diagrams on page 9 and page 10
E
AS 150
320
800
mJ
Electrostatic dischar
g
e capabilit
y
(
ESD
)
(Human Body Model)
V
ESD 1.0 kV
Input voltage (DC)
V
IN -10 ... +16 V
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 8
I
IN
I
ST
±2.0
±5.0 mA
Thermal resistance
junction - soldering point5),6) each channel:
R
thjs 16 K/W
junction - ambient5) one channel active:
all channels active:
R
thja 44
35
2)Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a
150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input
protection is integrated.
3)
R
I = internal resistance of the load dump test pulse generator
4) VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
5)Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 15
6)Soldering point: upper side of solder edge of device pin 15. See page 15
BTS 711 L1
Semiconductor Group 4
Electrical Characteristics
Parameter and Conditions, each of the four channels Symbol Values Unit
at Tj = 25 °C,
V
bb = 12 V unless otherwise specified min typ max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT)
IL = 1.8 A each channel,
T
j = 25°C:
T
j = 150°C:
two parallel channels,
T
j = 25°C:
four parallel channels,
T
j = 25°C:
R
ON -- 165
320
83
42
200
400
100
50
mΩ
Nominal load current one channel active:
two parallel channels active:
four parallel channels active:
Device on PCB5),
T
a = 85°C,
T
j ≤ 150°C
I
L(NOM) 1.7
2.6
4.1
1.9
2.8
4.4
-- A
Output current while GND disconnected or pulled
up; Vbb = 30 V,
V
IN = 0, see diagram page 9
I
L(GNDhigh) -- -- 10 mA
Turn-on time to 90%
V
OUT:
Turn-off time to 10%
V
OUT:
R
L = 12 Ω,
T
j =-40...+150°C
t
on
t
off
80
80 200
200 400
400 µs
Slew rate on
10 to 30%
V
OUT,
R
L = 12 Ω,
T
j =-40...+150°C: d
V
/dton 0.1 -- 1 V/µs
Slew rate off
70 to 40%
V
OUT,
R
L = 12 Ω,
T
j =-40...+150°C: -d
V
/dtoff 0.1 -- 1 V/µs
Operating Parameters
Operating voltage7)
T
j =-40...+150°C:
V
bb(on) 5.0 -- 34 V
Undervoltage shutdown
T
j =-40...+150°C:
V
bb(under) 3.5 -- 5.0 V
Undervoltage restart
T
j =-40...+25°C:
T
j =+150°C:
V
bb(u rst) -- -- 5.0
7.0 V
Undervolta
g
e restart of char
g
e pump
see diagram page 14
T
j =-40...+150°C:
V
bb(ucp) -- 5.6 7.0 V
Undervolta
g
e h
y
steresis
∆
V
bb(under) =
V
bb(u rst) -
V
bb(under) ∆
V
bb(under) -- 0.2 -- V
Overvoltage shutdown
T
j =-40...+150°C:
V
bb(over) 34 -- 43 V
Overvoltage restart
T
j =-40...+150°C:
V
bb(o rst) 33 -- -- V
Overvoltage hysteresis
T
j =-40...+150°C: ∆
V
bb(over) -- 0.5 -- V
Overvoltage protection8)
T
j =-40...+150°C:
I
bb = 40 mA
V
bb(AZ) 42 47 -- V
7) At supply voltage increase up to
V
bb = 5.6 V typ without charge pump,
V
OUT ≈
V
bb - 2 V
8) see also
V
ON(CL) in circuit diagram on page 8.
BTS 711 L1
Parameter and Conditions, each of the four channels Symbol Values Unit
at Tj = 25 °C,
V
bb = 12 V unless otherwise specified min typ max
Semiconductor Group 5
Standby current, all channels off
T
j =25°C:
VIN = 0
T
j =150°C:
I
bb(off) --
-- 28
44 60
70 µA
Leakage output current (included in
I
bb
(
off
)
)
V
IN = 0
I
L(off) -- -- 12 µA
Operating current 9),
V
IN = 5V,
T
j
=-40...+150°C
I
GND =
I
GND1/2 +
I
GND3/4, one channel on:
four channels on:
I
GND --
-- 2
83
12 mA
Protection Functions
Initial peak short circuit current limit, (see timing
diagrams, page 12)
each channel,
T
j =-40°C:
T
j =25°C:
T
j =+150°C:
I
L(SCp) 5.5
4.5
2.5
9.5
7.5
4.5
13
11
7
A
two parallel channels
twice the current of one channel
four parallel channels
four times the current of one channel
Repetitive short circuit current limit,
T
j =
T
jt each channel
two parallel channels
four parallel channels
(see timing diagrams, page 12)
I
L(SCr) --
--
--
4
4
4
--
--
--
A
Initial short circuit shutdown time
T
j,start =-40°C:
T
j,start = 25°C:
(see page 11 and timing diagrams on page 12)
t
off(SC) --
-- 5.5
4--
-- ms
Output clamp (inductive load switch off)10)
at VON(CL) = Vbb - VOUT
V
ON(CL) -- 47 -- V
Thermal overload trip temperature
T
jt 150 -- -- °C
Thermal hysteresis
∆T
jt -- 10 -- K
Reverse Battery
Reverse battery voltage 11)-
V
bb -- -- 32 V
Drain-source diode volta
g
e (Vout > Vbb)
I
L = - 1.9 A,
T
j = +150°C -
V
ON -- 610 -- mV
9)Add
I
ST, if
I
ST > 0
10)If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
11)Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 8).
BTS 711 L1
Parameter and Conditions, each of the four channels Symbol Values Unit
at Tj = 25 °C,
V
bb = 12 V unless otherwise specified min typ max
Semiconductor Group 6
Diagnostic Characteristics
Open load detection current, (on-condition)
each channel,
T
j = -40°C:
T
j = 25°C:
T
j = 150°C:
I
L (OL)110
10
10
--
--
--
200
150
150
mA
two parallel channels
twice the current of one channel
four parallel channels
four times the current of one channel
Open load detection voltage12)
T
j =-40..+150°C:
V
OUT(OL) 234V
Internal output pull down
(OUT to GND), VOUT = 5 V
T
j =-40..+150°C:
R
O41030k
Ω
Input and Status Feedback13)
Input resistance
(see circuit page 8)
T
j =-40..+150°C:
R
I2.5 3.5 6 kΩ
Input turn-on threshold volta
g
e
T
j =-40..+150°C:
V
IN(T+) 1.7 -- 3.5 V
Input turn-off threshold volta
g
e
T
j =-40..+150°C:
V
IN(T-) 1.5 -- -- V
Input threshold hysteresis ∆
V
IN(T) -- 0.5 -- V
Off state input current
V
IN = 0.4 V:
T
j =-40..+150°C:
I
IN(off) 1--50
µ
A
On state input current
V
IN = 5 V:
T
j =-40..+150°C:
I
IN(on) 20 50 90 µA
Dela
y
time for status with open load after switch
off
(
other channel in off state
)
(see timing diagrams, page 13),
T
j =-40..+150°C:
t
d(ST OL4) 100 320 800 µs
Dela
y
time for status with open load after switch
off
(
other channel in on state
)
(see timing diagrams, page 13),
T
j =-40..+150°C:
t
d(ST OL5) -- 5 20 µs
Status invalid after positive input slope
(open load)
T
j =-40..+150°C:
t
d(ST) -- 200 600 µs
Status output (open drain)
Zener limit voltage
T
j =-40...+150°C,
I
ST = +1.6 mA:
ST low voltage
T
j =-40...+25°C,
I
ST = +1.6 mA:
T
j = +150°C,
I
ST = +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
--
6.1
--
--
--
0.4
0.6
V
12) External pull up resistor required for open load detection in off state.
13) If ground resistors RGND are used, add the voltage drop across these resistors.
BTS 711 L1
Semiconductor Group 7
Truth Table
Channel 1 and 2 Chip 1 IN1 IN2 OUT1 OUT2 ST1/2 ST1/2
Channel 3 and 4
(equivalent to channel 1 and 2) Chip 2 IN3 IN4 OUT3 OUT4 ST3/4 ST3/4
BTS 711L1 BTS 712N1
Normal operation L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Open load Channel 1 (3) L
L
H
L
H
X
Z
Z
H
L
H
X
H(L14))
H
L
L
H
H
Channel 2 (4) L
H
X
L
L
H
L
H
X
Z
Z
H
H(L14))
H
L
L
H
H
Short circuit to Vbb Channel 1 (3) L
L
H
L
H
X
H
H
H
L
H
X
L15)
H
H(L16))
L15)
H
H
Channel 2 (4) L
H
X
L
L
H
L
H
X
H
H
H
L15)
H
H(L16))
L15)
H
H
Overtemperature both channel L
X
H
L
H
X
L
L
L
L
L
L
H
L
L
H
L
L
Channel 1 (3) L
HX
XL
LX
XH
LH
L
Channel 2 (4) X
XL
HX
XL
LH
LH
L
Undervoltage/ Overvoltage X X L L H H
L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
PROFET
IN2
ST1/2 OUT2
GND1/2
Vbb
VOUT2
IGND1/2
VON2
18
2
Leadframe
3
4
IN1
VOUT1
VON1
IL1
OUT1
5
17
VIN1 VIN2 VST1/2
Ibb
IIN1
IIN2
IST1/2 IL2
RGND1/2
Vbb
Chip 1 PROFET
IN4
ST3/4 OUT4
GND3/4
Vbb
VOUT4
IGND3/4
VON4
14
6
Leadframe
7
8
IN3
VOUT3
VON3
IL3
OUT3
9
13
VIN3 VIN4 VST3/4
IIN3
IIN4
IST3/4 IL4
RGND3/4
Chip 2
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External RGND optional; two resistors RGND1/2 ,RGND3/4 = 150 Ω or a single resistor RGND = 75 Ω for
reverse battery protection up to the max. operating voltage.
14)With additional external pull up resistor
15) An external short of output to Vbb in the off state causes an internal current from output to ground. If RGND is
used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
16)Low resistance to
V
bb may be detected by no-load-detection
BTS 711 L1
Semiconductor Group 8
Input circuit (ESD protection), IN1...4
IN
GND
I
R
ESD-ZD I
I
I
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
Status output, ST1/2 or ST3/4
ST
GND
ESD-
ZD
+5V
RST(ON)
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380 Ω
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of the zener voltage (increase of up to 1 V).
Inductive and overvoltage output clamp,
OUT1...4
+Vbb
OUT
PROFET
VZ
VON
Power GND
V
ON clamped to
V
ON(CL) = 47 V typ.
Overvoltage protection of logic part
GND1/2 or GND3/4
+ Vbb
IN
ST
ST
R
GND
GND
R
Signal GND
Logic
VZ2
IN RI
VZ1
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI = 3.5 kΩ typ.,
RGND = 150 Ω
Reverse battery protection
GND
Logic
ST
R
IN
ST
+ 5V
OUT
L
R
Power GND
GND
R
Signal GND
Power
Inverse
I
R
Vbb
-
Diode
R
GND = 150 Ω,
R
I = 3.5 kΩ typ,
Temperature protection is not active during inverse current
operation.
BTS 711 L1
Semiconductor Group 9
Open-load detection, OUT1...4
ON-state diagnostic condition:
V
ON < RON·IL(OL); IN high
Open load
detection
Logic
unit
+ Vbb
OUT
ON VON
OFF-state diagnostic condition:
V
OUT > 3 V typ.; IN low
Open load
detection
Logic
unit
VOUT
Signal GND
REXT
RO
OFF
GND disconnect
(channel 1/2 or 3/4)
PROFET
V
IN2
ST OUT2
GND
bb
Vbb Ibb
IN1 OUT1
VIN1VIN2 VST VGND
Any kind of load. In case of IN = high is
V
OUT ≈
V
IN -
V
IN(T+).
Due to V
GND
> 0, no VST = low signal available.
GND disconnect with GND pull up
(channel 1/2 or 3/4)
PROFET
V
IN2
ST OUT2
GND
bb
Vbb
IN1 OUT1
VIN1
VIN2
VST VGND
Any kind of load. If VGND >
V
IN -
V
IN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
Vbb disconnect with energized inductive
load
PROFET
V
IN2
ST OUT2
GND
bb
Vbb
IN1 OUT1
high
For an inductive load current up to the limit defined by EAS
(max. ratings see page 3 and diagram on page 10) each
switch is protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load the whole load
current flows through the GND connection.
BTS 711 L1
Semiconductor Group 10
Inductive load switch-off energy
dissipation
PROFET
V
IN
ST
OUT
GND
bb
=
E
E
E
EAS
bb
L
R
ELoad
RL
L
{
L
Z
Energy stored in load inductance:
E
L = 1/2·L·I2
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
AS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt,
with an approximate solution for RL > 0 Ω:
E
AS= IL· L
2·RL(Vbb + |VOUT(CL)|) ln (1+ IL·RL
|VOUT(CL)| )
Maximum allowable load inductance for
a single switch off (one channel)5)
L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
L [mH]
1
10
100
1000
11.522.53
I
L
[A]
BTS 711 L1
Semiconductor Group 11
Typ. on-state resistance
RON = f (Vbb,Tj ); IL = 1.8 A, IN = high
RON [mOhm]
0
50
100
150
200
250
300
350
400
450
500
010203040
Tj = 15 0° C
85°C
25°C
-40°C
Vbb [V]
Typ. open load detection current
IL(OL) = f (Vbb,Tj ); IN = high
IL(OL) [mA]
0
20
40
60
80
100
120
140
0 5 10 15 20 25 30
no load detection not specified
for Vbb < 6 V
Tj = 150°C
85°C
25°C
-40°C
Vbb [V]
Typ. standby current
Ibb(off) = f (Tj ); Vbb = 9...34 V, IN1...4 = low
Ibb(off) [µA]
0
10
20
30
40
50
60
-50 0 50 100 150 200
Tj [°C]
Typ. initial short circuit shutdown time
toff(SC) = f (Tj,start ); Vbb =12 V
toff(SC) [msec]
0
1
2
3
4
5
6
-50 0 50 100 150 200
Tj,start [°C]
BTS 711 L1
Semiconductor Group 12
Figure 1a: Vbb turn on:
IN2
V
OUT1
t
V
bb
ST ope n drain
IN1
VOUT2
Figure 2a: Switching a lamp:
IN
ST
OUT
L
t
V
I
The initial peak current should be limited by the lamp and not by
the initial short circuit current IL(SCp) = 7.5 A typ. of the device.
Figure 2b: Switching an inductive load
IN
ST
L
t
V
I
*)
OUT
td(ST)
IL(OL)
*) if the time constant of load is too large, open-load-status may
occur
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
othe r c han ne l: no rm a l ope r ation
t
I
ST
IN1
L1
L(SCr)
I
IL(SCp)
toff(SC)
Heating up of the chip may require several milliseconds, depending
on external conditions (toff(SC) vs. Tj,start see page 11)
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
BTS 711 L1
Semiconductor Group 13
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
t
ST1/2
IN1/2
L1 L2
L(SCr)
I
IL(SCp)
I + I
toff(SC)
Figure 4a: Overtemperature:
Reset if
T
j <
T
jt
IN
ST
OUT
J
t
V
T
Figure 5a: Open load: detection in ON-state, open
load occurs in on-state
IN2 channel 2: normal operation
OUT1
t
V
ST
IN1
IL1
td(ST OL1) td(ST OL2) td(ST OL1) td(ST OL2)
open
load open
load
normal
load
channel 1:
td(ST OL1) = 30 µs typ., td(ST OL2) = 20 µs typ
Figure 5b: Open load: detection in ON-state, turn
on/off to open load
OUT1
t
V
ST
IN1
IL1
td(ST) td(ST OL4) td(ST) td(ST OL5)
IN2 channel 2: normal operation
channel 1: open load
The status delay time td(STOL4) allows to distinguish between the
failure modes "open load in ON-state" and "overtemperature".
BTS 711 L1
Semiconductor Group 14
Figure 5c: Open load: detection in ON- and OFF-state
(with REXT), turn on/off to open load
t
V
ST
IN1
IL1
td(ST) d(ST OL5)
channel 1: open load
td(ST) t
OUT1
IN2 channel 2: nor m al operat ion
td(ST OL5) depends on external circuitry because of high
impedance
Figure 6a: Undervoltage:
IN
V
OUT
t
V
bb
ST ope n drain
VV
bb(under) bb(u rst)
bb(u cp)
V
Figure 6b: Undervoltage restart of charge pump
bb(under)
V
Vbb(u rst)
Vbb(over)
Vbb(o rst)
Vbb(u cp)
off-state
on-state
VON(CL)
Vbb
Von
off-state
IN = high, normal load conditions.
Charge pump starts at Vbb(ucp) = 5.6 V typ.
Figure 7a: Overvoltage:
IN
V
OUT
t
V
bb
ST
ON(CL)
VVbb(over) Vbb(o rst)
BTS 711 L1
Semiconductor Group 15
Package and Ordering Code
Standard P-DSO-20-9 Ordering Code
BTS711L1 Q67060-S7000-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature Ts:
upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70µm, 6cm2 active heatsink area) as a reference for
max. power dissipation Ptot, nominal load current
IL(NOM) and thermal resistance Rthja
