DI2CMS - Digital Core Design

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D

DI

I2

2C

CM

MS

S

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I2C Bus Interface – Master/Slave

ver 1.01

OVERVIEW

I2C is a two-wire, bi-directional serial bus that

provides a simple and efficient method of data

transmission over a short distance between

many devices. The DI2CMS core provides an

interface between a microprocessor / micro-

controller and an I2C bus. It can work as a

master or slave transmitter/receiver depend-

ing on working mode determined by micro-

processor/microcontroller. The DI2CMS core

incorporates all features required by the latest

I2C specification including clock synchroniza-

tion, arbitration, multi-master systems and

High-speed transmission mode. The DI2CMS

supports all the transmission speed modes.

Built-in timer allows operation from a wide

range of the clk frequencies.

The DI2CMS is a technology independent

VHDL or VERILOG design that can be imple-

mented in a variety of process technologies

and can be fully customized accordingly to

customer needs.

DI2CMS is delivered with fully automated

testbench and complete set of tests allow-

ing easy package validation at each stage of

SoC design flow.

KEY FEATURES

Conforms to v.2.1 of the I2C specification

Master mode

Master operation

Master transmitter

Master recei ver

Support for all transmission spee ds

Standard (up to 100 kb/s)

Fast (up to 400 kb/s)

High Speed (up to 3,4 Mb/s)

Arbitration and clock synchronization

Support for multi-master systems

Support for both 7-bit and 10-bit addressing

formats on the I2C bus

Build-in 8-bit timer for data transfers speed

adjusting

User-defined timing (data setup, start setup,

start hold, etc.)

Slave mode

Slave operation

Slave transmitter

Slave receiver

Supports 3 transmission speed m odes

Standard (up to 100 kb/s)

High Speed (up to 3,4 Mb/s)

Allows operation from a wide range of input

clock frequencies

User-defined data setup time

Simple interface allows easy connection to

microprocessor/microcontroller devices

Interrupt generation

Fully synthesizable

Static synchronous design with positive

edge clocking and synchronous reset

All trademarks mentioned in this document

are trademarks of their respective owners.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

No internal tri-states

Scan test ready

APPLICATIONS

Embedded microprocessor boards

Consumer and professional audio/video

Home and automotive radio

Low-power applications

Communication systems

Cost-effective reliable automotive systems

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

● Delivery the IP Core updates, mi-

nor and major versions changes

● Delivery the documentation up-

dates

● Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

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One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Desi gns

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

SYMBOL

datai(7:0) datao(7:0)

irq

rd

we

address(2:0)

scli

sdai

cs

rst

clk

sclhs

sclo

sdao

PINS DESCRIPTION

PIN TYPE DESCRIPTION

clk input Global clock

rst input Global reset

address(1:0) input Processor address lines

cs input Chip select

we input Processor write strobe

rd input Processor read strobe

scli input I2C bus clock line (input)

sdai input I2C bus data line (input)

datai(7:0) input Processor data bus (input)

datao(7:0) output Processor data bus (output)

sclo output I2C bus clock line (output)

sclhs output High-speed clock line (output)

sdao output I2C bus data line (output)

irq output Processor interrupt line

BLOCK DIAGRAM

Figure below shows the DI2CMS IP Core

block diagram.

address

(

2:0

)

datai

(

7:0

)

datao

(

7:0

)

rd

cs

we

rst

clk

ir

q

CPU

Interface

sdai

sdao

scli

sclo

Input

Filter

Output

Register

Shift

Register

Output

Register

Input

Filter

Timer

Control

Logic

Clock Control

Logic

Send

Data

Receive

Data

Slave

Address

Control

Register

Status

Register

Arbitration

Logic

Output

Register sclhs

CPU Interface – Performs the interface func-

tions between DI2CMS internal blocks and

microprocessor. Allows easy connection of the

core to a microprocessor/microcontroller sys-

tem.

Control Logic – Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

Shift Register – Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Control Register – Contains five control bits

used for performing all types of I2C Bus

transmissions.

Status Register – Contains seven status bits

that indicates state of the I2C Bus and the

DI2CMS core.

Input Filter – Performs spike filtering.

Clock Control Logic – Performs clock syn-

chronization, clock generation in master

mode, and clock stretching in slave mode.

Arbitration Logic – Performs arbitration dur-

ing operations in multi-master systems.

Timer – Allows operation from a wide range of

the input frequencies. It is programmed by an

user before transmission and can be repro-

grammed to change the SCL frequency.

IMPLEMENTATION PERFORMANCE

Figures below show the typical DI2CMS im-

plementations in system with Standard/Fast

and High-speed devices.

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route (all key features

have been included):

open drain

RPRP

VDD

sdai

SCL

SD

A

sdao

RSRS

sclo

scli

DI2CMS

Master

/Slave

device

scl

RS

sda

sclhs

Device Speed

grade Logic Cells Fmax

STRATIX-II -3 337 380 MHz

CYCOLNE-II -6 354 263 MHz

MERCURY -5 414 210 MHz

STRATIX -5 370 254 MHz

CYCLONE -6 370 220 MHz

APEX II -7 394 192 MHz

APEX20KC -7 394 150 MHz

APEX20KE -1 394 120 MHz

APEX20K -1 394 90 MHz

ACEX1K -1 411 107 MHz

FLEX10KE -1 411 107 MHz

MAX 2 -3 291 187 MHz

MAX 7000AE -5 198 67 MHz

MAX 3000A -7 198 49 MHz

Core performance in ALTERA® devices

DI2CMS implementation in I2C-bus system with

Standard/Fast devices only

open drain

RPRP

VDD

sdai

SCL

SD

A

sdao

RSRS

sclo

scli

DI2CMS

Master

/Slave

device

scl

RS

sda

sclhs

VDD

current-source

pull-up

DI2CMS implementation in I2C-bus system with

High-speed devices

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

The main features of each Digital Core Design I2C compliant cores have been summarized in table

below. It gives a briefly member characterization helping user to select the most suitable IP Core

for its application.

Design

I2C specification

version

Master operation

Slave operation

CPU interface

Passive device

interface

Interrupt genera-

tion

Clock synchroni-

zation

Arbitration

7-bit addressing

10-bit addressing

Standard mode

Fast mode

High-speed mode

User defined tim-

ing

Spike filtering

DI2CM 2.1 - -

DI2CS 2.1 - - - -

DI2CSB 2.1 - - - - - - -

DI2CMS 2.1 -

I2C cores summary table

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: info@dcd.pl

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dc

cd

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tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

Please check http://www.dcd.pl/apartn.php

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