K4S161622H CMOS SDRAM
Rev 1.4 August 2004
16Mb H-die SDRAM Specification
Revision 1.4
August 2004
Samsung Electronics res erves the right to change products or specification with ou t notic e.
50 TSOP-II with Pb-Free
(RoHS compliant)
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
Revision History
Revision 0.0 (October, 2003)
• Target spec release
Revision 1.0 (November, 2003)
• Revision 1.0 spec release
Revision 1.1 (December, 2003)
• Corrected PKG dimension.
Revision 1.2 (January, 2004)
• Deleted -10(10ns) speed
• Modified load cap 50pF -> 30pF
Modified DC current .
Revision 1.3 (May, 2004)
• Added Note 8. sentense of tRDL parameter.
Revision 1.4 (August, 2004)
• Corrected typo.
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications.
GENERAL DESCRIPTION
FEATURES
512K x 16Bit x 2 Banks Synchronous DRAM
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
• Pb-free Package
• RoHS compliant
ORDERING INFORMATION
Part NO. MAX Freq. Interface Package
K4S161622H-UC55 183MHz
LVTTL 50
TSOP(II)
K4S161622H-UC60 166MHz
K4S161622H-UC70 143MHz
K4S161622H-UC80 125MHz
Row & Column address configuration
Organization Row Address Column Address
1Mx16 A0~A10 A0-A7
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
50Pin TSOP(II) Package Dimension
Package Physical Dimension
#50 #26
#1 #25
11.76±0.20
(0.50)
0.125-0.035
+0.075
10.16
(10.76)
0.25 TYP
0~8°
± 0.10
(0.50)
11.76 ± 0.20
0.075MAX
[ ]
0.10MAX
(0.875) 0.30 -0.05
+0.10 [0.80±0.08]
0.80TYP 0.05MIN
1.20MAX 1.00± 0.10
20.95 ± 0.10
0.35 -0.05
+0.10
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
FUNCTIONAL BLOCK DIAGRAM
* Samsung Electronics reserves the right to change products or specification without notice.
Bank Select
Data Input Register
512K x 16
512K x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
Timing Register
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PIN CONFIGURATION (TOP VIEW)
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select Disables or enables device operation by maski ng or enabling all input s except
CLK, CKE and L(U)DQM
CKE Clock Enable Masks system clock to freez e operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
BA Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write Enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU No Connection/
Reserved for Future Use This pin is recommended to be left No Connection on the device.
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1W
Short circuit current IOS 50 mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high votlage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
Note :
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1. 4 V ± 200 mV)
Pin Symbol Min Max Unit
Clock CCLK 24pF
RAS, CAS, WE, CS, CKE, L(U)DQM CIN 24pF
Address CADD 24pF
DQ0 ~ DQ15 COUT 35pF
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
:
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitan ce added to power line at board.
Parameter Symbol Value Unit
Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Note :
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4S161622H-UC**
Note :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C )
Parameter Symbol Test Condition Version Unit Note
-55 -60 -70 -80
Operating Current
(One Bank Active) ICC1 Burst Length =1
tRC≥tRC(min)
Io = 0 mA 120 115 105 95 mA 2
Precharge Standby Current in
power-down mode ICC2PCKE≤VIL(max), tCC = 10ns 2 mA
ICC2PS CKE & CLK≤VIL(max), tCC = ∞2
Precharge Standby Current
in non power-down mode
ICC2NCKE≥VIH(min), CS≥VIH(min), tCC = 10ns
Input signals are changed one time during
30ns 15 mA
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable 5
Active Standby Current
in power-down mode ICC3PCKE≤VIL(max), tCC = 10ns 3 mA
ICC3PS CKE & CLK≤VIL(max), tCC = ∞3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3NCKE≥VIH(min), CS≥VIH(min), tCC = 10ns
Input signals are changed one time during
30ns 25 mA
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable 15 mA
Operating Current
(Burst Mode) ICC4 Io = 0 mA
Page Burst 2Banks Activated
tCCD = 2CLKs 155 150 140 130 mA 2
Refresh Current ICC5 tRC≥tRC(min) 105 100 90 90 mA 3
Self Refresh Current ICC6 CKE≤0.2V 1 mA
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter Value Unit
Input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200Ω
870Ω
Output VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt=1.4V
50Ω
Output Z0=50Ω
(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit
30pF 30pF
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter Symbol -55 -60 -70 -80 Unit Note
Min Max Min Max Min Max Min Max
CLK cycle time CAS Latency=3 tCC 5.5 1000 61000 71000 81000 ns 1
CAS Latency=2 - - 10 10
Row active to row active delay tRRD(min) 11-12-14-16-ns
RAS to CAS delay tRCD(min) 16.5 - 18 - 20 - 20 - ns
Row precharge time tRP(min) 16.5 - 18 - 20 - 20 - ns
Row active time tRAS(min) 38.5 100 42 100 49 100 48 100 ns
Row cycle time tRC(min)55-60-69-70-ns
Last data in to row precharge tRDL(min) 21CLK 2,8
Last data in to new col.address delay tCDL(min) 1CLK2
Last data in to burst stop tBDL(min) 1CLK2
Col. address to col. address delay tCCD(min) 1CLK
Mode Register Set cycle time tMRS(min) 2CLK
Number of valid out-
put data CAS Latency=3 2 ea 4
CAS Latency=2 1
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Parameters depend on programmed CAS latency.
6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
7. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL= 2CLK and tDAL=2CLK + tRP.
(AC operating conditions unless otherwise noted)
Parameter Symbol -55 -60 -70 -80 Unit Note
Min Max Min Max Min Max Min Max
CLK cycle time CAS Latency=3 tCC 5.5 1000 61000 71000 81000 ns 5
CAS Latency=2 - - 1 0 10
CLK to valid
output delay CAS Latency=3 tSAC - 5 -5.5-5.5- 6ns 5, 6
CAS Latency=2 - 6 - 6 - 6 - 6
Output data tOH 2 - 2.5 - 2.5 - 2.5 - ns 6
CLK high pulse
width CAS Latency=3 tCH 2-2.5 -3-3-ns7
CAS Latency=2 3 3
CLK low pulse
width CAS Latency=3 tCL 2-2.5 -3-3-ns7
CAS Latency=2 3 3
Input setup time CAS Latency=3 tSS 1.5 -1.5 -1.75 -2-ns7
CAS Latency=2 2 2 2
Input hold time tSH 1-1-1-1-ns7
CLK to output in Low-Z tSLZ 1-1-1-1-ns6
CLK to output
in Hi-Z CAS Latency=3 tSHZ - 5 -5.5-5.5 -6ns
CAS Latency=2 - 6 - 6 - 6 - 6
Notes :
K4S161622H CMOS SDRAM
Rev 1.4 August 2004
SIMPLIFIED TRUTH TABLE
(V=V alid, X=Don′t Care, H=Logic High, L= Logic Low)
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0Note
Register Mode Register Set H X L L L L X OP CODE 1, 2
Refresh
Auto Refresh HHLL LHX X 3
Self
Refresh
Entry L 3
Exit L H LHHHXX3
HX XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &
Column Address Auto Precharge Disable HXLHLHXV
LColumn
Address
(A0~A7)
4
Auto Precharge Enable H 4, 5
Write &
Column Address Auto Precharge Disable HXLHLLXV
LColumn
Address
(A0~A7)
4
Auto Precharge Enable H 4, 5
Burst Stop H X L H H L X X 6
Precharge Bank Selection HXLLHLX
VL X
Both Banks X H
Clock Suspend or
Active Power Down Entry H L HX XXXX
LVVV
Exit L H X X X X X
Precharge Power Down Mode
Entry H L HX XXX
X
LHHH
Exit L H HX XXX
LVVV
DQM H V X 7
No Operation Command H X HX XX XX
LHHH
1. OP Code : Operand Code
A0 ~ A10/AP, BA : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued on ly at both banks precharge state.
4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Note :
X
