LP3893
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SNVS237B –SEPTEMBER 2003–REVISED APRIL 2013
LP3893 3A Fast-Response Ultra Low Dropout Linear Regulators
Check for Samples: LP3893
1FEATURES DESCRIPTION
The LP3893 is a high-current, fast-response regulator
2• Ultra Low Dropout Voltage (270 mV at 3A typ) which can maintain output voltage regulation with
• Low Ground Pin Current minimum input to output voltage drop. Fabricated on
• Load Regulation of 0.04%/A a CMOS process, the device operates from two input
voltages: Vbias provides voltage to drive the gate of
• 60 nA Typical Quiescent Current in Shutdown the N-MOS power transistor, while Vin is the input
• 1.5% Output Accuracy (25°C) voltage which supplies power to the load. The use of
• TO-220, DDPAK/TO-263 Packages an external bias rail allows the part to operate from
ultra low Vin voltages. Unlike bipolar regulators, the
• Over Temperature/Over Current Protection CMOS architecture consumes extremely low
•−40°C to +125°C Junction Temperature Range quiescent current at any output load current. The use
of an N-MOS power transistor results in wide
APPLICATIONS bandwidth, yet minimum external capacitance is
required to maintain loop stability.
• DSP Power Supplies
• Server Core and I/O Supplies The fast transient response of these devices makes
them suitable for use in powering DSP,
• Linear Power Supplies for PC Add-in-Cards Microcontroller Core voltages and Switch Mode
• Set-Top Box Power Supplies Power Supply post regulators. The parts are available
• Microprocessor Power Supplies in TO-220 and DDPAK/TO-263 packages.
• High Efficiency Linear Power Supplies Dropout Voltage: 270 mV (typ) at 3A load current.
• SMPS Post-Regulators Ground Pin Current: 3 mA (typ) at full load.
Shutdown Current: 60 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature
accuracy.
TYPICAL APPLICATION CIRCUIT
At least 10 µF of input and output capacitance is required for stability.
*Tantalum capacitors are recommended. Aluminum electrolytic capacitors may be used for restricted temperature
range. See application hints.
CONNECTION DIAGRAM
Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LP3893
SNVS237B –SEPTEMBER 2003–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS (1)
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for
availability and specifications.
VALUE / UNITS
Storage Temperature Range −65°C to +150°C
Lead Temp. (Soldering, 5 seconds) 260°C
ESD Rating
Human Body Model (2) 2 kV
Machine Model (3) 200V
Power Dissipation (4) Internally Limited
VIN Supply Voltage (Survival) −0.3V to +6V
VBIAS Supply Voltage (Survival) −0.3V to +7V
Shutdown Input Voltage (Survival) −0.3V to +7V
IOUT (Survival) Internally Limited
Output Voltage (Survival) −0.3V to +6V
Junction Temperature −40°C to +150°C
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For specifications, see Electrical
Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
(3) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.
(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.
θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be
assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square
inches in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.
RECOMMENDED OPERATING CONDITIONS VALUE / UNITS
VIN (VOUT + VDO) to 5.5V
Shutdown 0 to +6V
IOUT 3A
Junction Temperature −40°C to +125°C
VBIAS 4.5V to 6V
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL= 10 mA, CIN = COUT =10 µF, VS/D = VBIAS.
Symbol Parameter Conditions Typical (1) MIN (2) MAX (2) Units
VOOutput Voltage Tolerance 10 mA ≤IL≤3A 1.198 1.234
1.216
VO(NOM) + 1V ≤VIN ≤5.5V 1.186 1.246
4.5V ≤VBIAS ≤6V 1.478 1.522
1.5 V
1.455 1.545
1.773 1.827
1.8 1.746 1.854
ΔVO/ΔVIOutput Voltage Line Regulation (3) VO(NOM) + 1V ≤VIN ≤5.5V 0.01 %/V
N
ΔVO/ΔILOutput Voltage Load Regulation (4) 10 mA ≤IL≤3A 0.04 %/A
0.06
VDO Dropout Voltage (5) IL= 3A 650
270 mV
1000
IQ(VIN) Quiescent Current Drawn from VIN 10 mA ≤IL≤3A 7
3 mA
Supply 8
VS/D ≤0.3V 1
0.03 µA
30
IQ(VBIAS) Quiescent Current Drawn from VBIAS 10 mA ≤IL≤3A 2
1 mA
Supply 3
VS/D ≤0.3V 1
0.03 µA
30
ISC Short-Circuit Current VOUT = 0V 6 A
Shutdown Input
VSDT Output Turn-off Threshold Output = ON 0.7 1.3 V
Output = OFF 0.7 0.3
Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 µs
Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15
IS/D S/D Input Current VS/D =1.3V 1 µA
VS/D ≤0.3V −1
AC Parameters
PSRR Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz 80
(VIN)VIN = VOUT + 1V, f = 1 kHz 65 dB
PSRR Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 70
(VBIAS)VBIAS = VOUT + 3V, f = 1 kHz 65
Output Noise Density f = 120 Hz µV/root−
1Hz
enOutput Noise Voltage BW = 10 Hz −100 kHz, VOUT = 1.8V 150 µV (rms)
BW = 300 Hz −300 kHz, VOUT = 1.8V 90
(1) Typical numbers represent the most likely parametric norm for 25°C operation.
(2) Limits are specified through testing, statistical correlation, or design.
(3) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(4) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(5) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: Tj= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
IGND vs VSD VOUT vs Temperature
Figure 3. Figure 4.
DC Load Regulation Line Regulation vs VIN
Figure 5. Figure 6.
Line Regulation vs VBIAS IBIAS vs IL
Figure 7. Figure 8.
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0 1 2 3 3.5
DROPOUT VOLTAGE (V)
ILOAD (A)
0
0.1
0.2
0.3
0.4
-40oC
25oC
125oC
LP3893
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SNVS237B –SEPTEMBER 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: Tj= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
ILOAD vs Dropout Voltage IGND vs VSD
Figure 9. Figure 10.
Noise Measurement VOUTStartup Waveform
Figure 11. Figure 12.
VOUTStartup Waveform VOUTStartup Waveform
Figure 13. Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: Tj= 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Line Regulation vs VBIAS Line Regulation vs VBIAS
Figure 15. Figure 16.
VIN PSRR VIN PSRR
Figure 17. Figure 18.
VBIAS PSRR VBIAS PSRR
Figure 19. Figure 20.
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LOAD CURRENT (A)
STABLE REGION COUT = 10PF
COUT = 100PF
0 1 2
COUT ESR (:)
3
.001
.01
0.1
1.0
10
LP3893
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SNVS237B –SEPTEMBER 2003–REVISED APRIL 2013
Application Hints
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
At least 10µF of output capacitance is required for stability (the amount of capacitance can be increased without
limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean
analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range
as shown in the graph below over the full operating temperature range for stable operation.
Figure 21. Minimum ESR vs Output Load Current
Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements
and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR
increases very rapidly at temperatures below 10°C. Aluminum caps can only be used in applications where lower
temperature operation is not required.
A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical
loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,
it must be one whose ESR is specified at a frequency of 100 kHz or more.
Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output
capacitors on LP389X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the
amount of Tantalum capacitance connected from the output to ground.
INPUT CAPACITOR
The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
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SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kΩto 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD= (VIN−VOUT)IOUT+ (VIN)IGND (1)
where IGND is the operating ground current of the device.
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax−TAmax (2)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD(3)
These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount
of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥60°C/W
for TO-220 package and ≥60°C/W for DDPAK/TO-263 package no heatsink is needed since the package can
dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat
sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on
a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for
DDPAK/TO-263 package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,
θHA≤ θJA − θCH − θJC. (4)
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING DDPAK/TO-263 PACKAGE
The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263
package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the
copper area for heat sinking.
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Figure 22. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 Package
As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.
The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.
Figure 23 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 23. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com 9-Jun-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3893ES-1.2 NRND DDPAK/
TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3893ES
-1.2
LP3893ES-1.2/NOPB ACTIVE DDPAK/
TO-263 KTT 5 45 Green (RoHS
& no Sb/Br) SN Level-3-245C-168 HR -40 to 125 LP3893ES
-1.2
LP3893ESX-1.2/NOPB ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) SN Level-3-245C-168 HR -40 to 125 LP3893ES
-1.2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3893ESX-1.2/NOPB DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3893ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
KTT0005B
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BOTTOM SIDE OF PACKAGE
TS5B (Rev D)
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