© 2006 Microchip Technology Inc. DS21978B-page 1
MCP4011/2/3/4
Features
Volatile Digital Potentiometer in SOT-23, SOIC,
MSOP and DFN packages
64 Taps: 63 Resistors with Taps to terminal A and
terminal B
Simple Up/Down (U/D) Protocol
Power-on Recall of Default Wiper Setting
- Custom POR wiper settings available
(contact factory)
Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ
Low Tempco:
- Absolute (Rheostat): 50 ppm (0°C to 70°C typ.)
- Ratiometric (Potentiometer): 10 ppm (typ.)
Low Wiper Resistance: 75Ω (typ.)
High-Voltage Tolerant Digital Inputs: Up to 12.5V
Low-Power Operation: 1 µA Max Static Current
Wide Operating Voltage Range:
- 1.8V to 5.5V - Device Operation
- 2.7V to 5.5V - Resistor Characteristics
Specified
Extended Temperature Range: -40°C to +125°C
Wide Bandwidth (-3 dB) Operation:
- 4 MHz (typ.) for 2.1 kΩ device
Description
The MCP4011/2/3/4 devices are volatile, 6-bit Digital
Potentiometers that can be configured as either a
potentiometer or rheostat. The wiper setting is
controlled through a simple Up/Down (U/D) serial
interface.
Package Types
Block Diagram
Device Features
.
A
W
B
MCP4011
SOIC, MSOP, DFN
MCP4012
SOT-23-6
MCP4013
SOT-23-6
MCP4014
SOT-23-5
RheostatPotentiometer
Potentiometer Rheostat
A
VSS
W
1
2
3
4
8
7
6
5
VDD U/D
NC
B
CS
4
1
2
3
5W
CS
VDD
VSS
U/D
4
1
2
3
6A
CS
VDD
VSS
U/D
5W
AW
B
4
1
2
3
6A
CS
VDD
VSS
U/D
5W
A
W
W
A
BB
VDD
VSS
U/D
W
B
(Resistor Array)
Wiper Register
CS
A
2-Wire
Interface
and
Control
Logic
Power-Up
and
Brown-Out
Control
Device Wiper
Configuration
Memory
Type
POR Wiper
Setting
Resistance (typical)
# of
Steps
VDD
Operating
Range (2)
Control
Interface
WiperLock™
Technology
Options (kΩ)Wiper
(Ω)
MCP4011 Potentiometer
(1) RAM Mid-Scale 2.1, 5.0, 10.0, 50.0 75 64 1.8V to 5.5V U/D No
MCP4012 Rheostat RAM Mid-Scale 2.1, 5.0, 10.0, 50.0 75 64 1.8V to 5.5V U/D No
MCP4013 Potentiometer RAM Mid-Scale 2.1, 5.0, 10.0, 50.0 75 64 1.8V to 5.5V U/D No
MCP4014 Rheostat RAM Mid-Scale 2.1, 5.0, 10.0, 50.0 75 64 1.8V to 5.5V U/D No
Note 1: Floating either terminal (A or B) allows the device to be used in Rheostat mode.
2: Analog characteristics (resistor) tested from 2.7V to 5.5V.
Low-Cost 64-Step Volatile Digital POT
MCP4011/2/3/4
DS21978B-page 2 © 2006 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ............................................................................................................. 6.5V
CS and U/D inputs w.r.t VSS.................................... -0.3V to 12.5V
A,B and W terminals w.r.t VSS..................... -0.3V to VDD + 0.3V
Current at Input Pins ..................................................±10 mA
Current at Supply Pins ...............................................±10 mA
Current at Potentiometer Pins ...................................±2.5 mA
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins ........... 4kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ) . .........................+150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V,
VSS = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Operating Voltage Range VDD 2.7 5.5 V
VDD —1.8 VV
DD = 1.8V, CS:VIHH = 8.5V,
VIH = 1.8V, VIL = 0V,
U/D:VIH = 1.8V, VIL = 0V
CS Input Voltage VCS V
SS 12.5 V The CS pin will be at one of three
input levels (VIL, VIH or VIHH).
(Note 6)
Supply Current IDD —45 µA5.5V, CS = VSS, fU/D = 1 MHz
—15 µA2.7V, CS
= VSS, fU/D = 1 MHz
0.3 1 µA Serial Interface Inactive
(CS = VIH, U/D = VIH)
Resistance
(± 20%)
RAB 1.68 2.1 2.52 kΩ-202 devices (Note 1)
4.0 5 6.0 kΩ-502 devices (Note 1)
8.0 10 12.0 kΩ-103 devices (Note 1)
40.0 50 60.0 kΩ-503 devices (Note 1)
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
3: MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4012/14 only, test conditions are:
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
8: For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”.
9: The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested.
Device
Resistance
Current at Voltage
Comments
5.5V 2.7V
2.1 kΩ2.25 mA 1.1 mA MCP4012 includes VWZSE
MCP4014 includes VWFSE
5kΩ1.4 mA 450 µA
10 kΩ450 µA 210 µA
50 kΩ90 µA 40 µA
© 2006 Microchip Technology Inc. DS21978B-page 3
MCP4011/2/3/4
Resolution N 64 Taps No Missing Codes
Step Resistance RSRAB / 63 Ω Note 6
Wiper Resistance (Note 3, Note 4) RW 70 125 Ω5.5V
70 325 Ω2.7V
Nominal Resistance Tempco ΔR/ΔT 50 ppm/°C TA = -20°C to +70°C
100 ppm/°C TA = -40°C to +85°C
150 ppm/°C TA = -40°C to +125°C
Ratiometeric Tempco ΔVWA/Δ
T
10 ppm/°C MCP4011 and MCP4013 only,
code = 1Fh
Full-Scale Error (MCP4011/13 only) VWFSE -0.5 -0.1 +0.5 LSb Code 3Fh, 2.7V VDD 5.5V
Zero-Scale Error (MCP4011/13 only) VWZSE -0.5 +0.1 +0.5 LSb Code 00h, 2.7V VDD 5.5V
Monotonicity N Yes Bits
Resistor Terminal Input Voltage Range
(Terminals A, B and W)
VA,VW,
VB
Vss VDD VNote 5, Note 6
Current through A, W or B IW—— 2.5 mANote 6
Leakage current into A, W or B IWL —100 nAMCP4011 A = W = B = VSS
—100 nAMCP4012/13 A = W = VSS
—100 nAMCP4014 W = VSS
Capacitance (PA)C
AW 75 pF f =1 MHz, code = 1Fh
Capacitance (Pw)C
W 120 pF f =1 MHz, code = 1Fh
Capacitance (PB)C
BW 75 pF f =1 MHz, code = 1Fh
Bandwidth -3 dB BW 4 MHz Code = 1F, output load = 30 pF
—2 MHz
—1 MHz
200 kHz
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V,
VSS = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
3: MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4012/14 only, test conditions are:
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
8: For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”.
9: The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested.
Device
Resistance
Current at Voltage
Comments
5.5V 2.7V
2.1 kΩ2.25 mA 1.1 mA MCP4012 includes VWZSE
MCP4014 includes VWFSE
5kΩ1.4 mA 450 µA
10 kΩ450 µA 210 µA
50 kΩ90 µA 40 µA
MCP4011/2/3/4
DS21978B-page 4 © 2006 Microchip Technology Inc.
Potentiometer Integral Non-linearity INL -0.5 ±0.25 +0.5 LSb MCP4011/13 only (Note 2)
Potentiometer Differential Non-linearity DNL -0.5 ±0.25 +0.5 LSb MCP4011/13 only (Note 2)
Rheostat Integral Non-linearity
MCP4011 (Note 4, Note 9)
MCP4012 and MCP4014 (Note 4)
R-INL -0.5 ±0.25 +0.5 LSb 2.1 kΩ 5.5V
-8.5 +4.5 +8.5 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 5 kΩ 5.5V
-5.5 +2.5 +5.5 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 10 kΩ 5.5V
-3 +1 +3 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 50 kΩ 5.5V
-1 +0.25 +1 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
Rheostat Differential Non-linearity
MCP4011 (Note 4, Note 9)
MCP4012 and MCP4014 (Note 4)
R-DNL -0.5 ±0.25 +0.5 LSb 2.1 kΩ 5.5V
-1 +0.5 +2 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 5 kΩ 5.5V
-1 +0.25 +1.25 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 10 kΩ 5.5V
-1 0+1 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
-0.5 ±0.25 +0.5 LSb 50 kΩ 5.5V
-0.5 0+0.5 LSb 2.7V (Note 7)
See Section 2.0 LSb 1.8V (Note 7, Note 8)
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V,
VSS = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
3: MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4012/14 only, test conditions are:
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
8: For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”.
9: The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested.
Device
Resistance
Current at Voltage
Comments
5.5V 2.7V
2.1 kΩ2.25 mA 1.1 mA MCP4012 includes VWZSE
MCP4014 includes VWFSE
5kΩ1.4 mA 450 µA
10 kΩ450 µA 210 µA
50 kΩ90 µA 40 µA
© 2006 Microchip Technology Inc. DS21978B-page 5
MCP4011/2/3/4
Digital Inputs/Outputs (CS, U/D)
Input High Voltage VIH 0.7 VDD ——V
Input Low Voltage VIL ——0.3V
DD V
High-Voltage Input Entry Voltage VIHH 8.5 12.5 (6) V Threshold for WiperLock™
Technology
High-Voltage Input Exit Voltage VIHH ——V
DD+0.8(6) V
CS Pull-up/Pull-down Resistance RCS —16 kΩVDD = 5.5V, VCS = 3V
CS Weak Pull-up/Pull-down Current IPU —170 µAV
DD = 5.5V, VCS = 3V
Input Leakage Current IIL -1 1 µA VIN = VDD
CS and U/D Pin Capacitance CIN,
COUT
—10 pFf
C = 1 MHz, VDD 2.7V
RAM (Wiper) Value
Value Range N 0h 3Fh hex
Default POR Setting N 1Fh hex
Power Requirements
Power Supply Sensitivity
(MCP4011 and MCP4013 only)
PSS 0.0015 0.0035 %/% VDD = 4.5V to 5.5V, VA = 4.5V,
Code = 1Fh
0.0015 0.0035 %/% VDD = 2.7V to 4.5V, VA = 2.7V,
Code = 1Fh
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V,
VSS = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
3: MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h.
4: MCP4012/14 only, test conditions are:
5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
8: For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”.
9: The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested.
Device
Resistance
Current at Voltage
Comments
5.5V 2.7V
2.1 kΩ2.25 mA 1.1 mA MCP4012 includes VWZSE
MCP4014 includes VWFSE
5kΩ1.4 mA 450 µA
10 kΩ450 µA 210 µA
50 kΩ90 µA 40 µA
MCP4011/2/3/4
DS21978B-page 6 © 2006 Microchip Technology Inc.
FIGURE 1-1: Increment Timing Waveform.
CS
U/D
tLCUR
tLO
tHI
tLUC
W
tCSHI
tS
1/fUD
tCSLO
tS
tLCUF
tLUC tLCUF
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C.
Parameters Sym Min Typ Max Units Conditions
CS Low Time tCSLO 5—µs
CS High Time tCSHI 500 ns 2.7V VDD 5.5V
———ns1.8V VDD < 2.7V
U/D to CS Hold Time tLUC 500 ns 2.7V VDD 5.5V
750 ns 1.8V VDD < 2.7V
CS to U/D Low Setup Time tLCUF 500 ns
CS to U/D High Setup Time tLCUR 3—µs
U/D High Time tHI 500 ns
U/D Low Time tLO 500 ns
Up/Down Toggle Frequency fUD —— 1MHz
Wiper Settling Time tS0.5 µs 2.1 kΩ, CL = 100 pF
1—µs5kΩ, CL = 100 pF
2—µs10kΩ, CL = 100 pF
10 5 µs 50 kΩ, CL = 100 pF
Wiper Response on Power-up tPU —200— ns
© 2006 Microchip Technology Inc. DS21978B-page 7
MCP4011/2/3/4
FIGURE 1-2: Decrement Timing Waveform.
CS
U/D
tLCUR
tHI
tLO
W
tS
tCSLO
tLUC
tCSHI
tLUC tLCUF
tS
1/fUD
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C.
Parameters Sym Min Typ Max Units Conditions
CS Low Time tCSLO 5—µs
CS High Time tCSHI 500 ns 2.7V VDD 5.5V
———ns1.8V VDD < 2.7V
U/D to CS Hold Time tLUC 500 ns 2.7V VDD 5.5V
750 ns 1.8V VDD < 2.7V
CS to U/D Low Setup Time tLCUF 500 ns
CS to U/D High Setup Time tLCUR 3—µs
U/D High Time tHI 500 ns
U/D Low Time tLO 500 ns
Up/Down Toggle Frequency fUD —— 1MHz
Wiper Settling Time tS0.5 µs 2.1 kΩ, CL = 100 pF
1—µs5kΩ, CL = 100 pF
2—µs10kΩ, CL = 100 pF
10 5 µs 50 kΩ, CL = 100 pF
Wiper Response on Power-up tPU —200— ns
MCP4011/2/3/4
DS21978B-page 8 © 2006 Microchip Technology Inc.
FIGURE 1-3: High-Voltage Increment Timing Waveform.
CS
U/D
tHCUR
tLO
tHI
tHUC
W
tCSHI
tS
1/fUD
tCSLO
tS
tHCUF
tHUC tHCUF
5V
12V
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C.
Parameters Sym Min Typ Max Units Conditions
CS Low Time tCSLO 5—µs
CS High Time tCSHI 500 ns 2.7V VDD 5.5V
———ns1.8V VDD < 2.7V
U/D High Time tHI 500 ns
U/D Low Time tLO 500 ns
Up/Down Toggle Frequency fUD —— 1MHz
HV U/D to CS Hold Time tHUC 1.5 µs
HV CS to U/D Low Setup Time tHCUF 8—µs
HV CS to U/D High Setup Time tHCUR 4.5 µs
Wiper Settling Time tS0.5 µs 2.1 kΩ, CL = 100 pF
1—µs5kΩ, CL = 100 pF
2—µs10kΩ, CL = 100 pF
10 5 µs 50 kΩ, CL = 100 pF
Wiper Response on Power-up tPU —200— ns
© 2006 Microchip Technology Inc. DS21978B-page 9
MCP4011/2/3/4
FIGURE 1-4: High-Voltage Decrement Timing Waveform.
CS
U/D
tHCUR
tHI
tLO
W
tS
tCSLO
tHUC
tCSHI
tHUC tHCUF
tS
5V
12V
1/fUD
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C.
Parameters Sym Min Typ Max Units Conditions
CS Low Time tCSLO 5—µs
CS High Time tCSHI 500 ns 2.7V VDD 5.5V
———ns1.8V VDD < 2.7V
U/D High Time tHI 500 ns
U/D Low Time tLO 500 ns
Up/Down Toggle Frequency fUD —— 1MHz
HV U/D to CS Hold Time tHUC 1.5 µs
HV CS to U/D Low Setup Time tHCUF 8—µs
HV CS to U/D High Setup Time tHCUR 4.5 µs
Wiper Settling Time tS0.5 µs 2.1 kΩ, CL = 100 pF
1—µs5kΩ, CL = 100 pF
2—µs10kΩ, CL = 100 pF
10 5 µs 50 kΩ, CL = 100 pF
Wiper Response on Power-up tPU —200— ns
MCP4011/2/3/4
DS21978B-page 10 © 2006 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS =GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 °C
Operating Temperature Range TA-40 +125 °C
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA —70°C/W
Thermal Resistance, 6L-SOT-23 θJA —120°C/W
Thermal Resistance, 8L-DFN (2x3) θJA —85°C/W
Thermal Resistance, 8L-MSOP θJA —206°C/W
Thermal Resistance, 8L-SOIC θJA —163°C/W
© 2006 Microchip Technology Inc. DS21978B-page 11
MCP4011/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-1: Device Current (IDD) vs. U/D
Frequency (fU/D) and Ambient Temperature
(VDD = 2.7V and 5.5V).
FIGURE 2-2: Device Current (ISHDN) and
VDD. (CS = VDD) vs. Ambient Temperature.
FIGURE 2-3: CS Pull-up/Pull-down
Resistance (RCS) and Current (ICS) vs. CS Input
Voltage (VCS) (VDD = 5.5V).
FIGURE 2-4: CS High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
10
20
30
40
50
60
70
80
0.20 0.40 0.60 0.80 1.00
f
U/D
(MHz)
Device Current (I
DD
) (µA)
2.7V -40°C
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-40 25 85 125
Ambient Temperature (°C)
Device Current (I
DD
) (µA)
VDD = 2.7V
VDD = 5.5V
0
50
100
150
200
250
987654321
V
CS
(V)
R
CS
(kOhms)
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
I
CS
(µA)
RCS
ICS
0
2
4
6
8
10
12
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
CS V
PP
Threshold (V)
1.8V Entry
2.7V Entry
5.5V Entry
1.8V Exit
2.7V Exit
5.5V Exit
MCP4011/2/3/4
DS21978B-page 12 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-5: 2.1 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-6: 2.1 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-7: 2.1 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
FIGURE 2-8: 2.1 k
Ω
Rheo Mode – RW
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-9: 2.1 k
Ω
Rheo Mode – RW
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-10: 2.1 k
Ω
Rheo Mode – RW
(
Ω
), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
0
20
40
60
80
100
120
140
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
0.075
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.05
0
0.05
0.1
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
600
700
800
900
1000
1100
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2.75
-2.25
-1.75
-1.25
-0.75
-0.25
0.25
0.75
1.25
1.75
2.25
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
20
40
60
80
100
120
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
600
700
800
900
1000
1100
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
© 2006 Microchip Technology Inc. DS21978B-page 13
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-11: 2.1 k
Ω
– Nominal
Resistance (
Ω
) vs. Ambient Temperature and
VDD.
FIGURE 2-12: 2.1 k
Ω
– RWB (
Ω
) vs. Wiper
Setting and Ambient Temperature.
2000
2020
2040
2060
2080
-40 0 40 80 120
Ambient Temperature (°C)
Nominal Resistance (R
AB
)
(Ohms)
VDD = 2.7V
VDD = 5.5V
0
500
1000
1500
2000
2500
0 8 16 24 32 40 48 56 64
Wiper Setting (decimal)
R
WB
(Ohms)
-40°C
25°C
85°C
125°C
MCP4011/2/3/4
DS21978B-page 14 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-13: 2.1 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-14: 2.1 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-15: 2.1 k
Ω
– Power-Up Wiper
Response Time.
FIGURE 2-16: 2.1 k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
FIGURE 2-17: 2.1 k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
WIPER
U/D
U/D
WIPER
WIPER
VDD
U/D
WIPER
WIPER
U/D
U/D
WIPER
© 2006 Microchip Technology Inc. DS21978B-page 15
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-18: 5k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-19: 5k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-20: 5k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
FIGURE 2-21: 5k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-22: 5k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-23: 5k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
0
20
40
60
80
100
120
140
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
0.075
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
50
100
150
200
250
300
350
400
450
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.125
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
0.075
0.1
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
500
1000
1500
2000
2500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2.75
-2.25
-1.75
-1.25
-0.75
-0.25
0.25
0.75
1.25
1.75
2.25
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
20
40
60
80
100
120
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
600
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-1
0
1
2
3
4
5
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
500
1000
1500
2000
2500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
MCP4011/2/3/4
DS21978B-page 16 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-24: 5k
Ω
– Nominal Resistance
(
Ω
) vs. Ambient Temperature and VDD.
FIGURE 2-25: 5k
Ω
– RWB (
Ω
) vs. Wiper
Setting and Ambient Temperature.
4800
4825
4850
4875
4900
4925
4950
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Nominal Resistance (R
AB
)
(Ohms)
VDD = 2.7V
VDD = 5.5V
0
1000
2000
3000
4000
5000
6000
0 8 16 24 32 40 48 56 64
Wiper Setting (decimal)
R
WB
(Ohms)
-40°C
25°C
85°C
125°C
© 2006 Microchip Technology Inc. DS21978B-page 17
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-26: 5k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-27: 5k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-28: 5k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
FIGURE 2-29: 5k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
U/D
WIPER
U/D
WIPER
U/D
WIPER
U/D
WIPER
MCP4011/2/3/4
DS21978B-page 18 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-30: 10 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-31: 10 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-32: 10 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
FIGURE 2-33: 10 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-34: 10 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-35: 10 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
0
20
40
60
80
100
120
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
50
100
150
200
250
300
350
400
450
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.125
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
500
1000
1500
2000
2500
3000
3500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2.75
-2.25
-1.75
-1.25
-0.75
-0.25
0.25
0.75
1.25
1.75
2.25
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
20
40
60
80
100
120
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2.5
-1.5
-0.5
0.5
1.5
2.5
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
500
1000
1500
2000
2500
3000
3500
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
© 2006 Microchip Technology Inc. DS21978B-page 19
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-36: 10 k
Ω
– Nominal Resistance
(
Ω
) vs. Ambient Temperature and VDD.
FIGURE 2-37: 10 k
Ω
– RWB (
Ω
) vs. Wiper
Setting and Ambient Temperature.
10050
10070
10090
10110
10130
10150
10170
10190
10210
10230
10250
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Nominal Resistance (R
AB
)
(Ohms)
VDD = 5.5V
VDD = 2.7V
0
2000
4000
6000
8000
10000
12000
0 8 16 24 32 40 48 56 64
Wiper Setting (decimal)
R
WB
(Ohms)
-40°C
25°C
85°C
125°C
MCP4011/2/3/4
DS21978B-page 20 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-38: 10 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-39: 10 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-40: 10 k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
FIGURE 2-41: 10 k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
U/D
WIPER
U/D
WIPER
U/D
WIPER
U/D
WIPER
© 2006 Microchip Technology Inc. DS21978B-page 21
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-42: 50 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-43: 50 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-44: 50 k
Ω
Pot Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
FIGURE 2-45: 50 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
FIGURE 2-46: 50 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
FIGURE 2-47: 50 k
Ω
Rheo Mode – RW (
Ω
),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
0
40
80
120
160
200
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.15
-0.1
-0.05
0
0.05
0.1
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
600
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.075
-0.05
-0.025
0
0.025
0.05
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
11000
12000
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
50
100
150
200
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-0.1
-0.05
0
0.05
0.1
0.15
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
100
200
300
400
500
600
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-1.5
-1
-0.5
0
0.5
1
1.5
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
11000
12000
0 8 16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Error (LSb)
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL
INL
DNL
RW
MCP4011/2/3/4
DS21978B-page 22 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-48: 50 k
Ω
– Nominal Resistance
(
Ω
) vs. Ambient Temperature and VDD.
FIGURE 2-49: 50 k
Ω
– RWB (
Ω
) vs. Wiper
Setting and Ambient Temperature.
48000
48200
48400
48600
48800
49000
49200
49400
49600
49800
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Nominal Resistance (R
AB
)
(Ohms)
VDD = 2.7V
VDD = 5.5V
0
10000
20000
30000
40000
50000
60000
0 8 16 24 32 40 48 56 64
Wiper Setting (decimal)
R
WB
(Ohms)
-40C
25C
85C
125C
© 2006 Microchip Technology Inc. DS21978B-page 23
MCP4011/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-50: 50 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-51: 50 k
Ω
– Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-52: 50 k
Ω
– Power-Up Wiper
Response Time.
FIGURE 2-53: 50 k
Ω
– Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
FIGURE 2-54: 50 k
Ω
- Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
U/D
WIPER
U/D
WIPER
VDD
WIPER
U/D
WIPER
U/D
WIPER
MCP4011/2/3/4
DS21978B-page 24 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-55: Gain vs. Frequency (-3 dB
Bandwidth).
FIGURE 2-56: Gain vs. Frequency (-3 dB
Bandwidth) Test Circuit.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-40 25 125
Temperature (°C)
-3dB Frequency (MHz)
2.1 k
:
5 k
:
10 k
:
50 k
:
VIN
-
+
+5V
VOUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
© 2006 Microchip Technology Inc. DS21978B-page 25
MCP4011/2/3/4
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS and can range
from 1.8V to 5.5V. A decoupling capacitor on VDD (to
VSS) is recommended to achieve maximum
performance.
3.2 Ground (VSS)
The VSS pin is the device ground reference.
3.3 Potentiometer Terminal A
The terminal A pin is connected to the internal potenti-
ometer’s terminal A (available on some devices). The
potentiometer’s terminal A is the fixed connection to the
0x3F terminal of the digital potentiometer.
The terminal A pin is available on the MCP4011,
MCP4012 and MCP4013 devices. The terminal A pin
does not have a polarity relative to the terminal W or B
pins. The terminal A pin can support both positive and
negative current. The voltage on terminal A must be
between VSS and VDD.
The terminal A pin is not available on the MCP4014.
The potentiometers terminal A is internally floating.
3.4 Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potenti-
ometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
terminal W must be between VSS and VDD.
3.5 Potentiometer Terminal B
The terminal B pin is connected to the internal potenti-
ometer’s terminal B (available on some devices). The
potentiometer’s terminal B is the fixed connection to the
0x00 terminal of the digital potentiometer.
The terminal B pin is available on the MCP4011 device.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
The terminal B pin is not available on the MCP4012,
MCP4013 and MCP4014 devices.
For the MCP4013 and MCP4014, the internal potenti-
ometer’s terminal B is internally connected to VSS.
Terminal B does not have a polarity relative to
terminals W or A. Terminal B can support both positive
and negative current.
For the MCP4012, terminal B is internally floating.
Pin Number
Symbol Pin
Type
Buffer
Type Function
MCP4011
(SOIC-8)
MCP4012
MCP4013
(SOT-23-6)
MCP4014
(SOT-23-5)
111V
DD P Positive Power Supply Input
222V
SS P Ground
3 6 A I/O A Potentiometer Terminal A
4 5 5 W I/O A Potentiometer Wiper Terminal
544CS
I TTL Chip Select Input
6 B I/O A Potentiometer Terminal B
7 NC No Connection
833U/D
I TTL Increment/Decrement Input
Legend: TTL = TTL compatible input A = Analog input
I = Input O = Output
P = Power
MCP4011/2/3/4
DS21978B-page 26 © 2006 Microchip Technology Inc.
3.6 Chip Select (CS)
The CS pin is the chip select input. Forcing the CS pin
to VIL enables the serial commands. These commands
can increment and decrement the wiper. Forcing the
CS pin to VIHH enables the high-voltage serial
commands. These commands can increment and
decrement the wiper and are compatibe with the
MCP402X devices. The wiper is saved to volatile
memory (RAM).
The CS pin has an internal pull-up resistor. The resistor
will become “disabled” when the voltage on the CS pin
is below the VIH level. This means that when the CS pin
is “floating”, the CS pin will be pulled to the VIH level
(serial communication (the U/D pin) is ignored). And
when the CS pin is driven low (VIL), the resistance
becomes very large to reduce the device current
consumption when serial commands are occurring.
See Figure 2-3 for additional information.
3.7 Increment/Decrement (U/D)
The U/D pin input is used to increment or decrement
the wiper on the digital potentiometer. An increment
moves the wiper one step toward terminal A, while a
decrement moves the wiper one step toward
terminal B.
© 2006 Microchip Technology Inc. DS21978B-page 27
MCP4011/2/3/4
4.0 GENERAL OVERVIEW
The MCP4011/2/3/4 devices are general purpose
digital potentiometers intended to be used in
applications where a programmable resistance with
moderate bandwidth is desired.
Applications generally suited for the MCP4011/2/3/4
devices include:
Set point or offset trimming
Sensor calibration
Selectable gain and offset amplifier designs
Cost-sensitive mechanical trim pot replacement
The digital potentiometer is available in four nominal
resistances (RAB), where the nominal resistance is
defined as the resistance between terminal A and
terminal B. The four nominal resistances are 2.1 kΩ,
5kΩ, 10 kΩ and 50 kΩ.
There are 63 resistors in a string between terminal A
and terminal B. The wiper can be set to tap onto any of
these 63 resistors thus providing 64 possible settings
(including terminal A and terminal B).
Figure 4-1 shows a block diagram for the resistive
network of the device. Equation 4-1 shows the
calculation for the step resistance, while Equation 4-2
illustrates the calculation used to determine the
resistance between the wiper and terminal B.
FIGURE 4-1: Resistor Block Diagram.
EQUATION 4-1: RS CALCULATION
EQUATION 4-2: RWB CALCULATION
1 LSb is the ideal resistance difference between two
successive codes. If we use N = 1 and RW = 0 in
Equation 4-2, we can calculate the step size for each
increment or decrement command.
The MCP4011 device offers a voltage divider
(potentiometer) with all terminals available on pins.
The MCP4012 is a true rheostat, with terminal A and
the wiper (W) of the variable resistor available on pins.
The MCP4013 device offers a voltage divider (potenti-
ometer) with terminal B connected to ground.
The MCP4014 device is a Rheostat device with
terminal A of the resistor floating, terminal B connected
to ground, and the wiper (W) available on pin.
The MCP4011 can be externally configured to
implement any of the MCP4012, MCP4013 or
MCP4014 configurations.
4.1 Serial Interface
A 2-wire synchronous serial protocol is used to
increment or decrement the digital potentiometer’s
wiper terminal. The Increment/Decrement (U/D)
protocol utilizes the CS and U/D input pins. Both inputs
are tolerant of signals up to 12.5V without damaging
the device. The CS pin can differenciate between two
high-voltage levels, VIH and VIHH. This enables
additional commands without requiring additional input
pins. The high-voltage commands (VIHH on the CS pin)
are similar to the standard commands and are
supported for compatability to the MCP401X family of
devices.
The simple U/D protocol uses the state of the U/D pin
at the falling edge of the CS pin to determine if
Increment or Decrement mode is desired. Subsequent
rising edges of the U/D pin move the wiper.
The wiper value will not underflow or overflow.
RS
A
RS
RS
RS
B
N = 63
N = 62
N = 61
N = 1
N = 0
RW (1)
W
01h
Analog
Mux
RW (1)
00h
RW (1)
3Dh
RW (1)
3Eh
RW (1)
3Fh
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 kΩ) more.
RS
RAB
63
---------=
RWB
RABN
63
--------------RW
+=
N = 0 to 63 (decimal)
MCP4011/2/3/4
DS21978B-page 28 © 2006 Microchip Technology Inc.
4.2 Power-up
When the device powers up (rising VDD crosses the
Trip Point Voltage (VTP)), the “default” wiper setting is
restored. Table 4 - 1 shows the default value loaded into
the wiper on POR/BOR.
TABLE 4-1: DEFAULT POR WIPER
SETTING SELECTION
While VDD < Vmin (1.8V), the electrical performance
may not meet the data sheet specifications (see
Figure 4-2). The wiper state may be unknown. Also, the
device may be capable of incrementing or decrement-
ing, if a valid command is detected on the CS and U/D
pins.
4.3 Brown Out
If the device VDD is below the specified minimum
voltage, care must be taken to ensure that the CS and
U/D pins do not “create” any of the serial commands.
When the device VDD drops below VMIN (1.8V), the
electrical performance may not meet the data sheet
specifications (see Figure 4-2). The wiper state may be
unknown. Also, the device may be capable of
incrementing or decrementing, if a valid command is
detected on the CS and U/D pins.
When the device voltage rises from below the power-
up trip point (VTP) into the valid operation voltage
range, the wiper state will be forced to the default POR
wiper setting (see Ta ble 4- 1 ).
4.4 Serial Interface Inactive
The serial interface is inactive any time the CS pin is at
VIH and all write cycles are completed.
FIGURE 4-2: Power-up and Brown-out.
Package
Code
Default
POR
Wiper
Setting
Wiper
Code
Typical
RAB Value
-202 Mid-scale 1Fh 2.1 kΩ
-502 Mid-scale 1Fh 5.0 kΩ
-103 Mid-scale 1Fh 10.0 kΩ
-503 Mid-scale 1Fh 50.0 kΩ
VTP
VSS
VDD
1.8V
POR Trip Point (on Rising VDD)
Outside Device Operation
Wiper Forced to Default POR Setting
© 2006 Microchip Technology Inc. DS21978B-page 29
MCP4011/2/3/4
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4011/2/3/4 utilizes a simple 2-wire interface to
increment or decrement the digital potentiometer’s
wiper terminal (W). This interface uses the CS and U/D
pins. The CS pin is the Chip Select input, while the U/D
pin is the Up/Down input.
The Increment/Decrement protocol enables the device
to move one step at a time through the range of
possible resistance values. The wiper value is
initialized with the “default” value upon power-up.
A wiper value of 00h connects the wiper to terminal B.
A wiper value of 3Fh connects the wiper to terminal A.
Increment commands move the wiper toward terminal
A, but will not increment to a value greater than 3Fh.
Decrement commands move the wiper toward terminal
B, but will not decrement below 00h.
Refer to Section 1.0 “Electrical Characteristics”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
Communication is unidirectional. Therefore, the value
of the current wiper setting cannot be read out of the
MCP401X device.
5.2 Serial Commands
The MCP401X devices support eight serial commands.
Six of these commands are for support and to ease
migration with the MCP402X family of devices. The
commands can be grouped into the following types:
Serial Commands
High-voltage Serial Commands
All the commands are shown in Table 5-1.
The command type is determined by the voltage level
the CS pin is driven to. The initial state that the CS pin
must be driven is VIH. From VIH, the two levels that the
CS pin can be driven are:
•V
IL
•V
IHH
If the CS pin is driven from VIH to V
IL, a serial
command is selected. If the CS pin is driven from VIH to
VIHH, a high-voltage serial command is selected.
Support of the high-voltage serial commands is for
compatiblity with the MCP402X devices.
TABLE 5-1: COMMANDS
Command Name High Voltage
on CS pin?
Increment
Increment (for MCP402X Compatibility)
Decrement
Decrement (for MCP402X Compatibility)
High-Voltage Increment 1 (for MCP402X Compatibility) Yes
High-Voltage Increment 2 (for MCP402X Compatibility) Yes
High-Voltage Decrement 1 (for MCP402X Compatibility) Yes
High-Voltage Decrement 2 (for MCP402X Compatibility) Yes
MCP4011/2/3/4
DS21978B-page 30 © 2006 Microchip Technology Inc.
5.2.1 INCREMENT
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increment the wiper setting toward terminal A. This is
shown in Figure 5-1.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions on the U/D pin do not cause
the wiper setting to increment. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
When the device voltage falls below the RAM retention
voltage of the device, the wiper state may be corrupted.
When the device returns to the operating range, the
wiper will be loaded with the default POR wiper setting.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-1: Increment.
Note: The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X+1
XX+2 X+3 X+4
VIH
VIH
56
VIL
VIL
© 2006 Microchip Technology Inc. DS21978B-page 31
MCP4011/2/3/4
5.2.2 INCREMENT (FOR MCP402X
COMPATIBILITY)
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increments the wiper setting toward terminal A. This is
shown in Figure 5-2.
After the wiper is incremented to the desired position,
the U/D pin should be driven low (VIL), and the CS pin
should be forced to VIH to ensure that “unexpected”
transitions on the U/D pin do not cause the wiper
setting to increment. Driving the CS pin to VIH should
occur as soon as possible (within device specifications)
after the last desired increment occurs.
When the device voltage falls below the RAM retention
voltage of the device, the wiper state may be corrupted.
When the device returns to the operating range, the
wiper will be loaded with the Default POR wiper setting.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-2: Increment (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting.
Note: The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X+1
XX+2 X+3 X+4
VIH
VIH
VIH
56
VIL
VIL
MCP4011/2/3/4
DS21978B-page 32 © 2006 Microchip Technology Inc.
5.2.3 DECREMENT
This mode is achieved by initializing the U/D pin to a low
state (VIL) prior to achieving a low state (VIL) on the CS
pin. Subsequent rising edges of the U/D pin will
decrement the wiper setting toward terminal B. This is
shown in Figure 5-3.
After the wiper is decremented to the desired position,
the U/D pin should be forced low (VIL) and the CS pin
should be forced to VIH. This will ensure that
“unexpected” transitions on the U/D pin do not cause
the wiper setting to decrement. Driving the CS pin to
VIH should occur as soon as possible (within device
specifications) after the last desired increment occurs.
When the device voltage falls below the RAM retention
voltage of the device, the wiper state may be corrupted.
When the device returns to the operating range, the
wiper will be loaded with the default POR wiper setting.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-3: Decrement.
Note: The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X-1XX-2X-3X-4
VIH
VIH 56
VIL
VIL
VIL
© 2006 Microchip Technology Inc. DS21978B-page 33
MCP4011/2/3/4
5.2.4 DECREMENT (FOR MCP402X
COMPATIBILITY)
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
decrement the wiper setting toward terminal B. This is
shown in Figure 5-4.
After the wiper is decremented to the desired position,
the U/D pin should remain high (VIH), and the CS pin
should be forced to VIH to ensure that “unexpected”
transitions on the U/D pin do not cause the wiper
setting to increment. Driving the CS pin to VIH should
occur as soon as possible (within device specifications)
after the last desired increment occurs.
When the device voltage falls below the RAM retention
voltage of the device, the wiper state may be corrupted.
When the device returns to the operating range, the
wiper will be loaded with the default POR wiper setting.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-4: Decrement (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting.
Note: The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
U/D
CS
Wiper X-1
XX-2 X-3 X-4
1 2 3 4
VIH
VIH
56
VIL
VIL
MCP4011/2/3/4
DS21978B-page 34 © 2006 Microchip Technology Inc.
5.2.5 HIGH-VOLTAGE INCREMENT 1
(FOR MCP402X COMPATIBILITY)
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
high state (VIH) prior to forcing the CS pin to VIH. This
is shown in Figure 5-5.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-5: High-Voltage Increment 1 (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting
with the WiperLock Technology feature.
Note: The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X+1
XX+2 X+3 X+4
VIHH
VIH
VIH
VIH
56
VIL
VIH
© 2006 Microchip Technology Inc. DS21978B-page 35
MCP4011/2/3/4
5.2.6 HIGH-VOLTAGE INCREMENT 2
(FOR MCP402X COMPATIBILITY)
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This is
shown in Figure 5-6.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-6: High-Voltage Increment 2 (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting
with the WiperLock Technology feature.
Note: The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X+1
XX+2 X+3 X+4
VIHH
VIH
VIH
56
VIL
VIH
VIL
MCP4011/2/3/4
DS21978B-page 36 © 2006 Microchip Technology Inc.
5.2.7 HIGH-VOLTAGE DECREMENT 1
(FOR MCP402X COMPATIBILITY)
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This is
shown in Figure 5-7.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-7: High-Voltage Decrement 1 (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting
with the WiperLock Technology feature.
Note: The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X-1
XX-2 X-3 X-4
VIHH
VIH
VIH
56
VIL
VIH
VIL
© 2006 Microchip Technology Inc. DS21978B-page 37
MCP4011/2/3/4
5.2.8 HIGH-VOLTAGE DECREMENT 2
(FOR MCP402X COMPATIBILITY)
This mode is achieved by initializing the U/D pin to the
low state (VIL) prior to driving the CS pin to VIHH.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to a
high state (VIH) prior to forcing the CS pin to VIH. This
is shown in Figure 5-8.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered.
FIGURE 5-8: High-Voltage Decrement 2 (For MCP402X Compatibility).
Note: This command allows compatibility with
the MCP402X family, which supports
updating of the non-volatile wiper setting
with the WiperLock Technology feature.
Note: The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
U/D
CS
Wiper
1 2 3 4
X-1
XX-2 X-3 X-4
VIHH
VDD
VIH
VIH
56
VIH
VIL
MCP4011/2/3/4
DS21978B-page 38 © 2006 Microchip Technology Inc.
5.3 CS High Voltage
The CS pin is High-Voltage (VIHH) tolerant, like the
MCP402X. This allows the MCP401X to be used in
MCP402X applications without needing to change
other portions of the application circuit.
6.0 RESISTOR
Digital potentiometer applications can be divided into
two categories:
Rheostat configuration
Potentiometer (or voltage divider) configuration
Figure 6-1 shows a block diagram for the MCP401X
resistors.
FIGURE 6-1: Resistor Block Diagram.
Step resistance (RS) is the resistance from one tap
setting to the next. This value will be dependent on the
RAB value that has been selected. Table 6-1 shows the
typical step resistances for each device.
The total resistance of the device has minimal variation
due to operating voltage (see Figure 2-11, Figure 2-24,
Figure 2-36 or Figure 2-48).
TABLE 6-1: TYPICAL STEP RESISTANCES
Terminal A and B, as well as the wiper W, do not have
a polarity. These terminals can support both positive
and negative current.
RS
A
RS
RS
RS
B
N = 63
N = 62
N = 61
N = 1
N = 0
RW (1)
W
01h
Analog
Mux
RW (1)
00h
RW (1)
3Dh
RW (1)
3Eh
RW (1)
3Fh
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 kΩ) more.
Part Number
Typical Resistance (Ω)
Total (RAB) Step (RS)
PIC18FXXXX-203E 2100 33.33
PIC18FXXXX-503E 5000 79.37
PIC18FXXXX-104E 10000 158.73
PIC18FXXXX-504E 50000 793.65
© 2006 Microchip Technology Inc. DS21978B-page 39
MCP4011/2/3/4
6.1 Resistor Configurations
6.1.1 RHEOSTAT CONFIGURATION
When used as a rheostat, two of the three digital poten-
tiometer’s terminals are used as a resistive element in
the circuit. With terminal W (wiper) and either terminal
A or terminal B, a variable resistor is created. The
resistance will depend on the tap setting of the wiper
and the wiper’s resistance. The resistance is controlled
by changing the wiper setting.
The unused terminal (B or A) should be left floating.
Figure 6-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
FIGURE 6-2: Rheostat Configuration.
This allows the control of the total resistance between
the two nodes. The total resistance depends on the
“starting” terminal to the wiper terminal. At the code
00h, the RBW resistance is minimal (RW), but the RAW
resistance in maximized (RAB + RW). Conversely, at the
code 3Fh, the RAW resistance is minimal (RW), but the
RBW resistance in maximized (RAB + RW).
The resistance step size (RS) equates to one LSb of the
resistor.
The change in wiper-to-end terminal resistance over
temperature is shown in Figure 2-11, Figure 2-24,
Figure 2-36 and Figure 2-48. The most variation over
temperature will occur in the first few codes due to the
wiper resistance coefficient affecting the total
resistance. The remaining codes are dominated by the
total resistance tempco RAB.
6.1.2 POTENTIOMETER
CONFIGURATION
When used as a potentiometer, all three terminals are
tied to different nodes in the circuit. This allows the
potentiometer to output a voltage proportional to the
input voltage. This configuration is sometimes called
voltage divider mode. The potentiometer is used to
provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 6-3. Reversing the polarity of the A and B
terminals will not affect operation.
FIGURE 6-3: Potentiometer Configuration.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
The wiper resistor temperature coefficient is different
from the RAB temperature coefficient. The voltage at
node V3 (Figure 6-3) is not dependent on this wiper
resistance, just the ratio of the RAB resistors, so this
temperature coefficient in most cases can be
ignored.
Note: To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
A
B
W
Resistor
RAW RBW
or
Note: To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
A
B
W
V1
V3
V2
MCP4011/2/3/4
DS21978B-page 40 © 2006 Microchip Technology Inc.
6.2 Wiper Resistance
Wiper resistance is the series resistance of the wiper.
This resistance is typically measured when the wiper is
positioned at either zero-scale (00h) or full-scale (3Fh).
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error.
The wiper resistance in rheostat applications can
create significant non-linearity as the wiper is moved
toward zero-scale (00h). The lower the nominal
resistance, the greater the possible error.
Wiper resistance is significant depending on the
devices operating voltage. As the device voltage
decreases, the wiper resistance increases (see
Figure 6-4 and Ta b l e 6 - 2 ).
In a rheostat configuration, this change in voltage
needs to be taken into account, particularly for the
lower resistance devices. For the 2.1 kΩ device, the
maximum wiper resistance at 5.5V is approximately 6%
of the total resistance, while at 2.7V, it is approximately
15.5% of the total resistance.
In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
terminal W pin.
The slope of the resistance has a linear area (at the
higher voltages) and a non-linear area (at the lower
voltages), where resistance increases faster than the
voltage drop (at low voltages).
FIGURE 6-4: Relationship of Wiper
Resistance (RW) to Voltage.
Since there is minimal variation of the total device
resistance over voltage, at a constant temperature (see
Figure 2-11, Figure 2-24, Figure 2-36 or Figure 2-48),
the change in wiper resistance over voltage can have a
significant impact on the INL and DNL error.
TABLE 6-2: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE
RW
VDD
Note: The slope of the resistance has a linear
area (at the higher voltages) and a non-
linear area (at the lower voltages).
Resistance (Ω)R
W / RS (%) (1, 2) R
W / RAB (%) (1, 3)
Typical Wiper (RW)
RW =
Typical
RW = Max
@ 5.5V
RW = Max
@ 2.7V
RW =
Typical
RW = Max
@ 5.5V
RW = Max
@ 2.7V
Total
(RAB)
Step
(RS)Typical Max @
5.5V
Max @
2.7V
2100 33.33 75 125 325 225.0% 375.0% 975.0% 3.57% 5.95% 15.48%
5000 79.37 75 125 325 94.5% 157.5% 409.5% 1.5% 2.50% 6.50%
10000 158.73 75 125 325 47.25% 78.75% 204.75% 0.75% 1.25% 3.25%
50000 793.65 75 125 325 9.45% 15.75% 40.95% 0.15% 0.25% 0.65%
Note 1: The wiper resistance (RW) is not a significant source of error in potentiometer-generated voltage divider
applications. In rheostat applications, the variation of the RW value can create significant non-linearity.
2: RS is the typical value. The variation of this resistance is minimal over voltage.
3: RAB is the typical value. The variation of this resistance is minimal over voltage.
© 2006 Microchip Technology Inc. DS21978B-page 41
MCP4011/2/3/4
6.3 Operational Characteristics
Understanding the operational characteristics of the
device’s resistor components is important to the system
design.
6.3.1 ACCURACY
6.3.1.1 Integral Non-Linearity (INL)
INL error for these devices is the maximum deviation
between an actual code transition point and its
corresponding ideal transition point after offset and
gain errors have been removed. These endpoints are
from 0x00 to 0x3F. Refer to Figure 6-5.
Positive INL means higher resistance than ideal.
Negative INL means lower resistance than ideal.
FIGURE 6-5: INL Accuracy.
6.3.1.2 Differential Non-Linearity (DNL)
DNL error is the measure of variations in code widths
from the ideal code width. A DNL error of zero would
imply that every code is exactly 1 LSb wide.
FIGURE 6-6: DNL Accuracy.
6.3.1.3 Ratiometric Temperature Coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a
potentiometer device (MCP4011 and MCP4013) in a
voltage divider configuration.
6.3.1.4 Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using a rheostat device (MCP4012
and MCP4014) in an adjustable resistor configuration.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Rransfer
Function
INL < 0
Ideal Transfer
Function
INL < 0
Digital Pot Output
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
Ideal Transfer
Function
Narrow Code < 1 LSb
Wide Code, > 1 LSb
Digital Pot Output
MCP4011/2/3/4
DS21978B-page 42 © 2006 Microchip Technology Inc.
6.3.2 MONOTONIC OPERATION
Monotonic operation means that the device’s
resistance increases with every step change (from
terminal A to terminal B or terminal B to terminal A).
The wiper resistance is different at each tap location.
When changing from one tap position to the next (either
increasing or decreasing), the ΔRW is less than the
ΔRS. When this change occurs, the device voltage and
temperature are “the same” for the two tap positions.
FIGURE 6-7: Resistance RBW.
0x3F
0x3E
0x3D
0x03
0x02
0x01
0x00
Digital Input Code
Resistance (RBW)
RW
(@ tap)
RS0
RS1
RS3
RS62
RS63
RBW = RSn + RW(@ Tap n)
n = 0
n = ?
© 2006 Microchip Technology Inc. DS21978B-page 43
MCP4011/2/3/4
7.0 DESIGN CONSIDERATIONS
In the design of a system with the MCP401X devices,
the following considerations should be taken into
account:
The Power Supply
The Layout
7.1 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 7-1: Typical Microcontroller
Connections.
7.2 Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4011/2/3/4’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
VDD
VDD
VSS VSS
MCP4011/2/3/4
0.1 µF
PIC® Microcontroller
0.1 µF
U/D
CS
W
B
A
MCP4011/2/3/4
DS21978B-page 44 © 2006 Microchip Technology Inc.
8.0 APPLICATIONS EXAMPLES
Non-volatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP4011/2/3/4 devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
8.1 Set Point Threshold Trimming
Applications that need accurate detection of an input
threshold event often need several sources of error
eliminated. Use of comparators and operational
amplifiers (op amps) with low offset and gain error can
help achieve the desired accuracy, but in many
applications, the input source variation is beyond the
designer’s control. If the entire system can be
calibrated after assembly in a controlled environment
(like factory test), these sources of error are minimized,
if not entirely eliminated.
Figure 8-1 illustrates a common digital potentiometer
configuration. This configuration is often referred to as
a “windowed voltage divider”. Note that R1 and R2 are
not necessary to create the voltage divider, but their
presence is useful when the desired threshold has
limited range. It is “windowed” because R1 and R2 can
narrow the adjustable range of VTRIP to a value much
less than VDD – VSS. If the output range is reduced, the
magnitude of each output step is reduced. This
effectively increases the trimming resolution for a fixed
digital potentiometer resolution. This technique may
allow a lower-cost digital potentiometer to be utilized
(64 steps instead of 256 steps).
The MCP4011’s and MCP4013’s low DNL performance
is critical to meeting calibration accuracy in production
without having to use a higher precision digital
potentiometer.
EQUATION 8-1: CALCULATING THE
WIPER SETTING FROM
THE DESIRED VTRIP
FIGURE 8-1: Using the Digital
Potentiometer to Set a Precise Output Voltage.
8.1.1 TRIMMING A THRESHOLD FOR AN
OPTICAL SENSOR
If the application has to calibrate the threshold of a
diode, transistor or resistor, a variation range of 0.1V is
common. Often, the desired resolution of 2 mV or
better is adequate to accurately detect the presence of
a precise signal. A “windowed” voltage divider, utilizing
the MCP4011 or MCP4013, would be a potential
solution as shown in Figure 8-2.
FIGURE 8-2: Set Point or Threshold
Calibration.
VTRIP VDD
R2RWB
+
R1RAB R2
++
-----------------------------------
⎝⎠
⎛⎞
=
RAB RNominal
=
RWB RAB
D
63
------
⎝⎠
⎛⎞
=
DVTRIP
VDD
--------------
⎝⎠
⎛⎞
R1RAB R2
++()R2
()
⎝⎠
⎛⎞
63=
Where:
D = Digital Potentiometer Wiper Setting (0-63)
VDD
VOUT
R2
A
R1
W
B
MCP4011
CS
U/D
VTRIP
0.1 µF
Comparator
VCC+
VCC–
VDD
Rsense
R1
R2
B
A
VDD
W
MCP4011
CS
U/D MCP6021
© 2006 Microchip Technology Inc. DS21978B-page 45
MCP4011/2/3/4
8.2 Operational Amplifier
Applications
Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical
amplifier circuits that could replace fixed resistors with
the MCP4011/2/3/4 to achieve digitally-adjustable
analog solutions.
Figure 8-4 shows a circuit that allows a non-inverting
amplifier to have its’ offset and gain to be independently
trimmed. The MCP4011 is used along with resistors R1
and R2 to set the offset voltage. The sum of R1 + R2
resistance should be significantly greater (> 100 times)
the resistance value of the MCP4011. This allows each
increment or decrement in the MCP4011 to be a fine
adjustment of the offset voltage. The input voltage of
the op amp (VIN) should be centered at the op amps Vw
voltage. The gain is adjusted by the MCP4012. If the
resistance value of the MCP4012 is small compared to
the resistance value of R3, then this is a fine adjustment
of the gain. If the resistance value of the MCP4012 is
equal (or large) compared to the resistance value of R3,
then this is a course adjustment of the gain. In general,
trim the course adjustments first and then trim the fine
adjustments.
FIGURE 8-3: Trimming Offset and Gain in
an Inverting Amplifier.
FIGURE 8-4: Trimming Offset and Gain in
a Non-Inverting Amplifier.
FIGURE 8-5: Programmable Filter.
Op Amp
VIN
VOUT
B
A
W
+
MCP4011
R1
R2
B
A
VDD
W
R3R4
MCP4011
MCP6001
Op Amp
VIN
VOUT
+
R1
R2
B
A
VDD
W
R3
MCP6291
MCP4011
MCP4012
AW
VW
VDD
Op Amp
VIN VOUT
B
A
W
+
MCP4011
R1
R2
B
A
VDD
W
MCP4011
R3R4
fc
1
2
π
REq C
⋅⋅
-----------------------------=
Pot1
Pot2
REq R1RAB RWB
+()R2RWB
+()Rw
+
||
=
Thevenin
Equivalent
MCP6021
MCP4011/2/3/4
DS21978B-page 46 © 2006 Microchip Technology Inc.
8.3 Temperature Sensor Applications
Thermistors are resistors with very predictable
variation with temperature. Thermistors are a popular
sensor choice when a low-cost, temperature-sensing
solution is desired. Unfortunately, thermistors have
non-linear characteristics that are undesirable, typically
requiring trimming in an application to achieve greater
accuracy. There are several common solutions to trim
and linearize thermistors. Figure 8-6 and Figure 8-7
are simple methods for linearizing a 3-terminal NTC
thermistor. Both are simple voltage dividers using a
Positive Temperature Coefficient (PTC) resistor (R1)
with a transfer function capable of compensating for the
linearity error in the Negative Temperature Coefficient
(NTC) thermistor.
The circuit, illustrated by Figure 8-6, utilizes a digital
rheostat for trimming the offset error caused by the
thermistor’s part-to-part variation. This solution puts the
digital potentiometer’s RW into the voltage divider
calculation. The MCP4011/2/3/4’s RAB temperature
coefficient is 50 ppm (-20°C to +70°C). RW’s error is
substantially greater than RAB’s error because RW
varies with VDD, wiper setting and temperature. For the
50 kΩ devices, the error introduced by RW is, in most
cases, insignificant as long as the wiper setting is > 6.
For the 2 kΩ devices, the error introduced by RW is
significant because it is a higher percentage of RWB.
For these reasons, the circuit illustrated in Figure 8-6 is
not the most optimum method for “exciting” and
linearizing a thermistor.
FIGURE 8-6: Thermistor Calibration using
a Digital Potentiometer in a Rheostat
Configuration.
The circuit illustrated by Figure 8-7 utilizes a digital
potentiometer for trimming the offset error. This
solution removes RW from the trimming equation along
with the error associated with RW. R2 is not required,
but can be utilized to reduce the trimming “window” and
reduce variation due to the digital potentiometer’s RAB
part-to-part variability.
FIGURE 8-7: Thermistor Calibration using
a Digital Potentiometer in a Potentiometer
Configuration.
8.4 Wheatstone Bridge Trimming
Another common configuration to “excite” a sensor
(such as a strain gauge, pressure sensor or thermistor)
is the wheatstone bridge configuration. The wheat-
stone bridge provides a differential output instead of a
single-ended output. Figure 8-8 illustrates a
wheatstone bridge utilizing one to three digital
potentiometers. The digital potentiometers in this
example are used to trim the offset and gain of the
wheatstone bridge.
FIGURE 8-8: Wheatstone Bridge
Trimming.
NTC
VDD
MCP4012
VOUT
Thermistor
R1
R2
W
A
NTC
VDD
MCP4011
VOUT
Thermistor
R1
R2
VDD
MCP4012
VOUT
2.1 kΩ
MCP4012
50 kΩ
MCP4012
50 kΩ
© 2006 Microchip Technology Inc. DS21978B-page 47
MCP4011/2/3/4
9.0 DEVELOPMENT SUPPORT
9.1 Evaluation/Demonstration Boards
Currently there are three boards that are available that
can be used to evaluate the MCP401X family of
devices.
1. The MCP402X Digital Potentiometer Evaluation
Board kit (MCP402XEV) contains a simple dem-
onstration board utilizing a PIC10F206, the
MCP401X and a blank PCB, which can be pop-
ulated with any desired MCP4011/2/3/4 device
in a SOT-23-5, SOT-23-6 or 150 mil SOIC 8-pin
package.
This board has two push buttons to control when
the PIC® microcontroller generates MCP402X
serial commands. The example firmware
demonstrates the following commands:
Increment
Decrement
High-Voltage Increment and Enable
WiperLock Technology
High-Voltage Decrement and Enable
WiperLock Technology
High-Voltage Increment and Disable
WiperLock Technology
High-Voltage Decrement and Disable
WiperLock Technology
The populated board (with the MCP4011) can
be used to evaluate the other MCP401X devices
by appropriately jumpering the PCB pads.
2. The SOT-23-5/6 Evaluation Board (VSUPEV2)
can be used to evaluate the characteristics of
the MCP4012, MCP4013 and MCP4014
devices.
3. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation
Board (SOIC8EV) can be used to evaluate the
characteristics of the MCP4011 device in either
the SOIC or MSOP package.
4. The MCP4XXX Digital Potentiometer Daughter
Board allows the system designer to quickly
evaluate the operation of Microchip Technol-
ogy's MCP42XXX and MCP402X Digital Poten-
tiometers. The board supports two MCP42XXX
devices and an MCP402X device, which can be
replaced with an MCP401X device.
The board also has a voltage doubler device
(TC1240A), which can be used to show the
WiperLock™ Technology feature of the
MCP4021.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
MCP4011/2/3/4
DS21978B-page 48 © 2006 Microchip Technology Inc.
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
5-Lead SOT-23 (MCP4014)Example:
XXNN JU25
Part Number Code
MCP4014T-202E/OT JUNN
MCP4014T-502E/OT JVNN
MCP4014T-103E/OT JWNN
MCP4014T-503E/OT JXNN
Note: Applies to 5-Lead SOT-23
6-Lead SOT-23 (MCP4012 / MCP4013)Example:
XXNN BJ25
Part Number
Code
MCP4012 MCP4013
MCP401xT-202E/CH BJNN BPNN
MCP401xT-502E/CH BKNN BQNN
MCP401xT-103E/CH BLNN BRNN
MCP401xT-503E/CH BMNN BSNN
Note: Applies to 6-Lead SOT-23
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
© 2006 Microchip Technology Inc. DS21978B-page 49
MCP4011/2/3/4
Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead MSOP (MCP4011) Example:
XXXXXX
YWWNNN
401122
534256
Example:8-Lead DFN (2x3) (MCP4011)
XXX
YWW
NNN
ABE
534
256
8-Lead SOIC (150 mil) (MCP4011) Example:
XXXXXXXX
XXXXYYWW
NNN
401152E
SN^^ 0534
256
3
e
Part Number Code
MCP4011T-202E/MC ABE
MCP4011T-502E/MC ABF
MCP4011T-103E/MC ABG
MCP4011T-503E/MC ABH
Note: Applies to 8-Lead DFN
Part Numbers
Code
8L-MSOP 8L-SOIC
MCP4011-202E/MS MCP4011-202E/SN 22
MCP4011-502E/MS MCP4011-502E/SN 52
MCP4011-103E/MS MCP4011-103E/SN 13
MCP4011-503E/MS MCP4011-503E/SN 53
MCP4011/2/3/4
DS21978B-page 50 © 2006 Microchip Technology Inc.
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
p
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
10501050
b
Mold Draft Angle Bottom
10501050
a
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
f
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059E1Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000A1Standoff
1.301.100.90.051.043.035A2Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
55
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES
*
Units
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
Notes:
EIAJ Equivalent: SC-74A
Drawing No. C04-091
*
Controlling Parameter
Revised 09-12-05
© 2006 Microchip Technology Inc. DS21978B-page 51
MCP4011/2/3/4
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
φ
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059E1Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000A1Standoff
1.301.100.90.051.043.035A2Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90 BSC.075 BSC
p1
Outside lead pitch
0.95 BSC.038 BSC
p
Pitch
66
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES
*
Units
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
Notes:
JEITA (formerly EIAJ) equivalent: SC-74A
*
Controlling Parameter
Drawing No. C04-120
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
Revised 09-12-05
MCP4011/2/3/4
DS21978B-page 52 © 2006 Microchip Technology Inc.
8-Lead Plastic Dual-Flat No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Overall Width
Exposed Pad Length
Exposed Pad Width
Contact Width
Contact Length §
Contact-to-Exposed Pad §
Units
Dimension Limits
N
e
A
A1
A3
D
E
D2
E2
b
L
K
0.80
0.00
1.30
1.50
0.18
0.30
0.20
8
0.50 BSC
0.90
0.02
0.20 REF
2.00 BSC
3.00 BSC
0.25
0.40
1.00
0.05
1.75
1.90
0.30
0.50
MIN NOM MAX
MILLIMETERS
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. § Significant Characteristic
4. Package is saw singulated
5. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–123, Sept. 8, 2006
A3 A1 NOTE 2
NOTE 1
NOTE 1
E2
D2
BOTTOM VIEW
EXPOSED PAD
K
L
1
2
N
e
b
TOP VIEW
2
1
N
D
E
A
© 2006 Microchip Technology Inc. DS21978B-page 53
MCP4011/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
L
L1
ϕ
c
A2
A1
A
b
2
1
NOTE 1
e
E
E1
D
N
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
A2
A1
E
E1
D
L
L1
ϕ
c
b
0.75
0.00
0.40
0.08
0.22
8
0.65 BSC
0.85
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
1.10
0.95
0.15
0.80
0.23
0.40
MIN NOM MAX
MILLIMETERS
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
MCP4011/2/3/4
DS21978B-page 54 © 2006 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27
.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
© 2006 Microchip Technology Inc. DS21978B-page 55
MCP4011/2/3/4
APPENDIX A: REVISION HISTORY
Revision B (October 2006)
For the 10 kΩ device, the rheostat differential
non-linearity specification at 2.7V was changed
from ±0.5 LSb to ±1 LSb.
Figure 2-9 in Section 2.0 “Typical Performance
Curves” was updated with the correct data.
Added Figure 2-55 for -3 db Bandwidth
information.
Added Figure 2-56 for -3 db Bandwidth test
circuit.
Updated available Development Tools
Added disclaimer to package outline drawings
and updated changed drawings as needed.
Revision A (November 2005)
Original Release of this Document.
MCP4011/2/3/4
DS21978B-page 56 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS21978B-page 57
MCP4011/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP4011: Single Potentiometer with U/D Interface
MCP4011T: Single Potentiometer with U/D Interface
(Tape and Reel) (SOIC, MSOP)
MCP4012: Single Rheostat with U/D interface
MCP4012T: Single Rheostat with U/D interface
(Tape and Reel) (SOT-23-6)
MCP4013: Single Potentiometer to GND with U/D
Interface
MCP4013T: Single Potentiometer to GND with U/D
Interface (Tape and Reel) (SOT-23-6)
MCP4014: Single Rheostat to GND with U/D
Interface
MCP4014T: Single Rheostat to GND with U/D
Interface (Tape and Reel)(SOT-23-5)
Resistance Version: 202 = 2.1 kΩ
502 = 5 kΩ
103 = 10 kΩ
503 = 50 kΩ
Temperature Range: E = -40°C to +125°C
Package: CH = Plastic Small Outline Transistor, 6-lead
MC = Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead
MS = Plastic MSOP, 8-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
OT = Plastic Small Outline Transistor, 5-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP4011-103E/MS: 10 kΩ, 8-LD MSOP
b) MCP4011-103E/SN: 10 kΩ, 8-LD SOIC
c) MCP4011T-103E/MC: T/R, 10 kΩ, 8-LD DFN
d) MCP4011T-103E/MS: T/R, 10 kΩ, 8-LD MSOP
e) MCP4011T-103E/SN: T/R, 10 kΩ, 8-LD SOIC
f) MCP4011-202E/MS: 2.1 kΩ, 8-LD MSOP
g) MCP4011-202E/SN: 2.1 kΩ, 8-LD SOIC
h) MCP4011T-202E/MC: T/R, 2.1 kΩ, 8-LD DFN
i) MCP4011T-202E/MS: T/R, 2.1 kΩ, 8-LD MSOP
j) MCP4011T-202E/SN: T/R, 2.1 kΩ, 8-LD SOIC
k) MCP4011-502E/MS: 5 kΩ, 8-LD MSOP
l) MCP4011-502E/SN: 5 kΩ, 8-LD SOIC
m) MCP4011T-502E/MC: T/R, 5 kΩ, 8-LD DFN
n) MCP4011T-502E/MS: T/R, 5 kΩ, 8-LD MSOP
o) MCP4011T-502E/SN: T/R, 5 kΩ, 8-LD SOIC
p) MCP4011-503E/MS: 50 kΩ, 8-LD MSOP
q) MCP4011-503E/SN: 50 kΩ, 8-LD SOIC
r) MCP4011T-503E/MC: T/R, 50 kΩ, 8-LD DFN
s) MCP4011T-503E/MS: T/R, 50 kΩ, 8-LD MSOP
t) MCP4011T-503E/SN: T/R, 50 kΩ, 8-LD SOIC
a) MCP4012T-202E/CH 2.1 kΩ, 6-LD SOT-23
b) MCP4012T-502E/CH 5 kΩ, 6-LD SOT-23
c) MCP4012T-103E/CH 10 kΩ, 6-LD SOT-23
d) MCP4012T-503E/CH 50 kΩ, 6-LD SOT-23
a) MCP4013T-202E/CH 2.1 kΩ, 6-LD SOT-23
b) MCP4013T-502E/CH 5 kΩ, 6-LD SOT-23
c) MCP4013T-103E/CH 10 kΩ, 6-LD SOT-23
d) MCP4013T-503E/CH 50 kΩ, 6-LD SOT-23
a) MCP4014T-202E/OT 2.1 kΩ, 5-LD SOT-23
b) MCP4014T-502E/OT 5 kΩ, 5-LD SOT-23
c) MCP4014T-103E/OT 10 kΩ, 5-LD SOT-23
d) MCP4014T-503E/OT 50 kΩ, 5-LD SOT-23
XXX
Resistance
Version
MCP4011/2/3/4
DS21978B-page 58 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS21978B-page 59
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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Trademarks
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PICSTART, PRO MATE, PowerSmart, rfPIC, and
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Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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All other trademarks mentioned herein are property of their
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© 2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
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development systems is ISO 9001:2000 certified.
DS21978B-page 60 © 2006 Microchip Technology Inc.
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