A8508GETTR-T - Allegro MicroSystems Europe Ltd.

Description

The A8508 is a multi-output white LED driver for backlighting

LCD panels. It integrates a current-mode boost controller and

eight individual current sinks.

The boost controller architecture allows for significant scaling

of boost voltage to optimize the solution for the required

number of LEDs per string. The FSET/SYNC pin either sets

the required boost switching frequency or synchronizes the

value in the range of 300 to 800 kHz.

The LED sink current value is set by an external ISET resistor

(see figure 1). The eight LED sinks can also be combined to

achieve even higher current per LED string.

The A8508 provides protection against output shorts and

overvoltage, open or shorted LED pins, and overtemperature.

A dual-level, pulse-by-pulse current limit function provides

soft start and protects the external current switch against

high current overloads. As an option, the A8508 can drive an

external P-FET interfaced to the ¯

pin to disconnect the

input supply from the system in the event of short-to-ground

in the boost converter.

The A8508 is available in a 24-pin TSSOP package (suffix LP)

with an exposed thermal pad for enhanced thermal dissipation.

Contact factory for additional options, including: a 24-pin

SOICW (LW) or a a 5 × 5 mm 28-contact QFN (ET) with

exposed thermal pad. All packages are lead (Pb) free, with

100% matte tin leadframe plating.

A8508-DS, Rev. 1

Features and Benefits

• Eight integrated high current sinks for LED strings; can be

tied together for even higher currents

• Fixed frequency current mode control with integrated gate

driver / boost controller; powerful gate driver to drive an

external N-channel MOSFET allows significant scaling

capability on the number of LEDs per string

• Parallel operation capability with one boost controller

(master) and up to three additional slave controllers; can

run up to 32 strings of LEDs while populating only a

single master boost regulator

• Active current sharing between LED strings for 0.7%

accuracy and 0.8% matching

• Wide input voltage range: 9 to 40 V

• Internal bias supply for single-supply operation (typically

VIN = 12 or 24 V)

• Fset / Sync function to either set the boost converter

switching frequency or synchronize at up to 800 kHz

• Protection Features

 Open or shorted LED pin protection

 Open Schottky protection

 Pulse-by-pulse current limit

 Overtemperature protection (OTP)

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

Typical Application

A8508

Packages (Not to scale)

24-pin SOICW

(LW package)

24-pin TSSOP with

Exposed Thermal Pad

(LP package)

28-contact QFN

with Exposed Thermal

Pad (ET package)

VDD

VDR

ISET

FSET/SYNC

RISET RZ

CDD

CDR

RFSET

RVDR

COMP

MODE

LED5

LED7

AGND PGND

PAD

GATEVIN SENNSENP OVP

COUT

ROVP

RSENSE

D1 VOUT

VIN

VDD

CIN

A8508

LED8

LED6

LED4

LED3

LED1

LED2

PWM

FAULT

5.00

10.00

15.00

20.00

25.00

30.00

30 50 70 90 110 130 150

RISET Value versus LED Current

ILED (mA)

RISET (k)

Figure 1. Typical application circuit

showing 8 channels of LEDs; RZ-CZ

optional (component list shown in the

Typical Applications section)

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings*

Characteristic Symbol Notes Rating Unit

LEDx Pin Voltage VLEDx –0.3 to 55 V

OVP Pin Voltage VOVP –0.3 to 60 V

VIN Pin Voltage VIN –0.3 to 40 V

U ¯¯

Pin Voltage VFAULT –0.3 to 40 V

COMP, EN, FSET/SYNC, ISET,

MODE, PWM, SENN, SENP, and VDD

Pin Voltage

– –0.3 to 5.5 V

GATE, VDR Pin Voltage – –0.3 to 8 V

Operating Ambient Temperature TAG temperature range –40 to 105 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

*Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical

Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Selection Guide

Part Number Package Packing1

A8508GETTR-T228-contact QFN with exposed thermal pad Contact factory

A8508GLPTR-T 24-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel

A8508GLWTR-T224-pin SOICW Contact factory

1Contact Allegro™ for additional packing options.

2Contact factory for availability.

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance RJA

Package ET, on 4-layer PCB based on JEDEC standard 32 ºC/W

Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W

Package LW, on 4-layer PCB based on JEDEC standard 44 ºC/W

*Additional thermal information available on the Allegro website

Table of Contents

Specifications 2

Functional Block Diagram 3

Pin-out Diagram and Terminal List 4

Electrical Characteristics Table 5

Functional Description 8

Enabling the IC 8

Powering up: LED pin short-to-GND check 8

Soft start function 9

Frequency selection 10

Synchronization 10

LED current setting and LED dimming 11

PWM dimming 12

Analog dimming 12

Boost switch overcurrent protection 13

Setting the current sense resistor 13

Current sense resistor routing 13

Pulse-by-pulse current limit 14

Secondary boost switch limit 14

Output overvoltage and undervoltage protection 14

LED Open Detect 15

Undervoltage Protection (UVP) 15

LED short detect 16

Input UVLO 16

VDD and VDR 16

Shutdown 17

Fault protection during operation 17

Application Information 19

Paralleling more than one A8508 19

Design Example 21

Typical Applications 24

Package Outline Drawing 27

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Block Diagram

VDD VDR

Regulator

UVLO

Internal

Soft Start

Enable

PWM

Thermal

Shutdown

Open/Short

LED Detect

ISET

PAD

Fault

LED

Driver

1.25 V

Ref

Driver

Circuit

Internal VDD

VREF1

VREF

VREF2

VREF

ISS

AGND

Current

Sense

Fault

OVP/UVP

Sense

Oscillator

GATE

VIN

FSET/SYNC

COMP

MODE

PWM

PGND

ET and LP

Packages Only

AGND

ISET

OVP

LED2

LED1

LED4

LED5

LED6

LED7

LED8

LED3

FAULT

AGND



–

100 k

SENP SENN

100 k

70 k

50 A

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Pin-out Diagrams

Terminal List Table

Name Number Function

ET LP, LW

AGND 13 19 LED ground.

COMP 23 5 Output of the error amplifier and compensation node. Connect a compensation network from this pin to ground.

EN 25 7 Enable for the A8508.

U ¯¯

¯ 312

This pin is used to indicate a fault condition. Connect a pull-up resistor between this pin and the required logic level

voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs.

FSET/SYNC 27 9 Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also

be used to synchronize two or more converters in the system.

GATE 21 3 Gate pin for driving external N-channel FET.

HVGATE 5 n.a. Input disconnect switch: gate driver

ISET 28 10 Connect the RISET resistor between this pin and ground to set the 100% LED current.

LED1 17 23

Connect the cathode of each LED string to these pins.

LED2 16 22

LED3 15 21

LED4 14 20

LED5 10 18

LED6 8 17

LED7 11 16

LED8 12 15

MODE 24 6 This pin is used to determine the mode of operation. MODE high tied to VDD allows parallel operation, and MODE low is

used for single IC operation.

OVP 4 13 This pin is used to sense an Overvoltage (OVP) condition. Connect the ROVP resistor from VOUT to this pin to adjust

the overvoltage protection.

PAD – – For QFN and TSSOP packages, this exposed pad provides enhanced thermal dissipation. This pad must be connected

to the ground plane(s) of the PCB with at least 8 vias, directly in the PAD solder pad.

PGND 18 24 Power ground for the internal gate driver circuit.

PWM 26 8 PWM dimming pin. Used to control the LED intensity by using pulse width modulation. The typical PWM dimming

frequency is in the range of 100 to 1000 Hz.

SENN 19 1 Negative sense line for boost switch current sensing.

SENP 20 2 Positive sense line for boost switch current sensing.

VDD 1 11 Output of internal LDO regulator. Connect a 0.1 F decoupling capacitor between this pin and ground.

VDR 22 4 Output of the gate driver bias voltage regulator. Connect a 0.22 F capacitor in series with a 7.5  resistor between this

pin and ground.

VIN 7 14 Input power to the A8508.

VSENSE 6 n.a. Input disconnect switch: current sense

PGND

LED1

LED2

LED3

LED4

AGND

LED5

LED6

LED7

LED8

VIN

OVP

SENN

SENP

GATE

VDR

COMP

MODE

PWM

FSET/SYNC

ISET

VDD

FAULT

PGND

LED1

LED2

LED3

LED4

AGND

LED5

LED6

LED7

LED8

VIN

OVP

SENN

SENP

GATE

VDR

COMP

MODE

PWM

FSET/SYNC

ISET

VDD

FAULT

PAD

LP Package

ET Package LW Package

PAD

ISET

FSET/SYNC

PWM

MODE

COMP

VDR

LED6

LED5

LED7

LED8

AGND

LED4

GATE

SENP

SENN

PGND

LED1

LED2

LED3

VDD

FAULT

OVP

HVGATE

VSENSE

VIN

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design and

characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Input Voltage Specifications

Operating Input Voltage Range VIN 9 – 40 V

UVLO Start Threshold VUVLO(th) VIN rising – 8.5 V

UVLO Hysteresis VUVLO(hys) VIN falling – 400 – mV

Input Currents

Input Quiescent Current IQEN = VIH ; fSW = 800 kHz, no load 7mA

Input Sleep Supply Current IQSLEEP VIN = 12 V, EN = FSET/SYNC = 0 V 0.5 10.0 A

Input Logic Levels (EN, PWM, MODE, FSET/SYNC)

Input Logic Level-Low VIL 9 V < VIN < 40 V – – 400 mV

Input Logic Level-High VIH 9 V < VIN < 40 V 1.5 – – V

EN and PWM Pins Pull-Down

Resistor Rpulldown EN, PWM= 5 V 100 k

MODE Pin Pull-Down Resistor RMODE MODE=2.5 V 70 k

Error Amplifier

Open Loop Voltage Gain AVOL 47 dB

Transconductance gmICOMP = ±10 A990 A/V

Source Current IEA(SRC) VCOMP = 1.5 V –360 A

Sink Current MODE High IEA(SINK)H VCOMP = 1.5 V, MODE = VIH 80 A

Sink Current MODE Low IEA(SINK)L VCOMP = 1.5 V, MODE = VIL 360 A

COMP Pin Pull-Down Resistor RCOMP ¯

U ¯¯

= 0 1.5 k

Soft Start COMP Level VCOMPSS 200 mV

Overvoltage Protection

Overvoltage Threshold VOVP(th) OVP connected to VOUT 1.11 1.25 1.4 V

OVP Sense Current IOVPH 45 49 53 A

Output Undervoltage Threshold VUVP(LOW) Falling 100 mV

VUVP(HIGH) Rising 120 mV

Boost Switch Gate Driver

Gate Driver Voltage VDRV Measured at GATE pin 7V

Driver Pull-up and Pull-down

Resistance RGATEUD Measured at VGATE =VDRV / 2  4.5  

Driver to Ground Resistance RGATEG EN = 0, VIN = 0  200  k

Sense Positive VSENSEP 85 100 115 mV

Secondary Sense Positive VSENSESEC 165 mV

Continued on the next page…

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Boost Switch Gate Driver (continued)

Soft Start Boost Current Limit

Reference Voltage VSWSS(LIM)

Reference voltage for boost switch current

limit during soft start. 39 mV

Minimum Switch On-Time tSWONTIME 110 ns

Minimum Switch Off-Time tSWOFFTIME 85 ns

Oscillator Frequency

Oscillator Frequency fSW

RFSET = 7.5 k725 800 875 kHz

RFSET = 10 k540 600 660 kHz

RFSET = 20 k300 kHz

FSET/SYNC Pin Voltage VFSET RFSET = 8.25 k1.00 V

Synchronization

Synchronized PWM Frequency fSWSYNC 300 800 kHz

Synchronization Input

Minimum Off-Time tPWSYNCOFF 150 ns

Synchronization Input

Minimum On-Time tPWSYNCON 150 ns

LED Current Sinks

LEDx Accuracy ErrLED ISET = 100 A – 0.7 – %

LEDx Matching LEDx ISET = 100 A – 0.8 2.5 %

LEDx Regulation Voltage VLED VLED1 through VLED8 all equal, ISET = 100 A650 mV

ISET to ILEDx Current Gain AISET ISET = 100 A – 1160 – A/A

ISET Pin Voltage VISET 1.000 V

Allowable ISET Current ISET 34 130 A

LEDx Pin Short Detect VLEDSC

While LED sinks are in regulation, sensed

from LEDx pin to GND 4.6 V

Soft Start LEDx Current Gain ILEDSS

Current through each enabled LEDx pin

during soft start, RISET = 12.4 k44 A/A

PWM High to LED-On Delay tdPWM(on)

Time between PWM enable and LEDx

current reaching 90% of maximum 0.5 1.1 s

PWM Low to LED-Off Delay tdPWM(off)

Time between PWM enable going low and

LEDx current reaching 10% of maximum 500 ns

ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design

and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Continued on the next page…

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design

and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

U ¯¯

Pin Pull-Down Voltage VFAULT

IFAULT = 1 mA (400  internal switch

resistance) 0.4 V

U ¯¯

Pin Leakage Current IFAULTLKG VFAULT = 5 V 1A

Thermal Protection (TSD)

Thermal Shutdown Threshold2TSD Temperature rising 165 ºC

Thermal Shutdown Hysteresis2TSDHYS 20 ºC

1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive

current is defined as going into the node or pin (sinking).

2Ensured by design and characterization, not production tested.

643

644

645

646

647

648

649

650

651

652

653

654

-40-20 0 20406080100

LEDx Regulation Voltage, V

REGx

(mV)

Junction Temperature, T

(°C)

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Enabling the IC

The IC turns on when a logic high signal is applied on the EN

pin, and the input voltage present on the VIN pin is greater than

the 8.5 V necessary to clear the UVLO (VUVLOrise ) threshold.

Before the LEDs are enabled, the A8508 driver goes through a

system check to determine if there are any possible fault condi-

tions that might prevent the system from functioning correctly.

Powering up: LED pin short-to-GND check

After the VIN pin goes above the UVLO threshold, and a high sig-

nal is present on the EN pin, the IC proceeds to check if any LEDx

pins are shorted to GND and/or are not used. Each unused pin

should be connected to GND with a 4.75 k pull-down resistor.

After the voltage threshold on the LEDx pins exceeds 120 mV, a

timer of 1536 clock cycles (2 ms at 800 kHz switching frequency,

see figure 2) is applied during which the A8508 determines the

status of the pins. Any unused pin connected to GND with the

pull-down resistor will be taken out of regulation at this point and

will not contribute to the boost regulation loop (see figure 3). A

typical example is shown in figure 4. When a pin is connected to

GND through a 4.75 k resistor, the voltage on that LEDx pin

during the LED detection period is about 200 mV. This is shown

in figure 2.

If an LEDx pin is shorted to ground such that LEDx pin voltage

is < 100 mV, the A8508 will not proceed with soft start until the

short is removed from the LEDx pin. This prevents the A8508 Figure 4. Channel select setup: (left) channel LED8 not used,

(right) using all channels.

GND

4.75 k

A8508

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

A8508

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

GND

Figure 3. LED detect circuit operation for an LED pin that is not being

used; shows VOUT (ch1, 10 V/div.), VEN (ch2, 5 V/div.), an unused LEDx

with a 4.75 k resistor from this pin to GND, VLEDa (ch3, 500 mV/div.), and

a used LEDx, VLEDb (ch4, 500 mV/div.), t = 2 ms/div.

Figure 2. LED detect circuit operation for two connected LEDs at fSW =

800 kHz; shows VOUT (ch1, 10 V/div.), VEN (ch2, 5 V/div.), an LEDx, VLEDa

(ch3, 500 mV/div.), another LEDx, VLEDb (ch4, 500 mV/div.), t = 2 ms/div.

VLEDa(not used)

VLEDb(used)

VOUT

VEN

Figure 5. LED detect circuit operation: device powers-up after the short

is removed from the LED pin; shows VOUT (ch1, 10 V/div.), VEN (ch2,

5 V/ div.), an LEDx with short, VLEDa (ch3, 500 mV/div.), and an LEDx

without short, VLEDb (ch4, 500 mV/div.), t = 2 ms/div.

LED detection period

Short removed

VEN

VOUT

VLEDa (with temporary short)

VLEDb (no short)

LED detection period

VEN

VLEDa

VLEDb

VOUT

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

from powering-up and putting an uncontrolled amount of current

through the LEDs. After the short is removed the affected LEDx

pin will rise up to the 500 mV level. When the LEDx pin voltage

exceeds the 260 mV threshold, the IC detects connected LEDs

and proceeds with LED detection and soft start. Figure 2 shows

a case when two LED channels are enabled. During the LED

detection period, voltage on both LEDx pins > 260 mV. Figure 5

shows a case with LEDa temporarily shorted to ground and

LEDb in normal operation.

Soft start function

During soft start the LED current gain is reduced to (ILEDSS).

As an example, for a 120 mA output current, the soft-start LED

current would be set to about 4.5 mA (see figure 7). Also dur-

ing soft start the boost switch sense voltage is reduced to the

ISWSS(LIM) level, to limit the initial inrush current generated by

the charging of the output capacitors. The actual current limit

(ILIM) is equal to:

ILIM = VSWSS(LIM) / RSENSE (1)

where VSWSS(LIM) is found in the Electrical Characteristics table,

and RSENSE is the current sense resistor value.

When the converter senses that there is enough voltage on the

LEDx pins, the converter proceeds to increase the LED current

to the preset regulation current and the boost switch current sense

voltage limit is switched to the ISW(LIM) level to allow the A8508

to deliver the necessary output power to the LEDs (figure 8).

Figure 8. Normal start-up behavior; shows VEN (ch1, 2 V/div.), VCOMP

(ch2, 2 V/div.), IIN (ch3, 1 V/div.), and VOUT (ch4, 10 V/div.), t = 500 s/div.

Figure 6. Start-up operation, individual LEDx current = 60 mA, boost

sense resistor = 0.020 ; shows VEN (ch1, 2 V/div.), IIN (ch2, 1 A/div.),

IOUT (ch3, 200 mA/div.), and VOUT (ch4, 20 V/div.), t = 500 s/div.

Figure 7. Start-up operation, individual LEDx current = 120 mA, boost

sense resistor = 0.010 ; shows VEN (ch1, 2 V/div.), IIN (ch2, 2 A/div.),

IOUT (ch3, 1 A/div.), and VOUT (ch4, 20 V/div.), t = 500 s/div.

IIN limited by boost switch

to VSWSS(lim) / RSENSE

VEN

IIN

VOUT

IOUT

IIN limited by boost switch

to VSWSS(LIM) / RSENSE

VEN

IIN

VOUT

IOUT

Boost starts operating in

normal current limit VSW(LIM)

IIN limited by boost switch

to VSWSS(LIM) / RSENSE

VOUT sufficient to begin

normal power-up

VEN

VCOMP

VOUT

IIN

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Frequency selection

The switching frequency on the boost regulator is set by connect-

ing a resistor, RFSET, between the FSET/SYNC pin and ground.

The switching frequency range is 300 to 800 kHz, with example

values of:

RFSET Value

(kΩ)

Swtiching Frequency, fSW

(kHz)

7.5 800

10 600

The relationship of RFSET and fSW is shown in figure 9.

The FSET/SYNC pin has short-to-ground protection. If the

FSET/SYNC pin is held low for more than 4 s typical, the

A8508 will stop switching and disable the LEDx pins (see figures

10 and 11). If the FSET/SYNC pin is released at any time after

7 s, the A8508 will proceed to soft start but will not perform the

LED detection phase.

Synchronization

The A8508 can also be synchronized by using an external clock

connected to the FSET/SYNC pin. The synchronization func-

tion of IC was designed to work with a push-pull type of clock

driver. The amplitude of the clock signal should be between

1.5 and 3.3 V. The synchronization clock should have duty

cycles that meet the minimum on/off times. Figure 12 shows the

timing for a synchronization clock into the A8508 at 800 kHz.

The 150 ns minimum on-time and 150 ns minimum off-time are

Figure 10. Shutdown when the FSET/SYNC pin is shorted to ground;

shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.), IIN (ch3, 2 A/div.),

and IOUT (ch4, 500 mA/div.), t = 200 s/div.

Figure 11. Zoomed-in view of figure 9, showing quick shutdown when

FSET/SYNC shorted to ground, preventing IC running at very high

frequency; shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.),

IIN (ch3, 2 A/div.), and IOUT (ch4, 1 A/div.), t = 10 s/div.

150 ns

T = 1.25 s

950 ns

PWSYNCON

PWSYNCOFF

150 ns

200

300

400

500

600

700

800

900

7 9 11 13 15 17 19 21

FSET Resistor Value, R

FSET

(k)

Switching Frequency, f

(kHz)

Figure 12. SYNC pulse minimum on and off time

requirements, for an 800-kHz clock.

Figure 9. Switching Frequency as determined by RFSET value.

FSET/SYNC shorted to GND

VOUT

VFSET/SYNC

IIN

IOUT

FSET/SYNC shorted to GND

VOUT

VFSET/SYNC

IIN

IOUT

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

indicated by the specifications for tPWSYNCON and tPWSYNCOFF

Thus any pulse with a duty cycle of 19% to 85% at 800 kHz will

synchronize the IC.

It is recommended to also use the RFSET resistor with the

external clock signal. If a synchronization clock is lost during

operation, the IC will revert to the preset switching frequency

that is set by the RFSET resistor. In this configuration the preset

frequency does not have any restrictions other than the normal

operating range of 300 to 800 kHz. During the changeover period

the IC stops switching for an approximately 5 s period to allow

the synchronization detection circuitry to switch over to the exter-

nal preset switching frequency.

Although examples shown in figures 13 and 14 are extreme

cases of clock-to-resistor frequency changes, it is recommended

that actual applications not have such large switching frequency

changes. In most applications the RFSET resistor and clock fre-

quency should be very close to each other in terms of frequency.

Setting the frequencies close together will prevent the system

from experiencing large changes on frequency-dependent signals

and components, such as the inductor ripple current and the com-

pensation resistor and capacitor.

LED current setting and LED dimming

The maximum LED current can be up to 150 mA per channel.

The LED current is set through the RISET resistor connected

between the ISET pin and ground. The ILED current is set accord-

ing to the following formula:

RISET = (1.000 / ILED ) × 1160 (2)

where RISET is in , and ILED is in A. This sets the maximum cur-

rent through the LEDs, referred to as the 100% current. Standard

RISET values are as follows:

Standard Resistor Value

Closest to RISET

(kΩ)

LED current per LED, ILED

(mA)

7.87 150

9.53 120

11.5 100

14.3 80

19.1 60

Figure 13. Synchronization feature with 200 kHz difference between RFSET

and external clock signal. The synchronization frequency is 600 kHz,

and the resistor preset frequency is 800 kHz. Note that there is very little

disturbance in the LED current at the time of changeover; shows

VGATE (ch1, 5 V/div.), VCOMP (ch2, 1 V/div.), IOUT (ch3, 1 A/div.), and

VFSET/SYNC (ch4, 5 V/div.), t = 5 s/div.

Figure 14. Synchronization feature with 500 kHz difference between RFSET

and external clock signal, illustrating the flexibility of the RFSET/SYNC pin;

synchronization frequency is 300 kHz, and the resistor preset frequency

is 800 kHz; shows VGATE (ch1, 5 V/div.), VCOMP (ch2, 1 V/div.),

IOUT (ch3, 1 A/div.), and VFSET/SYNC (ch4, 5 V/div.), t = 10 s/div.

Changeover

period fSW = 600 kHz

from SYNC pulse

fSW = 800 kHz from

RFSET value

VFSET/SYNC

IOUT

VGATE

VCOMP

Changeover

period fSW = 300 Hz

from SYNC pulse

fSW = 800 Hz from

RFSET value

VFSET/SYNC

IOUT

VGATE

VCOMP

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VOUT

IOUT

VCOMP

VPWM

The cited values are for 1% tolerance resistors. If the calculated

value was not present, the next lowest value of 1% resistor was

chosen.

PWM dimming

Applying an external PWM signal on the PWM pin performs

PWM dimming. When the PWM pin is pulled high, the A8508

enables the LEDx pins to sink 100% current. When PWM is

pulled low, the boost converter and LEDx sinks are turned off.

The compensation (COMP) pin is floated, and critical internal

circuits are kept active.

The typical PWM dimming frequencies fall between 100 and

1000 Hz. Figures 15 and 16 show examples of dimming at 50%

and 0.5% duty cycles.

Analog dimming

The A8508 can also be dimmed by using an external DAC or

other voltage source applied either directly to the ground side

of the RISET resistor or through an external resistor to the ISET

pin (see figure 17). The ISET current can be varied in the range

between 34 A and 130 A.

• For a single-resistor configuration (panel A of figure 17), the

ISET current is controlled by the following formula:

ISET =

VISET – VDAC

RISET

(3)

where VISET is the ISET pin voltage and VDAC is the DAC output

voltage.

• For a dual-resistor configuration (panel B of figure 17), the

ISET current is controlled by the following formula:

ISET =–

VISET

RISET

VDAC – VISET

(4)

The advantage of this circuit is that the DAC voltage can be

higher or lower, thus adjusting the LED current to a higher or

lower value of the preset LED current set by the RISET resistor:

 VDAC = 1.00 V: output is strictly controlled by RISET

 VDAC > 1.00 V: LED current is reduced

 VDAC < 1.00 V: LED current is increased

Figure 15. PWM dimming: fSW = 200 Hz, 50% duty cycle, VOUT = 30 V,

VIN = 12 V, and ILED = 120 mA per LED string; shows VOUT (ch1,

10 V/div.), IOUT (ch2, 500 mA/div.), VCOMP (ch3, 2 V/div.), and PWM (ch4,

5 V/div.), t = 2 ms/div.

Figure 16. PWM dimming: fSW = 200 Hz, 0.5% duty cycle, VOUT = 30 V,

VIN = 15 V, ILED = 120 mA per LED string; shows VOUT (ch1, 10 V/div.),

IOUT (ch2, 500 mA/div.), VCOMP (ch3, 2 V/div.), and VPWM (ch4, 5 V/div.),

t = 10 s/div.

Figure 17. Typical application simplified diagram of voltage LED current

control using a DAC to control LED current.

VOUT

IOUT

VCOMP

VPWM

GND

DAC

VDAC

GND

A8508

ISET

GND

DAC

VDAC

GND

A8508

ISET

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Boost switch overcurrent protection

The boost switch is protected with pulse-by-pulse current limiting

set by the external RSENSE resistor. There also is a secondary

current limit that is sensed on the boost switch.

Setting the current sense resistor

The current sense resistor (see figure 18) is set according to the

following formula:

ILIM =

VSENP

RSENSE

(5)

where VSENP is found in the Electrical Characteristics table, and

RSENSE is the current sense resistor value.

The current limit is calculated by the following formula:

ILIM = IIN(max) +

∆IL

2 (6)

where IIN(max) is the maximum input current, and IL is the

inductor current ripple.

Current sense resistor routing

The current sense resistor must be routed as a differential pair to

minimize measurement accuracy errors. For most current sense

resistors the resistance is measured between the inside edges of

the mounting pads of the RSENSE resistor.

Figure 19 shows correct differential current sensing connections

to the A8508. The individual current sense traces are kept short

and side-by-side to get proper signal voltage levels. The trace for

the positive sense pin (SENP) must be routed to the inside edge

of the mounting pad on the high side of RSENSE. The trace for

the negative sense pin (SENN) must be routed to the inside edge

of the mounting pad on the ground side of RSENSE.

It should be noted that when designing the PCB layout, the trace

for the negative sense pin (SENN) is often automatically merged

with the ground flood fill and with the mounting pad on the

ground side of RSENSE (shown in figure 20). However, the trace

must be kept separate and dedicated, and careful attention must

be given when routing the PCB.

Figure 18. Simplified schematic of the current sense resistor connections

to the current sense amplifier.

Figure 19. Correct layout of current sense resistor traces: (A) connect to

inside edges of pads, (B) parallel and dedicated

Figure 20. Incorrect layout of current sense resistor traces: (A) do not

connect to outside edge of pad, (B) do not merge trace into ground

A8508LP

GND

SENP

SENN

RSENSE

A A

A8508LP

GND

SENP

SENN

RSENSE

Current

Sense

–

SENP

A8508

SENN

RSENSE

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VOUT

VCOMP

VGATE

Pulse-by-pulse current limit

Figure 21 illustrates the normal waveform for the current sense

signal. The pulse-by-pulse current limit is designed to limit the

current through the external MOSFET to prevent failure. When

the VSENSEP threshold is reached, the IC stops switching to allow

the inductor current to fall. Operation of pulse-by-pulse current

limiting is shown in figure 22.

A8508

VOUT

OVP

ROVP

Figure 21. Current sense signal (VSENSE) during normal operation,

showing large spikes that are filtered out by a blanking period to avoid

false overcurrent tripping; RSENSE = 10 m; shows inductor current IL (ch1,

1 A/div.), VSENSE (ch2, 20 mV/div.), and gate voltage of the main boost

switch VGATE (ch3), t = 500 ns/div.

Figure 22. Typical pulse-by-pulse current limit; shows IL (ch1, 2 A/div.),

VOUT (ch2, 10 V/div.), VCOMP (ch3, 2 V/div.), and VGATE (ch4),

t = 500 ns/div.

Figure 23. Simplified schematic of the Overvoltage Protection section.

Figure 24. OVP resistor connections; (A) connection should be short,

(B) connection to VOUT can be long, and ROVP should be as close to the

OVP pin as possible.

OVP

1.25 V

50 A

100 mV

–

UVP

A8508

OVP

VOUT

ROVP

Normal spikes

due to switching

VGATE

VSENSE

Secondary boost switch limit

In case there is an inductor short during operation ,the A8508 has

a secondary switch current limit. When this threshold is reached,

the IC immediately shuts down. The level of this current limit is

set above the pulse-by-pulse current limit to protect the switch

from destructive currents when the boost inductor is shorted.

Output overvoltage and undervoltage

protection

The OVP pin on the A8508 controls both the overvoltage (OVP)

and undervoltage (UVP) protection features. The pin circuit is

shown in figure 23. The OVP protection protects the boost con-

verter from excessive voltage levels when the feedback control

loop is broken, usually caused by an open connection from output

voltage to the LEDs. The UVP function provides output voltage-

to-ground short protection when an external disconnect switch is

used. For more detailed information on disconnect switch appli-

cation, see the Undervoltage Protection (UVP) section.

For proper operation of this pin, due to the relatively low voltage

level, special care has to be taken during PCB layout. Figure 24 is

an example of a proper PCB layout.

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LED Open Detect

When any LED string opens, the boost control circuit increases

the output voltage until it reaches the overvoltage protection

level. The OVP event causes any LED string that is below regula-

tion level to be disabled. After disabling the open string, the

output voltage returns to normal operating voltage. An EN low

signal will reset the LED string regulation lock.

Figure 25 shows a typical overvoltage condition when the output

voltage is disconnected from the LED load. Figure 26 shows an

extended view of the same situation. Figure 27 shows an OVP

condition created by a single open LED string.

Undervoltage Protection (UVP)

If the output voltage is shorted to ground the OVP pin will sense

an undervoltage condition (UVP). When UVP is sensed, the IC

sets the Fault ﬂ ag low which, if used to interface to the output-

disconnect switch, will shut off the P-FET device. Figure 28 is a

schematic showing the input disconnect switch implementation.

Figure 25. OVP operation with all LEDx pins open. VOUT rises to the

overvoltage level and stays there until the IC is shut down; shows VOUT

(ch1, 20 V/div.), IOUT (ch2, 1 A/div.), and VCOMP (ch3, 2 V/div.),

t = 2 ms/div.

Figure 26. Extended view of the OVP condition in figure 25; shows VOUT

(ch1, 20 V/div.), IOUT (ch2, 1 A/div.), VCOMP (ch3, 1 V/div.), and switch node

(VSW) (ch4, 20 V/div.), t = 10 ms/div.

Figure 27. OVP condition created by an open LED string; shows VOUT

(ch1, 2 V/div.), pin voltage VLEDx (ch2, 5 V/div.), and IOUT (ch3,

200 mA/div.), t = 2 ms/div.

VCOMP begins to decrease

OVP level

Fault occurrence

VOUT

IOUT

VCOMP

Periodic switch node

bursts occur when all

LEDx pins are open

VOUT

IOUT

VCOMP

VSW

OVP level

LED string opens

OVP limit is reached,

and string is removed

from control loop

Control loop reduces VOUT

to new regulation level

VOUT (30 V)

VLEDx

IOUT

Figure 28. Simplified schematic of an external disconnect switch

implementation.

VDR

VIN

A8508

CIN (optional)

AO4421

2N7002

10 k

1 k1 k

FAULT

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Figure 29. Input disconnect switch shutdown during an output short

condition; shows VOUT (ch1, 20 V/div.), IIN (ch2, 10 A/div.), ¯

U ¯¯

(ch3,

5 V/div.), and PMOS device VGATE (ch4, 5 V/div.), t = 50 s/div.

Figure 30. Typical shorted LED: when voltage exceeds VLEDSC , the LED

is disabled and remains disabled until either the EN pin is toggled or the

power cycled; shows VOUT (ch1, 20 V/div.), VEN (ch2, 5 V/div.), IOUT (ch3,

0.5 A/div.), and VLEDx (ch4, 10 V/div.), t = 10 s/div.

The waveforms in figure 29 show the operation of the disconnect

feature.

LED short detect

All LEDx pins are rated for 55 V, thus allowing LEDx pin-to-

VOUT short protection in case of a connector short. Any LEDx

pin that has a voltage exceeding VLEDSC will be removed from

operation. This is to prevent the IC dissipating too much power

by having a large voltage present on the LEDx pins.

Input UVLO

When VIN rises above the UVLO threshold (VUVLO(th) ), the

A8508 is enabled. It is disabled when VIN falls below VUVLO(th)

– VUVLO(hys) for more than 2 s. This lag is to avoid shutdown

because of momentary glitches in the power supply.

VDD and VDR

The VDD pin provides the regulated bias supply for the internal

circuits. A capacitor with a value in the range 0.1 to 1 F should

be used to decouple the internal analog and digital circuitry.

VOUT

IIN

VGATE(PMOS)

Output short

occurrence

FAULT

VLEDSC is detected

VOUT

VEN

IOUT

VLEDx

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The VDR circuit provides power to the gate driver of the A8508.

For best stability, use a decoupling capacitor in series with a

resistor between the VDR pin and GND. The recommended value

for the decoupling capacitor is 0.22 F. The value of the series

resistor is typically between 5 and 10 . If necessary, a larger

resistor value may be used to limit the rising slope of the gate

signal, in order to reduce EMI.

Shutdown

If the EN pin is pulled low, the IC will shut down immediately.

Fault protection during operation

The A8508 device constantly monitors the state of the system

to determine if any fault conditions occur during normal opera-

tion. The response to a triggered fault condition is summarized in

table 1. The possible fault conditions that the part can detect are:

• Open LED pin

• Shorted inductor with second level switch current protection

• VOUT short-to-ground

• ISET pin short-to-ground

• FSET pin short-to-ground

• Shorted LED

• Open Schottky diode

• Short Schottky diode protection with second level switch cur-

rent protection

• Thermal shutdown (TSD)

• Overvoltage protection (OVP)

Figure 31. Input disconnect switch power-up: (1) VOUT charges via 10 k

resistor, (2) IIN current spike from charging COUT when the PMOS is

enabled; shows VOUT (ch1, 20 V/div.), IIN (ch2, 2 A/div.), ¯

U ¯¯

(ch3,

5 V/div.), and PMOS device VGATE (ch4, 5 V/div.), t = 2 ms/div.

LED detection

period

Soft start and

power-up

VGATE(PMOS)

VOUT

IIN

FAULT

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Table 1. Fault Modes

Fault Name Type Active

Fault

Flag

Set

Description Boost Sink

driver

Primary switch current

protection (pulse-by-

pulse current limit)

Auto-restart Always No This fault condition is triggered by the pulse-by-pulse current limit

when the SENSP pin voltage exceeds VSENSEP

Off for

a single

cycle

Secondary switch

current limit Latched Always Yes

When the current through the boost switch exceeds the secondary

current limit (VSENSESEC) the IC immediately shuts down the LED

drivers and the boost. To re-enable the A8508 the EN pin must be

toggled.

Off Off

LEDx pin short to GND

protection Auto-restart Startup Yes

This fault prevents the IC from starting-up if any of the LEDx pins are

shorted. The IC stops soft start from starting while any of the LEDx

pins are determined to be shorted. After the short is removed, soft

start is allowed to start.

Off Off

LEDx pin open Auto-restart Normal

operation No

When an LEDx pin is open the device will determine which LEDx

pin is open by increasing the output voltage until OVP is reached.

Any LED string below regulation will be turned off. The device then

goes back to normal operation by reducing the output voltage to the

appropriate voltage level.

Off for

open

pins. On

for all

others

LED short protection Auto-restart Always No

This fault occurs when the LED pin voltage exceeds VLEDSC

. When

the LED short protection is detected, the LED string that is above the

threshold will be removed from operation.

Off for

shorted

pins. On

for all

others

FSET pin short

protection Auto-restart Always No

This fault occurs when the FSET pin current goes above 150% of the

maximum current. The boost stops switching, and the IC disables

the LED sinks until the fault is removed. When the fault is removed

the IC tries to restart with soft start.

Off

On in

soft

start

current

ISET pin short

protection Auto-restart Always No

This fault occurs when the ISET pin current goes above 150% of the

maximum current. The boost stops switching and the IC disables the

LED sinks until the fault is removed. When the fault is removed the

IC tries to regulate to the preset LED current.

Off Off

Overvoltage protection Auto-restart Always No

The fault occurs when the OVP pin voltage exceeds the VOVP(th)

threshold. The A8508 immediately stops switching to try to reduce

the output voltage. If the output voltage decreases then the A8508

restarts switching to regulate the output voltage.

Stop

during

OVP

event

Output undervoltage

protection Auto-restart Always Yes This fault occurs when the OVP pin senses less than 100 mV on the

pin. The IC disables the external P-FET switch, if one is used. Off Off

Overtemperature

protection Auto-restart Always Yes The fault occurs when the die temperature exceeds the

overtemperature threshold, typically 165°C. Off Off

VIN UVLO Auto-restart Always No This fault occurs when VIN drops below VUVLO(th)(max), 8.5 V. This

fault resets all latched faults. Off Off

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Application Information

Paralleling more than one A8508

The A8508 can be paralleled together by using a single boost

converter (master) to provide output power for up to a total of

four A8508s (slaves). The MODE pin of each device must be tied

to the VDD pin of the same device for proper mode selection.

In this mode, the ¯

pins and the COMP pins become a bi-

direction signal bus for the system to communicate.

At initial power-up, each IC will release a pull-down resistor

on the COMP pin and start in soft start mode. When 200 mV is

detected on the COMP pin, the master will then switch to normal

mode. Also, for proper operation all of the ¯

pins must be

tied together to prevent the parallel ICs from powering-up into

a shorted LEDx pin situation. While the ¯

pins are pulled

low, the system will not proceed with start-up.

Below is a simple list of necessary connections between the

master and slave(s), to ensure proper parallel operation (refer to

Application C in the Typical Applications section):

• COMP pin

• VOUT node

• ¯

• EN pin

• PWM pin

Each one of these must be connected to the corresponding signal

on the slave devices.

OVP setting for parallel operation

A notable exception to the list is the OVP pin. In this system

each OVP pin must be set with a dedicated resistor. To make sure

that the system will operate properly, the overvoltage protection

on the master IC should be set higher than on the slave IC. The

A8508 checks open LED condition upon hitting the OVP voltage.

If the master OVP voltage is set lower than the slave OVP, the

slave OVP pin will not trip to permit the open LED check. This in

turn will not remove the corresponding LEDx pins from regula-

tion. Therefore, the output voltage will stay at the master OVP

limit and never decrease the output voltage to the lower regula-

tion level.

The required slave OVP resistor value can be calculated using the

following formula:

ROVP(slave) =

VOUT(OVP) – 1.25 V

IOVPH(min)

(7)

where VOUT(OVP) is the required OVP voltage level, and

IOVPH(min) is the current into the OVP pin found in the Electrical

Characteristics table. The minimum value should be used in this

calculation.

The required master OVP voltage level can be calculated using

the following formula:

VOVP(master) =

ROVP(slave) × IOVPH(max) + 1.25

(8)

where VOVP(master) is the minimum OVP voltage level of the

master IC, IOVPH(max) is current into the OVP pin found in the

Electrical Characteristics table. The maximum value should be

used in this calculation.

The required master OVP resistor value can be calculated using

the following formula:

ROVP(master) =

VOVP(master) – 1.25 V

IOVPH(min)

(9)

where VOVP(master) is the minimum required master OVP voltage

level, and IOVPH(min) is the current into the OVP pin found in the

Electrical Characteristics table. The minimum value should be

used in this calculation.

Following the above formulas will guarantee that there is no

overlap in OVP voltage levels in the system. All slave A8508s

in the system can have the same OVP voltage setting. Figure 32

shows a proper master-slave OVP setting, and figure 33 shows

the result of setting the master OVP too low.

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Figure 33. OVP on the master IC is set too low and the IC does not

respond properly to the open LED condition on the slave IC; shows VOUT

(ch1, 10 V/div.), VLEDx (ch2, 2 V/div.), and IOUT (ch3, 200 mA/div.),

t = 100 ms/div.

Figure 32. Proper OVP setting for the master and slave configuration. The

master OVP is set higher than the slave, shows VOUT (ch1, 2 V/div.), pin

voltage VLEDx (ch2, 2 V/div.), and IOUT (ch3, 200 mA/div.), t = 2 ms/div.

LED string opens

OVP limit is reached,

and string is removed

from control loop

Control loop reduces VOUT

to new regulation level

VOUT (30 V)

VLEDx

IOUT

OVP of slave is never

exceeded, so VOUT remains

higher than necessary

System VOUT clamped to

OVP setting of master IC

VOUT

VLEDx

IOUT

LED string opens

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Design Example

This section provides a method for selecting component values

when designing an application using the A8508.

Assumptions: For the purposes of this example, the following are

given as the application requirements:

• VIN: 10 to 16 V

• Quantity of LED channels, #CHANNELS: 8

• Quantity of series LEDs per channel, #SERIESLEDS : 10

• LED current per channel, ILED

: 120 mA

• V

f(120) at 120 mA: 3.2 V (max)

• fSW : 600 kHz

• TA(max): 65°C

• PWM dimming frequency: 200 Hz, 1% duty cycle

Step 1: Connect LEDs to pins LED1 through LED8.

Step 2: Determine the LED current by setting resistor RISET

. To

do so, apply equation 2:

RISET = (1.000 / ILED ) × 1160

= (1.000 V / 0.120 A ) × 1160

= 9.67 k

Choose a 9.53 k resistor.

STEP 3: Determine the OVP resistor. The OVP resistor is con-

nected between the OVP pin and the output voltage of the con-

verter. The first step is to determine the maximum voltage based

on the LED requirements. Then the regulation voltage of 600 mV

should be added, along with 2 V for noise and regulation. Given

the regulation voltage (VLED) of the A8508 is 850 mV, the mini-

mum required voltage can be determined as follows:

VOUT(OVP)

VOUT(OVP)(min)

#SERIESLEDS ×Vf(120) + VLED + 2 V

10 × 3.2 V + 0.650 V + 2 V

34.65 V

(10)

The OVP resistor (ROVP) value can be calculated as:

ROVP =VOUT(OVP)(min) – VOVP(th)(min)

IOVPH(min)

34.65 V – 1.11 V

745 k; use the nearest standard value, 750 k

45 A

(11)

where both IOVP(th)(min) and VOVP(th)(min) are found in the

Electrical Characteristics table. Choose a value of resistor that is

the closest value higher than the calculated ROVP . In this design

example, a value of 750 k is selected.

Below is the actual value of the minimum OVP trip level with the

selected resistor, applying equation 8:

VOVP =

ROVP × IOVPH + 1.25 V

750 k × 49 A + 1.25 V

38.75 V

STEP 4: Determine the inductor. The inductor must be chosen

such that it can handle the necessary input current. In most appli-

cations, due to stringent EMI requirements, the inductor must

operate in continuous conduction mode throughout the whole

input voltage range.

STEP 4a: Determine the maximum duty cycle of the system:

D(max) =

VIN(min) × 

74.5%

1–

VOUT(OVP)

+ Vf(boost)

10 V × 0.9

34.65 V

+ 0.4 V

(12)

A good approximation of efficiency () is 90%. The voltage drop

of the boost diode can be approximated to be about 0.4 V.

STEP 4b: Determine the maximum and minimum input current

to the system. The minimum input current dictates the inductor

value. The maximum current rating dictates the current rating of

the inductor.

To calculate the maximum input current, first determine the

required output current:

IOUT =

#CHANNELS × ILED

8 × 120 mA

0.960 A

(13)

Then substitute into the formula for maximum input current:

IIN(max) =

VIN(min) × 

3.7 A

VOUT

IOUT

34.65 V

× 0.960 A

10 V

× 0.90

(14)

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The minimum input current can be calculated as:

IIN(min) =

VIN(max) × 

2.31 A

VOUT

IOUT

34.65 V

× 0.960 A

16 V

× 0.90

(15)

STEP 4c: Determining the inductor value. To assure that the

inductor operates in continuous conduction mode, the value of

inductor must be set such that 1/2 of the inductor ripple current is

not greater than the average minimum input current.

As a first pass, take Iripple to be 30% of the maximum inductor

current:

IL=

IIN(max) × (Iripple / IIN(max))

3.72 A × 0.30

1.1 A

(16)

Check to make sure that 1/2 of the inductor ripple current is less

than IIN(min):

IL

2.31 A 0.56 A

IIN(min)

The inductor value can be calculated as:



IL × fSW

VIN(min)

10.62 H

D(max)

× 0.745

10 V

1.1 A

× 600 kHz

(17)

A good inductor value to use would be Lused = 10 H.

STEP 4d: Determining the inductor current rating. The inductor

current rating must be greater than the IIN(max) value plus the

ripple current IL , calculated as:

IL(min) IIN(max) +

4.28 A

3.72 A + 0.56 A

ILused

(18)

STEP 4e: Choosing the RSENSE resistor. The sense resistor

value can be calculated as follows:

RSENSE =

0.086 V

4.28 A

VSENSEP

IL(min)

0.02 

(19)

0.018  is a good value to use for the resistor.

STEP 4f: This step is used to verify that there is sufficient slope

compensation for the inductor chosen. The internal slope com-

pensation value is determined by the following formula:

2.81×10–7 × fSW

0.168 V

s

Slope Compensation

where fSW is in Hz. Substituting:

(20)

With RSENSE = 0.02  this translates to:

0.168 / 0.02 = 8.4 A/s

Next invert equation 17 and insert the inductor value used in the

design:



ILused

Lused × fSW

where fSW is in MHz. Substituting:

VIN(min)

1.24 A

D(max)

× 0.745

10 V

10 H × 600 kHz

(21)



ILused× 1 × 10

–6

fSW

2.91 A

s

Inductor Current Slope

× (1 – D(max))

× (1 – 0.745)

1.24 A × 1 × 10

–6

600 kHz

(22)

Note: that the 1×10

–6 is a constant multiplier. This slope should

be smaller than the internal slope compensation.

STEP 5: To determine the resistor values for a switching fre-

quency use figure 9.

STEP 6: Choosing the proper switching diode. The switching

diode must be chosen for three characteristics when it is used in

LED lighting circuitry: reverse voltage rating, current rating, and

reverse current characteristic of the diode.

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The reverse voltage rating should be such that, during any opera-

tion condition, the voltage rating of the device is larger than the

maximum output voltage. In this case, the maximum output volt-

age is VOUT(OVP)

The peak current through the diode is:

Id(peak)

∆ILused

IIN(max) +

0.56 A

3.72 A +

4.28 A

(23)

The other major component in determining the switching diode is

the reverse current characteristic of the diode. This characteristic

is especially important when PWM dimming is implemented.

During PWM off-time the boost converter is not switching. This

results in a slow bleeding-off of the output voltage due to leakage

currents (IR). IR , or reverse current, can be a huge contributor

especially at high temperatures. On the diode that was selected in

this design, the current varies between 1 and 100 A.

STEP 7: Choosing the output capacitors. The output capacitors

must be chosen such that they can provide filtering for both the

boost converter and for the PWM dimming function. The biggest

factor that contributes to the size of the output capacitor is PWM

dimming frequency and the PWM duty cycle. Another major

contributor is leakage current (ILK

). This current is the combina-

tion of the OVP current sense as well as the reverse current of the

switching diode.

In this design the PWM dimming frequency is 200 Hz and the

minimum duty cycle is 1%. Typically the voltage variation on the

output during PWM dimming must be less than 250 mV (VCOUT)

so that no audible hum can be heard:

ILK×

fPWM × VCOUT

300

A

5.94

F

COUT

1 – DPWM(min)

1 – 0.01

200 Hz

× 0.250 V

(24)

A capacitor larger than 5.94 F should be selected due to deg-

radation of capacitance at high voltages on the capacitor. Two

ceramic 4.7 F 50 V capacitors are a good choice to fulfill this

requirement.

The rms current through the capacitor is given by:

ICOUTrms =

1 – D(max)

D(max) + ILused

IOUT

0.960 A

1.67 A

IIN(max)

1 – 0.745

0.745

+1.24 A

3.72 A

(25)

The output capacitor must have a current rating of at least 1.67 A.

The output capacitors selected in this design have a combined

rms current rating of 2 A.

STEP 8: Selection of input capacitor. The input capacitor must be

selected such that it provides a good filtering of the input voltage

waveform. A good rule of thumb is to set the input voltage ripple

(VIN) to be 1% of the minimum input voltage. The minimum

input capacitor requirements are as follows:

CIN =

fSW

1.24 A

ILused

2.65 F

VIN

600 kHz 0.1 V

(26)

The rms current through the capacitor is given by:

IINrms =

(1 – D(max))

IOUT × ILused

0.363 A

IIN(max)

(1 – 0.765)

0.960 A × 1.24 A

3.72 A

(27)

A good ceramic input capacitor with ratings of 50 V, 4.7 F will

suffice for this application.

Corresponding capacitors include:

Vendor Value Part number

Murata 4.7 F 50 V GRM32ER71H475KA88L

Murata 2.2 F 50 V GRM31CR71H225KA88L

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Typical Applications

Designator Description Part Number Manufacturer

CDD 0.1 F / 10 V

GRM2195C1H104JA01D Murata

CDR 0.22 F / 10 V GRM188R61A224KA01D Murata

CIN 4.7 F / 50 V

GRM32ER71H475KA88L Murata

COUT 10 F / 50 V

GRM32ER71H475KA88L Murata

CP 1 F / 16V GRM188R61A474K Murata

CZ DNP

D1 60 V / 5 A Schottky CMSH5-60-AMI Central Semi

L1 10 H / 5 A 74477110 Wurth Electronics

Q1 NMOS FQD13N06LTM Faichild

R1 100 k DigiKey

RFSET 8.45 k 1%

RISET 12.4 k 1%

ROVP 732 k 1%

RSENSE 0.015 

RZ DNP

U1 A8508 A8508 Allegro

The following is the component list for the typical application circuit shown in figure 1.

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VDD

VDR

RISET

CDD

CDR

RFSET

MODE

LED5

LED7

AGND PGND

PAD

GATEVIN SENNSENP OVP

COUT ROVP

RSENSE

D1 VOUT

VIN

CIN

10 k

A8508

LED8

LED6

LED4

LED3

LED1

LED2

PWM

FAULT

ISET

FSET/SYNC

COMP

RVDR

VDD

VDR

RISET

CDD

CDR

RFSET

MODE

LED5

LED7

AGND PGND

PAD

GATEVIN SENNSENP OVP

COUT ROVP

RSENSE

10 k

1 k

VOUT

VIN

VDR

A8508

LED8

LED6

LED4

LED3

LED1

LED2

PWM

CIN

(Optional)

FAULT

1 k

ISET

FSET/SYNC

COMP

RVDR

Application A. Typical schematic for boost application with disconnect switch application

Application B. Typical application showing SEPIC configuration

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VDD

VDR

RISET

CDD

CDR

CP1

RFSET

MODE LED5

LED7

AGND PGND

PAD

GATEVIN SENNSENP OVP

COUT

ROVP

RSENSE

VOUT

VIN

CIN

A8508

(master)

A8508

(one slave)

LED8

LED6

LED4

LED3

LED1

LED2

PWM

FAULT

VDD

VDR

RISET

CDD

CDR

RFSET

MODE LED5

LED7

AGND PGND

PAD

GATEVIN SENNSENP OVP

ROVP

VOUTVIN

LED8

LED6

LED4

LED3

LED1

LED2

PWM

RGATE

50 k

FAULT

ISET

FSET/SYNC

COMP

ISET

FSET/SYNC

COMP

CP2

RVDR

Application C. Parallel operation of two A8508s; overvoltage protection on master must be

set higher than the OVP on the slave

VDD

VDR

RISET

CDD

CDR

RFSET

MODE

LED5

LED7

AGND PGND

PAD

GATEHGATEVIN VSEN SENNSENP OVP

COUT ROVP

RSENSE

VOUT

VIN

A8508

LED8

LED6

LED4

LED3

LED1

LED2

PWM

RADJ

FAULT

RSC

ISET

FSET/SYNC

COMP

(Optional)

CIN

RVDR

Application D. Input disconnect switch configuration for fault protection. Option available

only in QFN package. Contact factory for details.

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LP, 24-Pin TSSOP

with Exposed Thermal Pad

Contact factory for ET and LW packages.

1.20 MAX

0.15

0.00

0.30

0.19

0.20

0.09

8º

0º

0.60 ±0.15

1.00 REF

SEATING

PLANE

C0.10

24X

0.65 BSC

0.25 BSC

7.80±0.10

4.40±0.10 6.40±0.20

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

For Reference Only; not for tooling use (reference MO-153 ADT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Exposed thermal pad (bottom surface); dimensions may vary with device

4.32 NOM

3 NOM

0.65

6.103.00

4.32

1.65

0.45

Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

Package Outline Drawing

W ide Input Voltage Range, High Ef ficiency

8-Channel Fault Tolerant LED Driver

A8508

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Revision History

Revision Current

Revision Date Description of Revision

Rev. 1 July 9, 2012 Update typical component recommendations

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permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its

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